1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
234 /* Number of bytes to broadcast. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
268 unsupported_with_intel_mnemonic
,
271 invalid_vsib_address
,
272 invalid_vector_register_set
,
273 unsupported_vector_index_register
,
274 unsupported_broadcast
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands
;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types
[MAX_OPERANDS
];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op
[MAX_OPERANDS
];
309 /* Flags for operands. */
310 unsigned int flags
[MAX_OPERANDS
];
311 #define Operand_PCrel 1
312 #define Operand_Mem 2
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* Copied first memory operand string, for re-checking. */
330 /* PREFIX holds all the given prefix opcodes (usually null).
331 PREFIXES is the number of prefix opcodes. */
332 unsigned int prefixes
;
333 unsigned char prefix
[MAX_PREFIXES
];
335 /* RM and SIB are the modrm byte and the sib byte where the
336 addressing modes of this insn are encoded. */
343 /* Masking attributes. */
344 struct Mask_Operation
*mask
;
346 /* Rounding control and SAE attributes. */
347 struct RC_Operation
*rounding
;
349 /* Broadcasting attributes. */
350 struct Broadcast_Operation
*broadcast
;
352 /* Compressed disp8*N attribute. */
353 unsigned int memshift
;
355 /* Prefer load or store in encoding. */
358 dir_encoding_default
= 0,
363 /* Prefer 8bit or 32bit displacement in encoding. */
366 disp_encoding_default
= 0,
371 /* Prefer the REX byte in encoding. */
372 bfd_boolean rex_encoding
;
374 /* Disable instruction size optimization. */
375 bfd_boolean no_optimize
;
377 /* How to encode vector instructions. */
380 vex_encoding_default
= 0,
387 const char *rep_prefix
;
390 const char *hle_prefix
;
392 /* Have BND prefix. */
393 const char *bnd_prefix
;
395 /* Have NOTRACK prefix. */
396 const char *notrack_prefix
;
399 enum i386_error error
;
402 typedef struct _i386_insn i386_insn
;
404 /* Link RC type with corresponding string, that'll be looked for in
413 static const struct RC_name RC_NamesTable
[] =
415 { rne
, STRING_COMMA_LEN ("rn-sae") },
416 { rd
, STRING_COMMA_LEN ("rd-sae") },
417 { ru
, STRING_COMMA_LEN ("ru-sae") },
418 { rz
, STRING_COMMA_LEN ("rz-sae") },
419 { saeonly
, STRING_COMMA_LEN ("sae") },
422 /* List of chars besides those in app.c:symbol_chars that can start an
423 operand. Used to prevent the scrubber eating vital white-space. */
424 const char extra_symbol_chars
[] = "*%-([{}"
433 #if (defined (TE_I386AIX) \
434 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
435 && !defined (TE_GNU) \
436 && !defined (TE_LINUX) \
437 && !defined (TE_NACL) \
438 && !defined (TE_FreeBSD) \
439 && !defined (TE_DragonFly) \
440 && !defined (TE_NetBSD)))
441 /* This array holds the chars that always start a comment. If the
442 pre-processor is disabled, these aren't very useful. The option
443 --divide will remove '/' from this list. */
444 const char *i386_comment_chars
= "#/";
445 #define SVR4_COMMENT_CHARS 1
446 #define PREFIX_SEPARATOR '\\'
449 const char *i386_comment_chars
= "#";
450 #define PREFIX_SEPARATOR '/'
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output.
456 Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output.
459 Also note that comments started like this one will always work if
460 '/' isn't otherwise defined. */
461 const char line_comment_chars
[] = "#/";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant from exp in floating point
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant
472 const char FLT_CHARS
[] = "fFdDxX";
474 /* Tables for lexical analysis. */
475 static char mnemonic_chars
[256];
476 static char register_chars
[256];
477 static char operand_chars
[256];
478 static char identifier_chars
[256];
479 static char digit_chars
[256];
481 /* Lexical macros. */
482 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
483 #define is_operand_char(x) (operand_chars[(unsigned char) x])
484 #define is_register_char(x) (register_chars[(unsigned char) x])
485 #define is_space_char(x) ((x) == ' ')
486 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
487 #define is_digit_char(x) (digit_chars[(unsigned char) x])
489 /* All non-digit non-letter characters that may occur in an operand. */
490 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
492 /* md_assemble() always leaves the strings it's passed unaltered. To
493 effect this we maintain a stack of saved characters that we've smashed
494 with '\0's (indicating end of strings for various sub-fields of the
495 assembler instruction). */
496 static char save_stack
[32];
497 static char *save_stack_p
;
498 #define END_STRING_AND_SAVE(s) \
499 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
500 #define RESTORE_END_STRING(s) \
501 do { *(s) = *--save_stack_p; } while (0)
503 /* The instruction we're assembling. */
506 /* Possible templates for current insn. */
507 static const templates
*current_templates
;
509 /* Per instruction expressionS buffers: max displacements & immediates. */
510 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
511 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
513 /* Current operand we are working on. */
514 static int this_operand
= -1;
516 /* We support four different modes. FLAG_CODE variable is used to distinguish
524 static enum flag_code flag_code
;
525 static unsigned int object_64bit
;
526 static unsigned int disallow_64bit_reloc
;
527 static int use_rela_relocations
= 0;
529 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
530 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
531 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
533 /* The ELF ABI to use. */
541 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
544 #if defined (TE_PE) || defined (TE_PEP)
545 /* Use big object file format. */
546 static int use_big_obj
= 0;
549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
550 /* 1 if generating code for a shared library. */
551 static int shared
= 0;
554 /* 1 for intel syntax,
556 static int intel_syntax
= 0;
558 /* 1 for Intel64 ISA,
562 /* 1 for intel mnemonic,
563 0 if att mnemonic. */
564 static int intel_mnemonic
= !SYSV386_COMPAT
;
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg
= 0;
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg
= 0;
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
575 static int add_bnd_prefix
= 0;
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg
= 0;
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix
= 0;
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence
= 0;
588 /* 1 if the assembler should generate relax relocations. */
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
593 static enum check_kind
599 sse_check
, operand_check
= check_warning
;
602 1. Clear the REX_W bit with register operand if possible.
603 2. Above plus use 128bit vector instruction to clear the full vector
606 static int optimize
= 0;
609 1. Clear the REX_W bit with register operand if possible.
610 2. Above plus use 128bit vector instruction to clear the full vector
612 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
615 static int optimize_for_space
= 0;
617 /* Register prefix used for error message. */
618 static const char *register_prefix
= "%";
620 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
621 leave, push, and pop instructions so that gcc has the same stack
622 frame as in 32 bit mode. */
623 static char stackop_size
= '\0';
625 /* Non-zero to optimize code alignment. */
626 int optimize_align_code
= 1;
628 /* Non-zero to quieten some warnings. */
629 static int quiet_warnings
= 0;
632 static const char *cpu_arch_name
= NULL
;
633 static char *cpu_sub_arch_name
= NULL
;
635 /* CPU feature flags. */
636 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
638 /* If we have selected a cpu we are generating instructions for. */
639 static int cpu_arch_tune_set
= 0;
641 /* Cpu we are generating instructions for. */
642 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
644 /* CPU feature flags of cpu we are generating instructions for. */
645 static i386_cpu_flags cpu_arch_tune_flags
;
647 /* CPU instruction set architecture used. */
648 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
650 /* CPU feature flags of instruction set architecture used. */
651 i386_cpu_flags cpu_arch_isa_flags
;
653 /* If set, conditional jumps are not automatically promoted to handle
654 larger than a byte offset. */
655 static unsigned int no_cond_jump_promotion
= 0;
657 /* Encode SSE instructions with VEX prefix. */
658 static unsigned int sse2avx
;
660 /* Encode scalar AVX instructions with specific vector length. */
667 /* Encode scalar EVEX LIG instructions with specific vector length. */
675 /* Encode EVEX WIG instructions with specific evex.w. */
682 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
683 static enum rc_type evexrcig
= rne
;
685 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
686 static symbolS
*GOT_symbol
;
688 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
689 unsigned int x86_dwarf2_return_column
;
691 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
692 int x86_cie_data_alignment
;
694 /* Interface to relax_segment.
695 There are 3 major relax states for 386 jump insns because the
696 different types of jumps add different sizes to frags when we're
697 figuring out what sort of jump to choose to reach a given label. */
700 #define UNCOND_JUMP 0
702 #define COND_JUMP86 2
707 #define SMALL16 (SMALL | CODE16)
709 #define BIG16 (BIG | CODE16)
713 #define INLINE __inline__
719 #define ENCODE_RELAX_STATE(type, size) \
720 ((relax_substateT) (((type) << 2) | (size)))
721 #define TYPE_FROM_RELAX_STATE(s) \
723 #define DISP_SIZE_FROM_RELAX_STATE(s) \
724 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
726 /* This table is used by relax_frag to promote short jumps to long
727 ones where necessary. SMALL (short) jumps may be promoted to BIG
728 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
729 don't allow a short jump in a 32 bit code segment to be promoted to
730 a 16 bit offset jump because it's slower (requires data size
731 prefix), and doesn't work, unless the destination is in the bottom
732 64k of the code segment (The top 16 bits of eip are zeroed). */
734 const relax_typeS md_relax_table
[] =
737 1) most positive reach of this state,
738 2) most negative reach of this state,
739 3) how many bytes this mode will have in the variable part of the frag
740 4) which index into the table to try if we can't fit into this one. */
742 /* UNCOND_JUMP states. */
743 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
744 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
745 /* dword jmp adds 4 bytes to frag:
746 0 extra opcode bytes, 4 displacement bytes. */
748 /* word jmp adds 2 byte2 to frag:
749 0 extra opcode bytes, 2 displacement bytes. */
752 /* COND_JUMP states. */
753 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
754 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
755 /* dword conditionals adds 5 bytes to frag:
756 1 extra opcode byte, 4 displacement bytes. */
758 /* word conditionals add 3 bytes to frag:
759 1 extra opcode byte, 2 displacement bytes. */
762 /* COND_JUMP86 states. */
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
764 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
765 /* dword conditionals adds 5 bytes to frag:
766 1 extra opcode byte, 4 displacement bytes. */
768 /* word conditionals add 4 bytes to frag:
769 1 displacement byte and a 3 byte long branch insn. */
773 static const arch_entry cpu_arch
[] =
775 /* Do not replace the first two entries - i386_target_format()
776 relies on them being there in this order. */
777 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
778 CPU_GENERIC32_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
780 CPU_GENERIC64_FLAGS
, 0 },
781 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
783 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
785 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
787 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
789 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
791 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
793 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
795 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
797 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
798 CPU_PENTIUMPRO_FLAGS
, 0 },
799 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
801 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
803 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
805 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
807 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
808 CPU_NOCONA_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
811 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
813 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
814 CPU_CORE2_FLAGS
, 1 },
815 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
816 CPU_CORE2_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
818 CPU_COREI7_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
821 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
823 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
824 CPU_IAMCU_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
827 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
829 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
830 CPU_ATHLON_FLAGS
, 0 },
831 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
833 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
835 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
837 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
838 CPU_AMDFAM10_FLAGS
, 0 },
839 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
840 CPU_BDVER1_FLAGS
, 0 },
841 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
842 CPU_BDVER2_FLAGS
, 0 },
843 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
844 CPU_BDVER3_FLAGS
, 0 },
845 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
846 CPU_BDVER4_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
848 CPU_ZNVER1_FLAGS
, 0 },
849 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
850 CPU_ZNVER2_FLAGS
, 0 },
851 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
852 CPU_BTVER1_FLAGS
, 0 },
853 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
854 CPU_BTVER2_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
857 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
859 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
861 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
863 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
865 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
869 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
873 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
875 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
876 CPU_SSSE3_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
878 CPU_SSE4_1_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
880 CPU_SSE4_2_FLAGS
, 0 },
881 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
882 CPU_SSE4_2_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
885 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
887 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
888 CPU_AVX512F_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
890 CPU_AVX512CD_FLAGS
, 0 },
891 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
892 CPU_AVX512ER_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
894 CPU_AVX512PF_FLAGS
, 0 },
895 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
896 CPU_AVX512DQ_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
898 CPU_AVX512BW_FLAGS
, 0 },
899 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
900 CPU_AVX512VL_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
904 CPU_VMFUNC_FLAGS
, 0 },
905 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
908 CPU_XSAVE_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
910 CPU_XSAVEOPT_FLAGS
, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
912 CPU_XSAVEC_FLAGS
, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
914 CPU_XSAVES_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
918 CPU_PCLMUL_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
920 CPU_PCLMUL_FLAGS
, 1 },
921 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
922 CPU_FSGSBASE_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
924 CPU_RDRND_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
929 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
935 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
938 CPU_MOVBE_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
944 CPU_LZCNT_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
950 CPU_INVPCID_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
952 CPU_CLFLUSH_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
956 CPU_SYSCALL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
958 CPU_RDTSCP_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
960 CPU_3DNOW_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
962 CPU_3DNOWA_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
964 CPU_PADLOCK_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
970 CPU_SSE4A_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
977 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
980 CPU_RDSEED_FLAGS
, 0 },
981 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
982 CPU_PRFCHW_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
989 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSHOPT_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
992 CPU_PREFETCHWT1_FLAGS
, 0 },
993 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
998 CPU_AVX512IFMA_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1000 CPU_AVX512VBMI_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1002 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1004 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1006 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1008 CPU_AVX512_VBMI2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1010 CPU_AVX512_VNNI_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1012 CPU_AVX512_BITALG_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1014 CPU_CLZERO_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1016 CPU_MWAITX_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1018 CPU_OSPKE_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1020 CPU_RDPID_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1022 CPU_PTWRITE_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1026 CPU_SHSTK_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1028 CPU_GFNI_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1030 CPU_VAES_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1032 CPU_VPCLMULQDQ_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1034 CPU_WBNOINVD_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1036 CPU_PCONFIG_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1038 CPU_WAITPKG_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1040 CPU_CLDEMOTE_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1042 CPU_MOVDIRI_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1044 CPU_MOVDIR64B_FLAGS
, 0 },
1047 static const noarch_entry cpu_noarch
[] =
1049 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1050 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1051 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1052 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1053 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1054 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1055 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1056 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1057 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1058 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1059 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1060 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1061 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1062 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1071 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1072 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1073 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1074 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1075 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1076 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1077 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1078 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1079 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1080 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1081 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1082 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1083 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1087 /* Like s_lcomm_internal in gas/read.c but the alignment string
1088 is allowed to be optional. */
1091 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1098 && *input_line_pointer
== ',')
1100 align
= parse_align (needs_align
- 1);
1102 if (align
== (addressT
) -1)
1117 bss_alloc (symbolP
, size
, align
);
1122 pe_lcomm (int needs_align
)
1124 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1128 const pseudo_typeS md_pseudo_table
[] =
1130 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1131 {"align", s_align_bytes
, 0},
1133 {"align", s_align_ptwo
, 0},
1135 {"arch", set_cpu_arch
, 0},
1139 {"lcomm", pe_lcomm
, 1},
1141 {"ffloat", float_cons
, 'f'},
1142 {"dfloat", float_cons
, 'd'},
1143 {"tfloat", float_cons
, 'x'},
1145 {"slong", signed_cons
, 4},
1146 {"noopt", s_ignore
, 0},
1147 {"optim", s_ignore
, 0},
1148 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1149 {"code16", set_code_flag
, CODE_16BIT
},
1150 {"code32", set_code_flag
, CODE_32BIT
},
1152 {"code64", set_code_flag
, CODE_64BIT
},
1154 {"intel_syntax", set_intel_syntax
, 1},
1155 {"att_syntax", set_intel_syntax
, 0},
1156 {"intel_mnemonic", set_intel_mnemonic
, 1},
1157 {"att_mnemonic", set_intel_mnemonic
, 0},
1158 {"allow_index_reg", set_allow_index_reg
, 1},
1159 {"disallow_index_reg", set_allow_index_reg
, 0},
1160 {"sse_check", set_check
, 0},
1161 {"operand_check", set_check
, 1},
1162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1163 {"largecomm", handle_large_common
, 0},
1165 {"file", dwarf2_directive_file
, 0},
1166 {"loc", dwarf2_directive_loc
, 0},
1167 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1170 {"secrel32", pe_directive_secrel
, 0},
1175 /* For interface with expression (). */
1176 extern char *input_line_pointer
;
1178 /* Hash table for instruction mnemonic lookup. */
1179 static struct hash_control
*op_hash
;
1181 /* Hash table for register lookup. */
1182 static struct hash_control
*reg_hash
;
1184 /* Various efficient no-op patterns for aligning code labels.
1185 Note: Don't try to assemble the instructions in the comments.
1186 0L and 0w are not legal. */
1187 static const unsigned char f32_1
[] =
1189 static const unsigned char f32_2
[] =
1190 {0x66,0x90}; /* xchg %ax,%ax */
1191 static const unsigned char f32_3
[] =
1192 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1193 static const unsigned char f32_4
[] =
1194 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1195 static const unsigned char f32_6
[] =
1196 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1197 static const unsigned char f32_7
[] =
1198 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1199 static const unsigned char f16_3
[] =
1200 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1201 static const unsigned char f16_4
[] =
1202 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1203 static const unsigned char jump_disp8
[] =
1204 {0xeb}; /* jmp disp8 */
1205 static const unsigned char jump32_disp32
[] =
1206 {0xe9}; /* jmp disp32 */
1207 static const unsigned char jump16_disp32
[] =
1208 {0x66,0xe9}; /* jmp disp32 */
1209 /* 32-bit NOPs patterns. */
1210 static const unsigned char *const f32_patt
[] = {
1211 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1213 /* 16-bit NOPs patterns. */
1214 static const unsigned char *const f16_patt
[] = {
1215 f32_1
, f32_2
, f16_3
, f16_4
1217 /* nopl (%[re]ax) */
1218 static const unsigned char alt_3
[] =
1220 /* nopl 0(%[re]ax) */
1221 static const unsigned char alt_4
[] =
1222 {0x0f,0x1f,0x40,0x00};
1223 /* nopl 0(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_5
[] =
1225 {0x0f,0x1f,0x44,0x00,0x00};
1226 /* nopw 0(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_6
[] =
1228 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1229 /* nopl 0L(%[re]ax) */
1230 static const unsigned char alt_7
[] =
1231 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1232 /* nopl 0L(%[re]ax,%[re]ax,1) */
1233 static const unsigned char alt_8
[] =
1234 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* nopw 0L(%[re]ax,%[re]ax,1) */
1236 static const unsigned char alt_9
[] =
1237 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1238 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1239 static const unsigned char alt_10
[] =
1240 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1241 /* data16 nopw %cs:0L(%eax,%eax,1) */
1242 static const unsigned char alt_11
[] =
1243 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1244 /* 32-bit and 64-bit NOPs patterns. */
1245 static const unsigned char *const alt_patt
[] = {
1246 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1247 alt_9
, alt_10
, alt_11
1250 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1251 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1254 i386_output_nops (char *where
, const unsigned char *const *patt
,
1255 int count
, int max_single_nop_size
)
1258 /* Place the longer NOP first. */
1261 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1263 /* Use the smaller one if the requsted one isn't available. */
1266 max_single_nop_size
--;
1267 nops
= patt
[max_single_nop_size
- 1];
1270 last
= count
% max_single_nop_size
;
1273 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1274 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1278 nops
= patt
[last
- 1];
1281 /* Use the smaller one plus one-byte NOP if the needed one
1284 nops
= patt
[last
- 1];
1285 memcpy (where
+ offset
, nops
, last
);
1286 where
[offset
+ last
] = *patt
[0];
1289 memcpy (where
+ offset
, nops
, last
);
1294 fits_in_imm7 (offsetT num
)
1296 return (num
& 0x7f) == num
;
1300 fits_in_imm31 (offsetT num
)
1302 return (num
& 0x7fffffff) == num
;
1305 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1306 single NOP instruction LIMIT. */
1309 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1311 const unsigned char *const *patt
= NULL
;
1312 int max_single_nop_size
;
1313 /* Maximum number of NOPs before switching to jump over NOPs. */
1314 int max_number_of_nops
;
1316 switch (fragP
->fr_type
)
1325 /* We need to decide which NOP sequence to use for 32bit and
1326 64bit. When -mtune= is used:
1328 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1329 PROCESSOR_GENERIC32, f32_patt will be used.
1330 2. For the rest, alt_patt will be used.
1332 When -mtune= isn't used, alt_patt will be used if
1333 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1336 When -march= or .arch is used, we can't use anything beyond
1337 cpu_arch_isa_flags. */
1339 if (flag_code
== CODE_16BIT
)
1342 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1343 /* Limit number of NOPs to 2 in 16-bit mode. */
1344 max_number_of_nops
= 2;
1348 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1350 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1351 switch (cpu_arch_tune
)
1353 case PROCESSOR_UNKNOWN
:
1354 /* We use cpu_arch_isa_flags to check if we SHOULD
1355 optimize with nops. */
1356 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1361 case PROCESSOR_PENTIUM4
:
1362 case PROCESSOR_NOCONA
:
1363 case PROCESSOR_CORE
:
1364 case PROCESSOR_CORE2
:
1365 case PROCESSOR_COREI7
:
1366 case PROCESSOR_L1OM
:
1367 case PROCESSOR_K1OM
:
1368 case PROCESSOR_GENERIC64
:
1370 case PROCESSOR_ATHLON
:
1372 case PROCESSOR_AMDFAM10
:
1374 case PROCESSOR_ZNVER
:
1378 case PROCESSOR_I386
:
1379 case PROCESSOR_I486
:
1380 case PROCESSOR_PENTIUM
:
1381 case PROCESSOR_PENTIUMPRO
:
1382 case PROCESSOR_IAMCU
:
1383 case PROCESSOR_GENERIC32
:
1390 switch (fragP
->tc_frag_data
.tune
)
1392 case PROCESSOR_UNKNOWN
:
1393 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1394 PROCESSOR_UNKNOWN. */
1398 case PROCESSOR_I386
:
1399 case PROCESSOR_I486
:
1400 case PROCESSOR_PENTIUM
:
1401 case PROCESSOR_IAMCU
:
1403 case PROCESSOR_ATHLON
:
1405 case PROCESSOR_AMDFAM10
:
1407 case PROCESSOR_ZNVER
:
1409 case PROCESSOR_GENERIC32
:
1410 /* We use cpu_arch_isa_flags to check if we CAN optimize
1412 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1417 case PROCESSOR_PENTIUMPRO
:
1418 case PROCESSOR_PENTIUM4
:
1419 case PROCESSOR_NOCONA
:
1420 case PROCESSOR_CORE
:
1421 case PROCESSOR_CORE2
:
1422 case PROCESSOR_COREI7
:
1423 case PROCESSOR_L1OM
:
1424 case PROCESSOR_K1OM
:
1425 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1430 case PROCESSOR_GENERIC64
:
1436 if (patt
== f32_patt
)
1438 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1439 /* Limit number of NOPs to 2 for older processors. */
1440 max_number_of_nops
= 2;
1444 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1445 /* Limit number of NOPs to 7 for newer processors. */
1446 max_number_of_nops
= 7;
1451 limit
= max_single_nop_size
;
1453 if (fragP
->fr_type
== rs_fill_nop
)
1455 /* Output NOPs for .nop directive. */
1456 if (limit
> max_single_nop_size
)
1458 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1459 _("invalid single nop size: %d "
1460 "(expect within [0, %d])"),
1461 limit
, max_single_nop_size
);
1466 fragP
->fr_var
= count
;
1468 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1470 /* Generate jump over NOPs. */
1471 offsetT disp
= count
- 2;
1472 if (fits_in_imm7 (disp
))
1474 /* Use "jmp disp8" if possible. */
1476 where
[0] = jump_disp8
[0];
1482 unsigned int size_of_jump
;
1484 if (flag_code
== CODE_16BIT
)
1486 where
[0] = jump16_disp32
[0];
1487 where
[1] = jump16_disp32
[1];
1492 where
[0] = jump32_disp32
[0];
1496 count
-= size_of_jump
+ 4;
1497 if (!fits_in_imm31 (count
))
1499 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1500 _("jump over nop padding out of range"));
1504 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1505 where
+= size_of_jump
+ 4;
1509 /* Generate multiple NOPs. */
1510 i386_output_nops (where
, patt
, count
, limit
);
1514 operand_type_all_zero (const union i386_operand_type
*x
)
1516 switch (ARRAY_SIZE(x
->array
))
1527 return !x
->array
[0];
1534 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1536 switch (ARRAY_SIZE(x
->array
))
1554 operand_type_equal (const union i386_operand_type
*x
,
1555 const union i386_operand_type
*y
)
1557 switch (ARRAY_SIZE(x
->array
))
1560 if (x
->array
[2] != y
->array
[2])
1564 if (x
->array
[1] != y
->array
[1])
1568 return x
->array
[0] == y
->array
[0];
1576 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1578 switch (ARRAY_SIZE(x
->array
))
1593 return !x
->array
[0];
1600 cpu_flags_equal (const union i386_cpu_flags
*x
,
1601 const union i386_cpu_flags
*y
)
1603 switch (ARRAY_SIZE(x
->array
))
1606 if (x
->array
[3] != y
->array
[3])
1610 if (x
->array
[2] != y
->array
[2])
1614 if (x
->array
[1] != y
->array
[1])
1618 return x
->array
[0] == y
->array
[0];
1626 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1628 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1629 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1632 static INLINE i386_cpu_flags
1633 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1635 switch (ARRAY_SIZE (x
.array
))
1638 x
.array
[3] &= y
.array
[3];
1641 x
.array
[2] &= y
.array
[2];
1644 x
.array
[1] &= y
.array
[1];
1647 x
.array
[0] &= y
.array
[0];
1655 static INLINE i386_cpu_flags
1656 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1658 switch (ARRAY_SIZE (x
.array
))
1661 x
.array
[3] |= y
.array
[3];
1664 x
.array
[2] |= y
.array
[2];
1667 x
.array
[1] |= y
.array
[1];
1670 x
.array
[0] |= y
.array
[0];
1678 static INLINE i386_cpu_flags
1679 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1681 switch (ARRAY_SIZE (x
.array
))
1684 x
.array
[3] &= ~y
.array
[3];
1687 x
.array
[2] &= ~y
.array
[2];
1690 x
.array
[1] &= ~y
.array
[1];
1693 x
.array
[0] &= ~y
.array
[0];
1701 #define CPU_FLAGS_ARCH_MATCH 0x1
1702 #define CPU_FLAGS_64BIT_MATCH 0x2
1704 #define CPU_FLAGS_PERFECT_MATCH \
1705 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1707 /* Return CPU flags match bits. */
1710 cpu_flags_match (const insn_template
*t
)
1712 i386_cpu_flags x
= t
->cpu_flags
;
1713 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1715 x
.bitfield
.cpu64
= 0;
1716 x
.bitfield
.cpuno64
= 0;
1718 if (cpu_flags_all_zero (&x
))
1720 /* This instruction is available on all archs. */
1721 match
|= CPU_FLAGS_ARCH_MATCH
;
1725 /* This instruction is available only on some archs. */
1726 i386_cpu_flags cpu
= cpu_arch_flags
;
1728 /* AVX512VL is no standalone feature - match it and then strip it. */
1729 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1731 x
.bitfield
.cpuavx512vl
= 0;
1733 cpu
= cpu_flags_and (x
, cpu
);
1734 if (!cpu_flags_all_zero (&cpu
))
1736 if (x
.bitfield
.cpuavx
)
1738 /* We need to check a few extra flags with AVX. */
1739 if (cpu
.bitfield
.cpuavx
1740 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1741 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1742 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1743 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1744 match
|= CPU_FLAGS_ARCH_MATCH
;
1746 else if (x
.bitfield
.cpuavx512f
)
1748 /* We need to check a few extra flags with AVX512F. */
1749 if (cpu
.bitfield
.cpuavx512f
1750 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1751 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1752 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1753 match
|= CPU_FLAGS_ARCH_MATCH
;
1756 match
|= CPU_FLAGS_ARCH_MATCH
;
1762 static INLINE i386_operand_type
1763 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1765 switch (ARRAY_SIZE (x
.array
))
1768 x
.array
[2] &= y
.array
[2];
1771 x
.array
[1] &= y
.array
[1];
1774 x
.array
[0] &= y
.array
[0];
1782 static INLINE i386_operand_type
1783 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1785 switch (ARRAY_SIZE (x
.array
))
1788 x
.array
[2] &= ~y
.array
[2];
1791 x
.array
[1] &= ~y
.array
[1];
1794 x
.array
[0] &= ~y
.array
[0];
1802 static INLINE i386_operand_type
1803 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1805 switch (ARRAY_SIZE (x
.array
))
1808 x
.array
[2] |= y
.array
[2];
1811 x
.array
[1] |= y
.array
[1];
1814 x
.array
[0] |= y
.array
[0];
1822 static INLINE i386_operand_type
1823 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1825 switch (ARRAY_SIZE (x
.array
))
1828 x
.array
[2] ^= y
.array
[2];
1831 x
.array
[1] ^= y
.array
[1];
1834 x
.array
[0] ^= y
.array
[0];
1842 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1843 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1844 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1845 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1846 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1847 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1848 static const i386_operand_type anydisp
1849 = OPERAND_TYPE_ANYDISP
;
1850 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1851 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1852 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1853 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1854 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1855 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1856 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1857 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1858 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1859 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1860 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1861 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1872 operand_type_check (i386_operand_type t
, enum operand_type c
)
1877 return t
.bitfield
.reg
;
1880 return (t
.bitfield
.imm8
1884 || t
.bitfield
.imm32s
1885 || t
.bitfield
.imm64
);
1888 return (t
.bitfield
.disp8
1889 || t
.bitfield
.disp16
1890 || t
.bitfield
.disp32
1891 || t
.bitfield
.disp32s
1892 || t
.bitfield
.disp64
);
1895 return (t
.bitfield
.disp8
1896 || t
.bitfield
.disp16
1897 || t
.bitfield
.disp32
1898 || t
.bitfield
.disp32s
1899 || t
.bitfield
.disp64
1900 || t
.bitfield
.baseindex
);
1909 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1910 between operand GIVEN and opeand WANTED for instruction template T. */
1913 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1916 return !((i
.types
[given
].bitfield
.byte
1917 && !t
->operand_types
[wanted
].bitfield
.byte
)
1918 || (i
.types
[given
].bitfield
.word
1919 && !t
->operand_types
[wanted
].bitfield
.word
)
1920 || (i
.types
[given
].bitfield
.dword
1921 && !t
->operand_types
[wanted
].bitfield
.dword
)
1922 || (i
.types
[given
].bitfield
.qword
1923 && !t
->operand_types
[wanted
].bitfield
.qword
)
1924 || (i
.types
[given
].bitfield
.tbyte
1925 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1928 /* Return 1 if there is no conflict in SIMD register between operand
1929 GIVEN and opeand WANTED for instruction template T. */
1932 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1935 return !((i
.types
[given
].bitfield
.xmmword
1936 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1937 || (i
.types
[given
].bitfield
.ymmword
1938 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1939 || (i
.types
[given
].bitfield
.zmmword
1940 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1943 /* Return 1 if there is no conflict in any size between operand GIVEN
1944 and opeand WANTED for instruction template T. */
1947 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1950 return (match_operand_size (t
, wanted
, given
)
1951 && !((i
.types
[given
].bitfield
.unspecified
1953 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1954 || (i
.types
[given
].bitfield
.fword
1955 && !t
->operand_types
[wanted
].bitfield
.fword
)
1956 /* For scalar opcode templates to allow register and memory
1957 operands at the same time, some special casing is needed
1958 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1959 down-conversion vpmov*. */
1960 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1961 && !t
->opcode_modifier
.broadcast
1962 && (t
->operand_types
[wanted
].bitfield
.byte
1963 || t
->operand_types
[wanted
].bitfield
.word
1964 || t
->operand_types
[wanted
].bitfield
.dword
1965 || t
->operand_types
[wanted
].bitfield
.qword
))
1966 ? (i
.types
[given
].bitfield
.xmmword
1967 || i
.types
[given
].bitfield
.ymmword
1968 || i
.types
[given
].bitfield
.zmmword
)
1969 : !match_simd_size(t
, wanted
, given
))));
1972 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1973 operands for instruction template T, and it has MATCH_REVERSE set if there
1974 is no size conflict on any operands for the template with operands reversed
1975 (and the template allows for reversing in the first place). */
1977 #define MATCH_STRAIGHT 1
1978 #define MATCH_REVERSE 2
1980 static INLINE
unsigned int
1981 operand_size_match (const insn_template
*t
)
1983 unsigned int j
, match
= MATCH_STRAIGHT
;
1985 /* Don't check jump instructions. */
1986 if (t
->opcode_modifier
.jump
1987 || t
->opcode_modifier
.jumpbyte
1988 || t
->opcode_modifier
.jumpdword
1989 || t
->opcode_modifier
.jumpintersegment
)
1992 /* Check memory and accumulator operand size. */
1993 for (j
= 0; j
< i
.operands
; j
++)
1995 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1996 && t
->operand_types
[j
].bitfield
.anysize
)
1999 if (t
->operand_types
[j
].bitfield
.reg
2000 && !match_operand_size (t
, j
, j
))
2006 if (t
->operand_types
[j
].bitfield
.regsimd
2007 && !match_simd_size (t
, j
, j
))
2013 if (t
->operand_types
[j
].bitfield
.acc
2014 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2020 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2027 if (!t
->opcode_modifier
.d
)
2031 i
.error
= operand_size_mismatch
;
2035 /* Check reverse. */
2036 gas_assert (i
.operands
== 2);
2038 for (j
= 0; j
< 2; j
++)
2040 if ((t
->operand_types
[j
].bitfield
.reg
2041 || t
->operand_types
[j
].bitfield
.acc
)
2042 && !match_operand_size (t
, j
, !j
))
2045 if ((i
.flags
[!j
] & Operand_Mem
) && !match_mem_size (t
, j
, !j
))
2049 return match
| MATCH_REVERSE
;
2053 operand_type_match (i386_operand_type overlap
,
2054 i386_operand_type given
)
2056 i386_operand_type temp
= overlap
;
2058 temp
.bitfield
.jumpabsolute
= 0;
2059 temp
.bitfield
.unspecified
= 0;
2060 temp
.bitfield
.byte
= 0;
2061 temp
.bitfield
.word
= 0;
2062 temp
.bitfield
.dword
= 0;
2063 temp
.bitfield
.fword
= 0;
2064 temp
.bitfield
.qword
= 0;
2065 temp
.bitfield
.tbyte
= 0;
2066 temp
.bitfield
.xmmword
= 0;
2067 temp
.bitfield
.ymmword
= 0;
2068 temp
.bitfield
.zmmword
= 0;
2069 if (operand_type_all_zero (&temp
))
2072 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2073 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2077 i
.error
= operand_type_mismatch
;
2081 /* If given types g0 and g1 are registers they must be of the same type
2082 unless the expected operand type register overlap is null.
2083 Memory operand size of certain SIMD instructions is also being checked
2087 operand_type_register_match (i386_operand_type g0
,
2088 i386_operand_type t0
,
2089 i386_operand_type g1
,
2090 i386_operand_type t1
)
2092 if (!g0
.bitfield
.reg
2093 && !g0
.bitfield
.regsimd
2094 && (!operand_type_check (g0
, anymem
)
2095 || g0
.bitfield
.unspecified
2096 || !t0
.bitfield
.regsimd
))
2099 if (!g1
.bitfield
.reg
2100 && !g1
.bitfield
.regsimd
2101 && (!operand_type_check (g1
, anymem
)
2102 || g1
.bitfield
.unspecified
2103 || !t1
.bitfield
.regsimd
))
2106 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2107 && g0
.bitfield
.word
== g1
.bitfield
.word
2108 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2109 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2110 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2111 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2112 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2115 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2116 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2117 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2118 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2119 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2120 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2121 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2124 i
.error
= register_type_mismatch
;
2129 static INLINE
unsigned int
2130 register_number (const reg_entry
*r
)
2132 unsigned int nr
= r
->reg_num
;
2134 if (r
->reg_flags
& RegRex
)
2137 if (r
->reg_flags
& RegVRex
)
2143 static INLINE
unsigned int
2144 mode_from_disp_size (i386_operand_type t
)
2146 if (t
.bitfield
.disp8
)
2148 else if (t
.bitfield
.disp16
2149 || t
.bitfield
.disp32
2150 || t
.bitfield
.disp32s
)
2157 fits_in_signed_byte (addressT num
)
2159 return num
+ 0x80 <= 0xff;
2163 fits_in_unsigned_byte (addressT num
)
2169 fits_in_unsigned_word (addressT num
)
2171 return num
<= 0xffff;
2175 fits_in_signed_word (addressT num
)
2177 return num
+ 0x8000 <= 0xffff;
2181 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2186 return num
+ 0x80000000 <= 0xffffffff;
2188 } /* fits_in_signed_long() */
2191 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2196 return num
<= 0xffffffff;
2198 } /* fits_in_unsigned_long() */
2201 fits_in_disp8 (offsetT num
)
2203 int shift
= i
.memshift
;
2209 mask
= (1 << shift
) - 1;
2211 /* Return 0 if NUM isn't properly aligned. */
2215 /* Check if NUM will fit in 8bit after shift. */
2216 return fits_in_signed_byte (num
>> shift
);
2220 fits_in_imm4 (offsetT num
)
2222 return (num
& 0xf) == num
;
2225 static i386_operand_type
2226 smallest_imm_type (offsetT num
)
2228 i386_operand_type t
;
2230 operand_type_set (&t
, 0);
2231 t
.bitfield
.imm64
= 1;
2233 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2235 /* This code is disabled on the 486 because all the Imm1 forms
2236 in the opcode table are slower on the i486. They're the
2237 versions with the implicitly specified single-position
2238 displacement, which has another syntax if you really want to
2240 t
.bitfield
.imm1
= 1;
2241 t
.bitfield
.imm8
= 1;
2242 t
.bitfield
.imm8s
= 1;
2243 t
.bitfield
.imm16
= 1;
2244 t
.bitfield
.imm32
= 1;
2245 t
.bitfield
.imm32s
= 1;
2247 else if (fits_in_signed_byte (num
))
2249 t
.bitfield
.imm8
= 1;
2250 t
.bitfield
.imm8s
= 1;
2251 t
.bitfield
.imm16
= 1;
2252 t
.bitfield
.imm32
= 1;
2253 t
.bitfield
.imm32s
= 1;
2255 else if (fits_in_unsigned_byte (num
))
2257 t
.bitfield
.imm8
= 1;
2258 t
.bitfield
.imm16
= 1;
2259 t
.bitfield
.imm32
= 1;
2260 t
.bitfield
.imm32s
= 1;
2262 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2264 t
.bitfield
.imm16
= 1;
2265 t
.bitfield
.imm32
= 1;
2266 t
.bitfield
.imm32s
= 1;
2268 else if (fits_in_signed_long (num
))
2270 t
.bitfield
.imm32
= 1;
2271 t
.bitfield
.imm32s
= 1;
2273 else if (fits_in_unsigned_long (num
))
2274 t
.bitfield
.imm32
= 1;
2280 offset_in_range (offsetT val
, int size
)
2286 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2287 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2288 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2290 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2296 /* If BFD64, sign extend val for 32bit address mode. */
2297 if (flag_code
!= CODE_64BIT
2298 || i
.prefix
[ADDR_PREFIX
])
2299 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2300 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2303 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2305 char buf1
[40], buf2
[40];
2307 sprint_value (buf1
, val
);
2308 sprint_value (buf2
, val
& mask
);
2309 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2324 a. PREFIX_EXIST if attempting to add a prefix where one from the
2325 same class already exists.
2326 b. PREFIX_LOCK if lock prefix is added.
2327 c. PREFIX_REP if rep/repne prefix is added.
2328 d. PREFIX_DS if ds prefix is added.
2329 e. PREFIX_OTHER if other prefix is added.
2332 static enum PREFIX_GROUP
2333 add_prefix (unsigned int prefix
)
2335 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2338 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2339 && flag_code
== CODE_64BIT
)
2341 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2342 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2343 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2344 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2355 case DS_PREFIX_OPCODE
:
2358 case CS_PREFIX_OPCODE
:
2359 case ES_PREFIX_OPCODE
:
2360 case FS_PREFIX_OPCODE
:
2361 case GS_PREFIX_OPCODE
:
2362 case SS_PREFIX_OPCODE
:
2366 case REPNE_PREFIX_OPCODE
:
2367 case REPE_PREFIX_OPCODE
:
2372 case LOCK_PREFIX_OPCODE
:
2381 case ADDR_PREFIX_OPCODE
:
2385 case DATA_PREFIX_OPCODE
:
2389 if (i
.prefix
[q
] != 0)
2397 i
.prefix
[q
] |= prefix
;
2400 as_bad (_("same type of prefix used twice"));
2406 update_code_flag (int value
, int check
)
2408 PRINTF_LIKE ((*as_error
));
2410 flag_code
= (enum flag_code
) value
;
2411 if (flag_code
== CODE_64BIT
)
2413 cpu_arch_flags
.bitfield
.cpu64
= 1;
2414 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2418 cpu_arch_flags
.bitfield
.cpu64
= 0;
2419 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2421 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2424 as_error
= as_fatal
;
2427 (*as_error
) (_("64bit mode not supported on `%s'."),
2428 cpu_arch_name
? cpu_arch_name
: default_arch
);
2430 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2433 as_error
= as_fatal
;
2436 (*as_error
) (_("32bit mode not supported on `%s'."),
2437 cpu_arch_name
? cpu_arch_name
: default_arch
);
2439 stackop_size
= '\0';
2443 set_code_flag (int value
)
2445 update_code_flag (value
, 0);
2449 set_16bit_gcc_code_flag (int new_code_flag
)
2451 flag_code
= (enum flag_code
) new_code_flag
;
2452 if (flag_code
!= CODE_16BIT
)
2454 cpu_arch_flags
.bitfield
.cpu64
= 0;
2455 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2456 stackop_size
= LONG_MNEM_SUFFIX
;
2460 set_intel_syntax (int syntax_flag
)
2462 /* Find out if register prefixing is specified. */
2463 int ask_naked_reg
= 0;
2466 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2469 int e
= get_symbol_name (&string
);
2471 if (strcmp (string
, "prefix") == 0)
2473 else if (strcmp (string
, "noprefix") == 0)
2476 as_bad (_("bad argument to syntax directive."));
2477 (void) restore_line_pointer (e
);
2479 demand_empty_rest_of_line ();
2481 intel_syntax
= syntax_flag
;
2483 if (ask_naked_reg
== 0)
2484 allow_naked_reg
= (intel_syntax
2485 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2487 allow_naked_reg
= (ask_naked_reg
< 0);
2489 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2491 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2492 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2493 register_prefix
= allow_naked_reg
? "" : "%";
2497 set_intel_mnemonic (int mnemonic_flag
)
2499 intel_mnemonic
= mnemonic_flag
;
2503 set_allow_index_reg (int flag
)
2505 allow_index_reg
= flag
;
2509 set_check (int what
)
2511 enum check_kind
*kind
;
2516 kind
= &operand_check
;
2527 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2530 int e
= get_symbol_name (&string
);
2532 if (strcmp (string
, "none") == 0)
2534 else if (strcmp (string
, "warning") == 0)
2535 *kind
= check_warning
;
2536 else if (strcmp (string
, "error") == 0)
2537 *kind
= check_error
;
2539 as_bad (_("bad argument to %s_check directive."), str
);
2540 (void) restore_line_pointer (e
);
2543 as_bad (_("missing argument for %s_check directive"), str
);
2545 demand_empty_rest_of_line ();
2549 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2550 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2552 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2553 static const char *arch
;
2555 /* Intel LIOM is only supported on ELF. */
2561 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2562 use default_arch. */
2563 arch
= cpu_arch_name
;
2565 arch
= default_arch
;
2568 /* If we are targeting Intel MCU, we must enable it. */
2569 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2570 || new_flag
.bitfield
.cpuiamcu
)
2573 /* If we are targeting Intel L1OM, we must enable it. */
2574 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2575 || new_flag
.bitfield
.cpul1om
)
2578 /* If we are targeting Intel K1OM, we must enable it. */
2579 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2580 || new_flag
.bitfield
.cpuk1om
)
2583 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2588 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2592 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2595 int e
= get_symbol_name (&string
);
2597 i386_cpu_flags flags
;
2599 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2601 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2603 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2607 cpu_arch_name
= cpu_arch
[j
].name
;
2608 cpu_sub_arch_name
= NULL
;
2609 cpu_arch_flags
= cpu_arch
[j
].flags
;
2610 if (flag_code
== CODE_64BIT
)
2612 cpu_arch_flags
.bitfield
.cpu64
= 1;
2613 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2617 cpu_arch_flags
.bitfield
.cpu64
= 0;
2618 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2620 cpu_arch_isa
= cpu_arch
[j
].type
;
2621 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2622 if (!cpu_arch_tune_set
)
2624 cpu_arch_tune
= cpu_arch_isa
;
2625 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2630 flags
= cpu_flags_or (cpu_arch_flags
,
2633 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2635 if (cpu_sub_arch_name
)
2637 char *name
= cpu_sub_arch_name
;
2638 cpu_sub_arch_name
= concat (name
,
2640 (const char *) NULL
);
2644 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2645 cpu_arch_flags
= flags
;
2646 cpu_arch_isa_flags
= flags
;
2650 = cpu_flags_or (cpu_arch_isa_flags
,
2652 (void) restore_line_pointer (e
);
2653 demand_empty_rest_of_line ();
2658 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2660 /* Disable an ISA extension. */
2661 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2662 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2664 flags
= cpu_flags_and_not (cpu_arch_flags
,
2665 cpu_noarch
[j
].flags
);
2666 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2668 if (cpu_sub_arch_name
)
2670 char *name
= cpu_sub_arch_name
;
2671 cpu_sub_arch_name
= concat (name
, string
,
2672 (const char *) NULL
);
2676 cpu_sub_arch_name
= xstrdup (string
);
2677 cpu_arch_flags
= flags
;
2678 cpu_arch_isa_flags
= flags
;
2680 (void) restore_line_pointer (e
);
2681 demand_empty_rest_of_line ();
2685 j
= ARRAY_SIZE (cpu_arch
);
2688 if (j
>= ARRAY_SIZE (cpu_arch
))
2689 as_bad (_("no such architecture: `%s'"), string
);
2691 *input_line_pointer
= e
;
2694 as_bad (_("missing cpu architecture"));
2696 no_cond_jump_promotion
= 0;
2697 if (*input_line_pointer
== ','
2698 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2703 ++input_line_pointer
;
2704 e
= get_symbol_name (&string
);
2706 if (strcmp (string
, "nojumps") == 0)
2707 no_cond_jump_promotion
= 1;
2708 else if (strcmp (string
, "jumps") == 0)
2711 as_bad (_("no such architecture modifier: `%s'"), string
);
2713 (void) restore_line_pointer (e
);
2716 demand_empty_rest_of_line ();
2719 enum bfd_architecture
2722 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2724 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2725 || flag_code
!= CODE_64BIT
)
2726 as_fatal (_("Intel L1OM is 64bit ELF only"));
2727 return bfd_arch_l1om
;
2729 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2731 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2732 || flag_code
!= CODE_64BIT
)
2733 as_fatal (_("Intel K1OM is 64bit ELF only"));
2734 return bfd_arch_k1om
;
2736 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2738 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2739 || flag_code
== CODE_64BIT
)
2740 as_fatal (_("Intel MCU is 32bit ELF only"));
2741 return bfd_arch_iamcu
;
2744 return bfd_arch_i386
;
2750 if (!strncmp (default_arch
, "x86_64", 6))
2752 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2754 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2755 || default_arch
[6] != '\0')
2756 as_fatal (_("Intel L1OM is 64bit ELF only"));
2757 return bfd_mach_l1om
;
2759 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2761 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2762 || default_arch
[6] != '\0')
2763 as_fatal (_("Intel K1OM is 64bit ELF only"));
2764 return bfd_mach_k1om
;
2766 else if (default_arch
[6] == '\0')
2767 return bfd_mach_x86_64
;
2769 return bfd_mach_x64_32
;
2771 else if (!strcmp (default_arch
, "i386")
2772 || !strcmp (default_arch
, "iamcu"))
2774 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2776 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2777 as_fatal (_("Intel MCU is 32bit ELF only"));
2778 return bfd_mach_i386_iamcu
;
2781 return bfd_mach_i386_i386
;
2784 as_fatal (_("unknown architecture"));
2790 const char *hash_err
;
2792 /* Support pseudo prefixes like {disp32}. */
2793 lex_type
['{'] = LEX_BEGIN_NAME
;
2795 /* Initialize op_hash hash table. */
2796 op_hash
= hash_new ();
2799 const insn_template
*optab
;
2800 templates
*core_optab
;
2802 /* Setup for loop. */
2804 core_optab
= XNEW (templates
);
2805 core_optab
->start
= optab
;
2810 if (optab
->name
== NULL
2811 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2813 /* different name --> ship out current template list;
2814 add to hash table; & begin anew. */
2815 core_optab
->end
= optab
;
2816 hash_err
= hash_insert (op_hash
,
2818 (void *) core_optab
);
2821 as_fatal (_("can't hash %s: %s"),
2825 if (optab
->name
== NULL
)
2827 core_optab
= XNEW (templates
);
2828 core_optab
->start
= optab
;
2833 /* Initialize reg_hash hash table. */
2834 reg_hash
= hash_new ();
2836 const reg_entry
*regtab
;
2837 unsigned int regtab_size
= i386_regtab_size
;
2839 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2841 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2843 as_fatal (_("can't hash %s: %s"),
2849 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2854 for (c
= 0; c
< 256; c
++)
2859 mnemonic_chars
[c
] = c
;
2860 register_chars
[c
] = c
;
2861 operand_chars
[c
] = c
;
2863 else if (ISLOWER (c
))
2865 mnemonic_chars
[c
] = c
;
2866 register_chars
[c
] = c
;
2867 operand_chars
[c
] = c
;
2869 else if (ISUPPER (c
))
2871 mnemonic_chars
[c
] = TOLOWER (c
);
2872 register_chars
[c
] = mnemonic_chars
[c
];
2873 operand_chars
[c
] = c
;
2875 else if (c
== '{' || c
== '}')
2877 mnemonic_chars
[c
] = c
;
2878 operand_chars
[c
] = c
;
2881 if (ISALPHA (c
) || ISDIGIT (c
))
2882 identifier_chars
[c
] = c
;
2885 identifier_chars
[c
] = c
;
2886 operand_chars
[c
] = c
;
2891 identifier_chars
['@'] = '@';
2894 identifier_chars
['?'] = '?';
2895 operand_chars
['?'] = '?';
2897 digit_chars
['-'] = '-';
2898 mnemonic_chars
['_'] = '_';
2899 mnemonic_chars
['-'] = '-';
2900 mnemonic_chars
['.'] = '.';
2901 identifier_chars
['_'] = '_';
2902 identifier_chars
['.'] = '.';
2904 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2905 operand_chars
[(unsigned char) *p
] = *p
;
2908 if (flag_code
== CODE_64BIT
)
2910 #if defined (OBJ_COFF) && defined (TE_PE)
2911 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2914 x86_dwarf2_return_column
= 16;
2916 x86_cie_data_alignment
= -8;
2920 x86_dwarf2_return_column
= 8;
2921 x86_cie_data_alignment
= -4;
2926 i386_print_statistics (FILE *file
)
2928 hash_print_statistics (file
, "i386 opcode", op_hash
);
2929 hash_print_statistics (file
, "i386 register", reg_hash
);
2934 /* Debugging routines for md_assemble. */
2935 static void pte (insn_template
*);
2936 static void pt (i386_operand_type
);
2937 static void pe (expressionS
*);
2938 static void ps (symbolS
*);
2941 pi (char *line
, i386_insn
*x
)
2945 fprintf (stdout
, "%s: template ", line
);
2947 fprintf (stdout
, " address: base %s index %s scale %x\n",
2948 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2949 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2950 x
->log2_scale_factor
);
2951 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2952 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2953 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2954 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2955 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2956 (x
->rex
& REX_W
) != 0,
2957 (x
->rex
& REX_R
) != 0,
2958 (x
->rex
& REX_X
) != 0,
2959 (x
->rex
& REX_B
) != 0);
2960 for (j
= 0; j
< x
->operands
; j
++)
2962 fprintf (stdout
, " #%d: ", j
+ 1);
2964 fprintf (stdout
, "\n");
2965 if (x
->types
[j
].bitfield
.reg
2966 || x
->types
[j
].bitfield
.regmmx
2967 || x
->types
[j
].bitfield
.regsimd
2968 || x
->types
[j
].bitfield
.sreg2
2969 || x
->types
[j
].bitfield
.sreg3
2970 || x
->types
[j
].bitfield
.control
2971 || x
->types
[j
].bitfield
.debug
2972 || x
->types
[j
].bitfield
.test
)
2973 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2974 if (operand_type_check (x
->types
[j
], imm
))
2976 if (operand_type_check (x
->types
[j
], disp
))
2977 pe (x
->op
[j
].disps
);
2982 pte (insn_template
*t
)
2985 fprintf (stdout
, " %d operands ", t
->operands
);
2986 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2987 if (t
->extension_opcode
!= None
)
2988 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2989 if (t
->opcode_modifier
.d
)
2990 fprintf (stdout
, "D");
2991 if (t
->opcode_modifier
.w
)
2992 fprintf (stdout
, "W");
2993 fprintf (stdout
, "\n");
2994 for (j
= 0; j
< t
->operands
; j
++)
2996 fprintf (stdout
, " #%d type ", j
+ 1);
2997 pt (t
->operand_types
[j
]);
2998 fprintf (stdout
, "\n");
3005 fprintf (stdout
, " operation %d\n", e
->X_op
);
3006 fprintf (stdout
, " add_number %ld (%lx)\n",
3007 (long) e
->X_add_number
, (long) e
->X_add_number
);
3008 if (e
->X_add_symbol
)
3010 fprintf (stdout
, " add_symbol ");
3011 ps (e
->X_add_symbol
);
3012 fprintf (stdout
, "\n");
3016 fprintf (stdout
, " op_symbol ");
3017 ps (e
->X_op_symbol
);
3018 fprintf (stdout
, "\n");
3025 fprintf (stdout
, "%s type %s%s",
3027 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3028 segment_name (S_GET_SEGMENT (s
)));
3031 static struct type_name
3033 i386_operand_type mask
;
3036 const type_names
[] =
3038 { OPERAND_TYPE_REG8
, "r8" },
3039 { OPERAND_TYPE_REG16
, "r16" },
3040 { OPERAND_TYPE_REG32
, "r32" },
3041 { OPERAND_TYPE_REG64
, "r64" },
3042 { OPERAND_TYPE_IMM8
, "i8" },
3043 { OPERAND_TYPE_IMM8
, "i8s" },
3044 { OPERAND_TYPE_IMM16
, "i16" },
3045 { OPERAND_TYPE_IMM32
, "i32" },
3046 { OPERAND_TYPE_IMM32S
, "i32s" },
3047 { OPERAND_TYPE_IMM64
, "i64" },
3048 { OPERAND_TYPE_IMM1
, "i1" },
3049 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3050 { OPERAND_TYPE_DISP8
, "d8" },
3051 { OPERAND_TYPE_DISP16
, "d16" },
3052 { OPERAND_TYPE_DISP32
, "d32" },
3053 { OPERAND_TYPE_DISP32S
, "d32s" },
3054 { OPERAND_TYPE_DISP64
, "d64" },
3055 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3056 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3057 { OPERAND_TYPE_CONTROL
, "control reg" },
3058 { OPERAND_TYPE_TEST
, "test reg" },
3059 { OPERAND_TYPE_DEBUG
, "debug reg" },
3060 { OPERAND_TYPE_FLOATREG
, "FReg" },
3061 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3062 { OPERAND_TYPE_SREG2
, "SReg2" },
3063 { OPERAND_TYPE_SREG3
, "SReg3" },
3064 { OPERAND_TYPE_ACC
, "Acc" },
3065 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3066 { OPERAND_TYPE_REGMMX
, "rMMX" },
3067 { OPERAND_TYPE_REGXMM
, "rXMM" },
3068 { OPERAND_TYPE_REGYMM
, "rYMM" },
3069 { OPERAND_TYPE_REGZMM
, "rZMM" },
3070 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3071 { OPERAND_TYPE_ESSEG
, "es" },
3075 pt (i386_operand_type t
)
3078 i386_operand_type a
;
3080 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3082 a
= operand_type_and (t
, type_names
[j
].mask
);
3083 if (!operand_type_all_zero (&a
))
3084 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3089 #endif /* DEBUG386 */
3091 static bfd_reloc_code_real_type
3092 reloc (unsigned int size
,
3095 bfd_reloc_code_real_type other
)
3097 if (other
!= NO_RELOC
)
3099 reloc_howto_type
*rel
;
3104 case BFD_RELOC_X86_64_GOT32
:
3105 return BFD_RELOC_X86_64_GOT64
;
3107 case BFD_RELOC_X86_64_GOTPLT64
:
3108 return BFD_RELOC_X86_64_GOTPLT64
;
3110 case BFD_RELOC_X86_64_PLTOFF64
:
3111 return BFD_RELOC_X86_64_PLTOFF64
;
3113 case BFD_RELOC_X86_64_GOTPC32
:
3114 other
= BFD_RELOC_X86_64_GOTPC64
;
3116 case BFD_RELOC_X86_64_GOTPCREL
:
3117 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3119 case BFD_RELOC_X86_64_TPOFF32
:
3120 other
= BFD_RELOC_X86_64_TPOFF64
;
3122 case BFD_RELOC_X86_64_DTPOFF32
:
3123 other
= BFD_RELOC_X86_64_DTPOFF64
;
3129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3130 if (other
== BFD_RELOC_SIZE32
)
3133 other
= BFD_RELOC_SIZE64
;
3136 as_bad (_("there are no pc-relative size relocations"));
3142 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3143 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3146 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3148 as_bad (_("unknown relocation (%u)"), other
);
3149 else if (size
!= bfd_get_reloc_size (rel
))
3150 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3151 bfd_get_reloc_size (rel
),
3153 else if (pcrel
&& !rel
->pc_relative
)
3154 as_bad (_("non-pc-relative relocation for pc-relative field"));
3155 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3157 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3159 as_bad (_("relocated field and relocation type differ in signedness"));
3168 as_bad (_("there are no unsigned pc-relative relocations"));
3171 case 1: return BFD_RELOC_8_PCREL
;
3172 case 2: return BFD_RELOC_16_PCREL
;
3173 case 4: return BFD_RELOC_32_PCREL
;
3174 case 8: return BFD_RELOC_64_PCREL
;
3176 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3183 case 4: return BFD_RELOC_X86_64_32S
;
3188 case 1: return BFD_RELOC_8
;
3189 case 2: return BFD_RELOC_16
;
3190 case 4: return BFD_RELOC_32
;
3191 case 8: return BFD_RELOC_64
;
3193 as_bad (_("cannot do %s %u byte relocation"),
3194 sign
> 0 ? "signed" : "unsigned", size
);
3200 /* Here we decide which fixups can be adjusted to make them relative to
3201 the beginning of the section instead of the symbol. Basically we need
3202 to make sure that the dynamic relocations are done correctly, so in
3203 some cases we force the original symbol to be used. */
3206 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3212 /* Don't adjust pc-relative references to merge sections in 64-bit
3214 if (use_rela_relocations
3215 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3219 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3220 and changed later by validate_fix. */
3221 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3222 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3225 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3226 for size relocations. */
3227 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3228 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3229 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3230 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3231 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3232 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3235 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3236 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3237 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3238 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3239 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3240 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3241 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3242 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3248 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3249 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3250 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3251 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3252 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3253 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3254 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3255 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3256 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3257 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3258 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3259 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3266 intel_float_operand (const char *mnemonic
)
3268 /* Note that the value returned is meaningful only for opcodes with (memory)
3269 operands, hence the code here is free to improperly handle opcodes that
3270 have no operands (for better performance and smaller code). */
3272 if (mnemonic
[0] != 'f')
3273 return 0; /* non-math */
3275 switch (mnemonic
[1])
3277 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3278 the fs segment override prefix not currently handled because no
3279 call path can make opcodes without operands get here */
3281 return 2 /* integer op */;
3283 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3284 return 3; /* fldcw/fldenv */
3287 if (mnemonic
[2] != 'o' /* fnop */)
3288 return 3; /* non-waiting control op */
3291 if (mnemonic
[2] == 's')
3292 return 3; /* frstor/frstpm */
3295 if (mnemonic
[2] == 'a')
3296 return 3; /* fsave */
3297 if (mnemonic
[2] == 't')
3299 switch (mnemonic
[3])
3301 case 'c': /* fstcw */
3302 case 'd': /* fstdw */
3303 case 'e': /* fstenv */
3304 case 's': /* fsts[gw] */
3310 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3311 return 0; /* fxsave/fxrstor are not really math ops */
3318 /* Build the VEX prefix. */
3321 build_vex_prefix (const insn_template
*t
)
3323 unsigned int register_specifier
;
3324 unsigned int implied_prefix
;
3325 unsigned int vector_length
;
3327 /* Check register specifier. */
3328 if (i
.vex
.register_specifier
)
3330 register_specifier
=
3331 ~register_number (i
.vex
.register_specifier
) & 0xf;
3332 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3335 register_specifier
= 0xf;
3337 /* Use 2-byte VEX prefix by swapping destination and source
3339 if (i
.vec_encoding
!= vex_encoding_vex3
3340 && i
.dir_encoding
== dir_encoding_default
3341 && i
.operands
== i
.reg_operands
3342 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3343 && i
.tm
.opcode_modifier
.load
3346 unsigned int xchg
= i
.operands
- 1;
3347 union i386_op temp_op
;
3348 i386_operand_type temp_type
;
3350 temp_type
= i
.types
[xchg
];
3351 i
.types
[xchg
] = i
.types
[0];
3352 i
.types
[0] = temp_type
;
3353 temp_op
= i
.op
[xchg
];
3354 i
.op
[xchg
] = i
.op
[0];
3357 gas_assert (i
.rm
.mode
== 3);
3361 i
.rm
.regmem
= i
.rm
.reg
;
3364 /* Use the next insn. */
3368 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3369 vector_length
= avxscalar
;
3370 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3376 /* Determine vector length from the last multi-length vector
3379 for (op
= t
->operands
; op
--;)
3380 if (t
->operand_types
[op
].bitfield
.xmmword
3381 && t
->operand_types
[op
].bitfield
.ymmword
3382 && i
.types
[op
].bitfield
.ymmword
)
3389 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3394 case DATA_PREFIX_OPCODE
:
3397 case REPE_PREFIX_OPCODE
:
3400 case REPNE_PREFIX_OPCODE
:
3407 /* Use 2-byte VEX prefix if possible. */
3408 if (i
.vec_encoding
!= vex_encoding_vex3
3409 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3410 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3411 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3413 /* 2-byte VEX prefix. */
3417 i
.vex
.bytes
[0] = 0xc5;
3419 /* Check the REX.R bit. */
3420 r
= (i
.rex
& REX_R
) ? 0 : 1;
3421 i
.vex
.bytes
[1] = (r
<< 7
3422 | register_specifier
<< 3
3423 | vector_length
<< 2
3428 /* 3-byte VEX prefix. */
3433 switch (i
.tm
.opcode_modifier
.vexopcode
)
3437 i
.vex
.bytes
[0] = 0xc4;
3441 i
.vex
.bytes
[0] = 0xc4;
3445 i
.vex
.bytes
[0] = 0xc4;
3449 i
.vex
.bytes
[0] = 0x8f;
3453 i
.vex
.bytes
[0] = 0x8f;
3457 i
.vex
.bytes
[0] = 0x8f;
3463 /* The high 3 bits of the second VEX byte are 1's compliment
3464 of RXB bits from REX. */
3465 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3467 /* Check the REX.W bit. */
3468 w
= (i
.rex
& REX_W
) ? 1 : 0;
3469 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3472 i
.vex
.bytes
[2] = (w
<< 7
3473 | register_specifier
<< 3
3474 | vector_length
<< 2
3479 static INLINE bfd_boolean
3480 is_evex_encoding (const insn_template
*t
)
3482 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3483 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3484 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3487 static INLINE bfd_boolean
3488 is_any_vex_encoding (const insn_template
*t
)
3490 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3491 || is_evex_encoding (t
);
3494 /* Build the EVEX prefix. */
3497 build_evex_prefix (void)
3499 unsigned int register_specifier
;
3500 unsigned int implied_prefix
;
3502 rex_byte vrex_used
= 0;
3504 /* Check register specifier. */
3505 if (i
.vex
.register_specifier
)
3507 gas_assert ((i
.vrex
& REX_X
) == 0);
3509 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3510 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3511 register_specifier
+= 8;
3512 /* The upper 16 registers are encoded in the fourth byte of the
3514 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3515 i
.vex
.bytes
[3] = 0x8;
3516 register_specifier
= ~register_specifier
& 0xf;
3520 register_specifier
= 0xf;
3522 /* Encode upper 16 vector index register in the fourth byte of
3524 if (!(i
.vrex
& REX_X
))
3525 i
.vex
.bytes
[3] = 0x8;
3530 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3535 case DATA_PREFIX_OPCODE
:
3538 case REPE_PREFIX_OPCODE
:
3541 case REPNE_PREFIX_OPCODE
:
3548 /* 4 byte EVEX prefix. */
3550 i
.vex
.bytes
[0] = 0x62;
3553 switch (i
.tm
.opcode_modifier
.vexopcode
)
3569 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3571 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3573 /* The fifth bit of the second EVEX byte is 1's compliment of the
3574 REX_R bit in VREX. */
3575 if (!(i
.vrex
& REX_R
))
3576 i
.vex
.bytes
[1] |= 0x10;
3580 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3582 /* When all operands are registers, the REX_X bit in REX is not
3583 used. We reuse it to encode the upper 16 registers, which is
3584 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3585 as 1's compliment. */
3586 if ((i
.vrex
& REX_B
))
3589 i
.vex
.bytes
[1] &= ~0x40;
3593 /* EVEX instructions shouldn't need the REX prefix. */
3594 i
.vrex
&= ~vrex_used
;
3595 gas_assert (i
.vrex
== 0);
3597 /* Check the REX.W bit. */
3598 w
= (i
.rex
& REX_W
) ? 1 : 0;
3599 if (i
.tm
.opcode_modifier
.vexw
)
3601 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3604 /* If w is not set it means we are dealing with WIG instruction. */
3607 if (evexwig
== evexw1
)
3611 /* Encode the U bit. */
3612 implied_prefix
|= 0x4;
3614 /* The third byte of the EVEX prefix. */
3615 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3617 /* The fourth byte of the EVEX prefix. */
3618 /* The zeroing-masking bit. */
3619 if (i
.mask
&& i
.mask
->zeroing
)
3620 i
.vex
.bytes
[3] |= 0x80;
3622 /* Don't always set the broadcast bit if there is no RC. */
3625 /* Encode the vector length. */
3626 unsigned int vec_length
;
3628 if (!i
.tm
.opcode_modifier
.evex
3629 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3633 /* Determine vector length from the last multi-length vector
3636 for (op
= i
.operands
; op
--;)
3637 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3638 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3639 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3641 if (i
.types
[op
].bitfield
.zmmword
)
3643 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3646 else if (i
.types
[op
].bitfield
.ymmword
)
3648 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3651 else if (i
.types
[op
].bitfield
.xmmword
)
3653 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3656 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3658 switch (i
.broadcast
->bytes
)
3661 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3664 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3667 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3676 if (op
>= MAX_OPERANDS
)
3680 switch (i
.tm
.opcode_modifier
.evex
)
3682 case EVEXLIG
: /* LL' is ignored */
3683 vec_length
= evexlig
<< 5;
3686 vec_length
= 0 << 5;
3689 vec_length
= 1 << 5;
3692 vec_length
= 2 << 5;
3698 i
.vex
.bytes
[3] |= vec_length
;
3699 /* Encode the broadcast bit. */
3701 i
.vex
.bytes
[3] |= 0x10;
3705 if (i
.rounding
->type
!= saeonly
)
3706 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3708 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3711 if (i
.mask
&& i
.mask
->mask
)
3712 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3716 process_immext (void)
3720 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3723 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3724 with an opcode suffix which is coded in the same place as an
3725 8-bit immediate field would be.
3726 Here we check those operands and remove them afterwards. */
3729 for (x
= 0; x
< i
.operands
; x
++)
3730 if (register_number (i
.op
[x
].regs
) != x
)
3731 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3732 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3738 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3740 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3741 suffix which is coded in the same place as an 8-bit immediate
3743 Here we check those operands and remove them afterwards. */
3746 if (i
.operands
!= 3)
3749 for (x
= 0; x
< 2; x
++)
3750 if (register_number (i
.op
[x
].regs
) != x
)
3751 goto bad_register_operand
;
3753 /* Check for third operand for mwaitx/monitorx insn. */
3754 if (register_number (i
.op
[x
].regs
)
3755 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3757 bad_register_operand
:
3758 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3759 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3766 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3767 which is coded in the same place as an 8-bit immediate field
3768 would be. Here we fake an 8-bit immediate operand from the
3769 opcode suffix stored in tm.extension_opcode.
3771 AVX instructions also use this encoding, for some of
3772 3 argument instructions. */
3774 gas_assert (i
.imm_operands
<= 1
3776 || (is_any_vex_encoding (&i
.tm
)
3777 && i
.operands
<= 4)));
3779 exp
= &im_expressions
[i
.imm_operands
++];
3780 i
.op
[i
.operands
].imms
= exp
;
3781 i
.types
[i
.operands
] = imm8
;
3783 exp
->X_op
= O_constant
;
3784 exp
->X_add_number
= i
.tm
.extension_opcode
;
3785 i
.tm
.extension_opcode
= None
;
3792 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3797 as_bad (_("invalid instruction `%s' after `%s'"),
3798 i
.tm
.name
, i
.hle_prefix
);
3801 if (i
.prefix
[LOCK_PREFIX
])
3803 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3807 case HLEPrefixRelease
:
3808 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3810 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3814 if (i
.mem_operands
== 0
3815 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3817 as_bad (_("memory destination needed for instruction `%s'"
3818 " after `xrelease'"), i
.tm
.name
);
3825 /* Try the shortest encoding by shortening operand size. */
3828 optimize_encoding (void)
3832 if (optimize_for_space
3833 && i
.reg_operands
== 1
3834 && i
.imm_operands
== 1
3835 && !i
.types
[1].bitfield
.byte
3836 && i
.op
[0].imms
->X_op
== O_constant
3837 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3838 && ((i
.tm
.base_opcode
== 0xa8
3839 && i
.tm
.extension_opcode
== None
)
3840 || (i
.tm
.base_opcode
== 0xf6
3841 && i
.tm
.extension_opcode
== 0x0)))
3844 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3846 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3847 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3849 i
.types
[1].bitfield
.byte
= 1;
3850 /* Ignore the suffix. */
3852 if (base_regnum
>= 4
3853 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3855 /* Handle SP, BP, SI and DI registers. */
3856 if (i
.types
[1].bitfield
.word
)
3858 else if (i
.types
[1].bitfield
.dword
)
3866 else if (flag_code
== CODE_64BIT
3867 && ((i
.types
[1].bitfield
.qword
3868 && i
.reg_operands
== 1
3869 && i
.imm_operands
== 1
3870 && i
.op
[0].imms
->X_op
== O_constant
3871 && ((i
.tm
.base_opcode
== 0xb0
3872 && i
.tm
.extension_opcode
== None
3873 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3874 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3875 && (((i
.tm
.base_opcode
== 0x24
3876 || i
.tm
.base_opcode
== 0xa8)
3877 && i
.tm
.extension_opcode
== None
)
3878 || (i
.tm
.base_opcode
== 0x80
3879 && i
.tm
.extension_opcode
== 0x4)
3880 || ((i
.tm
.base_opcode
== 0xf6
3881 || i
.tm
.base_opcode
== 0xc6)
3882 && i
.tm
.extension_opcode
== 0x0)))))
3883 || (i
.types
[0].bitfield
.qword
3884 && ((i
.reg_operands
== 2
3885 && i
.op
[0].regs
== i
.op
[1].regs
3886 && ((i
.tm
.base_opcode
== 0x30
3887 || i
.tm
.base_opcode
== 0x28)
3888 && i
.tm
.extension_opcode
== None
))
3889 || (i
.reg_operands
== 1
3891 && i
.tm
.base_opcode
== 0x30
3892 && i
.tm
.extension_opcode
== None
)))))
3895 andq $imm31, %r64 -> andl $imm31, %r32
3896 testq $imm31, %r64 -> testl $imm31, %r32
3897 xorq %r64, %r64 -> xorl %r32, %r32
3898 subq %r64, %r64 -> subl %r32, %r32
3899 movq $imm31, %r64 -> movl $imm31, %r32
3900 movq $imm32, %r64 -> movl $imm32, %r32
3902 i
.tm
.opcode_modifier
.norex64
= 1;
3903 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3906 movq $imm31, %r64 -> movl $imm31, %r32
3907 movq $imm32, %r64 -> movl $imm32, %r32
3909 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3910 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3911 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3912 i
.types
[0].bitfield
.imm32
= 1;
3913 i
.types
[0].bitfield
.imm32s
= 0;
3914 i
.types
[0].bitfield
.imm64
= 0;
3915 i
.types
[1].bitfield
.dword
= 1;
3916 i
.types
[1].bitfield
.qword
= 0;
3917 if (i
.tm
.base_opcode
== 0xc6)
3920 movq $imm31, %r64 -> movl $imm31, %r32
3922 i
.tm
.base_opcode
= 0xb0;
3923 i
.tm
.extension_opcode
= None
;
3924 i
.tm
.opcode_modifier
.shortform
= 1;
3925 i
.tm
.opcode_modifier
.modrm
= 0;
3929 else if (optimize
> 1
3930 && i
.reg_operands
== 3
3931 && i
.op
[0].regs
== i
.op
[1].regs
3932 && !i
.types
[2].bitfield
.xmmword
3933 && (i
.tm
.opcode_modifier
.vex
3934 || ((!i
.mask
|| i
.mask
->zeroing
)
3936 && is_evex_encoding (&i
.tm
)
3937 && (i
.vec_encoding
!= vex_encoding_evex
3938 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3939 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3940 && i
.types
[2].bitfield
.ymmword
)
3941 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3942 && ((i
.tm
.base_opcode
== 0x55
3943 || i
.tm
.base_opcode
== 0x6655
3944 || i
.tm
.base_opcode
== 0x66df
3945 || i
.tm
.base_opcode
== 0x57
3946 || i
.tm
.base_opcode
== 0x6657
3947 || i
.tm
.base_opcode
== 0x66ef
3948 || i
.tm
.base_opcode
== 0x66f8
3949 || i
.tm
.base_opcode
== 0x66f9
3950 || i
.tm
.base_opcode
== 0x66fa
3951 || i
.tm
.base_opcode
== 0x66fb
3952 || i
.tm
.base_opcode
== 0x42
3953 || i
.tm
.base_opcode
== 0x6642
3954 || i
.tm
.base_opcode
== 0x47
3955 || i
.tm
.base_opcode
== 0x6647)
3956 && i
.tm
.extension_opcode
== None
))
3959 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3961 EVEX VOP %zmmM, %zmmM, %zmmN
3962 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3963 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3964 EVEX VOP %ymmM, %ymmM, %ymmN
3965 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3966 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3967 VEX VOP %ymmM, %ymmM, %ymmN
3968 -> VEX VOP %xmmM, %xmmM, %xmmN
3969 VOP, one of vpandn and vpxor:
3970 VEX VOP %ymmM, %ymmM, %ymmN
3971 -> VEX VOP %xmmM, %xmmM, %xmmN
3972 VOP, one of vpandnd and vpandnq:
3973 EVEX VOP %zmmM, %zmmM, %zmmN
3974 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3975 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3976 EVEX VOP %ymmM, %ymmM, %ymmN
3977 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3978 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3979 VOP, one of vpxord and vpxorq:
3980 EVEX VOP %zmmM, %zmmM, %zmmN
3981 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3982 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3983 EVEX VOP %ymmM, %ymmM, %ymmN
3984 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3985 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3986 VOP, one of kxord and kxorq:
3987 VEX VOP %kM, %kM, %kN
3988 -> VEX kxorw %kM, %kM, %kN
3989 VOP, one of kandnd and kandnq:
3990 VEX VOP %kM, %kM, %kN
3991 -> VEX kandnw %kM, %kM, %kN
3993 if (is_evex_encoding (&i
.tm
))
3995 if (i
.vec_encoding
== vex_encoding_evex
)
3996 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3999 i
.tm
.opcode_modifier
.vex
= VEX128
;
4000 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4001 i
.tm
.opcode_modifier
.evex
= 0;
4004 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4006 i
.tm
.base_opcode
&= 0xff;
4007 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4010 i
.tm
.opcode_modifier
.vex
= VEX128
;
4012 if (i
.tm
.opcode_modifier
.vex
)
4013 for (j
= 0; j
< 3; j
++)
4015 i
.types
[j
].bitfield
.xmmword
= 1;
4016 i
.types
[j
].bitfield
.ymmword
= 0;
4021 /* This is the guts of the machine-dependent assembler. LINE points to a
4022 machine dependent instruction. This function is supposed to emit
4023 the frags/bytes it assembles to. */
4026 md_assemble (char *line
)
4029 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4030 const insn_template
*t
;
4032 /* Initialize globals. */
4033 memset (&i
, '\0', sizeof (i
));
4034 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4035 i
.reloc
[j
] = NO_RELOC
;
4036 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4037 memset (im_expressions
, '\0', sizeof (im_expressions
));
4038 save_stack_p
= save_stack
;
4040 /* First parse an instruction mnemonic & call i386_operand for the operands.
4041 We assume that the scrubber has arranged it so that line[0] is the valid
4042 start of a (possibly prefixed) mnemonic. */
4044 line
= parse_insn (line
, mnemonic
);
4047 mnem_suffix
= i
.suffix
;
4049 line
= parse_operands (line
, mnemonic
);
4051 xfree (i
.memop1_string
);
4052 i
.memop1_string
= NULL
;
4056 /* Now we've parsed the mnemonic into a set of templates, and have the
4057 operands at hand. */
4059 /* All intel opcodes have reversed operands except for "bound" and
4060 "enter". We also don't reverse intersegment "jmp" and "call"
4061 instructions with 2 immediate operands so that the immediate segment
4062 precedes the offset, as it does when in AT&T mode. */
4065 && (strcmp (mnemonic
, "bound") != 0)
4066 && (strcmp (mnemonic
, "invlpga") != 0)
4067 && !(operand_type_check (i
.types
[0], imm
)
4068 && operand_type_check (i
.types
[1], imm
)))
4071 /* The order of the immediates should be reversed
4072 for 2 immediates extrq and insertq instructions */
4073 if (i
.imm_operands
== 2
4074 && (strcmp (mnemonic
, "extrq") == 0
4075 || strcmp (mnemonic
, "insertq") == 0))
4076 swap_2_operands (0, 1);
4081 /* Don't optimize displacement for movabs since it only takes 64bit
4084 && i
.disp_encoding
!= disp_encoding_32bit
4085 && (flag_code
!= CODE_64BIT
4086 || strcmp (mnemonic
, "movabs") != 0))
4089 /* Next, we find a template that matches the given insn,
4090 making sure the overlap of the given operands types is consistent
4091 with the template operand types. */
4093 if (!(t
= match_template (mnem_suffix
)))
4096 if (sse_check
!= check_none
4097 && !i
.tm
.opcode_modifier
.noavx
4098 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4099 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4100 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4101 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4102 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4103 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4104 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4105 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4106 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4107 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4109 (sse_check
== check_warning
4111 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4114 /* Zap movzx and movsx suffix. The suffix has been set from
4115 "word ptr" or "byte ptr" on the source operand in Intel syntax
4116 or extracted from mnemonic in AT&T syntax. But we'll use
4117 the destination register to choose the suffix for encoding. */
4118 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4120 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4121 there is no suffix, the default will be byte extension. */
4122 if (i
.reg_operands
!= 2
4125 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4130 if (i
.tm
.opcode_modifier
.fwait
)
4131 if (!add_prefix (FWAIT_OPCODE
))
4134 /* Check if REP prefix is OK. */
4135 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4137 as_bad (_("invalid instruction `%s' after `%s'"),
4138 i
.tm
.name
, i
.rep_prefix
);
4142 /* Check for lock without a lockable instruction. Destination operand
4143 must be memory unless it is xchg (0x86). */
4144 if (i
.prefix
[LOCK_PREFIX
]
4145 && (!i
.tm
.opcode_modifier
.islockable
4146 || i
.mem_operands
== 0
4147 || (i
.tm
.base_opcode
!= 0x86
4148 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4150 as_bad (_("expecting lockable instruction after `lock'"));
4154 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4155 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4157 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4161 /* Check if HLE prefix is OK. */
4162 if (i
.hle_prefix
&& !check_hle ())
4165 /* Check BND prefix. */
4166 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4167 as_bad (_("expecting valid branch instruction after `bnd'"));
4169 /* Check NOTRACK prefix. */
4170 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4171 as_bad (_("expecting indirect branch instruction after `notrack'"));
4173 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4175 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4176 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4177 else if (flag_code
!= CODE_16BIT
4178 ? i
.prefix
[ADDR_PREFIX
]
4179 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4180 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4183 /* Insert BND prefix. */
4184 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4186 if (!i
.prefix
[BND_PREFIX
])
4187 add_prefix (BND_PREFIX_OPCODE
);
4188 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4190 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4191 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4195 /* Check string instruction segment overrides. */
4196 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4198 if (!check_string ())
4200 i
.disp_operands
= 0;
4203 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4204 optimize_encoding ();
4206 if (!process_suffix ())
4209 /* Update operand types. */
4210 for (j
= 0; j
< i
.operands
; j
++)
4211 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4213 /* Make still unresolved immediate matches conform to size of immediate
4214 given in i.suffix. */
4215 if (!finalize_imm ())
4218 if (i
.types
[0].bitfield
.imm1
)
4219 i
.imm_operands
= 0; /* kludge for shift insns. */
4221 /* We only need to check those implicit registers for instructions
4222 with 3 operands or less. */
4223 if (i
.operands
<= 3)
4224 for (j
= 0; j
< i
.operands
; j
++)
4225 if (i
.types
[j
].bitfield
.inoutportreg
4226 || i
.types
[j
].bitfield
.shiftcount
4227 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4230 /* ImmExt should be processed after SSE2AVX. */
4231 if (!i
.tm
.opcode_modifier
.sse2avx
4232 && i
.tm
.opcode_modifier
.immext
)
4235 /* For insns with operands there are more diddles to do to the opcode. */
4238 if (!process_operands ())
4241 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4243 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4244 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4247 if (is_any_vex_encoding (&i
.tm
))
4249 if (flag_code
== CODE_16BIT
)
4251 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4256 if (i
.tm
.opcode_modifier
.vex
)
4257 build_vex_prefix (t
);
4259 build_evex_prefix ();
4262 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4263 instructions may define INT_OPCODE as well, so avoid this corner
4264 case for those instructions that use MODRM. */
4265 if (i
.tm
.base_opcode
== INT_OPCODE
4266 && !i
.tm
.opcode_modifier
.modrm
4267 && i
.op
[0].imms
->X_add_number
== 3)
4269 i
.tm
.base_opcode
= INT3_OPCODE
;
4273 if ((i
.tm
.opcode_modifier
.jump
4274 || i
.tm
.opcode_modifier
.jumpbyte
4275 || i
.tm
.opcode_modifier
.jumpdword
)
4276 && i
.op
[0].disps
->X_op
== O_constant
)
4278 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4279 the absolute address given by the constant. Since ix86 jumps and
4280 calls are pc relative, we need to generate a reloc. */
4281 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4282 i
.op
[0].disps
->X_op
= O_symbol
;
4285 if (i
.tm
.opcode_modifier
.rex64
)
4288 /* For 8 bit registers we need an empty rex prefix. Also if the
4289 instruction already has a prefix, we need to convert old
4290 registers to new ones. */
4292 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4293 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4294 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4295 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4296 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4297 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4302 i
.rex
|= REX_OPCODE
;
4303 for (x
= 0; x
< 2; x
++)
4305 /* Look for 8 bit operand that uses old registers. */
4306 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4307 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4309 /* In case it is "hi" register, give up. */
4310 if (i
.op
[x
].regs
->reg_num
> 3)
4311 as_bad (_("can't encode register '%s%s' in an "
4312 "instruction requiring REX prefix."),
4313 register_prefix
, i
.op
[x
].regs
->reg_name
);
4315 /* Otherwise it is equivalent to the extended register.
4316 Since the encoding doesn't change this is merely
4317 cosmetic cleanup for debug output. */
4319 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4324 if (i
.rex
== 0 && i
.rex_encoding
)
4326 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4327 that uses legacy register. If it is "hi" register, don't add
4328 the REX_OPCODE byte. */
4330 for (x
= 0; x
< 2; x
++)
4331 if (i
.types
[x
].bitfield
.reg
4332 && i
.types
[x
].bitfield
.byte
4333 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4334 && i
.op
[x
].regs
->reg_num
> 3)
4336 i
.rex_encoding
= FALSE
;
4345 add_prefix (REX_OPCODE
| i
.rex
);
4347 /* We are ready to output the insn. */
4352 parse_insn (char *line
, char *mnemonic
)
4355 char *token_start
= l
;
4358 const insn_template
*t
;
4364 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4369 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4371 as_bad (_("no such instruction: `%s'"), token_start
);
4376 if (!is_space_char (*l
)
4377 && *l
!= END_OF_INSN
4379 || (*l
!= PREFIX_SEPARATOR
4382 as_bad (_("invalid character %s in mnemonic"),
4383 output_invalid (*l
));
4386 if (token_start
== l
)
4388 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4389 as_bad (_("expecting prefix; got nothing"));
4391 as_bad (_("expecting mnemonic; got nothing"));
4395 /* Look up instruction (or prefix) via hash table. */
4396 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4398 if (*l
!= END_OF_INSN
4399 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4400 && current_templates
4401 && current_templates
->start
->opcode_modifier
.isprefix
)
4403 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4405 as_bad ((flag_code
!= CODE_64BIT
4406 ? _("`%s' is only supported in 64-bit mode")
4407 : _("`%s' is not supported in 64-bit mode")),
4408 current_templates
->start
->name
);
4411 /* If we are in 16-bit mode, do not allow addr16 or data16.
4412 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4413 if ((current_templates
->start
->opcode_modifier
.size16
4414 || current_templates
->start
->opcode_modifier
.size32
)
4415 && flag_code
!= CODE_64BIT
4416 && (current_templates
->start
->opcode_modifier
.size32
4417 ^ (flag_code
== CODE_16BIT
)))
4419 as_bad (_("redundant %s prefix"),
4420 current_templates
->start
->name
);
4423 if (current_templates
->start
->opcode_length
== 0)
4425 /* Handle pseudo prefixes. */
4426 switch (current_templates
->start
->base_opcode
)
4430 i
.disp_encoding
= disp_encoding_8bit
;
4434 i
.disp_encoding
= disp_encoding_32bit
;
4438 i
.dir_encoding
= dir_encoding_load
;
4442 i
.dir_encoding
= dir_encoding_store
;
4446 i
.vec_encoding
= vex_encoding_vex2
;
4450 i
.vec_encoding
= vex_encoding_vex3
;
4454 i
.vec_encoding
= vex_encoding_evex
;
4458 i
.rex_encoding
= TRUE
;
4462 i
.no_optimize
= TRUE
;
4470 /* Add prefix, checking for repeated prefixes. */
4471 switch (add_prefix (current_templates
->start
->base_opcode
))
4476 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4477 i
.notrack_prefix
= current_templates
->start
->name
;
4480 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4481 i
.hle_prefix
= current_templates
->start
->name
;
4482 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4483 i
.bnd_prefix
= current_templates
->start
->name
;
4485 i
.rep_prefix
= current_templates
->start
->name
;
4491 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4498 if (!current_templates
)
4500 /* Check if we should swap operand or force 32bit displacement in
4502 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4503 i
.dir_encoding
= dir_encoding_store
;
4504 else if (mnem_p
- 3 == dot_p
4507 i
.disp_encoding
= disp_encoding_8bit
;
4508 else if (mnem_p
- 4 == dot_p
4512 i
.disp_encoding
= disp_encoding_32bit
;
4517 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4520 if (!current_templates
)
4523 /* See if we can get a match by trimming off a suffix. */
4526 case WORD_MNEM_SUFFIX
:
4527 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4528 i
.suffix
= SHORT_MNEM_SUFFIX
;
4531 case BYTE_MNEM_SUFFIX
:
4532 case QWORD_MNEM_SUFFIX
:
4533 i
.suffix
= mnem_p
[-1];
4535 current_templates
= (const templates
*) hash_find (op_hash
,
4538 case SHORT_MNEM_SUFFIX
:
4539 case LONG_MNEM_SUFFIX
:
4542 i
.suffix
= mnem_p
[-1];
4544 current_templates
= (const templates
*) hash_find (op_hash
,
4553 if (intel_float_operand (mnemonic
) == 1)
4554 i
.suffix
= SHORT_MNEM_SUFFIX
;
4556 i
.suffix
= LONG_MNEM_SUFFIX
;
4558 current_templates
= (const templates
*) hash_find (op_hash
,
4563 if (!current_templates
)
4565 as_bad (_("no such instruction: `%s'"), token_start
);
4570 if (current_templates
->start
->opcode_modifier
.jump
4571 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4573 /* Check for a branch hint. We allow ",pt" and ",pn" for
4574 predict taken and predict not taken respectively.
4575 I'm not sure that branch hints actually do anything on loop
4576 and jcxz insns (JumpByte) for current Pentium4 chips. They
4577 may work in the future and it doesn't hurt to accept them
4579 if (l
[0] == ',' && l
[1] == 'p')
4583 if (!add_prefix (DS_PREFIX_OPCODE
))
4587 else if (l
[2] == 'n')
4589 if (!add_prefix (CS_PREFIX_OPCODE
))
4595 /* Any other comma loses. */
4598 as_bad (_("invalid character %s in mnemonic"),
4599 output_invalid (*l
));
4603 /* Check if instruction is supported on specified architecture. */
4605 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4607 supported
|= cpu_flags_match (t
);
4608 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4610 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4611 as_warn (_("use .code16 to ensure correct addressing mode"));
4617 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4618 as_bad (flag_code
== CODE_64BIT
4619 ? _("`%s' is not supported in 64-bit mode")
4620 : _("`%s' is only supported in 64-bit mode"),
4621 current_templates
->start
->name
);
4623 as_bad (_("`%s' is not supported on `%s%s'"),
4624 current_templates
->start
->name
,
4625 cpu_arch_name
? cpu_arch_name
: default_arch
,
4626 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4632 parse_operands (char *l
, const char *mnemonic
)
4636 /* 1 if operand is pending after ','. */
4637 unsigned int expecting_operand
= 0;
4639 /* Non-zero if operand parens not balanced. */
4640 unsigned int paren_not_balanced
;
4642 while (*l
!= END_OF_INSN
)
4644 /* Skip optional white space before operand. */
4645 if (is_space_char (*l
))
4647 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4649 as_bad (_("invalid character %s before operand %d"),
4650 output_invalid (*l
),
4654 token_start
= l
; /* After white space. */
4655 paren_not_balanced
= 0;
4656 while (paren_not_balanced
|| *l
!= ',')
4658 if (*l
== END_OF_INSN
)
4660 if (paren_not_balanced
)
4663 as_bad (_("unbalanced parenthesis in operand %d."),
4666 as_bad (_("unbalanced brackets in operand %d."),
4671 break; /* we are done */
4673 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4675 as_bad (_("invalid character %s in operand %d"),
4676 output_invalid (*l
),
4683 ++paren_not_balanced
;
4685 --paren_not_balanced
;
4690 ++paren_not_balanced
;
4692 --paren_not_balanced
;
4696 if (l
!= token_start
)
4697 { /* Yes, we've read in another operand. */
4698 unsigned int operand_ok
;
4699 this_operand
= i
.operands
++;
4700 if (i
.operands
> MAX_OPERANDS
)
4702 as_bad (_("spurious operands; (%d operands/instruction max)"),
4706 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4707 /* Now parse operand adding info to 'i' as we go along. */
4708 END_STRING_AND_SAVE (l
);
4710 if (i
.mem_operands
> 1)
4712 as_bad (_("too many memory references for `%s'"),
4719 i386_intel_operand (token_start
,
4720 intel_float_operand (mnemonic
));
4722 operand_ok
= i386_att_operand (token_start
);
4724 RESTORE_END_STRING (l
);
4730 if (expecting_operand
)
4732 expecting_operand_after_comma
:
4733 as_bad (_("expecting operand after ','; got nothing"));
4738 as_bad (_("expecting operand before ','; got nothing"));
4743 /* Now *l must be either ',' or END_OF_INSN. */
4746 if (*++l
== END_OF_INSN
)
4748 /* Just skip it, if it's \n complain. */
4749 goto expecting_operand_after_comma
;
4751 expecting_operand
= 1;
4758 swap_2_operands (int xchg1
, int xchg2
)
4760 union i386_op temp_op
;
4761 i386_operand_type temp_type
;
4762 unsigned int temp_flags
;
4763 enum bfd_reloc_code_real temp_reloc
;
4765 temp_type
= i
.types
[xchg2
];
4766 i
.types
[xchg2
] = i
.types
[xchg1
];
4767 i
.types
[xchg1
] = temp_type
;
4769 temp_flags
= i
.flags
[xchg2
];
4770 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4771 i
.flags
[xchg1
] = temp_flags
;
4773 temp_op
= i
.op
[xchg2
];
4774 i
.op
[xchg2
] = i
.op
[xchg1
];
4775 i
.op
[xchg1
] = temp_op
;
4777 temp_reloc
= i
.reloc
[xchg2
];
4778 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4779 i
.reloc
[xchg1
] = temp_reloc
;
4783 if (i
.mask
->operand
== xchg1
)
4784 i
.mask
->operand
= xchg2
;
4785 else if (i
.mask
->operand
== xchg2
)
4786 i
.mask
->operand
= xchg1
;
4790 if (i
.broadcast
->operand
== xchg1
)
4791 i
.broadcast
->operand
= xchg2
;
4792 else if (i
.broadcast
->operand
== xchg2
)
4793 i
.broadcast
->operand
= xchg1
;
4797 if (i
.rounding
->operand
== xchg1
)
4798 i
.rounding
->operand
= xchg2
;
4799 else if (i
.rounding
->operand
== xchg2
)
4800 i
.rounding
->operand
= xchg1
;
4805 swap_operands (void)
4811 swap_2_operands (1, i
.operands
- 2);
4815 swap_2_operands (0, i
.operands
- 1);
4821 if (i
.mem_operands
== 2)
4823 const seg_entry
*temp_seg
;
4824 temp_seg
= i
.seg
[0];
4825 i
.seg
[0] = i
.seg
[1];
4826 i
.seg
[1] = temp_seg
;
4830 /* Try to ensure constant immediates are represented in the smallest
4835 char guess_suffix
= 0;
4839 guess_suffix
= i
.suffix
;
4840 else if (i
.reg_operands
)
4842 /* Figure out a suffix from the last register operand specified.
4843 We can't do this properly yet, ie. excluding InOutPortReg,
4844 but the following works for instructions with immediates.
4845 In any case, we can't set i.suffix yet. */
4846 for (op
= i
.operands
; --op
>= 0;)
4847 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4849 guess_suffix
= BYTE_MNEM_SUFFIX
;
4852 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4854 guess_suffix
= WORD_MNEM_SUFFIX
;
4857 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4859 guess_suffix
= LONG_MNEM_SUFFIX
;
4862 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4864 guess_suffix
= QWORD_MNEM_SUFFIX
;
4868 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4869 guess_suffix
= WORD_MNEM_SUFFIX
;
4871 for (op
= i
.operands
; --op
>= 0;)
4872 if (operand_type_check (i
.types
[op
], imm
))
4874 switch (i
.op
[op
].imms
->X_op
)
4877 /* If a suffix is given, this operand may be shortened. */
4878 switch (guess_suffix
)
4880 case LONG_MNEM_SUFFIX
:
4881 i
.types
[op
].bitfield
.imm32
= 1;
4882 i
.types
[op
].bitfield
.imm64
= 1;
4884 case WORD_MNEM_SUFFIX
:
4885 i
.types
[op
].bitfield
.imm16
= 1;
4886 i
.types
[op
].bitfield
.imm32
= 1;
4887 i
.types
[op
].bitfield
.imm32s
= 1;
4888 i
.types
[op
].bitfield
.imm64
= 1;
4890 case BYTE_MNEM_SUFFIX
:
4891 i
.types
[op
].bitfield
.imm8
= 1;
4892 i
.types
[op
].bitfield
.imm8s
= 1;
4893 i
.types
[op
].bitfield
.imm16
= 1;
4894 i
.types
[op
].bitfield
.imm32
= 1;
4895 i
.types
[op
].bitfield
.imm32s
= 1;
4896 i
.types
[op
].bitfield
.imm64
= 1;
4900 /* If this operand is at most 16 bits, convert it
4901 to a signed 16 bit number before trying to see
4902 whether it will fit in an even smaller size.
4903 This allows a 16-bit operand such as $0xffe0 to
4904 be recognised as within Imm8S range. */
4905 if ((i
.types
[op
].bitfield
.imm16
)
4906 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4908 i
.op
[op
].imms
->X_add_number
=
4909 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4912 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4913 if ((i
.types
[op
].bitfield
.imm32
)
4914 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4917 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4918 ^ ((offsetT
) 1 << 31))
4919 - ((offsetT
) 1 << 31));
4923 = operand_type_or (i
.types
[op
],
4924 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4926 /* We must avoid matching of Imm32 templates when 64bit
4927 only immediate is available. */
4928 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4929 i
.types
[op
].bitfield
.imm32
= 0;
4936 /* Symbols and expressions. */
4938 /* Convert symbolic operand to proper sizes for matching, but don't
4939 prevent matching a set of insns that only supports sizes other
4940 than those matching the insn suffix. */
4942 i386_operand_type mask
, allowed
;
4943 const insn_template
*t
;
4945 operand_type_set (&mask
, 0);
4946 operand_type_set (&allowed
, 0);
4948 for (t
= current_templates
->start
;
4949 t
< current_templates
->end
;
4951 allowed
= operand_type_or (allowed
,
4952 t
->operand_types
[op
]);
4953 switch (guess_suffix
)
4955 case QWORD_MNEM_SUFFIX
:
4956 mask
.bitfield
.imm64
= 1;
4957 mask
.bitfield
.imm32s
= 1;
4959 case LONG_MNEM_SUFFIX
:
4960 mask
.bitfield
.imm32
= 1;
4962 case WORD_MNEM_SUFFIX
:
4963 mask
.bitfield
.imm16
= 1;
4965 case BYTE_MNEM_SUFFIX
:
4966 mask
.bitfield
.imm8
= 1;
4971 allowed
= operand_type_and (mask
, allowed
);
4972 if (!operand_type_all_zero (&allowed
))
4973 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4980 /* Try to use the smallest displacement type too. */
4982 optimize_disp (void)
4986 for (op
= i
.operands
; --op
>= 0;)
4987 if (operand_type_check (i
.types
[op
], disp
))
4989 if (i
.op
[op
].disps
->X_op
== O_constant
)
4991 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4993 if (i
.types
[op
].bitfield
.disp16
4994 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4996 /* If this operand is at most 16 bits, convert
4997 to a signed 16 bit number and don't use 64bit
4999 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5000 i
.types
[op
].bitfield
.disp64
= 0;
5003 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5004 if (i
.types
[op
].bitfield
.disp32
5005 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5007 /* If this operand is at most 32 bits, convert
5008 to a signed 32 bit number and don't use 64bit
5010 op_disp
&= (((offsetT
) 2 << 31) - 1);
5011 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5012 i
.types
[op
].bitfield
.disp64
= 0;
5015 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5017 i
.types
[op
].bitfield
.disp8
= 0;
5018 i
.types
[op
].bitfield
.disp16
= 0;
5019 i
.types
[op
].bitfield
.disp32
= 0;
5020 i
.types
[op
].bitfield
.disp32s
= 0;
5021 i
.types
[op
].bitfield
.disp64
= 0;
5025 else if (flag_code
== CODE_64BIT
)
5027 if (fits_in_signed_long (op_disp
))
5029 i
.types
[op
].bitfield
.disp64
= 0;
5030 i
.types
[op
].bitfield
.disp32s
= 1;
5032 if (i
.prefix
[ADDR_PREFIX
]
5033 && fits_in_unsigned_long (op_disp
))
5034 i
.types
[op
].bitfield
.disp32
= 1;
5036 if ((i
.types
[op
].bitfield
.disp32
5037 || i
.types
[op
].bitfield
.disp32s
5038 || i
.types
[op
].bitfield
.disp16
)
5039 && fits_in_disp8 (op_disp
))
5040 i
.types
[op
].bitfield
.disp8
= 1;
5042 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5043 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5045 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5046 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5047 i
.types
[op
].bitfield
.disp8
= 0;
5048 i
.types
[op
].bitfield
.disp16
= 0;
5049 i
.types
[op
].bitfield
.disp32
= 0;
5050 i
.types
[op
].bitfield
.disp32s
= 0;
5051 i
.types
[op
].bitfield
.disp64
= 0;
5054 /* We only support 64bit displacement on constants. */
5055 i
.types
[op
].bitfield
.disp64
= 0;
5059 /* Return 1 if there is a match in broadcast bytes between operand
5060 GIVEN and instruction template T. */
5063 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5065 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5066 && i
.types
[given
].bitfield
.byte
)
5067 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5068 && i
.types
[given
].bitfield
.word
)
5069 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5070 && i
.types
[given
].bitfield
.dword
)
5071 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5072 && i
.types
[given
].bitfield
.qword
));
5075 /* Check if operands are valid for the instruction. */
5078 check_VecOperands (const insn_template
*t
)
5082 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5084 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5085 any one operand are implicity requiring AVX512VL support if the actual
5086 operand size is YMMword or XMMword. Since this function runs after
5087 template matching, there's no need to check for YMMword/XMMword in
5089 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5090 if (!cpu_flags_all_zero (&cpu
)
5091 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5092 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5094 for (op
= 0; op
< t
->operands
; ++op
)
5096 if (t
->operand_types
[op
].bitfield
.zmmword
5097 && (i
.types
[op
].bitfield
.ymmword
5098 || i
.types
[op
].bitfield
.xmmword
))
5100 i
.error
= unsupported
;
5106 /* Without VSIB byte, we can't have a vector register for index. */
5107 if (!t
->opcode_modifier
.vecsib
5109 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5110 || i
.index_reg
->reg_type
.bitfield
.ymmword
5111 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5113 i
.error
= unsupported_vector_index_register
;
5117 /* Check if default mask is allowed. */
5118 if (t
->opcode_modifier
.nodefmask
5119 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5121 i
.error
= no_default_mask
;
5125 /* For VSIB byte, we need a vector register for index, and all vector
5126 registers must be distinct. */
5127 if (t
->opcode_modifier
.vecsib
)
5130 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5131 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5132 || (t
->opcode_modifier
.vecsib
== VecSIB256
5133 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5134 || (t
->opcode_modifier
.vecsib
== VecSIB512
5135 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5137 i
.error
= invalid_vsib_address
;
5141 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5142 if (i
.reg_operands
== 2 && !i
.mask
)
5144 gas_assert (i
.types
[0].bitfield
.regsimd
);
5145 gas_assert (i
.types
[0].bitfield
.xmmword
5146 || i
.types
[0].bitfield
.ymmword
);
5147 gas_assert (i
.types
[2].bitfield
.regsimd
);
5148 gas_assert (i
.types
[2].bitfield
.xmmword
5149 || i
.types
[2].bitfield
.ymmword
);
5150 if (operand_check
== check_none
)
5152 if (register_number (i
.op
[0].regs
)
5153 != register_number (i
.index_reg
)
5154 && register_number (i
.op
[2].regs
)
5155 != register_number (i
.index_reg
)
5156 && register_number (i
.op
[0].regs
)
5157 != register_number (i
.op
[2].regs
))
5159 if (operand_check
== check_error
)
5161 i
.error
= invalid_vector_register_set
;
5164 as_warn (_("mask, index, and destination registers should be distinct"));
5166 else if (i
.reg_operands
== 1 && i
.mask
)
5168 if (i
.types
[1].bitfield
.regsimd
5169 && (i
.types
[1].bitfield
.xmmword
5170 || i
.types
[1].bitfield
.ymmword
5171 || i
.types
[1].bitfield
.zmmword
)
5172 && (register_number (i
.op
[1].regs
)
5173 == register_number (i
.index_reg
)))
5175 if (operand_check
== check_error
)
5177 i
.error
= invalid_vector_register_set
;
5180 if (operand_check
!= check_none
)
5181 as_warn (_("index and destination registers should be distinct"));
5186 /* Check if broadcast is supported by the instruction and is applied
5187 to the memory operand. */
5190 i386_operand_type type
, overlap
;
5192 /* Check if specified broadcast is supported in this instruction,
5193 and its broadcast bytes match the memory operand. */
5194 op
= i
.broadcast
->operand
;
5195 if (!t
->opcode_modifier
.broadcast
5196 || !(i
.flags
[op
] & Operand_Mem
)
5197 || (!i
.types
[op
].bitfield
.unspecified
5198 && !match_broadcast_size (t
, op
)))
5201 i
.error
= unsupported_broadcast
;
5205 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5206 * i
.broadcast
->type
);
5207 operand_type_set (&type
, 0);
5208 switch (i
.broadcast
->bytes
)
5211 type
.bitfield
.word
= 1;
5214 type
.bitfield
.dword
= 1;
5217 type
.bitfield
.qword
= 1;
5220 type
.bitfield
.xmmword
= 1;
5223 type
.bitfield
.ymmword
= 1;
5226 type
.bitfield
.zmmword
= 1;
5232 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5233 if (operand_type_all_zero (&overlap
))
5236 if (t
->opcode_modifier
.checkregsize
)
5240 type
.bitfield
.baseindex
= 1;
5241 for (j
= 0; j
< i
.operands
; ++j
)
5244 && !operand_type_register_match(i
.types
[j
],
5245 t
->operand_types
[j
],
5247 t
->operand_types
[op
]))
5252 /* If broadcast is supported in this instruction, we need to check if
5253 operand of one-element size isn't specified without broadcast. */
5254 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5256 /* Find memory operand. */
5257 for (op
= 0; op
< i
.operands
; op
++)
5258 if (operand_type_check (i
.types
[op
], anymem
))
5260 gas_assert (op
< i
.operands
);
5261 /* Check size of the memory operand. */
5262 if (match_broadcast_size (t
, op
))
5264 i
.error
= broadcast_needed
;
5269 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5271 /* Check if requested masking is supported. */
5274 switch (t
->opcode_modifier
.masking
)
5278 case MERGING_MASKING
:
5279 if (i
.mask
->zeroing
)
5282 i
.error
= unsupported_masking
;
5286 case DYNAMIC_MASKING
:
5287 /* Memory destinations allow only merging masking. */
5288 if (i
.mask
->zeroing
&& i
.mem_operands
)
5290 /* Find memory operand. */
5291 for (op
= 0; op
< i
.operands
; op
++)
5292 if (i
.flags
[op
] & Operand_Mem
)
5294 gas_assert (op
< i
.operands
);
5295 if (op
== i
.operands
- 1)
5297 i
.error
= unsupported_masking
;
5307 /* Check if masking is applied to dest operand. */
5308 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5310 i
.error
= mask_not_on_destination
;
5317 if ((i
.rounding
->type
!= saeonly
5318 && !t
->opcode_modifier
.staticrounding
)
5319 || (i
.rounding
->type
== saeonly
5320 && (t
->opcode_modifier
.staticrounding
5321 || !t
->opcode_modifier
.sae
)))
5323 i
.error
= unsupported_rc_sae
;
5326 /* If the instruction has several immediate operands and one of
5327 them is rounding, the rounding operand should be the last
5328 immediate operand. */
5329 if (i
.imm_operands
> 1
5330 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5332 i
.error
= rc_sae_operand_not_last_imm
;
5337 /* Check vector Disp8 operand. */
5338 if (t
->opcode_modifier
.disp8memshift
5339 && i
.disp_encoding
!= disp_encoding_32bit
)
5342 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5343 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5344 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5347 const i386_operand_type
*type
= NULL
;
5350 for (op
= 0; op
< i
.operands
; op
++)
5351 if (operand_type_check (i
.types
[op
], anymem
))
5353 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5354 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5355 else if (t
->operand_types
[op
].bitfield
.xmmword
5356 + t
->operand_types
[op
].bitfield
.ymmword
5357 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5358 type
= &t
->operand_types
[op
];
5359 else if (!i
.types
[op
].bitfield
.unspecified
)
5360 type
= &i
.types
[op
];
5362 else if (i
.types
[op
].bitfield
.regsimd
5363 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5365 if (i
.types
[op
].bitfield
.zmmword
)
5367 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5369 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5375 if (type
->bitfield
.zmmword
)
5377 else if (type
->bitfield
.ymmword
)
5379 else if (type
->bitfield
.xmmword
)
5383 /* For the check in fits_in_disp8(). */
5384 if (i
.memshift
== 0)
5388 for (op
= 0; op
< i
.operands
; op
++)
5389 if (operand_type_check (i
.types
[op
], disp
)
5390 && i
.op
[op
].disps
->X_op
== O_constant
)
5392 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5394 i
.types
[op
].bitfield
.disp8
= 1;
5397 i
.types
[op
].bitfield
.disp8
= 0;
5406 /* Check if operands are valid for the instruction. Update VEX
5410 VEX_check_operands (const insn_template
*t
)
5412 if (i
.vec_encoding
== vex_encoding_evex
)
5414 /* This instruction must be encoded with EVEX prefix. */
5415 if (!is_evex_encoding (t
))
5417 i
.error
= unsupported
;
5423 if (!t
->opcode_modifier
.vex
)
5425 /* This instruction template doesn't have VEX prefix. */
5426 if (i
.vec_encoding
!= vex_encoding_default
)
5428 i
.error
= unsupported
;
5434 /* Only check VEX_Imm4, which must be the first operand. */
5435 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5437 if (i
.op
[0].imms
->X_op
!= O_constant
5438 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5444 /* Turn off Imm8 so that update_imm won't complain. */
5445 i
.types
[0] = vec_imm4
;
5451 static const insn_template
*
5452 match_template (char mnem_suffix
)
5454 /* Points to template once we've found it. */
5455 const insn_template
*t
;
5456 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5457 i386_operand_type overlap4
;
5458 unsigned int found_reverse_match
;
5459 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5460 i386_operand_type operand_types
[MAX_OPERANDS
];
5461 int addr_prefix_disp
;
5463 unsigned int found_cpu_match
, size_match
;
5464 unsigned int check_register
;
5465 enum i386_error specific_error
= 0;
5467 #if MAX_OPERANDS != 5
5468 # error "MAX_OPERANDS must be 5."
5471 found_reverse_match
= 0;
5472 addr_prefix_disp
= -1;
5474 memset (&suffix_check
, 0, sizeof (suffix_check
));
5475 if (intel_syntax
&& i
.broadcast
)
5477 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5478 suffix_check
.no_bsuf
= 1;
5479 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5480 suffix_check
.no_wsuf
= 1;
5481 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5482 suffix_check
.no_ssuf
= 1;
5483 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5484 suffix_check
.no_lsuf
= 1;
5485 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5486 suffix_check
.no_qsuf
= 1;
5487 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5488 suffix_check
.no_ldsuf
= 1;
5490 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5493 switch (mnem_suffix
)
5495 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5496 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5497 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5498 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5499 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5503 /* Must have right number of operands. */
5504 i
.error
= number_of_operands_mismatch
;
5506 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5508 addr_prefix_disp
= -1;
5510 if (i
.operands
!= t
->operands
)
5513 /* Check processor support. */
5514 i
.error
= unsupported
;
5515 found_cpu_match
= (cpu_flags_match (t
)
5516 == CPU_FLAGS_PERFECT_MATCH
);
5517 if (!found_cpu_match
)
5520 /* Check AT&T mnemonic. */
5521 i
.error
= unsupported_with_intel_mnemonic
;
5522 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5525 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5526 i
.error
= unsupported_syntax
;
5527 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5528 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5529 || (intel64
&& t
->opcode_modifier
.amd64
)
5530 || (!intel64
&& t
->opcode_modifier
.intel64
))
5533 /* Check the suffix, except for some instructions in intel mode. */
5534 i
.error
= invalid_instruction_suffix
;
5535 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5536 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5537 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5538 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5539 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5540 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5541 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5543 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5544 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5545 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5546 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5547 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5548 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5549 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5552 size_match
= operand_size_match (t
);
5556 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5557 operand_types
[j
] = t
->operand_types
[j
];
5559 /* In general, don't allow 64-bit operands in 32-bit mode. */
5560 if (i
.suffix
== QWORD_MNEM_SUFFIX
5561 && flag_code
!= CODE_64BIT
5563 ? (!t
->opcode_modifier
.ignoresize
5564 && !t
->opcode_modifier
.broadcast
5565 && !intel_float_operand (t
->name
))
5566 : intel_float_operand (t
->name
) != 2)
5567 && ((!operand_types
[0].bitfield
.regmmx
5568 && !operand_types
[0].bitfield
.regsimd
)
5569 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5570 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5571 && (t
->base_opcode
!= 0x0fc7
5572 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5575 /* In general, don't allow 32-bit operands on pre-386. */
5576 else if (i
.suffix
== LONG_MNEM_SUFFIX
5577 && !cpu_arch_flags
.bitfield
.cpui386
5579 ? (!t
->opcode_modifier
.ignoresize
5580 && !intel_float_operand (t
->name
))
5581 : intel_float_operand (t
->name
) != 2)
5582 && ((!operand_types
[0].bitfield
.regmmx
5583 && !operand_types
[0].bitfield
.regsimd
)
5584 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5585 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5588 /* Do not verify operands when there are none. */
5592 /* We've found a match; break out of loop. */
5596 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5597 into Disp32/Disp16/Disp32 operand. */
5598 if (i
.prefix
[ADDR_PREFIX
] != 0)
5600 /* There should be only one Disp operand. */
5604 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5606 if (operand_types
[j
].bitfield
.disp16
)
5608 addr_prefix_disp
= j
;
5609 operand_types
[j
].bitfield
.disp32
= 1;
5610 operand_types
[j
].bitfield
.disp16
= 0;
5616 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5618 if (operand_types
[j
].bitfield
.disp32
)
5620 addr_prefix_disp
= j
;
5621 operand_types
[j
].bitfield
.disp32
= 0;
5622 operand_types
[j
].bitfield
.disp16
= 1;
5628 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5630 if (operand_types
[j
].bitfield
.disp64
)
5632 addr_prefix_disp
= j
;
5633 operand_types
[j
].bitfield
.disp64
= 0;
5634 operand_types
[j
].bitfield
.disp32
= 1;
5642 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5643 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5646 /* We check register size if needed. */
5647 if (t
->opcode_modifier
.checkregsize
)
5649 check_register
= (1 << t
->operands
) - 1;
5651 check_register
&= ~(1 << i
.broadcast
->operand
);
5656 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5657 switch (t
->operands
)
5660 if (!operand_type_match (overlap0
, i
.types
[0]))
5664 /* xchg %eax, %eax is a special case. It is an alias for nop
5665 only in 32bit mode and we can use opcode 0x90. In 64bit
5666 mode, we can't use 0x90 for xchg %eax, %eax since it should
5667 zero-extend %eax to %rax. */
5668 if (flag_code
== CODE_64BIT
5669 && t
->base_opcode
== 0x90
5670 && operand_type_equal (&i
.types
[0], &acc32
)
5671 && operand_type_equal (&i
.types
[1], &acc32
))
5673 /* xrelease mov %eax, <disp> is another special case. It must not
5674 match the accumulator-only encoding of mov. */
5675 if (flag_code
!= CODE_64BIT
5677 && t
->base_opcode
== 0xa0
5678 && i
.types
[0].bitfield
.acc
5679 && operand_type_check (i
.types
[1], anymem
))
5681 if (!(size_match
& MATCH_STRAIGHT
))
5683 /* If we want store form, we reverse direction of operands. */
5684 if (i
.dir_encoding
== dir_encoding_store
5685 && t
->opcode_modifier
.d
)
5690 /* If we want store form, we skip the current load. */
5691 if (i
.dir_encoding
== dir_encoding_store
5692 && i
.mem_operands
== 0
5693 && t
->opcode_modifier
.load
)
5698 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5699 if (!operand_type_match (overlap0
, i
.types
[0])
5700 || !operand_type_match (overlap1
, i
.types
[1])
5701 || ((check_register
& 3) == 3
5702 && !operand_type_register_match (i
.types
[0],
5707 /* Check if other direction is valid ... */
5708 if (!t
->opcode_modifier
.d
)
5712 if (!(size_match
& MATCH_REVERSE
))
5714 /* Try reversing direction of operands. */
5715 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5716 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5717 if (!operand_type_match (overlap0
, i
.types
[0])
5718 || !operand_type_match (overlap1
, i
.types
[1])
5720 && !operand_type_register_match (i
.types
[0],
5725 /* Does not match either direction. */
5728 /* found_reverse_match holds which of D or FloatR
5730 if (!t
->opcode_modifier
.d
)
5731 found_reverse_match
= 0;
5732 else if (operand_types
[0].bitfield
.tbyte
)
5733 found_reverse_match
= Opcode_FloatD
;
5735 found_reverse_match
= Opcode_D
;
5736 if (t
->opcode_modifier
.floatr
)
5737 found_reverse_match
|= Opcode_FloatR
;
5741 /* Found a forward 2 operand match here. */
5742 switch (t
->operands
)
5745 overlap4
= operand_type_and (i
.types
[4],
5749 overlap3
= operand_type_and (i
.types
[3],
5753 overlap2
= operand_type_and (i
.types
[2],
5758 switch (t
->operands
)
5761 if (!operand_type_match (overlap4
, i
.types
[4])
5762 || !operand_type_register_match (i
.types
[3],
5769 if (!operand_type_match (overlap3
, i
.types
[3])
5770 || ((check_register
& 0xa) == 0xa
5771 && !operand_type_register_match (i
.types
[1],
5775 || ((check_register
& 0xc) == 0xc
5776 && !operand_type_register_match (i
.types
[2],
5783 /* Here we make use of the fact that there are no
5784 reverse match 3 operand instructions. */
5785 if (!operand_type_match (overlap2
, i
.types
[2])
5786 || ((check_register
& 5) == 5
5787 && !operand_type_register_match (i
.types
[0],
5791 || ((check_register
& 6) == 6
5792 && !operand_type_register_match (i
.types
[1],
5800 /* Found either forward/reverse 2, 3 or 4 operand match here:
5801 slip through to break. */
5803 if (!found_cpu_match
)
5805 found_reverse_match
= 0;
5809 /* Check if vector and VEX operands are valid. */
5810 if (check_VecOperands (t
) || VEX_check_operands (t
))
5812 specific_error
= i
.error
;
5816 /* We've found a match; break out of loop. */
5820 if (t
== current_templates
->end
)
5822 /* We found no match. */
5823 const char *err_msg
;
5824 switch (specific_error
? specific_error
: i
.error
)
5828 case operand_size_mismatch
:
5829 err_msg
= _("operand size mismatch");
5831 case operand_type_mismatch
:
5832 err_msg
= _("operand type mismatch");
5834 case register_type_mismatch
:
5835 err_msg
= _("register type mismatch");
5837 case number_of_operands_mismatch
:
5838 err_msg
= _("number of operands mismatch");
5840 case invalid_instruction_suffix
:
5841 err_msg
= _("invalid instruction suffix");
5844 err_msg
= _("constant doesn't fit in 4 bits");
5846 case unsupported_with_intel_mnemonic
:
5847 err_msg
= _("unsupported with Intel mnemonic");
5849 case unsupported_syntax
:
5850 err_msg
= _("unsupported syntax");
5853 as_bad (_("unsupported instruction `%s'"),
5854 current_templates
->start
->name
);
5856 case invalid_vsib_address
:
5857 err_msg
= _("invalid VSIB address");
5859 case invalid_vector_register_set
:
5860 err_msg
= _("mask, index, and destination registers must be distinct");
5862 case unsupported_vector_index_register
:
5863 err_msg
= _("unsupported vector index register");
5865 case unsupported_broadcast
:
5866 err_msg
= _("unsupported broadcast");
5868 case broadcast_needed
:
5869 err_msg
= _("broadcast is needed for operand of such type");
5871 case unsupported_masking
:
5872 err_msg
= _("unsupported masking");
5874 case mask_not_on_destination
:
5875 err_msg
= _("mask not on destination operand");
5877 case no_default_mask
:
5878 err_msg
= _("default mask isn't allowed");
5880 case unsupported_rc_sae
:
5881 err_msg
= _("unsupported static rounding/sae");
5883 case rc_sae_operand_not_last_imm
:
5885 err_msg
= _("RC/SAE operand must precede immediate operands");
5887 err_msg
= _("RC/SAE operand must follow immediate operands");
5889 case invalid_register_operand
:
5890 err_msg
= _("invalid register operand");
5893 as_bad (_("%s for `%s'"), err_msg
,
5894 current_templates
->start
->name
);
5898 if (!quiet_warnings
)
5901 && (i
.types
[0].bitfield
.jumpabsolute
5902 != operand_types
[0].bitfield
.jumpabsolute
))
5904 as_warn (_("indirect %s without `*'"), t
->name
);
5907 if (t
->opcode_modifier
.isprefix
5908 && t
->opcode_modifier
.ignoresize
)
5910 /* Warn them that a data or address size prefix doesn't
5911 affect assembly of the next line of code. */
5912 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5916 /* Copy the template we found. */
5919 if (addr_prefix_disp
!= -1)
5920 i
.tm
.operand_types
[addr_prefix_disp
]
5921 = operand_types
[addr_prefix_disp
];
5923 if (found_reverse_match
)
5925 /* If we found a reverse match we must alter the opcode
5926 direction bit. found_reverse_match holds bits to change
5927 (different for int & float insns). */
5929 i
.tm
.base_opcode
^= found_reverse_match
;
5931 i
.tm
.operand_types
[0] = operand_types
[1];
5932 i
.tm
.operand_types
[1] = operand_types
[0];
5941 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5942 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5944 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5946 as_bad (_("`%s' operand %d must use `%ses' segment"),
5952 /* There's only ever one segment override allowed per instruction.
5953 This instruction possibly has a legal segment override on the
5954 second operand, so copy the segment to where non-string
5955 instructions store it, allowing common code. */
5956 i
.seg
[0] = i
.seg
[1];
5958 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5960 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5962 as_bad (_("`%s' operand %d must use `%ses' segment"),
5973 process_suffix (void)
5975 /* If matched instruction specifies an explicit instruction mnemonic
5977 if (i
.tm
.opcode_modifier
.size16
)
5978 i
.suffix
= WORD_MNEM_SUFFIX
;
5979 else if (i
.tm
.opcode_modifier
.size32
)
5980 i
.suffix
= LONG_MNEM_SUFFIX
;
5981 else if (i
.tm
.opcode_modifier
.size64
)
5982 i
.suffix
= QWORD_MNEM_SUFFIX
;
5983 else if (i
.reg_operands
)
5985 /* If there's no instruction mnemonic suffix we try to invent one
5986 based on register operands. */
5989 /* We take i.suffix from the last register operand specified,
5990 Destination register type is more significant than source
5991 register type. crc32 in SSE4.2 prefers source register
5993 if (i
.tm
.base_opcode
== 0xf20f38f1)
5995 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5996 i
.suffix
= WORD_MNEM_SUFFIX
;
5997 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5998 i
.suffix
= LONG_MNEM_SUFFIX
;
5999 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
6000 i
.suffix
= QWORD_MNEM_SUFFIX
;
6002 else if (i
.tm
.base_opcode
== 0xf20f38f0)
6004 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
6005 i
.suffix
= BYTE_MNEM_SUFFIX
;
6012 if (i
.tm
.base_opcode
== 0xf20f38f1
6013 || i
.tm
.base_opcode
== 0xf20f38f0)
6015 /* We have to know the operand size for crc32. */
6016 as_bad (_("ambiguous memory operand size for `%s`"),
6021 for (op
= i
.operands
; --op
>= 0;)
6022 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6023 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6025 if (!i
.types
[op
].bitfield
.reg
)
6027 if (i
.types
[op
].bitfield
.byte
)
6028 i
.suffix
= BYTE_MNEM_SUFFIX
;
6029 else if (i
.types
[op
].bitfield
.word
)
6030 i
.suffix
= WORD_MNEM_SUFFIX
;
6031 else if (i
.types
[op
].bitfield
.dword
)
6032 i
.suffix
= LONG_MNEM_SUFFIX
;
6033 else if (i
.types
[op
].bitfield
.qword
)
6034 i
.suffix
= QWORD_MNEM_SUFFIX
;
6041 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6044 && i
.tm
.opcode_modifier
.ignoresize
6045 && i
.tm
.opcode_modifier
.no_bsuf
)
6047 else if (!check_byte_reg ())
6050 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6053 && i
.tm
.opcode_modifier
.ignoresize
6054 && i
.tm
.opcode_modifier
.no_lsuf
6055 && !i
.tm
.opcode_modifier
.todword
6056 && !i
.tm
.opcode_modifier
.toqword
)
6058 else if (!check_long_reg ())
6061 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6064 && i
.tm
.opcode_modifier
.ignoresize
6065 && i
.tm
.opcode_modifier
.no_qsuf
6066 && !i
.tm
.opcode_modifier
.todword
6067 && !i
.tm
.opcode_modifier
.toqword
)
6069 else if (!check_qword_reg ())
6072 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6075 && i
.tm
.opcode_modifier
.ignoresize
6076 && i
.tm
.opcode_modifier
.no_wsuf
)
6078 else if (!check_word_reg ())
6081 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6082 /* Do nothing if the instruction is going to ignore the prefix. */
6087 else if (i
.tm
.opcode_modifier
.defaultsize
6089 /* exclude fldenv/frstor/fsave/fstenv */
6090 && i
.tm
.opcode_modifier
.no_ssuf
)
6092 i
.suffix
= stackop_size
;
6094 else if (intel_syntax
6096 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6097 || i
.tm
.opcode_modifier
.jumpbyte
6098 || i
.tm
.opcode_modifier
.jumpintersegment
6099 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6100 && i
.tm
.extension_opcode
<= 3)))
6105 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6107 i
.suffix
= QWORD_MNEM_SUFFIX
;
6112 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6113 i
.suffix
= LONG_MNEM_SUFFIX
;
6116 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6117 i
.suffix
= WORD_MNEM_SUFFIX
;
6126 if (i
.tm
.opcode_modifier
.w
)
6128 as_bad (_("no instruction mnemonic suffix given and "
6129 "no register operands; can't size instruction"));
6135 unsigned int suffixes
;
6137 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6138 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6140 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6142 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6144 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6146 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6149 /* There are more than suffix matches. */
6150 if (i
.tm
.opcode_modifier
.w
6151 || ((suffixes
& (suffixes
- 1))
6152 && !i
.tm
.opcode_modifier
.defaultsize
6153 && !i
.tm
.opcode_modifier
.ignoresize
))
6155 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6161 /* Change the opcode based on the operand size given by i.suffix. */
6164 /* Size floating point instruction. */
6165 case LONG_MNEM_SUFFIX
:
6166 if (i
.tm
.opcode_modifier
.floatmf
)
6168 i
.tm
.base_opcode
^= 4;
6172 case WORD_MNEM_SUFFIX
:
6173 case QWORD_MNEM_SUFFIX
:
6174 /* It's not a byte, select word/dword operation. */
6175 if (i
.tm
.opcode_modifier
.w
)
6177 if (i
.tm
.opcode_modifier
.shortform
)
6178 i
.tm
.base_opcode
|= 8;
6180 i
.tm
.base_opcode
|= 1;
6183 case SHORT_MNEM_SUFFIX
:
6184 /* Now select between word & dword operations via the operand
6185 size prefix, except for instructions that will ignore this
6187 if (i
.reg_operands
> 0
6188 && i
.types
[0].bitfield
.reg
6189 && i
.tm
.opcode_modifier
.addrprefixopreg
6190 && (i
.tm
.opcode_modifier
.immext
6191 || i
.operands
== 1))
6193 /* The address size override prefix changes the size of the
6195 if ((flag_code
== CODE_32BIT
6196 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6197 || (flag_code
!= CODE_32BIT
6198 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6199 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6202 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6203 && !i
.tm
.opcode_modifier
.ignoresize
6204 && !i
.tm
.opcode_modifier
.floatmf
6205 && !i
.tm
.opcode_modifier
.vex
6206 && !i
.tm
.opcode_modifier
.vexopcode
6207 && !is_evex_encoding (&i
.tm
)
6208 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6209 || (flag_code
== CODE_64BIT
6210 && i
.tm
.opcode_modifier
.jumpbyte
)))
6212 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6214 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6215 prefix
= ADDR_PREFIX_OPCODE
;
6217 if (!add_prefix (prefix
))
6221 /* Set mode64 for an operand. */
6222 if (i
.suffix
== QWORD_MNEM_SUFFIX
6223 && flag_code
== CODE_64BIT
6224 && !i
.tm
.opcode_modifier
.norex64
6225 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6227 && ! (i
.operands
== 2
6228 && i
.tm
.base_opcode
== 0x90
6229 && i
.tm
.extension_opcode
== None
6230 && operand_type_equal (&i
.types
[0], &acc64
)
6231 && operand_type_equal (&i
.types
[1], &acc64
)))
6237 if (i
.reg_operands
!= 0
6239 && i
.tm
.opcode_modifier
.addrprefixopreg
6240 && !i
.tm
.opcode_modifier
.immext
)
6242 /* Check invalid register operand when the address size override
6243 prefix changes the size of register operands. */
6245 enum { need_word
, need_dword
, need_qword
} need
;
6247 if (flag_code
== CODE_32BIT
)
6248 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6251 if (i
.prefix
[ADDR_PREFIX
])
6254 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6257 for (op
= 0; op
< i
.operands
; op
++)
6258 if (i
.types
[op
].bitfield
.reg
6259 && ((need
== need_word
6260 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6261 || (need
== need_dword
6262 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6263 || (need
== need_qword
6264 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6266 as_bad (_("invalid register operand size for `%s'"),
6276 check_byte_reg (void)
6280 for (op
= i
.operands
; --op
>= 0;)
6282 /* Skip non-register operands. */
6283 if (!i
.types
[op
].bitfield
.reg
)
6286 /* If this is an eight bit register, it's OK. If it's the 16 or
6287 32 bit version of an eight bit register, we will just use the
6288 low portion, and that's OK too. */
6289 if (i
.types
[op
].bitfield
.byte
)
6292 /* I/O port address operands are OK too. */
6293 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6296 /* crc32 doesn't generate this warning. */
6297 if (i
.tm
.base_opcode
== 0xf20f38f0)
6300 if ((i
.types
[op
].bitfield
.word
6301 || i
.types
[op
].bitfield
.dword
6302 || i
.types
[op
].bitfield
.qword
)
6303 && i
.op
[op
].regs
->reg_num
< 4
6304 /* Prohibit these changes in 64bit mode, since the lowering
6305 would be more complicated. */
6306 && flag_code
!= CODE_64BIT
)
6308 #if REGISTER_WARNINGS
6309 if (!quiet_warnings
)
6310 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6312 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6313 ? REGNAM_AL
- REGNAM_AX
6314 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6316 i
.op
[op
].regs
->reg_name
,
6321 /* Any other register is bad. */
6322 if (i
.types
[op
].bitfield
.reg
6323 || i
.types
[op
].bitfield
.regmmx
6324 || i
.types
[op
].bitfield
.regsimd
6325 || i
.types
[op
].bitfield
.sreg2
6326 || i
.types
[op
].bitfield
.sreg3
6327 || i
.types
[op
].bitfield
.control
6328 || i
.types
[op
].bitfield
.debug
6329 || i
.types
[op
].bitfield
.test
)
6331 as_bad (_("`%s%s' not allowed with `%s%c'"),
6333 i
.op
[op
].regs
->reg_name
,
6343 check_long_reg (void)
6347 for (op
= i
.operands
; --op
>= 0;)
6348 /* Skip non-register operands. */
6349 if (!i
.types
[op
].bitfield
.reg
)
6351 /* Reject eight bit registers, except where the template requires
6352 them. (eg. movzb) */
6353 else if (i
.types
[op
].bitfield
.byte
6354 && (i
.tm
.operand_types
[op
].bitfield
.reg
6355 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6356 && (i
.tm
.operand_types
[op
].bitfield
.word
6357 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6359 as_bad (_("`%s%s' not allowed with `%s%c'"),
6361 i
.op
[op
].regs
->reg_name
,
6366 /* Warn if the e prefix on a general reg is missing. */
6367 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6368 && i
.types
[op
].bitfield
.word
6369 && (i
.tm
.operand_types
[op
].bitfield
.reg
6370 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6371 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6373 /* Prohibit these changes in the 64bit mode, since the
6374 lowering is more complicated. */
6375 if (flag_code
== CODE_64BIT
)
6377 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6378 register_prefix
, i
.op
[op
].regs
->reg_name
,
6382 #if REGISTER_WARNINGS
6383 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6385 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6386 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6389 /* Warn if the r prefix on a general reg is present. */
6390 else if (i
.types
[op
].bitfield
.qword
6391 && (i
.tm
.operand_types
[op
].bitfield
.reg
6392 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6393 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6396 && i
.tm
.opcode_modifier
.toqword
6397 && !i
.types
[0].bitfield
.regsimd
)
6399 /* Convert to QWORD. We want REX byte. */
6400 i
.suffix
= QWORD_MNEM_SUFFIX
;
6404 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6405 register_prefix
, i
.op
[op
].regs
->reg_name
,
6414 check_qword_reg (void)
6418 for (op
= i
.operands
; --op
>= 0; )
6419 /* Skip non-register operands. */
6420 if (!i
.types
[op
].bitfield
.reg
)
6422 /* Reject eight bit registers, except where the template requires
6423 them. (eg. movzb) */
6424 else if (i
.types
[op
].bitfield
.byte
6425 && (i
.tm
.operand_types
[op
].bitfield
.reg
6426 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6427 && (i
.tm
.operand_types
[op
].bitfield
.word
6428 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6430 as_bad (_("`%s%s' not allowed with `%s%c'"),
6432 i
.op
[op
].regs
->reg_name
,
6437 /* Warn if the r prefix on a general reg is missing. */
6438 else if ((i
.types
[op
].bitfield
.word
6439 || i
.types
[op
].bitfield
.dword
)
6440 && (i
.tm
.operand_types
[op
].bitfield
.reg
6441 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6442 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6444 /* Prohibit these changes in the 64bit mode, since the
6445 lowering is more complicated. */
6447 && i
.tm
.opcode_modifier
.todword
6448 && !i
.types
[0].bitfield
.regsimd
)
6450 /* Convert to DWORD. We don't want REX byte. */
6451 i
.suffix
= LONG_MNEM_SUFFIX
;
6455 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6456 register_prefix
, i
.op
[op
].regs
->reg_name
,
6465 check_word_reg (void)
6468 for (op
= i
.operands
; --op
>= 0;)
6469 /* Skip non-register operands. */
6470 if (!i
.types
[op
].bitfield
.reg
)
6472 /* Reject eight bit registers, except where the template requires
6473 them. (eg. movzb) */
6474 else if (i
.types
[op
].bitfield
.byte
6475 && (i
.tm
.operand_types
[op
].bitfield
.reg
6476 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6477 && (i
.tm
.operand_types
[op
].bitfield
.word
6478 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6480 as_bad (_("`%s%s' not allowed with `%s%c'"),
6482 i
.op
[op
].regs
->reg_name
,
6487 /* Warn if the e or r prefix on a general reg is present. */
6488 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6489 && (i
.types
[op
].bitfield
.dword
6490 || i
.types
[op
].bitfield
.qword
)
6491 && (i
.tm
.operand_types
[op
].bitfield
.reg
6492 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6493 && i
.tm
.operand_types
[op
].bitfield
.word
)
6495 /* Prohibit these changes in the 64bit mode, since the
6496 lowering is more complicated. */
6497 if (flag_code
== CODE_64BIT
)
6499 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6500 register_prefix
, i
.op
[op
].regs
->reg_name
,
6504 #if REGISTER_WARNINGS
6505 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6507 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6508 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6515 update_imm (unsigned int j
)
6517 i386_operand_type overlap
= i
.types
[j
];
6518 if ((overlap
.bitfield
.imm8
6519 || overlap
.bitfield
.imm8s
6520 || overlap
.bitfield
.imm16
6521 || overlap
.bitfield
.imm32
6522 || overlap
.bitfield
.imm32s
6523 || overlap
.bitfield
.imm64
)
6524 && !operand_type_equal (&overlap
, &imm8
)
6525 && !operand_type_equal (&overlap
, &imm8s
)
6526 && !operand_type_equal (&overlap
, &imm16
)
6527 && !operand_type_equal (&overlap
, &imm32
)
6528 && !operand_type_equal (&overlap
, &imm32s
)
6529 && !operand_type_equal (&overlap
, &imm64
))
6533 i386_operand_type temp
;
6535 operand_type_set (&temp
, 0);
6536 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6538 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6539 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6541 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6542 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6543 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6545 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6546 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6549 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6552 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6553 || operand_type_equal (&overlap
, &imm16_32
)
6554 || operand_type_equal (&overlap
, &imm16_32s
))
6556 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6561 if (!operand_type_equal (&overlap
, &imm8
)
6562 && !operand_type_equal (&overlap
, &imm8s
)
6563 && !operand_type_equal (&overlap
, &imm16
)
6564 && !operand_type_equal (&overlap
, &imm32
)
6565 && !operand_type_equal (&overlap
, &imm32s
)
6566 && !operand_type_equal (&overlap
, &imm64
))
6568 as_bad (_("no instruction mnemonic suffix given; "
6569 "can't determine immediate size"));
6573 i
.types
[j
] = overlap
;
6583 /* Update the first 2 immediate operands. */
6584 n
= i
.operands
> 2 ? 2 : i
.operands
;
6587 for (j
= 0; j
< n
; j
++)
6588 if (update_imm (j
) == 0)
6591 /* The 3rd operand can't be immediate operand. */
6592 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6599 process_operands (void)
6601 /* Default segment register this instruction will use for memory
6602 accesses. 0 means unknown. This is only for optimizing out
6603 unnecessary segment overrides. */
6604 const seg_entry
*default_seg
= 0;
6606 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6608 unsigned int dupl
= i
.operands
;
6609 unsigned int dest
= dupl
- 1;
6612 /* The destination must be an xmm register. */
6613 gas_assert (i
.reg_operands
6614 && MAX_OPERANDS
> dupl
6615 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6617 if (i
.tm
.operand_types
[0].bitfield
.acc
6618 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6620 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6622 /* Keep xmm0 for instructions with VEX prefix and 3
6624 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6625 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6630 /* We remove the first xmm0 and keep the number of
6631 operands unchanged, which in fact duplicates the
6633 for (j
= 1; j
< i
.operands
; j
++)
6635 i
.op
[j
- 1] = i
.op
[j
];
6636 i
.types
[j
- 1] = i
.types
[j
];
6637 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6641 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6643 gas_assert ((MAX_OPERANDS
- 1) > dupl
6644 && (i
.tm
.opcode_modifier
.vexsources
6647 /* Add the implicit xmm0 for instructions with VEX prefix
6649 for (j
= i
.operands
; j
> 0; j
--)
6651 i
.op
[j
] = i
.op
[j
- 1];
6652 i
.types
[j
] = i
.types
[j
- 1];
6653 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6656 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6657 i
.types
[0] = regxmm
;
6658 i
.tm
.operand_types
[0] = regxmm
;
6661 i
.reg_operands
+= 2;
6666 i
.op
[dupl
] = i
.op
[dest
];
6667 i
.types
[dupl
] = i
.types
[dest
];
6668 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6677 i
.op
[dupl
] = i
.op
[dest
];
6678 i
.types
[dupl
] = i
.types
[dest
];
6679 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6682 if (i
.tm
.opcode_modifier
.immext
)
6685 else if (i
.tm
.operand_types
[0].bitfield
.acc
6686 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6690 for (j
= 1; j
< i
.operands
; j
++)
6692 i
.op
[j
- 1] = i
.op
[j
];
6693 i
.types
[j
- 1] = i
.types
[j
];
6695 /* We need to adjust fields in i.tm since they are used by
6696 build_modrm_byte. */
6697 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6704 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6706 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6708 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6709 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6710 regnum
= register_number (i
.op
[1].regs
);
6711 first_reg_in_group
= regnum
& ~3;
6712 last_reg_in_group
= first_reg_in_group
+ 3;
6713 if (regnum
!= first_reg_in_group
)
6714 as_warn (_("source register `%s%s' implicitly denotes"
6715 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6716 register_prefix
, i
.op
[1].regs
->reg_name
,
6717 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6718 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6721 else if (i
.tm
.opcode_modifier
.regkludge
)
6723 /* The imul $imm, %reg instruction is converted into
6724 imul $imm, %reg, %reg, and the clr %reg instruction
6725 is converted into xor %reg, %reg. */
6727 unsigned int first_reg_op
;
6729 if (operand_type_check (i
.types
[0], reg
))
6733 /* Pretend we saw the extra register operand. */
6734 gas_assert (i
.reg_operands
== 1
6735 && i
.op
[first_reg_op
+ 1].regs
== 0);
6736 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6737 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6742 if (i
.tm
.opcode_modifier
.shortform
)
6744 if (i
.types
[0].bitfield
.sreg2
6745 || i
.types
[0].bitfield
.sreg3
)
6747 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6748 && i
.op
[0].regs
->reg_num
== 1)
6750 as_bad (_("you can't `pop %scs'"), register_prefix
);
6753 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6754 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6759 /* The register or float register operand is in operand
6763 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6764 || operand_type_check (i
.types
[0], reg
))
6768 /* Register goes in low 3 bits of opcode. */
6769 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6770 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6772 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6774 /* Warn about some common errors, but press on regardless.
6775 The first case can be generated by gcc (<= 2.8.1). */
6776 if (i
.operands
== 2)
6778 /* Reversed arguments on faddp, fsubp, etc. */
6779 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6780 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6781 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6785 /* Extraneous `l' suffix on fp insn. */
6786 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6787 register_prefix
, i
.op
[0].regs
->reg_name
);
6792 else if (i
.tm
.opcode_modifier
.modrm
)
6794 /* The opcode is completed (modulo i.tm.extension_opcode which
6795 must be put into the modrm byte). Now, we make the modrm and
6796 index base bytes based on all the info we've collected. */
6798 default_seg
= build_modrm_byte ();
6800 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6804 else if (i
.tm
.opcode_modifier
.isstring
)
6806 /* For the string instructions that allow a segment override
6807 on one of their operands, the default segment is ds. */
6811 if (i
.tm
.base_opcode
== 0x8d /* lea */
6814 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6816 /* If a segment was explicitly specified, and the specified segment
6817 is not the default, use an opcode prefix to select it. If we
6818 never figured out what the default segment is, then default_seg
6819 will be zero at this point, and the specified segment prefix will
6821 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6823 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6829 static const seg_entry
*
6830 build_modrm_byte (void)
6832 const seg_entry
*default_seg
= 0;
6833 unsigned int source
, dest
;
6836 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6839 unsigned int nds
, reg_slot
;
6842 dest
= i
.operands
- 1;
6845 /* There are 2 kinds of instructions:
6846 1. 5 operands: 4 register operands or 3 register operands
6847 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6848 VexW0 or VexW1. The destination must be either XMM, YMM or
6850 2. 4 operands: 4 register operands or 3 register operands
6851 plus 1 memory operand, with VexXDS. */
6852 gas_assert ((i
.reg_operands
== 4
6853 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6854 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6855 && i
.tm
.opcode_modifier
.vexw
6856 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6858 /* If VexW1 is set, the first non-immediate operand is the source and
6859 the second non-immediate one is encoded in the immediate operand. */
6860 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6862 source
= i
.imm_operands
;
6863 reg_slot
= i
.imm_operands
+ 1;
6867 source
= i
.imm_operands
+ 1;
6868 reg_slot
= i
.imm_operands
;
6871 if (i
.imm_operands
== 0)
6873 /* When there is no immediate operand, generate an 8bit
6874 immediate operand to encode the first operand. */
6875 exp
= &im_expressions
[i
.imm_operands
++];
6876 i
.op
[i
.operands
].imms
= exp
;
6877 i
.types
[i
.operands
] = imm8
;
6880 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6881 exp
->X_op
= O_constant
;
6882 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6883 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6887 unsigned int imm_slot
;
6889 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6891 if (i
.tm
.opcode_modifier
.immext
)
6893 /* When ImmExt is set, the immediate byte is the last
6895 imm_slot
= i
.operands
- 1;
6903 /* Turn on Imm8 so that output_imm will generate it. */
6904 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6907 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6908 i
.op
[imm_slot
].imms
->X_add_number
6909 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6910 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6913 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6914 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6919 /* i.reg_operands MUST be the number of real register operands;
6920 implicit registers do not count. If there are 3 register
6921 operands, it must be a instruction with VexNDS. For a
6922 instruction with VexNDD, the destination register is encoded
6923 in VEX prefix. If there are 4 register operands, it must be
6924 a instruction with VEX prefix and 3 sources. */
6925 if (i
.mem_operands
== 0
6926 && ((i
.reg_operands
== 2
6927 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6928 || (i
.reg_operands
== 3
6929 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6930 || (i
.reg_operands
== 4 && vex_3_sources
)))
6938 /* When there are 3 operands, one of them may be immediate,
6939 which may be the first or the last operand. Otherwise,
6940 the first operand must be shift count register (cl) or it
6941 is an instruction with VexNDS. */
6942 gas_assert (i
.imm_operands
== 1
6943 || (i
.imm_operands
== 0
6944 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6945 || i
.types
[0].bitfield
.shiftcount
)));
6946 if (operand_type_check (i
.types
[0], imm
)
6947 || i
.types
[0].bitfield
.shiftcount
)
6953 /* When there are 4 operands, the first two must be 8bit
6954 immediate operands. The source operand will be the 3rd
6957 For instructions with VexNDS, if the first operand
6958 an imm8, the source operand is the 2nd one. If the last
6959 operand is imm8, the source operand is the first one. */
6960 gas_assert ((i
.imm_operands
== 2
6961 && i
.types
[0].bitfield
.imm8
6962 && i
.types
[1].bitfield
.imm8
)
6963 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6964 && i
.imm_operands
== 1
6965 && (i
.types
[0].bitfield
.imm8
6966 || i
.types
[i
.operands
- 1].bitfield
.imm8
6968 if (i
.imm_operands
== 2)
6972 if (i
.types
[0].bitfield
.imm8
)
6979 if (is_evex_encoding (&i
.tm
))
6981 /* For EVEX instructions, when there are 5 operands, the
6982 first one must be immediate operand. If the second one
6983 is immediate operand, the source operand is the 3th
6984 one. If the last one is immediate operand, the source
6985 operand is the 2nd one. */
6986 gas_assert (i
.imm_operands
== 2
6987 && i
.tm
.opcode_modifier
.sae
6988 && operand_type_check (i
.types
[0], imm
));
6989 if (operand_type_check (i
.types
[1], imm
))
6991 else if (operand_type_check (i
.types
[4], imm
))
7005 /* RC/SAE operand could be between DEST and SRC. That happens
7006 when one operand is GPR and the other one is XMM/YMM/ZMM
7008 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7011 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7013 /* For instructions with VexNDS, the register-only source
7014 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7015 register. It is encoded in VEX prefix. We need to
7016 clear RegMem bit before calling operand_type_equal. */
7018 i386_operand_type op
;
7021 /* Check register-only source operand when two source
7022 operands are swapped. */
7023 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7024 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7032 op
= i
.tm
.operand_types
[vvvv
];
7033 op
.bitfield
.regmem
= 0;
7034 if ((dest
+ 1) >= i
.operands
7035 || ((!op
.bitfield
.reg
7036 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7037 && !op
.bitfield
.regsimd
7038 && !operand_type_equal (&op
, ®mask
)))
7040 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7046 /* One of the register operands will be encoded in the i.tm.reg
7047 field, the other in the combined i.tm.mode and i.tm.regmem
7048 fields. If no form of this instruction supports a memory
7049 destination operand, then we assume the source operand may
7050 sometimes be a memory operand and so we need to store the
7051 destination in the i.rm.reg field. */
7052 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7053 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7055 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7056 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7057 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7059 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7061 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7063 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7068 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7069 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7070 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7072 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7074 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7076 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7079 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7081 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7084 add_prefix (LOCK_PREFIX_OPCODE
);
7088 { /* If it's not 2 reg operands... */
7093 unsigned int fake_zero_displacement
= 0;
7096 for (op
= 0; op
< i
.operands
; op
++)
7097 if (operand_type_check (i
.types
[op
], anymem
))
7099 gas_assert (op
< i
.operands
);
7101 if (i
.tm
.opcode_modifier
.vecsib
)
7103 if (i
.index_reg
->reg_num
== RegIZ
)
7106 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7109 i
.sib
.base
= NO_BASE_REGISTER
;
7110 i
.sib
.scale
= i
.log2_scale_factor
;
7111 i
.types
[op
].bitfield
.disp8
= 0;
7112 i
.types
[op
].bitfield
.disp16
= 0;
7113 i
.types
[op
].bitfield
.disp64
= 0;
7114 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7116 /* Must be 32 bit */
7117 i
.types
[op
].bitfield
.disp32
= 1;
7118 i
.types
[op
].bitfield
.disp32s
= 0;
7122 i
.types
[op
].bitfield
.disp32
= 0;
7123 i
.types
[op
].bitfield
.disp32s
= 1;
7126 i
.sib
.index
= i
.index_reg
->reg_num
;
7127 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7129 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7135 if (i
.base_reg
== 0)
7138 if (!i
.disp_operands
)
7139 fake_zero_displacement
= 1;
7140 if (i
.index_reg
== 0)
7142 i386_operand_type newdisp
;
7144 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7145 /* Operand is just <disp> */
7146 if (flag_code
== CODE_64BIT
)
7148 /* 64bit mode overwrites the 32bit absolute
7149 addressing by RIP relative addressing and
7150 absolute addressing is encoded by one of the
7151 redundant SIB forms. */
7152 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7153 i
.sib
.base
= NO_BASE_REGISTER
;
7154 i
.sib
.index
= NO_INDEX_REGISTER
;
7155 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7157 else if ((flag_code
== CODE_16BIT
)
7158 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7160 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7165 i
.rm
.regmem
= NO_BASE_REGISTER
;
7168 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7169 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7171 else if (!i
.tm
.opcode_modifier
.vecsib
)
7173 /* !i.base_reg && i.index_reg */
7174 if (i
.index_reg
->reg_num
== RegIZ
)
7175 i
.sib
.index
= NO_INDEX_REGISTER
;
7177 i
.sib
.index
= i
.index_reg
->reg_num
;
7178 i
.sib
.base
= NO_BASE_REGISTER
;
7179 i
.sib
.scale
= i
.log2_scale_factor
;
7180 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7181 i
.types
[op
].bitfield
.disp8
= 0;
7182 i
.types
[op
].bitfield
.disp16
= 0;
7183 i
.types
[op
].bitfield
.disp64
= 0;
7184 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7186 /* Must be 32 bit */
7187 i
.types
[op
].bitfield
.disp32
= 1;
7188 i
.types
[op
].bitfield
.disp32s
= 0;
7192 i
.types
[op
].bitfield
.disp32
= 0;
7193 i
.types
[op
].bitfield
.disp32s
= 1;
7195 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7199 /* RIP addressing for 64bit mode. */
7200 else if (i
.base_reg
->reg_num
== RegIP
)
7202 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7203 i
.rm
.regmem
= NO_BASE_REGISTER
;
7204 i
.types
[op
].bitfield
.disp8
= 0;
7205 i
.types
[op
].bitfield
.disp16
= 0;
7206 i
.types
[op
].bitfield
.disp32
= 0;
7207 i
.types
[op
].bitfield
.disp32s
= 1;
7208 i
.types
[op
].bitfield
.disp64
= 0;
7209 i
.flags
[op
] |= Operand_PCrel
;
7210 if (! i
.disp_operands
)
7211 fake_zero_displacement
= 1;
7213 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7215 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7216 switch (i
.base_reg
->reg_num
)
7219 if (i
.index_reg
== 0)
7221 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7222 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7226 if (i
.index_reg
== 0)
7229 if (operand_type_check (i
.types
[op
], disp
) == 0)
7231 /* fake (%bp) into 0(%bp) */
7232 i
.types
[op
].bitfield
.disp8
= 1;
7233 fake_zero_displacement
= 1;
7236 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7237 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7239 default: /* (%si) -> 4 or (%di) -> 5 */
7240 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7242 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7244 else /* i.base_reg and 32/64 bit mode */
7246 if (flag_code
== CODE_64BIT
7247 && operand_type_check (i
.types
[op
], disp
))
7249 i
.types
[op
].bitfield
.disp16
= 0;
7250 i
.types
[op
].bitfield
.disp64
= 0;
7251 if (i
.prefix
[ADDR_PREFIX
] == 0)
7253 i
.types
[op
].bitfield
.disp32
= 0;
7254 i
.types
[op
].bitfield
.disp32s
= 1;
7258 i
.types
[op
].bitfield
.disp32
= 1;
7259 i
.types
[op
].bitfield
.disp32s
= 0;
7263 if (!i
.tm
.opcode_modifier
.vecsib
)
7264 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7265 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7267 i
.sib
.base
= i
.base_reg
->reg_num
;
7268 /* x86-64 ignores REX prefix bit here to avoid decoder
7270 if (!(i
.base_reg
->reg_flags
& RegRex
)
7271 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7272 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7274 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7276 fake_zero_displacement
= 1;
7277 i
.types
[op
].bitfield
.disp8
= 1;
7279 i
.sib
.scale
= i
.log2_scale_factor
;
7280 if (i
.index_reg
== 0)
7282 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7283 /* <disp>(%esp) becomes two byte modrm with no index
7284 register. We've already stored the code for esp
7285 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7286 Any base register besides %esp will not use the
7287 extra modrm byte. */
7288 i
.sib
.index
= NO_INDEX_REGISTER
;
7290 else if (!i
.tm
.opcode_modifier
.vecsib
)
7292 if (i
.index_reg
->reg_num
== RegIZ
)
7293 i
.sib
.index
= NO_INDEX_REGISTER
;
7295 i
.sib
.index
= i
.index_reg
->reg_num
;
7296 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7297 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7302 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7303 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7307 if (!fake_zero_displacement
7311 fake_zero_displacement
= 1;
7312 if (i
.disp_encoding
== disp_encoding_8bit
)
7313 i
.types
[op
].bitfield
.disp8
= 1;
7315 i
.types
[op
].bitfield
.disp32
= 1;
7317 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7321 if (fake_zero_displacement
)
7323 /* Fakes a zero displacement assuming that i.types[op]
7324 holds the correct displacement size. */
7327 gas_assert (i
.op
[op
].disps
== 0);
7328 exp
= &disp_expressions
[i
.disp_operands
++];
7329 i
.op
[op
].disps
= exp
;
7330 exp
->X_op
= O_constant
;
7331 exp
->X_add_number
= 0;
7332 exp
->X_add_symbol
= (symbolS
*) 0;
7333 exp
->X_op_symbol
= (symbolS
*) 0;
7341 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7343 if (operand_type_check (i
.types
[0], imm
))
7344 i
.vex
.register_specifier
= NULL
;
7347 /* VEX.vvvv encodes one of the sources when the first
7348 operand is not an immediate. */
7349 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7350 i
.vex
.register_specifier
= i
.op
[0].regs
;
7352 i
.vex
.register_specifier
= i
.op
[1].regs
;
7355 /* Destination is a XMM register encoded in the ModRM.reg
7357 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7358 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7361 /* ModRM.rm and VEX.B encodes the other source. */
7362 if (!i
.mem_operands
)
7366 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7367 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7369 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7371 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7375 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7377 i
.vex
.register_specifier
= i
.op
[2].regs
;
7378 if (!i
.mem_operands
)
7381 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7382 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7386 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7387 (if any) based on i.tm.extension_opcode. Again, we must be
7388 careful to make sure that segment/control/debug/test/MMX
7389 registers are coded into the i.rm.reg field. */
7390 else if (i
.reg_operands
)
7393 unsigned int vex_reg
= ~0;
7395 for (op
= 0; op
< i
.operands
; op
++)
7396 if (i
.types
[op
].bitfield
.reg
7397 || i
.types
[op
].bitfield
.regmmx
7398 || i
.types
[op
].bitfield
.regsimd
7399 || i
.types
[op
].bitfield
.regbnd
7400 || i
.types
[op
].bitfield
.regmask
7401 || i
.types
[op
].bitfield
.sreg2
7402 || i
.types
[op
].bitfield
.sreg3
7403 || i
.types
[op
].bitfield
.control
7404 || i
.types
[op
].bitfield
.debug
7405 || i
.types
[op
].bitfield
.test
)
7410 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7412 /* For instructions with VexNDS, the register-only
7413 source operand is encoded in VEX prefix. */
7414 gas_assert (mem
!= (unsigned int) ~0);
7419 gas_assert (op
< i
.operands
);
7423 /* Check register-only source operand when two source
7424 operands are swapped. */
7425 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7426 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7430 gas_assert (mem
== (vex_reg
+ 1)
7431 && op
< i
.operands
);
7436 gas_assert (vex_reg
< i
.operands
);
7440 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7442 /* For instructions with VexNDD, the register destination
7443 is encoded in VEX prefix. */
7444 if (i
.mem_operands
== 0)
7446 /* There is no memory operand. */
7447 gas_assert ((op
+ 2) == i
.operands
);
7452 /* There are only 2 non-immediate operands. */
7453 gas_assert (op
< i
.imm_operands
+ 2
7454 && i
.operands
== i
.imm_operands
+ 2);
7455 vex_reg
= i
.imm_operands
+ 1;
7459 gas_assert (op
< i
.operands
);
7461 if (vex_reg
!= (unsigned int) ~0)
7463 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7465 if ((!type
->bitfield
.reg
7466 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7467 && !type
->bitfield
.regsimd
7468 && !operand_type_equal (type
, ®mask
))
7471 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7474 /* Don't set OP operand twice. */
7477 /* If there is an extension opcode to put here, the
7478 register number must be put into the regmem field. */
7479 if (i
.tm
.extension_opcode
!= None
)
7481 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7482 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7484 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7489 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7490 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7492 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7497 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7498 must set it to 3 to indicate this is a register operand
7499 in the regmem field. */
7500 if (!i
.mem_operands
)
7504 /* Fill in i.rm.reg field with extension opcode (if any). */
7505 if (i
.tm
.extension_opcode
!= None
)
7506 i
.rm
.reg
= i
.tm
.extension_opcode
;
7512 output_branch (void)
7518 relax_substateT subtype
;
7522 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7523 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7526 if (i
.prefix
[DATA_PREFIX
] != 0)
7532 /* Pentium4 branch hints. */
7533 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7534 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7539 if (i
.prefix
[REX_PREFIX
] != 0)
7545 /* BND prefixed jump. */
7546 if (i
.prefix
[BND_PREFIX
] != 0)
7548 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7552 if (i
.prefixes
!= 0 && !intel_syntax
)
7553 as_warn (_("skipping prefixes on this instruction"));
7555 /* It's always a symbol; End frag & setup for relax.
7556 Make sure there is enough room in this frag for the largest
7557 instruction we may generate in md_convert_frag. This is 2
7558 bytes for the opcode and room for the prefix and largest
7560 frag_grow (prefix
+ 2 + 4);
7561 /* Prefix and 1 opcode byte go in fr_fix. */
7562 p
= frag_more (prefix
+ 1);
7563 if (i
.prefix
[DATA_PREFIX
] != 0)
7564 *p
++ = DATA_PREFIX_OPCODE
;
7565 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7566 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7567 *p
++ = i
.prefix
[SEG_PREFIX
];
7568 if (i
.prefix
[REX_PREFIX
] != 0)
7569 *p
++ = i
.prefix
[REX_PREFIX
];
7570 *p
= i
.tm
.base_opcode
;
7572 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7573 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7574 else if (cpu_arch_flags
.bitfield
.cpui386
)
7575 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7577 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7580 sym
= i
.op
[0].disps
->X_add_symbol
;
7581 off
= i
.op
[0].disps
->X_add_number
;
7583 if (i
.op
[0].disps
->X_op
!= O_constant
7584 && i
.op
[0].disps
->X_op
!= O_symbol
)
7586 /* Handle complex expressions. */
7587 sym
= make_expr_symbol (i
.op
[0].disps
);
7591 /* 1 possible extra opcode + 4 byte displacement go in var part.
7592 Pass reloc in fr_var. */
7593 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7597 /* Return TRUE iff PLT32 relocation should be used for branching to
7601 need_plt32_p (symbolS
*s
)
7603 /* PLT32 relocation is ELF only. */
7607 /* Since there is no need to prepare for PLT branch on x86-64, we
7608 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7609 be used as a marker for 32-bit PC-relative branches. */
7613 /* Weak or undefined symbol need PLT32 relocation. */
7614 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7617 /* Non-global symbol doesn't need PLT32 relocation. */
7618 if (! S_IS_EXTERNAL (s
))
7621 /* Other global symbols need PLT32 relocation. NB: Symbol with
7622 non-default visibilities are treated as normal global symbol
7623 so that PLT32 relocation can be used as a marker for 32-bit
7624 PC-relative branches. It is useful for linker relaxation. */
7635 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7637 if (i
.tm
.opcode_modifier
.jumpbyte
)
7639 /* This is a loop or jecxz type instruction. */
7641 if (i
.prefix
[ADDR_PREFIX
] != 0)
7643 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7646 /* Pentium4 branch hints. */
7647 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7648 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7650 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7659 if (flag_code
== CODE_16BIT
)
7662 if (i
.prefix
[DATA_PREFIX
] != 0)
7664 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7674 if (i
.prefix
[REX_PREFIX
] != 0)
7676 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7680 /* BND prefixed jump. */
7681 if (i
.prefix
[BND_PREFIX
] != 0)
7683 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7687 if (i
.prefixes
!= 0 && !intel_syntax
)
7688 as_warn (_("skipping prefixes on this instruction"));
7690 p
= frag_more (i
.tm
.opcode_length
+ size
);
7691 switch (i
.tm
.opcode_length
)
7694 *p
++ = i
.tm
.base_opcode
>> 8;
7697 *p
++ = i
.tm
.base_opcode
;
7703 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7705 && jump_reloc
== NO_RELOC
7706 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7707 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7710 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7712 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7713 i
.op
[0].disps
, 1, jump_reloc
);
7715 /* All jumps handled here are signed, but don't use a signed limit
7716 check for 32 and 16 bit jumps as we want to allow wrap around at
7717 4G and 64k respectively. */
7719 fixP
->fx_signed
= 1;
7723 output_interseg_jump (void)
7731 if (flag_code
== CODE_16BIT
)
7735 if (i
.prefix
[DATA_PREFIX
] != 0)
7741 if (i
.prefix
[REX_PREFIX
] != 0)
7751 if (i
.prefixes
!= 0 && !intel_syntax
)
7752 as_warn (_("skipping prefixes on this instruction"));
7754 /* 1 opcode; 2 segment; offset */
7755 p
= frag_more (prefix
+ 1 + 2 + size
);
7757 if (i
.prefix
[DATA_PREFIX
] != 0)
7758 *p
++ = DATA_PREFIX_OPCODE
;
7760 if (i
.prefix
[REX_PREFIX
] != 0)
7761 *p
++ = i
.prefix
[REX_PREFIX
];
7763 *p
++ = i
.tm
.base_opcode
;
7764 if (i
.op
[1].imms
->X_op
== O_constant
)
7766 offsetT n
= i
.op
[1].imms
->X_add_number
;
7769 && !fits_in_unsigned_word (n
)
7770 && !fits_in_signed_word (n
))
7772 as_bad (_("16-bit jump out of range"));
7775 md_number_to_chars (p
, n
, size
);
7778 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7779 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7780 if (i
.op
[0].imms
->X_op
!= O_constant
)
7781 as_bad (_("can't handle non absolute segment in `%s'"),
7783 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7789 fragS
*insn_start_frag
;
7790 offsetT insn_start_off
;
7792 /* Tie dwarf2 debug info to the address at the start of the insn.
7793 We can't do this after the insn has been output as the current
7794 frag may have been closed off. eg. by frag_var. */
7795 dwarf2_emit_insn (0);
7797 insn_start_frag
= frag_now
;
7798 insn_start_off
= frag_now_fix ();
7801 if (i
.tm
.opcode_modifier
.jump
)
7803 else if (i
.tm
.opcode_modifier
.jumpbyte
7804 || i
.tm
.opcode_modifier
.jumpdword
)
7806 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7807 output_interseg_jump ();
7810 /* Output normal instructions here. */
7814 unsigned int prefix
;
7817 && i
.tm
.base_opcode
== 0xfae
7819 && i
.imm_operands
== 1
7820 && (i
.op
[0].imms
->X_add_number
== 0xe8
7821 || i
.op
[0].imms
->X_add_number
== 0xf0
7822 || i
.op
[0].imms
->X_add_number
== 0xf8))
7824 /* Encode lfence, mfence, and sfence as
7825 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7826 offsetT val
= 0x240483f0ULL
;
7828 md_number_to_chars (p
, val
, 5);
7832 /* Some processors fail on LOCK prefix. This options makes
7833 assembler ignore LOCK prefix and serves as a workaround. */
7834 if (omit_lock_prefix
)
7836 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7838 i
.prefix
[LOCK_PREFIX
] = 0;
7841 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7842 don't need the explicit prefix. */
7843 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7845 switch (i
.tm
.opcode_length
)
7848 if (i
.tm
.base_opcode
& 0xff000000)
7850 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7851 add_prefix (prefix
);
7855 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7857 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7858 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
7859 || prefix
!= REPE_PREFIX_OPCODE
7860 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
7861 add_prefix (prefix
);
7867 /* Check for pseudo prefixes. */
7868 as_bad_where (insn_start_frag
->fr_file
,
7869 insn_start_frag
->fr_line
,
7870 _("pseudo prefix without instruction"));
7876 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7877 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7878 R_X86_64_GOTTPOFF relocation so that linker can safely
7879 perform IE->LE optimization. */
7880 if (x86_elf_abi
== X86_64_X32_ABI
7882 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7883 && i
.prefix
[REX_PREFIX
] == 0)
7884 add_prefix (REX_OPCODE
);
7887 /* The prefix bytes. */
7888 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7890 FRAG_APPEND_1_CHAR (*q
);
7894 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7899 /* REX byte is encoded in VEX prefix. */
7903 FRAG_APPEND_1_CHAR (*q
);
7906 /* There should be no other prefixes for instructions
7911 /* For EVEX instructions i.vrex should become 0 after
7912 build_evex_prefix. For VEX instructions upper 16 registers
7913 aren't available, so VREX should be 0. */
7916 /* Now the VEX prefix. */
7917 p
= frag_more (i
.vex
.length
);
7918 for (j
= 0; j
< i
.vex
.length
; j
++)
7919 p
[j
] = i
.vex
.bytes
[j
];
7922 /* Now the opcode; be careful about word order here! */
7923 if (i
.tm
.opcode_length
== 1)
7925 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7929 switch (i
.tm
.opcode_length
)
7933 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7934 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7938 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7948 /* Put out high byte first: can't use md_number_to_chars! */
7949 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7950 *p
= i
.tm
.base_opcode
& 0xff;
7953 /* Now the modrm byte and sib byte (if present). */
7954 if (i
.tm
.opcode_modifier
.modrm
)
7956 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7959 /* If i.rm.regmem == ESP (4)
7960 && i.rm.mode != (Register mode)
7962 ==> need second modrm byte. */
7963 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7965 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7966 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7968 | i
.sib
.scale
<< 6));
7971 if (i
.disp_operands
)
7972 output_disp (insn_start_frag
, insn_start_off
);
7975 output_imm (insn_start_frag
, insn_start_off
);
7981 pi ("" /*line*/, &i
);
7983 #endif /* DEBUG386 */
7986 /* Return the size of the displacement operand N. */
7989 disp_size (unsigned int n
)
7993 if (i
.types
[n
].bitfield
.disp64
)
7995 else if (i
.types
[n
].bitfield
.disp8
)
7997 else if (i
.types
[n
].bitfield
.disp16
)
8002 /* Return the size of the immediate operand N. */
8005 imm_size (unsigned int n
)
8008 if (i
.types
[n
].bitfield
.imm64
)
8010 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8012 else if (i
.types
[n
].bitfield
.imm16
)
8018 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8023 for (n
= 0; n
< i
.operands
; n
++)
8025 if (operand_type_check (i
.types
[n
], disp
))
8027 if (i
.op
[n
].disps
->X_op
== O_constant
)
8029 int size
= disp_size (n
);
8030 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8032 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8034 p
= frag_more (size
);
8035 md_number_to_chars (p
, val
, size
);
8039 enum bfd_reloc_code_real reloc_type
;
8040 int size
= disp_size (n
);
8041 int sign
= i
.types
[n
].bitfield
.disp32s
;
8042 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8045 /* We can't have 8 bit displacement here. */
8046 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8048 /* The PC relative address is computed relative
8049 to the instruction boundary, so in case immediate
8050 fields follows, we need to adjust the value. */
8051 if (pcrel
&& i
.imm_operands
)
8056 for (n1
= 0; n1
< i
.operands
; n1
++)
8057 if (operand_type_check (i
.types
[n1
], imm
))
8059 /* Only one immediate is allowed for PC
8060 relative address. */
8061 gas_assert (sz
== 0);
8063 i
.op
[n
].disps
->X_add_number
-= sz
;
8065 /* We should find the immediate. */
8066 gas_assert (sz
!= 0);
8069 p
= frag_more (size
);
8070 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8072 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8073 && (((reloc_type
== BFD_RELOC_32
8074 || reloc_type
== BFD_RELOC_X86_64_32S
8075 || (reloc_type
== BFD_RELOC_64
8077 && (i
.op
[n
].disps
->X_op
== O_symbol
8078 || (i
.op
[n
].disps
->X_op
== O_add
8079 && ((symbol_get_value_expression
8080 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8082 || reloc_type
== BFD_RELOC_32_PCREL
))
8086 if (insn_start_frag
== frag_now
)
8087 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8092 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8093 for (fr
= insn_start_frag
->fr_next
;
8094 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8096 add
+= p
- frag_now
->fr_literal
;
8101 reloc_type
= BFD_RELOC_386_GOTPC
;
8102 i
.op
[n
].imms
->X_add_number
+= add
;
8104 else if (reloc_type
== BFD_RELOC_64
)
8105 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8107 /* Don't do the adjustment for x86-64, as there
8108 the pcrel addressing is relative to the _next_
8109 insn, and that is taken care of in other code. */
8110 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8112 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8113 size
, i
.op
[n
].disps
, pcrel
,
8115 /* Check for "call/jmp *mem", "mov mem, %reg",
8116 "test %reg, mem" and "binop mem, %reg" where binop
8117 is one of adc, add, and, cmp, or, sbb, sub, xor
8118 instructions. Always generate R_386_GOT32X for
8119 "sym*GOT" operand in 32-bit mode. */
8120 if ((generate_relax_relocations
8123 && i
.rm
.regmem
== 5))
8125 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8126 && ((i
.operands
== 1
8127 && i
.tm
.base_opcode
== 0xff
8128 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8130 && (i
.tm
.base_opcode
== 0x8b
8131 || i
.tm
.base_opcode
== 0x85
8132 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8136 fixP
->fx_tcbit
= i
.rex
!= 0;
8138 && (i
.base_reg
->reg_num
== RegIP
))
8139 fixP
->fx_tcbit2
= 1;
8142 fixP
->fx_tcbit2
= 1;
8150 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8155 for (n
= 0; n
< i
.operands
; n
++)
8157 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8158 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8161 if (operand_type_check (i
.types
[n
], imm
))
8163 if (i
.op
[n
].imms
->X_op
== O_constant
)
8165 int size
= imm_size (n
);
8168 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8170 p
= frag_more (size
);
8171 md_number_to_chars (p
, val
, size
);
8175 /* Not absolute_section.
8176 Need a 32-bit fixup (don't support 8bit
8177 non-absolute imms). Try to support other
8179 enum bfd_reloc_code_real reloc_type
;
8180 int size
= imm_size (n
);
8183 if (i
.types
[n
].bitfield
.imm32s
8184 && (i
.suffix
== QWORD_MNEM_SUFFIX
8185 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8190 p
= frag_more (size
);
8191 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8193 /* This is tough to explain. We end up with this one if we
8194 * have operands that look like
8195 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8196 * obtain the absolute address of the GOT, and it is strongly
8197 * preferable from a performance point of view to avoid using
8198 * a runtime relocation for this. The actual sequence of
8199 * instructions often look something like:
8204 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8206 * The call and pop essentially return the absolute address
8207 * of the label .L66 and store it in %ebx. The linker itself
8208 * will ultimately change the first operand of the addl so
8209 * that %ebx points to the GOT, but to keep things simple, the
8210 * .o file must have this operand set so that it generates not
8211 * the absolute address of .L66, but the absolute address of
8212 * itself. This allows the linker itself simply treat a GOTPC
8213 * relocation as asking for a pcrel offset to the GOT to be
8214 * added in, and the addend of the relocation is stored in the
8215 * operand field for the instruction itself.
8217 * Our job here is to fix the operand so that it would add
8218 * the correct offset so that %ebx would point to itself. The
8219 * thing that is tricky is that .-.L66 will point to the
8220 * beginning of the instruction, so we need to further modify
8221 * the operand so that it will point to itself. There are
8222 * other cases where you have something like:
8224 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8226 * and here no correction would be required. Internally in
8227 * the assembler we treat operands of this form as not being
8228 * pcrel since the '.' is explicitly mentioned, and I wonder
8229 * whether it would simplify matters to do it this way. Who
8230 * knows. In earlier versions of the PIC patches, the
8231 * pcrel_adjust field was used to store the correction, but
8232 * since the expression is not pcrel, I felt it would be
8233 * confusing to do it this way. */
8235 if ((reloc_type
== BFD_RELOC_32
8236 || reloc_type
== BFD_RELOC_X86_64_32S
8237 || reloc_type
== BFD_RELOC_64
)
8239 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8240 && (i
.op
[n
].imms
->X_op
== O_symbol
8241 || (i
.op
[n
].imms
->X_op
== O_add
8242 && ((symbol_get_value_expression
8243 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8248 if (insn_start_frag
== frag_now
)
8249 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8254 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8255 for (fr
= insn_start_frag
->fr_next
;
8256 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8258 add
+= p
- frag_now
->fr_literal
;
8262 reloc_type
= BFD_RELOC_386_GOTPC
;
8264 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8266 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8267 i
.op
[n
].imms
->X_add_number
+= add
;
8269 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8270 i
.op
[n
].imms
, 0, reloc_type
);
8276 /* x86_cons_fix_new is called via the expression parsing code when a
8277 reloc is needed. We use this hook to get the correct .got reloc. */
8278 static int cons_sign
= -1;
8281 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8282 expressionS
*exp
, bfd_reloc_code_real_type r
)
8284 r
= reloc (len
, 0, cons_sign
, r
);
8287 if (exp
->X_op
== O_secrel
)
8289 exp
->X_op
= O_symbol
;
8290 r
= BFD_RELOC_32_SECREL
;
8294 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8297 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8298 purpose of the `.dc.a' internal pseudo-op. */
8301 x86_address_bytes (void)
8303 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8305 return stdoutput
->arch_info
->bits_per_address
/ 8;
8308 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8310 # define lex_got(reloc, adjust, types) NULL
8312 /* Parse operands of the form
8313 <symbol>@GOTOFF+<nnn>
8314 and similar .plt or .got references.
8316 If we find one, set up the correct relocation in RELOC and copy the
8317 input string, minus the `@GOTOFF' into a malloc'd buffer for
8318 parsing by the calling routine. Return this buffer, and if ADJUST
8319 is non-null set it to the length of the string we removed from the
8320 input line. Otherwise return NULL. */
8322 lex_got (enum bfd_reloc_code_real
*rel
,
8324 i386_operand_type
*types
)
8326 /* Some of the relocations depend on the size of what field is to
8327 be relocated. But in our callers i386_immediate and i386_displacement
8328 we don't yet know the operand size (this will be set by insn
8329 matching). Hence we record the word32 relocation here,
8330 and adjust the reloc according to the real size in reloc(). */
8331 static const struct {
8334 const enum bfd_reloc_code_real rel
[2];
8335 const i386_operand_type types64
;
8337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8338 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8340 OPERAND_TYPE_IMM32_64
},
8342 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8343 BFD_RELOC_X86_64_PLTOFF64
},
8344 OPERAND_TYPE_IMM64
},
8345 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8346 BFD_RELOC_X86_64_PLT32
},
8347 OPERAND_TYPE_IMM32_32S_DISP32
},
8348 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8349 BFD_RELOC_X86_64_GOTPLT64
},
8350 OPERAND_TYPE_IMM64_DISP64
},
8351 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8352 BFD_RELOC_X86_64_GOTOFF64
},
8353 OPERAND_TYPE_IMM64_DISP64
},
8354 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8355 BFD_RELOC_X86_64_GOTPCREL
},
8356 OPERAND_TYPE_IMM32_32S_DISP32
},
8357 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8358 BFD_RELOC_X86_64_TLSGD
},
8359 OPERAND_TYPE_IMM32_32S_DISP32
},
8360 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8361 _dummy_first_bfd_reloc_code_real
},
8362 OPERAND_TYPE_NONE
},
8363 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8364 BFD_RELOC_X86_64_TLSLD
},
8365 OPERAND_TYPE_IMM32_32S_DISP32
},
8366 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8367 BFD_RELOC_X86_64_GOTTPOFF
},
8368 OPERAND_TYPE_IMM32_32S_DISP32
},
8369 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8370 BFD_RELOC_X86_64_TPOFF32
},
8371 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8372 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8373 _dummy_first_bfd_reloc_code_real
},
8374 OPERAND_TYPE_NONE
},
8375 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8376 BFD_RELOC_X86_64_DTPOFF32
},
8377 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8378 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8379 _dummy_first_bfd_reloc_code_real
},
8380 OPERAND_TYPE_NONE
},
8381 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8382 _dummy_first_bfd_reloc_code_real
},
8383 OPERAND_TYPE_NONE
},
8384 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8385 BFD_RELOC_X86_64_GOT32
},
8386 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8387 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8388 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8389 OPERAND_TYPE_IMM32_32S_DISP32
},
8390 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8391 BFD_RELOC_X86_64_TLSDESC_CALL
},
8392 OPERAND_TYPE_IMM32_32S_DISP32
},
8397 #if defined (OBJ_MAYBE_ELF)
8402 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8403 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8406 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8408 int len
= gotrel
[j
].len
;
8409 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8411 if (gotrel
[j
].rel
[object_64bit
] != 0)
8414 char *tmpbuf
, *past_reloc
;
8416 *rel
= gotrel
[j
].rel
[object_64bit
];
8420 if (flag_code
!= CODE_64BIT
)
8422 types
->bitfield
.imm32
= 1;
8423 types
->bitfield
.disp32
= 1;
8426 *types
= gotrel
[j
].types64
;
8429 if (j
!= 0 && GOT_symbol
== NULL
)
8430 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8432 /* The length of the first part of our input line. */
8433 first
= cp
- input_line_pointer
;
8435 /* The second part goes from after the reloc token until
8436 (and including) an end_of_line char or comma. */
8437 past_reloc
= cp
+ 1 + len
;
8439 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8441 second
= cp
+ 1 - past_reloc
;
8443 /* Allocate and copy string. The trailing NUL shouldn't
8444 be necessary, but be safe. */
8445 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8446 memcpy (tmpbuf
, input_line_pointer
, first
);
8447 if (second
!= 0 && *past_reloc
!= ' ')
8448 /* Replace the relocation token with ' ', so that
8449 errors like foo@GOTOFF1 will be detected. */
8450 tmpbuf
[first
++] = ' ';
8452 /* Increment length by 1 if the relocation token is
8457 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8458 tmpbuf
[first
+ second
] = '\0';
8462 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8463 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8468 /* Might be a symbol version string. Don't as_bad here. */
8477 /* Parse operands of the form
8478 <symbol>@SECREL32+<nnn>
8480 If we find one, set up the correct relocation in RELOC and copy the
8481 input string, minus the `@SECREL32' into a malloc'd buffer for
8482 parsing by the calling routine. Return this buffer, and if ADJUST
8483 is non-null set it to the length of the string we removed from the
8484 input line. Otherwise return NULL.
8486 This function is copied from the ELF version above adjusted for PE targets. */
8489 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8490 int *adjust ATTRIBUTE_UNUSED
,
8491 i386_operand_type
*types
)
8497 const enum bfd_reloc_code_real rel
[2];
8498 const i386_operand_type types64
;
8502 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8503 BFD_RELOC_32_SECREL
},
8504 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8510 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8511 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8514 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8516 int len
= gotrel
[j
].len
;
8518 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8520 if (gotrel
[j
].rel
[object_64bit
] != 0)
8523 char *tmpbuf
, *past_reloc
;
8525 *rel
= gotrel
[j
].rel
[object_64bit
];
8531 if (flag_code
!= CODE_64BIT
)
8533 types
->bitfield
.imm32
= 1;
8534 types
->bitfield
.disp32
= 1;
8537 *types
= gotrel
[j
].types64
;
8540 /* The length of the first part of our input line. */
8541 first
= cp
- input_line_pointer
;
8543 /* The second part goes from after the reloc token until
8544 (and including) an end_of_line char or comma. */
8545 past_reloc
= cp
+ 1 + len
;
8547 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8549 second
= cp
+ 1 - past_reloc
;
8551 /* Allocate and copy string. The trailing NUL shouldn't
8552 be necessary, but be safe. */
8553 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8554 memcpy (tmpbuf
, input_line_pointer
, first
);
8555 if (second
!= 0 && *past_reloc
!= ' ')
8556 /* Replace the relocation token with ' ', so that
8557 errors like foo@SECLREL321 will be detected. */
8558 tmpbuf
[first
++] = ' ';
8559 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8560 tmpbuf
[first
+ second
] = '\0';
8564 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8565 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8570 /* Might be a symbol version string. Don't as_bad here. */
8576 bfd_reloc_code_real_type
8577 x86_cons (expressionS
*exp
, int size
)
8579 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8581 intel_syntax
= -intel_syntax
;
8584 if (size
== 4 || (object_64bit
&& size
== 8))
8586 /* Handle @GOTOFF and the like in an expression. */
8588 char *gotfree_input_line
;
8591 save
= input_line_pointer
;
8592 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8593 if (gotfree_input_line
)
8594 input_line_pointer
= gotfree_input_line
;
8598 if (gotfree_input_line
)
8600 /* expression () has merrily parsed up to the end of line,
8601 or a comma - in the wrong buffer. Transfer how far
8602 input_line_pointer has moved to the right buffer. */
8603 input_line_pointer
= (save
8604 + (input_line_pointer
- gotfree_input_line
)
8606 free (gotfree_input_line
);
8607 if (exp
->X_op
== O_constant
8608 || exp
->X_op
== O_absent
8609 || exp
->X_op
== O_illegal
8610 || exp
->X_op
== O_register
8611 || exp
->X_op
== O_big
)
8613 char c
= *input_line_pointer
;
8614 *input_line_pointer
= 0;
8615 as_bad (_("missing or invalid expression `%s'"), save
);
8616 *input_line_pointer
= c
;
8623 intel_syntax
= -intel_syntax
;
8626 i386_intel_simplify (exp
);
8632 signed_cons (int size
)
8634 if (flag_code
== CODE_64BIT
)
8642 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8649 if (exp
.X_op
== O_symbol
)
8650 exp
.X_op
= O_secrel
;
8652 emit_expr (&exp
, 4);
8654 while (*input_line_pointer
++ == ',');
8656 input_line_pointer
--;
8657 demand_empty_rest_of_line ();
8661 /* Handle Vector operations. */
8664 check_VecOperations (char *op_string
, char *op_end
)
8666 const reg_entry
*mask
;
8671 && (op_end
== NULL
|| op_string
< op_end
))
8674 if (*op_string
== '{')
8678 /* Check broadcasts. */
8679 if (strncmp (op_string
, "1to", 3) == 0)
8684 goto duplicated_vec_op
;
8687 if (*op_string
== '8')
8689 else if (*op_string
== '4')
8691 else if (*op_string
== '2')
8693 else if (*op_string
== '1'
8694 && *(op_string
+1) == '6')
8701 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8706 broadcast_op
.type
= bcst_type
;
8707 broadcast_op
.operand
= this_operand
;
8708 broadcast_op
.bytes
= 0;
8709 i
.broadcast
= &broadcast_op
;
8711 /* Check masking operation. */
8712 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8714 /* k0 can't be used for write mask. */
8715 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8717 as_bad (_("`%s%s' can't be used for write mask"),
8718 register_prefix
, mask
->reg_name
);
8724 mask_op
.mask
= mask
;
8725 mask_op
.zeroing
= 0;
8726 mask_op
.operand
= this_operand
;
8732 goto duplicated_vec_op
;
8734 i
.mask
->mask
= mask
;
8736 /* Only "{z}" is allowed here. No need to check
8737 zeroing mask explicitly. */
8738 if (i
.mask
->operand
!= this_operand
)
8740 as_bad (_("invalid write mask `%s'"), saved
);
8747 /* Check zeroing-flag for masking operation. */
8748 else if (*op_string
== 'z')
8752 mask_op
.mask
= NULL
;
8753 mask_op
.zeroing
= 1;
8754 mask_op
.operand
= this_operand
;
8759 if (i
.mask
->zeroing
)
8762 as_bad (_("duplicated `%s'"), saved
);
8766 i
.mask
->zeroing
= 1;
8768 /* Only "{%k}" is allowed here. No need to check mask
8769 register explicitly. */
8770 if (i
.mask
->operand
!= this_operand
)
8772 as_bad (_("invalid zeroing-masking `%s'"),
8781 goto unknown_vec_op
;
8783 if (*op_string
!= '}')
8785 as_bad (_("missing `}' in `%s'"), saved
);
8790 /* Strip whitespace since the addition of pseudo prefixes
8791 changed how the scrubber treats '{'. */
8792 if (is_space_char (*op_string
))
8798 /* We don't know this one. */
8799 as_bad (_("unknown vector operation: `%s'"), saved
);
8803 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8805 as_bad (_("zeroing-masking only allowed with write mask"));
8813 i386_immediate (char *imm_start
)
8815 char *save_input_line_pointer
;
8816 char *gotfree_input_line
;
8819 i386_operand_type types
;
8821 operand_type_set (&types
, ~0);
8823 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8825 as_bad (_("at most %d immediate operands are allowed"),
8826 MAX_IMMEDIATE_OPERANDS
);
8830 exp
= &im_expressions
[i
.imm_operands
++];
8831 i
.op
[this_operand
].imms
= exp
;
8833 if (is_space_char (*imm_start
))
8836 save_input_line_pointer
= input_line_pointer
;
8837 input_line_pointer
= imm_start
;
8839 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8840 if (gotfree_input_line
)
8841 input_line_pointer
= gotfree_input_line
;
8843 exp_seg
= expression (exp
);
8847 /* Handle vector operations. */
8848 if (*input_line_pointer
== '{')
8850 input_line_pointer
= check_VecOperations (input_line_pointer
,
8852 if (input_line_pointer
== NULL
)
8856 if (*input_line_pointer
)
8857 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8859 input_line_pointer
= save_input_line_pointer
;
8860 if (gotfree_input_line
)
8862 free (gotfree_input_line
);
8864 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8865 exp
->X_op
= O_illegal
;
8868 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8872 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8873 i386_operand_type types
, const char *imm_start
)
8875 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8878 as_bad (_("missing or invalid immediate expression `%s'"),
8882 else if (exp
->X_op
== O_constant
)
8884 /* Size it properly later. */
8885 i
.types
[this_operand
].bitfield
.imm64
= 1;
8886 /* If not 64bit, sign extend val. */
8887 if (flag_code
!= CODE_64BIT
8888 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8890 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8892 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8893 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8894 && exp_seg
!= absolute_section
8895 && exp_seg
!= text_section
8896 && exp_seg
!= data_section
8897 && exp_seg
!= bss_section
8898 && exp_seg
!= undefined_section
8899 && !bfd_is_com_section (exp_seg
))
8901 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8905 else if (!intel_syntax
&& exp_seg
== reg_section
)
8908 as_bad (_("illegal immediate register operand %s"), imm_start
);
8913 /* This is an address. The size of the address will be
8914 determined later, depending on destination register,
8915 suffix, or the default for the section. */
8916 i
.types
[this_operand
].bitfield
.imm8
= 1;
8917 i
.types
[this_operand
].bitfield
.imm16
= 1;
8918 i
.types
[this_operand
].bitfield
.imm32
= 1;
8919 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8920 i
.types
[this_operand
].bitfield
.imm64
= 1;
8921 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8929 i386_scale (char *scale
)
8932 char *save
= input_line_pointer
;
8934 input_line_pointer
= scale
;
8935 val
= get_absolute_expression ();
8940 i
.log2_scale_factor
= 0;
8943 i
.log2_scale_factor
= 1;
8946 i
.log2_scale_factor
= 2;
8949 i
.log2_scale_factor
= 3;
8953 char sep
= *input_line_pointer
;
8955 *input_line_pointer
= '\0';
8956 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8958 *input_line_pointer
= sep
;
8959 input_line_pointer
= save
;
8963 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8965 as_warn (_("scale factor of %d without an index register"),
8966 1 << i
.log2_scale_factor
);
8967 i
.log2_scale_factor
= 0;
8969 scale
= input_line_pointer
;
8970 input_line_pointer
= save
;
8975 i386_displacement (char *disp_start
, char *disp_end
)
8979 char *save_input_line_pointer
;
8980 char *gotfree_input_line
;
8982 i386_operand_type bigdisp
, types
= anydisp
;
8985 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8987 as_bad (_("at most %d displacement operands are allowed"),
8988 MAX_MEMORY_OPERANDS
);
8992 operand_type_set (&bigdisp
, 0);
8993 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8994 || (!current_templates
->start
->opcode_modifier
.jump
8995 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8997 bigdisp
.bitfield
.disp32
= 1;
8998 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8999 if (flag_code
== CODE_64BIT
)
9003 bigdisp
.bitfield
.disp32s
= 1;
9004 bigdisp
.bitfield
.disp64
= 1;
9007 else if ((flag_code
== CODE_16BIT
) ^ override
)
9009 bigdisp
.bitfield
.disp32
= 0;
9010 bigdisp
.bitfield
.disp16
= 1;
9015 /* For PC-relative branches, the width of the displacement
9016 is dependent upon data size, not address size. */
9017 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9018 if (flag_code
== CODE_64BIT
)
9020 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9021 bigdisp
.bitfield
.disp16
= 1;
9024 bigdisp
.bitfield
.disp32
= 1;
9025 bigdisp
.bitfield
.disp32s
= 1;
9031 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9033 : LONG_MNEM_SUFFIX
));
9034 bigdisp
.bitfield
.disp32
= 1;
9035 if ((flag_code
== CODE_16BIT
) ^ override
)
9037 bigdisp
.bitfield
.disp32
= 0;
9038 bigdisp
.bitfield
.disp16
= 1;
9042 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9045 exp
= &disp_expressions
[i
.disp_operands
];
9046 i
.op
[this_operand
].disps
= exp
;
9048 save_input_line_pointer
= input_line_pointer
;
9049 input_line_pointer
= disp_start
;
9050 END_STRING_AND_SAVE (disp_end
);
9052 #ifndef GCC_ASM_O_HACK
9053 #define GCC_ASM_O_HACK 0
9056 END_STRING_AND_SAVE (disp_end
+ 1);
9057 if (i
.types
[this_operand
].bitfield
.baseIndex
9058 && displacement_string_end
[-1] == '+')
9060 /* This hack is to avoid a warning when using the "o"
9061 constraint within gcc asm statements.
9064 #define _set_tssldt_desc(n,addr,limit,type) \
9065 __asm__ __volatile__ ( \
9067 "movw %w1,2+%0\n\t" \
9069 "movb %b1,4+%0\n\t" \
9070 "movb %4,5+%0\n\t" \
9071 "movb $0,6+%0\n\t" \
9072 "movb %h1,7+%0\n\t" \
9074 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9076 This works great except that the output assembler ends
9077 up looking a bit weird if it turns out that there is
9078 no offset. You end up producing code that looks like:
9091 So here we provide the missing zero. */
9093 *displacement_string_end
= '0';
9096 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9097 if (gotfree_input_line
)
9098 input_line_pointer
= gotfree_input_line
;
9100 exp_seg
= expression (exp
);
9103 if (*input_line_pointer
)
9104 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9106 RESTORE_END_STRING (disp_end
+ 1);
9108 input_line_pointer
= save_input_line_pointer
;
9109 if (gotfree_input_line
)
9111 free (gotfree_input_line
);
9113 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9114 exp
->X_op
= O_illegal
;
9117 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9119 RESTORE_END_STRING (disp_end
);
9125 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9126 i386_operand_type types
, const char *disp_start
)
9128 i386_operand_type bigdisp
;
9131 /* We do this to make sure that the section symbol is in
9132 the symbol table. We will ultimately change the relocation
9133 to be relative to the beginning of the section. */
9134 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9135 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9136 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9138 if (exp
->X_op
!= O_symbol
)
9141 if (S_IS_LOCAL (exp
->X_add_symbol
)
9142 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9143 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9144 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9145 exp
->X_op
= O_subtract
;
9146 exp
->X_op_symbol
= GOT_symbol
;
9147 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9148 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9149 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9150 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9152 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9155 else if (exp
->X_op
== O_absent
9156 || exp
->X_op
== O_illegal
9157 || exp
->X_op
== O_big
)
9160 as_bad (_("missing or invalid displacement expression `%s'"),
9165 else if (flag_code
== CODE_64BIT
9166 && !i
.prefix
[ADDR_PREFIX
]
9167 && exp
->X_op
== O_constant
)
9169 /* Since displacement is signed extended to 64bit, don't allow
9170 disp32 and turn off disp32s if they are out of range. */
9171 i
.types
[this_operand
].bitfield
.disp32
= 0;
9172 if (!fits_in_signed_long (exp
->X_add_number
))
9174 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9175 if (i
.types
[this_operand
].bitfield
.baseindex
)
9177 as_bad (_("0x%lx out range of signed 32bit displacement"),
9178 (long) exp
->X_add_number
);
9184 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9185 else if (exp
->X_op
!= O_constant
9186 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9187 && exp_seg
!= absolute_section
9188 && exp_seg
!= text_section
9189 && exp_seg
!= data_section
9190 && exp_seg
!= bss_section
9191 && exp_seg
!= undefined_section
9192 && !bfd_is_com_section (exp_seg
))
9194 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9199 /* Check if this is a displacement only operand. */
9200 bigdisp
= i
.types
[this_operand
];
9201 bigdisp
.bitfield
.disp8
= 0;
9202 bigdisp
.bitfield
.disp16
= 0;
9203 bigdisp
.bitfield
.disp32
= 0;
9204 bigdisp
.bitfield
.disp32s
= 0;
9205 bigdisp
.bitfield
.disp64
= 0;
9206 if (operand_type_all_zero (&bigdisp
))
9207 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9213 /* Return the active addressing mode, taking address override and
9214 registers forming the address into consideration. Update the
9215 address override prefix if necessary. */
9217 static enum flag_code
9218 i386_addressing_mode (void)
9220 enum flag_code addr_mode
;
9222 if (i
.prefix
[ADDR_PREFIX
])
9223 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9226 addr_mode
= flag_code
;
9228 #if INFER_ADDR_PREFIX
9229 if (i
.mem_operands
== 0)
9231 /* Infer address prefix from the first memory operand. */
9232 const reg_entry
*addr_reg
= i
.base_reg
;
9234 if (addr_reg
== NULL
)
9235 addr_reg
= i
.index_reg
;
9239 if (addr_reg
->reg_type
.bitfield
.dword
)
9240 addr_mode
= CODE_32BIT
;
9241 else if (flag_code
!= CODE_64BIT
9242 && addr_reg
->reg_type
.bitfield
.word
)
9243 addr_mode
= CODE_16BIT
;
9245 if (addr_mode
!= flag_code
)
9247 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9249 /* Change the size of any displacement too. At most one
9250 of Disp16 or Disp32 is set.
9251 FIXME. There doesn't seem to be any real need for
9252 separate Disp16 and Disp32 flags. The same goes for
9253 Imm16 and Imm32. Removing them would probably clean
9254 up the code quite a lot. */
9255 if (flag_code
!= CODE_64BIT
9256 && (i
.types
[this_operand
].bitfield
.disp16
9257 || i
.types
[this_operand
].bitfield
.disp32
))
9258 i
.types
[this_operand
]
9259 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9269 /* Make sure the memory operand we've been dealt is valid.
9270 Return 1 on success, 0 on a failure. */
9273 i386_index_check (const char *operand_string
)
9275 const char *kind
= "base/index";
9276 enum flag_code addr_mode
= i386_addressing_mode ();
9278 if (current_templates
->start
->opcode_modifier
.isstring
9279 && !current_templates
->start
->opcode_modifier
.immext
9280 && (current_templates
->end
[-1].opcode_modifier
.isstring
9283 /* Memory operands of string insns are special in that they only allow
9284 a single register (rDI, rSI, or rBX) as their memory address. */
9285 const reg_entry
*expected_reg
;
9286 static const char *di_si
[][2] =
9292 static const char *bx
[] = { "ebx", "bx", "rbx" };
9294 kind
= "string address";
9296 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9298 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9300 if (!type
.bitfield
.baseindex
9301 || ((!i
.mem_operands
!= !intel_syntax
)
9302 && current_templates
->end
[-1].operand_types
[1]
9303 .bitfield
.baseindex
))
9304 type
= current_templates
->end
[-1].operand_types
[1];
9305 expected_reg
= hash_find (reg_hash
,
9306 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9310 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9312 if (i
.base_reg
!= expected_reg
9314 || operand_type_check (i
.types
[this_operand
], disp
))
9316 /* The second memory operand must have the same size as
9320 && !((addr_mode
== CODE_64BIT
9321 && i
.base_reg
->reg_type
.bitfield
.qword
)
9322 || (addr_mode
== CODE_32BIT
9323 ? i
.base_reg
->reg_type
.bitfield
.dword
9324 : i
.base_reg
->reg_type
.bitfield
.word
)))
9327 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9329 intel_syntax
? '[' : '(',
9331 expected_reg
->reg_name
,
9332 intel_syntax
? ']' : ')');
9339 as_bad (_("`%s' is not a valid %s expression"),
9340 operand_string
, kind
);
9345 if (addr_mode
!= CODE_16BIT
)
9347 /* 32-bit/64-bit checks. */
9349 && ((addr_mode
== CODE_64BIT
9350 ? !i
.base_reg
->reg_type
.bitfield
.qword
9351 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9352 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9353 || i
.base_reg
->reg_num
== RegIZ
))
9355 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9356 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9357 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9358 && ((addr_mode
== CODE_64BIT
9359 ? !i
.index_reg
->reg_type
.bitfield
.qword
9360 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9361 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9364 /* bndmk, bndldx, and bndstx have special restrictions. */
9365 if (current_templates
->start
->base_opcode
== 0xf30f1b
9366 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9368 /* They cannot use RIP-relative addressing. */
9369 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9371 as_bad (_("`%s' cannot be used here"), operand_string
);
9375 /* bndldx and bndstx ignore their scale factor. */
9376 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9377 && i
.log2_scale_factor
)
9378 as_warn (_("register scaling is being ignored here"));
9383 /* 16-bit checks. */
9385 && (!i
.base_reg
->reg_type
.bitfield
.word
9386 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9388 && (!i
.index_reg
->reg_type
.bitfield
.word
9389 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9391 && i
.base_reg
->reg_num
< 6
9392 && i
.index_reg
->reg_num
>= 6
9393 && i
.log2_scale_factor
== 0))))
9400 /* Handle vector immediates. */
9403 RC_SAE_immediate (const char *imm_start
)
9405 unsigned int match_found
, j
;
9406 const char *pstr
= imm_start
;
9414 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9416 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9420 rc_op
.type
= RC_NamesTable
[j
].type
;
9421 rc_op
.operand
= this_operand
;
9422 i
.rounding
= &rc_op
;
9426 as_bad (_("duplicated `%s'"), imm_start
);
9429 pstr
+= RC_NamesTable
[j
].len
;
9439 as_bad (_("Missing '}': '%s'"), imm_start
);
9442 /* RC/SAE immediate string should contain nothing more. */;
9445 as_bad (_("Junk after '}': '%s'"), imm_start
);
9449 exp
= &im_expressions
[i
.imm_operands
++];
9450 i
.op
[this_operand
].imms
= exp
;
9452 exp
->X_op
= O_constant
;
9453 exp
->X_add_number
= 0;
9454 exp
->X_add_symbol
= (symbolS
*) 0;
9455 exp
->X_op_symbol
= (symbolS
*) 0;
9457 i
.types
[this_operand
].bitfield
.imm8
= 1;
9461 /* Only string instructions can have a second memory operand, so
9462 reduce current_templates to just those if it contains any. */
9464 maybe_adjust_templates (void)
9466 const insn_template
*t
;
9468 gas_assert (i
.mem_operands
== 1);
9470 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9471 if (t
->opcode_modifier
.isstring
)
9474 if (t
< current_templates
->end
)
9476 static templates aux_templates
;
9477 bfd_boolean recheck
;
9479 aux_templates
.start
= t
;
9480 for (; t
< current_templates
->end
; ++t
)
9481 if (!t
->opcode_modifier
.isstring
)
9483 aux_templates
.end
= t
;
9485 /* Determine whether to re-check the first memory operand. */
9486 recheck
= (aux_templates
.start
!= current_templates
->start
9487 || t
!= current_templates
->end
);
9489 current_templates
= &aux_templates
;
9494 if (i
.memop1_string
!= NULL
9495 && i386_index_check (i
.memop1_string
) == 0)
9504 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9508 i386_att_operand (char *operand_string
)
9512 char *op_string
= operand_string
;
9514 if (is_space_char (*op_string
))
9517 /* We check for an absolute prefix (differentiating,
9518 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9519 if (*op_string
== ABSOLUTE_PREFIX
)
9522 if (is_space_char (*op_string
))
9524 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9527 /* Check if operand is a register. */
9528 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9530 i386_operand_type temp
;
9532 /* Check for a segment override by searching for ':' after a
9533 segment register. */
9535 if (is_space_char (*op_string
))
9537 if (*op_string
== ':'
9538 && (r
->reg_type
.bitfield
.sreg2
9539 || r
->reg_type
.bitfield
.sreg3
))
9544 i
.seg
[i
.mem_operands
] = &es
;
9547 i
.seg
[i
.mem_operands
] = &cs
;
9550 i
.seg
[i
.mem_operands
] = &ss
;
9553 i
.seg
[i
.mem_operands
] = &ds
;
9556 i
.seg
[i
.mem_operands
] = &fs
;
9559 i
.seg
[i
.mem_operands
] = &gs
;
9563 /* Skip the ':' and whitespace. */
9565 if (is_space_char (*op_string
))
9568 if (!is_digit_char (*op_string
)
9569 && !is_identifier_char (*op_string
)
9570 && *op_string
!= '('
9571 && *op_string
!= ABSOLUTE_PREFIX
)
9573 as_bad (_("bad memory operand `%s'"), op_string
);
9576 /* Handle case of %es:*foo. */
9577 if (*op_string
== ABSOLUTE_PREFIX
)
9580 if (is_space_char (*op_string
))
9582 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9584 goto do_memory_reference
;
9587 /* Handle vector operations. */
9588 if (*op_string
== '{')
9590 op_string
= check_VecOperations (op_string
, NULL
);
9591 if (op_string
== NULL
)
9597 as_bad (_("junk `%s' after register"), op_string
);
9601 temp
.bitfield
.baseindex
= 0;
9602 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9604 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9605 i
.op
[this_operand
].regs
= r
;
9608 else if (*op_string
== REGISTER_PREFIX
)
9610 as_bad (_("bad register name `%s'"), op_string
);
9613 else if (*op_string
== IMMEDIATE_PREFIX
)
9616 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9618 as_bad (_("immediate operand illegal with absolute jump"));
9621 if (!i386_immediate (op_string
))
9624 else if (RC_SAE_immediate (operand_string
))
9626 /* If it is a RC or SAE immediate, do nothing. */
9629 else if (is_digit_char (*op_string
)
9630 || is_identifier_char (*op_string
)
9631 || *op_string
== '"'
9632 || *op_string
== '(')
9634 /* This is a memory reference of some sort. */
9637 /* Start and end of displacement string expression (if found). */
9638 char *displacement_string_start
;
9639 char *displacement_string_end
;
9642 do_memory_reference
:
9643 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9645 if ((i
.mem_operands
== 1
9646 && !current_templates
->start
->opcode_modifier
.isstring
)
9647 || i
.mem_operands
== 2)
9649 as_bad (_("too many memory references for `%s'"),
9650 current_templates
->start
->name
);
9654 /* Check for base index form. We detect the base index form by
9655 looking for an ')' at the end of the operand, searching
9656 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9658 base_string
= op_string
+ strlen (op_string
);
9660 /* Handle vector operations. */
9661 vop_start
= strchr (op_string
, '{');
9662 if (vop_start
&& vop_start
< base_string
)
9664 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9666 base_string
= vop_start
;
9670 if (is_space_char (*base_string
))
9673 /* If we only have a displacement, set-up for it to be parsed later. */
9674 displacement_string_start
= op_string
;
9675 displacement_string_end
= base_string
+ 1;
9677 if (*base_string
== ')')
9680 unsigned int parens_balanced
= 1;
9681 /* We've already checked that the number of left & right ()'s are
9682 equal, so this loop will not be infinite. */
9686 if (*base_string
== ')')
9688 if (*base_string
== '(')
9691 while (parens_balanced
);
9693 temp_string
= base_string
;
9695 /* Skip past '(' and whitespace. */
9697 if (is_space_char (*base_string
))
9700 if (*base_string
== ','
9701 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9704 displacement_string_end
= temp_string
;
9706 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9710 base_string
= end_op
;
9711 if (is_space_char (*base_string
))
9715 /* There may be an index reg or scale factor here. */
9716 if (*base_string
== ',')
9719 if (is_space_char (*base_string
))
9722 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9725 base_string
= end_op
;
9726 if (is_space_char (*base_string
))
9728 if (*base_string
== ',')
9731 if (is_space_char (*base_string
))
9734 else if (*base_string
!= ')')
9736 as_bad (_("expecting `,' or `)' "
9737 "after index register in `%s'"),
9742 else if (*base_string
== REGISTER_PREFIX
)
9744 end_op
= strchr (base_string
, ',');
9747 as_bad (_("bad register name `%s'"), base_string
);
9751 /* Check for scale factor. */
9752 if (*base_string
!= ')')
9754 char *end_scale
= i386_scale (base_string
);
9759 base_string
= end_scale
;
9760 if (is_space_char (*base_string
))
9762 if (*base_string
!= ')')
9764 as_bad (_("expecting `)' "
9765 "after scale factor in `%s'"),
9770 else if (!i
.index_reg
)
9772 as_bad (_("expecting index register or scale factor "
9773 "after `,'; got '%c'"),
9778 else if (*base_string
!= ')')
9780 as_bad (_("expecting `,' or `)' "
9781 "after base register in `%s'"),
9786 else if (*base_string
== REGISTER_PREFIX
)
9788 end_op
= strchr (base_string
, ',');
9791 as_bad (_("bad register name `%s'"), base_string
);
9796 /* If there's an expression beginning the operand, parse it,
9797 assuming displacement_string_start and
9798 displacement_string_end are meaningful. */
9799 if (displacement_string_start
!= displacement_string_end
)
9801 if (!i386_displacement (displacement_string_start
,
9802 displacement_string_end
))
9806 /* Special case for (%dx) while doing input/output op. */
9808 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
9810 && i
.log2_scale_factor
== 0
9811 && i
.seg
[i
.mem_operands
] == 0
9812 && !operand_type_check (i
.types
[this_operand
], disp
))
9814 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
9818 if (i386_index_check (operand_string
) == 0)
9820 i
.flags
[this_operand
] |= Operand_Mem
;
9821 if (i
.mem_operands
== 0)
9822 i
.memop1_string
= xstrdup (operand_string
);
9827 /* It's not a memory operand; argh! */
9828 as_bad (_("invalid char %s beginning operand %d `%s'"),
9829 output_invalid (*op_string
),
9834 return 1; /* Normal return. */
9837 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9838 that an rs_machine_dependent frag may reach. */
9841 i386_frag_max_var (fragS
*frag
)
9843 /* The only relaxable frags are for jumps.
9844 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9845 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9846 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9851 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9853 /* STT_GNU_IFUNC symbol must go through PLT. */
9854 if ((symbol_get_bfdsym (fr_symbol
)->flags
9855 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9858 if (!S_IS_EXTERNAL (fr_symbol
))
9859 /* Symbol may be weak or local. */
9860 return !S_IS_WEAK (fr_symbol
);
9862 /* Global symbols with non-default visibility can't be preempted. */
9863 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9866 if (fr_var
!= NO_RELOC
)
9867 switch ((enum bfd_reloc_code_real
) fr_var
)
9869 case BFD_RELOC_386_PLT32
:
9870 case BFD_RELOC_X86_64_PLT32
:
9871 /* Symbol with PLT relocation may be preempted. */
9877 /* Global symbols with default visibility in a shared library may be
9878 preempted by another definition. */
9883 /* md_estimate_size_before_relax()
9885 Called just before relax() for rs_machine_dependent frags. The x86
9886 assembler uses these frags to handle variable size jump
9889 Any symbol that is now undefined will not become defined.
9890 Return the correct fr_subtype in the frag.
9891 Return the initial "guess for variable size of frag" to caller.
9892 The guess is actually the growth beyond the fixed part. Whatever
9893 we do to grow the fixed or variable part contributes to our
9897 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9899 /* We've already got fragP->fr_subtype right; all we have to do is
9900 check for un-relaxable symbols. On an ELF system, we can't relax
9901 an externally visible symbol, because it may be overridden by a
9903 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9906 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9909 #if defined (OBJ_COFF) && defined (TE_PE)
9910 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9911 && S_IS_WEAK (fragP
->fr_symbol
))
9915 /* Symbol is undefined in this segment, or we need to keep a
9916 reloc so that weak symbols can be overridden. */
9917 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9918 enum bfd_reloc_code_real reloc_type
;
9919 unsigned char *opcode
;
9922 if (fragP
->fr_var
!= NO_RELOC
)
9923 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9925 reloc_type
= BFD_RELOC_16_PCREL
;
9926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9927 else if (need_plt32_p (fragP
->fr_symbol
))
9928 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9931 reloc_type
= BFD_RELOC_32_PCREL
;
9933 old_fr_fix
= fragP
->fr_fix
;
9934 opcode
= (unsigned char *) fragP
->fr_opcode
;
9936 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9939 /* Make jmp (0xeb) a (d)word displacement jump. */
9941 fragP
->fr_fix
+= size
;
9942 fix_new (fragP
, old_fr_fix
, size
,
9944 fragP
->fr_offset
, 1,
9950 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9952 /* Negate the condition, and branch past an
9953 unconditional jump. */
9956 /* Insert an unconditional jump. */
9958 /* We added two extra opcode bytes, and have a two byte
9960 fragP
->fr_fix
+= 2 + 2;
9961 fix_new (fragP
, old_fr_fix
+ 2, 2,
9963 fragP
->fr_offset
, 1,
9970 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9975 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9977 fragP
->fr_offset
, 1,
9979 fixP
->fx_signed
= 1;
9983 /* This changes the byte-displacement jump 0x7N
9984 to the (d)word-displacement jump 0x0f,0x8N. */
9985 opcode
[1] = opcode
[0] + 0x10;
9986 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9987 /* We've added an opcode byte. */
9988 fragP
->fr_fix
+= 1 + size
;
9989 fix_new (fragP
, old_fr_fix
+ 1, size
,
9991 fragP
->fr_offset
, 1,
9996 BAD_CASE (fragP
->fr_subtype
);
10000 return fragP
->fr_fix
- old_fr_fix
;
10003 /* Guess size depending on current relax state. Initially the relax
10004 state will correspond to a short jump and we return 1, because
10005 the variable part of the frag (the branch offset) is one byte
10006 long. However, we can relax a section more than once and in that
10007 case we must either set fr_subtype back to the unrelaxed state,
10008 or return the value for the appropriate branch. */
10009 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10012 /* Called after relax() is finished.
10014 In: Address of frag.
10015 fr_type == rs_machine_dependent.
10016 fr_subtype is what the address relaxed to.
10018 Out: Any fixSs and constants are set up.
10019 Caller will turn frag into a ".space 0". */
10022 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10025 unsigned char *opcode
;
10026 unsigned char *where_to_put_displacement
= NULL
;
10027 offsetT target_address
;
10028 offsetT opcode_address
;
10029 unsigned int extension
= 0;
10030 offsetT displacement_from_opcode_start
;
10032 opcode
= (unsigned char *) fragP
->fr_opcode
;
10034 /* Address we want to reach in file space. */
10035 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10037 /* Address opcode resides at in file space. */
10038 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10040 /* Displacement from opcode start to fill into instruction. */
10041 displacement_from_opcode_start
= target_address
- opcode_address
;
10043 if ((fragP
->fr_subtype
& BIG
) == 0)
10045 /* Don't have to change opcode. */
10046 extension
= 1; /* 1 opcode + 1 displacement */
10047 where_to_put_displacement
= &opcode
[1];
10051 if (no_cond_jump_promotion
10052 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10053 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10054 _("long jump required"));
10056 switch (fragP
->fr_subtype
)
10058 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10059 extension
= 4; /* 1 opcode + 4 displacement */
10061 where_to_put_displacement
= &opcode
[1];
10064 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10065 extension
= 2; /* 1 opcode + 2 displacement */
10067 where_to_put_displacement
= &opcode
[1];
10070 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10071 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10072 extension
= 5; /* 2 opcode + 4 displacement */
10073 opcode
[1] = opcode
[0] + 0x10;
10074 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10075 where_to_put_displacement
= &opcode
[2];
10078 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10079 extension
= 3; /* 2 opcode + 2 displacement */
10080 opcode
[1] = opcode
[0] + 0x10;
10081 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10082 where_to_put_displacement
= &opcode
[2];
10085 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10090 where_to_put_displacement
= &opcode
[3];
10094 BAD_CASE (fragP
->fr_subtype
);
10099 /* If size if less then four we are sure that the operand fits,
10100 but if it's 4, then it could be that the displacement is larger
10102 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10104 && ((addressT
) (displacement_from_opcode_start
- extension
10105 + ((addressT
) 1 << 31))
10106 > (((addressT
) 2 << 31) - 1)))
10108 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10109 _("jump target out of range"));
10110 /* Make us emit 0. */
10111 displacement_from_opcode_start
= extension
;
10113 /* Now put displacement after opcode. */
10114 md_number_to_chars ((char *) where_to_put_displacement
,
10115 (valueT
) (displacement_from_opcode_start
- extension
),
10116 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10117 fragP
->fr_fix
+= extension
;
10120 /* Apply a fixup (fixP) to segment data, once it has been determined
10121 by our caller that we have all the info we need to fix it up.
10123 Parameter valP is the pointer to the value of the bits.
10125 On the 386, immediates, displacements, and data pointers are all in
10126 the same (little-endian) format, so we don't need to care about which
10127 we are handling. */
10130 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10132 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10133 valueT value
= *valP
;
10135 #if !defined (TE_Mach)
10136 if (fixP
->fx_pcrel
)
10138 switch (fixP
->fx_r_type
)
10144 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10147 case BFD_RELOC_X86_64_32S
:
10148 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10151 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10154 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10159 if (fixP
->fx_addsy
!= NULL
10160 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10161 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10162 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10163 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10164 && !use_rela_relocations
)
10166 /* This is a hack. There should be a better way to handle this.
10167 This covers for the fact that bfd_install_relocation will
10168 subtract the current location (for partial_inplace, PC relative
10169 relocations); see more below. */
10173 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10176 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10181 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10183 if ((sym_seg
== seg
10184 || (symbol_section_p (fixP
->fx_addsy
)
10185 && sym_seg
!= absolute_section
))
10186 && !generic_force_reloc (fixP
))
10188 /* Yes, we add the values in twice. This is because
10189 bfd_install_relocation subtracts them out again. I think
10190 bfd_install_relocation is broken, but I don't dare change
10192 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10196 #if defined (OBJ_COFF) && defined (TE_PE)
10197 /* For some reason, the PE format does not store a
10198 section address offset for a PC relative symbol. */
10199 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10200 || S_IS_WEAK (fixP
->fx_addsy
))
10201 value
+= md_pcrel_from (fixP
);
10204 #if defined (OBJ_COFF) && defined (TE_PE)
10205 if (fixP
->fx_addsy
!= NULL
10206 && S_IS_WEAK (fixP
->fx_addsy
)
10207 /* PR 16858: Do not modify weak function references. */
10208 && ! fixP
->fx_pcrel
)
10210 #if !defined (TE_PEP)
10211 /* For x86 PE weak function symbols are neither PC-relative
10212 nor do they set S_IS_FUNCTION. So the only reliable way
10213 to detect them is to check the flags of their containing
10215 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10216 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10220 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10224 /* Fix a few things - the dynamic linker expects certain values here,
10225 and we must not disappoint it. */
10226 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10227 if (IS_ELF
&& fixP
->fx_addsy
)
10228 switch (fixP
->fx_r_type
)
10230 case BFD_RELOC_386_PLT32
:
10231 case BFD_RELOC_X86_64_PLT32
:
10232 /* Make the jump instruction point to the address of the operand. At
10233 runtime we merely add the offset to the actual PLT entry. */
10237 case BFD_RELOC_386_TLS_GD
:
10238 case BFD_RELOC_386_TLS_LDM
:
10239 case BFD_RELOC_386_TLS_IE_32
:
10240 case BFD_RELOC_386_TLS_IE
:
10241 case BFD_RELOC_386_TLS_GOTIE
:
10242 case BFD_RELOC_386_TLS_GOTDESC
:
10243 case BFD_RELOC_X86_64_TLSGD
:
10244 case BFD_RELOC_X86_64_TLSLD
:
10245 case BFD_RELOC_X86_64_GOTTPOFF
:
10246 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10247 value
= 0; /* Fully resolved at runtime. No addend. */
10249 case BFD_RELOC_386_TLS_LE
:
10250 case BFD_RELOC_386_TLS_LDO_32
:
10251 case BFD_RELOC_386_TLS_LE_32
:
10252 case BFD_RELOC_X86_64_DTPOFF32
:
10253 case BFD_RELOC_X86_64_DTPOFF64
:
10254 case BFD_RELOC_X86_64_TPOFF32
:
10255 case BFD_RELOC_X86_64_TPOFF64
:
10256 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10259 case BFD_RELOC_386_TLS_DESC_CALL
:
10260 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10261 value
= 0; /* Fully resolved at runtime. No addend. */
10262 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10266 case BFD_RELOC_VTABLE_INHERIT
:
10267 case BFD_RELOC_VTABLE_ENTRY
:
10274 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10276 #endif /* !defined (TE_Mach) */
10278 /* Are we finished with this relocation now? */
10279 if (fixP
->fx_addsy
== NULL
)
10281 #if defined (OBJ_COFF) && defined (TE_PE)
10282 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10285 /* Remember value for tc_gen_reloc. */
10286 fixP
->fx_addnumber
= value
;
10287 /* Clear out the frag for now. */
10291 else if (use_rela_relocations
)
10293 fixP
->fx_no_overflow
= 1;
10294 /* Remember value for tc_gen_reloc. */
10295 fixP
->fx_addnumber
= value
;
10299 md_number_to_chars (p
, value
, fixP
->fx_size
);
10303 md_atof (int type
, char *litP
, int *sizeP
)
10305 /* This outputs the LITTLENUMs in REVERSE order;
10306 in accord with the bigendian 386. */
10307 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10310 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10313 output_invalid (int c
)
10316 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10319 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10320 "(0x%x)", (unsigned char) c
);
10321 return output_invalid_buf
;
10324 /* REG_STRING starts *before* REGISTER_PREFIX. */
10326 static const reg_entry
*
10327 parse_real_register (char *reg_string
, char **end_op
)
10329 char *s
= reg_string
;
10331 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10332 const reg_entry
*r
;
10334 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10335 if (*s
== REGISTER_PREFIX
)
10338 if (is_space_char (*s
))
10341 p
= reg_name_given
;
10342 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10344 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10345 return (const reg_entry
*) NULL
;
10349 /* For naked regs, make sure that we are not dealing with an identifier.
10350 This prevents confusing an identifier like `eax_var' with register
10352 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10353 return (const reg_entry
*) NULL
;
10357 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10359 /* Handle floating point regs, allowing spaces in the (i) part. */
10360 if (r
== i386_regtab
/* %st is first entry of table */)
10362 if (!cpu_arch_flags
.bitfield
.cpu8087
10363 && !cpu_arch_flags
.bitfield
.cpu287
10364 && !cpu_arch_flags
.bitfield
.cpu387
)
10365 return (const reg_entry
*) NULL
;
10367 if (is_space_char (*s
))
10372 if (is_space_char (*s
))
10374 if (*s
>= '0' && *s
<= '7')
10376 int fpr
= *s
- '0';
10378 if (is_space_char (*s
))
10383 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10388 /* We have "%st(" then garbage. */
10389 return (const reg_entry
*) NULL
;
10393 if (r
== NULL
|| allow_pseudo_reg
)
10396 if (operand_type_all_zero (&r
->reg_type
))
10397 return (const reg_entry
*) NULL
;
10399 if ((r
->reg_type
.bitfield
.dword
10400 || r
->reg_type
.bitfield
.sreg3
10401 || r
->reg_type
.bitfield
.control
10402 || r
->reg_type
.bitfield
.debug
10403 || r
->reg_type
.bitfield
.test
)
10404 && !cpu_arch_flags
.bitfield
.cpui386
)
10405 return (const reg_entry
*) NULL
;
10407 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10408 return (const reg_entry
*) NULL
;
10410 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10412 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10413 return (const reg_entry
*) NULL
;
10415 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10417 if (r
->reg_type
.bitfield
.ymmword
)
10418 return (const reg_entry
*) NULL
;
10420 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10421 return (const reg_entry
*) NULL
;
10425 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10426 return (const reg_entry
*) NULL
;
10428 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10429 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10430 return (const reg_entry
*) NULL
;
10432 /* Upper 16 vector registers are only available with VREX in 64bit
10433 mode, and require EVEX encoding. */
10434 if (r
->reg_flags
& RegVRex
)
10436 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10437 || flag_code
!= CODE_64BIT
)
10438 return (const reg_entry
*) NULL
;
10440 i
.vec_encoding
= vex_encoding_evex
;
10443 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10444 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10445 && flag_code
!= CODE_64BIT
)
10446 return (const reg_entry
*) NULL
;
10448 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10449 return (const reg_entry
*) NULL
;
10454 /* REG_STRING starts *before* REGISTER_PREFIX. */
10456 static const reg_entry
*
10457 parse_register (char *reg_string
, char **end_op
)
10459 const reg_entry
*r
;
10461 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10462 r
= parse_real_register (reg_string
, end_op
);
10467 char *save
= input_line_pointer
;
10471 input_line_pointer
= reg_string
;
10472 c
= get_symbol_name (®_string
);
10473 symbolP
= symbol_find (reg_string
);
10474 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10476 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10478 know (e
->X_op
== O_register
);
10479 know (e
->X_add_number
>= 0
10480 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10481 r
= i386_regtab
+ e
->X_add_number
;
10482 if ((r
->reg_flags
& RegVRex
))
10483 i
.vec_encoding
= vex_encoding_evex
;
10484 *end_op
= input_line_pointer
;
10486 *input_line_pointer
= c
;
10487 input_line_pointer
= save
;
10493 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10495 const reg_entry
*r
;
10496 char *end
= input_line_pointer
;
10499 r
= parse_register (name
, &input_line_pointer
);
10500 if (r
&& end
<= input_line_pointer
)
10502 *nextcharP
= *input_line_pointer
;
10503 *input_line_pointer
= 0;
10504 e
->X_op
= O_register
;
10505 e
->X_add_number
= r
- i386_regtab
;
10508 input_line_pointer
= end
;
10510 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10514 md_operand (expressionS
*e
)
10517 const reg_entry
*r
;
10519 switch (*input_line_pointer
)
10521 case REGISTER_PREFIX
:
10522 r
= parse_real_register (input_line_pointer
, &end
);
10525 e
->X_op
= O_register
;
10526 e
->X_add_number
= r
- i386_regtab
;
10527 input_line_pointer
= end
;
10532 gas_assert (intel_syntax
);
10533 end
= input_line_pointer
++;
10535 if (*input_line_pointer
== ']')
10537 ++input_line_pointer
;
10538 e
->X_op_symbol
= make_expr_symbol (e
);
10539 e
->X_add_symbol
= NULL
;
10540 e
->X_add_number
= 0;
10545 e
->X_op
= O_absent
;
10546 input_line_pointer
= end
;
10553 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10554 const char *md_shortopts
= "kVQ:sqnO::";
10556 const char *md_shortopts
= "qnO::";
10559 #define OPTION_32 (OPTION_MD_BASE + 0)
10560 #define OPTION_64 (OPTION_MD_BASE + 1)
10561 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10562 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10563 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10564 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10565 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10566 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10567 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10568 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10569 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10570 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10571 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10572 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10573 #define OPTION_X32 (OPTION_MD_BASE + 14)
10574 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10575 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10576 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10577 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10578 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10579 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10580 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10581 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10582 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10583 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10585 struct option md_longopts
[] =
10587 {"32", no_argument
, NULL
, OPTION_32
},
10588 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10589 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10590 {"64", no_argument
, NULL
, OPTION_64
},
10592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10593 {"x32", no_argument
, NULL
, OPTION_X32
},
10594 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10596 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10597 {"march", required_argument
, NULL
, OPTION_MARCH
},
10598 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10599 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10600 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10601 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10602 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10603 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10604 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10605 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10606 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10607 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10608 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10609 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10610 # if defined (TE_PE) || defined (TE_PEP)
10611 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10613 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10614 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10615 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10616 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10617 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10618 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10619 {NULL
, no_argument
, NULL
, 0}
10621 size_t md_longopts_size
= sizeof (md_longopts
);
10624 md_parse_option (int c
, const char *arg
)
10627 char *arch
, *next
, *saved
;
10632 optimize_align_code
= 0;
10636 quiet_warnings
= 1;
10639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10640 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10641 should be emitted or not. FIXME: Not implemented. */
10645 /* -V: SVR4 argument to print version ID. */
10647 print_version_id ();
10650 /* -k: Ignore for FreeBSD compatibility. */
10655 /* -s: On i386 Solaris, this tells the native assembler to use
10656 .stab instead of .stab.excl. We always use .stab anyhow. */
10659 case OPTION_MSHARED
:
10663 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10664 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10667 const char **list
, **l
;
10669 list
= bfd_target_list ();
10670 for (l
= list
; *l
!= NULL
; l
++)
10671 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10672 || strcmp (*l
, "coff-x86-64") == 0
10673 || strcmp (*l
, "pe-x86-64") == 0
10674 || strcmp (*l
, "pei-x86-64") == 0
10675 || strcmp (*l
, "mach-o-x86-64") == 0)
10677 default_arch
= "x86_64";
10681 as_fatal (_("no compiled in support for x86_64"));
10687 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10691 const char **list
, **l
;
10693 list
= bfd_target_list ();
10694 for (l
= list
; *l
!= NULL
; l
++)
10695 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10697 default_arch
= "x86_64:32";
10701 as_fatal (_("no compiled in support for 32bit x86_64"));
10705 as_fatal (_("32bit x86_64 is only supported for ELF"));
10710 default_arch
= "i386";
10713 case OPTION_DIVIDE
:
10714 #ifdef SVR4_COMMENT_CHARS
10719 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10721 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10725 i386_comment_chars
= n
;
10731 saved
= xstrdup (arg
);
10733 /* Allow -march=+nosse. */
10739 as_fatal (_("invalid -march= option: `%s'"), arg
);
10740 next
= strchr (arch
, '+');
10743 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10745 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10748 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10751 cpu_arch_name
= cpu_arch
[j
].name
;
10752 cpu_sub_arch_name
= NULL
;
10753 cpu_arch_flags
= cpu_arch
[j
].flags
;
10754 cpu_arch_isa
= cpu_arch
[j
].type
;
10755 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10756 if (!cpu_arch_tune_set
)
10758 cpu_arch_tune
= cpu_arch_isa
;
10759 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10763 else if (*cpu_arch
[j
].name
== '.'
10764 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10766 /* ISA extension. */
10767 i386_cpu_flags flags
;
10769 flags
= cpu_flags_or (cpu_arch_flags
,
10770 cpu_arch
[j
].flags
);
10772 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10774 if (cpu_sub_arch_name
)
10776 char *name
= cpu_sub_arch_name
;
10777 cpu_sub_arch_name
= concat (name
,
10779 (const char *) NULL
);
10783 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10784 cpu_arch_flags
= flags
;
10785 cpu_arch_isa_flags
= flags
;
10789 = cpu_flags_or (cpu_arch_isa_flags
,
10790 cpu_arch
[j
].flags
);
10795 if (j
>= ARRAY_SIZE (cpu_arch
))
10797 /* Disable an ISA extension. */
10798 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10799 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10801 i386_cpu_flags flags
;
10803 flags
= cpu_flags_and_not (cpu_arch_flags
,
10804 cpu_noarch
[j
].flags
);
10805 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10807 if (cpu_sub_arch_name
)
10809 char *name
= cpu_sub_arch_name
;
10810 cpu_sub_arch_name
= concat (arch
,
10811 (const char *) NULL
);
10815 cpu_sub_arch_name
= xstrdup (arch
);
10816 cpu_arch_flags
= flags
;
10817 cpu_arch_isa_flags
= flags
;
10822 if (j
>= ARRAY_SIZE (cpu_noarch
))
10823 j
= ARRAY_SIZE (cpu_arch
);
10826 if (j
>= ARRAY_SIZE (cpu_arch
))
10827 as_fatal (_("invalid -march= option: `%s'"), arg
);
10831 while (next
!= NULL
);
10837 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10838 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10840 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10842 cpu_arch_tune_set
= 1;
10843 cpu_arch_tune
= cpu_arch
[j
].type
;
10844 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10848 if (j
>= ARRAY_SIZE (cpu_arch
))
10849 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10852 case OPTION_MMNEMONIC
:
10853 if (strcasecmp (arg
, "att") == 0)
10854 intel_mnemonic
= 0;
10855 else if (strcasecmp (arg
, "intel") == 0)
10856 intel_mnemonic
= 1;
10858 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10861 case OPTION_MSYNTAX
:
10862 if (strcasecmp (arg
, "att") == 0)
10864 else if (strcasecmp (arg
, "intel") == 0)
10867 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10870 case OPTION_MINDEX_REG
:
10871 allow_index_reg
= 1;
10874 case OPTION_MNAKED_REG
:
10875 allow_naked_reg
= 1;
10878 case OPTION_MSSE2AVX
:
10882 case OPTION_MSSE_CHECK
:
10883 if (strcasecmp (arg
, "error") == 0)
10884 sse_check
= check_error
;
10885 else if (strcasecmp (arg
, "warning") == 0)
10886 sse_check
= check_warning
;
10887 else if (strcasecmp (arg
, "none") == 0)
10888 sse_check
= check_none
;
10890 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10893 case OPTION_MOPERAND_CHECK
:
10894 if (strcasecmp (arg
, "error") == 0)
10895 operand_check
= check_error
;
10896 else if (strcasecmp (arg
, "warning") == 0)
10897 operand_check
= check_warning
;
10898 else if (strcasecmp (arg
, "none") == 0)
10899 operand_check
= check_none
;
10901 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10904 case OPTION_MAVXSCALAR
:
10905 if (strcasecmp (arg
, "128") == 0)
10906 avxscalar
= vex128
;
10907 else if (strcasecmp (arg
, "256") == 0)
10908 avxscalar
= vex256
;
10910 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10913 case OPTION_MADD_BND_PREFIX
:
10914 add_bnd_prefix
= 1;
10917 case OPTION_MEVEXLIG
:
10918 if (strcmp (arg
, "128") == 0)
10919 evexlig
= evexl128
;
10920 else if (strcmp (arg
, "256") == 0)
10921 evexlig
= evexl256
;
10922 else if (strcmp (arg
, "512") == 0)
10923 evexlig
= evexl512
;
10925 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10928 case OPTION_MEVEXRCIG
:
10929 if (strcmp (arg
, "rne") == 0)
10931 else if (strcmp (arg
, "rd") == 0)
10933 else if (strcmp (arg
, "ru") == 0)
10935 else if (strcmp (arg
, "rz") == 0)
10938 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10941 case OPTION_MEVEXWIG
:
10942 if (strcmp (arg
, "0") == 0)
10944 else if (strcmp (arg
, "1") == 0)
10947 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10950 # if defined (TE_PE) || defined (TE_PEP)
10951 case OPTION_MBIG_OBJ
:
10956 case OPTION_MOMIT_LOCK_PREFIX
:
10957 if (strcasecmp (arg
, "yes") == 0)
10958 omit_lock_prefix
= 1;
10959 else if (strcasecmp (arg
, "no") == 0)
10960 omit_lock_prefix
= 0;
10962 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10965 case OPTION_MFENCE_AS_LOCK_ADD
:
10966 if (strcasecmp (arg
, "yes") == 0)
10968 else if (strcasecmp (arg
, "no") == 0)
10971 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10974 case OPTION_MRELAX_RELOCATIONS
:
10975 if (strcasecmp (arg
, "yes") == 0)
10976 generate_relax_relocations
= 1;
10977 else if (strcasecmp (arg
, "no") == 0)
10978 generate_relax_relocations
= 0;
10980 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10983 case OPTION_MAMD64
:
10987 case OPTION_MINTEL64
:
10995 /* Turn off -Os. */
10996 optimize_for_space
= 0;
10998 else if (*arg
== 's')
11000 optimize_for_space
= 1;
11001 /* Turn on all encoding optimizations. */
11006 optimize
= atoi (arg
);
11007 /* Turn off -Os. */
11008 optimize_for_space
= 0;
11018 #define MESSAGE_TEMPLATE \
11022 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11023 int *left_p
, const char *name
, int len
)
11025 int size
= sizeof (MESSAGE_TEMPLATE
);
11026 int left
= *left_p
;
11028 /* Reserve 2 spaces for ", " or ",\0" */
11031 /* Check if there is any room. */
11039 p
= mempcpy (p
, name
, len
);
11043 /* Output the current message now and start a new one. */
11046 fprintf (stream
, "%s\n", message
);
11048 left
= size
- (start
- message
) - len
- 2;
11050 gas_assert (left
>= 0);
11052 p
= mempcpy (p
, name
, len
);
11060 show_arch (FILE *stream
, int ext
, int check
)
11062 static char message
[] = MESSAGE_TEMPLATE
;
11063 char *start
= message
+ 27;
11065 int size
= sizeof (MESSAGE_TEMPLATE
);
11072 left
= size
- (start
- message
);
11073 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11075 /* Should it be skipped? */
11076 if (cpu_arch
[j
].skip
)
11079 name
= cpu_arch
[j
].name
;
11080 len
= cpu_arch
[j
].len
;
11083 /* It is an extension. Skip if we aren't asked to show it. */
11094 /* It is an processor. Skip if we show only extension. */
11097 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11099 /* It is an impossible processor - skip. */
11103 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11106 /* Display disabled extensions. */
11108 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11110 name
= cpu_noarch
[j
].name
;
11111 len
= cpu_noarch
[j
].len
;
11112 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11117 fprintf (stream
, "%s\n", message
);
11121 md_show_usage (FILE *stream
)
11123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11124 fprintf (stream
, _("\
11126 -V print assembler version number\n\
11129 fprintf (stream
, _("\
11130 -n Do not optimize code alignment\n\
11131 -q quieten some warnings\n"));
11132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11133 fprintf (stream
, _("\
11136 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11137 || defined (TE_PE) || defined (TE_PEP))
11138 fprintf (stream
, _("\
11139 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11141 #ifdef SVR4_COMMENT_CHARS
11142 fprintf (stream
, _("\
11143 --divide do not treat `/' as a comment character\n"));
11145 fprintf (stream
, _("\
11146 --divide ignored\n"));
11148 fprintf (stream
, _("\
11149 -march=CPU[,+EXTENSION...]\n\
11150 generate code for CPU and EXTENSION, CPU is one of:\n"));
11151 show_arch (stream
, 0, 1);
11152 fprintf (stream
, _("\
11153 EXTENSION is combination of:\n"));
11154 show_arch (stream
, 1, 0);
11155 fprintf (stream
, _("\
11156 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11157 show_arch (stream
, 0, 0);
11158 fprintf (stream
, _("\
11159 -msse2avx encode SSE instructions with VEX prefix\n"));
11160 fprintf (stream
, _("\
11161 -msse-check=[none|error|warning] (default: warning)\n\
11162 check SSE instructions\n"));
11163 fprintf (stream
, _("\
11164 -moperand-check=[none|error|warning] (default: warning)\n\
11165 check operand combinations for validity\n"));
11166 fprintf (stream
, _("\
11167 -mavxscalar=[128|256] (default: 128)\n\
11168 encode scalar AVX instructions with specific vector\n\
11170 fprintf (stream
, _("\
11171 -mevexlig=[128|256|512] (default: 128)\n\
11172 encode scalar EVEX instructions with specific vector\n\
11174 fprintf (stream
, _("\
11175 -mevexwig=[0|1] (default: 0)\n\
11176 encode EVEX instructions with specific EVEX.W value\n\
11177 for EVEX.W bit ignored instructions\n"));
11178 fprintf (stream
, _("\
11179 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11180 encode EVEX instructions with specific EVEX.RC value\n\
11181 for SAE-only ignored instructions\n"));
11182 fprintf (stream
, _("\
11183 -mmnemonic=[att|intel] "));
11184 if (SYSV386_COMPAT
)
11185 fprintf (stream
, _("(default: att)\n"));
11187 fprintf (stream
, _("(default: intel)\n"));
11188 fprintf (stream
, _("\
11189 use AT&T/Intel mnemonic\n"));
11190 fprintf (stream
, _("\
11191 -msyntax=[att|intel] (default: att)\n\
11192 use AT&T/Intel syntax\n"));
11193 fprintf (stream
, _("\
11194 -mindex-reg support pseudo index registers\n"));
11195 fprintf (stream
, _("\
11196 -mnaked-reg don't require `%%' prefix for registers\n"));
11197 fprintf (stream
, _("\
11198 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11199 fprintf (stream
, _("\
11200 -mshared disable branch optimization for shared code\n"));
11201 # if defined (TE_PE) || defined (TE_PEP)
11202 fprintf (stream
, _("\
11203 -mbig-obj generate big object files\n"));
11205 fprintf (stream
, _("\
11206 -momit-lock-prefix=[no|yes] (default: no)\n\
11207 strip all lock prefixes\n"));
11208 fprintf (stream
, _("\
11209 -mfence-as-lock-add=[no|yes] (default: no)\n\
11210 encode lfence, mfence and sfence as\n\
11211 lock addl $0x0, (%%{re}sp)\n"));
11212 fprintf (stream
, _("\
11213 -mrelax-relocations=[no|yes] "));
11214 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11215 fprintf (stream
, _("(default: yes)\n"));
11217 fprintf (stream
, _("(default: no)\n"));
11218 fprintf (stream
, _("\
11219 generate relax relocations\n"));
11220 fprintf (stream
, _("\
11221 -mamd64 accept only AMD64 ISA [default]\n"));
11222 fprintf (stream
, _("\
11223 -mintel64 accept only Intel64 ISA\n"));
11226 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11227 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11228 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11230 /* Pick the target format to use. */
11233 i386_target_format (void)
11235 if (!strncmp (default_arch
, "x86_64", 6))
11237 update_code_flag (CODE_64BIT
, 1);
11238 if (default_arch
[6] == '\0')
11239 x86_elf_abi
= X86_64_ABI
;
11241 x86_elf_abi
= X86_64_X32_ABI
;
11243 else if (!strcmp (default_arch
, "i386"))
11244 update_code_flag (CODE_32BIT
, 1);
11245 else if (!strcmp (default_arch
, "iamcu"))
11247 update_code_flag (CODE_32BIT
, 1);
11248 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11250 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11251 cpu_arch_name
= "iamcu";
11252 cpu_sub_arch_name
= NULL
;
11253 cpu_arch_flags
= iamcu_flags
;
11254 cpu_arch_isa
= PROCESSOR_IAMCU
;
11255 cpu_arch_isa_flags
= iamcu_flags
;
11256 if (!cpu_arch_tune_set
)
11258 cpu_arch_tune
= cpu_arch_isa
;
11259 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11262 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11263 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11267 as_fatal (_("unknown architecture"));
11269 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11270 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11271 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11272 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11274 switch (OUTPUT_FLAVOR
)
11276 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11277 case bfd_target_aout_flavour
:
11278 return AOUT_TARGET_FORMAT
;
11280 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11281 # if defined (TE_PE) || defined (TE_PEP)
11282 case bfd_target_coff_flavour
:
11283 if (flag_code
== CODE_64BIT
)
11284 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11287 # elif defined (TE_GO32)
11288 case bfd_target_coff_flavour
:
11289 return "coff-go32";
11291 case bfd_target_coff_flavour
:
11292 return "coff-i386";
11295 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11296 case bfd_target_elf_flavour
:
11298 const char *format
;
11300 switch (x86_elf_abi
)
11303 format
= ELF_TARGET_FORMAT
;
11306 use_rela_relocations
= 1;
11308 format
= ELF_TARGET_FORMAT64
;
11310 case X86_64_X32_ABI
:
11311 use_rela_relocations
= 1;
11313 disallow_64bit_reloc
= 1;
11314 format
= ELF_TARGET_FORMAT32
;
11317 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11319 if (x86_elf_abi
!= X86_64_ABI
)
11320 as_fatal (_("Intel L1OM is 64bit only"));
11321 return ELF_TARGET_L1OM_FORMAT
;
11323 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11325 if (x86_elf_abi
!= X86_64_ABI
)
11326 as_fatal (_("Intel K1OM is 64bit only"));
11327 return ELF_TARGET_K1OM_FORMAT
;
11329 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11331 if (x86_elf_abi
!= I386_ABI
)
11332 as_fatal (_("Intel MCU is 32bit only"));
11333 return ELF_TARGET_IAMCU_FORMAT
;
11339 #if defined (OBJ_MACH_O)
11340 case bfd_target_mach_o_flavour
:
11341 if (flag_code
== CODE_64BIT
)
11343 use_rela_relocations
= 1;
11345 return "mach-o-x86-64";
11348 return "mach-o-i386";
11356 #endif /* OBJ_MAYBE_ more than one */
11359 md_undefined_symbol (char *name
)
11361 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11362 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11363 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11364 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11368 if (symbol_find (name
))
11369 as_bad (_("GOT already in symbol table"));
11370 GOT_symbol
= symbol_new (name
, undefined_section
,
11371 (valueT
) 0, &zero_address_frag
);
11378 /* Round up a section size to the appropriate boundary. */
11381 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11383 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11384 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11386 /* For a.out, force the section size to be aligned. If we don't do
11387 this, BFD will align it for us, but it will not write out the
11388 final bytes of the section. This may be a bug in BFD, but it is
11389 easier to fix it here since that is how the other a.out targets
11393 align
= bfd_get_section_alignment (stdoutput
, segment
);
11394 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11401 /* On the i386, PC-relative offsets are relative to the start of the
11402 next instruction. That is, the address of the offset, plus its
11403 size, since the offset is always the last part of the insn. */
11406 md_pcrel_from (fixS
*fixP
)
11408 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11414 s_bss (int ignore ATTRIBUTE_UNUSED
)
11418 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11420 obj_elf_section_change_hook ();
11422 temp
= get_absolute_expression ();
11423 subseg_set (bss_section
, (subsegT
) temp
);
11424 demand_empty_rest_of_line ();
11430 i386_validate_fix (fixS
*fixp
)
11432 if (fixp
->fx_subsy
)
11434 if (fixp
->fx_subsy
== GOT_symbol
)
11436 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11440 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11441 if (fixp
->fx_tcbit2
)
11442 fixp
->fx_r_type
= (fixp
->fx_tcbit
11443 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11444 : BFD_RELOC_X86_64_GOTPCRELX
);
11447 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11452 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11454 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11456 fixp
->fx_subsy
= 0;
11459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11460 else if (!object_64bit
)
11462 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11463 && fixp
->fx_tcbit2
)
11464 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11470 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11473 bfd_reloc_code_real_type code
;
11475 switch (fixp
->fx_r_type
)
11477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11478 case BFD_RELOC_SIZE32
:
11479 case BFD_RELOC_SIZE64
:
11480 if (S_IS_DEFINED (fixp
->fx_addsy
)
11481 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11483 /* Resolve size relocation against local symbol to size of
11484 the symbol plus addend. */
11485 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11486 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11487 && !fits_in_unsigned_long (value
))
11488 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11489 _("symbol size computation overflow"));
11490 fixp
->fx_addsy
= NULL
;
11491 fixp
->fx_subsy
= NULL
;
11492 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11496 /* Fall through. */
11498 case BFD_RELOC_X86_64_PLT32
:
11499 case BFD_RELOC_X86_64_GOT32
:
11500 case BFD_RELOC_X86_64_GOTPCREL
:
11501 case BFD_RELOC_X86_64_GOTPCRELX
:
11502 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11503 case BFD_RELOC_386_PLT32
:
11504 case BFD_RELOC_386_GOT32
:
11505 case BFD_RELOC_386_GOT32X
:
11506 case BFD_RELOC_386_GOTOFF
:
11507 case BFD_RELOC_386_GOTPC
:
11508 case BFD_RELOC_386_TLS_GD
:
11509 case BFD_RELOC_386_TLS_LDM
:
11510 case BFD_RELOC_386_TLS_LDO_32
:
11511 case BFD_RELOC_386_TLS_IE_32
:
11512 case BFD_RELOC_386_TLS_IE
:
11513 case BFD_RELOC_386_TLS_GOTIE
:
11514 case BFD_RELOC_386_TLS_LE_32
:
11515 case BFD_RELOC_386_TLS_LE
:
11516 case BFD_RELOC_386_TLS_GOTDESC
:
11517 case BFD_RELOC_386_TLS_DESC_CALL
:
11518 case BFD_RELOC_X86_64_TLSGD
:
11519 case BFD_RELOC_X86_64_TLSLD
:
11520 case BFD_RELOC_X86_64_DTPOFF32
:
11521 case BFD_RELOC_X86_64_DTPOFF64
:
11522 case BFD_RELOC_X86_64_GOTTPOFF
:
11523 case BFD_RELOC_X86_64_TPOFF32
:
11524 case BFD_RELOC_X86_64_TPOFF64
:
11525 case BFD_RELOC_X86_64_GOTOFF64
:
11526 case BFD_RELOC_X86_64_GOTPC32
:
11527 case BFD_RELOC_X86_64_GOT64
:
11528 case BFD_RELOC_X86_64_GOTPCREL64
:
11529 case BFD_RELOC_X86_64_GOTPC64
:
11530 case BFD_RELOC_X86_64_GOTPLT64
:
11531 case BFD_RELOC_X86_64_PLTOFF64
:
11532 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11533 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11534 case BFD_RELOC_RVA
:
11535 case BFD_RELOC_VTABLE_ENTRY
:
11536 case BFD_RELOC_VTABLE_INHERIT
:
11538 case BFD_RELOC_32_SECREL
:
11540 code
= fixp
->fx_r_type
;
11542 case BFD_RELOC_X86_64_32S
:
11543 if (!fixp
->fx_pcrel
)
11545 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11546 code
= fixp
->fx_r_type
;
11549 /* Fall through. */
11551 if (fixp
->fx_pcrel
)
11553 switch (fixp
->fx_size
)
11556 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11557 _("can not do %d byte pc-relative relocation"),
11559 code
= BFD_RELOC_32_PCREL
;
11561 case 1: code
= BFD_RELOC_8_PCREL
; break;
11562 case 2: code
= BFD_RELOC_16_PCREL
; break;
11563 case 4: code
= BFD_RELOC_32_PCREL
; break;
11565 case 8: code
= BFD_RELOC_64_PCREL
; break;
11571 switch (fixp
->fx_size
)
11574 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11575 _("can not do %d byte relocation"),
11577 code
= BFD_RELOC_32
;
11579 case 1: code
= BFD_RELOC_8
; break;
11580 case 2: code
= BFD_RELOC_16
; break;
11581 case 4: code
= BFD_RELOC_32
; break;
11583 case 8: code
= BFD_RELOC_64
; break;
11590 if ((code
== BFD_RELOC_32
11591 || code
== BFD_RELOC_32_PCREL
11592 || code
== BFD_RELOC_X86_64_32S
)
11594 && fixp
->fx_addsy
== GOT_symbol
)
11597 code
= BFD_RELOC_386_GOTPC
;
11599 code
= BFD_RELOC_X86_64_GOTPC32
;
11601 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11603 && fixp
->fx_addsy
== GOT_symbol
)
11605 code
= BFD_RELOC_X86_64_GOTPC64
;
11608 rel
= XNEW (arelent
);
11609 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11610 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11612 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11614 if (!use_rela_relocations
)
11616 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11617 vtable entry to be used in the relocation's section offset. */
11618 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11619 rel
->address
= fixp
->fx_offset
;
11620 #if defined (OBJ_COFF) && defined (TE_PE)
11621 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11622 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11627 /* Use the rela in 64bit mode. */
11630 if (disallow_64bit_reloc
)
11633 case BFD_RELOC_X86_64_DTPOFF64
:
11634 case BFD_RELOC_X86_64_TPOFF64
:
11635 case BFD_RELOC_64_PCREL
:
11636 case BFD_RELOC_X86_64_GOTOFF64
:
11637 case BFD_RELOC_X86_64_GOT64
:
11638 case BFD_RELOC_X86_64_GOTPCREL64
:
11639 case BFD_RELOC_X86_64_GOTPC64
:
11640 case BFD_RELOC_X86_64_GOTPLT64
:
11641 case BFD_RELOC_X86_64_PLTOFF64
:
11642 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11643 _("cannot represent relocation type %s in x32 mode"),
11644 bfd_get_reloc_code_name (code
));
11650 if (!fixp
->fx_pcrel
)
11651 rel
->addend
= fixp
->fx_offset
;
11655 case BFD_RELOC_X86_64_PLT32
:
11656 case BFD_RELOC_X86_64_GOT32
:
11657 case BFD_RELOC_X86_64_GOTPCREL
:
11658 case BFD_RELOC_X86_64_GOTPCRELX
:
11659 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11660 case BFD_RELOC_X86_64_TLSGD
:
11661 case BFD_RELOC_X86_64_TLSLD
:
11662 case BFD_RELOC_X86_64_GOTTPOFF
:
11663 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11664 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11665 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11668 rel
->addend
= (section
->vma
11670 + fixp
->fx_addnumber
11671 + md_pcrel_from (fixp
));
11676 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11677 if (rel
->howto
== NULL
)
11679 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11680 _("cannot represent relocation type %s"),
11681 bfd_get_reloc_code_name (code
));
11682 /* Set howto to a garbage value so that we can keep going. */
11683 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11684 gas_assert (rel
->howto
!= NULL
);
11690 #include "tc-i386-intel.c"
11693 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11695 int saved_naked_reg
;
11696 char saved_register_dot
;
11698 saved_naked_reg
= allow_naked_reg
;
11699 allow_naked_reg
= 1;
11700 saved_register_dot
= register_chars
['.'];
11701 register_chars
['.'] = '.';
11702 allow_pseudo_reg
= 1;
11703 expression_and_evaluate (exp
);
11704 allow_pseudo_reg
= 0;
11705 register_chars
['.'] = saved_register_dot
;
11706 allow_naked_reg
= saved_naked_reg
;
11708 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11710 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11712 exp
->X_op
= O_constant
;
11713 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11714 .dw2_regnum
[flag_code
>> 1];
11717 exp
->X_op
= O_illegal
;
11722 tc_x86_frame_initial_instructions (void)
11724 static unsigned int sp_regno
[2];
11726 if (!sp_regno
[flag_code
>> 1])
11728 char *saved_input
= input_line_pointer
;
11729 char sp
[][4] = {"esp", "rsp"};
11732 input_line_pointer
= sp
[flag_code
>> 1];
11733 tc_x86_parse_to_dw2regnum (&exp
);
11734 gas_assert (exp
.X_op
== O_constant
);
11735 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11736 input_line_pointer
= saved_input
;
11739 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11740 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11744 x86_dwarf2_addr_size (void)
11746 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11747 if (x86_elf_abi
== X86_64_X32_ABI
)
11750 return bfd_arch_bits_per_address (stdoutput
) / 8;
11754 i386_elf_section_type (const char *str
, size_t len
)
11756 if (flag_code
== CODE_64BIT
11757 && len
== sizeof ("unwind") - 1
11758 && strncmp (str
, "unwind", 6) == 0)
11759 return SHT_X86_64_UNWIND
;
11766 i386_solaris_fix_up_eh_frame (segT sec
)
11768 if (flag_code
== CODE_64BIT
)
11769 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11775 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11779 exp
.X_op
= O_secrel
;
11780 exp
.X_add_symbol
= symbol
;
11781 exp
.X_add_number
= 0;
11782 emit_expr (&exp
, size
);
11786 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11787 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11790 x86_64_section_letter (int letter
, const char **ptr_msg
)
11792 if (flag_code
== CODE_64BIT
)
11795 return SHF_X86_64_LARGE
;
11797 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11800 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11805 x86_64_section_word (char *str
, size_t len
)
11807 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11808 return SHF_X86_64_LARGE
;
11814 handle_large_common (int small ATTRIBUTE_UNUSED
)
11816 if (flag_code
!= CODE_64BIT
)
11818 s_comm_internal (0, elf_common_parse
);
11819 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11823 static segT lbss_section
;
11824 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11825 asection
*saved_bss_section
= bss_section
;
11827 if (lbss_section
== NULL
)
11829 flagword applicable
;
11830 segT seg
= now_seg
;
11831 subsegT subseg
= now_subseg
;
11833 /* The .lbss section is for local .largecomm symbols. */
11834 lbss_section
= subseg_new (".lbss", 0);
11835 applicable
= bfd_applicable_section_flags (stdoutput
);
11836 bfd_set_section_flags (stdoutput
, lbss_section
,
11837 applicable
& SEC_ALLOC
);
11838 seg_info (lbss_section
)->bss
= 1;
11840 subseg_set (seg
, subseg
);
11843 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11844 bss_section
= lbss_section
;
11846 s_comm_internal (0, elf_common_parse
);
11848 elf_com_section_ptr
= saved_com_section_ptr
;
11849 bss_section
= saved_bss_section
;
11852 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */