gas/config/tc-i960.h

   1 /* tc-i960.h - Basic 80960 instruction formats.
   2    Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc.
   3
   4 This file is part of GAS, the GNU Assembler.
   5
   6 GAS is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as
   8 published by the Free Software Foundation; either version 1,
   9 or (at your option) any later version.
  10
  11 GAS is distributed in the hope that it will be useful, but
  12 WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public
  17 License along with GAS; see the file COPYING.  If not, write
  18 to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
  19
  20 /* $Id$ */
  21
  22 /*
  23  * The 'COJ' instructions are actually COBR instructions with the 'b' in
  24  * the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if necessary:
  25  * if the displacement will not fit in 13 bits, the assembler will replace them
  26  * with the corresponding compare and branch instructions.
  27  *
  28  * All of the 'MEMn' instructions are the same format; the 'n' in the name
  29  * indicates the default index scale factor (the size of the datum operated on).
  30  *
  31  * The FBRA formats are not actually an instruction format.  They are the
  32  * "convenience directives" for branching on floating-point comparisons,
  33  * each of which generates 2 instructions (a 'bno' and one other branch).
  34  *
  35  * The CALLJ format is not actually an instruction format.  It indicates that
  36  * the instruction generated (a CTRL-format 'call') should have its relocation
  37  * specially flagged for link-time replacement with a 'bal' or 'calls' if
  38  * appropriate.
  39  */
  40
  41 #define TC_I960 1
  42
  43  /* tailor gas */
  44 #define SYMBOLS_NEED_BACKPOINTERS
  45 #define LOCAL_LABELS_FB
  46 #define WANT_BITFIELDS
  47
  48  /* tailor the coff format */
  49 #define OBJ_COFF_SECTION_HEADER_HAS_ALIGNMENT
  50 #define OBJ_COFF_MAX_AUXENTRIES (2)
  51
  52  /* other */
  53 #define CTRL    0
  54 #define COBR    1
  55 #define COJ     2
  56 #define REG     3
  57 #define MEM1    4
  58 #define MEM2    5
  59 #define MEM4    6
  60 #define MEM8    7
  61 #define MEM12   8
  62 #define MEM16   9
  63 #define FBRA    10
  64 #define CALLJ   11
  65
  66 /* Masks for the mode bits in REG format instructions */
  67 #define M1              0x0800
  68 #define M2              0x1000
  69 #define M3              0x2000
  70
  71 /* Generate the 12-bit opcode for a REG format instruction by placing the
  72  * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
  73  * 7-10.
  74  */
  75
  76 #define REG_OPC(opc)    ((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
  77
  78 /* Generate a template for a REG format instruction:  place the opcode bits
  79  * in the appropriate fields and OR in mode bits for the operands that will not
  80  * be used.  I.e.,
  81  *              set m1=1, if src1 will not be used
  82  *              set m2=1, if src2 will not be used
  83  *              set m3=1, if dst  will not be used
  84  *
  85  * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
  86  * The information is also useful to us because some 1-operand REG instructions
  87  * use the src1 field, others the dst field; and some 2-operand REG instructions
  88  * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
  89  */
  90 #define R_0(opc)        ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands      */
  91 #define R_1(opc)        ( REG_OPC(opc) | M2 | M3 )      /* 1 operand: src1  */
  92 #define R_1D(opc)       ( REG_OPC(opc) | M1 | M2 )      /* 1 operand: dst   */
  93 #define R_2(opc)        ( REG_OPC(opc) | M3 )           /* 2 ops: src1/src2 */
  94 #define R_2D(opc)       ( REG_OPC(opc) | M2 )           /* 2 ops: src1/dst  */
  95 #define R_3(opc)        ( REG_OPC(opc) )                /* 3 operands       */
  96
  97 /* DESCRIPTOR BYTES FOR REGISTER OPERANDS
  98  *
  99  * Interpret names as follows:
 100  *      R:   global or local register only
 101  *      RS:  global, local, or (if target allows) special-function register only
 102  *      RL:  global or local register, or integer literal
 103  *      RSL: global, local, or (if target allows) special-function register;
 104  *              or integer literal
 105  *      F:   global, local, or floating-point register
 106  *      FL:  global, local, or floating-point register; or literal (including
 107  *              floating point)
 108  *
 109  * A number appended to a name indicates that registers must be aligned,
 110  * as follows:
 111  *      2: register number must be multiple of 2
 112  *      4: register number must be multiple of 4
 113  */
 114
 115 #define SFR     0x10            /* Mask for the "sfr-OK" bit */
 116 #define LIT     0x08            /* Mask for the "literal-OK" bit */
 117 #define FP      0x04            /* Mask for "floating-point-OK" bit */
 118
 119 /* This macro ors the bits together.  Note that 'align' is a mask
 120  * for the low 0, 1, or 2 bits of the register number, as appropriate.
 121  */
 122 #define OP(align,lit,fp,sfr)    ( align | lit | fp | sfr )
 123
 124 #define R       OP( 0, 0,   0,  0   )
 125 #define RS      OP( 0, 0,   0,  SFR )
 126 #define RL      OP( 0, LIT, 0,  0   )
 127 #define RSL     OP( 0, LIT, 0,  SFR )
 128 #define F       OP( 0, 0,   FP, 0   )
 129 #define FL      OP( 0, LIT, FP, 0   )
 130 #define R2      OP( 1, 0,   0,  0   )
 131 #define RL2     OP( 1, LIT, 0,  0   )
 132 #define F2      OP( 1, 0,   FP, 0   )
 133 #define FL2     OP( 1, LIT, FP, 0   )
 134 #define R4      OP( 3, 0,   0,  0   )
 135 #define RL4     OP( 3, LIT, 0,  0   )
 136 #define F4      OP( 3, 0,   FP, 0   )
 137 #define FL4     OP( 3, LIT, FP, 0   )
 138
 139 #define M       0x7f    /* Memory operand (MEMA & MEMB format instructions) */
 140
 141 /* Macros to extract info from the register operand descriptor byte 'od'.
 142  */
 143 #define SFR_OK(od)      (od & SFR)      /* TRUE if sfr operand allowed */
 144 #define LIT_OK(od)      (od & LIT)      /* TRUE if literal operand allowed */
 145 #define FP_OK(od)       (od & FP)       /* TRUE if floating-point op allowed */
 146 #define REG_ALIGN(od,n) ((od & 0x3 & n) == 0)
 147                                         /* TRUE if reg #n is properly aligned */
 148 #define MEMOP(od)       (od == M)       /* TRUE if operand is a memory operand*/
 149
 150 /* Classes of 960 intructions:
 151  *      - each instruction falls into one class.
 152  *      - each target architecture supports one or more classes.
 153  *
 154  * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
 155  */
 156 #define I_BASE  0x01    /* 80960 base instruction set   */
 157 #define I_CX    0x02    /* 80960Cx instruction          */
 158 #define I_DEC   0x04    /* Decimal instruction          */
 159 #define I_FP    0x08    /* Floating point instruction   */
 160 #define I_KX    0x10    /* 80960Kx instruction          */
 161 #define I_MIL   0x20    /* Military instruction         */
 162
 163 /* MEANING OF 'n_other' in the symbol record.
 164  *
 165  * If non-zero, the 'n_other' fields indicates either a leaf procedure or
 166  * a system procedure, as follows:
 167  *
 168  *      1 <= n_other <= 32 :
 169  *              The symbol is the entry point to a system procedure.
 170  *              'n_value' is the address of the entry, as for any other
 171  *              procedure.  The system procedure number (which can be used in
 172  *              a 'calls' instruction) is (n_other-1).  These entries come from
 173  *              '.sysproc' directives.
 174  *
 175  *      n_other == N_CALLNAME
 176  *              the symbol is the 'call' entry point to a leaf procedure.
 177  *              The *next* symbol in the symbol table must be the corresponding
 178  *              'bal' entry point to the procedure (see following).  These
 179  *              entries come from '.leafproc' directives in which two different
 180  *              symbols are specified (the first one is represented here).
 181  *
 182  *
 183  *      n_other == N_BALNAME
 184  *              the symbol is the 'bal' entry point to a leaf procedure.
 185  *              These entries result from '.leafproc' directives in which only
 186  *              one symbol is specified, or in which the same symbol is
 187  *              specified twice.
 188  *
 189  * Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry,
 190  * but not every N_BALNAME entry must have an N_CALLNAME entry.
 191  */
 192 #define N_CALLNAME      (-1)
 193 #define N_BALNAME       (-2)
 194
 195
 196  /* i960 uses a custom relocation record. */
 197
 198  /* let obj-aout.h know */
 199 #define CUSTOM_RELOC_FORMAT 1
 200  /* let a.out.gnu.h know */
 201 #define N_RELOCATION_INFO_DECLARED 1
 202 struct relocation_info {
 203         int      r_address;     /* File address of item to be relocated */
 204         unsigned
 205                 r_index:24,/* Index of symbol on which relocation is based*/
 206                 r_pcrel:1,      /* 1 => relocate PC-relative; else absolute
 207                                  *      On i960, pc-relative implies 24-bit
 208                                  *      address, absolute implies 32-bit.
 209                                  */
 210                 r_length:2,     /* Number of bytes to relocate:
 211                                  *      0 => 1 byte
 212                                  *      1 => 2 bytes
 213                                  *      2 => 4 bytes -- only value used for i960
 214                                  */
 215                 r_extern:1,
 216                 r_bsr:1,        /* Something for the GNU NS32K assembler */
 217                 r_disp:1,       /* Something for the GNU NS32K assembler */
 218                 r_callj:1,      /* 1 if relocation target is an i960 'callj' */
 219                 nuthin:1;       /* Unused                               */
 220 };
 221
 222  /* hacks for tracking callj's */
 223 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
 224
 225 #define TC_S_IS_SYSPROC(s)      ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
 226 #define TC_S_IS_BALNAME(s)      (S_GET_OTHER(s) == N_BALNAME)
 227 #define TC_S_IS_CALLNAME(s)     (S_GET_OTHER(s) == N_CALLNAME)
 228 #define TC_S_IS_BADPROC(s)      ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
 229
 230 #define TC_S_SET_SYSPROC(s, p)  (S_SET_OTHER((s), (p)+1))
 231 #define TC_S_GET_SYSPROC(s)     (S_GET_OTHER(s)-1)
 232
 233 #define TC_S_FORCE_TO_BALNAME(s)        (S_SET_OTHER((s), N_BALNAME))
 234 #define TC_S_FORCE_TO_CALLNAME(s)       (S_SET_OTHER((s), N_CALLNAME))
 235 #define TC_S_FORCE_TO_SYSPROC(s)        {;}
 236
 237 #elif defined(OBJ_COFF)
 238
 239 #define TC_S_IS_SYSPROC(s)      (S_GET_STORAGE_CLASS(s) == C_SCALL)
 240 #define TC_S_IS_BALNAME(s)      (SF_GET_BALNAME(s))
 241 #define TC_S_IS_CALLNAME(s)     (SF_GET_CALLNAME(s))
 242 #define TC_S_IS_BADPROC(s)      (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
 243
 244 #define TC_S_SET_SYSPROC(s, p)  ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
 245 #define TC_S_GET_SYSPROC(s)     ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
 246
 247 #define TC_S_FORCE_TO_BALNAME(s)        (SF_SET_BALNAME(s))
 248 #define TC_S_FORCE_TO_CALLNAME(s)       (SF_SET_CALLNAME(s))
 249 #define TC_S_FORCE_TO_SYSPROC(s)        (S_SET_STORAGE_CLASS((s), C_SCALL))
 250
 251 #else /* switch on OBJ */
 252 you lose
 253 #endif /* witch on OBJ */
 254
 255 #ifdef __STDC__
 256
 257 void brtab_emit(void);
 258 void reloc_callj(); /* this is really reloc_callj(fixS *fixP) but I don't want to change header inclusion order. */
 259 void tc_set_bal_of_call(); /* this is really tc_set_bal_of_call(symbolS *callP, symbolS *balP) */
 260
 261 #else /* __STDC__ */
 262
 263 void brtab_emit();
 264 void reloc_callj();
 265 void tc_set_bal_of_call();
 266
 267 #endif /* __STDC__ */
 268
 269 char *_tc_get_bal_of_call(); /* this is really symbolS *tc_get_bal_of_call(symbolS *callP). */
 270 #define tc_get_bal_of_call(c)   ((symbolS *) _tc_get_bal_of_call(c))
 271
 272 /*
 273  * Local Variables:
 274  * comment-column: 0
 275  * fill-column: 131
 276  * End:
 277  */
 278
 279 /* end of tp-i960.h */