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[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
181 0
182 };
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
185 0
186 };
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
189 0
190 };
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
193 0
194 };
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
197 0
198 };
199 static const enum m68k_register mcf52223_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52235_ctrl[] = {
204 VBR, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf5225_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5235_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5249_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
217 0
218 };
219 static const enum m68k_register mcf5250_ctrl[] = {
220 VBR,
221 0
222 };
223 static const enum m68k_register mcf5253_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
225 0
226 };
227 static const enum m68k_register mcf5271_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
229 0
230 };
231 static const enum m68k_register mcf5272_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
233 0
234 };
235 static const enum m68k_register mcf5275_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
237 0
238 };
239 static const enum m68k_register mcf5282_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5307_ctrl[] = {
244 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
245 0
246 };
247 static const enum m68k_register mcf5329_ctrl[] = {
248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
249 0
250 };
251 static const enum m68k_register mcf5373_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcfv4e_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
258 MBAR, SECMBAR,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
264 /* Legacy names */
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
269 0
270 };
271 static const enum m68k_register mcf54455_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
273 VBR, PC, RAMBAR1, MBAR,
274 /* Legacy names */
275 TC /* ASID */, BUSCR /* MMUBAR */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
278 0
279 };
280 static const enum m68k_register mcf5475_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
283 /* Legacy names */
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
287 0
288 };
289 static const enum m68k_register mcf5485_ctrl[] = {
290 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
291 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
292 /* Legacy names */
293 TC /* ASID */, BUSCR /* MMUBAR */,
294 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
295 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
296 0
297 };
298 static const enum m68k_register fido_ctrl[] = {
299 SFC, DFC, USP, VBR, CAC, MBB,
300 0
301 };
302 #define cpu32_ctrl m68010_ctrl
303
304 static const enum m68k_register *control_regs;
305
306 /* Internal form of a 68020 instruction. */
307 struct m68k_it
308 {
309 const char *error;
310 const char *args; /* List of opcode info. */
311 int numargs;
312
313 int numo; /* Number of shorts in opcode. */
314 short opcode[11];
315
316 struct m68k_op operands[6];
317
318 int nexp; /* Number of exprs in use. */
319 struct m68k_exp exprs[4];
320
321 int nfrag; /* Number of frags we have to produce. */
322 struct
323 {
324 int fragoff; /* Where in the current opcode the frag ends. */
325 symbolS *fadd;
326 offsetT foff;
327 int fragty;
328 }
329 fragb[4];
330
331 int nrel; /* Num of reloc strucs in use. */
332 struct
333 {
334 int n;
335 expressionS exp;
336 char wid;
337 char pcrel;
338 /* In a pc relative address the difference between the address
339 of the offset and the address that the offset is relative
340 to. This depends on the addressing mode. Basically this
341 is the value to put in the offset field to address the
342 first byte of the offset, without regarding the special
343 significance of some values (in the branch instruction, for
344 example). */
345 int pcrel_fix;
346 #ifdef OBJ_ELF
347 /* Whether this expression needs special pic relocation, and if
348 so, which. */
349 enum pic_relocation pic_reloc;
350 #endif
351 }
352 reloc[5]; /* Five is enough??? */
353 };
354
355 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
356 #define float_of_arch(x) ((x) & mfloat)
357 #define mmu_of_arch(x) ((x) & mmmu)
358 #define arch_coldfire_p(x) ((x) & mcfisa_a)
359 #define arch_coldfire_fpu(x) ((x) & cfloat)
360
361 /* Macros for determining if cpu supports a specific addressing mode. */
362 #define HAVE_LONG_DISP(x) \
363 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
364 #define HAVE_LONG_CALL(x) \
365 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
366 #define HAVE_LONG_COND(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368 #define HAVE_LONG_BRANCH(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
370
371 static struct m68k_it the_ins; /* The instruction being assembled. */
372
373 #define op(ex) ((ex)->exp.X_op)
374 #define adds(ex) ((ex)->exp.X_add_symbol)
375 #define subs(ex) ((ex)->exp.X_op_symbol)
376 #define offs(ex) ((ex)->exp.X_add_number)
377
378 /* Macros for adding things to the m68k_it struct. */
379 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
380
381 /* Like addword, but goes BEFORE general operands. */
382
383 static void
384 insop (int w, const struct m68k_incant *opcode)
385 {
386 int z;
387 for (z = the_ins.numo; z > opcode->m_codenum; --z)
388 the_ins.opcode[z] = the_ins.opcode[z - 1];
389 for (z = 0; z < the_ins.nrel; z++)
390 the_ins.reloc[z].n += 2;
391 for (z = 0; z < the_ins.nfrag; z++)
392 the_ins.fragb[z].fragoff++;
393 the_ins.opcode[opcode->m_codenum] = w;
394 the_ins.numo++;
395 }
396
397 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
398 Blecch. */
399 static void
400 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
401 {
402 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
403 ? the_ins.numo * 2 - 1
404 : (width == 'b'
405 ? the_ins.numo * 2 + 1
406 : the_ins.numo * 2));
407 the_ins.reloc[the_ins.nrel].exp = exp->exp;
408 the_ins.reloc[the_ins.nrel].wid = width;
409 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
410 #ifdef OBJ_ELF
411 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
412 #endif
413 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
414 }
415
416 /* Cause an extra frag to be generated here, inserting up to 10 bytes
417 (that value is chosen in the frag_var call in md_assemble). TYPE
418 is the subtype of the frag to be generated; its primary type is
419 rs_machine_dependent.
420
421 The TYPE parameter is also used by md_convert_frag_1 and
422 md_estimate_size_before_relax. The appropriate type of fixup will
423 be emitted by md_convert_frag_1.
424
425 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
426 static void
427 add_frag (symbolS *add, offsetT off, int type)
428 {
429 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
430 the_ins.fragb[the_ins.nfrag].fadd = add;
431 the_ins.fragb[the_ins.nfrag].foff = off;
432 the_ins.fragb[the_ins.nfrag++].fragty = type;
433 }
434
435 #define isvar(ex) \
436 (op (ex) != O_constant && op (ex) != O_big)
437
438 static char *crack_operand (char *str, struct m68k_op *opP);
439 static int get_num (struct m68k_exp *exp, int ok);
440 static int reverse_16_bits (int in);
441 static int reverse_8_bits (int in);
442 static void install_gen_operand (int mode, int val);
443 static void install_operand (int mode, int val);
444 static void s_bss (int);
445 static void s_data1 (int);
446 static void s_data2 (int);
447 static void s_even (int);
448 static void s_proc (int);
449 static void s_chip (int);
450 static void s_fopt (int);
451 static void s_opt (int);
452 static void s_reg (int);
453 static void s_restore (int);
454 static void s_save (int);
455 static void s_mri_if (int);
456 static void s_mri_else (int);
457 static void s_mri_endi (int);
458 static void s_mri_break (int);
459 static void s_mri_next (int);
460 static void s_mri_for (int);
461 static void s_mri_endf (int);
462 static void s_mri_repeat (int);
463 static void s_mri_until (int);
464 static void s_mri_while (int);
465 static void s_mri_endw (int);
466 static void s_m68k_cpu (int);
467 static void s_m68k_arch (int);
468
469 struct m68k_cpu
470 {
471 unsigned long arch; /* Architecture features. */
472 const enum m68k_register *control_regs; /* Control regs on chip */
473 const char *name; /* Name */
474 int alias; /* Alias for a cannonical name. If 1, then
475 succeeds canonical name, if -1 then
476 succeeds canonical name, if <-1 ||>1 this is a
477 deprecated name, and the next/previous name
478 should be used. */
479 };
480
481 /* We hold flags for features explicitly enabled and explicitly
482 disabled. */
483 static int current_architecture;
484 static int not_current_architecture;
485 static const struct m68k_cpu *selected_arch;
486 static const struct m68k_cpu *selected_cpu;
487 static int initialized;
488
489 /* Architecture models. */
490 static const struct m68k_cpu m68k_archs[] =
491 {
492 {m68000, m68000_ctrl, "68000", 0},
493 {m68010, m68010_ctrl, "68010", 0},
494 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
495 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
496 {m68040, m68040_ctrl, "68040", 0},
497 {m68060, m68060_ctrl, "68060", 0},
498 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
499 {fido_a, fido_ctrl, "fidoa", 0},
500 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
501 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
502 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
503 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
504 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
505 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
506 {0,0,NULL, 0}
507 };
508
509 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
510 for either. */
511 static const struct m68k_cpu m68k_extensions[] =
512 {
513 {m68851, NULL, "68851", -1},
514 {m68881, NULL, "68881", -1},
515 {m68881, NULL, "68882", -1},
516
517 {cfloat|m68881, NULL, "float", 0},
518
519 {mcfhwdiv, NULL, "div", 1},
520 {mcfusp, NULL, "usp", 1},
521 {mcfmac, NULL, "mac", 1},
522 {mcfemac, NULL, "emac", 1},
523
524 {0,NULL,NULL, 0}
525 };
526
527 /* Processor list */
528 static const struct m68k_cpu m68k_cpus[] =
529 {
530 {m68000, m68000_ctrl, "68000", 0},
531 {m68000, m68000_ctrl, "68ec000", 1},
532 {m68000, m68000_ctrl, "68hc000", 1},
533 {m68000, m68000_ctrl, "68hc001", 1},
534 {m68000, m68000_ctrl, "68008", 1},
535 {m68000, m68000_ctrl, "68302", 1},
536 {m68000, m68000_ctrl, "68306", 1},
537 {m68000, m68000_ctrl, "68307", 1},
538 {m68000, m68000_ctrl, "68322", 1},
539 {m68000, m68000_ctrl, "68356", 1},
540 {m68010, m68010_ctrl, "68010", 0},
541 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
542 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
543 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
544 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
545 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
546 {m68040, m68040_ctrl, "68040", 0},
547 {m68040, m68040_ctrl, "68ec040", 1},
548 {m68060, m68060_ctrl, "68060", 0},
549 {m68060, m68060_ctrl, "68ec060", 1},
550
551 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
552 {cpu32|m68881, cpu32_ctrl, "68330", 1},
553 {cpu32|m68881, cpu32_ctrl, "68331", 1},
554 {cpu32|m68881, cpu32_ctrl, "68332", 1},
555 {cpu32|m68881, cpu32_ctrl, "68333", 1},
556 {cpu32|m68881, cpu32_ctrl, "68334", 1},
557 {cpu32|m68881, cpu32_ctrl, "68336", 1},
558 {cpu32|m68881, cpu32_ctrl, "68340", 1},
559 {cpu32|m68881, cpu32_ctrl, "68341", 1},
560 {cpu32|m68881, cpu32_ctrl, "68349", 1},
561 {cpu32|m68881, cpu32_ctrl, "68360", 1},
562
563 {mcfisa_a, mcf_ctrl, "5200", 0},
564 {mcfisa_a, mcf_ctrl, "5202", 1},
565 {mcfisa_a, mcf_ctrl, "5204", 1},
566 {mcfisa_a, mcf5206_ctrl, "5206", 1},
567
568 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
569
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
572
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
574 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
579
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
583
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
586
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
591
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
594
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
600
601 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
602 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
603 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
604
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
607
608 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
612
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
617
618 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
619
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
628
629 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
630
631 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
632 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
633 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
634 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
635 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
636 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
637
638 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
639 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
640 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
641 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
642 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
643 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
645
646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
647 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
648 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
649 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
651 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
652 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
653
654 {fido_a, fido_ctrl, "fidoa", 0},
655 {fido_a, fido_ctrl, "fido", 1},
656
657 {0,NULL,NULL, 0}
658 };
659
660 static const struct m68k_cpu *m68k_lookup_cpu
661 (const char *, const struct m68k_cpu *, int, int *);
662 static int m68k_set_arch (const char *, int, int);
663 static int m68k_set_cpu (const char *, int, int);
664 static int m68k_set_extension (const char *, int, int);
665 static void m68k_init_arch (void);
666
667 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
668 architecture and we have a lot of relaxation modes. */
669
670 /* Macros used in the relaxation code. */
671 #define TAB(x,y) (((x) << 2) + (y))
672 #define TABTYPE(x) ((x) >> 2)
673
674 /* Relaxation states. */
675 #define BYTE 0
676 #define SHORT 1
677 #define LONG 2
678 #define SZ_UNDEF 3
679
680 /* Here are all the relaxation modes we support. First we can relax ordinary
681 branches. On 68020 and higher and on CPU32 all branch instructions take
682 three forms, so on these CPUs all branches always remain as such. When we
683 have to expand to the LONG form on a 68000, though, we substitute an
684 absolute jump instead. This is a direct replacement for unconditional
685 branches and a branch over a jump for conditional branches. However, if the
686 user requires PIC and disables this with --pcrel, we can only relax between
687 BYTE and SHORT forms, punting if that isn't enough. This gives us four
688 different relaxation modes for branches: */
689
690 #define BRANCHBWL 0 /* Branch byte, word, or long. */
691 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
692 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
693 #define BRANCHBW 3 /* Branch byte or word. */
694
695 /* We also relax coprocessor branches and DBcc's. All CPUs that support
696 coprocessor branches support them in word and long forms, so we have only
697 one relaxation mode for them. DBcc's are word only on all CPUs. We can
698 relax them to the LONG form with a branch-around sequence. This sequence
699 can use a long branch (if available) or an absolute jump (if acceptable).
700 This gives us two relaxation modes. If long branches are not available and
701 absolute jumps are not acceptable, we don't relax DBcc's. */
702
703 #define FBRANCH 4 /* Coprocessor branch. */
704 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
705 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
706
707 /* That's all for instruction relaxation. However, we also relax PC-relative
708 operands. Specifically, we have three operand relaxation modes. On the
709 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
710 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
711 two. Also PC+displacement+index operands in their simple form (with a non-
712 suppressed index without memory indirection) are supported on all CPUs, but
713 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
714 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
715 form of the PC+displacement+index operand. Finally, some absolute operands
716 can be relaxed down to 16-bit PC-relative. */
717
718 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
719 #define PCINDEX 8 /* PC + displacement + index. */
720 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
721
722 /* Note that calls to frag_var need to specify the maximum expansion
723 needed; this is currently 10 bytes for DBCC. */
724
725 /* The fields are:
726 How far Forward this mode will reach:
727 How far Backward this mode will reach:
728 How many bytes this mode will add to the size of the frag
729 Which mode to go to if the offset won't fit in this one
730
731 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
732 relax_typeS md_relax_table[] =
733 {
734 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
735 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
736 { 0, 0, 4, 0 },
737 { 1, 1, 0, 0 },
738
739 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
740 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
741 { 0, 0, 4, 0 },
742 { 1, 1, 0, 0 },
743
744 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
745 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
746 { 0, 0, 6, 0 },
747 { 1, 1, 0, 0 },
748
749 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
750 { 0, 0, 2, 0 },
751 { 1, 1, 0, 0 },
752 { 1, 1, 0, 0 },
753
754 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
755 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
756 { 0, 0, 4, 0 },
757 { 1, 1, 0, 0 },
758
759 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
760 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
761 { 0, 0, 10, 0 },
762 { 1, 1, 0, 0 },
763
764 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
765 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
766 { 0, 0, 10, 0 },
767 { 1, 1, 0, 0 },
768
769 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
771 { 0, 0, 6, 0 },
772 { 1, 1, 0, 0 },
773
774 { 125, -130, 0, TAB (PCINDEX, SHORT) },
775 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
776 { 0, 0, 4, 0 },
777 { 1, 1, 0, 0 },
778
779 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
781 { 0, 0, 4, 0 },
782 { 1, 1, 0, 0 },
783 };
784
785 /* These are the machine dependent pseudo-ops. These are included so
786 the assembler can work on the output from the SUN C compiler, which
787 generates these. */
788
789 /* This table describes all the machine specific pseudo-ops the assembler
790 has to support. The fields are:
791 pseudo-op name without dot
792 function to call to execute this pseudo-op
793 Integer arg to pass to the function. */
794 const pseudo_typeS md_pseudo_table[] =
795 {
796 {"data1", s_data1, 0},
797 {"data2", s_data2, 0},
798 {"bss", s_bss, 0},
799 {"even", s_even, 0},
800 {"skip", s_space, 0},
801 {"proc", s_proc, 0},
802 #if defined (TE_SUN3) || defined (OBJ_ELF)
803 {"align", s_align_bytes, 0},
804 #endif
805 #ifdef OBJ_ELF
806 {"swbeg", s_ignore, 0},
807 #endif
808 {"extend", float_cons, 'x'},
809 {"ldouble", float_cons, 'x'},
810
811 {"arch", s_m68k_arch, 0},
812 {"cpu", s_m68k_cpu, 0},
813
814 /* The following pseudo-ops are supported for MRI compatibility. */
815 {"chip", s_chip, 0},
816 {"comline", s_space, 1},
817 {"fopt", s_fopt, 0},
818 {"mask2", s_ignore, 0},
819 {"opt", s_opt, 0},
820 {"reg", s_reg, 0},
821 {"restore", s_restore, 0},
822 {"save", s_save, 0},
823
824 {"if", s_mri_if, 0},
825 {"if.b", s_mri_if, 'b'},
826 {"if.w", s_mri_if, 'w'},
827 {"if.l", s_mri_if, 'l'},
828 {"else", s_mri_else, 0},
829 {"else.s", s_mri_else, 's'},
830 {"else.l", s_mri_else, 'l'},
831 {"endi", s_mri_endi, 0},
832 {"break", s_mri_break, 0},
833 {"break.s", s_mri_break, 's'},
834 {"break.l", s_mri_break, 'l'},
835 {"next", s_mri_next, 0},
836 {"next.s", s_mri_next, 's'},
837 {"next.l", s_mri_next, 'l'},
838 {"for", s_mri_for, 0},
839 {"for.b", s_mri_for, 'b'},
840 {"for.w", s_mri_for, 'w'},
841 {"for.l", s_mri_for, 'l'},
842 {"endf", s_mri_endf, 0},
843 {"repeat", s_mri_repeat, 0},
844 {"until", s_mri_until, 0},
845 {"until.b", s_mri_until, 'b'},
846 {"until.w", s_mri_until, 'w'},
847 {"until.l", s_mri_until, 'l'},
848 {"while", s_mri_while, 0},
849 {"while.b", s_mri_while, 'b'},
850 {"while.w", s_mri_while, 'w'},
851 {"while.l", s_mri_while, 'l'},
852 {"endw", s_mri_endw, 0},
853
854 {0, 0, 0}
855 };
856
857 /* The mote pseudo ops are put into the opcode table, since they
858 don't start with a . they look like opcodes to gas. */
859
860 const pseudo_typeS mote_pseudo_table[] =
861 {
862
863 {"dcl", cons, 4},
864 {"dc", cons, 2},
865 {"dcw", cons, 2},
866 {"dcb", cons, 1},
867
868 {"dsl", s_space, 4},
869 {"ds", s_space, 2},
870 {"dsw", s_space, 2},
871 {"dsb", s_space, 1},
872
873 {"xdef", s_globl, 0},
874 #ifdef OBJ_ELF
875 {"align", s_align_bytes, 0},
876 #else
877 {"align", s_align_ptwo, 0},
878 #endif
879 #ifdef M68KCOFF
880 {"sect", obj_coff_section, 0},
881 {"section", obj_coff_section, 0},
882 #endif
883 {0, 0, 0}
884 };
885
886 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
887 gives identical results to a 32-bit host. */
888 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
889 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
890
891 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
892 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
893 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
894 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
895
896 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
897 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
898 #define islong(x) (1)
899
900 static char notend_table[256];
901 static char alt_notend_table[256];
902 #define notend(s) \
903 (! (notend_table[(unsigned char) *s] \
904 || (*s == ':' \
905 && alt_notend_table[(unsigned char) s[1]])))
906
907 #ifdef OBJ_ELF
908
909 /* Return zero if the reference to SYMBOL from within the same segment may
910 be relaxed. */
911
912 /* On an ELF system, we can't relax an externally visible symbol,
913 because it may be overridden by a shared library. However, if
914 TARGET_OS is "elf", then we presume that we are assembling for an
915 embedded system, in which case we don't have to worry about shared
916 libraries, and we can relax any external sym. */
917
918 #define relaxable_symbol(symbol) \
919 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
920 || S_IS_WEAK (symbol)))
921
922 /* Compute the relocation code for a fixup of SIZE bytes, using pc
923 relative relocation if PCREL is non-zero. PIC says whether a special
924 pic relocation was requested. */
925
926 static bfd_reloc_code_real_type
927 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
928 {
929 switch (pic)
930 {
931 case pic_got_pcrel:
932 switch (size)
933 {
934 case 1:
935 return BFD_RELOC_8_GOT_PCREL;
936 case 2:
937 return BFD_RELOC_16_GOT_PCREL;
938 case 4:
939 return BFD_RELOC_32_GOT_PCREL;
940 }
941 break;
942
943 case pic_got_off:
944 switch (size)
945 {
946 case 1:
947 return BFD_RELOC_8_GOTOFF;
948 case 2:
949 return BFD_RELOC_16_GOTOFF;
950 case 4:
951 return BFD_RELOC_32_GOTOFF;
952 }
953 break;
954
955 case pic_plt_pcrel:
956 switch (size)
957 {
958 case 1:
959 return BFD_RELOC_8_PLT_PCREL;
960 case 2:
961 return BFD_RELOC_16_PLT_PCREL;
962 case 4:
963 return BFD_RELOC_32_PLT_PCREL;
964 }
965 break;
966
967 case pic_plt_off:
968 switch (size)
969 {
970 case 1:
971 return BFD_RELOC_8_PLTOFF;
972 case 2:
973 return BFD_RELOC_16_PLTOFF;
974 case 4:
975 return BFD_RELOC_32_PLTOFF;
976 }
977 break;
978
979 case pic_none:
980 if (pcrel)
981 {
982 switch (size)
983 {
984 case 1:
985 return BFD_RELOC_8_PCREL;
986 case 2:
987 return BFD_RELOC_16_PCREL;
988 case 4:
989 return BFD_RELOC_32_PCREL;
990 }
991 }
992 else
993 {
994 switch (size)
995 {
996 case 1:
997 return BFD_RELOC_8;
998 case 2:
999 return BFD_RELOC_16;
1000 case 4:
1001 return BFD_RELOC_32;
1002 }
1003 }
1004 }
1005
1006 if (pcrel)
1007 {
1008 if (pic == pic_none)
1009 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1010 else
1011 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1012 }
1013 else
1014 {
1015 if (pic == pic_none)
1016 as_bad (_("Can not do %d byte relocation"), size);
1017 else
1018 as_bad (_("Can not do %d byte pic relocation"), size);
1019 }
1020
1021 return BFD_RELOC_NONE;
1022 }
1023
1024 /* Here we decide which fixups can be adjusted to make them relative
1025 to the beginning of the section instead of the symbol. Basically
1026 we need to make sure that the dynamic relocations are done
1027 correctly, so in some cases we force the original symbol to be
1028 used. */
1029 int
1030 tc_m68k_fix_adjustable (fixS *fixP)
1031 {
1032 /* Adjust_reloc_syms doesn't know about the GOT. */
1033 switch (fixP->fx_r_type)
1034 {
1035 case BFD_RELOC_8_GOT_PCREL:
1036 case BFD_RELOC_16_GOT_PCREL:
1037 case BFD_RELOC_32_GOT_PCREL:
1038 case BFD_RELOC_8_GOTOFF:
1039 case BFD_RELOC_16_GOTOFF:
1040 case BFD_RELOC_32_GOTOFF:
1041 case BFD_RELOC_8_PLT_PCREL:
1042 case BFD_RELOC_16_PLT_PCREL:
1043 case BFD_RELOC_32_PLT_PCREL:
1044 case BFD_RELOC_8_PLTOFF:
1045 case BFD_RELOC_16_PLTOFF:
1046 case BFD_RELOC_32_PLTOFF:
1047 return 0;
1048
1049 case BFD_RELOC_VTABLE_INHERIT:
1050 case BFD_RELOC_VTABLE_ENTRY:
1051 return 0;
1052
1053 default:
1054 return 1;
1055 }
1056 }
1057
1058 #else /* !OBJ_ELF */
1059
1060 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1061
1062 /* PR gas/3041 Weak symbols are not relaxable
1063 because they must be treated as extern. */
1064 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1065
1066 #endif /* OBJ_ELF */
1067
1068 arelent *
1069 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1070 {
1071 arelent *reloc;
1072 bfd_reloc_code_real_type code;
1073
1074 /* If the tcbit is set, then this was a fixup of a negative value
1075 that was never resolved. We do not have a reloc to handle this,
1076 so just return. We assume that other code will have detected this
1077 situation and produced a helpful error message, so we just tell the
1078 user that the reloc cannot be produced. */
1079 if (fixp->fx_tcbit)
1080 {
1081 if (fixp->fx_addsy)
1082 as_bad_where (fixp->fx_file, fixp->fx_line,
1083 _("Unable to produce reloc against symbol '%s'"),
1084 S_GET_NAME (fixp->fx_addsy));
1085 return NULL;
1086 }
1087
1088 if (fixp->fx_r_type != BFD_RELOC_NONE)
1089 {
1090 code = fixp->fx_r_type;
1091
1092 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1093 that fixup_segment converted a non-PC relative reloc into a
1094 PC relative reloc. In such a case, we need to convert the
1095 reloc code. */
1096 if (fixp->fx_pcrel)
1097 {
1098 switch (code)
1099 {
1100 case BFD_RELOC_8:
1101 code = BFD_RELOC_8_PCREL;
1102 break;
1103 case BFD_RELOC_16:
1104 code = BFD_RELOC_16_PCREL;
1105 break;
1106 case BFD_RELOC_32:
1107 code = BFD_RELOC_32_PCREL;
1108 break;
1109 case BFD_RELOC_8_PCREL:
1110 case BFD_RELOC_16_PCREL:
1111 case BFD_RELOC_32_PCREL:
1112 case BFD_RELOC_8_GOT_PCREL:
1113 case BFD_RELOC_16_GOT_PCREL:
1114 case BFD_RELOC_32_GOT_PCREL:
1115 case BFD_RELOC_8_GOTOFF:
1116 case BFD_RELOC_16_GOTOFF:
1117 case BFD_RELOC_32_GOTOFF:
1118 case BFD_RELOC_8_PLT_PCREL:
1119 case BFD_RELOC_16_PLT_PCREL:
1120 case BFD_RELOC_32_PLT_PCREL:
1121 case BFD_RELOC_8_PLTOFF:
1122 case BFD_RELOC_16_PLTOFF:
1123 case BFD_RELOC_32_PLTOFF:
1124 break;
1125 default:
1126 as_bad_where (fixp->fx_file, fixp->fx_line,
1127 _("Cannot make %s relocation PC relative"),
1128 bfd_get_reloc_code_name (code));
1129 }
1130 }
1131 }
1132 else
1133 {
1134 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1135 switch (F (fixp->fx_size, fixp->fx_pcrel))
1136 {
1137 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1138 MAP (1, 0, BFD_RELOC_8);
1139 MAP (2, 0, BFD_RELOC_16);
1140 MAP (4, 0, BFD_RELOC_32);
1141 MAP (1, 1, BFD_RELOC_8_PCREL);
1142 MAP (2, 1, BFD_RELOC_16_PCREL);
1143 MAP (4, 1, BFD_RELOC_32_PCREL);
1144 default:
1145 abort ();
1146 }
1147 }
1148 #undef F
1149 #undef MAP
1150
1151 reloc = (arelent *) xmalloc (sizeof (arelent));
1152 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1153 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1154 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1155 #ifndef OBJ_ELF
1156 if (fixp->fx_pcrel)
1157 reloc->addend = fixp->fx_addnumber;
1158 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1159 && fixp->fx_addsy
1160 && S_IS_WEAK (fixp->fx_addsy)
1161 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1162 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1163 to put the symbol offset into frags referencing a weak symbol. */
1164 reloc->addend = fixp->fx_addnumber
1165 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1166 else
1167 reloc->addend = 0;
1168 #else
1169 if (!fixp->fx_pcrel)
1170 reloc->addend = fixp->fx_addnumber;
1171 else
1172 reloc->addend = (section->vma
1173 /* Explicit sign extension in case char is
1174 unsigned. */
1175 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1176 + fixp->fx_addnumber
1177 + md_pcrel_from (fixp));
1178 #endif
1179
1180 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1181 assert (reloc->howto != 0);
1182
1183 return reloc;
1184 }
1185
1186 /* Handle of the OPCODE hash table. NULL means any use before
1187 m68k_ip_begin() will crash. */
1188 static struct hash_control *op_hash;
1189 \f
1190 /* Assemble an m68k instruction. */
1191
1192 static void
1193 m68k_ip (char *instring)
1194 {
1195 register char *p;
1196 register struct m68k_op *opP;
1197 register const struct m68k_incant *opcode;
1198 register const char *s;
1199 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1200 char *pdot, *pdotmove;
1201 enum m68k_size siz1, siz2;
1202 char c;
1203 int losing;
1204 int opsfound;
1205 struct m68k_op operands_backup[6];
1206 LITTLENUM_TYPE words[6];
1207 LITTLENUM_TYPE *wordp;
1208 unsigned long ok_arch = 0;
1209
1210 if (*instring == ' ')
1211 instring++; /* Skip leading whitespace. */
1212
1213 /* Scan up to end of operation-code, which MUST end in end-of-string
1214 or exactly 1 space. */
1215 pdot = 0;
1216 for (p = instring; *p != '\0'; p++)
1217 {
1218 if (*p == ' ')
1219 break;
1220 if (*p == '.')
1221 pdot = p;
1222 }
1223
1224 if (p == instring)
1225 {
1226 the_ins.error = _("No operator");
1227 return;
1228 }
1229
1230 /* p now points to the end of the opcode name, probably whitespace.
1231 Make sure the name is null terminated by clobbering the
1232 whitespace, look it up in the hash table, then fix it back.
1233 Remove a dot, first, since the opcode tables have none. */
1234 if (pdot != NULL)
1235 {
1236 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1237 *pdotmove = pdotmove[1];
1238 p--;
1239 }
1240
1241 c = *p;
1242 *p = '\0';
1243 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1244 *p = c;
1245
1246 if (pdot != NULL)
1247 {
1248 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1249 *pdotmove = pdotmove[-1];
1250 *pdot = '.';
1251 ++p;
1252 }
1253
1254 if (opcode == NULL)
1255 {
1256 the_ins.error = _("Unknown operator");
1257 return;
1258 }
1259
1260 /* Found a legitimate opcode, start matching operands. */
1261 while (*p == ' ')
1262 ++p;
1263
1264 if (opcode->m_operands == 0)
1265 {
1266 char *old = input_line_pointer;
1267 *old = '\n';
1268 input_line_pointer = p;
1269 /* Ahh - it's a motorola style psuedo op. */
1270 mote_pseudo_table[opcode->m_opnum].poc_handler
1271 (mote_pseudo_table[opcode->m_opnum].poc_val);
1272 input_line_pointer = old;
1273 *old = 0;
1274
1275 return;
1276 }
1277
1278 if (flag_mri && opcode->m_opnum == 0)
1279 {
1280 /* In MRI mode, random garbage is allowed after an instruction
1281 which accepts no operands. */
1282 the_ins.args = opcode->m_operands;
1283 the_ins.numargs = opcode->m_opnum;
1284 the_ins.numo = opcode->m_codenum;
1285 the_ins.opcode[0] = getone (opcode);
1286 the_ins.opcode[1] = gettwo (opcode);
1287 return;
1288 }
1289
1290 for (opP = &the_ins.operands[0]; *p; opP++)
1291 {
1292 p = crack_operand (p, opP);
1293
1294 if (opP->error)
1295 {
1296 the_ins.error = opP->error;
1297 return;
1298 }
1299 }
1300
1301 opsfound = opP - &the_ins.operands[0];
1302
1303 /* This ugly hack is to support the floating pt opcodes in their
1304 standard form. Essentially, we fake a first enty of type COP#1 */
1305 if (opcode->m_operands[0] == 'I')
1306 {
1307 int n;
1308
1309 for (n = opsfound; n > 0; --n)
1310 the_ins.operands[n] = the_ins.operands[n - 1];
1311
1312 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1313 the_ins.operands[0].mode = CONTROL;
1314 the_ins.operands[0].reg = m68k_float_copnum;
1315 opsfound++;
1316 }
1317
1318 /* We've got the operands. Find an opcode that'll accept them. */
1319 for (losing = 0;;)
1320 {
1321 /* If we didn't get the right number of ops, or we have no
1322 common model with this pattern then reject this pattern. */
1323
1324 ok_arch |= opcode->m_arch;
1325 if (opsfound != opcode->m_opnum
1326 || ((opcode->m_arch & current_architecture) == 0))
1327 ++losing;
1328 else
1329 {
1330 int i;
1331
1332 /* Make a copy of the operands of this insn so that
1333 we can modify them safely, should we want to. */
1334 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1335 for (i = 0; i < opsfound; i++)
1336 operands_backup[i] = the_ins.operands[i];
1337
1338 for (s = opcode->m_operands, opP = &operands_backup[0];
1339 *s && !losing;
1340 s += 2, opP++)
1341 {
1342 /* Warning: this switch is huge! */
1343 /* I've tried to organize the cases into this order:
1344 non-alpha first, then alpha by letter. Lower-case
1345 goes directly before uppercase counterpart. */
1346 /* Code with multiple case ...: gets sorted by the lowest
1347 case ... it belongs to. I hope this makes sense. */
1348 switch (*s)
1349 {
1350 case '!':
1351 switch (opP->mode)
1352 {
1353 case IMMED:
1354 case DREG:
1355 case AREG:
1356 case FPREG:
1357 case CONTROL:
1358 case AINC:
1359 case ADEC:
1360 case REGLST:
1361 losing++;
1362 break;
1363 default:
1364 break;
1365 }
1366 break;
1367
1368 case '<':
1369 switch (opP->mode)
1370 {
1371 case DREG:
1372 case AREG:
1373 case FPREG:
1374 case CONTROL:
1375 case IMMED:
1376 case ADEC:
1377 case REGLST:
1378 losing++;
1379 break;
1380 default:
1381 break;
1382 }
1383 break;
1384
1385 case '>':
1386 switch (opP->mode)
1387 {
1388 case DREG:
1389 case AREG:
1390 case FPREG:
1391 case CONTROL:
1392 case IMMED:
1393 case AINC:
1394 case REGLST:
1395 losing++;
1396 break;
1397 case ABSL:
1398 break;
1399 default:
1400 if (opP->reg == PC
1401 || opP->reg == ZPC)
1402 losing++;
1403 break;
1404 }
1405 break;
1406
1407 case 'm':
1408 switch (opP->mode)
1409 {
1410 case DREG:
1411 case AREG:
1412 case AINDR:
1413 case AINC:
1414 case ADEC:
1415 break;
1416 default:
1417 losing++;
1418 }
1419 break;
1420
1421 case 'n':
1422 switch (opP->mode)
1423 {
1424 case DISP:
1425 break;
1426 default:
1427 losing++;
1428 }
1429 break;
1430
1431 case 'o':
1432 switch (opP->mode)
1433 {
1434 case BASE:
1435 case ABSL:
1436 case IMMED:
1437 break;
1438 default:
1439 losing++;
1440 }
1441 break;
1442
1443 case 'p':
1444 switch (opP->mode)
1445 {
1446 case DREG:
1447 case AREG:
1448 case AINDR:
1449 case AINC:
1450 case ADEC:
1451 break;
1452 case DISP:
1453 if (opP->reg == PC || opP->reg == ZPC)
1454 losing++;
1455 break;
1456 default:
1457 losing++;
1458 }
1459 break;
1460
1461 case 'q':
1462 switch (opP->mode)
1463 {
1464 case DREG:
1465 case AINDR:
1466 case AINC:
1467 case ADEC:
1468 break;
1469 case DISP:
1470 if (opP->reg == PC || opP->reg == ZPC)
1471 losing++;
1472 break;
1473 default:
1474 losing++;
1475 break;
1476 }
1477 break;
1478
1479 case 'v':
1480 switch (opP->mode)
1481 {
1482 case DREG:
1483 case AINDR:
1484 case AINC:
1485 case ADEC:
1486 case ABSL:
1487 break;
1488 case DISP:
1489 if (opP->reg == PC || opP->reg == ZPC)
1490 losing++;
1491 break;
1492 default:
1493 losing++;
1494 break;
1495 }
1496 break;
1497
1498 case '#':
1499 if (opP->mode != IMMED)
1500 losing++;
1501 else if (s[1] == 'b'
1502 && ! isvar (&opP->disp)
1503 && (opP->disp.exp.X_op != O_constant
1504 || ! isbyte (opP->disp.exp.X_add_number)))
1505 losing++;
1506 else if (s[1] == 'B'
1507 && ! isvar (&opP->disp)
1508 && (opP->disp.exp.X_op != O_constant
1509 || ! issbyte (opP->disp.exp.X_add_number)))
1510 losing++;
1511 else if (s[1] == 'w'
1512 && ! isvar (&opP->disp)
1513 && (opP->disp.exp.X_op != O_constant
1514 || ! isword (opP->disp.exp.X_add_number)))
1515 losing++;
1516 else if (s[1] == 'W'
1517 && ! isvar (&opP->disp)
1518 && (opP->disp.exp.X_op != O_constant
1519 || ! issword (opP->disp.exp.X_add_number)))
1520 losing++;
1521 break;
1522
1523 case '^':
1524 case 'T':
1525 if (opP->mode != IMMED)
1526 losing++;
1527 break;
1528
1529 case '$':
1530 if (opP->mode == AREG
1531 || opP->mode == CONTROL
1532 || opP->mode == FPREG
1533 || opP->mode == IMMED
1534 || opP->mode == REGLST
1535 || (opP->mode != ABSL
1536 && (opP->reg == PC
1537 || opP->reg == ZPC)))
1538 losing++;
1539 break;
1540
1541 case '%':
1542 if (opP->mode == CONTROL
1543 || opP->mode == FPREG
1544 || opP->mode == REGLST
1545 || opP->mode == IMMED
1546 || (opP->mode != ABSL
1547 && (opP->reg == PC
1548 || opP->reg == ZPC)))
1549 losing++;
1550 break;
1551
1552 case '&':
1553 switch (opP->mode)
1554 {
1555 case DREG:
1556 case AREG:
1557 case FPREG:
1558 case CONTROL:
1559 case IMMED:
1560 case AINC:
1561 case ADEC:
1562 case REGLST:
1563 losing++;
1564 break;
1565 case ABSL:
1566 break;
1567 default:
1568 if (opP->reg == PC
1569 || opP->reg == ZPC)
1570 losing++;
1571 break;
1572 }
1573 break;
1574
1575 case '*':
1576 if (opP->mode == CONTROL
1577 || opP->mode == FPREG
1578 || opP->mode == REGLST)
1579 losing++;
1580 break;
1581
1582 case '+':
1583 if (opP->mode != AINC)
1584 losing++;
1585 break;
1586
1587 case '-':
1588 if (opP->mode != ADEC)
1589 losing++;
1590 break;
1591
1592 case '/':
1593 switch (opP->mode)
1594 {
1595 case AREG:
1596 case CONTROL:
1597 case FPREG:
1598 case AINC:
1599 case ADEC:
1600 case IMMED:
1601 case REGLST:
1602 losing++;
1603 break;
1604 default:
1605 break;
1606 }
1607 break;
1608
1609 case ';':
1610 switch (opP->mode)
1611 {
1612 case AREG:
1613 case CONTROL:
1614 case FPREG:
1615 case REGLST:
1616 losing++;
1617 break;
1618 default:
1619 break;
1620 }
1621 break;
1622
1623 case '?':
1624 switch (opP->mode)
1625 {
1626 case AREG:
1627 case CONTROL:
1628 case FPREG:
1629 case AINC:
1630 case ADEC:
1631 case IMMED:
1632 case REGLST:
1633 losing++;
1634 break;
1635 case ABSL:
1636 break;
1637 default:
1638 if (opP->reg == PC || opP->reg == ZPC)
1639 losing++;
1640 break;
1641 }
1642 break;
1643
1644 case '@':
1645 switch (opP->mode)
1646 {
1647 case AREG:
1648 case CONTROL:
1649 case FPREG:
1650 case IMMED:
1651 case REGLST:
1652 losing++;
1653 break;
1654 default:
1655 break;
1656 }
1657 break;
1658
1659 case '~': /* For now! (JF FOO is this right?) */
1660 switch (opP->mode)
1661 {
1662 case DREG:
1663 case AREG:
1664 case CONTROL:
1665 case FPREG:
1666 case IMMED:
1667 case REGLST:
1668 losing++;
1669 break;
1670 case ABSL:
1671 break;
1672 default:
1673 if (opP->reg == PC
1674 || opP->reg == ZPC)
1675 losing++;
1676 break;
1677 }
1678 break;
1679
1680 case '3':
1681 if (opP->mode != CONTROL
1682 || (opP->reg != TT0 && opP->reg != TT1))
1683 losing++;
1684 break;
1685
1686 case 'A':
1687 if (opP->mode != AREG)
1688 losing++;
1689 break;
1690
1691 case 'a':
1692 if (opP->mode != AINDR)
1693 ++losing;
1694 break;
1695
1696 case '4':
1697 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1698 && (opP->mode != DISP
1699 || opP->reg < ADDR0
1700 || opP->reg > ADDR7))
1701 ++losing;
1702 break;
1703
1704 case 'B': /* FOO */
1705 if (opP->mode != ABSL
1706 || (flag_long_jumps
1707 && strncmp (instring, "jbsr", 4) == 0))
1708 losing++;
1709 break;
1710
1711 case 'b':
1712 switch (opP->mode)
1713 {
1714 case IMMED:
1715 case ABSL:
1716 case AREG:
1717 case FPREG:
1718 case CONTROL:
1719 case POST:
1720 case PRE:
1721 case REGLST:
1722 losing++;
1723 break;
1724 default:
1725 break;
1726 }
1727 break;
1728
1729 case 'C':
1730 if (opP->mode != CONTROL || opP->reg != CCR)
1731 losing++;
1732 break;
1733
1734 case 'd':
1735 if (opP->mode != DISP
1736 || opP->reg < ADDR0
1737 || opP->reg > ADDR7)
1738 losing++;
1739 break;
1740
1741 case 'D':
1742 if (opP->mode != DREG)
1743 losing++;
1744 break;
1745
1746 case 'E':
1747 if (opP->reg != ACC)
1748 losing++;
1749 break;
1750
1751 case 'e':
1752 if (opP->reg != ACC && opP->reg != ACC1
1753 && opP->reg != ACC2 && opP->reg != ACC3)
1754 losing++;
1755 break;
1756
1757 case 'F':
1758 if (opP->mode != FPREG)
1759 losing++;
1760 break;
1761
1762 case 'G':
1763 if (opP->reg != MACSR)
1764 losing++;
1765 break;
1766
1767 case 'g':
1768 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1769 losing++;
1770 break;
1771
1772 case 'H':
1773 if (opP->reg != MASK)
1774 losing++;
1775 break;
1776
1777 case 'I':
1778 if (opP->mode != CONTROL
1779 || opP->reg < COP0
1780 || opP->reg > COP7)
1781 losing++;
1782 break;
1783
1784 case 'i':
1785 if (opP->mode != LSH && opP->mode != RSH)
1786 losing++;
1787 break;
1788
1789 case 'J':
1790 if (opP->mode != CONTROL
1791 || opP->reg < USP
1792 || opP->reg > last_movec_reg
1793 || !control_regs)
1794 losing++;
1795 else
1796 {
1797 const enum m68k_register *rp;
1798
1799 for (rp = control_regs; *rp; rp++)
1800 {
1801 if (*rp == opP->reg)
1802 break;
1803 /* In most CPUs RAMBAR refers to control reg
1804 c05 (RAMBAR1), but a few CPUs have it
1805 refer to c04 (RAMBAR0). */
1806 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1807 {
1808 opP->reg = RAMBAR_ALT;
1809 break;
1810 }
1811 }
1812 if (*rp == 0)
1813 losing++;
1814 }
1815 break;
1816
1817 case 'k':
1818 if (opP->mode != IMMED)
1819 losing++;
1820 break;
1821
1822 case 'l':
1823 case 'L':
1824 if (opP->mode == DREG
1825 || opP->mode == AREG
1826 || opP->mode == FPREG)
1827 {
1828 if (s[1] == '8')
1829 losing++;
1830 else
1831 {
1832 switch (opP->mode)
1833 {
1834 case DREG:
1835 opP->mask = 1 << (opP->reg - DATA0);
1836 break;
1837 case AREG:
1838 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1839 break;
1840 case FPREG:
1841 opP->mask = 1 << (opP->reg - FP0 + 16);
1842 break;
1843 default:
1844 abort ();
1845 }
1846 opP->mode = REGLST;
1847 }
1848 }
1849 else if (opP->mode == CONTROL)
1850 {
1851 if (s[1] != '8')
1852 losing++;
1853 else
1854 {
1855 switch (opP->reg)
1856 {
1857 case FPI:
1858 opP->mask = 1 << 24;
1859 break;
1860 case FPS:
1861 opP->mask = 1 << 25;
1862 break;
1863 case FPC:
1864 opP->mask = 1 << 26;
1865 break;
1866 default:
1867 losing++;
1868 break;
1869 }
1870 opP->mode = REGLST;
1871 }
1872 }
1873 else if (opP->mode != REGLST)
1874 losing++;
1875 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1876 losing++;
1877 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1878 losing++;
1879 break;
1880
1881 case 'M':
1882 if (opP->mode != IMMED)
1883 losing++;
1884 else if (opP->disp.exp.X_op != O_constant
1885 || ! issbyte (opP->disp.exp.X_add_number))
1886 losing++;
1887 else if (! m68k_quick
1888 && instring[3] != 'q'
1889 && instring[4] != 'q')
1890 losing++;
1891 break;
1892
1893 case 'O':
1894 if (opP->mode != DREG
1895 && opP->mode != IMMED
1896 && opP->mode != ABSL)
1897 losing++;
1898 break;
1899
1900 case 'Q':
1901 if (opP->mode != IMMED)
1902 losing++;
1903 else if (opP->disp.exp.X_op != O_constant
1904 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1905 losing++;
1906 else if (! m68k_quick
1907 && (strncmp (instring, "add", 3) == 0
1908 || strncmp (instring, "sub", 3) == 0)
1909 && instring[3] != 'q')
1910 losing++;
1911 break;
1912
1913 case 'R':
1914 if (opP->mode != DREG && opP->mode != AREG)
1915 losing++;
1916 break;
1917
1918 case 'r':
1919 if (opP->mode != AINDR
1920 && (opP->mode != BASE
1921 || (opP->reg != 0
1922 && opP->reg != ZADDR0)
1923 || opP->disp.exp.X_op != O_absent
1924 || ((opP->index.reg < DATA0
1925 || opP->index.reg > DATA7)
1926 && (opP->index.reg < ADDR0
1927 || opP->index.reg > ADDR7))
1928 || opP->index.size != SIZE_UNSPEC
1929 || opP->index.scale != 1))
1930 losing++;
1931 break;
1932
1933 case 's':
1934 if (opP->mode != CONTROL
1935 || ! (opP->reg == FPI
1936 || opP->reg == FPS
1937 || opP->reg == FPC))
1938 losing++;
1939 break;
1940
1941 case 'S':
1942 if (opP->mode != CONTROL || opP->reg != SR)
1943 losing++;
1944 break;
1945
1946 case 't':
1947 if (opP->mode != IMMED)
1948 losing++;
1949 else if (opP->disp.exp.X_op != O_constant
1950 || TRUNC (opP->disp.exp.X_add_number) > 7)
1951 losing++;
1952 break;
1953
1954 case 'U':
1955 if (opP->mode != CONTROL || opP->reg != USP)
1956 losing++;
1957 break;
1958
1959 case 'x':
1960 if (opP->mode != IMMED)
1961 losing++;
1962 else if (opP->disp.exp.X_op != O_constant
1963 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1964 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1965 losing++;
1966 break;
1967
1968 /* JF these are out of order. We could put them
1969 in order if we were willing to put up with
1970 bunches of #ifdef m68851s in the code.
1971
1972 Don't forget that you need these operands
1973 to use 68030 MMU instructions. */
1974 #ifndef NO_68851
1975 /* Memory addressing mode used by pflushr. */
1976 case '|':
1977 if (opP->mode == CONTROL
1978 || opP->mode == FPREG
1979 || opP->mode == DREG
1980 || opP->mode == AREG
1981 || opP->mode == REGLST)
1982 losing++;
1983 /* We should accept immediate operands, but they
1984 supposedly have to be quad word, and we don't
1985 handle that. I would like to see what a Motorola
1986 assembler does before doing something here. */
1987 if (opP->mode == IMMED)
1988 losing++;
1989 break;
1990
1991 case 'f':
1992 if (opP->mode != CONTROL
1993 || (opP->reg != SFC && opP->reg != DFC))
1994 losing++;
1995 break;
1996
1997 case '0':
1998 if (opP->mode != CONTROL || opP->reg != TC)
1999 losing++;
2000 break;
2001
2002 case '1':
2003 if (opP->mode != CONTROL || opP->reg != AC)
2004 losing++;
2005 break;
2006
2007 case '2':
2008 if (opP->mode != CONTROL
2009 || (opP->reg != CAL
2010 && opP->reg != VAL
2011 && opP->reg != SCC))
2012 losing++;
2013 break;
2014
2015 case 'V':
2016 if (opP->mode != CONTROL
2017 || opP->reg != VAL)
2018 losing++;
2019 break;
2020
2021 case 'W':
2022 if (opP->mode != CONTROL
2023 || (opP->reg != DRP
2024 && opP->reg != SRP
2025 && opP->reg != CRP))
2026 losing++;
2027 break;
2028
2029 case 'w':
2030 switch (opP->mode)
2031 {
2032 case IMMED:
2033 case ABSL:
2034 case AREG:
2035 case DREG:
2036 case FPREG:
2037 case CONTROL:
2038 case POST:
2039 case PRE:
2040 case REGLST:
2041 losing++;
2042 break;
2043 default:
2044 break;
2045 }
2046 break;
2047
2048 case 'X':
2049 if (opP->mode != CONTROL
2050 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2051 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2052 losing++;
2053 break;
2054
2055 case 'Y':
2056 if (opP->mode != CONTROL || opP->reg != PSR)
2057 losing++;
2058 break;
2059
2060 case 'Z':
2061 if (opP->mode != CONTROL || opP->reg != PCSR)
2062 losing++;
2063 break;
2064 #endif
2065 case 'c':
2066 if (opP->mode != CONTROL
2067 || (opP->reg != NC
2068 && opP->reg != IC
2069 && opP->reg != DC
2070 && opP->reg != BC))
2071 losing++;
2072 break;
2073
2074 case '_':
2075 if (opP->mode != ABSL)
2076 ++losing;
2077 break;
2078
2079 case 'u':
2080 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2081 losing++;
2082 /* FIXME: kludge instead of fixing parser:
2083 upper/lower registers are *not* CONTROL
2084 registers, but ordinary ones. */
2085 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2086 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2087 opP->mode = DREG;
2088 else
2089 opP->mode = AREG;
2090 break;
2091
2092 case 'y':
2093 if (!(opP->mode == AINDR
2094 || (opP->mode == DISP
2095 && !(opP->reg == PC || opP->reg == ZPC))))
2096 losing++;
2097 break;
2098
2099 case 'z':
2100 if (!(opP->mode == AINDR || opP->mode == DISP))
2101 losing++;
2102 break;
2103
2104 default:
2105 abort ();
2106 }
2107
2108 if (losing)
2109 break;
2110 }
2111
2112 /* Since we have found the correct instruction, copy
2113 in the modifications that we may have made. */
2114 if (!losing)
2115 for (i = 0; i < opsfound; i++)
2116 the_ins.operands[i] = operands_backup[i];
2117 }
2118
2119 if (!losing)
2120 break;
2121
2122 opcode = opcode->m_next;
2123
2124 if (!opcode)
2125 {
2126 if (ok_arch
2127 && !(ok_arch & current_architecture))
2128 {
2129 const struct m68k_cpu *cpu;
2130 int any = 0;
2131 size_t space = 400;
2132 char *buf = xmalloc (space + 1);
2133 size_t len;
2134 int paren = 1;
2135
2136 the_ins.error = buf;
2137 /* Make sure there's a NUL at the end of the buffer -- strncpy
2138 won't write one when it runs out of buffer */
2139 buf[space] = 0;
2140 #define APPEND(STRING) \
2141 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2142
2143 APPEND (_("invalid instruction for this architecture; needs "));
2144 switch (ok_arch)
2145 {
2146 case mcfisa_a:
2147 APPEND (_("ColdFire ISA_A"));
2148 break;
2149 case mcfhwdiv:
2150 APPEND (_("ColdFire hardware divide"));
2151 break;
2152 case mcfisa_aa:
2153 APPEND (_("ColdFire ISA_A+"));
2154 break;
2155 case mcfisa_b:
2156 APPEND (_("ColdFire ISA_B"));
2157 break;
2158 case cfloat:
2159 APPEND (_("ColdFire fpu"));
2160 break;
2161 case mfloat:
2162 APPEND (_("M68K fpu"));
2163 break;
2164 case mmmu:
2165 APPEND (_("M68K mmu"));
2166 break;
2167 case m68020up:
2168 APPEND (_("68020 or higher"));
2169 break;
2170 case m68000up:
2171 APPEND (_("68000 or higher"));
2172 break;
2173 case m68010up:
2174 APPEND (_("68010 or higher"));
2175 break;
2176 default:
2177 paren = 0;
2178 }
2179 if (paren)
2180 APPEND (" (");
2181
2182 for (cpu = m68k_cpus; cpu->name; cpu++)
2183 if (!cpu->alias && (cpu->arch & ok_arch))
2184 {
2185 const struct m68k_cpu *alias;
2186 int seen_master = 0;
2187
2188 if (any)
2189 APPEND (", ");
2190 any = 0;
2191 APPEND (cpu->name);
2192 for (alias = cpu; alias != m68k_cpus; alias--)
2193 if (alias[-1].alias >= 0)
2194 break;
2195 for (; !seen_master || alias->alias > 0; alias++)
2196 {
2197 if (!alias->alias)
2198 seen_master = 1;
2199 else
2200 {
2201 if (any)
2202 APPEND (", ");
2203 else
2204 APPEND (" [");
2205 APPEND (alias->name);
2206 any = 1;
2207 }
2208 }
2209 if (any)
2210 APPEND ("]");
2211 any = 1;
2212 }
2213 if (paren)
2214 APPEND (")");
2215 #undef APPEND
2216 if (!space)
2217 {
2218 /* we ran out of space, so replace the end of the list
2219 with ellipsis. */
2220 buf -= 4;
2221 while (*buf != ' ')
2222 buf--;
2223 strcpy (buf, " ...");
2224 }
2225 }
2226 else
2227 the_ins.error = _("operands mismatch");
2228 return;
2229 }
2230
2231 losing = 0;
2232 }
2233
2234 /* Now assemble it. */
2235 the_ins.args = opcode->m_operands;
2236 the_ins.numargs = opcode->m_opnum;
2237 the_ins.numo = opcode->m_codenum;
2238 the_ins.opcode[0] = getone (opcode);
2239 the_ins.opcode[1] = gettwo (opcode);
2240
2241 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2242 {
2243 int have_disp = 0;
2244
2245 /* This switch is a doozy.
2246 Watch the first step; its a big one! */
2247 switch (s[0])
2248 {
2249
2250 case '*':
2251 case '~':
2252 case '%':
2253 case ';':
2254 case '@':
2255 case '!':
2256 case '&':
2257 case '$':
2258 case '?':
2259 case '/':
2260 case '<':
2261 case '>':
2262 case 'b':
2263 case 'm':
2264 case 'n':
2265 case 'o':
2266 case 'p':
2267 case 'q':
2268 case 'v':
2269 case 'w':
2270 case 'y':
2271 case 'z':
2272 case '4':
2273 #ifndef NO_68851
2274 case '|':
2275 #endif
2276 switch (opP->mode)
2277 {
2278 case IMMED:
2279 tmpreg = 0x3c; /* 7.4 */
2280 if (strchr ("bwl", s[1]))
2281 nextword = get_num (&opP->disp, 90);
2282 else
2283 nextword = get_num (&opP->disp, 0);
2284 if (isvar (&opP->disp))
2285 add_fix (s[1], &opP->disp, 0, 0);
2286 switch (s[1])
2287 {
2288 case 'b':
2289 if (!isbyte (nextword))
2290 opP->error = _("operand out of range");
2291 addword (nextword);
2292 baseo = 0;
2293 break;
2294 case 'w':
2295 if (!isword (nextword))
2296 opP->error = _("operand out of range");
2297 addword (nextword);
2298 baseo = 0;
2299 break;
2300 case 'W':
2301 if (!issword (nextword))
2302 opP->error = _("operand out of range");
2303 addword (nextword);
2304 baseo = 0;
2305 break;
2306 case 'l':
2307 addword (nextword >> 16);
2308 addword (nextword);
2309 baseo = 0;
2310 break;
2311
2312 case 'f':
2313 baseo = 2;
2314 outro = 8;
2315 break;
2316 case 'F':
2317 baseo = 4;
2318 outro = 11;
2319 break;
2320 case 'x':
2321 baseo = 6;
2322 outro = 15;
2323 break;
2324 case 'p':
2325 baseo = 6;
2326 outro = -1;
2327 break;
2328 default:
2329 abort ();
2330 }
2331 if (!baseo)
2332 break;
2333
2334 /* We gotta put out some float. */
2335 if (op (&opP->disp) != O_big)
2336 {
2337 valueT val;
2338 int gencnt;
2339
2340 /* Can other cases happen here? */
2341 if (op (&opP->disp) != O_constant)
2342 abort ();
2343
2344 val = (valueT) offs (&opP->disp);
2345 gencnt = 0;
2346 do
2347 {
2348 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2349 val >>= LITTLENUM_NUMBER_OF_BITS;
2350 ++gencnt;
2351 }
2352 while (val != 0);
2353 offs (&opP->disp) = gencnt;
2354 }
2355 if (offs (&opP->disp) > 0)
2356 {
2357 if (offs (&opP->disp) > baseo)
2358 {
2359 as_warn (_("Bignum too big for %c format; truncated"),
2360 s[1]);
2361 offs (&opP->disp) = baseo;
2362 }
2363 baseo -= offs (&opP->disp);
2364 while (baseo--)
2365 addword (0);
2366 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2367 offs (&opP->disp)--;
2368 --wordp)
2369 addword (*wordp);
2370 break;
2371 }
2372 gen_to_words (words, baseo, (long) outro);
2373 for (wordp = words; baseo--; wordp++)
2374 addword (*wordp);
2375 break;
2376 case DREG:
2377 tmpreg = opP->reg - DATA; /* 0.dreg */
2378 break;
2379 case AREG:
2380 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2381 break;
2382 case AINDR:
2383 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2384 break;
2385 case ADEC:
2386 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2387 break;
2388 case AINC:
2389 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2390 break;
2391 case DISP:
2392
2393 nextword = get_num (&opP->disp, 90);
2394
2395 /* Convert mode 5 addressing with a zero offset into
2396 mode 2 addressing to reduce the instruction size by a
2397 word. */
2398 if (! isvar (&opP->disp)
2399 && (nextword == 0)
2400 && (opP->disp.size == SIZE_UNSPEC)
2401 && (opP->reg >= ADDR0)
2402 && (opP->reg <= ADDR7))
2403 {
2404 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2405 break;
2406 }
2407
2408 if (opP->reg == PC
2409 && ! isvar (&opP->disp)
2410 && m68k_abspcadd)
2411 {
2412 opP->disp.exp.X_op = O_symbol;
2413 opP->disp.exp.X_add_symbol =
2414 section_symbol (absolute_section);
2415 }
2416
2417 /* Force into index mode. Hope this works. */
2418
2419 /* We do the first bit for 32-bit displacements, and the
2420 second bit for 16 bit ones. It is possible that we
2421 should make the default be WORD instead of LONG, but
2422 I think that'd break GCC, so we put up with a little
2423 inefficiency for the sake of working output. */
2424
2425 if (!issword (nextword)
2426 || (isvar (&opP->disp)
2427 && ((opP->disp.size == SIZE_UNSPEC
2428 && flag_short_refs == 0
2429 && cpu_of_arch (current_architecture) >= m68020
2430 && ! arch_coldfire_p (current_architecture))
2431 || opP->disp.size == SIZE_LONG)))
2432 {
2433 if (cpu_of_arch (current_architecture) < m68020
2434 || arch_coldfire_p (current_architecture))
2435 opP->error =
2436 _("displacement too large for this architecture; needs 68020 or higher");
2437 if (opP->reg == PC)
2438 tmpreg = 0x3B; /* 7.3 */
2439 else
2440 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2441 if (isvar (&opP->disp))
2442 {
2443 if (opP->reg == PC)
2444 {
2445 if (opP->disp.size == SIZE_LONG
2446 #ifdef OBJ_ELF
2447 /* If the displacement needs pic
2448 relocation it cannot be relaxed. */
2449 || opP->disp.pic_reloc != pic_none
2450 #endif
2451 )
2452 {
2453 addword (0x0170);
2454 add_fix ('l', &opP->disp, 1, 2);
2455 }
2456 else
2457 {
2458 add_frag (adds (&opP->disp),
2459 SEXT (offs (&opP->disp)),
2460 TAB (PCREL1632, SZ_UNDEF));
2461 break;
2462 }
2463 }
2464 else
2465 {
2466 addword (0x0170);
2467 add_fix ('l', &opP->disp, 0, 0);
2468 }
2469 }
2470 else
2471 addword (0x0170);
2472 addword (nextword >> 16);
2473 }
2474 else
2475 {
2476 if (opP->reg == PC)
2477 tmpreg = 0x3A; /* 7.2 */
2478 else
2479 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2480
2481 if (isvar (&opP->disp))
2482 {
2483 if (opP->reg == PC)
2484 {
2485 add_fix ('w', &opP->disp, 1, 0);
2486 }
2487 else
2488 add_fix ('w', &opP->disp, 0, 0);
2489 }
2490 }
2491 addword (nextword);
2492 break;
2493
2494 case POST:
2495 case PRE:
2496 case BASE:
2497 nextword = 0;
2498 baseo = get_num (&opP->disp, 90);
2499 if (opP->mode == POST || opP->mode == PRE)
2500 outro = get_num (&opP->odisp, 90);
2501 /* Figure out the `addressing mode'.
2502 Also turn on the BASE_DISABLE bit, if needed. */
2503 if (opP->reg == PC || opP->reg == ZPC)
2504 {
2505 tmpreg = 0x3b; /* 7.3 */
2506 if (opP->reg == ZPC)
2507 nextword |= 0x80;
2508 }
2509 else if (opP->reg == 0)
2510 {
2511 nextword |= 0x80;
2512 tmpreg = 0x30; /* 6.garbage */
2513 }
2514 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2515 {
2516 nextword |= 0x80;
2517 tmpreg = 0x30 + opP->reg - ZADDR0;
2518 }
2519 else
2520 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2521
2522 siz1 = opP->disp.size;
2523 if (opP->mode == POST || opP->mode == PRE)
2524 siz2 = opP->odisp.size;
2525 else
2526 siz2 = SIZE_UNSPEC;
2527
2528 /* Index register stuff. */
2529 if (opP->index.reg != 0
2530 && opP->index.reg >= DATA
2531 && opP->index.reg <= ADDR7)
2532 {
2533 nextword |= (opP->index.reg - DATA) << 12;
2534
2535 if (opP->index.size == SIZE_LONG
2536 || (opP->index.size == SIZE_UNSPEC
2537 && m68k_index_width_default == SIZE_LONG))
2538 nextword |= 0x800;
2539
2540 if ((opP->index.scale != 1
2541 && cpu_of_arch (current_architecture) < m68020)
2542 || (opP->index.scale == 8
2543 && (arch_coldfire_p (current_architecture)
2544 && !arch_coldfire_fpu (current_architecture))))
2545 {
2546 opP->error =
2547 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2548 }
2549
2550 if (arch_coldfire_p (current_architecture)
2551 && opP->index.size == SIZE_WORD)
2552 opP->error = _("invalid index size for coldfire");
2553
2554 switch (opP->index.scale)
2555 {
2556 case 1:
2557 break;
2558 case 2:
2559 nextword |= 0x200;
2560 break;
2561 case 4:
2562 nextword |= 0x400;
2563 break;
2564 case 8:
2565 nextword |= 0x600;
2566 break;
2567 default:
2568 abort ();
2569 }
2570 /* IF its simple,
2571 GET US OUT OF HERE! */
2572
2573 /* Must be INDEX, with an index register. Address
2574 register cannot be ZERO-PC, and either :b was
2575 forced, or we know it will fit. For a 68000 or
2576 68010, force this mode anyways, because the
2577 larger modes aren't supported. */
2578 if (opP->mode == BASE
2579 && ((opP->reg >= ADDR0
2580 && opP->reg <= ADDR7)
2581 || opP->reg == PC))
2582 {
2583 if (siz1 == SIZE_BYTE
2584 || cpu_of_arch (current_architecture) < m68020
2585 || arch_coldfire_p (current_architecture)
2586 || (siz1 == SIZE_UNSPEC
2587 && ! isvar (&opP->disp)
2588 && issbyte (baseo)))
2589 {
2590 nextword += baseo & 0xff;
2591 addword (nextword);
2592 if (isvar (&opP->disp))
2593 {
2594 /* Do a byte relocation. If it doesn't
2595 fit (possible on m68000) let the
2596 fixup processing complain later. */
2597 if (opP->reg == PC)
2598 add_fix ('B', &opP->disp, 1, 1);
2599 else
2600 add_fix ('B', &opP->disp, 0, 0);
2601 }
2602 else if (siz1 != SIZE_BYTE)
2603 {
2604 if (siz1 != SIZE_UNSPEC)
2605 as_warn (_("Forcing byte displacement"));
2606 if (! issbyte (baseo))
2607 opP->error = _("byte displacement out of range");
2608 }
2609
2610 break;
2611 }
2612 else if (siz1 == SIZE_UNSPEC
2613 && opP->reg == PC
2614 && isvar (&opP->disp)
2615 && subs (&opP->disp) == NULL
2616 #ifdef OBJ_ELF
2617 /* If the displacement needs pic
2618 relocation it cannot be relaxed. */
2619 && opP->disp.pic_reloc == pic_none
2620 #endif
2621 )
2622 {
2623 /* The code in md_convert_frag_1 needs to be
2624 able to adjust nextword. Call frag_grow
2625 to ensure that we have enough space in
2626 the frag obstack to make all the bytes
2627 contiguous. */
2628 frag_grow (14);
2629 nextword += baseo & 0xff;
2630 addword (nextword);
2631 add_frag (adds (&opP->disp),
2632 SEXT (offs (&opP->disp)),
2633 TAB (PCINDEX, SZ_UNDEF));
2634
2635 break;
2636 }
2637 }
2638 }
2639 else
2640 {
2641 nextword |= 0x40; /* No index reg. */
2642 if (opP->index.reg >= ZDATA0
2643 && opP->index.reg <= ZDATA7)
2644 nextword |= (opP->index.reg - ZDATA0) << 12;
2645 else if (opP->index.reg >= ZADDR0
2646 || opP->index.reg <= ZADDR7)
2647 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2648 }
2649
2650 /* It isn't simple. */
2651
2652 if (cpu_of_arch (current_architecture) < m68020
2653 || arch_coldfire_p (current_architecture))
2654 opP->error =
2655 _("invalid operand mode for this architecture; needs 68020 or higher");
2656
2657 nextword |= 0x100;
2658 /* If the guy specified a width, we assume that it is
2659 wide enough. Maybe it isn't. If so, we lose. */
2660 switch (siz1)
2661 {
2662 case SIZE_UNSPEC:
2663 if (isvar (&opP->disp)
2664 ? m68k_rel32
2665 : ! issword (baseo))
2666 {
2667 siz1 = SIZE_LONG;
2668 nextword |= 0x30;
2669 }
2670 else if (! isvar (&opP->disp) && baseo == 0)
2671 nextword |= 0x10;
2672 else
2673 {
2674 nextword |= 0x20;
2675 siz1 = SIZE_WORD;
2676 }
2677 break;
2678 case SIZE_BYTE:
2679 as_warn (_(":b not permitted; defaulting to :w"));
2680 /* Fall through. */
2681 case SIZE_WORD:
2682 nextword |= 0x20;
2683 break;
2684 case SIZE_LONG:
2685 nextword |= 0x30;
2686 break;
2687 }
2688
2689 /* Figure out inner displacement stuff. */
2690 if (opP->mode == POST || opP->mode == PRE)
2691 {
2692 if (cpu_of_arch (current_architecture) & cpu32)
2693 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2694 switch (siz2)
2695 {
2696 case SIZE_UNSPEC:
2697 if (isvar (&opP->odisp)
2698 ? m68k_rel32
2699 : ! issword (outro))
2700 {
2701 siz2 = SIZE_LONG;
2702 nextword |= 0x3;
2703 }
2704 else if (! isvar (&opP->odisp) && outro == 0)
2705 nextword |= 0x1;
2706 else
2707 {
2708 nextword |= 0x2;
2709 siz2 = SIZE_WORD;
2710 }
2711 break;
2712 case 1:
2713 as_warn (_(":b not permitted; defaulting to :w"));
2714 /* Fall through. */
2715 case 2:
2716 nextword |= 0x2;
2717 break;
2718 case 3:
2719 nextword |= 0x3;
2720 break;
2721 }
2722 if (opP->mode == POST
2723 && (nextword & 0x40) == 0)
2724 nextword |= 0x04;
2725 }
2726 addword (nextword);
2727
2728 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2729 {
2730 if (opP->reg == PC || opP->reg == ZPC)
2731 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2732 else
2733 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2734 }
2735 if (siz1 == SIZE_LONG)
2736 addword (baseo >> 16);
2737 if (siz1 != SIZE_UNSPEC)
2738 addword (baseo);
2739
2740 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2741 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2742 if (siz2 == SIZE_LONG)
2743 addword (outro >> 16);
2744 if (siz2 != SIZE_UNSPEC)
2745 addword (outro);
2746
2747 break;
2748
2749 case ABSL:
2750 nextword = get_num (&opP->disp, 90);
2751 switch (opP->disp.size)
2752 {
2753 default:
2754 abort ();
2755 case SIZE_UNSPEC:
2756 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2757 {
2758 tmpreg = 0x38; /* 7.0 */
2759 addword (nextword);
2760 break;
2761 }
2762 if (isvar (&opP->disp)
2763 && !subs (&opP->disp)
2764 && adds (&opP->disp)
2765 #ifdef OBJ_ELF
2766 /* If the displacement needs pic relocation it
2767 cannot be relaxed. */
2768 && opP->disp.pic_reloc == pic_none
2769 #endif
2770 && !flag_long_jumps
2771 && !strchr ("~%&$?", s[0]))
2772 {
2773 tmpreg = 0x3A; /* 7.2 */
2774 add_frag (adds (&opP->disp),
2775 SEXT (offs (&opP->disp)),
2776 TAB (ABSTOPCREL, SZ_UNDEF));
2777 break;
2778 }
2779 /* Fall through into long. */
2780 case SIZE_LONG:
2781 if (isvar (&opP->disp))
2782 add_fix ('l', &opP->disp, 0, 0);
2783
2784 tmpreg = 0x39;/* 7.1 mode */
2785 addword (nextword >> 16);
2786 addword (nextword);
2787 break;
2788
2789 case SIZE_BYTE:
2790 as_bad (_("unsupported byte value; use a different suffix"));
2791 /* Fall through. */
2792
2793 case SIZE_WORD:
2794 if (isvar (&opP->disp))
2795 add_fix ('w', &opP->disp, 0, 0);
2796
2797 tmpreg = 0x38;/* 7.0 mode */
2798 addword (nextword);
2799 break;
2800 }
2801 break;
2802 case CONTROL:
2803 case FPREG:
2804 default:
2805 as_bad (_("unknown/incorrect operand"));
2806 /* abort (); */
2807 }
2808
2809 /* If s[0] is '4', then this is for the mac instructions
2810 that can have a trailing_ampersand set. If so, set 0x100
2811 bit on tmpreg so install_gen_operand can check for it and
2812 set the appropriate bit (word2, bit 5). */
2813 if (s[0] == '4')
2814 {
2815 if (opP->trailing_ampersand)
2816 tmpreg |= 0x100;
2817 }
2818 install_gen_operand (s[1], tmpreg);
2819 break;
2820
2821 case '#':
2822 case '^':
2823 switch (s[1])
2824 { /* JF: I hate floating point! */
2825 case 'j':
2826 tmpreg = 70;
2827 break;
2828 case '8':
2829 tmpreg = 20;
2830 break;
2831 case 'C':
2832 tmpreg = 50;
2833 break;
2834 case '3':
2835 default:
2836 tmpreg = 90;
2837 break;
2838 }
2839 tmpreg = get_num (&opP->disp, tmpreg);
2840 if (isvar (&opP->disp))
2841 add_fix (s[1], &opP->disp, 0, 0);
2842 switch (s[1])
2843 {
2844 case 'b': /* Danger: These do no check for
2845 certain types of overflow.
2846 user beware! */
2847 if (!isbyte (tmpreg))
2848 opP->error = _("out of range");
2849 insop (tmpreg, opcode);
2850 if (isvar (&opP->disp))
2851 the_ins.reloc[the_ins.nrel - 1].n =
2852 (opcode->m_codenum) * 2 + 1;
2853 break;
2854 case 'B':
2855 if (!issbyte (tmpreg))
2856 opP->error = _("out of range");
2857 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2858 if (isvar (&opP->disp))
2859 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2860 break;
2861 case 'w':
2862 if (!isword (tmpreg))
2863 opP->error = _("out of range");
2864 insop (tmpreg, opcode);
2865 if (isvar (&opP->disp))
2866 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2867 break;
2868 case 'W':
2869 if (!issword (tmpreg))
2870 opP->error = _("out of range");
2871 insop (tmpreg, opcode);
2872 if (isvar (&opP->disp))
2873 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2874 break;
2875 case 'l':
2876 /* Because of the way insop works, we put these two out
2877 backwards. */
2878 insop (tmpreg, opcode);
2879 insop (tmpreg >> 16, opcode);
2880 if (isvar (&opP->disp))
2881 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2882 break;
2883 case '3':
2884 tmpreg &= 0xFF;
2885 case '8':
2886 case 'C':
2887 case 'j':
2888 install_operand (s[1], tmpreg);
2889 break;
2890 default:
2891 abort ();
2892 }
2893 break;
2894
2895 case '+':
2896 case '-':
2897 case 'A':
2898 case 'a':
2899 install_operand (s[1], opP->reg - ADDR);
2900 break;
2901
2902 case 'B':
2903 tmpreg = get_num (&opP->disp, 90);
2904
2905 switch (s[1])
2906 {
2907 case 'B':
2908 add_fix ('B', &opP->disp, 1, -1);
2909 break;
2910 case 'W':
2911 add_fix ('w', &opP->disp, 1, 0);
2912 addword (0);
2913 break;
2914 case 'L':
2915 long_branch:
2916 the_ins.opcode[0] |= 0xff;
2917 add_fix ('l', &opP->disp, 1, 0);
2918 addword (0);
2919 addword (0);
2920 break;
2921 case 'g': /* Conditional branch */
2922 have_disp = HAVE_LONG_CALL (current_architecture);
2923 goto var_branch;
2924
2925 case 'b': /* Unconditional branch */
2926 have_disp = HAVE_LONG_BRANCH (current_architecture);
2927 goto var_branch;
2928
2929 case 's': /* Unconditional subroutine */
2930 have_disp = HAVE_LONG_CALL (current_architecture);
2931
2932 var_branch:
2933 if (subs (&opP->disp) /* We can't relax it. */
2934 #ifdef OBJ_ELF
2935 /* If the displacement needs pic relocation it cannot be
2936 relaxed. */
2937 || opP->disp.pic_reloc != pic_none
2938 #endif
2939 || 0)
2940 {
2941 if (!have_disp)
2942 as_warn (_("Can't use long branches on this architecture"));
2943 goto long_branch;
2944 }
2945
2946 /* This could either be a symbol, or an absolute
2947 address. If it's an absolute address, turn it into
2948 an absolute jump right here and keep it out of the
2949 relaxer. */
2950 if (adds (&opP->disp) == 0)
2951 {
2952 if (the_ins.opcode[0] == 0x6000) /* jbra */
2953 the_ins.opcode[0] = 0x4EF9;
2954 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2955 the_ins.opcode[0] = 0x4EB9;
2956 else /* jCC */
2957 {
2958 the_ins.opcode[0] ^= 0x0100;
2959 the_ins.opcode[0] |= 0x0006;
2960 addword (0x4EF9);
2961 }
2962 add_fix ('l', &opP->disp, 0, 0);
2963 addword (0);
2964 addword (0);
2965 break;
2966 }
2967
2968 /* Now we know it's going into the relaxer. Now figure
2969 out which mode. We try in this order of preference:
2970 long branch, absolute jump, byte/word branches only. */
2971 if (have_disp)
2972 add_frag (adds (&opP->disp),
2973 SEXT (offs (&opP->disp)),
2974 TAB (BRANCHBWL, SZ_UNDEF));
2975 else if (! flag_keep_pcrel)
2976 {
2977 if ((the_ins.opcode[0] == 0x6000)
2978 || (the_ins.opcode[0] == 0x6100))
2979 add_frag (adds (&opP->disp),
2980 SEXT (offs (&opP->disp)),
2981 TAB (BRABSJUNC, SZ_UNDEF));
2982 else
2983 add_frag (adds (&opP->disp),
2984 SEXT (offs (&opP->disp)),
2985 TAB (BRABSJCOND, SZ_UNDEF));
2986 }
2987 else
2988 add_frag (adds (&opP->disp),
2989 SEXT (offs (&opP->disp)),
2990 TAB (BRANCHBW, SZ_UNDEF));
2991 break;
2992 case 'w':
2993 if (isvar (&opP->disp))
2994 {
2995 /* Check for DBcc instructions. We can relax them,
2996 but only if we have long branches and/or absolute
2997 jumps. */
2998 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2999 && (HAVE_LONG_BRANCH (current_architecture)
3000 || ! flag_keep_pcrel))
3001 {
3002 if (HAVE_LONG_BRANCH (current_architecture))
3003 add_frag (adds (&opP->disp),
3004 SEXT (offs (&opP->disp)),
3005 TAB (DBCCLBR, SZ_UNDEF));
3006 else
3007 add_frag (adds (&opP->disp),
3008 SEXT (offs (&opP->disp)),
3009 TAB (DBCCABSJ, SZ_UNDEF));
3010 break;
3011 }
3012 add_fix ('w', &opP->disp, 1, 0);
3013 }
3014 addword (0);
3015 break;
3016 case 'C': /* Fixed size LONG coproc branches. */
3017 add_fix ('l', &opP->disp, 1, 0);
3018 addword (0);
3019 addword (0);
3020 break;
3021 case 'c': /* Var size Coprocesssor branches. */
3022 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3023 {
3024 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3025 add_fix ('l', &opP->disp, 1, 0);
3026 addword (0);
3027 addword (0);
3028 }
3029 else
3030 add_frag (adds (&opP->disp),
3031 SEXT (offs (&opP->disp)),
3032 TAB (FBRANCH, SZ_UNDEF));
3033 break;
3034 default:
3035 abort ();
3036 }
3037 break;
3038
3039 case 'C': /* Ignore it. */
3040 break;
3041
3042 case 'd': /* JF this is a kludge. */
3043 install_operand ('s', opP->reg - ADDR);
3044 tmpreg = get_num (&opP->disp, 90);
3045 if (!issword (tmpreg))
3046 {
3047 as_warn (_("Expression out of range, using 0"));
3048 tmpreg = 0;
3049 }
3050 addword (tmpreg);
3051 break;
3052
3053 case 'D':
3054 install_operand (s[1], opP->reg - DATA);
3055 break;
3056
3057 case 'e': /* EMAC ACCx, reg/reg. */
3058 install_operand (s[1], opP->reg - ACC);
3059 break;
3060
3061 case 'E': /* Ignore it. */
3062 break;
3063
3064 case 'F':
3065 install_operand (s[1], opP->reg - FP0);
3066 break;
3067
3068 case 'g': /* EMAC ACCEXTx. */
3069 install_operand (s[1], opP->reg - ACCEXT01);
3070 break;
3071
3072 case 'G': /* Ignore it. */
3073 case 'H':
3074 break;
3075
3076 case 'I':
3077 tmpreg = opP->reg - COP0;
3078 install_operand (s[1], tmpreg);
3079 break;
3080
3081 case 'i': /* MAC/EMAC scale factor. */
3082 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3083 break;
3084
3085 case 'J': /* JF foo. */
3086 switch (opP->reg)
3087 {
3088 case SFC:
3089 tmpreg = 0x000;
3090 break;
3091 case DFC:
3092 tmpreg = 0x001;
3093 break;
3094 case CACR:
3095 tmpreg = 0x002;
3096 break;
3097 case TC:
3098 case ASID:
3099 tmpreg = 0x003;
3100 break;
3101 case ACR0:
3102 case ITT0:
3103 tmpreg = 0x004;
3104 break;
3105 case ACR1:
3106 case ITT1:
3107 tmpreg = 0x005;
3108 break;
3109 case ACR2:
3110 case DTT0:
3111 tmpreg = 0x006;
3112 break;
3113 case ACR3:
3114 case DTT1:
3115 tmpreg = 0x007;
3116 break;
3117 case BUSCR:
3118 case MMUBAR:
3119 tmpreg = 0x008;
3120 break;
3121
3122 case USP:
3123 tmpreg = 0x800;
3124 break;
3125 case VBR:
3126 tmpreg = 0x801;
3127 break;
3128 case CAAR:
3129 tmpreg = 0x802;
3130 break;
3131 case MSP:
3132 tmpreg = 0x803;
3133 break;
3134 case ISP:
3135 tmpreg = 0x804;
3136 break;
3137 case MMUSR:
3138 tmpreg = 0x805;
3139 break;
3140 case URP:
3141 tmpreg = 0x806;
3142 break;
3143 case SRP:
3144 tmpreg = 0x807;
3145 break;
3146 case PCR:
3147 tmpreg = 0x808;
3148 break;
3149 case ROMBAR:
3150 case ROMBAR0:
3151 tmpreg = 0xC00;
3152 break;
3153 case ROMBAR1:
3154 tmpreg = 0xC01;
3155 break;
3156 case FLASHBAR:
3157 case RAMBAR0:
3158 case RAMBAR_ALT:
3159 tmpreg = 0xC04;
3160 break;
3161 case RAMBAR:
3162 case RAMBAR1:
3163 tmpreg = 0xC05;
3164 break;
3165 case MPCR:
3166 tmpreg = 0xC0C;
3167 break;
3168 case EDRAMBAR:
3169 tmpreg = 0xC0D;
3170 break;
3171 case MBAR0:
3172 case MBAR2:
3173 case SECMBAR:
3174 tmpreg = 0xC0E;
3175 break;
3176 case MBAR1:
3177 case MBAR:
3178 tmpreg = 0xC0F;
3179 break;
3180 case PCR1U0:
3181 tmpreg = 0xD02;
3182 break;
3183 case PCR1L0:
3184 tmpreg = 0xD03;
3185 break;
3186 case PCR2U0:
3187 tmpreg = 0xD04;
3188 break;
3189 case PCR2L0:
3190 tmpreg = 0xD05;
3191 break;
3192 case PCR3U0:
3193 tmpreg = 0xD06;
3194 break;
3195 case PCR3L0:
3196 tmpreg = 0xD07;
3197 break;
3198 case PCR1L1:
3199 tmpreg = 0xD0A;
3200 break;
3201 case PCR1U1:
3202 tmpreg = 0xD0B;
3203 break;
3204 case PCR2L1:
3205 tmpreg = 0xD0C;
3206 break;
3207 case PCR2U1:
3208 tmpreg = 0xD0D;
3209 break;
3210 case PCR3L1:
3211 tmpreg = 0xD0E;
3212 break;
3213 case PCR3U1:
3214 tmpreg = 0xD0F;
3215 break;
3216 case CAC:
3217 tmpreg = 0xFFE;
3218 break;
3219 case MBB:
3220 tmpreg = 0xFFF;
3221 break;
3222 default:
3223 abort ();
3224 }
3225 install_operand (s[1], tmpreg);
3226 break;
3227
3228 case 'k':
3229 tmpreg = get_num (&opP->disp, 55);
3230 install_operand (s[1], tmpreg & 0x7f);
3231 break;
3232
3233 case 'l':
3234 tmpreg = opP->mask;
3235 if (s[1] == 'w')
3236 {
3237 if (tmpreg & 0x7FF0000)
3238 as_bad (_("Floating point register in register list"));
3239 insop (reverse_16_bits (tmpreg), opcode);
3240 }
3241 else
3242 {
3243 if (tmpreg & 0x700FFFF)
3244 as_bad (_("Wrong register in floating-point reglist"));
3245 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3246 }
3247 break;
3248
3249 case 'L':
3250 tmpreg = opP->mask;
3251 if (s[1] == 'w')
3252 {
3253 if (tmpreg & 0x7FF0000)
3254 as_bad (_("Floating point register in register list"));
3255 insop (tmpreg, opcode);
3256 }
3257 else if (s[1] == '8')
3258 {
3259 if (tmpreg & 0x0FFFFFF)
3260 as_bad (_("incorrect register in reglist"));
3261 install_operand (s[1], tmpreg >> 24);
3262 }
3263 else
3264 {
3265 if (tmpreg & 0x700FFFF)
3266 as_bad (_("wrong register in floating-point reglist"));
3267 else
3268 install_operand (s[1], tmpreg >> 16);
3269 }
3270 break;
3271
3272 case 'M':
3273 install_operand (s[1], get_num (&opP->disp, 60));
3274 break;
3275
3276 case 'O':
3277 tmpreg = ((opP->mode == DREG)
3278 ? 0x20 + (int) (opP->reg - DATA)
3279 : (get_num (&opP->disp, 40) & 0x1F));
3280 install_operand (s[1], tmpreg);
3281 break;
3282
3283 case 'Q':
3284 tmpreg = get_num (&opP->disp, 10);
3285 if (tmpreg == 8)
3286 tmpreg = 0;
3287 install_operand (s[1], tmpreg);
3288 break;
3289
3290 case 'R':
3291 /* This depends on the fact that ADDR registers are eight
3292 more than their corresponding DATA regs, so the result
3293 will have the ADDR_REG bit set. */
3294 install_operand (s[1], opP->reg - DATA);
3295 break;
3296
3297 case 'r':
3298 if (opP->mode == AINDR)
3299 install_operand (s[1], opP->reg - DATA);
3300 else
3301 install_operand (s[1], opP->index.reg - DATA);
3302 break;
3303
3304 case 's':
3305 if (opP->reg == FPI)
3306 tmpreg = 0x1;
3307 else if (opP->reg == FPS)
3308 tmpreg = 0x2;
3309 else if (opP->reg == FPC)
3310 tmpreg = 0x4;
3311 else
3312 abort ();
3313 install_operand (s[1], tmpreg);
3314 break;
3315
3316 case 'S': /* Ignore it. */
3317 break;
3318
3319 case 'T':
3320 install_operand (s[1], get_num (&opP->disp, 30));
3321 break;
3322
3323 case 'U': /* Ignore it. */
3324 break;
3325
3326 case 'c':
3327 switch (opP->reg)
3328 {
3329 case NC:
3330 tmpreg = 0;
3331 break;
3332 case DC:
3333 tmpreg = 1;
3334 break;
3335 case IC:
3336 tmpreg = 2;
3337 break;
3338 case BC:
3339 tmpreg = 3;
3340 break;
3341 default:
3342 as_fatal (_("failed sanity check"));
3343 } /* switch on cache token. */
3344 install_operand (s[1], tmpreg);
3345 break;
3346 #ifndef NO_68851
3347 /* JF: These are out of order, I fear. */
3348 case 'f':
3349 switch (opP->reg)
3350 {
3351 case SFC:
3352 tmpreg = 0;
3353 break;
3354 case DFC:
3355 tmpreg = 1;
3356 break;
3357 default:
3358 abort ();
3359 }
3360 install_operand (s[1], tmpreg);
3361 break;
3362
3363 case '0':
3364 case '1':
3365 case '2':
3366 switch (opP->reg)
3367 {
3368 case TC:
3369 tmpreg = 0;
3370 break;
3371 case CAL:
3372 tmpreg = 4;
3373 break;
3374 case VAL:
3375 tmpreg = 5;
3376 break;
3377 case SCC:
3378 tmpreg = 6;
3379 break;
3380 case AC:
3381 tmpreg = 7;
3382 break;
3383 default:
3384 abort ();
3385 }
3386 install_operand (s[1], tmpreg);
3387 break;
3388
3389 case 'V':
3390 if (opP->reg == VAL)
3391 break;
3392 abort ();
3393
3394 case 'W':
3395 switch (opP->reg)
3396 {
3397 case DRP:
3398 tmpreg = 1;
3399 break;
3400 case SRP:
3401 tmpreg = 2;
3402 break;
3403 case CRP:
3404 tmpreg = 3;
3405 break;
3406 default:
3407 abort ();
3408 }
3409 install_operand (s[1], tmpreg);
3410 break;
3411
3412 case 'X':
3413 switch (opP->reg)
3414 {
3415 case BAD:
3416 case BAD + 1:
3417 case BAD + 2:
3418 case BAD + 3:
3419 case BAD + 4:
3420 case BAD + 5:
3421 case BAD + 6:
3422 case BAD + 7:
3423 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3424 break;
3425
3426 case BAC:
3427 case BAC + 1:
3428 case BAC + 2:
3429 case BAC + 3:
3430 case BAC + 4:
3431 case BAC + 5:
3432 case BAC + 6:
3433 case BAC + 7:
3434 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3435 break;
3436
3437 default:
3438 abort ();
3439 }
3440 install_operand (s[1], tmpreg);
3441 break;
3442 case 'Y':
3443 know (opP->reg == PSR);
3444 break;
3445 case 'Z':
3446 know (opP->reg == PCSR);
3447 break;
3448 #endif /* m68851 */
3449 case '3':
3450 switch (opP->reg)
3451 {
3452 case TT0:
3453 tmpreg = 2;
3454 break;
3455 case TT1:
3456 tmpreg = 3;
3457 break;
3458 default:
3459 abort ();
3460 }
3461 install_operand (s[1], tmpreg);
3462 break;
3463 case 't':
3464 tmpreg = get_num (&opP->disp, 20);
3465 install_operand (s[1], tmpreg);
3466 break;
3467 case '_': /* used only for move16 absolute 32-bit address. */
3468 if (isvar (&opP->disp))
3469 add_fix ('l', &opP->disp, 0, 0);
3470 tmpreg = get_num (&opP->disp, 90);
3471 addword (tmpreg >> 16);
3472 addword (tmpreg & 0xFFFF);
3473 break;
3474 case 'u':
3475 install_operand (s[1], opP->reg - DATA0L);
3476 opP->reg -= (DATA0L);
3477 opP->reg &= 0x0F; /* remove upper/lower bit. */
3478 break;
3479 case 'x':
3480 tmpreg = get_num (&opP->disp, 80);
3481 if (tmpreg == -1)
3482 tmpreg = 0;
3483 install_operand (s[1], tmpreg);
3484 break;
3485 default:
3486 abort ();
3487 }
3488 }
3489
3490 /* By the time whe get here (FINALLY) the_ins contains the complete
3491 instruction, ready to be emitted. . . */
3492 }
3493
3494 static int
3495 reverse_16_bits (int in)
3496 {
3497 int out = 0;
3498 int n;
3499
3500 static int mask[16] =
3501 {
3502 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3503 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3504 };
3505 for (n = 0; n < 16; n++)
3506 {
3507 if (in & mask[n])
3508 out |= mask[15 - n];
3509 }
3510 return out;
3511 } /* reverse_16_bits() */
3512
3513 static int
3514 reverse_8_bits (int in)
3515 {
3516 int out = 0;
3517 int n;
3518
3519 static int mask[8] =
3520 {
3521 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3522 };
3523
3524 for (n = 0; n < 8; n++)
3525 {
3526 if (in & mask[n])
3527 out |= mask[7 - n];
3528 }
3529 return out;
3530 } /* reverse_8_bits() */
3531
3532 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3533 (that value is chosen in the frag_var call in md_assemble). TYPE
3534 is the subtype of the frag to be generated; its primary type is
3535 rs_machine_dependent.
3536
3537 The TYPE parameter is also used by md_convert_frag_1 and
3538 md_estimate_size_before_relax. The appropriate type of fixup will
3539 be emitted by md_convert_frag_1.
3540
3541 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3542 static void
3543 install_operand (int mode, int val)
3544 {
3545 switch (mode)
3546 {
3547 case 's':
3548 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3549 break;
3550 case 'd':
3551 the_ins.opcode[0] |= val << 9;
3552 break;
3553 case '1':
3554 the_ins.opcode[1] |= val << 12;
3555 break;
3556 case '2':
3557 the_ins.opcode[1] |= val << 6;
3558 break;
3559 case '3':
3560 the_ins.opcode[1] |= val;
3561 break;
3562 case '4':
3563 the_ins.opcode[2] |= val << 12;
3564 break;
3565 case '5':
3566 the_ins.opcode[2] |= val << 6;
3567 break;
3568 case '6':
3569 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3570 three words long! */
3571 the_ins.numo++;
3572 the_ins.opcode[2] |= val;
3573 break;
3574 case '7':
3575 the_ins.opcode[1] |= val << 7;
3576 break;
3577 case '8':
3578 the_ins.opcode[1] |= val << 10;
3579 break;
3580 #ifndef NO_68851
3581 case '9':
3582 the_ins.opcode[1] |= val << 5;
3583 break;
3584 #endif
3585
3586 case 't':
3587 the_ins.opcode[1] |= (val << 10) | (val << 7);
3588 break;
3589 case 'D':
3590 the_ins.opcode[1] |= (val << 12) | val;
3591 break;
3592 case 'g':
3593 the_ins.opcode[0] |= val = 0xff;
3594 break;
3595 case 'i':
3596 the_ins.opcode[0] |= val << 9;
3597 break;
3598 case 'C':
3599 the_ins.opcode[1] |= val;
3600 break;
3601 case 'j':
3602 the_ins.opcode[1] |= val;
3603 the_ins.numo++; /* What a hack. */
3604 break;
3605 case 'k':
3606 the_ins.opcode[1] |= val << 4;
3607 break;
3608 case 'b':
3609 case 'w':
3610 case 'W':
3611 case 'l':
3612 break;
3613 case 'e':
3614 the_ins.opcode[0] |= (val << 6);
3615 break;
3616 case 'L':
3617 the_ins.opcode[1] = (val >> 16);
3618 the_ins.opcode[2] = val & 0xffff;
3619 break;
3620 case 'm':
3621 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3622 the_ins.opcode[0] |= ((val & 0x7) << 9);
3623 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3624 break;
3625 case 'n': /* MAC/EMAC Rx on !load. */
3626 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3627 the_ins.opcode[0] |= ((val & 0x7) << 9);
3628 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3629 break;
3630 case 'o': /* MAC/EMAC Rx on load. */
3631 the_ins.opcode[1] |= val << 12;
3632 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3633 break;
3634 case 'M': /* MAC/EMAC Ry on !load. */
3635 the_ins.opcode[0] |= (val & 0xF);
3636 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3637 break;
3638 case 'N': /* MAC/EMAC Ry on load. */
3639 the_ins.opcode[1] |= (val & 0xF);
3640 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3641 break;
3642 case 'h':
3643 the_ins.opcode[1] |= ((val != 1) << 10);
3644 break;
3645 case 'F':
3646 the_ins.opcode[0] |= ((val & 0x3) << 9);
3647 break;
3648 case 'f':
3649 the_ins.opcode[0] |= ((val & 0x3) << 0);
3650 break;
3651 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3652 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3653 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3654 break;
3655 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3656 the_ins.opcode[0] |= ((val & 0x1) << 7);
3657 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3658 break;
3659 case 'I':
3660 the_ins.opcode[1] |= ((val & 0x3) << 9);
3661 break;
3662 case ']':
3663 the_ins.opcode[0] |= (val & 0x1) <<10;
3664 break;
3665 case 'c':
3666 default:
3667 as_fatal (_("failed sanity check."));
3668 }
3669 }
3670
3671 static void
3672 install_gen_operand (int mode, int val)
3673 {
3674 switch (mode)
3675 {
3676 case '/': /* Special for mask loads for mac/msac insns with
3677 possible mask; trailing_ampersend set in bit 8. */
3678 the_ins.opcode[0] |= (val & 0x3f);
3679 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3680 break;
3681 case 's':
3682 the_ins.opcode[0] |= val;
3683 break;
3684 case 'd':
3685 /* This is a kludge!!! */
3686 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3687 break;
3688 case 'b':
3689 case 'w':
3690 case 'l':
3691 case 'f':
3692 case 'F':
3693 case 'x':
3694 case 'p':
3695 the_ins.opcode[0] |= val;
3696 break;
3697 /* more stuff goes here. */
3698 default:
3699 as_fatal (_("failed sanity check."));
3700 }
3701 }
3702
3703 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3704 then deal with the bitfield hack. */
3705
3706 static char *
3707 crack_operand (char *str, struct m68k_op *opP)
3708 {
3709 register int parens;
3710 register int c;
3711 register char *beg_str;
3712 int inquote = 0;
3713
3714 if (!str)
3715 {
3716 return str;
3717 }
3718 beg_str = str;
3719 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3720 {
3721 if (! inquote)
3722 {
3723 if (*str == '(')
3724 parens++;
3725 else if (*str == ')')
3726 {
3727 if (!parens)
3728 { /* ERROR. */
3729 opP->error = _("Extra )");
3730 return str;
3731 }
3732 --parens;
3733 }
3734 }
3735 if (flag_mri && *str == '\'')
3736 inquote = ! inquote;
3737 }
3738 if (!*str && parens)
3739 { /* ERROR. */
3740 opP->error = _("Missing )");
3741 return str;
3742 }
3743 c = *str;
3744 *str = '\0';
3745 if (m68k_ip_op (beg_str, opP) != 0)
3746 {
3747 *str = c;
3748 return str;
3749 }
3750 *str = c;
3751 if (c == '}')
3752 c = *++str; /* JF bitfield hack. */
3753 if (c)
3754 {
3755 c = *++str;
3756 if (!c)
3757 as_bad (_("Missing operand"));
3758 }
3759
3760 /* Detect MRI REG symbols and convert them to REGLSTs. */
3761 if (opP->mode == CONTROL && (int)opP->reg < 0)
3762 {
3763 opP->mode = REGLST;
3764 opP->mask = ~(int)opP->reg;
3765 opP->reg = 0;
3766 }
3767
3768 return str;
3769 }
3770
3771 /* This is the guts of the machine-dependent assembler. STR points to a
3772 machine dependent instruction. This function is supposed to emit
3773 the frags/bytes it assembles to.
3774 */
3775
3776 static void
3777 insert_reg (const char *regname, int regnum)
3778 {
3779 char buf[100];
3780 int i;
3781
3782 #ifdef REGISTER_PREFIX
3783 if (!flag_reg_prefix_optional)
3784 {
3785 buf[0] = REGISTER_PREFIX;
3786 strcpy (buf + 1, regname);
3787 regname = buf;
3788 }
3789 #endif
3790
3791 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3792 &zero_address_frag));
3793
3794 for (i = 0; regname[i]; i++)
3795 buf[i] = TOUPPER (regname[i]);
3796 buf[i] = '\0';
3797
3798 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3799 &zero_address_frag));
3800 }
3801
3802 struct init_entry
3803 {
3804 const char *name;
3805 int number;
3806 };
3807
3808 static const struct init_entry init_table[] =
3809 {
3810 { "d0", DATA0 },
3811 { "d1", DATA1 },
3812 { "d2", DATA2 },
3813 { "d3", DATA3 },
3814 { "d4", DATA4 },
3815 { "d5", DATA5 },
3816 { "d6", DATA6 },
3817 { "d7", DATA7 },
3818 { "a0", ADDR0 },
3819 { "a1", ADDR1 },
3820 { "a2", ADDR2 },
3821 { "a3", ADDR3 },
3822 { "a4", ADDR4 },
3823 { "a5", ADDR5 },
3824 { "a6", ADDR6 },
3825 { "fp", ADDR6 },
3826 { "a7", ADDR7 },
3827 { "sp", ADDR7 },
3828 { "ssp", ADDR7 },
3829 { "fp0", FP0 },
3830 { "fp1", FP1 },
3831 { "fp2", FP2 },
3832 { "fp3", FP3 },
3833 { "fp4", FP4 },
3834 { "fp5", FP5 },
3835 { "fp6", FP6 },
3836 { "fp7", FP7 },
3837 { "fpi", FPI },
3838 { "fpiar", FPI },
3839 { "fpc", FPI },
3840 { "fps", FPS },
3841 { "fpsr", FPS },
3842 { "fpc", FPC },
3843 { "fpcr", FPC },
3844 { "control", FPC },
3845 { "status", FPS },
3846 { "iaddr", FPI },
3847
3848 { "cop0", COP0 },
3849 { "cop1", COP1 },
3850 { "cop2", COP2 },
3851 { "cop3", COP3 },
3852 { "cop4", COP4 },
3853 { "cop5", COP5 },
3854 { "cop6", COP6 },
3855 { "cop7", COP7 },
3856 { "pc", PC },
3857 { "zpc", ZPC },
3858 { "sr", SR },
3859
3860 { "ccr", CCR },
3861 { "cc", CCR },
3862
3863 { "acc", ACC },
3864 { "acc0", ACC },
3865 { "acc1", ACC1 },
3866 { "acc2", ACC2 },
3867 { "acc3", ACC3 },
3868 { "accext01", ACCEXT01 },
3869 { "accext23", ACCEXT23 },
3870 { "macsr", MACSR },
3871 { "mask", MASK },
3872
3873 /* Control registers. */
3874 { "sfc", SFC }, /* Source Function Code. */
3875 { "sfcr", SFC },
3876 { "dfc", DFC }, /* Destination Function Code. */
3877 { "dfcr", DFC },
3878 { "cacr", CACR }, /* Cache Control Register. */
3879 { "caar", CAAR }, /* Cache Address Register. */
3880
3881 { "usp", USP }, /* User Stack Pointer. */
3882 { "vbr", VBR }, /* Vector Base Register. */
3883 { "msp", MSP }, /* Master Stack Pointer. */
3884 { "isp", ISP }, /* Interrupt Stack Pointer. */
3885
3886 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3887 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3888 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3889 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3890
3891 /* 68ec040 versions of same */
3892 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3893 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3894 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3895 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3896
3897 /* Coldfire versions of same. The ColdFire programmer's reference
3898 manual indicated that the order is 2,3,0,1, but Ken Rose
3899 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3900 { "acr0", ACR0 }, /* Access Control Unit 0. */
3901 { "acr1", ACR1 }, /* Access Control Unit 1. */
3902 { "acr2", ACR2 }, /* Access Control Unit 2. */
3903 { "acr3", ACR3 }, /* Access Control Unit 3. */
3904
3905 { "tc", TC }, /* MMU Translation Control Register. */
3906 { "tcr", TC },
3907 { "asid", ASID },
3908
3909 { "mmusr", MMUSR }, /* MMU Status Register. */
3910 { "srp", SRP }, /* User Root Pointer. */
3911 { "urp", URP }, /* Supervisor Root Pointer. */
3912
3913 { "buscr", BUSCR },
3914 { "mmubar", MMUBAR },
3915 { "pcr", PCR },
3916
3917 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3918 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3919 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3920 { "mbar", MBAR }, /* Module Base Address Register. */
3921
3922 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3923 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3924 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3925 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3926 { "mpcr", MPCR }, /* mcfv4e registers. */
3927 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3928 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3929 { "asid", TC }, /* mcfv4e registers. */
3930 { "mmubar", BUSCR }, /* mcfv4e registers. */
3931 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3932 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3933 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3934 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3935 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3936 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3937 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3938 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3939 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3940 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3941 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3942 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3943
3944 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3945 { "rambar", RAMBAR }, /* mcf528x registers. */
3946
3947 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3948
3949 { "cac", CAC }, /* fido registers. */
3950 { "mbb", MBB }, /* fido registers. */
3951 /* End of control registers. */
3952
3953 { "ac", AC },
3954 { "bc", BC },
3955 { "cal", CAL },
3956 { "crp", CRP },
3957 { "drp", DRP },
3958 { "pcsr", PCSR },
3959 { "psr", PSR },
3960 { "scc", SCC },
3961 { "val", VAL },
3962 { "bad0", BAD0 },
3963 { "bad1", BAD1 },
3964 { "bad2", BAD2 },
3965 { "bad3", BAD3 },
3966 { "bad4", BAD4 },
3967 { "bad5", BAD5 },
3968 { "bad6", BAD6 },
3969 { "bad7", BAD7 },
3970 { "bac0", BAC0 },
3971 { "bac1", BAC1 },
3972 { "bac2", BAC2 },
3973 { "bac3", BAC3 },
3974 { "bac4", BAC4 },
3975 { "bac5", BAC5 },
3976 { "bac6", BAC6 },
3977 { "bac7", BAC7 },
3978
3979 { "ic", IC },
3980 { "dc", DC },
3981 { "nc", NC },
3982
3983 { "tt0", TT0 },
3984 { "tt1", TT1 },
3985 /* 68ec030 versions of same. */
3986 { "ac0", TT0 },
3987 { "ac1", TT1 },
3988 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3989 { "acusr", PSR },
3990
3991 /* Suppressed data and address registers. */
3992 { "zd0", ZDATA0 },
3993 { "zd1", ZDATA1 },
3994 { "zd2", ZDATA2 },
3995 { "zd3", ZDATA3 },
3996 { "zd4", ZDATA4 },
3997 { "zd5", ZDATA5 },
3998 { "zd6", ZDATA6 },
3999 { "zd7", ZDATA7 },
4000 { "za0", ZADDR0 },
4001 { "za1", ZADDR1 },
4002 { "za2", ZADDR2 },
4003 { "za3", ZADDR3 },
4004 { "za4", ZADDR4 },
4005 { "za5", ZADDR5 },
4006 { "za6", ZADDR6 },
4007 { "za7", ZADDR7 },
4008
4009 /* Upper and lower data and address registers, used by macw and msacw. */
4010 { "d0l", DATA0L },
4011 { "d1l", DATA1L },
4012 { "d2l", DATA2L },
4013 { "d3l", DATA3L },
4014 { "d4l", DATA4L },
4015 { "d5l", DATA5L },
4016 { "d6l", DATA6L },
4017 { "d7l", DATA7L },
4018
4019 { "a0l", ADDR0L },
4020 { "a1l", ADDR1L },
4021 { "a2l", ADDR2L },
4022 { "a3l", ADDR3L },
4023 { "a4l", ADDR4L },
4024 { "a5l", ADDR5L },
4025 { "a6l", ADDR6L },
4026 { "a7l", ADDR7L },
4027
4028 { "d0u", DATA0U },
4029 { "d1u", DATA1U },
4030 { "d2u", DATA2U },
4031 { "d3u", DATA3U },
4032 { "d4u", DATA4U },
4033 { "d5u", DATA5U },
4034 { "d6u", DATA6U },
4035 { "d7u", DATA7U },
4036
4037 { "a0u", ADDR0U },
4038 { "a1u", ADDR1U },
4039 { "a2u", ADDR2U },
4040 { "a3u", ADDR3U },
4041 { "a4u", ADDR4U },
4042 { "a5u", ADDR5U },
4043 { "a6u", ADDR6U },
4044 { "a7u", ADDR7U },
4045
4046 { 0, 0 }
4047 };
4048
4049 static void
4050 init_regtable (void)
4051 {
4052 int i;
4053 for (i = 0; init_table[i].name; i++)
4054 insert_reg (init_table[i].name, init_table[i].number);
4055 }
4056
4057 void
4058 md_assemble (char *str)
4059 {
4060 const char *er;
4061 short *fromP;
4062 char *toP = NULL;
4063 int m, n = 0;
4064 char *to_beg_P;
4065 int shorts_this_frag;
4066 fixS *fixP;
4067
4068 if (!selected_cpu && !selected_arch)
4069 {
4070 /* We've not selected an architecture yet. Set the default
4071 now. We do this lazily so that an initial .cpu or .arch directive
4072 can specify. */
4073 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4074 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4075 }
4076 if (!initialized)
4077 m68k_init_arch ();
4078
4079 /* In MRI mode, the instruction and operands are separated by a
4080 space. Anything following the operands is a comment. The label
4081 has already been removed. */
4082 if (flag_mri)
4083 {
4084 char *s;
4085 int fields = 0;
4086 int infield = 0;
4087 int inquote = 0;
4088
4089 for (s = str; *s != '\0'; s++)
4090 {
4091 if ((*s == ' ' || *s == '\t') && ! inquote)
4092 {
4093 if (infield)
4094 {
4095 ++fields;
4096 if (fields >= 2)
4097 {
4098 *s = '\0';
4099 break;
4100 }
4101 infield = 0;
4102 }
4103 }
4104 else
4105 {
4106 if (! infield)
4107 infield = 1;
4108 if (*s == '\'')
4109 inquote = ! inquote;
4110 }
4111 }
4112 }
4113
4114 memset (&the_ins, '\0', sizeof (the_ins));
4115 m68k_ip (str);
4116 er = the_ins.error;
4117 if (!er)
4118 {
4119 for (n = 0; n < the_ins.numargs; n++)
4120 if (the_ins.operands[n].error)
4121 {
4122 er = the_ins.operands[n].error;
4123 break;
4124 }
4125 }
4126 if (er)
4127 {
4128 as_bad (_("%s -- statement `%s' ignored"), er, str);
4129 return;
4130 }
4131
4132 /* If there is a current label, record that it marks an instruction. */
4133 if (current_label != NULL)
4134 {
4135 current_label->text = 1;
4136 current_label = NULL;
4137 }
4138
4139 #ifdef OBJ_ELF
4140 /* Tie dwarf2 debug info to the address at the start of the insn. */
4141 dwarf2_emit_insn (0);
4142 #endif
4143
4144 if (the_ins.nfrag == 0)
4145 {
4146 /* No frag hacking involved; just put it out. */
4147 toP = frag_more (2 * the_ins.numo);
4148 fromP = &the_ins.opcode[0];
4149 for (m = the_ins.numo; m; --m)
4150 {
4151 md_number_to_chars (toP, (long) (*fromP), 2);
4152 toP += 2;
4153 fromP++;
4154 }
4155 /* Put out symbol-dependent info. */
4156 for (m = 0; m < the_ins.nrel; m++)
4157 {
4158 switch (the_ins.reloc[m].wid)
4159 {
4160 case 'B':
4161 n = 1;
4162 break;
4163 case 'b':
4164 n = 1;
4165 break;
4166 case '3':
4167 n = 1;
4168 break;
4169 case 'w':
4170 case 'W':
4171 n = 2;
4172 break;
4173 case 'l':
4174 n = 4;
4175 break;
4176 default:
4177 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4178 the_ins.reloc[m].wid);
4179 }
4180
4181 fixP = fix_new_exp (frag_now,
4182 ((toP - frag_now->fr_literal)
4183 - the_ins.numo * 2 + the_ins.reloc[m].n),
4184 n,
4185 &the_ins.reloc[m].exp,
4186 the_ins.reloc[m].pcrel,
4187 get_reloc_code (n, the_ins.reloc[m].pcrel,
4188 the_ins.reloc[m].pic_reloc));
4189 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4190 if (the_ins.reloc[m].wid == 'B')
4191 fixP->fx_signed = 1;
4192 }
4193 return;
4194 }
4195
4196 /* There's some frag hacking. */
4197 {
4198 /* Calculate the max frag size. */
4199 int wid;
4200
4201 wid = 2 * the_ins.fragb[0].fragoff;
4202 for (n = 1; n < the_ins.nfrag; n++)
4203 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4204 /* frag_var part. */
4205 wid += 10;
4206 /* Make sure the whole insn fits in one chunk, in particular that
4207 the var part is attached, as we access one byte before the
4208 variable frag for byte branches. */
4209 frag_grow (wid);
4210 }
4211
4212 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4213 {
4214 int wid;
4215
4216 if (n == 0)
4217 wid = 2 * the_ins.fragb[n].fragoff;
4218 else
4219 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4220 toP = frag_more (wid);
4221 to_beg_P = toP;
4222 shorts_this_frag = 0;
4223 for (m = wid / 2; m; --m)
4224 {
4225 md_number_to_chars (toP, (long) (*fromP), 2);
4226 toP += 2;
4227 fromP++;
4228 shorts_this_frag++;
4229 }
4230 for (m = 0; m < the_ins.nrel; m++)
4231 {
4232 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4233 {
4234 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4235 break;
4236 }
4237 wid = the_ins.reloc[m].wid;
4238 if (wid == 0)
4239 continue;
4240 the_ins.reloc[m].wid = 0;
4241 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4242
4243 fixP = fix_new_exp (frag_now,
4244 ((toP - frag_now->fr_literal)
4245 - the_ins.numo * 2 + the_ins.reloc[m].n),
4246 wid,
4247 &the_ins.reloc[m].exp,
4248 the_ins.reloc[m].pcrel,
4249 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4250 the_ins.reloc[m].pic_reloc));
4251 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4252 }
4253 (void) frag_var (rs_machine_dependent, 10, 0,
4254 (relax_substateT) (the_ins.fragb[n].fragty),
4255 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4256 }
4257 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4258 shorts_this_frag = 0;
4259 if (n)
4260 {
4261 toP = frag_more (n * 2);
4262 while (n--)
4263 {
4264 md_number_to_chars (toP, (long) (*fromP), 2);
4265 toP += 2;
4266 fromP++;
4267 shorts_this_frag++;
4268 }
4269 }
4270 for (m = 0; m < the_ins.nrel; m++)
4271 {
4272 int wid;
4273
4274 wid = the_ins.reloc[m].wid;
4275 if (wid == 0)
4276 continue;
4277 the_ins.reloc[m].wid = 0;
4278 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4279
4280 fixP = fix_new_exp (frag_now,
4281 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4282 - shorts_this_frag * 2),
4283 wid,
4284 &the_ins.reloc[m].exp,
4285 the_ins.reloc[m].pcrel,
4286 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4287 the_ins.reloc[m].pic_reloc));
4288 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4289 }
4290 }
4291
4292 /* Comparison function used by qsort to rank the opcode entries by name. */
4293
4294 static int
4295 m68k_compare_opcode (const void * v1, const void * v2)
4296 {
4297 struct m68k_opcode * op1, * op2;
4298 int ret;
4299
4300 if (v1 == v2)
4301 return 0;
4302
4303 op1 = *(struct m68k_opcode **) v1;
4304 op2 = *(struct m68k_opcode **) v2;
4305
4306 /* Compare the two names. If different, return the comparison.
4307 If the same, return the order they are in the opcode table. */
4308 ret = strcmp (op1->name, op2->name);
4309 if (ret)
4310 return ret;
4311 if (op1 < op2)
4312 return -1;
4313 return 1;
4314 }
4315
4316 void
4317 md_begin (void)
4318 {
4319 const struct m68k_opcode *ins;
4320 struct m68k_incant *hack, *slak;
4321 const char *retval = 0; /* Empty string, or error msg text. */
4322 int i;
4323
4324 /* Set up hash tables with 68000 instructions.
4325 similar to what the vax assembler does. */
4326 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4327 a copy of it at runtime, adding in the information we want but isn't
4328 there. I think it'd be better to have an awk script hack the table
4329 at compile time. Or even just xstr the table and use it as-is. But
4330 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4331 names. */
4332
4333 if (flag_mri)
4334 {
4335 flag_reg_prefix_optional = 1;
4336 m68k_abspcadd = 1;
4337 if (! m68k_rel32_from_cmdline)
4338 m68k_rel32 = 0;
4339 }
4340
4341 /* First sort the opcode table into alphabetical order to seperate
4342 the order that the assembler wants to see the opcodes from the
4343 order that the disassembler wants to see them. */
4344 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4345 if (!m68k_sorted_opcodes)
4346 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4347 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4348
4349 for (i = m68k_numopcodes; i--;)
4350 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4351
4352 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4353 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4354
4355 op_hash = hash_new ();
4356
4357 obstack_begin (&robyn, 4000);
4358 for (i = 0; i < m68k_numopcodes; i++)
4359 {
4360 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4361 do
4362 {
4363 ins = m68k_sorted_opcodes[i];
4364
4365 /* We *could* ignore insns that don't match our
4366 arch here by just leaving them out of the hash. */
4367 slak->m_operands = ins->args;
4368 slak->m_opnum = strlen (slak->m_operands) / 2;
4369 slak->m_arch = ins->arch;
4370 slak->m_opcode = ins->opcode;
4371 /* This is kludgey. */
4372 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4373 if (i + 1 != m68k_numopcodes
4374 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4375 {
4376 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4377 i++;
4378 }
4379 else
4380 slak->m_next = 0;
4381 slak = slak->m_next;
4382 }
4383 while (slak);
4384
4385 retval = hash_insert (op_hash, ins->name, (char *) hack);
4386 if (retval)
4387 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4388 }
4389
4390 for (i = 0; i < m68k_numaliases; i++)
4391 {
4392 const char *name = m68k_opcode_aliases[i].primary;
4393 const char *alias = m68k_opcode_aliases[i].alias;
4394 PTR val = hash_find (op_hash, name);
4395
4396 if (!val)
4397 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4398 retval = hash_insert (op_hash, alias, val);
4399 if (retval)
4400 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4401 }
4402
4403 /* In MRI mode, all unsized branches are variable sized. Normally,
4404 they are word sized. */
4405 if (flag_mri)
4406 {
4407 static struct m68k_opcode_alias mri_aliases[] =
4408 {
4409 { "bhi", "jhi", },
4410 { "bls", "jls", },
4411 { "bcc", "jcc", },
4412 { "bcs", "jcs", },
4413 { "bne", "jne", },
4414 { "beq", "jeq", },
4415 { "bvc", "jvc", },
4416 { "bvs", "jvs", },
4417 { "bpl", "jpl", },
4418 { "bmi", "jmi", },
4419 { "bge", "jge", },
4420 { "blt", "jlt", },
4421 { "bgt", "jgt", },
4422 { "ble", "jle", },
4423 { "bra", "jra", },
4424 { "bsr", "jbsr", },
4425 };
4426
4427 for (i = 0;
4428 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4429 i++)
4430 {
4431 const char *name = mri_aliases[i].primary;
4432 const char *alias = mri_aliases[i].alias;
4433 PTR val = hash_find (op_hash, name);
4434
4435 if (!val)
4436 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4437 retval = hash_jam (op_hash, alias, val);
4438 if (retval)
4439 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4440 }
4441 }
4442
4443 for (i = 0; i < (int) sizeof (notend_table); i++)
4444 {
4445 notend_table[i] = 0;
4446 alt_notend_table[i] = 0;
4447 }
4448
4449 notend_table[','] = 1;
4450 notend_table['{'] = 1;
4451 notend_table['}'] = 1;
4452 alt_notend_table['a'] = 1;
4453 alt_notend_table['A'] = 1;
4454 alt_notend_table['d'] = 1;
4455 alt_notend_table['D'] = 1;
4456 alt_notend_table['#'] = 1;
4457 alt_notend_table['&'] = 1;
4458 alt_notend_table['f'] = 1;
4459 alt_notend_table['F'] = 1;
4460 #ifdef REGISTER_PREFIX
4461 alt_notend_table[REGISTER_PREFIX] = 1;
4462 #endif
4463
4464 /* We need to put '(' in alt_notend_table to handle
4465 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4466 alt_notend_table['('] = 1;
4467
4468 /* We need to put '@' in alt_notend_table to handle
4469 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4470 alt_notend_table['@'] = 1;
4471
4472 /* We need to put digits in alt_notend_table to handle
4473 bfextu %d0{24:1},%d0 */
4474 alt_notend_table['0'] = 1;
4475 alt_notend_table['1'] = 1;
4476 alt_notend_table['2'] = 1;
4477 alt_notend_table['3'] = 1;
4478 alt_notend_table['4'] = 1;
4479 alt_notend_table['5'] = 1;
4480 alt_notend_table['6'] = 1;
4481 alt_notend_table['7'] = 1;
4482 alt_notend_table['8'] = 1;
4483 alt_notend_table['9'] = 1;
4484
4485 #ifndef MIT_SYNTAX_ONLY
4486 /* Insert pseudo ops, these have to go into the opcode table since
4487 gas expects pseudo ops to start with a dot. */
4488 {
4489 int n = 0;
4490
4491 while (mote_pseudo_table[n].poc_name)
4492 {
4493 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4494 hash_insert (op_hash,
4495 mote_pseudo_table[n].poc_name, (char *) hack);
4496 hack->m_operands = 0;
4497 hack->m_opnum = n;
4498 n++;
4499 }
4500 }
4501 #endif
4502
4503 init_regtable ();
4504
4505 #ifdef OBJ_ELF
4506 record_alignment (text_section, 2);
4507 record_alignment (data_section, 2);
4508 record_alignment (bss_section, 2);
4509 #endif
4510 }
4511
4512 \f
4513 /* This is called when a label is defined. */
4514
4515 void
4516 m68k_frob_label (symbolS *sym)
4517 {
4518 struct label_line *n;
4519
4520 n = (struct label_line *) xmalloc (sizeof *n);
4521 n->next = labels;
4522 n->label = sym;
4523 as_where (&n->file, &n->line);
4524 n->text = 0;
4525 labels = n;
4526 current_label = n;
4527
4528 #ifdef OBJ_ELF
4529 dwarf2_emit_label (sym);
4530 #endif
4531 }
4532
4533 /* This is called when a value that is not an instruction is emitted. */
4534
4535 void
4536 m68k_flush_pending_output (void)
4537 {
4538 current_label = NULL;
4539 }
4540
4541 /* This is called at the end of the assembly, when the final value of
4542 the label is known. We warn if this is a text symbol aligned at an
4543 odd location. */
4544
4545 void
4546 m68k_frob_symbol (symbolS *sym)
4547 {
4548 if (S_GET_SEGMENT (sym) == reg_section
4549 && (int) S_GET_VALUE (sym) < 0)
4550 {
4551 S_SET_SEGMENT (sym, absolute_section);
4552 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4553 }
4554 else if ((S_GET_VALUE (sym) & 1) != 0)
4555 {
4556 struct label_line *l;
4557
4558 for (l = labels; l != NULL; l = l->next)
4559 {
4560 if (l->label == sym)
4561 {
4562 if (l->text)
4563 as_warn_where (l->file, l->line,
4564 _("text label `%s' aligned to odd boundary"),
4565 S_GET_NAME (sym));
4566 break;
4567 }
4568 }
4569 }
4570 }
4571 \f
4572 /* This is called if we go in or out of MRI mode because of the .mri
4573 pseudo-op. */
4574
4575 void
4576 m68k_mri_mode_change (int on)
4577 {
4578 if (on)
4579 {
4580 if (! flag_reg_prefix_optional)
4581 {
4582 flag_reg_prefix_optional = 1;
4583 #ifdef REGISTER_PREFIX
4584 init_regtable ();
4585 #endif
4586 }
4587 m68k_abspcadd = 1;
4588 if (! m68k_rel32_from_cmdline)
4589 m68k_rel32 = 0;
4590 }
4591 else
4592 {
4593 if (! reg_prefix_optional_seen)
4594 {
4595 #ifdef REGISTER_PREFIX_OPTIONAL
4596 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4597 #else
4598 flag_reg_prefix_optional = 0;
4599 #endif
4600 #ifdef REGISTER_PREFIX
4601 init_regtable ();
4602 #endif
4603 }
4604 m68k_abspcadd = 0;
4605 if (! m68k_rel32_from_cmdline)
4606 m68k_rel32 = 1;
4607 }
4608 }
4609
4610 /* Equal to MAX_PRECISION in atof-ieee.c. */
4611 #define MAX_LITTLENUMS 6
4612
4613 /* Turn a string in input_line_pointer into a floating point constant
4614 of type TYPE, and store the appropriate bytes in *LITP. The number
4615 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4616 returned, or NULL on OK. */
4617
4618 char *
4619 md_atof (int type, char *litP, int *sizeP)
4620 {
4621 int prec;
4622 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4623 LITTLENUM_TYPE *wordP;
4624 char *t;
4625
4626 switch (type)
4627 {
4628 case 'f':
4629 case 'F':
4630 case 's':
4631 case 'S':
4632 prec = 2;
4633 break;
4634
4635 case 'd':
4636 case 'D':
4637 case 'r':
4638 case 'R':
4639 prec = 4;
4640 break;
4641
4642 case 'x':
4643 case 'X':
4644 prec = 6;
4645 break;
4646
4647 case 'p':
4648 case 'P':
4649 prec = 6;
4650 break;
4651
4652 default:
4653 *sizeP = 0;
4654 return _("Bad call to MD_ATOF()");
4655 }
4656 t = atof_ieee (input_line_pointer, type, words);
4657 if (t)
4658 input_line_pointer = t;
4659
4660 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4661 for (wordP = words; prec--;)
4662 {
4663 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4664 litP += sizeof (LITTLENUM_TYPE);
4665 }
4666 return 0;
4667 }
4668
4669 void
4670 md_number_to_chars (char *buf, valueT val, int n)
4671 {
4672 number_to_chars_bigendian (buf, val, n);
4673 }
4674
4675 void
4676 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4677 {
4678 offsetT val = *valP;
4679 addressT upper_limit;
4680 offsetT lower_limit;
4681
4682 /* This is unnecessary but it convinces the native rs6000 compiler
4683 to generate the code we want. */
4684 char *buf = fixP->fx_frag->fr_literal;
4685 buf += fixP->fx_where;
4686 /* End ibm compiler workaround. */
4687
4688 val = SEXT (val);
4689
4690 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4691 fixP->fx_done = 1;
4692
4693 #ifdef OBJ_ELF
4694 if (fixP->fx_addsy)
4695 {
4696 memset (buf, 0, fixP->fx_size);
4697 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4698
4699 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4700 && !S_IS_DEFINED (fixP->fx_addsy)
4701 && !S_IS_WEAK (fixP->fx_addsy))
4702 S_SET_WEAK (fixP->fx_addsy);
4703 return;
4704 }
4705 #elif defined(OBJ_AOUT)
4706 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4707 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4708 {
4709 memset (buf, 0, fixP->fx_size);
4710 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4711 return;
4712 }
4713 #endif
4714
4715 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4716 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4717 return;
4718
4719 switch (fixP->fx_size)
4720 {
4721 /* The cast to offsetT below are necessary to make code
4722 correct for machines where ints are smaller than offsetT. */
4723 case 1:
4724 *buf++ = val;
4725 upper_limit = 0x7f;
4726 lower_limit = - (offsetT) 0x80;
4727 break;
4728 case 2:
4729 *buf++ = (val >> 8);
4730 *buf++ = val;
4731 upper_limit = 0x7fff;
4732 lower_limit = - (offsetT) 0x8000;
4733 break;
4734 case 4:
4735 *buf++ = (val >> 24);
4736 *buf++ = (val >> 16);
4737 *buf++ = (val >> 8);
4738 *buf++ = val;
4739 upper_limit = 0x7fffffff;
4740 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4741 break;
4742 default:
4743 BAD_CASE (fixP->fx_size);
4744 }
4745
4746 /* Fix up a negative reloc. */
4747 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4748 {
4749 fixP->fx_addsy = fixP->fx_subsy;
4750 fixP->fx_subsy = NULL;
4751 fixP->fx_tcbit = 1;
4752 }
4753
4754 /* For non-pc-relative values, it's conceivable we might get something
4755 like "0xff" for a byte field. So extend the upper part of the range
4756 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4757 so that we can do any range checking at all. */
4758 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4759 upper_limit = upper_limit * 2 + 1;
4760
4761 if ((addressT) val > upper_limit
4762 && (val > 0 || val < lower_limit))
4763 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4764
4765 /* A one byte PC-relative reloc means a short branch. We can't use
4766 a short branch with a value of 0 or -1, because those indicate
4767 different opcodes (branches with longer offsets). fixup_segment
4768 in write.c may have clobbered fx_pcrel, so we need to examine the
4769 reloc type. */
4770 if ((fixP->fx_pcrel
4771 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4772 && fixP->fx_size == 1
4773 && (fixP->fx_addsy == NULL
4774 || S_IS_DEFINED (fixP->fx_addsy))
4775 && (val == 0 || val == -1))
4776 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4777 }
4778
4779 /* *fragP has been relaxed to its final size, and now needs to have
4780 the bytes inside it modified to conform to the new size There is UGLY
4781 MAGIC here. ..
4782 */
4783 static void
4784 md_convert_frag_1 (fragS *fragP)
4785 {
4786 long disp;
4787 fixS *fixP;
4788
4789 /* Address in object code of the displacement. */
4790 register int object_address = fragP->fr_fix + fragP->fr_address;
4791
4792 /* Address in gas core of the place to store the displacement. */
4793 /* This convinces the native rs6000 compiler to generate the code we
4794 want. */
4795 register char *buffer_address = fragP->fr_literal;
4796 buffer_address += fragP->fr_fix;
4797 /* End ibm compiler workaround. */
4798
4799 /* The displacement of the address, from current location. */
4800 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4801 disp = (disp + fragP->fr_offset) - object_address;
4802
4803 switch (fragP->fr_subtype)
4804 {
4805 case TAB (BRANCHBWL, BYTE):
4806 case TAB (BRABSJUNC, BYTE):
4807 case TAB (BRABSJCOND, BYTE):
4808 case TAB (BRANCHBW, BYTE):
4809 know (issbyte (disp));
4810 if (disp == 0)
4811 as_bad_where (fragP->fr_file, fragP->fr_line,
4812 _("short branch with zero offset: use :w"));
4813 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4814 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4815 fixP->fx_pcrel_adjust = -1;
4816 break;
4817 case TAB (BRANCHBWL, SHORT):
4818 case TAB (BRABSJUNC, SHORT):
4819 case TAB (BRABSJCOND, SHORT):
4820 case TAB (BRANCHBW, SHORT):
4821 fragP->fr_opcode[1] = 0x00;
4822 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4823 1, RELAX_RELOC_PC16);
4824 fragP->fr_fix += 2;
4825 break;
4826 case TAB (BRANCHBWL, LONG):
4827 fragP->fr_opcode[1] = (char) 0xFF;
4828 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4829 1, RELAX_RELOC_PC32);
4830 fragP->fr_fix += 4;
4831 break;
4832 case TAB (BRABSJUNC, LONG):
4833 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4834 {
4835 if (flag_keep_pcrel)
4836 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4837 fragP->fr_opcode[0] = 0x4E;
4838 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4839 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4840 0, RELAX_RELOC_ABS32);
4841 fragP->fr_fix += 4;
4842 }
4843 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4844 {
4845 if (flag_keep_pcrel)
4846 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4847 fragP->fr_opcode[0] = 0x4E;
4848 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4849 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4850 0, RELAX_RELOC_ABS32);
4851 fragP->fr_fix += 4;
4852 }
4853 else
4854 {
4855 /* This cannot happen, because jbsr and jbra are the only two
4856 unconditional branches. */
4857 abort ();
4858 }
4859 break;
4860 case TAB (BRABSJCOND, LONG):
4861 if (flag_keep_pcrel)
4862 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4863
4864 /* Only Bcc 68000 instructions can come here
4865 Change bcc into b!cc/jmp absl long. */
4866 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4867 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4868
4869 /* JF: these used to be fr_opcode[2,3], but they may be in a
4870 different frag, in which case referring to them is a no-no.
4871 Only fr_opcode[0,1] are guaranteed to work. */
4872 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4873 *buffer_address++ = (char) 0xf9;
4874 fragP->fr_fix += 2; /* Account for jmp instruction. */
4875 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4876 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4877 fragP->fr_fix += 4;
4878 break;
4879 case TAB (FBRANCH, SHORT):
4880 know ((fragP->fr_opcode[1] & 0x40) == 0);
4881 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4882 1, RELAX_RELOC_PC16);
4883 fragP->fr_fix += 2;
4884 break;
4885 case TAB (FBRANCH, LONG):
4886 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4887 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4888 1, RELAX_RELOC_PC32);
4889 fragP->fr_fix += 4;
4890 break;
4891 case TAB (DBCCLBR, SHORT):
4892 case TAB (DBCCABSJ, SHORT):
4893 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4894 1, RELAX_RELOC_PC16);
4895 fragP->fr_fix += 2;
4896 break;
4897 case TAB (DBCCLBR, LONG):
4898 /* Only DBcc instructions can come here.
4899 Change dbcc into dbcc/bral.
4900 JF: these used to be fr_opcode[2-7], but that's wrong. */
4901 if (flag_keep_pcrel)
4902 as_fatal (_("Tried to convert DBcc to absolute jump"));
4903
4904 *buffer_address++ = 0x00; /* Branch offset = 4. */
4905 *buffer_address++ = 0x04;
4906 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4907 *buffer_address++ = 0x06;
4908 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4909 *buffer_address++ = (char) 0xff;
4910
4911 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4912 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4913 RELAX_RELOC_PC32);
4914 fragP->fr_fix += 4;
4915 break;
4916 case TAB (DBCCABSJ, LONG):
4917 /* Only DBcc instructions can come here.
4918 Change dbcc into dbcc/jmp.
4919 JF: these used to be fr_opcode[2-7], but that's wrong. */
4920 if (flag_keep_pcrel)
4921 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4922
4923 *buffer_address++ = 0x00; /* Branch offset = 4. */
4924 *buffer_address++ = 0x04;
4925 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4926 *buffer_address++ = 0x06;
4927 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4928 *buffer_address++ = (char) 0xf9;
4929
4930 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4931 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4932 RELAX_RELOC_ABS32);
4933 fragP->fr_fix += 4;
4934 break;
4935 case TAB (PCREL1632, SHORT):
4936 fragP->fr_opcode[1] &= ~0x3F;
4937 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4938 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4939 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4940 fragP->fr_fix += 2;
4941 break;
4942 case TAB (PCREL1632, LONG):
4943 /* Already set to mode 7.3; this indicates: PC indirect with
4944 suppressed index, 32-bit displacement. */
4945 *buffer_address++ = 0x01;
4946 *buffer_address++ = 0x70;
4947 fragP->fr_fix += 2;
4948 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4949 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4950 fixP->fx_pcrel_adjust = 2;
4951 fragP->fr_fix += 4;
4952 break;
4953 case TAB (PCINDEX, BYTE):
4954 assert (fragP->fr_fix >= 2);
4955 buffer_address[-2] &= ~1;
4956 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4957 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4958 fixP->fx_pcrel_adjust = 1;
4959 break;
4960 case TAB (PCINDEX, SHORT):
4961 assert (fragP->fr_fix >= 2);
4962 buffer_address[-2] |= 0x1;
4963 buffer_address[-1] = 0x20;
4964 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4965 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4966 fixP->fx_pcrel_adjust = 2;
4967 fragP->fr_fix += 2;
4968 break;
4969 case TAB (PCINDEX, LONG):
4970 assert (fragP->fr_fix >= 2);
4971 buffer_address[-2] |= 0x1;
4972 buffer_address[-1] = 0x30;
4973 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4974 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4975 fixP->fx_pcrel_adjust = 2;
4976 fragP->fr_fix += 4;
4977 break;
4978 case TAB (ABSTOPCREL, SHORT):
4979 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4980 1, RELAX_RELOC_PC16);
4981 fragP->fr_fix += 2;
4982 break;
4983 case TAB (ABSTOPCREL, LONG):
4984 if (flag_keep_pcrel)
4985 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4986 /* The thing to do here is force it to ABSOLUTE LONG, since
4987 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4988 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4989 abort ();
4990 fragP->fr_opcode[1] &= ~0x3F;
4991 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4992 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4993 0, RELAX_RELOC_ABS32);
4994 fragP->fr_fix += 4;
4995 break;
4996 }
4997 }
4998
4999 void
5000 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5001 segT sec ATTRIBUTE_UNUSED,
5002 fragS *fragP)
5003 {
5004 md_convert_frag_1 (fragP);
5005 }
5006
5007 /* Force truly undefined symbols to their maximum size, and generally set up
5008 the frag list to be relaxed
5009 */
5010 int
5011 md_estimate_size_before_relax (fragS *fragP, segT segment)
5012 {
5013 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5014 switch (fragP->fr_subtype)
5015 {
5016 case TAB (BRANCHBWL, SZ_UNDEF):
5017 case TAB (BRABSJUNC, SZ_UNDEF):
5018 case TAB (BRABSJCOND, SZ_UNDEF):
5019 {
5020 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5021 && relaxable_symbol (fragP->fr_symbol))
5022 {
5023 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5024 }
5025 else if (flag_short_refs)
5026 {
5027 /* Symbol is undefined and we want short ref. */
5028 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5029 }
5030 else
5031 {
5032 /* Symbol is still undefined. Make it LONG. */
5033 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5034 }
5035 break;
5036 }
5037
5038 case TAB (BRANCHBW, SZ_UNDEF):
5039 {
5040 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5041 && relaxable_symbol (fragP->fr_symbol))
5042 {
5043 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5044 }
5045 else
5046 {
5047 /* Symbol is undefined and we don't have long branches. */
5048 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5049 }
5050 break;
5051 }
5052
5053 case TAB (FBRANCH, SZ_UNDEF):
5054 case TAB (DBCCLBR, SZ_UNDEF):
5055 case TAB (DBCCABSJ, SZ_UNDEF):
5056 case TAB (PCREL1632, SZ_UNDEF):
5057 {
5058 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5059 && relaxable_symbol (fragP->fr_symbol))
5060 || flag_short_refs)
5061 {
5062 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5063 }
5064 else
5065 {
5066 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5067 }
5068 break;
5069 }
5070
5071 case TAB (PCINDEX, SZ_UNDEF):
5072 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5073 && relaxable_symbol (fragP->fr_symbol)))
5074 {
5075 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5076 }
5077 else
5078 {
5079 fragP->fr_subtype = TAB (PCINDEX, LONG);
5080 }
5081 break;
5082
5083 case TAB (ABSTOPCREL, SZ_UNDEF):
5084 {
5085 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5086 && relaxable_symbol (fragP->fr_symbol)))
5087 {
5088 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5089 }
5090 else
5091 {
5092 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5093 }
5094 break;
5095 }
5096
5097 default:
5098 break;
5099 }
5100
5101 /* Now that SZ_UNDEF are taken care of, check others. */
5102 switch (fragP->fr_subtype)
5103 {
5104 case TAB (BRANCHBWL, BYTE):
5105 case TAB (BRABSJUNC, BYTE):
5106 case TAB (BRABSJCOND, BYTE):
5107 case TAB (BRANCHBW, BYTE):
5108 /* We can't do a short jump to the next instruction, so in that
5109 case we force word mode. If the symbol is at the start of a
5110 frag, and it is the next frag with any data in it (usually
5111 this is just the next frag, but assembler listings may
5112 introduce empty frags), we must use word mode. */
5113 if (fragP->fr_symbol)
5114 {
5115 fragS *sym_frag;
5116
5117 sym_frag = symbol_get_frag (fragP->fr_symbol);
5118 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5119 {
5120 fragS *l;
5121
5122 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5123 if (l->fr_fix != 0)
5124 break;
5125 if (l == sym_frag)
5126 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5127 }
5128 }
5129 break;
5130 default:
5131 break;
5132 }
5133 return md_relax_table[fragP->fr_subtype].rlx_length;
5134 }
5135
5136 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5137 /* the bit-field entries in the relocation_info struct plays hell
5138 with the byte-order problems of cross-assembly. So as a hack,
5139 I added this mach. dependent ri twiddler. Ugly, but it gets
5140 you there. -KWK */
5141 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5142 are symbolnum, most sig. byte first. Last byte is broken up with
5143 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5144 nibble as nuthin. (on Sun 3 at least) */
5145 /* Translate the internal relocation information into target-specific
5146 format. */
5147 #ifdef comment
5148 void
5149 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5150 {
5151 /* This is easy. */
5152 md_number_to_chars (the_bytes, ri->r_address, 4);
5153 /* Now the fun stuff. */
5154 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5155 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5156 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5157 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5158 | ((ri->r_length << 5) & 0x60)
5159 | ((ri->r_extern << 4) & 0x10));
5160 }
5161
5162 #endif
5163
5164 #endif /* OBJ_AOUT or OBJ_BOUT */
5165
5166 #ifndef WORKING_DOT_WORD
5167 int md_short_jump_size = 4;
5168 int md_long_jump_size = 6;
5169
5170 void
5171 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5172 fragS *frag ATTRIBUTE_UNUSED,
5173 symbolS *to_symbol ATTRIBUTE_UNUSED)
5174 {
5175 valueT offset;
5176
5177 offset = to_addr - (from_addr + 2);
5178
5179 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5180 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5181 }
5182
5183 void
5184 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5185 fragS *frag, symbolS *to_symbol)
5186 {
5187 valueT offset;
5188
5189 if (!HAVE_LONG_BRANCH (current_architecture))
5190 {
5191 if (flag_keep_pcrel)
5192 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5193 offset = to_addr - S_GET_VALUE (to_symbol);
5194 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5195 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5196 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5197 0, NO_RELOC);
5198 }
5199 else
5200 {
5201 offset = to_addr - (from_addr + 2);
5202 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5203 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5204 }
5205 }
5206
5207 #endif
5208
5209 /* Different values of OK tell what its OK to return. Things that
5210 aren't OK are an error (what a shock, no?)
5211
5212 0: Everything is OK
5213 10: Absolute 1:8 only
5214 20: Absolute 0:7 only
5215 30: absolute 0:15 only
5216 40: Absolute 0:31 only
5217 50: absolute 0:127 only
5218 55: absolute -64:63 only
5219 60: absolute -128:127 only
5220 70: absolute 0:4095 only
5221 80: absolute -1, 1:7 only
5222 90: No bignums. */
5223
5224 static int
5225 get_num (struct m68k_exp *exp, int ok)
5226 {
5227 if (exp->exp.X_op == O_absent)
5228 {
5229 /* Do the same thing the VAX asm does. */
5230 op (exp) = O_constant;
5231 adds (exp) = 0;
5232 subs (exp) = 0;
5233 offs (exp) = 0;
5234 if (ok == 10)
5235 {
5236 as_warn (_("expression out of range: defaulting to 1"));
5237 offs (exp) = 1;
5238 }
5239 }
5240 else if (exp->exp.X_op == O_constant)
5241 {
5242 switch (ok)
5243 {
5244 case 10:
5245 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5246 {
5247 as_warn (_("expression out of range: defaulting to 1"));
5248 offs (exp) = 1;
5249 }
5250 break;
5251 case 20:
5252 if ((valueT) TRUNC (offs (exp)) > 7)
5253 goto outrange;
5254 break;
5255 case 30:
5256 if ((valueT) TRUNC (offs (exp)) > 15)
5257 goto outrange;
5258 break;
5259 case 40:
5260 if ((valueT) TRUNC (offs (exp)) > 32)
5261 goto outrange;
5262 break;
5263 case 50:
5264 if ((valueT) TRUNC (offs (exp)) > 127)
5265 goto outrange;
5266 break;
5267 case 55:
5268 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5269 goto outrange;
5270 break;
5271 case 60:
5272 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5273 goto outrange;
5274 break;
5275 case 70:
5276 if ((valueT) TRUNC (offs (exp)) > 4095)
5277 {
5278 outrange:
5279 as_warn (_("expression out of range: defaulting to 0"));
5280 offs (exp) = 0;
5281 }
5282 break;
5283 case 80:
5284 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5285 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5286 {
5287 as_warn (_("expression out of range: defaulting to 1"));
5288 offs (exp) = 1;
5289 }
5290 break;
5291 default:
5292 break;
5293 }
5294 }
5295 else if (exp->exp.X_op == O_big)
5296 {
5297 if (offs (exp) <= 0 /* flonum. */
5298 && (ok == 90 /* no bignums */
5299 || (ok > 10 /* Small-int ranges including 0 ok. */
5300 /* If we have a flonum zero, a zero integer should
5301 do as well (e.g., in moveq). */
5302 && generic_floating_point_number.exponent == 0
5303 && generic_floating_point_number.low[0] == 0)))
5304 {
5305 /* HACK! Turn it into a long. */
5306 LITTLENUM_TYPE words[6];
5307
5308 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5309 op (exp) = O_constant;
5310 adds (exp) = 0;
5311 subs (exp) = 0;
5312 offs (exp) = words[1] | (words[0] << 16);
5313 }
5314 else if (ok != 0)
5315 {
5316 op (exp) = O_constant;
5317 adds (exp) = 0;
5318 subs (exp) = 0;
5319 offs (exp) = (ok == 10) ? 1 : 0;
5320 as_warn (_("Can't deal with expression; defaulting to %ld"),
5321 (long) offs (exp));
5322 }
5323 }
5324 else
5325 {
5326 if (ok >= 10 && ok <= 80)
5327 {
5328 op (exp) = O_constant;
5329 adds (exp) = 0;
5330 subs (exp) = 0;
5331 offs (exp) = (ok == 10) ? 1 : 0;
5332 as_warn (_("Can't deal with expression; defaulting to %ld"),
5333 (long) offs (exp));
5334 }
5335 }
5336
5337 if (exp->size != SIZE_UNSPEC)
5338 {
5339 switch (exp->size)
5340 {
5341 case SIZE_UNSPEC:
5342 case SIZE_LONG:
5343 break;
5344 case SIZE_BYTE:
5345 if (!isbyte (offs (exp)))
5346 as_warn (_("expression doesn't fit in BYTE"));
5347 break;
5348 case SIZE_WORD:
5349 if (!isword (offs (exp)))
5350 as_warn (_("expression doesn't fit in WORD"));
5351 break;
5352 }
5353 }
5354
5355 return offs (exp);
5356 }
5357
5358 /* These are the back-ends for the various machine dependent pseudo-ops. */
5359
5360 static void
5361 s_data1 (int ignore ATTRIBUTE_UNUSED)
5362 {
5363 subseg_set (data_section, 1);
5364 demand_empty_rest_of_line ();
5365 }
5366
5367 static void
5368 s_data2 (int ignore ATTRIBUTE_UNUSED)
5369 {
5370 subseg_set (data_section, 2);
5371 demand_empty_rest_of_line ();
5372 }
5373
5374 static void
5375 s_bss (int ignore ATTRIBUTE_UNUSED)
5376 {
5377 /* We don't support putting frags in the BSS segment, we fake it
5378 by marking in_bss, then looking at s_skip for clues. */
5379
5380 subseg_set (bss_section, 0);
5381 demand_empty_rest_of_line ();
5382 }
5383
5384 static void
5385 s_even (int ignore ATTRIBUTE_UNUSED)
5386 {
5387 register int temp;
5388 register long temp_fill;
5389
5390 temp = 1; /* JF should be 2? */
5391 temp_fill = get_absolute_expression ();
5392 if (!need_pass_2) /* Never make frag if expect extra pass. */
5393 frag_align (temp, (int) temp_fill, 0);
5394 demand_empty_rest_of_line ();
5395 record_alignment (now_seg, temp);
5396 }
5397
5398 static void
5399 s_proc (int ignore ATTRIBUTE_UNUSED)
5400 {
5401 demand_empty_rest_of_line ();
5402 }
5403 \f
5404 /* Pseudo-ops handled for MRI compatibility. */
5405
5406 /* This function returns non-zero if the argument is a conditional
5407 pseudo-op. This is called when checking whether a pending
5408 alignment is needed. */
5409
5410 int
5411 m68k_conditional_pseudoop (pseudo_typeS *pop)
5412 {
5413 return (pop->poc_handler == s_mri_if
5414 || pop->poc_handler == s_mri_else);
5415 }
5416
5417 /* Handle an MRI style chip specification. */
5418
5419 static void
5420 mri_chip (void)
5421 {
5422 char *s;
5423 char c;
5424 int i;
5425
5426 s = input_line_pointer;
5427 /* We can't use get_symbol_end since the processor names are not proper
5428 symbols. */
5429 while (is_part_of_name (c = *input_line_pointer++))
5430 ;
5431 *--input_line_pointer = 0;
5432 for (i = 0; m68k_cpus[i].name; i++)
5433 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5434 break;
5435 if (!m68k_cpus[i].name)
5436 {
5437 as_bad (_("%s: unrecognized processor name"), s);
5438 *input_line_pointer = c;
5439 ignore_rest_of_line ();
5440 return;
5441 }
5442 *input_line_pointer = c;
5443
5444 if (*input_line_pointer == '/')
5445 current_architecture = 0;
5446 else
5447 current_architecture &= m68881 | m68851;
5448 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5449 control_regs = m68k_cpus[i].control_regs;
5450
5451 while (*input_line_pointer == '/')
5452 {
5453 ++input_line_pointer;
5454 s = input_line_pointer;
5455 /* We can't use get_symbol_end since the processor names are not
5456 proper symbols. */
5457 while (is_part_of_name (c = *input_line_pointer++))
5458 ;
5459 *--input_line_pointer = 0;
5460 if (strcmp (s, "68881") == 0)
5461 current_architecture |= m68881;
5462 else if (strcmp (s, "68851") == 0)
5463 current_architecture |= m68851;
5464 *input_line_pointer = c;
5465 }
5466 }
5467
5468 /* The MRI CHIP pseudo-op. */
5469
5470 static void
5471 s_chip (int ignore ATTRIBUTE_UNUSED)
5472 {
5473 char *stop = NULL;
5474 char stopc;
5475
5476 if (flag_mri)
5477 stop = mri_comment_field (&stopc);
5478 mri_chip ();
5479 if (flag_mri)
5480 mri_comment_end (stop, stopc);
5481 demand_empty_rest_of_line ();
5482 }
5483
5484 /* The MRI FOPT pseudo-op. */
5485
5486 static void
5487 s_fopt (int ignore ATTRIBUTE_UNUSED)
5488 {
5489 SKIP_WHITESPACE ();
5490
5491 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5492 {
5493 int temp;
5494
5495 input_line_pointer += 3;
5496 temp = get_absolute_expression ();
5497 if (temp < 0 || temp > 7)
5498 as_bad (_("bad coprocessor id"));
5499 else
5500 m68k_float_copnum = COP0 + temp;
5501 }
5502 else
5503 {
5504 as_bad (_("unrecognized fopt option"));
5505 ignore_rest_of_line ();
5506 return;
5507 }
5508
5509 demand_empty_rest_of_line ();
5510 }
5511
5512 /* The structure used to handle the MRI OPT pseudo-op. */
5513
5514 struct opt_action
5515 {
5516 /* The name of the option. */
5517 const char *name;
5518
5519 /* If this is not NULL, just call this function. The first argument
5520 is the ARG field of this structure, the second argument is
5521 whether the option was negated. */
5522 void (*pfn) (int arg, int on);
5523
5524 /* If this is not NULL, and the PFN field is NULL, set the variable
5525 this points to. Set it to the ARG field if the option was not
5526 negated, and the NOTARG field otherwise. */
5527 int *pvar;
5528
5529 /* The value to pass to PFN or to assign to *PVAR. */
5530 int arg;
5531
5532 /* The value to assign to *PVAR if the option is negated. If PFN is
5533 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5534 the option may not be negated. */
5535 int notarg;
5536 };
5537
5538 /* The table used to handle the MRI OPT pseudo-op. */
5539
5540 static void skip_to_comma (int, int);
5541 static void opt_nest (int, int);
5542 static void opt_chip (int, int);
5543 static void opt_list (int, int);
5544 static void opt_list_symbols (int, int);
5545
5546 static const struct opt_action opt_table[] =
5547 {
5548 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5549
5550 /* We do relaxing, so there is little use for these options. */
5551 { "b", 0, 0, 0, 0 },
5552 { "brs", 0, 0, 0, 0 },
5553 { "brb", 0, 0, 0, 0 },
5554 { "brl", 0, 0, 0, 0 },
5555 { "brw", 0, 0, 0, 0 },
5556
5557 { "c", 0, 0, 0, 0 },
5558 { "cex", 0, 0, 0, 0 },
5559 { "case", 0, &symbols_case_sensitive, 1, 0 },
5560 { "cl", 0, 0, 0, 0 },
5561 { "cre", 0, 0, 0, 0 },
5562 { "d", 0, &flag_keep_locals, 1, 0 },
5563 { "e", 0, 0, 0, 0 },
5564 { "f", 0, &flag_short_refs, 1, 0 },
5565 { "frs", 0, &flag_short_refs, 1, 0 },
5566 { "frl", 0, &flag_short_refs, 0, 1 },
5567 { "g", 0, 0, 0, 0 },
5568 { "i", 0, 0, 0, 0 },
5569 { "m", 0, 0, 0, 0 },
5570 { "mex", 0, 0, 0, 0 },
5571 { "mc", 0, 0, 0, 0 },
5572 { "md", 0, 0, 0, 0 },
5573 { "nest", opt_nest, 0, 0, 0 },
5574 { "next", skip_to_comma, 0, 0, 0 },
5575 { "o", 0, 0, 0, 0 },
5576 { "old", 0, 0, 0, 0 },
5577 { "op", skip_to_comma, 0, 0, 0 },
5578 { "pco", 0, 0, 0, 0 },
5579 { "p", opt_chip, 0, 0, 0 },
5580 { "pcr", 0, 0, 0, 0 },
5581 { "pcs", 0, 0, 0, 0 },
5582 { "r", 0, 0, 0, 0 },
5583 { "quick", 0, &m68k_quick, 1, 0 },
5584 { "rel32", 0, &m68k_rel32, 1, 0 },
5585 { "s", opt_list, 0, 0, 0 },
5586 { "t", opt_list_symbols, 0, 0, 0 },
5587 { "w", 0, &flag_no_warnings, 0, 1 },
5588 { "x", 0, 0, 0, 0 }
5589 };
5590
5591 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5592
5593 /* The MRI OPT pseudo-op. */
5594
5595 static void
5596 s_opt (int ignore ATTRIBUTE_UNUSED)
5597 {
5598 do
5599 {
5600 int t;
5601 char *s;
5602 char c;
5603 int i;
5604 const struct opt_action *o;
5605
5606 SKIP_WHITESPACE ();
5607
5608 t = 1;
5609 if (*input_line_pointer == '-')
5610 {
5611 ++input_line_pointer;
5612 t = 0;
5613 }
5614 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5615 {
5616 input_line_pointer += 2;
5617 t = 0;
5618 }
5619
5620 s = input_line_pointer;
5621 c = get_symbol_end ();
5622
5623 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5624 {
5625 if (strcasecmp (s, o->name) == 0)
5626 {
5627 if (o->pfn)
5628 {
5629 /* Restore input_line_pointer now in case the option
5630 takes arguments. */
5631 *input_line_pointer = c;
5632 (*o->pfn) (o->arg, t);
5633 }
5634 else if (o->pvar != NULL)
5635 {
5636 if (! t && o->arg == o->notarg)
5637 as_bad (_("option `%s' may not be negated"), s);
5638 *input_line_pointer = c;
5639 *o->pvar = t ? o->arg : o->notarg;
5640 }
5641 else
5642 *input_line_pointer = c;
5643 break;
5644 }
5645 }
5646 if (i >= OPTCOUNT)
5647 {
5648 as_bad (_("option `%s' not recognized"), s);
5649 *input_line_pointer = c;
5650 }
5651 }
5652 while (*input_line_pointer++ == ',');
5653
5654 /* Move back to terminating character. */
5655 --input_line_pointer;
5656 demand_empty_rest_of_line ();
5657 }
5658
5659 /* Skip ahead to a comma. This is used for OPT options which we do
5660 not support and which take arguments. */
5661
5662 static void
5663 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5664 {
5665 while (*input_line_pointer != ','
5666 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5667 ++input_line_pointer;
5668 }
5669
5670 /* Handle the OPT NEST=depth option. */
5671
5672 static void
5673 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5674 {
5675 if (*input_line_pointer != '=')
5676 {
5677 as_bad (_("bad format of OPT NEST=depth"));
5678 return;
5679 }
5680
5681 ++input_line_pointer;
5682 max_macro_nest = get_absolute_expression ();
5683 }
5684
5685 /* Handle the OPT P=chip option. */
5686
5687 static void
5688 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5689 {
5690 if (*input_line_pointer != '=')
5691 {
5692 /* This is just OPT P, which we do not support. */
5693 return;
5694 }
5695
5696 ++input_line_pointer;
5697 mri_chip ();
5698 }
5699
5700 /* Handle the OPT S option. */
5701
5702 static void
5703 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5704 {
5705 listing_list (on);
5706 }
5707
5708 /* Handle the OPT T option. */
5709
5710 static void
5711 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5712 {
5713 if (on)
5714 listing |= LISTING_SYMBOLS;
5715 else
5716 listing &= ~LISTING_SYMBOLS;
5717 }
5718
5719 /* Handle the MRI REG pseudo-op. */
5720
5721 static void
5722 s_reg (int ignore ATTRIBUTE_UNUSED)
5723 {
5724 char *s;
5725 int c;
5726 struct m68k_op rop;
5727 int mask;
5728 char *stop = NULL;
5729 char stopc;
5730
5731 if (line_label == NULL)
5732 {
5733 as_bad (_("missing label"));
5734 ignore_rest_of_line ();
5735 return;
5736 }
5737
5738 if (flag_mri)
5739 stop = mri_comment_field (&stopc);
5740
5741 SKIP_WHITESPACE ();
5742
5743 s = input_line_pointer;
5744 while (ISALNUM (*input_line_pointer)
5745 #ifdef REGISTER_PREFIX
5746 || *input_line_pointer == REGISTER_PREFIX
5747 #endif
5748 || *input_line_pointer == '/'
5749 || *input_line_pointer == '-')
5750 ++input_line_pointer;
5751 c = *input_line_pointer;
5752 *input_line_pointer = '\0';
5753
5754 if (m68k_ip_op (s, &rop) != 0)
5755 {
5756 if (rop.error == NULL)
5757 as_bad (_("bad register list"));
5758 else
5759 as_bad (_("bad register list: %s"), rop.error);
5760 *input_line_pointer = c;
5761 ignore_rest_of_line ();
5762 return;
5763 }
5764
5765 *input_line_pointer = c;
5766
5767 if (rop.mode == REGLST)
5768 mask = rop.mask;
5769 else if (rop.mode == DREG)
5770 mask = 1 << (rop.reg - DATA0);
5771 else if (rop.mode == AREG)
5772 mask = 1 << (rop.reg - ADDR0 + 8);
5773 else if (rop.mode == FPREG)
5774 mask = 1 << (rop.reg - FP0 + 16);
5775 else if (rop.mode == CONTROL
5776 && rop.reg == FPI)
5777 mask = 1 << 24;
5778 else if (rop.mode == CONTROL
5779 && rop.reg == FPS)
5780 mask = 1 << 25;
5781 else if (rop.mode == CONTROL
5782 && rop.reg == FPC)
5783 mask = 1 << 26;
5784 else
5785 {
5786 as_bad (_("bad register list"));
5787 ignore_rest_of_line ();
5788 return;
5789 }
5790
5791 S_SET_SEGMENT (line_label, reg_section);
5792 S_SET_VALUE (line_label, ~mask);
5793 symbol_set_frag (line_label, &zero_address_frag);
5794
5795 if (flag_mri)
5796 mri_comment_end (stop, stopc);
5797
5798 demand_empty_rest_of_line ();
5799 }
5800
5801 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5802
5803 struct save_opts
5804 {
5805 struct save_opts *next;
5806 int abspcadd;
5807 int symbols_case_sensitive;
5808 int keep_locals;
5809 int short_refs;
5810 int architecture;
5811 const enum m68k_register *control_regs;
5812 int quick;
5813 int rel32;
5814 int listing;
5815 int no_warnings;
5816 /* FIXME: We don't save OPT S. */
5817 };
5818
5819 /* This variable holds the stack of saved options. */
5820
5821 static struct save_opts *save_stack;
5822
5823 /* The MRI SAVE pseudo-op. */
5824
5825 static void
5826 s_save (int ignore ATTRIBUTE_UNUSED)
5827 {
5828 struct save_opts *s;
5829
5830 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5831 s->abspcadd = m68k_abspcadd;
5832 s->symbols_case_sensitive = symbols_case_sensitive;
5833 s->keep_locals = flag_keep_locals;
5834 s->short_refs = flag_short_refs;
5835 s->architecture = current_architecture;
5836 s->control_regs = control_regs;
5837 s->quick = m68k_quick;
5838 s->rel32 = m68k_rel32;
5839 s->listing = listing;
5840 s->no_warnings = flag_no_warnings;
5841
5842 s->next = save_stack;
5843 save_stack = s;
5844
5845 demand_empty_rest_of_line ();
5846 }
5847
5848 /* The MRI RESTORE pseudo-op. */
5849
5850 static void
5851 s_restore (int ignore ATTRIBUTE_UNUSED)
5852 {
5853 struct save_opts *s;
5854
5855 if (save_stack == NULL)
5856 {
5857 as_bad (_("restore without save"));
5858 ignore_rest_of_line ();
5859 return;
5860 }
5861
5862 s = save_stack;
5863 save_stack = s->next;
5864
5865 m68k_abspcadd = s->abspcadd;
5866 symbols_case_sensitive = s->symbols_case_sensitive;
5867 flag_keep_locals = s->keep_locals;
5868 flag_short_refs = s->short_refs;
5869 current_architecture = s->architecture;
5870 control_regs = s->control_regs;
5871 m68k_quick = s->quick;
5872 m68k_rel32 = s->rel32;
5873 listing = s->listing;
5874 flag_no_warnings = s->no_warnings;
5875
5876 free (s);
5877
5878 demand_empty_rest_of_line ();
5879 }
5880
5881 /* Types of MRI structured control directives. */
5882
5883 enum mri_control_type
5884 {
5885 mri_for,
5886 mri_if,
5887 mri_repeat,
5888 mri_while
5889 };
5890
5891 /* This structure is used to stack the MRI structured control
5892 directives. */
5893
5894 struct mri_control_info
5895 {
5896 /* The directive within which this one is enclosed. */
5897 struct mri_control_info *outer;
5898
5899 /* The type of directive. */
5900 enum mri_control_type type;
5901
5902 /* Whether an ELSE has been in an IF. */
5903 int else_seen;
5904
5905 /* The add or sub statement at the end of a FOR. */
5906 char *incr;
5907
5908 /* The label of the top of a FOR or REPEAT loop. */
5909 char *top;
5910
5911 /* The label to jump to for the next iteration, or the else
5912 expression of a conditional. */
5913 char *next;
5914
5915 /* The label to jump to to break out of the loop, or the label past
5916 the end of a conditional. */
5917 char *bottom;
5918 };
5919
5920 /* The stack of MRI structured control directives. */
5921
5922 static struct mri_control_info *mri_control_stack;
5923
5924 /* The current MRI structured control directive index number, used to
5925 generate label names. */
5926
5927 static int mri_control_index;
5928
5929 /* Assemble an instruction for an MRI structured control directive. */
5930
5931 static void
5932 mri_assemble (char *str)
5933 {
5934 char *s;
5935
5936 /* md_assemble expects the opcode to be in lower case. */
5937 for (s = str; *s != ' ' && *s != '\0'; s++)
5938 *s = TOLOWER (*s);
5939
5940 md_assemble (str);
5941 }
5942
5943 /* Generate a new MRI label structured control directive label name. */
5944
5945 static char *
5946 mri_control_label (void)
5947 {
5948 char *n;
5949
5950 n = (char *) xmalloc (20);
5951 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5952 ++mri_control_index;
5953 return n;
5954 }
5955
5956 /* Create a new MRI structured control directive. */
5957
5958 static struct mri_control_info *
5959 push_mri_control (enum mri_control_type type)
5960 {
5961 struct mri_control_info *n;
5962
5963 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5964
5965 n->type = type;
5966 n->else_seen = 0;
5967 if (type == mri_if || type == mri_while)
5968 n->top = NULL;
5969 else
5970 n->top = mri_control_label ();
5971 n->next = mri_control_label ();
5972 n->bottom = mri_control_label ();
5973
5974 n->outer = mri_control_stack;
5975 mri_control_stack = n;
5976
5977 return n;
5978 }
5979
5980 /* Pop off the stack of MRI structured control directives. */
5981
5982 static void
5983 pop_mri_control (void)
5984 {
5985 struct mri_control_info *n;
5986
5987 n = mri_control_stack;
5988 mri_control_stack = n->outer;
5989 if (n->top != NULL)
5990 free (n->top);
5991 free (n->next);
5992 free (n->bottom);
5993 free (n);
5994 }
5995
5996 /* Recognize a condition code in an MRI structured control expression. */
5997
5998 static int
5999 parse_mri_condition (int *pcc)
6000 {
6001 char c1, c2;
6002
6003 know (*input_line_pointer == '<');
6004
6005 ++input_line_pointer;
6006 c1 = *input_line_pointer++;
6007 c2 = *input_line_pointer++;
6008
6009 if (*input_line_pointer != '>')
6010 {
6011 as_bad (_("syntax error in structured control directive"));
6012 return 0;
6013 }
6014
6015 ++input_line_pointer;
6016 SKIP_WHITESPACE ();
6017
6018 c1 = TOLOWER (c1);
6019 c2 = TOLOWER (c2);
6020
6021 *pcc = (c1 << 8) | c2;
6022
6023 return 1;
6024 }
6025
6026 /* Parse a single operand in an MRI structured control expression. */
6027
6028 static int
6029 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6030 char **rightstart, char **rightstop)
6031 {
6032 char *s;
6033
6034 SKIP_WHITESPACE ();
6035
6036 *pcc = -1;
6037 *leftstart = NULL;
6038 *leftstop = NULL;
6039 *rightstart = NULL;
6040 *rightstop = NULL;
6041
6042 if (*input_line_pointer == '<')
6043 {
6044 /* It's just a condition code. */
6045 return parse_mri_condition (pcc);
6046 }
6047
6048 /* Look ahead for the condition code. */
6049 for (s = input_line_pointer; *s != '\0'; ++s)
6050 {
6051 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6052 break;
6053 }
6054 if (*s == '\0')
6055 {
6056 as_bad (_("missing condition code in structured control directive"));
6057 return 0;
6058 }
6059
6060 *leftstart = input_line_pointer;
6061 *leftstop = s;
6062 if (*leftstop > *leftstart
6063 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6064 --*leftstop;
6065
6066 input_line_pointer = s;
6067 if (! parse_mri_condition (pcc))
6068 return 0;
6069
6070 /* Look ahead for AND or OR or end of line. */
6071 for (s = input_line_pointer; *s != '\0'; ++s)
6072 {
6073 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6074 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6075 ^^^ ^^ */
6076 if ((s == input_line_pointer
6077 || *(s-1) == ' '
6078 || *(s-1) == '\t')
6079 && ((strncasecmp (s, "AND", 3) == 0
6080 && (s[3] == '.' || ! is_part_of_name (s[3])))
6081 || (strncasecmp (s, "OR", 2) == 0
6082 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6083 break;
6084 }
6085
6086 *rightstart = input_line_pointer;
6087 *rightstop = s;
6088 if (*rightstop > *rightstart
6089 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6090 --*rightstop;
6091
6092 input_line_pointer = s;
6093
6094 return 1;
6095 }
6096
6097 #define MCC(b1, b2) (((b1) << 8) | (b2))
6098
6099 /* Swap the sense of a condition. This changes the condition so that
6100 it generates the same result when the operands are swapped. */
6101
6102 static int
6103 swap_mri_condition (int cc)
6104 {
6105 switch (cc)
6106 {
6107 case MCC ('h', 'i'): return MCC ('c', 's');
6108 case MCC ('l', 's'): return MCC ('c', 'c');
6109 /* <HS> is an alias for <CC>. */
6110 case MCC ('h', 's'):
6111 case MCC ('c', 'c'): return MCC ('l', 's');
6112 /* <LO> is an alias for <CS>. */
6113 case MCC ('l', 'o'):
6114 case MCC ('c', 's'): return MCC ('h', 'i');
6115 case MCC ('p', 'l'): return MCC ('m', 'i');
6116 case MCC ('m', 'i'): return MCC ('p', 'l');
6117 case MCC ('g', 'e'): return MCC ('l', 'e');
6118 case MCC ('l', 't'): return MCC ('g', 't');
6119 case MCC ('g', 't'): return MCC ('l', 't');
6120 case MCC ('l', 'e'): return MCC ('g', 'e');
6121 /* Issue a warning for conditions we can not swap. */
6122 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6123 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6124 case MCC ('v', 'c'):
6125 case MCC ('v', 's'):
6126 default :
6127 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6128 (char) (cc >> 8), (char) (cc));
6129 break;
6130 }
6131 return cc;
6132 }
6133
6134 /* Reverse the sense of a condition. */
6135
6136 static int
6137 reverse_mri_condition (int cc)
6138 {
6139 switch (cc)
6140 {
6141 case MCC ('h', 'i'): return MCC ('l', 's');
6142 case MCC ('l', 's'): return MCC ('h', 'i');
6143 /* <HS> is an alias for <CC> */
6144 case MCC ('h', 's'): return MCC ('l', 'o');
6145 case MCC ('c', 'c'): return MCC ('c', 's');
6146 /* <LO> is an alias for <CS> */
6147 case MCC ('l', 'o'): return MCC ('h', 's');
6148 case MCC ('c', 's'): return MCC ('c', 'c');
6149 case MCC ('n', 'e'): return MCC ('e', 'q');
6150 case MCC ('e', 'q'): return MCC ('n', 'e');
6151 case MCC ('v', 'c'): return MCC ('v', 's');
6152 case MCC ('v', 's'): return MCC ('v', 'c');
6153 case MCC ('p', 'l'): return MCC ('m', 'i');
6154 case MCC ('m', 'i'): return MCC ('p', 'l');
6155 case MCC ('g', 'e'): return MCC ('l', 't');
6156 case MCC ('l', 't'): return MCC ('g', 'e');
6157 case MCC ('g', 't'): return MCC ('l', 'e');
6158 case MCC ('l', 'e'): return MCC ('g', 't');
6159 }
6160 return cc;
6161 }
6162
6163 /* Build an MRI structured control expression. This generates test
6164 and branch instructions. It goes to TRUELAB if the condition is
6165 true, and to FALSELAB if the condition is false. Exactly one of
6166 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6167 is the size qualifier for the expression. EXTENT is the size to
6168 use for the branch. */
6169
6170 static void
6171 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6172 char *rightstart, char *rightstop,
6173 const char *truelab, const char *falselab,
6174 int extent)
6175 {
6176 char *buf;
6177 char *s;
6178
6179 if (leftstart != NULL)
6180 {
6181 struct m68k_op leftop, rightop;
6182 char c;
6183
6184 /* Swap the compare operands, if necessary, to produce a legal
6185 m68k compare instruction. Comparing a register operand with
6186 a non-register operand requires the register to be on the
6187 right (cmp, cmpa). Comparing an immediate value with
6188 anything requires the immediate value to be on the left
6189 (cmpi). */
6190
6191 c = *leftstop;
6192 *leftstop = '\0';
6193 (void) m68k_ip_op (leftstart, &leftop);
6194 *leftstop = c;
6195
6196 c = *rightstop;
6197 *rightstop = '\0';
6198 (void) m68k_ip_op (rightstart, &rightop);
6199 *rightstop = c;
6200
6201 if (rightop.mode == IMMED
6202 || ((leftop.mode == DREG || leftop.mode == AREG)
6203 && (rightop.mode != DREG && rightop.mode != AREG)))
6204 {
6205 char *temp;
6206
6207 /* Correct conditional handling:
6208 if #1 <lt> d0 then ;means if (1 < d0)
6209 ...
6210 endi
6211
6212 should assemble to:
6213
6214 cmp #1,d0 if we do *not* swap the operands
6215 bgt true we need the swapped condition!
6216 ble false
6217 true:
6218 ...
6219 false:
6220 */
6221 temp = leftstart;
6222 leftstart = rightstart;
6223 rightstart = temp;
6224 temp = leftstop;
6225 leftstop = rightstop;
6226 rightstop = temp;
6227 }
6228 else
6229 {
6230 cc = swap_mri_condition (cc);
6231 }
6232 }
6233
6234 if (truelab == NULL)
6235 {
6236 cc = reverse_mri_condition (cc);
6237 truelab = falselab;
6238 }
6239
6240 if (leftstart != NULL)
6241 {
6242 buf = (char *) xmalloc (20
6243 + (leftstop - leftstart)
6244 + (rightstop - rightstart));
6245 s = buf;
6246 *s++ = 'c';
6247 *s++ = 'm';
6248 *s++ = 'p';
6249 if (qual != '\0')
6250 *s++ = TOLOWER (qual);
6251 *s++ = ' ';
6252 memcpy (s, leftstart, leftstop - leftstart);
6253 s += leftstop - leftstart;
6254 *s++ = ',';
6255 memcpy (s, rightstart, rightstop - rightstart);
6256 s += rightstop - rightstart;
6257 *s = '\0';
6258 mri_assemble (buf);
6259 free (buf);
6260 }
6261
6262 buf = (char *) xmalloc (20 + strlen (truelab));
6263 s = buf;
6264 *s++ = 'b';
6265 *s++ = cc >> 8;
6266 *s++ = cc & 0xff;
6267 if (extent != '\0')
6268 *s++ = TOLOWER (extent);
6269 *s++ = ' ';
6270 strcpy (s, truelab);
6271 mri_assemble (buf);
6272 free (buf);
6273 }
6274
6275 /* Parse an MRI structured control expression. This generates test
6276 and branch instructions. STOP is where the expression ends. It
6277 goes to TRUELAB if the condition is true, and to FALSELAB if the
6278 condition is false. Exactly one of TRUELAB and FALSELAB will be
6279 NULL, meaning to fall through. QUAL is the size qualifier for the
6280 expression. EXTENT is the size to use for the branch. */
6281
6282 static void
6283 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6284 const char *falselab, int extent)
6285 {
6286 int c;
6287 int cc;
6288 char *leftstart;
6289 char *leftstop;
6290 char *rightstart;
6291 char *rightstop;
6292
6293 c = *stop;
6294 *stop = '\0';
6295
6296 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6297 &rightstart, &rightstop))
6298 {
6299 *stop = c;
6300 return;
6301 }
6302
6303 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6304 {
6305 const char *flab;
6306
6307 if (falselab != NULL)
6308 flab = falselab;
6309 else
6310 flab = mri_control_label ();
6311
6312 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6313 rightstop, (const char *) NULL, flab, extent);
6314
6315 input_line_pointer += 3;
6316 if (*input_line_pointer != '.'
6317 || input_line_pointer[1] == '\0')
6318 qual = '\0';
6319 else
6320 {
6321 qual = input_line_pointer[1];
6322 input_line_pointer += 2;
6323 }
6324
6325 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6326 &rightstart, &rightstop))
6327 {
6328 *stop = c;
6329 return;
6330 }
6331
6332 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6333 rightstop, truelab, falselab, extent);
6334
6335 if (falselab == NULL)
6336 colon (flab);
6337 }
6338 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6339 {
6340 const char *tlab;
6341
6342 if (truelab != NULL)
6343 tlab = truelab;
6344 else
6345 tlab = mri_control_label ();
6346
6347 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6348 rightstop, tlab, (const char *) NULL, extent);
6349
6350 input_line_pointer += 2;
6351 if (*input_line_pointer != '.'
6352 || input_line_pointer[1] == '\0')
6353 qual = '\0';
6354 else
6355 {
6356 qual = input_line_pointer[1];
6357 input_line_pointer += 2;
6358 }
6359
6360 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6361 &rightstart, &rightstop))
6362 {
6363 *stop = c;
6364 return;
6365 }
6366
6367 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6368 rightstop, truelab, falselab, extent);
6369
6370 if (truelab == NULL)
6371 colon (tlab);
6372 }
6373 else
6374 {
6375 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6376 rightstop, truelab, falselab, extent);
6377 }
6378
6379 *stop = c;
6380 if (input_line_pointer != stop)
6381 as_bad (_("syntax error in structured control directive"));
6382 }
6383
6384 /* Handle the MRI IF pseudo-op. This may be a structured control
6385 directive, or it may be a regular assembler conditional, depending
6386 on its operands. */
6387
6388 static void
6389 s_mri_if (int qual)
6390 {
6391 char *s;
6392 int c;
6393 struct mri_control_info *n;
6394
6395 /* A structured control directive must end with THEN with an
6396 optional qualifier. */
6397 s = input_line_pointer;
6398 /* We only accept '*' as introduction of comments if preceded by white space
6399 or at first column of a line (I think this can't actually happen here?)
6400 This is important when assembling:
6401 if d0 <ne> 12(a0,d0*2) then
6402 if d0 <ne> #CONST*20 then. */
6403 while (! (is_end_of_line[(unsigned char) *s]
6404 || (flag_mri
6405 && *s == '*'
6406 && (s == input_line_pointer
6407 || *(s-1) == ' '
6408 || *(s-1) == '\t'))))
6409 ++s;
6410 --s;
6411 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6412 --s;
6413
6414 if (s - input_line_pointer > 1
6415 && s[-1] == '.')
6416 s -= 2;
6417
6418 if (s - input_line_pointer < 3
6419 || strncasecmp (s - 3, "THEN", 4) != 0)
6420 {
6421 if (qual != '\0')
6422 {
6423 as_bad (_("missing then"));
6424 ignore_rest_of_line ();
6425 return;
6426 }
6427
6428 /* It's a conditional. */
6429 s_if (O_ne);
6430 return;
6431 }
6432
6433 /* Since this might be a conditional if, this pseudo-op will be
6434 called even if we are supported to be ignoring input. Double
6435 check now. Clobber *input_line_pointer so that ignore_input
6436 thinks that this is not a special pseudo-op. */
6437 c = *input_line_pointer;
6438 *input_line_pointer = 0;
6439 if (ignore_input ())
6440 {
6441 *input_line_pointer = c;
6442 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6443 ++input_line_pointer;
6444 demand_empty_rest_of_line ();
6445 return;
6446 }
6447 *input_line_pointer = c;
6448
6449 n = push_mri_control (mri_if);
6450
6451 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6452 n->next, s[1] == '.' ? s[2] : '\0');
6453
6454 if (s[1] == '.')
6455 input_line_pointer = s + 3;
6456 else
6457 input_line_pointer = s + 1;
6458
6459 if (flag_mri)
6460 {
6461 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6462 ++input_line_pointer;
6463 }
6464
6465 demand_empty_rest_of_line ();
6466 }
6467
6468 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6469 structured IF, associate the ELSE with the IF. Otherwise, assume
6470 it is a conditional else. */
6471
6472 static void
6473 s_mri_else (int qual)
6474 {
6475 int c;
6476 char *buf;
6477 char q[2];
6478
6479 if (qual == '\0'
6480 && (mri_control_stack == NULL
6481 || mri_control_stack->type != mri_if
6482 || mri_control_stack->else_seen))
6483 {
6484 s_else (0);
6485 return;
6486 }
6487
6488 c = *input_line_pointer;
6489 *input_line_pointer = 0;
6490 if (ignore_input ())
6491 {
6492 *input_line_pointer = c;
6493 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6494 ++input_line_pointer;
6495 demand_empty_rest_of_line ();
6496 return;
6497 }
6498 *input_line_pointer = c;
6499
6500 if (mri_control_stack == NULL
6501 || mri_control_stack->type != mri_if
6502 || mri_control_stack->else_seen)
6503 {
6504 as_bad (_("else without matching if"));
6505 ignore_rest_of_line ();
6506 return;
6507 }
6508
6509 mri_control_stack->else_seen = 1;
6510
6511 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6512 q[0] = TOLOWER (qual);
6513 q[1] = '\0';
6514 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6515 mri_assemble (buf);
6516 free (buf);
6517
6518 colon (mri_control_stack->next);
6519
6520 if (flag_mri)
6521 {
6522 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6523 ++input_line_pointer;
6524 }
6525
6526 demand_empty_rest_of_line ();
6527 }
6528
6529 /* Handle the MRI ENDI pseudo-op. */
6530
6531 static void
6532 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6533 {
6534 if (mri_control_stack == NULL
6535 || mri_control_stack->type != mri_if)
6536 {
6537 as_bad (_("endi without matching if"));
6538 ignore_rest_of_line ();
6539 return;
6540 }
6541
6542 /* ignore_input will not return true for ENDI, so we don't need to
6543 worry about checking it again here. */
6544
6545 if (! mri_control_stack->else_seen)
6546 colon (mri_control_stack->next);
6547 colon (mri_control_stack->bottom);
6548
6549 pop_mri_control ();
6550
6551 if (flag_mri)
6552 {
6553 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6554 ++input_line_pointer;
6555 }
6556
6557 demand_empty_rest_of_line ();
6558 }
6559
6560 /* Handle the MRI BREAK pseudo-op. */
6561
6562 static void
6563 s_mri_break (int extent)
6564 {
6565 struct mri_control_info *n;
6566 char *buf;
6567 char ex[2];
6568
6569 n = mri_control_stack;
6570 while (n != NULL
6571 && n->type != mri_for
6572 && n->type != mri_repeat
6573 && n->type != mri_while)
6574 n = n->outer;
6575 if (n == NULL)
6576 {
6577 as_bad (_("break outside of structured loop"));
6578 ignore_rest_of_line ();
6579 return;
6580 }
6581
6582 buf = (char *) xmalloc (20 + strlen (n->bottom));
6583 ex[0] = TOLOWER (extent);
6584 ex[1] = '\0';
6585 sprintf (buf, "bra%s %s", ex, n->bottom);
6586 mri_assemble (buf);
6587 free (buf);
6588
6589 if (flag_mri)
6590 {
6591 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6592 ++input_line_pointer;
6593 }
6594
6595 demand_empty_rest_of_line ();
6596 }
6597
6598 /* Handle the MRI NEXT pseudo-op. */
6599
6600 static void
6601 s_mri_next (int extent)
6602 {
6603 struct mri_control_info *n;
6604 char *buf;
6605 char ex[2];
6606
6607 n = mri_control_stack;
6608 while (n != NULL
6609 && n->type != mri_for
6610 && n->type != mri_repeat
6611 && n->type != mri_while)
6612 n = n->outer;
6613 if (n == NULL)
6614 {
6615 as_bad (_("next outside of structured loop"));
6616 ignore_rest_of_line ();
6617 return;
6618 }
6619
6620 buf = (char *) xmalloc (20 + strlen (n->next));
6621 ex[0] = TOLOWER (extent);
6622 ex[1] = '\0';
6623 sprintf (buf, "bra%s %s", ex, n->next);
6624 mri_assemble (buf);
6625 free (buf);
6626
6627 if (flag_mri)
6628 {
6629 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6630 ++input_line_pointer;
6631 }
6632
6633 demand_empty_rest_of_line ();
6634 }
6635
6636 /* Handle the MRI FOR pseudo-op. */
6637
6638 static void
6639 s_mri_for (int qual)
6640 {
6641 const char *varstart, *varstop;
6642 const char *initstart, *initstop;
6643 const char *endstart, *endstop;
6644 const char *bystart, *bystop;
6645 int up;
6646 int by;
6647 int extent;
6648 struct mri_control_info *n;
6649 char *buf;
6650 char *s;
6651 char ex[2];
6652
6653 /* The syntax is
6654 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6655 */
6656
6657 SKIP_WHITESPACE ();
6658 varstart = input_line_pointer;
6659
6660 /* Look for the '='. */
6661 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6662 && *input_line_pointer != '=')
6663 ++input_line_pointer;
6664 if (*input_line_pointer != '=')
6665 {
6666 as_bad (_("missing ="));
6667 ignore_rest_of_line ();
6668 return;
6669 }
6670
6671 varstop = input_line_pointer;
6672 if (varstop > varstart
6673 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6674 --varstop;
6675
6676 ++input_line_pointer;
6677
6678 initstart = input_line_pointer;
6679
6680 /* Look for TO or DOWNTO. */
6681 up = 1;
6682 initstop = NULL;
6683 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6684 {
6685 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6686 && ! is_part_of_name (input_line_pointer[2]))
6687 {
6688 initstop = input_line_pointer;
6689 input_line_pointer += 2;
6690 break;
6691 }
6692 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6693 && ! is_part_of_name (input_line_pointer[6]))
6694 {
6695 initstop = input_line_pointer;
6696 up = 0;
6697 input_line_pointer += 6;
6698 break;
6699 }
6700 ++input_line_pointer;
6701 }
6702 if (initstop == NULL)
6703 {
6704 as_bad (_("missing to or downto"));
6705 ignore_rest_of_line ();
6706 return;
6707 }
6708 if (initstop > initstart
6709 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6710 --initstop;
6711
6712 SKIP_WHITESPACE ();
6713 endstart = input_line_pointer;
6714
6715 /* Look for BY or DO. */
6716 by = 0;
6717 endstop = NULL;
6718 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6719 {
6720 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6721 && ! is_part_of_name (input_line_pointer[2]))
6722 {
6723 endstop = input_line_pointer;
6724 by = 1;
6725 input_line_pointer += 2;
6726 break;
6727 }
6728 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6729 && (input_line_pointer[2] == '.'
6730 || ! is_part_of_name (input_line_pointer[2])))
6731 {
6732 endstop = input_line_pointer;
6733 input_line_pointer += 2;
6734 break;
6735 }
6736 ++input_line_pointer;
6737 }
6738 if (endstop == NULL)
6739 {
6740 as_bad (_("missing do"));
6741 ignore_rest_of_line ();
6742 return;
6743 }
6744 if (endstop > endstart
6745 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6746 --endstop;
6747
6748 if (! by)
6749 {
6750 bystart = "#1";
6751 bystop = bystart + 2;
6752 }
6753 else
6754 {
6755 SKIP_WHITESPACE ();
6756 bystart = input_line_pointer;
6757
6758 /* Look for DO. */
6759 bystop = NULL;
6760 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6761 {
6762 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6763 && (input_line_pointer[2] == '.'
6764 || ! is_part_of_name (input_line_pointer[2])))
6765 {
6766 bystop = input_line_pointer;
6767 input_line_pointer += 2;
6768 break;
6769 }
6770 ++input_line_pointer;
6771 }
6772 if (bystop == NULL)
6773 {
6774 as_bad (_("missing do"));
6775 ignore_rest_of_line ();
6776 return;
6777 }
6778 if (bystop > bystart
6779 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6780 --bystop;
6781 }
6782
6783 if (*input_line_pointer != '.')
6784 extent = '\0';
6785 else
6786 {
6787 extent = input_line_pointer[1];
6788 input_line_pointer += 2;
6789 }
6790
6791 /* We have fully parsed the FOR operands. Now build the loop. */
6792 n = push_mri_control (mri_for);
6793
6794 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6795
6796 /* Move init,var. */
6797 s = buf;
6798 *s++ = 'm';
6799 *s++ = 'o';
6800 *s++ = 'v';
6801 *s++ = 'e';
6802 if (qual != '\0')
6803 *s++ = TOLOWER (qual);
6804 *s++ = ' ';
6805 memcpy (s, initstart, initstop - initstart);
6806 s += initstop - initstart;
6807 *s++ = ',';
6808 memcpy (s, varstart, varstop - varstart);
6809 s += varstop - varstart;
6810 *s = '\0';
6811 mri_assemble (buf);
6812
6813 colon (n->top);
6814
6815 /* cmp end,var. */
6816 s = buf;
6817 *s++ = 'c';
6818 *s++ = 'm';
6819 *s++ = 'p';
6820 if (qual != '\0')
6821 *s++ = TOLOWER (qual);
6822 *s++ = ' ';
6823 memcpy (s, endstart, endstop - endstart);
6824 s += endstop - endstart;
6825 *s++ = ',';
6826 memcpy (s, varstart, varstop - varstart);
6827 s += varstop - varstart;
6828 *s = '\0';
6829 mri_assemble (buf);
6830
6831 /* bcc bottom. */
6832 ex[0] = TOLOWER (extent);
6833 ex[1] = '\0';
6834 if (up)
6835 sprintf (buf, "blt%s %s", ex, n->bottom);
6836 else
6837 sprintf (buf, "bgt%s %s", ex, n->bottom);
6838 mri_assemble (buf);
6839
6840 /* Put together the add or sub instruction used by ENDF. */
6841 s = buf;
6842 if (up)
6843 strcpy (s, "add");
6844 else
6845 strcpy (s, "sub");
6846 s += 3;
6847 if (qual != '\0')
6848 *s++ = TOLOWER (qual);
6849 *s++ = ' ';
6850 memcpy (s, bystart, bystop - bystart);
6851 s += bystop - bystart;
6852 *s++ = ',';
6853 memcpy (s, varstart, varstop - varstart);
6854 s += varstop - varstart;
6855 *s = '\0';
6856 n->incr = buf;
6857
6858 if (flag_mri)
6859 {
6860 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6861 ++input_line_pointer;
6862 }
6863
6864 demand_empty_rest_of_line ();
6865 }
6866
6867 /* Handle the MRI ENDF pseudo-op. */
6868
6869 static void
6870 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6871 {
6872 if (mri_control_stack == NULL
6873 || mri_control_stack->type != mri_for)
6874 {
6875 as_bad (_("endf without for"));
6876 ignore_rest_of_line ();
6877 return;
6878 }
6879
6880 colon (mri_control_stack->next);
6881
6882 mri_assemble (mri_control_stack->incr);
6883
6884 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6885 mri_assemble (mri_control_stack->incr);
6886
6887 free (mri_control_stack->incr);
6888
6889 colon (mri_control_stack->bottom);
6890
6891 pop_mri_control ();
6892
6893 if (flag_mri)
6894 {
6895 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6896 ++input_line_pointer;
6897 }
6898
6899 demand_empty_rest_of_line ();
6900 }
6901
6902 /* Handle the MRI REPEAT pseudo-op. */
6903
6904 static void
6905 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6906 {
6907 struct mri_control_info *n;
6908
6909 n = push_mri_control (mri_repeat);
6910 colon (n->top);
6911 if (flag_mri)
6912 {
6913 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6914 ++input_line_pointer;
6915 }
6916 demand_empty_rest_of_line ();
6917 }
6918
6919 /* Handle the MRI UNTIL pseudo-op. */
6920
6921 static void
6922 s_mri_until (int qual)
6923 {
6924 char *s;
6925
6926 if (mri_control_stack == NULL
6927 || mri_control_stack->type != mri_repeat)
6928 {
6929 as_bad (_("until without repeat"));
6930 ignore_rest_of_line ();
6931 return;
6932 }
6933
6934 colon (mri_control_stack->next);
6935
6936 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6937 ;
6938
6939 parse_mri_control_expression (s, qual, (const char *) NULL,
6940 mri_control_stack->top, '\0');
6941
6942 colon (mri_control_stack->bottom);
6943
6944 input_line_pointer = s;
6945
6946 pop_mri_control ();
6947
6948 if (flag_mri)
6949 {
6950 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6951 ++input_line_pointer;
6952 }
6953
6954 demand_empty_rest_of_line ();
6955 }
6956
6957 /* Handle the MRI WHILE pseudo-op. */
6958
6959 static void
6960 s_mri_while (int qual)
6961 {
6962 char *s;
6963
6964 struct mri_control_info *n;
6965
6966 s = input_line_pointer;
6967 /* We only accept '*' as introduction of comments if preceded by white space
6968 or at first column of a line (I think this can't actually happen here?)
6969 This is important when assembling:
6970 while d0 <ne> 12(a0,d0*2) do
6971 while d0 <ne> #CONST*20 do. */
6972 while (! (is_end_of_line[(unsigned char) *s]
6973 || (flag_mri
6974 && *s == '*'
6975 && (s == input_line_pointer
6976 || *(s-1) == ' '
6977 || *(s-1) == '\t'))))
6978 s++;
6979 --s;
6980 while (*s == ' ' || *s == '\t')
6981 --s;
6982 if (s - input_line_pointer > 1
6983 && s[-1] == '.')
6984 s -= 2;
6985 if (s - input_line_pointer < 2
6986 || strncasecmp (s - 1, "DO", 2) != 0)
6987 {
6988 as_bad (_("missing do"));
6989 ignore_rest_of_line ();
6990 return;
6991 }
6992
6993 n = push_mri_control (mri_while);
6994
6995 colon (n->next);
6996
6997 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6998 s[1] == '.' ? s[2] : '\0');
6999
7000 input_line_pointer = s + 1;
7001 if (*input_line_pointer == '.')
7002 input_line_pointer += 2;
7003
7004 if (flag_mri)
7005 {
7006 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7007 ++input_line_pointer;
7008 }
7009
7010 demand_empty_rest_of_line ();
7011 }
7012
7013 /* Handle the MRI ENDW pseudo-op. */
7014
7015 static void
7016 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7017 {
7018 char *buf;
7019
7020 if (mri_control_stack == NULL
7021 || mri_control_stack->type != mri_while)
7022 {
7023 as_bad (_("endw without while"));
7024 ignore_rest_of_line ();
7025 return;
7026 }
7027
7028 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7029 sprintf (buf, "bra %s", mri_control_stack->next);
7030 mri_assemble (buf);
7031 free (buf);
7032
7033 colon (mri_control_stack->bottom);
7034
7035 pop_mri_control ();
7036
7037 if (flag_mri)
7038 {
7039 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7040 ++input_line_pointer;
7041 }
7042
7043 demand_empty_rest_of_line ();
7044 }
7045 \f
7046 /* Parse a .cpu directive. */
7047
7048 static void
7049 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7050 {
7051 char saved_char;
7052 char *name;
7053
7054 if (initialized)
7055 {
7056 as_bad (_("already assembled instructions"));
7057 ignore_rest_of_line ();
7058 return;
7059 }
7060
7061 name = input_line_pointer;
7062 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7063 input_line_pointer++;
7064 saved_char = *input_line_pointer;
7065 *input_line_pointer = 0;
7066
7067 m68k_set_cpu (name, 1, 0);
7068
7069 *input_line_pointer = saved_char;
7070 demand_empty_rest_of_line ();
7071 return;
7072 }
7073
7074 /* Parse a .arch directive. */
7075
7076 static void
7077 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7078 {
7079 char saved_char;
7080 char *name;
7081
7082 if (initialized)
7083 {
7084 as_bad (_("already assembled instructions"));
7085 ignore_rest_of_line ();
7086 return;
7087 }
7088
7089 name = input_line_pointer;
7090 while (*input_line_pointer && *input_line_pointer != ','
7091 && !ISSPACE (*input_line_pointer))
7092 input_line_pointer++;
7093 saved_char = *input_line_pointer;
7094 *input_line_pointer = 0;
7095
7096 if (m68k_set_arch (name, 1, 0))
7097 {
7098 /* Scan extensions. */
7099 do
7100 {
7101 *input_line_pointer++ = saved_char;
7102 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7103 break;
7104 name = input_line_pointer;
7105 while (*input_line_pointer && *input_line_pointer != ','
7106 && !ISSPACE (*input_line_pointer))
7107 input_line_pointer++;
7108 saved_char = *input_line_pointer;
7109 *input_line_pointer = 0;
7110 }
7111 while (m68k_set_extension (name, 1, 0));
7112 }
7113
7114 *input_line_pointer = saved_char;
7115 demand_empty_rest_of_line ();
7116 return;
7117 }
7118 \f
7119 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7120 if none is found, the caller is responsible for emitting an error
7121 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7122 cpu name, if it begins with a '6' (possibly skipping an intervening
7123 'c'. We also allow a 'c' in the same place. if NEGATED is
7124 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7125 the option is indeed negated. */
7126
7127 static const struct m68k_cpu *
7128 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7129 int allow_m, int *negated)
7130 {
7131 /* allow negated value? */
7132 if (negated)
7133 {
7134 *negated = 0;
7135
7136 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7137 {
7138 arg += 3;
7139 *negated = 1;
7140 }
7141 }
7142
7143 /* Remove 'm' or 'mc' prefix from 68k variants. */
7144 if (allow_m)
7145 {
7146 if (arg[0] == 'm')
7147 {
7148 if (arg[1] == '6')
7149 arg += 1;
7150 else if (arg[1] == 'c' && arg[2] == '6')
7151 arg += 2;
7152 }
7153 }
7154 else if (arg[0] == 'c' && arg[1] == '6')
7155 arg += 1;
7156
7157 for (; table->name; table++)
7158 if (!strcmp (arg, table->name))
7159 {
7160 if (table->alias < -1 || table->alias > 1)
7161 as_bad (_("`%s' is deprecated, use `%s'"),
7162 table->name, table[table->alias < 0 ? 1 : -1].name);
7163 return table;
7164 }
7165 return 0;
7166 }
7167
7168 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7169
7170 static int
7171 m68k_set_cpu (char const *name, int allow_m, int silent)
7172 {
7173 const struct m68k_cpu *cpu;
7174
7175 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7176
7177 if (!cpu)
7178 {
7179 if (!silent)
7180 as_bad (_("cpu `%s' unrecognized"), name);
7181 return 0;
7182 }
7183
7184 if (selected_cpu && selected_cpu != cpu)
7185 {
7186 as_bad (_("already selected `%s' processor"),
7187 selected_cpu->name);
7188 return 0;
7189 }
7190 selected_cpu = cpu;
7191 return 1;
7192 }
7193
7194 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7195
7196 static int
7197 m68k_set_arch (char const *name, int allow_m, int silent)
7198 {
7199 const struct m68k_cpu *arch;
7200
7201 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7202
7203 if (!arch)
7204 {
7205 if (!silent)
7206 as_bad (_("architecture `%s' unrecognized"), name);
7207 return 0;
7208 }
7209
7210 if (selected_arch && selected_arch != arch)
7211 {
7212 as_bad (_("already selected `%s' architecture"),
7213 selected_arch->name);
7214 return 0;
7215 }
7216
7217 selected_arch = arch;
7218 return 1;
7219 }
7220
7221 /* Set the architecture extension, issuing errors if it is
7222 unrecognized, or invalid */
7223
7224 static int
7225 m68k_set_extension (char const *name, int allow_m, int silent)
7226 {
7227 int negated;
7228 const struct m68k_cpu *ext;
7229
7230 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7231
7232 if (!ext)
7233 {
7234 if (!silent)
7235 as_bad (_("extension `%s' unrecognized"), name);
7236 return 0;
7237 }
7238
7239 if (negated)
7240 not_current_architecture |= ext->arch;
7241 else
7242 current_architecture |= ext->arch;
7243 return 1;
7244 }
7245
7246 /* md_parse_option
7247 Invocation line includes a switch not recognized by the base assembler.
7248 */
7249
7250 #ifdef OBJ_ELF
7251 const char *md_shortopts = "lSA:m:kQ:V";
7252 #else
7253 const char *md_shortopts = "lSA:m:k";
7254 #endif
7255
7256 struct option md_longopts[] = {
7257 #define OPTION_PIC (OPTION_MD_BASE)
7258 {"pic", no_argument, NULL, OPTION_PIC},
7259 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7260 {"register-prefix-optional", no_argument, NULL,
7261 OPTION_REGISTER_PREFIX_OPTIONAL},
7262 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7263 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7264 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7265 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7266 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7267 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7268 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7269 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7270 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7271 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7272 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7273 {"pcrel", no_argument, NULL, OPTION_PCREL},
7274 {NULL, no_argument, NULL, 0}
7275 };
7276 size_t md_longopts_size = sizeof (md_longopts);
7277
7278 int
7279 md_parse_option (int c, char *arg)
7280 {
7281 switch (c)
7282 {
7283 case 'l': /* -l means keep external to 2 bit offset
7284 rather than 16 bit one. */
7285 flag_short_refs = 1;
7286 break;
7287
7288 case 'S': /* -S means that jbsr's always turn into
7289 jsr's. */
7290 flag_long_jumps = 1;
7291 break;
7292
7293 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7294 branches into absolute jumps. */
7295 flag_keep_pcrel = 1;
7296 break;
7297
7298 case OPTION_PIC:
7299 case 'k':
7300 flag_want_pic = 1;
7301 break; /* -pic, Position Independent Code. */
7302
7303 case OPTION_REGISTER_PREFIX_OPTIONAL:
7304 flag_reg_prefix_optional = 1;
7305 reg_prefix_optional_seen = 1;
7306 break;
7307
7308 /* -V: SVR4 argument to print version ID. */
7309 case 'V':
7310 print_version_id ();
7311 break;
7312
7313 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7314 should be emitted or not. FIXME: Not implemented. */
7315 case 'Q':
7316 break;
7317
7318 case OPTION_BITWISE_OR:
7319 {
7320 char *n, *t;
7321 const char *s;
7322
7323 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7324 t = n;
7325 for (s = m68k_comment_chars; *s != '\0'; s++)
7326 if (*s != '|')
7327 *t++ = *s;
7328 *t = '\0';
7329 m68k_comment_chars = n;
7330 }
7331 break;
7332
7333 case OPTION_BASE_SIZE_DEFAULT_16:
7334 m68k_index_width_default = SIZE_WORD;
7335 break;
7336
7337 case OPTION_BASE_SIZE_DEFAULT_32:
7338 m68k_index_width_default = SIZE_LONG;
7339 break;
7340
7341 case OPTION_DISP_SIZE_DEFAULT_16:
7342 m68k_rel32 = 0;
7343 m68k_rel32_from_cmdline = 1;
7344 break;
7345
7346 case OPTION_DISP_SIZE_DEFAULT_32:
7347 m68k_rel32 = 1;
7348 m68k_rel32_from_cmdline = 1;
7349 break;
7350
7351 case 'A':
7352 #if WARN_DEPRECATED
7353 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7354 arg, arg));
7355 #endif
7356 /* Intentional fall-through. */
7357 case 'm':
7358 if (!strncmp (arg, "arch=", 5))
7359 m68k_set_arch (arg + 5, 1, 0);
7360 else if (!strncmp (arg, "cpu=", 4))
7361 m68k_set_cpu (arg + 4, 1, 0);
7362 else if (m68k_set_extension (arg, 0, 1))
7363 ;
7364 else if (m68k_set_arch (arg, 0, 1))
7365 ;
7366 else if (m68k_set_cpu (arg, 0, 1))
7367 ;
7368 else
7369 return 0;
7370 break;
7371
7372 default:
7373 return 0;
7374 }
7375
7376 return 1;
7377 }
7378
7379 /* Setup tables from the selected arch and/or cpu */
7380
7381 static void
7382 m68k_init_arch (void)
7383 {
7384 if (not_current_architecture & current_architecture)
7385 {
7386 as_bad (_("architecture features both enabled and disabled"));
7387 not_current_architecture &= ~current_architecture;
7388 }
7389 if (selected_arch)
7390 {
7391 current_architecture |= selected_arch->arch;
7392 control_regs = selected_arch->control_regs;
7393 }
7394 else
7395 current_architecture |= selected_cpu->arch;
7396
7397 current_architecture &= ~not_current_architecture;
7398
7399 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7400 {
7401 /* Determine which float is really meant. */
7402 if (current_architecture & (m68k_mask & ~m68881))
7403 current_architecture ^= cfloat;
7404 else
7405 current_architecture ^= m68881;
7406 }
7407
7408 if (selected_cpu)
7409 {
7410 control_regs = selected_cpu->control_regs;
7411 if (current_architecture & ~selected_cpu->arch)
7412 {
7413 as_bad (_("selected processor does not have all features of selected architecture"));
7414 current_architecture
7415 = selected_cpu->arch & ~not_current_architecture;
7416 }
7417 }
7418
7419 if ((current_architecture & m68k_mask)
7420 && (current_architecture & ~m68k_mask))
7421 {
7422 as_bad (_ ("m68k and cf features both selected"));
7423 if (current_architecture & m68k_mask)
7424 current_architecture &= m68k_mask;
7425 else
7426 current_architecture &= ~m68k_mask;
7427 }
7428
7429 /* Permit m68881 specification with all cpus; those that can't work
7430 with a coprocessor could be doing emulation. */
7431 if (current_architecture & m68851)
7432 {
7433 if (current_architecture & m68040)
7434 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7435 }
7436 /* What other incompatibilities could we check for? */
7437
7438 if (cpu_of_arch (current_architecture) < m68020
7439 || arch_coldfire_p (current_architecture))
7440 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7441
7442 initialized = 1;
7443 }
7444
7445 void
7446 md_show_usage (FILE *stream)
7447 {
7448 const char *default_cpu = TARGET_CPU;
7449 int i;
7450 unsigned int default_arch;
7451
7452 /* Get the canonical name for the default target CPU. */
7453 if (*default_cpu == 'm')
7454 default_cpu++;
7455 for (i = 0; m68k_cpus[i].name; i++)
7456 {
7457 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7458 {
7459 default_arch = m68k_cpus[i].arch;
7460 while (m68k_cpus[i].alias > 0)
7461 i--;
7462 while (m68k_cpus[i].alias < 0)
7463 i++;
7464 default_cpu = m68k_cpus[i].name;
7465 }
7466 }
7467
7468 fprintf (stream, _("\
7469 -march=<arch> set architecture\n\
7470 -mcpu=<cpu> set cpu [default %s]\n\
7471 "), default_cpu);
7472 for (i = 0; m68k_extensions[i].name; i++)
7473 fprintf (stream, _("\
7474 -m[no-]%-16s enable/disable%s architecture extension\n\
7475 "), m68k_extensions[i].name,
7476 m68k_extensions[i].alias > 0 ? " ColdFire"
7477 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7478
7479 fprintf (stream, _("\
7480 -l use 1 word for refs to undefined symbols [default 2]\n\
7481 -pic, -k generate position independent code\n\
7482 -S turn jbsr into jsr\n\
7483 --pcrel never turn PC-relative branches into absolute jumps\n\
7484 --register-prefix-optional\n\
7485 recognize register names without prefix character\n\
7486 --bitwise-or do not treat `|' as a comment character\n\
7487 --base-size-default-16 base reg without size is 16 bits\n\
7488 --base-size-default-32 base reg without size is 32 bits (default)\n\
7489 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7490 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7491 "));
7492
7493 fprintf (stream, _("Architecture variants are: "));
7494 for (i = 0; m68k_archs[i].name; i++)
7495 {
7496 if (i)
7497 fprintf (stream, " | ");
7498 fprintf (stream, m68k_archs[i].name);
7499 }
7500 fprintf (stream, "\n");
7501
7502 fprintf (stream, _("Processor variants are: "));
7503 for (i = 0; m68k_cpus[i].name; i++)
7504 {
7505 if (i)
7506 fprintf (stream, " | ");
7507 fprintf (stream, m68k_cpus[i].name);
7508 }
7509 fprintf (stream, _("\n"));
7510 }
7511 \f
7512 #ifdef TEST2
7513
7514 /* TEST2: Test md_assemble() */
7515 /* Warning, this routine probably doesn't work anymore. */
7516 int
7517 main (void)
7518 {
7519 struct m68k_it the_ins;
7520 char buf[120];
7521 char *cp;
7522 int n;
7523
7524 m68k_ip_begin ();
7525 for (;;)
7526 {
7527 if (!gets (buf) || !*buf)
7528 break;
7529 if (buf[0] == '|' || buf[1] == '.')
7530 continue;
7531 for (cp = buf; *cp; cp++)
7532 if (*cp == '\t')
7533 *cp = ' ';
7534 if (is_label (buf))
7535 continue;
7536 memset (&the_ins, '\0', sizeof (the_ins));
7537 m68k_ip (&the_ins, buf);
7538 if (the_ins.error)
7539 {
7540 printf (_("Error %s in %s\n"), the_ins.error, buf);
7541 }
7542 else
7543 {
7544 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7545 for (n = 0; n < the_ins.numo; n++)
7546 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7547 printf (" ");
7548 print_the_insn (&the_ins.opcode[0], stdout);
7549 (void) putchar ('\n');
7550 }
7551 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7552 {
7553 if (the_ins.operands[n].error)
7554 {
7555 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7556 continue;
7557 }
7558 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7559 the_ins.operands[n].reg);
7560 if (the_ins.operands[n].b_const)
7561 printf ("Constant: '%.*s', ",
7562 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7563 the_ins.operands[n].b_const);
7564 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7565 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7566 if (the_ins.operands[n].b_iadd)
7567 printf ("Iadd: '%.*s',",
7568 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7569 the_ins.operands[n].b_iadd);
7570 putchar ('\n');
7571 }
7572 }
7573 m68k_ip_end ();
7574 return 0;
7575 }
7576
7577 int
7578 is_label (char *str)
7579 {
7580 while (*str == ' ')
7581 str++;
7582 while (*str && *str != ' ')
7583 str++;
7584 if (str[-1] == ':' || str[1] == '=')
7585 return 1;
7586 return 0;
7587 }
7588
7589 #endif
7590
7591 /* Possible states for relaxation:
7592
7593 0 0 branch offset byte (bra, etc)
7594 0 1 word
7595 0 2 long
7596
7597 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7598 1 1 word
7599 1 2 long
7600
7601 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7602 2 1 word-long
7603 2 2 long-word
7604 2 3 long-long
7605
7606 */
7607
7608 /* We have no need to default values of symbols. */
7609
7610 symbolS *
7611 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7612 {
7613 return 0;
7614 }
7615
7616 /* Round up a section size to the appropriate boundary. */
7617 valueT
7618 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7619 {
7620 #ifdef OBJ_AOUT
7621 /* For a.out, force the section size to be aligned. If we don't do
7622 this, BFD will align it for us, but it will not write out the
7623 final bytes of the section. This may be a bug in BFD, but it is
7624 easier to fix it here since that is how the other a.out targets
7625 work. */
7626 int align;
7627
7628 align = bfd_get_section_alignment (stdoutput, segment);
7629 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7630 #endif
7631
7632 return size;
7633 }
7634
7635 /* Exactly what point is a PC-relative offset relative TO?
7636 On the 68k, it is relative to the address of the first extension
7637 word. The difference between the addresses of the offset and the
7638 first extension word is stored in fx_pcrel_adjust. */
7639 long
7640 md_pcrel_from (fixS *fixP)
7641 {
7642 int adjust;
7643
7644 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7645 sign extend the value here. */
7646 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7647 if (adjust == 64)
7648 adjust = -1;
7649 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7650 }
7651
7652 #ifdef OBJ_ELF
7653 void
7654 m68k_elf_final_processing (void)
7655 {
7656 unsigned flags = 0;
7657
7658 if (arch_coldfire_fpu (current_architecture))
7659 flags |= EF_M68K_CFV4E;
7660 /* Set file-specific flags if this is a cpu32 processor. */
7661 if (cpu_of_arch (current_architecture) & cpu32)
7662 flags |= EF_M68K_CPU32;
7663 else if (cpu_of_arch (current_architecture) & fido_a)
7664 flags |= EF_M68K_FIDO;
7665 else if ((cpu_of_arch (current_architecture) & m68000up)
7666 && !(cpu_of_arch (current_architecture) & m68020up))
7667 flags |= EF_M68K_M68000;
7668
7669 if (current_architecture & mcfisa_a)
7670 {
7671 static const unsigned isa_features[][2] =
7672 {
7673 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7674 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7675 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7676 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7677 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7678 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7679 {0,0},
7680 };
7681 static const unsigned mac_features[][2] =
7682 {
7683 {EF_M68K_CF_MAC, mcfmac},
7684 {EF_M68K_CF_EMAC, mcfemac},
7685 {0,0},
7686 };
7687 unsigned ix;
7688 unsigned pattern;
7689
7690 pattern = (current_architecture
7691 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7692 for (ix = 0; isa_features[ix][1]; ix++)
7693 {
7694 if (pattern == isa_features[ix][1])
7695 {
7696 flags |= isa_features[ix][0];
7697 break;
7698 }
7699 }
7700 if (!isa_features[ix][1])
7701 {
7702 cf_bad:
7703 as_warn (_("Not a defined coldfire architecture"));
7704 }
7705 else
7706 {
7707 if (current_architecture & cfloat)
7708 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7709
7710 pattern = current_architecture & (mcfmac|mcfemac);
7711 if (pattern)
7712 {
7713 for (ix = 0; mac_features[ix][1]; ix++)
7714 {
7715 if (pattern == mac_features[ix][1])
7716 {
7717 flags |= mac_features[ix][0];
7718 break;
7719 }
7720 }
7721 if (!mac_features[ix][1])
7722 goto cf_bad;
7723 }
7724 }
7725 }
7726 elf_elfheader (stdoutput)->e_flags |= flags;
7727 }
7728 #endif
7729
7730 int
7731 tc_m68k_regname_to_dw2regnum (char *regname)
7732 {
7733 unsigned int regnum;
7734 static const char *const regnames[] =
7735 {
7736 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7737 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7738 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7739 "pc"
7740 };
7741
7742 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7743 if (strcmp (regname, regnames[regnum]) == 0)
7744 return regnum;
7745
7746 return -1;
7747 }
7748
7749 void
7750 tc_m68k_frame_initial_instructions (void)
7751 {
7752 static int sp_regno = -1;
7753
7754 if (sp_regno < 0)
7755 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7756
7757 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7758 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7759 }
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