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[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
181 0
182 };
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
185 0
186 };
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
189 0
190 };
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
193 0
194 };
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
197 0
198 };
199 static const enum m68k_register mcf52223_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52235_ctrl[] = {
204 VBR, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf5225_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5235_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5249_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
217 0
218 };
219 static const enum m68k_register mcf5250_ctrl[] = {
220 VBR,
221 0
222 };
223 static const enum m68k_register mcf5253_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
225 0
226 };
227 static const enum m68k_register mcf5271_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
229 0
230 };
231 static const enum m68k_register mcf5272_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
233 0
234 };
235 static const enum m68k_register mcf5275_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
237 0
238 };
239 static const enum m68k_register mcf5282_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5307_ctrl[] = {
244 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
245 0
246 };
247 static const enum m68k_register mcf5329_ctrl[] = {
248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
249 0
250 };
251 static const enum m68k_register mcf5373_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcfv4e_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
258 MBAR, SECMBAR,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
264 /* Legacy names */
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
269 0
270 };
271 static const enum m68k_register mcf54455_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
273 VBR, PC, RAMBAR1, MBAR,
274 /* Legacy names */
275 TC /* ASID */, BUSCR /* MMUBAR */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
278 0
279 };
280 static const enum m68k_register mcf5475_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
283 /* Legacy names */
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
287 0
288 };
289 static const enum m68k_register mcf5485_ctrl[] = {
290 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
291 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
292 /* Legacy names */
293 TC /* ASID */, BUSCR /* MMUBAR */,
294 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
295 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
296 0
297 };
298 static const enum m68k_register fido_ctrl[] = {
299 SFC, DFC, USP, VBR, CAC, MBB,
300 0
301 };
302 #define cpu32_ctrl m68010_ctrl
303
304 static const enum m68k_register *control_regs;
305
306 /* Internal form of a 68020 instruction. */
307 struct m68k_it
308 {
309 const char *error;
310 const char *args; /* List of opcode info. */
311 int numargs;
312
313 int numo; /* Number of shorts in opcode. */
314 short opcode[11];
315
316 struct m68k_op operands[6];
317
318 int nexp; /* Number of exprs in use. */
319 struct m68k_exp exprs[4];
320
321 int nfrag; /* Number of frags we have to produce. */
322 struct
323 {
324 int fragoff; /* Where in the current opcode the frag ends. */
325 symbolS *fadd;
326 offsetT foff;
327 int fragty;
328 }
329 fragb[4];
330
331 int nrel; /* Num of reloc strucs in use. */
332 struct
333 {
334 int n;
335 expressionS exp;
336 char wid;
337 char pcrel;
338 /* In a pc relative address the difference between the address
339 of the offset and the address that the offset is relative
340 to. This depends on the addressing mode. Basically this
341 is the value to put in the offset field to address the
342 first byte of the offset, without regarding the special
343 significance of some values (in the branch instruction, for
344 example). */
345 int pcrel_fix;
346 #ifdef OBJ_ELF
347 /* Whether this expression needs special pic relocation, and if
348 so, which. */
349 enum pic_relocation pic_reloc;
350 #endif
351 }
352 reloc[5]; /* Five is enough??? */
353 };
354
355 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
356 #define float_of_arch(x) ((x) & mfloat)
357 #define mmu_of_arch(x) ((x) & mmmu)
358 #define arch_coldfire_p(x) ((x) & mcfisa_a)
359 #define arch_coldfire_fpu(x) ((x) & cfloat)
360
361 /* Macros for determining if cpu supports a specific addressing mode. */
362 #define HAVE_LONG_DISP(x) \
363 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
364 #define HAVE_LONG_CALL(x) \
365 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
366 #define HAVE_LONG_COND(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368 #define HAVE_LONG_BRANCH(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
370
371 static struct m68k_it the_ins; /* The instruction being assembled. */
372
373 #define op(ex) ((ex)->exp.X_op)
374 #define adds(ex) ((ex)->exp.X_add_symbol)
375 #define subs(ex) ((ex)->exp.X_op_symbol)
376 #define offs(ex) ((ex)->exp.X_add_number)
377
378 /* Macros for adding things to the m68k_it struct. */
379 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
380
381 /* Like addword, but goes BEFORE general operands. */
382
383 static void
384 insop (int w, const struct m68k_incant *opcode)
385 {
386 int z;
387 for (z = the_ins.numo; z > opcode->m_codenum; --z)
388 the_ins.opcode[z] = the_ins.opcode[z - 1];
389 for (z = 0; z < the_ins.nrel; z++)
390 the_ins.reloc[z].n += 2;
391 for (z = 0; z < the_ins.nfrag; z++)
392 the_ins.fragb[z].fragoff++;
393 the_ins.opcode[opcode->m_codenum] = w;
394 the_ins.numo++;
395 }
396
397 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
398 Blecch. */
399 static void
400 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
401 {
402 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
403 ? the_ins.numo * 2 - 1
404 : (width == 'b'
405 ? the_ins.numo * 2 + 1
406 : the_ins.numo * 2));
407 the_ins.reloc[the_ins.nrel].exp = exp->exp;
408 the_ins.reloc[the_ins.nrel].wid = width;
409 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
410 #ifdef OBJ_ELF
411 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
412 #endif
413 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
414 }
415
416 /* Cause an extra frag to be generated here, inserting up to 10 bytes
417 (that value is chosen in the frag_var call in md_assemble). TYPE
418 is the subtype of the frag to be generated; its primary type is
419 rs_machine_dependent.
420
421 The TYPE parameter is also used by md_convert_frag_1 and
422 md_estimate_size_before_relax. The appropriate type of fixup will
423 be emitted by md_convert_frag_1.
424
425 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
426 static void
427 add_frag (symbolS *add, offsetT off, int type)
428 {
429 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
430 the_ins.fragb[the_ins.nfrag].fadd = add;
431 the_ins.fragb[the_ins.nfrag].foff = off;
432 the_ins.fragb[the_ins.nfrag++].fragty = type;
433 }
434
435 #define isvar(ex) \
436 (op (ex) != O_constant && op (ex) != O_big)
437
438 static char *crack_operand (char *str, struct m68k_op *opP);
439 static int get_num (struct m68k_exp *exp, int ok);
440 static int reverse_16_bits (int in);
441 static int reverse_8_bits (int in);
442 static void install_gen_operand (int mode, int val);
443 static void install_operand (int mode, int val);
444 static void s_bss (int);
445 static void s_data1 (int);
446 static void s_data2 (int);
447 static void s_even (int);
448 static void s_proc (int);
449 static void s_chip (int);
450 static void s_fopt (int);
451 static void s_opt (int);
452 static void s_reg (int);
453 static void s_restore (int);
454 static void s_save (int);
455 static void s_mri_if (int);
456 static void s_mri_else (int);
457 static void s_mri_endi (int);
458 static void s_mri_break (int);
459 static void s_mri_next (int);
460 static void s_mri_for (int);
461 static void s_mri_endf (int);
462 static void s_mri_repeat (int);
463 static void s_mri_until (int);
464 static void s_mri_while (int);
465 static void s_mri_endw (int);
466 static void s_m68k_cpu (int);
467 static void s_m68k_arch (int);
468
469 struct m68k_cpu
470 {
471 unsigned long arch; /* Architecture features. */
472 const enum m68k_register *control_regs; /* Control regs on chip */
473 const char *name; /* Name */
474 int alias; /* Alias for a cannonical name. If 1, then
475 succeeds canonical name, if -1 then
476 succeeds canonical name, if <-1 ||>1 this is a
477 deprecated name, and the next/previous name
478 should be used. */
479 };
480
481 /* We hold flags for features explicitly enabled and explicitly
482 disabled. */
483 static int current_architecture;
484 static int not_current_architecture;
485 static const struct m68k_cpu *selected_arch;
486 static const struct m68k_cpu *selected_cpu;
487 static int initialized;
488
489 /* Architecture models. */
490 static const struct m68k_cpu m68k_archs[] =
491 {
492 {m68000, m68000_ctrl, "68000", 0},
493 {m68010, m68010_ctrl, "68010", 0},
494 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
495 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
496 {m68040, m68040_ctrl, "68040", 0},
497 {m68060, m68060_ctrl, "68060", 0},
498 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
499 {fido_a, fido_ctrl, "fidoa", 0},
500 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
501 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
502 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
503 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
504 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
505 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
506 {0,0,NULL, 0}
507 };
508
509 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
510 for either. */
511 static const struct m68k_cpu m68k_extensions[] =
512 {
513 {m68851, NULL, "68851", -1},
514 {m68881, NULL, "68881", -1},
515 {m68881, NULL, "68882", -1},
516
517 {cfloat|m68881, NULL, "float", 0},
518
519 {mcfhwdiv, NULL, "div", 1},
520 {mcfusp, NULL, "usp", 1},
521 {mcfmac, NULL, "mac", 1},
522 {mcfemac, NULL, "emac", 1},
523
524 {0,NULL,NULL, 0}
525 };
526
527 /* Processor list */
528 static const struct m68k_cpu m68k_cpus[] =
529 {
530 {m68000, m68000_ctrl, "68000", 0},
531 {m68000, m68000_ctrl, "68ec000", 1},
532 {m68000, m68000_ctrl, "68hc000", 1},
533 {m68000, m68000_ctrl, "68hc001", 1},
534 {m68000, m68000_ctrl, "68008", 1},
535 {m68000, m68000_ctrl, "68302", 1},
536 {m68000, m68000_ctrl, "68306", 1},
537 {m68000, m68000_ctrl, "68307", 1},
538 {m68000, m68000_ctrl, "68322", 1},
539 {m68000, m68000_ctrl, "68356", 1},
540 {m68010, m68010_ctrl, "68010", 0},
541 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
542 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
543 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
544 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
545 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
546 {m68040, m68040_ctrl, "68040", 0},
547 {m68040, m68040_ctrl, "68ec040", 1},
548 {m68060, m68060_ctrl, "68060", 0},
549 {m68060, m68060_ctrl, "68ec060", 1},
550
551 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
552 {cpu32|m68881, cpu32_ctrl, "68330", 1},
553 {cpu32|m68881, cpu32_ctrl, "68331", 1},
554 {cpu32|m68881, cpu32_ctrl, "68332", 1},
555 {cpu32|m68881, cpu32_ctrl, "68333", 1},
556 {cpu32|m68881, cpu32_ctrl, "68334", 1},
557 {cpu32|m68881, cpu32_ctrl, "68336", 1},
558 {cpu32|m68881, cpu32_ctrl, "68340", 1},
559 {cpu32|m68881, cpu32_ctrl, "68341", 1},
560 {cpu32|m68881, cpu32_ctrl, "68349", 1},
561 {cpu32|m68881, cpu32_ctrl, "68360", 1},
562
563 {mcfisa_a, mcf_ctrl, "5200", 0},
564 {mcfisa_a, mcf_ctrl, "5202", 1},
565 {mcfisa_a, mcf_ctrl, "5204", 1},
566 {mcfisa_a, mcf5206_ctrl, "5206", 1},
567
568 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
569
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
572
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
574 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
579
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
583
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
586
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
591
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
594
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
600
601 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
602 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
603 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
604
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
607
608 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
612
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
617
618 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
619
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
628
629 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
630
631 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
632 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
633 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
634 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
635 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
636 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
637
638 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
639 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
640 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
641 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
642 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
643 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
645
646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
647 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
648 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
649 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
651 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
652 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
653
654 {fido_a, fido_ctrl, "fidoa", 0},
655 {fido_a, fido_ctrl, "fido", 1},
656
657 {0,NULL,NULL, 0}
658 };
659
660 static const struct m68k_cpu *m68k_lookup_cpu
661 (const char *, const struct m68k_cpu *, int, int *);
662 static int m68k_set_arch (const char *, int, int);
663 static int m68k_set_cpu (const char *, int, int);
664 static int m68k_set_extension (const char *, int, int);
665 static void m68k_init_arch (void);
666
667 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
668 architecture and we have a lot of relaxation modes. */
669
670 /* Macros used in the relaxation code. */
671 #define TAB(x,y) (((x) << 2) + (y))
672 #define TABTYPE(x) ((x) >> 2)
673
674 /* Relaxation states. */
675 #define BYTE 0
676 #define SHORT 1
677 #define LONG 2
678 #define SZ_UNDEF 3
679
680 /* Here are all the relaxation modes we support. First we can relax ordinary
681 branches. On 68020 and higher and on CPU32 all branch instructions take
682 three forms, so on these CPUs all branches always remain as such. When we
683 have to expand to the LONG form on a 68000, though, we substitute an
684 absolute jump instead. This is a direct replacement for unconditional
685 branches and a branch over a jump for conditional branches. However, if the
686 user requires PIC and disables this with --pcrel, we can only relax between
687 BYTE and SHORT forms, punting if that isn't enough. This gives us four
688 different relaxation modes for branches: */
689
690 #define BRANCHBWL 0 /* Branch byte, word, or long. */
691 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
692 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
693 #define BRANCHBW 3 /* Branch byte or word. */
694
695 /* We also relax coprocessor branches and DBcc's. All CPUs that support
696 coprocessor branches support them in word and long forms, so we have only
697 one relaxation mode for them. DBcc's are word only on all CPUs. We can
698 relax them to the LONG form with a branch-around sequence. This sequence
699 can use a long branch (if available) or an absolute jump (if acceptable).
700 This gives us two relaxation modes. If long branches are not available and
701 absolute jumps are not acceptable, we don't relax DBcc's. */
702
703 #define FBRANCH 4 /* Coprocessor branch. */
704 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
705 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
706
707 /* That's all for instruction relaxation. However, we also relax PC-relative
708 operands. Specifically, we have three operand relaxation modes. On the
709 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
710 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
711 two. Also PC+displacement+index operands in their simple form (with a non-
712 suppressed index without memory indirection) are supported on all CPUs, but
713 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
714 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
715 form of the PC+displacement+index operand. Finally, some absolute operands
716 can be relaxed down to 16-bit PC-relative. */
717
718 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
719 #define PCINDEX 8 /* PC + displacement + index. */
720 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
721
722 /* Note that calls to frag_var need to specify the maximum expansion
723 needed; this is currently 10 bytes for DBCC. */
724
725 /* The fields are:
726 How far Forward this mode will reach:
727 How far Backward this mode will reach:
728 How many bytes this mode will add to the size of the frag
729 Which mode to go to if the offset won't fit in this one
730
731 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
732 relax_typeS md_relax_table[] =
733 {
734 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
735 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
736 { 0, 0, 4, 0 },
737 { 1, 1, 0, 0 },
738
739 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
740 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
741 { 0, 0, 4, 0 },
742 { 1, 1, 0, 0 },
743
744 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
745 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
746 { 0, 0, 6, 0 },
747 { 1, 1, 0, 0 },
748
749 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
750 { 0, 0, 2, 0 },
751 { 1, 1, 0, 0 },
752 { 1, 1, 0, 0 },
753
754 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
755 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
756 { 0, 0, 4, 0 },
757 { 1, 1, 0, 0 },
758
759 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
760 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
761 { 0, 0, 10, 0 },
762 { 1, 1, 0, 0 },
763
764 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
765 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
766 { 0, 0, 10, 0 },
767 { 1, 1, 0, 0 },
768
769 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
771 { 0, 0, 6, 0 },
772 { 1, 1, 0, 0 },
773
774 { 125, -130, 0, TAB (PCINDEX, SHORT) },
775 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
776 { 0, 0, 4, 0 },
777 { 1, 1, 0, 0 },
778
779 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
781 { 0, 0, 4, 0 },
782 { 1, 1, 0, 0 },
783 };
784
785 /* These are the machine dependent pseudo-ops. These are included so
786 the assembler can work on the output from the SUN C compiler, which
787 generates these. */
788
789 /* This table describes all the machine specific pseudo-ops the assembler
790 has to support. The fields are:
791 pseudo-op name without dot
792 function to call to execute this pseudo-op
793 Integer arg to pass to the function. */
794 const pseudo_typeS md_pseudo_table[] =
795 {
796 {"data1", s_data1, 0},
797 {"data2", s_data2, 0},
798 {"bss", s_bss, 0},
799 {"even", s_even, 0},
800 {"skip", s_space, 0},
801 {"proc", s_proc, 0},
802 #if defined (TE_SUN3) || defined (OBJ_ELF)
803 {"align", s_align_bytes, 0},
804 #endif
805 #ifdef OBJ_ELF
806 {"swbeg", s_ignore, 0},
807 #endif
808 {"extend", float_cons, 'x'},
809 {"ldouble", float_cons, 'x'},
810
811 {"arch", s_m68k_arch, 0},
812 {"cpu", s_m68k_cpu, 0},
813
814 /* The following pseudo-ops are supported for MRI compatibility. */
815 {"chip", s_chip, 0},
816 {"comline", s_space, 1},
817 {"fopt", s_fopt, 0},
818 {"mask2", s_ignore, 0},
819 {"opt", s_opt, 0},
820 {"reg", s_reg, 0},
821 {"restore", s_restore, 0},
822 {"save", s_save, 0},
823
824 {"if", s_mri_if, 0},
825 {"if.b", s_mri_if, 'b'},
826 {"if.w", s_mri_if, 'w'},
827 {"if.l", s_mri_if, 'l'},
828 {"else", s_mri_else, 0},
829 {"else.s", s_mri_else, 's'},
830 {"else.l", s_mri_else, 'l'},
831 {"endi", s_mri_endi, 0},
832 {"break", s_mri_break, 0},
833 {"break.s", s_mri_break, 's'},
834 {"break.l", s_mri_break, 'l'},
835 {"next", s_mri_next, 0},
836 {"next.s", s_mri_next, 's'},
837 {"next.l", s_mri_next, 'l'},
838 {"for", s_mri_for, 0},
839 {"for.b", s_mri_for, 'b'},
840 {"for.w", s_mri_for, 'w'},
841 {"for.l", s_mri_for, 'l'},
842 {"endf", s_mri_endf, 0},
843 {"repeat", s_mri_repeat, 0},
844 {"until", s_mri_until, 0},
845 {"until.b", s_mri_until, 'b'},
846 {"until.w", s_mri_until, 'w'},
847 {"until.l", s_mri_until, 'l'},
848 {"while", s_mri_while, 0},
849 {"while.b", s_mri_while, 'b'},
850 {"while.w", s_mri_while, 'w'},
851 {"while.l", s_mri_while, 'l'},
852 {"endw", s_mri_endw, 0},
853
854 {0, 0, 0}
855 };
856
857 /* The mote pseudo ops are put into the opcode table, since they
858 don't start with a . they look like opcodes to gas. */
859
860 const pseudo_typeS mote_pseudo_table[] =
861 {
862
863 {"dcl", cons, 4},
864 {"dc", cons, 2},
865 {"dcw", cons, 2},
866 {"dcb", cons, 1},
867
868 {"dsl", s_space, 4},
869 {"ds", s_space, 2},
870 {"dsw", s_space, 2},
871 {"dsb", s_space, 1},
872
873 {"xdef", s_globl, 0},
874 #ifdef OBJ_ELF
875 {"align", s_align_bytes, 0},
876 #else
877 {"align", s_align_ptwo, 0},
878 #endif
879 #ifdef M68KCOFF
880 {"sect", obj_coff_section, 0},
881 {"section", obj_coff_section, 0},
882 #endif
883 {0, 0, 0}
884 };
885
886 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
887 gives identical results to a 32-bit host. */
888 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
889 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
890
891 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
892 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
893 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
894 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
895
896 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
897 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
898 #define islong(x) (1)
899
900 static char notend_table[256];
901 static char alt_notend_table[256];
902 #define notend(s) \
903 (! (notend_table[(unsigned char) *s] \
904 || (*s == ':' \
905 && alt_notend_table[(unsigned char) s[1]])))
906
907 #ifdef OBJ_ELF
908
909 /* Return zero if the reference to SYMBOL from within the same segment may
910 be relaxed. */
911
912 /* On an ELF system, we can't relax an externally visible symbol,
913 because it may be overridden by a shared library. However, if
914 TARGET_OS is "elf", then we presume that we are assembling for an
915 embedded system, in which case we don't have to worry about shared
916 libraries, and we can relax any external sym. */
917
918 #define relaxable_symbol(symbol) \
919 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
920 || S_IS_WEAK (symbol)))
921
922 /* Compute the relocation code for a fixup of SIZE bytes, using pc
923 relative relocation if PCREL is non-zero. PIC says whether a special
924 pic relocation was requested. */
925
926 static bfd_reloc_code_real_type
927 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
928 {
929 switch (pic)
930 {
931 case pic_got_pcrel:
932 switch (size)
933 {
934 case 1:
935 return BFD_RELOC_8_GOT_PCREL;
936 case 2:
937 return BFD_RELOC_16_GOT_PCREL;
938 case 4:
939 return BFD_RELOC_32_GOT_PCREL;
940 }
941 break;
942
943 case pic_got_off:
944 switch (size)
945 {
946 case 1:
947 return BFD_RELOC_8_GOTOFF;
948 case 2:
949 return BFD_RELOC_16_GOTOFF;
950 case 4:
951 return BFD_RELOC_32_GOTOFF;
952 }
953 break;
954
955 case pic_plt_pcrel:
956 switch (size)
957 {
958 case 1:
959 return BFD_RELOC_8_PLT_PCREL;
960 case 2:
961 return BFD_RELOC_16_PLT_PCREL;
962 case 4:
963 return BFD_RELOC_32_PLT_PCREL;
964 }
965 break;
966
967 case pic_plt_off:
968 switch (size)
969 {
970 case 1:
971 return BFD_RELOC_8_PLTOFF;
972 case 2:
973 return BFD_RELOC_16_PLTOFF;
974 case 4:
975 return BFD_RELOC_32_PLTOFF;
976 }
977 break;
978
979 case pic_none:
980 if (pcrel)
981 {
982 switch (size)
983 {
984 case 1:
985 return BFD_RELOC_8_PCREL;
986 case 2:
987 return BFD_RELOC_16_PCREL;
988 case 4:
989 return BFD_RELOC_32_PCREL;
990 }
991 }
992 else
993 {
994 switch (size)
995 {
996 case 1:
997 return BFD_RELOC_8;
998 case 2:
999 return BFD_RELOC_16;
1000 case 4:
1001 return BFD_RELOC_32;
1002 }
1003 }
1004 }
1005
1006 if (pcrel)
1007 {
1008 if (pic == pic_none)
1009 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1010 else
1011 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1012 }
1013 else
1014 {
1015 if (pic == pic_none)
1016 as_bad (_("Can not do %d byte relocation"), size);
1017 else
1018 as_bad (_("Can not do %d byte pic relocation"), size);
1019 }
1020
1021 return BFD_RELOC_NONE;
1022 }
1023
1024 /* Here we decide which fixups can be adjusted to make them relative
1025 to the beginning of the section instead of the symbol. Basically
1026 we need to make sure that the dynamic relocations are done
1027 correctly, so in some cases we force the original symbol to be
1028 used. */
1029 int
1030 tc_m68k_fix_adjustable (fixS *fixP)
1031 {
1032 /* Adjust_reloc_syms doesn't know about the GOT. */
1033 switch (fixP->fx_r_type)
1034 {
1035 case BFD_RELOC_8_GOT_PCREL:
1036 case BFD_RELOC_16_GOT_PCREL:
1037 case BFD_RELOC_32_GOT_PCREL:
1038 case BFD_RELOC_8_GOTOFF:
1039 case BFD_RELOC_16_GOTOFF:
1040 case BFD_RELOC_32_GOTOFF:
1041 case BFD_RELOC_8_PLT_PCREL:
1042 case BFD_RELOC_16_PLT_PCREL:
1043 case BFD_RELOC_32_PLT_PCREL:
1044 case BFD_RELOC_8_PLTOFF:
1045 case BFD_RELOC_16_PLTOFF:
1046 case BFD_RELOC_32_PLTOFF:
1047 return 0;
1048
1049 case BFD_RELOC_VTABLE_INHERIT:
1050 case BFD_RELOC_VTABLE_ENTRY:
1051 return 0;
1052
1053 default:
1054 return 1;
1055 }
1056 }
1057
1058 #else /* !OBJ_ELF */
1059
1060 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1061
1062 /* PR gas/3041 Weak symbols are not relaxable
1063 because they must be treated as extern. */
1064 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1065
1066 #endif /* OBJ_ELF */
1067
1068 arelent *
1069 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1070 {
1071 arelent *reloc;
1072 bfd_reloc_code_real_type code;
1073
1074 /* If the tcbit is set, then this was a fixup of a negative value
1075 that was never resolved. We do not have a reloc to handle this,
1076 so just return. We assume that other code will have detected this
1077 situation and produced a helpful error message, so we just tell the
1078 user that the reloc cannot be produced. */
1079 if (fixp->fx_tcbit)
1080 {
1081 if (fixp->fx_addsy)
1082 as_bad_where (fixp->fx_file, fixp->fx_line,
1083 _("Unable to produce reloc against symbol '%s'"),
1084 S_GET_NAME (fixp->fx_addsy));
1085 return NULL;
1086 }
1087
1088 if (fixp->fx_r_type != BFD_RELOC_NONE)
1089 {
1090 code = fixp->fx_r_type;
1091
1092 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1093 that fixup_segment converted a non-PC relative reloc into a
1094 PC relative reloc. In such a case, we need to convert the
1095 reloc code. */
1096 if (fixp->fx_pcrel)
1097 {
1098 switch (code)
1099 {
1100 case BFD_RELOC_8:
1101 code = BFD_RELOC_8_PCREL;
1102 break;
1103 case BFD_RELOC_16:
1104 code = BFD_RELOC_16_PCREL;
1105 break;
1106 case BFD_RELOC_32:
1107 code = BFD_RELOC_32_PCREL;
1108 break;
1109 case BFD_RELOC_8_PCREL:
1110 case BFD_RELOC_16_PCREL:
1111 case BFD_RELOC_32_PCREL:
1112 case BFD_RELOC_8_GOT_PCREL:
1113 case BFD_RELOC_16_GOT_PCREL:
1114 case BFD_RELOC_32_GOT_PCREL:
1115 case BFD_RELOC_8_GOTOFF:
1116 case BFD_RELOC_16_GOTOFF:
1117 case BFD_RELOC_32_GOTOFF:
1118 case BFD_RELOC_8_PLT_PCREL:
1119 case BFD_RELOC_16_PLT_PCREL:
1120 case BFD_RELOC_32_PLT_PCREL:
1121 case BFD_RELOC_8_PLTOFF:
1122 case BFD_RELOC_16_PLTOFF:
1123 case BFD_RELOC_32_PLTOFF:
1124 break;
1125 default:
1126 as_bad_where (fixp->fx_file, fixp->fx_line,
1127 _("Cannot make %s relocation PC relative"),
1128 bfd_get_reloc_code_name (code));
1129 }
1130 }
1131 }
1132 else
1133 {
1134 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1135 switch (F (fixp->fx_size, fixp->fx_pcrel))
1136 {
1137 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1138 MAP (1, 0, BFD_RELOC_8);
1139 MAP (2, 0, BFD_RELOC_16);
1140 MAP (4, 0, BFD_RELOC_32);
1141 MAP (1, 1, BFD_RELOC_8_PCREL);
1142 MAP (2, 1, BFD_RELOC_16_PCREL);
1143 MAP (4, 1, BFD_RELOC_32_PCREL);
1144 default:
1145 abort ();
1146 }
1147 }
1148 #undef F
1149 #undef MAP
1150
1151 reloc = (arelent *) xmalloc (sizeof (arelent));
1152 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1153 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1154 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1155 #ifndef OBJ_ELF
1156 if (fixp->fx_pcrel)
1157 reloc->addend = fixp->fx_addnumber;
1158 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1159 && fixp->fx_addsy
1160 && S_IS_WEAK (fixp->fx_addsy)
1161 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1162 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1163 to put a zero value into frags referencing a weak symbol. */
1164 reloc->addend = - S_GET_VALUE (fixp->fx_addsy);
1165 else
1166 reloc->addend = 0;
1167 #else
1168 if (!fixp->fx_pcrel)
1169 reloc->addend = fixp->fx_addnumber;
1170 else
1171 reloc->addend = (section->vma
1172 /* Explicit sign extension in case char is
1173 unsigned. */
1174 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1175 + fixp->fx_addnumber
1176 + md_pcrel_from (fixp));
1177 #endif
1178
1179 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1180 assert (reloc->howto != 0);
1181
1182 return reloc;
1183 }
1184
1185 /* Handle of the OPCODE hash table. NULL means any use before
1186 m68k_ip_begin() will crash. */
1187 static struct hash_control *op_hash;
1188 \f
1189 /* Assemble an m68k instruction. */
1190
1191 static void
1192 m68k_ip (char *instring)
1193 {
1194 register char *p;
1195 register struct m68k_op *opP;
1196 register const struct m68k_incant *opcode;
1197 register const char *s;
1198 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1199 char *pdot, *pdotmove;
1200 enum m68k_size siz1, siz2;
1201 char c;
1202 int losing;
1203 int opsfound;
1204 struct m68k_op operands_backup[6];
1205 LITTLENUM_TYPE words[6];
1206 LITTLENUM_TYPE *wordp;
1207 unsigned long ok_arch = 0;
1208
1209 if (*instring == ' ')
1210 instring++; /* Skip leading whitespace. */
1211
1212 /* Scan up to end of operation-code, which MUST end in end-of-string
1213 or exactly 1 space. */
1214 pdot = 0;
1215 for (p = instring; *p != '\0'; p++)
1216 {
1217 if (*p == ' ')
1218 break;
1219 if (*p == '.')
1220 pdot = p;
1221 }
1222
1223 if (p == instring)
1224 {
1225 the_ins.error = _("No operator");
1226 return;
1227 }
1228
1229 /* p now points to the end of the opcode name, probably whitespace.
1230 Make sure the name is null terminated by clobbering the
1231 whitespace, look it up in the hash table, then fix it back.
1232 Remove a dot, first, since the opcode tables have none. */
1233 if (pdot != NULL)
1234 {
1235 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1236 *pdotmove = pdotmove[1];
1237 p--;
1238 }
1239
1240 c = *p;
1241 *p = '\0';
1242 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1243 *p = c;
1244
1245 if (pdot != NULL)
1246 {
1247 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1248 *pdotmove = pdotmove[-1];
1249 *pdot = '.';
1250 ++p;
1251 }
1252
1253 if (opcode == NULL)
1254 {
1255 the_ins.error = _("Unknown operator");
1256 return;
1257 }
1258
1259 /* Found a legitimate opcode, start matching operands. */
1260 while (*p == ' ')
1261 ++p;
1262
1263 if (opcode->m_operands == 0)
1264 {
1265 char *old = input_line_pointer;
1266 *old = '\n';
1267 input_line_pointer = p;
1268 /* Ahh - it's a motorola style psuedo op. */
1269 mote_pseudo_table[opcode->m_opnum].poc_handler
1270 (mote_pseudo_table[opcode->m_opnum].poc_val);
1271 input_line_pointer = old;
1272 *old = 0;
1273
1274 return;
1275 }
1276
1277 if (flag_mri && opcode->m_opnum == 0)
1278 {
1279 /* In MRI mode, random garbage is allowed after an instruction
1280 which accepts no operands. */
1281 the_ins.args = opcode->m_operands;
1282 the_ins.numargs = opcode->m_opnum;
1283 the_ins.numo = opcode->m_codenum;
1284 the_ins.opcode[0] = getone (opcode);
1285 the_ins.opcode[1] = gettwo (opcode);
1286 return;
1287 }
1288
1289 for (opP = &the_ins.operands[0]; *p; opP++)
1290 {
1291 p = crack_operand (p, opP);
1292
1293 if (opP->error)
1294 {
1295 the_ins.error = opP->error;
1296 return;
1297 }
1298 }
1299
1300 opsfound = opP - &the_ins.operands[0];
1301
1302 /* This ugly hack is to support the floating pt opcodes in their
1303 standard form. Essentially, we fake a first enty of type COP#1 */
1304 if (opcode->m_operands[0] == 'I')
1305 {
1306 int n;
1307
1308 for (n = opsfound; n > 0; --n)
1309 the_ins.operands[n] = the_ins.operands[n - 1];
1310
1311 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1312 the_ins.operands[0].mode = CONTROL;
1313 the_ins.operands[0].reg = m68k_float_copnum;
1314 opsfound++;
1315 }
1316
1317 /* We've got the operands. Find an opcode that'll accept them. */
1318 for (losing = 0;;)
1319 {
1320 /* If we didn't get the right number of ops, or we have no
1321 common model with this pattern then reject this pattern. */
1322
1323 ok_arch |= opcode->m_arch;
1324 if (opsfound != opcode->m_opnum
1325 || ((opcode->m_arch & current_architecture) == 0))
1326 ++losing;
1327 else
1328 {
1329 int i;
1330
1331 /* Make a copy of the operands of this insn so that
1332 we can modify them safely, should we want to. */
1333 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1334 for (i = 0; i < opsfound; i++)
1335 operands_backup[i] = the_ins.operands[i];
1336
1337 for (s = opcode->m_operands, opP = &operands_backup[0];
1338 *s && !losing;
1339 s += 2, opP++)
1340 {
1341 /* Warning: this switch is huge! */
1342 /* I've tried to organize the cases into this order:
1343 non-alpha first, then alpha by letter. Lower-case
1344 goes directly before uppercase counterpart. */
1345 /* Code with multiple case ...: gets sorted by the lowest
1346 case ... it belongs to. I hope this makes sense. */
1347 switch (*s)
1348 {
1349 case '!':
1350 switch (opP->mode)
1351 {
1352 case IMMED:
1353 case DREG:
1354 case AREG:
1355 case FPREG:
1356 case CONTROL:
1357 case AINC:
1358 case ADEC:
1359 case REGLST:
1360 losing++;
1361 break;
1362 default:
1363 break;
1364 }
1365 break;
1366
1367 case '<':
1368 switch (opP->mode)
1369 {
1370 case DREG:
1371 case AREG:
1372 case FPREG:
1373 case CONTROL:
1374 case IMMED:
1375 case ADEC:
1376 case REGLST:
1377 losing++;
1378 break;
1379 default:
1380 break;
1381 }
1382 break;
1383
1384 case '>':
1385 switch (opP->mode)
1386 {
1387 case DREG:
1388 case AREG:
1389 case FPREG:
1390 case CONTROL:
1391 case IMMED:
1392 case AINC:
1393 case REGLST:
1394 losing++;
1395 break;
1396 case ABSL:
1397 break;
1398 default:
1399 if (opP->reg == PC
1400 || opP->reg == ZPC)
1401 losing++;
1402 break;
1403 }
1404 break;
1405
1406 case 'm':
1407 switch (opP->mode)
1408 {
1409 case DREG:
1410 case AREG:
1411 case AINDR:
1412 case AINC:
1413 case ADEC:
1414 break;
1415 default:
1416 losing++;
1417 }
1418 break;
1419
1420 case 'n':
1421 switch (opP->mode)
1422 {
1423 case DISP:
1424 break;
1425 default:
1426 losing++;
1427 }
1428 break;
1429
1430 case 'o':
1431 switch (opP->mode)
1432 {
1433 case BASE:
1434 case ABSL:
1435 case IMMED:
1436 break;
1437 default:
1438 losing++;
1439 }
1440 break;
1441
1442 case 'p':
1443 switch (opP->mode)
1444 {
1445 case DREG:
1446 case AREG:
1447 case AINDR:
1448 case AINC:
1449 case ADEC:
1450 break;
1451 case DISP:
1452 if (opP->reg == PC || opP->reg == ZPC)
1453 losing++;
1454 break;
1455 default:
1456 losing++;
1457 }
1458 break;
1459
1460 case 'q':
1461 switch (opP->mode)
1462 {
1463 case DREG:
1464 case AINDR:
1465 case AINC:
1466 case ADEC:
1467 break;
1468 case DISP:
1469 if (opP->reg == PC || opP->reg == ZPC)
1470 losing++;
1471 break;
1472 default:
1473 losing++;
1474 break;
1475 }
1476 break;
1477
1478 case 'v':
1479 switch (opP->mode)
1480 {
1481 case DREG:
1482 case AINDR:
1483 case AINC:
1484 case ADEC:
1485 case ABSL:
1486 break;
1487 case DISP:
1488 if (opP->reg == PC || opP->reg == ZPC)
1489 losing++;
1490 break;
1491 default:
1492 losing++;
1493 break;
1494 }
1495 break;
1496
1497 case '#':
1498 if (opP->mode != IMMED)
1499 losing++;
1500 else if (s[1] == 'b'
1501 && ! isvar (&opP->disp)
1502 && (opP->disp.exp.X_op != O_constant
1503 || ! isbyte (opP->disp.exp.X_add_number)))
1504 losing++;
1505 else if (s[1] == 'B'
1506 && ! isvar (&opP->disp)
1507 && (opP->disp.exp.X_op != O_constant
1508 || ! issbyte (opP->disp.exp.X_add_number)))
1509 losing++;
1510 else if (s[1] == 'w'
1511 && ! isvar (&opP->disp)
1512 && (opP->disp.exp.X_op != O_constant
1513 || ! isword (opP->disp.exp.X_add_number)))
1514 losing++;
1515 else if (s[1] == 'W'
1516 && ! isvar (&opP->disp)
1517 && (opP->disp.exp.X_op != O_constant
1518 || ! issword (opP->disp.exp.X_add_number)))
1519 losing++;
1520 break;
1521
1522 case '^':
1523 case 'T':
1524 if (opP->mode != IMMED)
1525 losing++;
1526 break;
1527
1528 case '$':
1529 if (opP->mode == AREG
1530 || opP->mode == CONTROL
1531 || opP->mode == FPREG
1532 || opP->mode == IMMED
1533 || opP->mode == REGLST
1534 || (opP->mode != ABSL
1535 && (opP->reg == PC
1536 || opP->reg == ZPC)))
1537 losing++;
1538 break;
1539
1540 case '%':
1541 if (opP->mode == CONTROL
1542 || opP->mode == FPREG
1543 || opP->mode == REGLST
1544 || opP->mode == IMMED
1545 || (opP->mode != ABSL
1546 && (opP->reg == PC
1547 || opP->reg == ZPC)))
1548 losing++;
1549 break;
1550
1551 case '&':
1552 switch (opP->mode)
1553 {
1554 case DREG:
1555 case AREG:
1556 case FPREG:
1557 case CONTROL:
1558 case IMMED:
1559 case AINC:
1560 case ADEC:
1561 case REGLST:
1562 losing++;
1563 break;
1564 case ABSL:
1565 break;
1566 default:
1567 if (opP->reg == PC
1568 || opP->reg == ZPC)
1569 losing++;
1570 break;
1571 }
1572 break;
1573
1574 case '*':
1575 if (opP->mode == CONTROL
1576 || opP->mode == FPREG
1577 || opP->mode == REGLST)
1578 losing++;
1579 break;
1580
1581 case '+':
1582 if (opP->mode != AINC)
1583 losing++;
1584 break;
1585
1586 case '-':
1587 if (opP->mode != ADEC)
1588 losing++;
1589 break;
1590
1591 case '/':
1592 switch (opP->mode)
1593 {
1594 case AREG:
1595 case CONTROL:
1596 case FPREG:
1597 case AINC:
1598 case ADEC:
1599 case IMMED:
1600 case REGLST:
1601 losing++;
1602 break;
1603 default:
1604 break;
1605 }
1606 break;
1607
1608 case ';':
1609 switch (opP->mode)
1610 {
1611 case AREG:
1612 case CONTROL:
1613 case FPREG:
1614 case REGLST:
1615 losing++;
1616 break;
1617 default:
1618 break;
1619 }
1620 break;
1621
1622 case '?':
1623 switch (opP->mode)
1624 {
1625 case AREG:
1626 case CONTROL:
1627 case FPREG:
1628 case AINC:
1629 case ADEC:
1630 case IMMED:
1631 case REGLST:
1632 losing++;
1633 break;
1634 case ABSL:
1635 break;
1636 default:
1637 if (opP->reg == PC || opP->reg == ZPC)
1638 losing++;
1639 break;
1640 }
1641 break;
1642
1643 case '@':
1644 switch (opP->mode)
1645 {
1646 case AREG:
1647 case CONTROL:
1648 case FPREG:
1649 case IMMED:
1650 case REGLST:
1651 losing++;
1652 break;
1653 default:
1654 break;
1655 }
1656 break;
1657
1658 case '~': /* For now! (JF FOO is this right?) */
1659 switch (opP->mode)
1660 {
1661 case DREG:
1662 case AREG:
1663 case CONTROL:
1664 case FPREG:
1665 case IMMED:
1666 case REGLST:
1667 losing++;
1668 break;
1669 case ABSL:
1670 break;
1671 default:
1672 if (opP->reg == PC
1673 || opP->reg == ZPC)
1674 losing++;
1675 break;
1676 }
1677 break;
1678
1679 case '3':
1680 if (opP->mode != CONTROL
1681 || (opP->reg != TT0 && opP->reg != TT1))
1682 losing++;
1683 break;
1684
1685 case 'A':
1686 if (opP->mode != AREG)
1687 losing++;
1688 break;
1689
1690 case 'a':
1691 if (opP->mode != AINDR)
1692 ++losing;
1693 break;
1694
1695 case '4':
1696 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1697 && (opP->mode != DISP
1698 || opP->reg < ADDR0
1699 || opP->reg > ADDR7))
1700 ++losing;
1701 break;
1702
1703 case 'B': /* FOO */
1704 if (opP->mode != ABSL
1705 || (flag_long_jumps
1706 && strncmp (instring, "jbsr", 4) == 0))
1707 losing++;
1708 break;
1709
1710 case 'b':
1711 switch (opP->mode)
1712 {
1713 case IMMED:
1714 case ABSL:
1715 case AREG:
1716 case FPREG:
1717 case CONTROL:
1718 case POST:
1719 case PRE:
1720 case REGLST:
1721 losing++;
1722 break;
1723 default:
1724 break;
1725 }
1726 break;
1727
1728 case 'C':
1729 if (opP->mode != CONTROL || opP->reg != CCR)
1730 losing++;
1731 break;
1732
1733 case 'd':
1734 if (opP->mode != DISP
1735 || opP->reg < ADDR0
1736 || opP->reg > ADDR7)
1737 losing++;
1738 break;
1739
1740 case 'D':
1741 if (opP->mode != DREG)
1742 losing++;
1743 break;
1744
1745 case 'E':
1746 if (opP->reg != ACC)
1747 losing++;
1748 break;
1749
1750 case 'e':
1751 if (opP->reg != ACC && opP->reg != ACC1
1752 && opP->reg != ACC2 && opP->reg != ACC3)
1753 losing++;
1754 break;
1755
1756 case 'F':
1757 if (opP->mode != FPREG)
1758 losing++;
1759 break;
1760
1761 case 'G':
1762 if (opP->reg != MACSR)
1763 losing++;
1764 break;
1765
1766 case 'g':
1767 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1768 losing++;
1769 break;
1770
1771 case 'H':
1772 if (opP->reg != MASK)
1773 losing++;
1774 break;
1775
1776 case 'I':
1777 if (opP->mode != CONTROL
1778 || opP->reg < COP0
1779 || opP->reg > COP7)
1780 losing++;
1781 break;
1782
1783 case 'i':
1784 if (opP->mode != LSH && opP->mode != RSH)
1785 losing++;
1786 break;
1787
1788 case 'J':
1789 if (opP->mode != CONTROL
1790 || opP->reg < USP
1791 || opP->reg > last_movec_reg
1792 || !control_regs)
1793 losing++;
1794 else
1795 {
1796 const enum m68k_register *rp;
1797
1798 for (rp = control_regs; *rp; rp++)
1799 {
1800 if (*rp == opP->reg)
1801 break;
1802 /* In most CPUs RAMBAR refers to control reg
1803 c05 (RAMBAR1), but a few CPUs have it
1804 refer to c04 (RAMBAR0). */
1805 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1806 {
1807 opP->reg = RAMBAR_ALT;
1808 break;
1809 }
1810 }
1811 if (*rp == 0)
1812 losing++;
1813 }
1814 break;
1815
1816 case 'k':
1817 if (opP->mode != IMMED)
1818 losing++;
1819 break;
1820
1821 case 'l':
1822 case 'L':
1823 if (opP->mode == DREG
1824 || opP->mode == AREG
1825 || opP->mode == FPREG)
1826 {
1827 if (s[1] == '8')
1828 losing++;
1829 else
1830 {
1831 switch (opP->mode)
1832 {
1833 case DREG:
1834 opP->mask = 1 << (opP->reg - DATA0);
1835 break;
1836 case AREG:
1837 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1838 break;
1839 case FPREG:
1840 opP->mask = 1 << (opP->reg - FP0 + 16);
1841 break;
1842 default:
1843 abort ();
1844 }
1845 opP->mode = REGLST;
1846 }
1847 }
1848 else if (opP->mode == CONTROL)
1849 {
1850 if (s[1] != '8')
1851 losing++;
1852 else
1853 {
1854 switch (opP->reg)
1855 {
1856 case FPI:
1857 opP->mask = 1 << 24;
1858 break;
1859 case FPS:
1860 opP->mask = 1 << 25;
1861 break;
1862 case FPC:
1863 opP->mask = 1 << 26;
1864 break;
1865 default:
1866 losing++;
1867 break;
1868 }
1869 opP->mode = REGLST;
1870 }
1871 }
1872 else if (opP->mode != REGLST)
1873 losing++;
1874 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1875 losing++;
1876 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1877 losing++;
1878 break;
1879
1880 case 'M':
1881 if (opP->mode != IMMED)
1882 losing++;
1883 else if (opP->disp.exp.X_op != O_constant
1884 || ! issbyte (opP->disp.exp.X_add_number))
1885 losing++;
1886 else if (! m68k_quick
1887 && instring[3] != 'q'
1888 && instring[4] != 'q')
1889 losing++;
1890 break;
1891
1892 case 'O':
1893 if (opP->mode != DREG
1894 && opP->mode != IMMED
1895 && opP->mode != ABSL)
1896 losing++;
1897 break;
1898
1899 case 'Q':
1900 if (opP->mode != IMMED)
1901 losing++;
1902 else if (opP->disp.exp.X_op != O_constant
1903 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1904 losing++;
1905 else if (! m68k_quick
1906 && (strncmp (instring, "add", 3) == 0
1907 || strncmp (instring, "sub", 3) == 0)
1908 && instring[3] != 'q')
1909 losing++;
1910 break;
1911
1912 case 'R':
1913 if (opP->mode != DREG && opP->mode != AREG)
1914 losing++;
1915 break;
1916
1917 case 'r':
1918 if (opP->mode != AINDR
1919 && (opP->mode != BASE
1920 || (opP->reg != 0
1921 && opP->reg != ZADDR0)
1922 || opP->disp.exp.X_op != O_absent
1923 || ((opP->index.reg < DATA0
1924 || opP->index.reg > DATA7)
1925 && (opP->index.reg < ADDR0
1926 || opP->index.reg > ADDR7))
1927 || opP->index.size != SIZE_UNSPEC
1928 || opP->index.scale != 1))
1929 losing++;
1930 break;
1931
1932 case 's':
1933 if (opP->mode != CONTROL
1934 || ! (opP->reg == FPI
1935 || opP->reg == FPS
1936 || opP->reg == FPC))
1937 losing++;
1938 break;
1939
1940 case 'S':
1941 if (opP->mode != CONTROL || opP->reg != SR)
1942 losing++;
1943 break;
1944
1945 case 't':
1946 if (opP->mode != IMMED)
1947 losing++;
1948 else if (opP->disp.exp.X_op != O_constant
1949 || TRUNC (opP->disp.exp.X_add_number) > 7)
1950 losing++;
1951 break;
1952
1953 case 'U':
1954 if (opP->mode != CONTROL || opP->reg != USP)
1955 losing++;
1956 break;
1957
1958 case 'x':
1959 if (opP->mode != IMMED)
1960 losing++;
1961 else if (opP->disp.exp.X_op != O_constant
1962 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1963 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1964 losing++;
1965 break;
1966
1967 /* JF these are out of order. We could put them
1968 in order if we were willing to put up with
1969 bunches of #ifdef m68851s in the code.
1970
1971 Don't forget that you need these operands
1972 to use 68030 MMU instructions. */
1973 #ifndef NO_68851
1974 /* Memory addressing mode used by pflushr. */
1975 case '|':
1976 if (opP->mode == CONTROL
1977 || opP->mode == FPREG
1978 || opP->mode == DREG
1979 || opP->mode == AREG
1980 || opP->mode == REGLST)
1981 losing++;
1982 /* We should accept immediate operands, but they
1983 supposedly have to be quad word, and we don't
1984 handle that. I would like to see what a Motorola
1985 assembler does before doing something here. */
1986 if (opP->mode == IMMED)
1987 losing++;
1988 break;
1989
1990 case 'f':
1991 if (opP->mode != CONTROL
1992 || (opP->reg != SFC && opP->reg != DFC))
1993 losing++;
1994 break;
1995
1996 case '0':
1997 if (opP->mode != CONTROL || opP->reg != TC)
1998 losing++;
1999 break;
2000
2001 case '1':
2002 if (opP->mode != CONTROL || opP->reg != AC)
2003 losing++;
2004 break;
2005
2006 case '2':
2007 if (opP->mode != CONTROL
2008 || (opP->reg != CAL
2009 && opP->reg != VAL
2010 && opP->reg != SCC))
2011 losing++;
2012 break;
2013
2014 case 'V':
2015 if (opP->mode != CONTROL
2016 || opP->reg != VAL)
2017 losing++;
2018 break;
2019
2020 case 'W':
2021 if (opP->mode != CONTROL
2022 || (opP->reg != DRP
2023 && opP->reg != SRP
2024 && opP->reg != CRP))
2025 losing++;
2026 break;
2027
2028 case 'w':
2029 switch (opP->mode)
2030 {
2031 case IMMED:
2032 case ABSL:
2033 case AREG:
2034 case DREG:
2035 case FPREG:
2036 case CONTROL:
2037 case POST:
2038 case PRE:
2039 case REGLST:
2040 losing++;
2041 break;
2042 default:
2043 break;
2044 }
2045 break;
2046
2047 case 'X':
2048 if (opP->mode != CONTROL
2049 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2050 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2051 losing++;
2052 break;
2053
2054 case 'Y':
2055 if (opP->mode != CONTROL || opP->reg != PSR)
2056 losing++;
2057 break;
2058
2059 case 'Z':
2060 if (opP->mode != CONTROL || opP->reg != PCSR)
2061 losing++;
2062 break;
2063 #endif
2064 case 'c':
2065 if (opP->mode != CONTROL
2066 || (opP->reg != NC
2067 && opP->reg != IC
2068 && opP->reg != DC
2069 && opP->reg != BC))
2070 losing++;
2071 break;
2072
2073 case '_':
2074 if (opP->mode != ABSL)
2075 ++losing;
2076 break;
2077
2078 case 'u':
2079 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2080 losing++;
2081 /* FIXME: kludge instead of fixing parser:
2082 upper/lower registers are *not* CONTROL
2083 registers, but ordinary ones. */
2084 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2085 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2086 opP->mode = DREG;
2087 else
2088 opP->mode = AREG;
2089 break;
2090
2091 case 'y':
2092 if (!(opP->mode == AINDR
2093 || (opP->mode == DISP
2094 && !(opP->reg == PC || opP->reg == ZPC))))
2095 losing++;
2096 break;
2097
2098 case 'z':
2099 if (!(opP->mode == AINDR || opP->mode == DISP))
2100 losing++;
2101 break;
2102
2103 default:
2104 abort ();
2105 }
2106
2107 if (losing)
2108 break;
2109 }
2110
2111 /* Since we have found the correct instruction, copy
2112 in the modifications that we may have made. */
2113 if (!losing)
2114 for (i = 0; i < opsfound; i++)
2115 the_ins.operands[i] = operands_backup[i];
2116 }
2117
2118 if (!losing)
2119 break;
2120
2121 opcode = opcode->m_next;
2122
2123 if (!opcode)
2124 {
2125 if (ok_arch
2126 && !(ok_arch & current_architecture))
2127 {
2128 const struct m68k_cpu *cpu;
2129 int any = 0;
2130 size_t space = 400;
2131 char *buf = xmalloc (space + 1);
2132 size_t len;
2133 int paren = 1;
2134
2135 the_ins.error = buf;
2136 /* Make sure there's a NUL at the end of the buffer -- strncpy
2137 won't write one when it runs out of buffer */
2138 buf[space] = 0;
2139 #define APPEND(STRING) \
2140 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2141
2142 APPEND (_("invalid instruction for this architecture; needs "));
2143 switch (ok_arch)
2144 {
2145 case mcfisa_a:
2146 APPEND (_("ColdFire ISA_A"));
2147 break;
2148 case mcfhwdiv:
2149 APPEND (_("ColdFire hardware divide"));
2150 break;
2151 case mcfisa_aa:
2152 APPEND (_("ColdFire ISA_A+"));
2153 break;
2154 case mcfisa_b:
2155 APPEND (_("ColdFire ISA_B"));
2156 break;
2157 case cfloat:
2158 APPEND (_("ColdFire fpu"));
2159 break;
2160 case mfloat:
2161 APPEND (_("M68K fpu"));
2162 break;
2163 case mmmu:
2164 APPEND (_("M68K mmu"));
2165 break;
2166 case m68020up:
2167 APPEND (_("68020 or higher"));
2168 break;
2169 case m68000up:
2170 APPEND (_("68000 or higher"));
2171 break;
2172 case m68010up:
2173 APPEND (_("68010 or higher"));
2174 break;
2175 default:
2176 paren = 0;
2177 }
2178 if (paren)
2179 APPEND (" (");
2180
2181 for (cpu = m68k_cpus; cpu->name; cpu++)
2182 if (!cpu->alias && (cpu->arch & ok_arch))
2183 {
2184 const struct m68k_cpu *alias;
2185 int seen_master = 0;
2186
2187 if (any)
2188 APPEND (", ");
2189 any = 0;
2190 APPEND (cpu->name);
2191 for (alias = cpu; alias != m68k_cpus; alias--)
2192 if (alias[-1].alias >= 0)
2193 break;
2194 for (; !seen_master || alias->alias > 0; alias++)
2195 {
2196 if (!alias->alias)
2197 seen_master = 1;
2198 else
2199 {
2200 if (any)
2201 APPEND (", ");
2202 else
2203 APPEND (" [");
2204 APPEND (alias->name);
2205 any = 1;
2206 }
2207 }
2208 if (any)
2209 APPEND ("]");
2210 any = 1;
2211 }
2212 if (paren)
2213 APPEND (")");
2214 #undef APPEND
2215 if (!space)
2216 {
2217 /* we ran out of space, so replace the end of the list
2218 with ellipsis. */
2219 buf -= 4;
2220 while (*buf != ' ')
2221 buf--;
2222 strcpy (buf, " ...");
2223 }
2224 }
2225 else
2226 the_ins.error = _("operands mismatch");
2227 return;
2228 }
2229
2230 losing = 0;
2231 }
2232
2233 /* Now assemble it. */
2234 the_ins.args = opcode->m_operands;
2235 the_ins.numargs = opcode->m_opnum;
2236 the_ins.numo = opcode->m_codenum;
2237 the_ins.opcode[0] = getone (opcode);
2238 the_ins.opcode[1] = gettwo (opcode);
2239
2240 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2241 {
2242 int have_disp = 0;
2243
2244 /* This switch is a doozy.
2245 Watch the first step; its a big one! */
2246 switch (s[0])
2247 {
2248
2249 case '*':
2250 case '~':
2251 case '%':
2252 case ';':
2253 case '@':
2254 case '!':
2255 case '&':
2256 case '$':
2257 case '?':
2258 case '/':
2259 case '<':
2260 case '>':
2261 case 'b':
2262 case 'm':
2263 case 'n':
2264 case 'o':
2265 case 'p':
2266 case 'q':
2267 case 'v':
2268 case 'w':
2269 case 'y':
2270 case 'z':
2271 case '4':
2272 #ifndef NO_68851
2273 case '|':
2274 #endif
2275 switch (opP->mode)
2276 {
2277 case IMMED:
2278 tmpreg = 0x3c; /* 7.4 */
2279 if (strchr ("bwl", s[1]))
2280 nextword = get_num (&opP->disp, 90);
2281 else
2282 nextword = get_num (&opP->disp, 0);
2283 if (isvar (&opP->disp))
2284 add_fix (s[1], &opP->disp, 0, 0);
2285 switch (s[1])
2286 {
2287 case 'b':
2288 if (!isbyte (nextword))
2289 opP->error = _("operand out of range");
2290 addword (nextword);
2291 baseo = 0;
2292 break;
2293 case 'w':
2294 if (!isword (nextword))
2295 opP->error = _("operand out of range");
2296 addword (nextword);
2297 baseo = 0;
2298 break;
2299 case 'W':
2300 if (!issword (nextword))
2301 opP->error = _("operand out of range");
2302 addword (nextword);
2303 baseo = 0;
2304 break;
2305 case 'l':
2306 addword (nextword >> 16);
2307 addword (nextword);
2308 baseo = 0;
2309 break;
2310
2311 case 'f':
2312 baseo = 2;
2313 outro = 8;
2314 break;
2315 case 'F':
2316 baseo = 4;
2317 outro = 11;
2318 break;
2319 case 'x':
2320 baseo = 6;
2321 outro = 15;
2322 break;
2323 case 'p':
2324 baseo = 6;
2325 outro = -1;
2326 break;
2327 default:
2328 abort ();
2329 }
2330 if (!baseo)
2331 break;
2332
2333 /* We gotta put out some float. */
2334 if (op (&opP->disp) != O_big)
2335 {
2336 valueT val;
2337 int gencnt;
2338
2339 /* Can other cases happen here? */
2340 if (op (&opP->disp) != O_constant)
2341 abort ();
2342
2343 val = (valueT) offs (&opP->disp);
2344 gencnt = 0;
2345 do
2346 {
2347 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2348 val >>= LITTLENUM_NUMBER_OF_BITS;
2349 ++gencnt;
2350 }
2351 while (val != 0);
2352 offs (&opP->disp) = gencnt;
2353 }
2354 if (offs (&opP->disp) > 0)
2355 {
2356 if (offs (&opP->disp) > baseo)
2357 {
2358 as_warn (_("Bignum too big for %c format; truncated"),
2359 s[1]);
2360 offs (&opP->disp) = baseo;
2361 }
2362 baseo -= offs (&opP->disp);
2363 while (baseo--)
2364 addword (0);
2365 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2366 offs (&opP->disp)--;
2367 --wordp)
2368 addword (*wordp);
2369 break;
2370 }
2371 gen_to_words (words, baseo, (long) outro);
2372 for (wordp = words; baseo--; wordp++)
2373 addword (*wordp);
2374 break;
2375 case DREG:
2376 tmpreg = opP->reg - DATA; /* 0.dreg */
2377 break;
2378 case AREG:
2379 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2380 break;
2381 case AINDR:
2382 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2383 break;
2384 case ADEC:
2385 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2386 break;
2387 case AINC:
2388 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2389 break;
2390 case DISP:
2391
2392 nextword = get_num (&opP->disp, 90);
2393
2394 /* Convert mode 5 addressing with a zero offset into
2395 mode 2 addressing to reduce the instruction size by a
2396 word. */
2397 if (! isvar (&opP->disp)
2398 && (nextword == 0)
2399 && (opP->disp.size == SIZE_UNSPEC)
2400 && (opP->reg >= ADDR0)
2401 && (opP->reg <= ADDR7))
2402 {
2403 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2404 break;
2405 }
2406
2407 if (opP->reg == PC
2408 && ! isvar (&opP->disp)
2409 && m68k_abspcadd)
2410 {
2411 opP->disp.exp.X_op = O_symbol;
2412 opP->disp.exp.X_add_symbol =
2413 section_symbol (absolute_section);
2414 }
2415
2416 /* Force into index mode. Hope this works. */
2417
2418 /* We do the first bit for 32-bit displacements, and the
2419 second bit for 16 bit ones. It is possible that we
2420 should make the default be WORD instead of LONG, but
2421 I think that'd break GCC, so we put up with a little
2422 inefficiency for the sake of working output. */
2423
2424 if (!issword (nextword)
2425 || (isvar (&opP->disp)
2426 && ((opP->disp.size == SIZE_UNSPEC
2427 && flag_short_refs == 0
2428 && cpu_of_arch (current_architecture) >= m68020
2429 && ! arch_coldfire_p (current_architecture))
2430 || opP->disp.size == SIZE_LONG)))
2431 {
2432 if (cpu_of_arch (current_architecture) < m68020
2433 || arch_coldfire_p (current_architecture))
2434 opP->error =
2435 _("displacement too large for this architecture; needs 68020 or higher");
2436 if (opP->reg == PC)
2437 tmpreg = 0x3B; /* 7.3 */
2438 else
2439 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2440 if (isvar (&opP->disp))
2441 {
2442 if (opP->reg == PC)
2443 {
2444 if (opP->disp.size == SIZE_LONG
2445 #ifdef OBJ_ELF
2446 /* If the displacement needs pic
2447 relocation it cannot be relaxed. */
2448 || opP->disp.pic_reloc != pic_none
2449 #endif
2450 )
2451 {
2452 addword (0x0170);
2453 add_fix ('l', &opP->disp, 1, 2);
2454 }
2455 else
2456 {
2457 add_frag (adds (&opP->disp),
2458 SEXT (offs (&opP->disp)),
2459 TAB (PCREL1632, SZ_UNDEF));
2460 break;
2461 }
2462 }
2463 else
2464 {
2465 addword (0x0170);
2466 add_fix ('l', &opP->disp, 0, 0);
2467 }
2468 }
2469 else
2470 addword (0x0170);
2471 addword (nextword >> 16);
2472 }
2473 else
2474 {
2475 if (opP->reg == PC)
2476 tmpreg = 0x3A; /* 7.2 */
2477 else
2478 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2479
2480 if (isvar (&opP->disp))
2481 {
2482 if (opP->reg == PC)
2483 {
2484 add_fix ('w', &opP->disp, 1, 0);
2485 }
2486 else
2487 add_fix ('w', &opP->disp, 0, 0);
2488 }
2489 }
2490 addword (nextword);
2491 break;
2492
2493 case POST:
2494 case PRE:
2495 case BASE:
2496 nextword = 0;
2497 baseo = get_num (&opP->disp, 90);
2498 if (opP->mode == POST || opP->mode == PRE)
2499 outro = get_num (&opP->odisp, 90);
2500 /* Figure out the `addressing mode'.
2501 Also turn on the BASE_DISABLE bit, if needed. */
2502 if (opP->reg == PC || opP->reg == ZPC)
2503 {
2504 tmpreg = 0x3b; /* 7.3 */
2505 if (opP->reg == ZPC)
2506 nextword |= 0x80;
2507 }
2508 else if (opP->reg == 0)
2509 {
2510 nextword |= 0x80;
2511 tmpreg = 0x30; /* 6.garbage */
2512 }
2513 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2514 {
2515 nextword |= 0x80;
2516 tmpreg = 0x30 + opP->reg - ZADDR0;
2517 }
2518 else
2519 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2520
2521 siz1 = opP->disp.size;
2522 if (opP->mode == POST || opP->mode == PRE)
2523 siz2 = opP->odisp.size;
2524 else
2525 siz2 = SIZE_UNSPEC;
2526
2527 /* Index register stuff. */
2528 if (opP->index.reg != 0
2529 && opP->index.reg >= DATA
2530 && opP->index.reg <= ADDR7)
2531 {
2532 nextword |= (opP->index.reg - DATA) << 12;
2533
2534 if (opP->index.size == SIZE_LONG
2535 || (opP->index.size == SIZE_UNSPEC
2536 && m68k_index_width_default == SIZE_LONG))
2537 nextword |= 0x800;
2538
2539 if ((opP->index.scale != 1
2540 && cpu_of_arch (current_architecture) < m68020)
2541 || (opP->index.scale == 8
2542 && (arch_coldfire_p (current_architecture)
2543 && !arch_coldfire_fpu (current_architecture))))
2544 {
2545 opP->error =
2546 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2547 }
2548
2549 if (arch_coldfire_p (current_architecture)
2550 && opP->index.size == SIZE_WORD)
2551 opP->error = _("invalid index size for coldfire");
2552
2553 switch (opP->index.scale)
2554 {
2555 case 1:
2556 break;
2557 case 2:
2558 nextword |= 0x200;
2559 break;
2560 case 4:
2561 nextword |= 0x400;
2562 break;
2563 case 8:
2564 nextword |= 0x600;
2565 break;
2566 default:
2567 abort ();
2568 }
2569 /* IF its simple,
2570 GET US OUT OF HERE! */
2571
2572 /* Must be INDEX, with an index register. Address
2573 register cannot be ZERO-PC, and either :b was
2574 forced, or we know it will fit. For a 68000 or
2575 68010, force this mode anyways, because the
2576 larger modes aren't supported. */
2577 if (opP->mode == BASE
2578 && ((opP->reg >= ADDR0
2579 && opP->reg <= ADDR7)
2580 || opP->reg == PC))
2581 {
2582 if (siz1 == SIZE_BYTE
2583 || cpu_of_arch (current_architecture) < m68020
2584 || arch_coldfire_p (current_architecture)
2585 || (siz1 == SIZE_UNSPEC
2586 && ! isvar (&opP->disp)
2587 && issbyte (baseo)))
2588 {
2589 nextword += baseo & 0xff;
2590 addword (nextword);
2591 if (isvar (&opP->disp))
2592 {
2593 /* Do a byte relocation. If it doesn't
2594 fit (possible on m68000) let the
2595 fixup processing complain later. */
2596 if (opP->reg == PC)
2597 add_fix ('B', &opP->disp, 1, 1);
2598 else
2599 add_fix ('B', &opP->disp, 0, 0);
2600 }
2601 else if (siz1 != SIZE_BYTE)
2602 {
2603 if (siz1 != SIZE_UNSPEC)
2604 as_warn (_("Forcing byte displacement"));
2605 if (! issbyte (baseo))
2606 opP->error = _("byte displacement out of range");
2607 }
2608
2609 break;
2610 }
2611 else if (siz1 == SIZE_UNSPEC
2612 && opP->reg == PC
2613 && isvar (&opP->disp)
2614 && subs (&opP->disp) == NULL
2615 #ifdef OBJ_ELF
2616 /* If the displacement needs pic
2617 relocation it cannot be relaxed. */
2618 && opP->disp.pic_reloc == pic_none
2619 #endif
2620 )
2621 {
2622 /* The code in md_convert_frag_1 needs to be
2623 able to adjust nextword. Call frag_grow
2624 to ensure that we have enough space in
2625 the frag obstack to make all the bytes
2626 contiguous. */
2627 frag_grow (14);
2628 nextword += baseo & 0xff;
2629 addword (nextword);
2630 add_frag (adds (&opP->disp),
2631 SEXT (offs (&opP->disp)),
2632 TAB (PCINDEX, SZ_UNDEF));
2633
2634 break;
2635 }
2636 }
2637 }
2638 else
2639 {
2640 nextword |= 0x40; /* No index reg. */
2641 if (opP->index.reg >= ZDATA0
2642 && opP->index.reg <= ZDATA7)
2643 nextword |= (opP->index.reg - ZDATA0) << 12;
2644 else if (opP->index.reg >= ZADDR0
2645 || opP->index.reg <= ZADDR7)
2646 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2647 }
2648
2649 /* It isn't simple. */
2650
2651 if (cpu_of_arch (current_architecture) < m68020
2652 || arch_coldfire_p (current_architecture))
2653 opP->error =
2654 _("invalid operand mode for this architecture; needs 68020 or higher");
2655
2656 nextword |= 0x100;
2657 /* If the guy specified a width, we assume that it is
2658 wide enough. Maybe it isn't. If so, we lose. */
2659 switch (siz1)
2660 {
2661 case SIZE_UNSPEC:
2662 if (isvar (&opP->disp)
2663 ? m68k_rel32
2664 : ! issword (baseo))
2665 {
2666 siz1 = SIZE_LONG;
2667 nextword |= 0x30;
2668 }
2669 else if (! isvar (&opP->disp) && baseo == 0)
2670 nextword |= 0x10;
2671 else
2672 {
2673 nextword |= 0x20;
2674 siz1 = SIZE_WORD;
2675 }
2676 break;
2677 case SIZE_BYTE:
2678 as_warn (_(":b not permitted; defaulting to :w"));
2679 /* Fall through. */
2680 case SIZE_WORD:
2681 nextword |= 0x20;
2682 break;
2683 case SIZE_LONG:
2684 nextword |= 0x30;
2685 break;
2686 }
2687
2688 /* Figure out inner displacement stuff. */
2689 if (opP->mode == POST || opP->mode == PRE)
2690 {
2691 if (cpu_of_arch (current_architecture) & cpu32)
2692 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2693 switch (siz2)
2694 {
2695 case SIZE_UNSPEC:
2696 if (isvar (&opP->odisp)
2697 ? m68k_rel32
2698 : ! issword (outro))
2699 {
2700 siz2 = SIZE_LONG;
2701 nextword |= 0x3;
2702 }
2703 else if (! isvar (&opP->odisp) && outro == 0)
2704 nextword |= 0x1;
2705 else
2706 {
2707 nextword |= 0x2;
2708 siz2 = SIZE_WORD;
2709 }
2710 break;
2711 case 1:
2712 as_warn (_(":b not permitted; defaulting to :w"));
2713 /* Fall through. */
2714 case 2:
2715 nextword |= 0x2;
2716 break;
2717 case 3:
2718 nextword |= 0x3;
2719 break;
2720 }
2721 if (opP->mode == POST
2722 && (nextword & 0x40) == 0)
2723 nextword |= 0x04;
2724 }
2725 addword (nextword);
2726
2727 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2728 {
2729 if (opP->reg == PC || opP->reg == ZPC)
2730 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2731 else
2732 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2733 }
2734 if (siz1 == SIZE_LONG)
2735 addword (baseo >> 16);
2736 if (siz1 != SIZE_UNSPEC)
2737 addword (baseo);
2738
2739 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2740 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2741 if (siz2 == SIZE_LONG)
2742 addword (outro >> 16);
2743 if (siz2 != SIZE_UNSPEC)
2744 addword (outro);
2745
2746 break;
2747
2748 case ABSL:
2749 nextword = get_num (&opP->disp, 90);
2750 switch (opP->disp.size)
2751 {
2752 default:
2753 abort ();
2754 case SIZE_UNSPEC:
2755 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2756 {
2757 tmpreg = 0x38; /* 7.0 */
2758 addword (nextword);
2759 break;
2760 }
2761 if (isvar (&opP->disp)
2762 && !subs (&opP->disp)
2763 && adds (&opP->disp)
2764 #ifdef OBJ_ELF
2765 /* If the displacement needs pic relocation it
2766 cannot be relaxed. */
2767 && opP->disp.pic_reloc == pic_none
2768 #endif
2769 && !flag_long_jumps
2770 && !strchr ("~%&$?", s[0]))
2771 {
2772 tmpreg = 0x3A; /* 7.2 */
2773 add_frag (adds (&opP->disp),
2774 SEXT (offs (&opP->disp)),
2775 TAB (ABSTOPCREL, SZ_UNDEF));
2776 break;
2777 }
2778 /* Fall through into long. */
2779 case SIZE_LONG:
2780 if (isvar (&opP->disp))
2781 add_fix ('l', &opP->disp, 0, 0);
2782
2783 tmpreg = 0x39;/* 7.1 mode */
2784 addword (nextword >> 16);
2785 addword (nextword);
2786 break;
2787
2788 case SIZE_BYTE:
2789 as_bad (_("unsupported byte value; use a different suffix"));
2790 /* Fall through. */
2791
2792 case SIZE_WORD:
2793 if (isvar (&opP->disp))
2794 add_fix ('w', &opP->disp, 0, 0);
2795
2796 tmpreg = 0x38;/* 7.0 mode */
2797 addword (nextword);
2798 break;
2799 }
2800 break;
2801 case CONTROL:
2802 case FPREG:
2803 default:
2804 as_bad (_("unknown/incorrect operand"));
2805 /* abort (); */
2806 }
2807
2808 /* If s[0] is '4', then this is for the mac instructions
2809 that can have a trailing_ampersand set. If so, set 0x100
2810 bit on tmpreg so install_gen_operand can check for it and
2811 set the appropriate bit (word2, bit 5). */
2812 if (s[0] == '4')
2813 {
2814 if (opP->trailing_ampersand)
2815 tmpreg |= 0x100;
2816 }
2817 install_gen_operand (s[1], tmpreg);
2818 break;
2819
2820 case '#':
2821 case '^':
2822 switch (s[1])
2823 { /* JF: I hate floating point! */
2824 case 'j':
2825 tmpreg = 70;
2826 break;
2827 case '8':
2828 tmpreg = 20;
2829 break;
2830 case 'C':
2831 tmpreg = 50;
2832 break;
2833 case '3':
2834 default:
2835 tmpreg = 90;
2836 break;
2837 }
2838 tmpreg = get_num (&opP->disp, tmpreg);
2839 if (isvar (&opP->disp))
2840 add_fix (s[1], &opP->disp, 0, 0);
2841 switch (s[1])
2842 {
2843 case 'b': /* Danger: These do no check for
2844 certain types of overflow.
2845 user beware! */
2846 if (!isbyte (tmpreg))
2847 opP->error = _("out of range");
2848 insop (tmpreg, opcode);
2849 if (isvar (&opP->disp))
2850 the_ins.reloc[the_ins.nrel - 1].n =
2851 (opcode->m_codenum) * 2 + 1;
2852 break;
2853 case 'B':
2854 if (!issbyte (tmpreg))
2855 opP->error = _("out of range");
2856 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2857 if (isvar (&opP->disp))
2858 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2859 break;
2860 case 'w':
2861 if (!isword (tmpreg))
2862 opP->error = _("out of range");
2863 insop (tmpreg, opcode);
2864 if (isvar (&opP->disp))
2865 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2866 break;
2867 case 'W':
2868 if (!issword (tmpreg))
2869 opP->error = _("out of range");
2870 insop (tmpreg, opcode);
2871 if (isvar (&opP->disp))
2872 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2873 break;
2874 case 'l':
2875 /* Because of the way insop works, we put these two out
2876 backwards. */
2877 insop (tmpreg, opcode);
2878 insop (tmpreg >> 16, opcode);
2879 if (isvar (&opP->disp))
2880 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2881 break;
2882 case '3':
2883 tmpreg &= 0xFF;
2884 case '8':
2885 case 'C':
2886 case 'j':
2887 install_operand (s[1], tmpreg);
2888 break;
2889 default:
2890 abort ();
2891 }
2892 break;
2893
2894 case '+':
2895 case '-':
2896 case 'A':
2897 case 'a':
2898 install_operand (s[1], opP->reg - ADDR);
2899 break;
2900
2901 case 'B':
2902 tmpreg = get_num (&opP->disp, 90);
2903
2904 switch (s[1])
2905 {
2906 case 'B':
2907 add_fix ('B', &opP->disp, 1, -1);
2908 break;
2909 case 'W':
2910 add_fix ('w', &opP->disp, 1, 0);
2911 addword (0);
2912 break;
2913 case 'L':
2914 long_branch:
2915 the_ins.opcode[0] |= 0xff;
2916 add_fix ('l', &opP->disp, 1, 0);
2917 addword (0);
2918 addword (0);
2919 break;
2920 case 'g': /* Conditional branch */
2921 have_disp = HAVE_LONG_CALL (current_architecture);
2922 goto var_branch;
2923
2924 case 'b': /* Unconditional branch */
2925 have_disp = HAVE_LONG_BRANCH (current_architecture);
2926 goto var_branch;
2927
2928 case 's': /* Unconditional subroutine */
2929 have_disp = HAVE_LONG_CALL (current_architecture);
2930
2931 var_branch:
2932 if (subs (&opP->disp) /* We can't relax it. */
2933 #ifdef OBJ_ELF
2934 /* If the displacement needs pic relocation it cannot be
2935 relaxed. */
2936 || opP->disp.pic_reloc != pic_none
2937 #endif
2938 || 0)
2939 {
2940 if (!have_disp)
2941 as_warn (_("Can't use long branches on this architecture"));
2942 goto long_branch;
2943 }
2944
2945 /* This could either be a symbol, or an absolute
2946 address. If it's an absolute address, turn it into
2947 an absolute jump right here and keep it out of the
2948 relaxer. */
2949 if (adds (&opP->disp) == 0)
2950 {
2951 if (the_ins.opcode[0] == 0x6000) /* jbra */
2952 the_ins.opcode[0] = 0x4EF9;
2953 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2954 the_ins.opcode[0] = 0x4EB9;
2955 else /* jCC */
2956 {
2957 the_ins.opcode[0] ^= 0x0100;
2958 the_ins.opcode[0] |= 0x0006;
2959 addword (0x4EF9);
2960 }
2961 add_fix ('l', &opP->disp, 0, 0);
2962 addword (0);
2963 addword (0);
2964 break;
2965 }
2966
2967 /* Now we know it's going into the relaxer. Now figure
2968 out which mode. We try in this order of preference:
2969 long branch, absolute jump, byte/word branches only. */
2970 if (have_disp)
2971 add_frag (adds (&opP->disp),
2972 SEXT (offs (&opP->disp)),
2973 TAB (BRANCHBWL, SZ_UNDEF));
2974 else if (! flag_keep_pcrel)
2975 {
2976 if ((the_ins.opcode[0] == 0x6000)
2977 || (the_ins.opcode[0] == 0x6100))
2978 add_frag (adds (&opP->disp),
2979 SEXT (offs (&opP->disp)),
2980 TAB (BRABSJUNC, SZ_UNDEF));
2981 else
2982 add_frag (adds (&opP->disp),
2983 SEXT (offs (&opP->disp)),
2984 TAB (BRABSJCOND, SZ_UNDEF));
2985 }
2986 else
2987 add_frag (adds (&opP->disp),
2988 SEXT (offs (&opP->disp)),
2989 TAB (BRANCHBW, SZ_UNDEF));
2990 break;
2991 case 'w':
2992 if (isvar (&opP->disp))
2993 {
2994 /* Check for DBcc instructions. We can relax them,
2995 but only if we have long branches and/or absolute
2996 jumps. */
2997 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2998 && (HAVE_LONG_BRANCH (current_architecture)
2999 || ! flag_keep_pcrel))
3000 {
3001 if (HAVE_LONG_BRANCH (current_architecture))
3002 add_frag (adds (&opP->disp),
3003 SEXT (offs (&opP->disp)),
3004 TAB (DBCCLBR, SZ_UNDEF));
3005 else
3006 add_frag (adds (&opP->disp),
3007 SEXT (offs (&opP->disp)),
3008 TAB (DBCCABSJ, SZ_UNDEF));
3009 break;
3010 }
3011 add_fix ('w', &opP->disp, 1, 0);
3012 }
3013 addword (0);
3014 break;
3015 case 'C': /* Fixed size LONG coproc branches. */
3016 add_fix ('l', &opP->disp, 1, 0);
3017 addword (0);
3018 addword (0);
3019 break;
3020 case 'c': /* Var size Coprocesssor branches. */
3021 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3022 {
3023 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3024 add_fix ('l', &opP->disp, 1, 0);
3025 addword (0);
3026 addword (0);
3027 }
3028 else
3029 add_frag (adds (&opP->disp),
3030 SEXT (offs (&opP->disp)),
3031 TAB (FBRANCH, SZ_UNDEF));
3032 break;
3033 default:
3034 abort ();
3035 }
3036 break;
3037
3038 case 'C': /* Ignore it. */
3039 break;
3040
3041 case 'd': /* JF this is a kludge. */
3042 install_operand ('s', opP->reg - ADDR);
3043 tmpreg = get_num (&opP->disp, 90);
3044 if (!issword (tmpreg))
3045 {
3046 as_warn (_("Expression out of range, using 0"));
3047 tmpreg = 0;
3048 }
3049 addword (tmpreg);
3050 break;
3051
3052 case 'D':
3053 install_operand (s[1], opP->reg - DATA);
3054 break;
3055
3056 case 'e': /* EMAC ACCx, reg/reg. */
3057 install_operand (s[1], opP->reg - ACC);
3058 break;
3059
3060 case 'E': /* Ignore it. */
3061 break;
3062
3063 case 'F':
3064 install_operand (s[1], opP->reg - FP0);
3065 break;
3066
3067 case 'g': /* EMAC ACCEXTx. */
3068 install_operand (s[1], opP->reg - ACCEXT01);
3069 break;
3070
3071 case 'G': /* Ignore it. */
3072 case 'H':
3073 break;
3074
3075 case 'I':
3076 tmpreg = opP->reg - COP0;
3077 install_operand (s[1], tmpreg);
3078 break;
3079
3080 case 'i': /* MAC/EMAC scale factor. */
3081 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3082 break;
3083
3084 case 'J': /* JF foo. */
3085 switch (opP->reg)
3086 {
3087 case SFC:
3088 tmpreg = 0x000;
3089 break;
3090 case DFC:
3091 tmpreg = 0x001;
3092 break;
3093 case CACR:
3094 tmpreg = 0x002;
3095 break;
3096 case TC:
3097 case ASID:
3098 tmpreg = 0x003;
3099 break;
3100 case ACR0:
3101 case ITT0:
3102 tmpreg = 0x004;
3103 break;
3104 case ACR1:
3105 case ITT1:
3106 tmpreg = 0x005;
3107 break;
3108 case ACR2:
3109 case DTT0:
3110 tmpreg = 0x006;
3111 break;
3112 case ACR3:
3113 case DTT1:
3114 tmpreg = 0x007;
3115 break;
3116 case BUSCR:
3117 case MMUBAR:
3118 tmpreg = 0x008;
3119 break;
3120
3121 case USP:
3122 tmpreg = 0x800;
3123 break;
3124 case VBR:
3125 tmpreg = 0x801;
3126 break;
3127 case CAAR:
3128 tmpreg = 0x802;
3129 break;
3130 case MSP:
3131 tmpreg = 0x803;
3132 break;
3133 case ISP:
3134 tmpreg = 0x804;
3135 break;
3136 case MMUSR:
3137 tmpreg = 0x805;
3138 break;
3139 case URP:
3140 tmpreg = 0x806;
3141 break;
3142 case SRP:
3143 tmpreg = 0x807;
3144 break;
3145 case PCR:
3146 tmpreg = 0x808;
3147 break;
3148 case ROMBAR:
3149 case ROMBAR0:
3150 tmpreg = 0xC00;
3151 break;
3152 case ROMBAR1:
3153 tmpreg = 0xC01;
3154 break;
3155 case FLASHBAR:
3156 case RAMBAR0:
3157 case RAMBAR_ALT:
3158 tmpreg = 0xC04;
3159 break;
3160 case RAMBAR:
3161 case RAMBAR1:
3162 tmpreg = 0xC05;
3163 break;
3164 case MPCR:
3165 tmpreg = 0xC0C;
3166 break;
3167 case EDRAMBAR:
3168 tmpreg = 0xC0D;
3169 break;
3170 case MBAR0:
3171 case MBAR2:
3172 case SECMBAR:
3173 tmpreg = 0xC0E;
3174 break;
3175 case MBAR1:
3176 case MBAR:
3177 tmpreg = 0xC0F;
3178 break;
3179 case PCR1U0:
3180 tmpreg = 0xD02;
3181 break;
3182 case PCR1L0:
3183 tmpreg = 0xD03;
3184 break;
3185 case PCR2U0:
3186 tmpreg = 0xD04;
3187 break;
3188 case PCR2L0:
3189 tmpreg = 0xD05;
3190 break;
3191 case PCR3U0:
3192 tmpreg = 0xD06;
3193 break;
3194 case PCR3L0:
3195 tmpreg = 0xD07;
3196 break;
3197 case PCR1L1:
3198 tmpreg = 0xD0A;
3199 break;
3200 case PCR1U1:
3201 tmpreg = 0xD0B;
3202 break;
3203 case PCR2L1:
3204 tmpreg = 0xD0C;
3205 break;
3206 case PCR2U1:
3207 tmpreg = 0xD0D;
3208 break;
3209 case PCR3L1:
3210 tmpreg = 0xD0E;
3211 break;
3212 case PCR3U1:
3213 tmpreg = 0xD0F;
3214 break;
3215 case CAC:
3216 tmpreg = 0xFFE;
3217 break;
3218 case MBB:
3219 tmpreg = 0xFFF;
3220 break;
3221 default:
3222 abort ();
3223 }
3224 install_operand (s[1], tmpreg);
3225 break;
3226
3227 case 'k':
3228 tmpreg = get_num (&opP->disp, 55);
3229 install_operand (s[1], tmpreg & 0x7f);
3230 break;
3231
3232 case 'l':
3233 tmpreg = opP->mask;
3234 if (s[1] == 'w')
3235 {
3236 if (tmpreg & 0x7FF0000)
3237 as_bad (_("Floating point register in register list"));
3238 insop (reverse_16_bits (tmpreg), opcode);
3239 }
3240 else
3241 {
3242 if (tmpreg & 0x700FFFF)
3243 as_bad (_("Wrong register in floating-point reglist"));
3244 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3245 }
3246 break;
3247
3248 case 'L':
3249 tmpreg = opP->mask;
3250 if (s[1] == 'w')
3251 {
3252 if (tmpreg & 0x7FF0000)
3253 as_bad (_("Floating point register in register list"));
3254 insop (tmpreg, opcode);
3255 }
3256 else if (s[1] == '8')
3257 {
3258 if (tmpreg & 0x0FFFFFF)
3259 as_bad (_("incorrect register in reglist"));
3260 install_operand (s[1], tmpreg >> 24);
3261 }
3262 else
3263 {
3264 if (tmpreg & 0x700FFFF)
3265 as_bad (_("wrong register in floating-point reglist"));
3266 else
3267 install_operand (s[1], tmpreg >> 16);
3268 }
3269 break;
3270
3271 case 'M':
3272 install_operand (s[1], get_num (&opP->disp, 60));
3273 break;
3274
3275 case 'O':
3276 tmpreg = ((opP->mode == DREG)
3277 ? 0x20 + (int) (opP->reg - DATA)
3278 : (get_num (&opP->disp, 40) & 0x1F));
3279 install_operand (s[1], tmpreg);
3280 break;
3281
3282 case 'Q':
3283 tmpreg = get_num (&opP->disp, 10);
3284 if (tmpreg == 8)
3285 tmpreg = 0;
3286 install_operand (s[1], tmpreg);
3287 break;
3288
3289 case 'R':
3290 /* This depends on the fact that ADDR registers are eight
3291 more than their corresponding DATA regs, so the result
3292 will have the ADDR_REG bit set. */
3293 install_operand (s[1], opP->reg - DATA);
3294 break;
3295
3296 case 'r':
3297 if (opP->mode == AINDR)
3298 install_operand (s[1], opP->reg - DATA);
3299 else
3300 install_operand (s[1], opP->index.reg - DATA);
3301 break;
3302
3303 case 's':
3304 if (opP->reg == FPI)
3305 tmpreg = 0x1;
3306 else if (opP->reg == FPS)
3307 tmpreg = 0x2;
3308 else if (opP->reg == FPC)
3309 tmpreg = 0x4;
3310 else
3311 abort ();
3312 install_operand (s[1], tmpreg);
3313 break;
3314
3315 case 'S': /* Ignore it. */
3316 break;
3317
3318 case 'T':
3319 install_operand (s[1], get_num (&opP->disp, 30));
3320 break;
3321
3322 case 'U': /* Ignore it. */
3323 break;
3324
3325 case 'c':
3326 switch (opP->reg)
3327 {
3328 case NC:
3329 tmpreg = 0;
3330 break;
3331 case DC:
3332 tmpreg = 1;
3333 break;
3334 case IC:
3335 tmpreg = 2;
3336 break;
3337 case BC:
3338 tmpreg = 3;
3339 break;
3340 default:
3341 as_fatal (_("failed sanity check"));
3342 } /* switch on cache token. */
3343 install_operand (s[1], tmpreg);
3344 break;
3345 #ifndef NO_68851
3346 /* JF: These are out of order, I fear. */
3347 case 'f':
3348 switch (opP->reg)
3349 {
3350 case SFC:
3351 tmpreg = 0;
3352 break;
3353 case DFC:
3354 tmpreg = 1;
3355 break;
3356 default:
3357 abort ();
3358 }
3359 install_operand (s[1], tmpreg);
3360 break;
3361
3362 case '0':
3363 case '1':
3364 case '2':
3365 switch (opP->reg)
3366 {
3367 case TC:
3368 tmpreg = 0;
3369 break;
3370 case CAL:
3371 tmpreg = 4;
3372 break;
3373 case VAL:
3374 tmpreg = 5;
3375 break;
3376 case SCC:
3377 tmpreg = 6;
3378 break;
3379 case AC:
3380 tmpreg = 7;
3381 break;
3382 default:
3383 abort ();
3384 }
3385 install_operand (s[1], tmpreg);
3386 break;
3387
3388 case 'V':
3389 if (opP->reg == VAL)
3390 break;
3391 abort ();
3392
3393 case 'W':
3394 switch (opP->reg)
3395 {
3396 case DRP:
3397 tmpreg = 1;
3398 break;
3399 case SRP:
3400 tmpreg = 2;
3401 break;
3402 case CRP:
3403 tmpreg = 3;
3404 break;
3405 default:
3406 abort ();
3407 }
3408 install_operand (s[1], tmpreg);
3409 break;
3410
3411 case 'X':
3412 switch (opP->reg)
3413 {
3414 case BAD:
3415 case BAD + 1:
3416 case BAD + 2:
3417 case BAD + 3:
3418 case BAD + 4:
3419 case BAD + 5:
3420 case BAD + 6:
3421 case BAD + 7:
3422 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3423 break;
3424
3425 case BAC:
3426 case BAC + 1:
3427 case BAC + 2:
3428 case BAC + 3:
3429 case BAC + 4:
3430 case BAC + 5:
3431 case BAC + 6:
3432 case BAC + 7:
3433 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3434 break;
3435
3436 default:
3437 abort ();
3438 }
3439 install_operand (s[1], tmpreg);
3440 break;
3441 case 'Y':
3442 know (opP->reg == PSR);
3443 break;
3444 case 'Z':
3445 know (opP->reg == PCSR);
3446 break;
3447 #endif /* m68851 */
3448 case '3':
3449 switch (opP->reg)
3450 {
3451 case TT0:
3452 tmpreg = 2;
3453 break;
3454 case TT1:
3455 tmpreg = 3;
3456 break;
3457 default:
3458 abort ();
3459 }
3460 install_operand (s[1], tmpreg);
3461 break;
3462 case 't':
3463 tmpreg = get_num (&opP->disp, 20);
3464 install_operand (s[1], tmpreg);
3465 break;
3466 case '_': /* used only for move16 absolute 32-bit address. */
3467 if (isvar (&opP->disp))
3468 add_fix ('l', &opP->disp, 0, 0);
3469 tmpreg = get_num (&opP->disp, 90);
3470 addword (tmpreg >> 16);
3471 addword (tmpreg & 0xFFFF);
3472 break;
3473 case 'u':
3474 install_operand (s[1], opP->reg - DATA0L);
3475 opP->reg -= (DATA0L);
3476 opP->reg &= 0x0F; /* remove upper/lower bit. */
3477 break;
3478 case 'x':
3479 tmpreg = get_num (&opP->disp, 80);
3480 if (tmpreg == -1)
3481 tmpreg = 0;
3482 install_operand (s[1], tmpreg);
3483 break;
3484 default:
3485 abort ();
3486 }
3487 }
3488
3489 /* By the time whe get here (FINALLY) the_ins contains the complete
3490 instruction, ready to be emitted. . . */
3491 }
3492
3493 static int
3494 reverse_16_bits (int in)
3495 {
3496 int out = 0;
3497 int n;
3498
3499 static int mask[16] =
3500 {
3501 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3502 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3503 };
3504 for (n = 0; n < 16; n++)
3505 {
3506 if (in & mask[n])
3507 out |= mask[15 - n];
3508 }
3509 return out;
3510 } /* reverse_16_bits() */
3511
3512 static int
3513 reverse_8_bits (int in)
3514 {
3515 int out = 0;
3516 int n;
3517
3518 static int mask[8] =
3519 {
3520 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3521 };
3522
3523 for (n = 0; n < 8; n++)
3524 {
3525 if (in & mask[n])
3526 out |= mask[7 - n];
3527 }
3528 return out;
3529 } /* reverse_8_bits() */
3530
3531 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3532 (that value is chosen in the frag_var call in md_assemble). TYPE
3533 is the subtype of the frag to be generated; its primary type is
3534 rs_machine_dependent.
3535
3536 The TYPE parameter is also used by md_convert_frag_1 and
3537 md_estimate_size_before_relax. The appropriate type of fixup will
3538 be emitted by md_convert_frag_1.
3539
3540 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3541 static void
3542 install_operand (int mode, int val)
3543 {
3544 switch (mode)
3545 {
3546 case 's':
3547 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3548 break;
3549 case 'd':
3550 the_ins.opcode[0] |= val << 9;
3551 break;
3552 case '1':
3553 the_ins.opcode[1] |= val << 12;
3554 break;
3555 case '2':
3556 the_ins.opcode[1] |= val << 6;
3557 break;
3558 case '3':
3559 the_ins.opcode[1] |= val;
3560 break;
3561 case '4':
3562 the_ins.opcode[2] |= val << 12;
3563 break;
3564 case '5':
3565 the_ins.opcode[2] |= val << 6;
3566 break;
3567 case '6':
3568 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3569 three words long! */
3570 the_ins.numo++;
3571 the_ins.opcode[2] |= val;
3572 break;
3573 case '7':
3574 the_ins.opcode[1] |= val << 7;
3575 break;
3576 case '8':
3577 the_ins.opcode[1] |= val << 10;
3578 break;
3579 #ifndef NO_68851
3580 case '9':
3581 the_ins.opcode[1] |= val << 5;
3582 break;
3583 #endif
3584
3585 case 't':
3586 the_ins.opcode[1] |= (val << 10) | (val << 7);
3587 break;
3588 case 'D':
3589 the_ins.opcode[1] |= (val << 12) | val;
3590 break;
3591 case 'g':
3592 the_ins.opcode[0] |= val = 0xff;
3593 break;
3594 case 'i':
3595 the_ins.opcode[0] |= val << 9;
3596 break;
3597 case 'C':
3598 the_ins.opcode[1] |= val;
3599 break;
3600 case 'j':
3601 the_ins.opcode[1] |= val;
3602 the_ins.numo++; /* What a hack. */
3603 break;
3604 case 'k':
3605 the_ins.opcode[1] |= val << 4;
3606 break;
3607 case 'b':
3608 case 'w':
3609 case 'W':
3610 case 'l':
3611 break;
3612 case 'e':
3613 the_ins.opcode[0] |= (val << 6);
3614 break;
3615 case 'L':
3616 the_ins.opcode[1] = (val >> 16);
3617 the_ins.opcode[2] = val & 0xffff;
3618 break;
3619 case 'm':
3620 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3621 the_ins.opcode[0] |= ((val & 0x7) << 9);
3622 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3623 break;
3624 case 'n': /* MAC/EMAC Rx on !load. */
3625 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3626 the_ins.opcode[0] |= ((val & 0x7) << 9);
3627 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3628 break;
3629 case 'o': /* MAC/EMAC Rx on load. */
3630 the_ins.opcode[1] |= val << 12;
3631 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3632 break;
3633 case 'M': /* MAC/EMAC Ry on !load. */
3634 the_ins.opcode[0] |= (val & 0xF);
3635 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3636 break;
3637 case 'N': /* MAC/EMAC Ry on load. */
3638 the_ins.opcode[1] |= (val & 0xF);
3639 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3640 break;
3641 case 'h':
3642 the_ins.opcode[1] |= ((val != 1) << 10);
3643 break;
3644 case 'F':
3645 the_ins.opcode[0] |= ((val & 0x3) << 9);
3646 break;
3647 case 'f':
3648 the_ins.opcode[0] |= ((val & 0x3) << 0);
3649 break;
3650 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3651 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3652 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3653 break;
3654 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3655 the_ins.opcode[0] |= ((val & 0x1) << 7);
3656 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3657 break;
3658 case 'I':
3659 the_ins.opcode[1] |= ((val & 0x3) << 9);
3660 break;
3661 case ']':
3662 the_ins.opcode[0] |= (val & 0x1) <<10;
3663 break;
3664 case 'c':
3665 default:
3666 as_fatal (_("failed sanity check."));
3667 }
3668 }
3669
3670 static void
3671 install_gen_operand (int mode, int val)
3672 {
3673 switch (mode)
3674 {
3675 case '/': /* Special for mask loads for mac/msac insns with
3676 possible mask; trailing_ampersend set in bit 8. */
3677 the_ins.opcode[0] |= (val & 0x3f);
3678 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3679 break;
3680 case 's':
3681 the_ins.opcode[0] |= val;
3682 break;
3683 case 'd':
3684 /* This is a kludge!!! */
3685 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3686 break;
3687 case 'b':
3688 case 'w':
3689 case 'l':
3690 case 'f':
3691 case 'F':
3692 case 'x':
3693 case 'p':
3694 the_ins.opcode[0] |= val;
3695 break;
3696 /* more stuff goes here. */
3697 default:
3698 as_fatal (_("failed sanity check."));
3699 }
3700 }
3701
3702 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3703 then deal with the bitfield hack. */
3704
3705 static char *
3706 crack_operand (char *str, struct m68k_op *opP)
3707 {
3708 register int parens;
3709 register int c;
3710 register char *beg_str;
3711 int inquote = 0;
3712
3713 if (!str)
3714 {
3715 return str;
3716 }
3717 beg_str = str;
3718 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3719 {
3720 if (! inquote)
3721 {
3722 if (*str == '(')
3723 parens++;
3724 else if (*str == ')')
3725 {
3726 if (!parens)
3727 { /* ERROR. */
3728 opP->error = _("Extra )");
3729 return str;
3730 }
3731 --parens;
3732 }
3733 }
3734 if (flag_mri && *str == '\'')
3735 inquote = ! inquote;
3736 }
3737 if (!*str && parens)
3738 { /* ERROR. */
3739 opP->error = _("Missing )");
3740 return str;
3741 }
3742 c = *str;
3743 *str = '\0';
3744 if (m68k_ip_op (beg_str, opP) != 0)
3745 {
3746 *str = c;
3747 return str;
3748 }
3749 *str = c;
3750 if (c == '}')
3751 c = *++str; /* JF bitfield hack. */
3752 if (c)
3753 {
3754 c = *++str;
3755 if (!c)
3756 as_bad (_("Missing operand"));
3757 }
3758
3759 /* Detect MRI REG symbols and convert them to REGLSTs. */
3760 if (opP->mode == CONTROL && (int)opP->reg < 0)
3761 {
3762 opP->mode = REGLST;
3763 opP->mask = ~(int)opP->reg;
3764 opP->reg = 0;
3765 }
3766
3767 return str;
3768 }
3769
3770 /* This is the guts of the machine-dependent assembler. STR points to a
3771 machine dependent instruction. This function is supposed to emit
3772 the frags/bytes it assembles to.
3773 */
3774
3775 static void
3776 insert_reg (const char *regname, int regnum)
3777 {
3778 char buf[100];
3779 int i;
3780
3781 #ifdef REGISTER_PREFIX
3782 if (!flag_reg_prefix_optional)
3783 {
3784 buf[0] = REGISTER_PREFIX;
3785 strcpy (buf + 1, regname);
3786 regname = buf;
3787 }
3788 #endif
3789
3790 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3791 &zero_address_frag));
3792
3793 for (i = 0; regname[i]; i++)
3794 buf[i] = TOUPPER (regname[i]);
3795 buf[i] = '\0';
3796
3797 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3798 &zero_address_frag));
3799 }
3800
3801 struct init_entry
3802 {
3803 const char *name;
3804 int number;
3805 };
3806
3807 static const struct init_entry init_table[] =
3808 {
3809 { "d0", DATA0 },
3810 { "d1", DATA1 },
3811 { "d2", DATA2 },
3812 { "d3", DATA3 },
3813 { "d4", DATA4 },
3814 { "d5", DATA5 },
3815 { "d6", DATA6 },
3816 { "d7", DATA7 },
3817 { "a0", ADDR0 },
3818 { "a1", ADDR1 },
3819 { "a2", ADDR2 },
3820 { "a3", ADDR3 },
3821 { "a4", ADDR4 },
3822 { "a5", ADDR5 },
3823 { "a6", ADDR6 },
3824 { "fp", ADDR6 },
3825 { "a7", ADDR7 },
3826 { "sp", ADDR7 },
3827 { "ssp", ADDR7 },
3828 { "fp0", FP0 },
3829 { "fp1", FP1 },
3830 { "fp2", FP2 },
3831 { "fp3", FP3 },
3832 { "fp4", FP4 },
3833 { "fp5", FP5 },
3834 { "fp6", FP6 },
3835 { "fp7", FP7 },
3836 { "fpi", FPI },
3837 { "fpiar", FPI },
3838 { "fpc", FPI },
3839 { "fps", FPS },
3840 { "fpsr", FPS },
3841 { "fpc", FPC },
3842 { "fpcr", FPC },
3843 { "control", FPC },
3844 { "status", FPS },
3845 { "iaddr", FPI },
3846
3847 { "cop0", COP0 },
3848 { "cop1", COP1 },
3849 { "cop2", COP2 },
3850 { "cop3", COP3 },
3851 { "cop4", COP4 },
3852 { "cop5", COP5 },
3853 { "cop6", COP6 },
3854 { "cop7", COP7 },
3855 { "pc", PC },
3856 { "zpc", ZPC },
3857 { "sr", SR },
3858
3859 { "ccr", CCR },
3860 { "cc", CCR },
3861
3862 { "acc", ACC },
3863 { "acc0", ACC },
3864 { "acc1", ACC1 },
3865 { "acc2", ACC2 },
3866 { "acc3", ACC3 },
3867 { "accext01", ACCEXT01 },
3868 { "accext23", ACCEXT23 },
3869 { "macsr", MACSR },
3870 { "mask", MASK },
3871
3872 /* Control registers. */
3873 { "sfc", SFC }, /* Source Function Code. */
3874 { "sfcr", SFC },
3875 { "dfc", DFC }, /* Destination Function Code. */
3876 { "dfcr", DFC },
3877 { "cacr", CACR }, /* Cache Control Register. */
3878 { "caar", CAAR }, /* Cache Address Register. */
3879
3880 { "usp", USP }, /* User Stack Pointer. */
3881 { "vbr", VBR }, /* Vector Base Register. */
3882 { "msp", MSP }, /* Master Stack Pointer. */
3883 { "isp", ISP }, /* Interrupt Stack Pointer. */
3884
3885 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3886 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3887 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3888 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3889
3890 /* 68ec040 versions of same */
3891 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3892 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3893 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3894 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3895
3896 /* Coldfire versions of same. The ColdFire programmer's reference
3897 manual indicated that the order is 2,3,0,1, but Ken Rose
3898 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3899 { "acr0", ACR0 }, /* Access Control Unit 0. */
3900 { "acr1", ACR1 }, /* Access Control Unit 1. */
3901 { "acr2", ACR2 }, /* Access Control Unit 2. */
3902 { "acr3", ACR3 }, /* Access Control Unit 3. */
3903
3904 { "tc", TC }, /* MMU Translation Control Register. */
3905 { "tcr", TC },
3906 { "asid", ASID },
3907
3908 { "mmusr", MMUSR }, /* MMU Status Register. */
3909 { "srp", SRP }, /* User Root Pointer. */
3910 { "urp", URP }, /* Supervisor Root Pointer. */
3911
3912 { "buscr", BUSCR },
3913 { "mmubar", MMUBAR },
3914 { "pcr", PCR },
3915
3916 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3917 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3918 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3919 { "mbar", MBAR }, /* Module Base Address Register. */
3920
3921 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3922 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3923 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3924 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3925 { "mpcr", MPCR }, /* mcfv4e registers. */
3926 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3927 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3928 { "asid", TC }, /* mcfv4e registers. */
3929 { "mmubar", BUSCR }, /* mcfv4e registers. */
3930 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3931 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3932 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3933 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3934 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3935 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3936 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3937 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3938 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3939 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3940 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3941 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3942
3943 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3944 { "rambar", RAMBAR }, /* mcf528x registers. */
3945
3946 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3947
3948 { "cac", CAC }, /* fido registers. */
3949 { "mbb", MBB }, /* fido registers. */
3950 /* End of control registers. */
3951
3952 { "ac", AC },
3953 { "bc", BC },
3954 { "cal", CAL },
3955 { "crp", CRP },
3956 { "drp", DRP },
3957 { "pcsr", PCSR },
3958 { "psr", PSR },
3959 { "scc", SCC },
3960 { "val", VAL },
3961 { "bad0", BAD0 },
3962 { "bad1", BAD1 },
3963 { "bad2", BAD2 },
3964 { "bad3", BAD3 },
3965 { "bad4", BAD4 },
3966 { "bad5", BAD5 },
3967 { "bad6", BAD6 },
3968 { "bad7", BAD7 },
3969 { "bac0", BAC0 },
3970 { "bac1", BAC1 },
3971 { "bac2", BAC2 },
3972 { "bac3", BAC3 },
3973 { "bac4", BAC4 },
3974 { "bac5", BAC5 },
3975 { "bac6", BAC6 },
3976 { "bac7", BAC7 },
3977
3978 { "ic", IC },
3979 { "dc", DC },
3980 { "nc", NC },
3981
3982 { "tt0", TT0 },
3983 { "tt1", TT1 },
3984 /* 68ec030 versions of same. */
3985 { "ac0", TT0 },
3986 { "ac1", TT1 },
3987 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3988 { "acusr", PSR },
3989
3990 /* Suppressed data and address registers. */
3991 { "zd0", ZDATA0 },
3992 { "zd1", ZDATA1 },
3993 { "zd2", ZDATA2 },
3994 { "zd3", ZDATA3 },
3995 { "zd4", ZDATA4 },
3996 { "zd5", ZDATA5 },
3997 { "zd6", ZDATA6 },
3998 { "zd7", ZDATA7 },
3999 { "za0", ZADDR0 },
4000 { "za1", ZADDR1 },
4001 { "za2", ZADDR2 },
4002 { "za3", ZADDR3 },
4003 { "za4", ZADDR4 },
4004 { "za5", ZADDR5 },
4005 { "za6", ZADDR6 },
4006 { "za7", ZADDR7 },
4007
4008 /* Upper and lower data and address registers, used by macw and msacw. */
4009 { "d0l", DATA0L },
4010 { "d1l", DATA1L },
4011 { "d2l", DATA2L },
4012 { "d3l", DATA3L },
4013 { "d4l", DATA4L },
4014 { "d5l", DATA5L },
4015 { "d6l", DATA6L },
4016 { "d7l", DATA7L },
4017
4018 { "a0l", ADDR0L },
4019 { "a1l", ADDR1L },
4020 { "a2l", ADDR2L },
4021 { "a3l", ADDR3L },
4022 { "a4l", ADDR4L },
4023 { "a5l", ADDR5L },
4024 { "a6l", ADDR6L },
4025 { "a7l", ADDR7L },
4026
4027 { "d0u", DATA0U },
4028 { "d1u", DATA1U },
4029 { "d2u", DATA2U },
4030 { "d3u", DATA3U },
4031 { "d4u", DATA4U },
4032 { "d5u", DATA5U },
4033 { "d6u", DATA6U },
4034 { "d7u", DATA7U },
4035
4036 { "a0u", ADDR0U },
4037 { "a1u", ADDR1U },
4038 { "a2u", ADDR2U },
4039 { "a3u", ADDR3U },
4040 { "a4u", ADDR4U },
4041 { "a5u", ADDR5U },
4042 { "a6u", ADDR6U },
4043 { "a7u", ADDR7U },
4044
4045 { 0, 0 }
4046 };
4047
4048 static void
4049 init_regtable (void)
4050 {
4051 int i;
4052 for (i = 0; init_table[i].name; i++)
4053 insert_reg (init_table[i].name, init_table[i].number);
4054 }
4055
4056 void
4057 md_assemble (char *str)
4058 {
4059 const char *er;
4060 short *fromP;
4061 char *toP = NULL;
4062 int m, n = 0;
4063 char *to_beg_P;
4064 int shorts_this_frag;
4065 fixS *fixP;
4066
4067 if (!selected_cpu && !selected_arch)
4068 {
4069 /* We've not selected an architecture yet. Set the default
4070 now. We do this lazily so that an initial .cpu or .arch directive
4071 can specify. */
4072 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4073 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4074 }
4075 if (!initialized)
4076 m68k_init_arch ();
4077
4078 /* In MRI mode, the instruction and operands are separated by a
4079 space. Anything following the operands is a comment. The label
4080 has already been removed. */
4081 if (flag_mri)
4082 {
4083 char *s;
4084 int fields = 0;
4085 int infield = 0;
4086 int inquote = 0;
4087
4088 for (s = str; *s != '\0'; s++)
4089 {
4090 if ((*s == ' ' || *s == '\t') && ! inquote)
4091 {
4092 if (infield)
4093 {
4094 ++fields;
4095 if (fields >= 2)
4096 {
4097 *s = '\0';
4098 break;
4099 }
4100 infield = 0;
4101 }
4102 }
4103 else
4104 {
4105 if (! infield)
4106 infield = 1;
4107 if (*s == '\'')
4108 inquote = ! inquote;
4109 }
4110 }
4111 }
4112
4113 memset (&the_ins, '\0', sizeof (the_ins));
4114 m68k_ip (str);
4115 er = the_ins.error;
4116 if (!er)
4117 {
4118 for (n = 0; n < the_ins.numargs; n++)
4119 if (the_ins.operands[n].error)
4120 {
4121 er = the_ins.operands[n].error;
4122 break;
4123 }
4124 }
4125 if (er)
4126 {
4127 as_bad (_("%s -- statement `%s' ignored"), er, str);
4128 return;
4129 }
4130
4131 /* If there is a current label, record that it marks an instruction. */
4132 if (current_label != NULL)
4133 {
4134 current_label->text = 1;
4135 current_label = NULL;
4136 }
4137
4138 #ifdef OBJ_ELF
4139 /* Tie dwarf2 debug info to the address at the start of the insn. */
4140 dwarf2_emit_insn (0);
4141 #endif
4142
4143 if (the_ins.nfrag == 0)
4144 {
4145 /* No frag hacking involved; just put it out. */
4146 toP = frag_more (2 * the_ins.numo);
4147 fromP = &the_ins.opcode[0];
4148 for (m = the_ins.numo; m; --m)
4149 {
4150 md_number_to_chars (toP, (long) (*fromP), 2);
4151 toP += 2;
4152 fromP++;
4153 }
4154 /* Put out symbol-dependent info. */
4155 for (m = 0; m < the_ins.nrel; m++)
4156 {
4157 switch (the_ins.reloc[m].wid)
4158 {
4159 case 'B':
4160 n = 1;
4161 break;
4162 case 'b':
4163 n = 1;
4164 break;
4165 case '3':
4166 n = 1;
4167 break;
4168 case 'w':
4169 case 'W':
4170 n = 2;
4171 break;
4172 case 'l':
4173 n = 4;
4174 break;
4175 default:
4176 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4177 the_ins.reloc[m].wid);
4178 }
4179
4180 fixP = fix_new_exp (frag_now,
4181 ((toP - frag_now->fr_literal)
4182 - the_ins.numo * 2 + the_ins.reloc[m].n),
4183 n,
4184 &the_ins.reloc[m].exp,
4185 the_ins.reloc[m].pcrel,
4186 get_reloc_code (n, the_ins.reloc[m].pcrel,
4187 the_ins.reloc[m].pic_reloc));
4188 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4189 if (the_ins.reloc[m].wid == 'B')
4190 fixP->fx_signed = 1;
4191 }
4192 return;
4193 }
4194
4195 /* There's some frag hacking. */
4196 {
4197 /* Calculate the max frag size. */
4198 int wid;
4199
4200 wid = 2 * the_ins.fragb[0].fragoff;
4201 for (n = 1; n < the_ins.nfrag; n++)
4202 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4203 /* frag_var part. */
4204 wid += 10;
4205 /* Make sure the whole insn fits in one chunk, in particular that
4206 the var part is attached, as we access one byte before the
4207 variable frag for byte branches. */
4208 frag_grow (wid);
4209 }
4210
4211 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4212 {
4213 int wid;
4214
4215 if (n == 0)
4216 wid = 2 * the_ins.fragb[n].fragoff;
4217 else
4218 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4219 toP = frag_more (wid);
4220 to_beg_P = toP;
4221 shorts_this_frag = 0;
4222 for (m = wid / 2; m; --m)
4223 {
4224 md_number_to_chars (toP, (long) (*fromP), 2);
4225 toP += 2;
4226 fromP++;
4227 shorts_this_frag++;
4228 }
4229 for (m = 0; m < the_ins.nrel; m++)
4230 {
4231 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4232 {
4233 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4234 break;
4235 }
4236 wid = the_ins.reloc[m].wid;
4237 if (wid == 0)
4238 continue;
4239 the_ins.reloc[m].wid = 0;
4240 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4241
4242 fixP = fix_new_exp (frag_now,
4243 ((toP - frag_now->fr_literal)
4244 - the_ins.numo * 2 + the_ins.reloc[m].n),
4245 wid,
4246 &the_ins.reloc[m].exp,
4247 the_ins.reloc[m].pcrel,
4248 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4249 the_ins.reloc[m].pic_reloc));
4250 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4251 }
4252 (void) frag_var (rs_machine_dependent, 10, 0,
4253 (relax_substateT) (the_ins.fragb[n].fragty),
4254 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4255 }
4256 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4257 shorts_this_frag = 0;
4258 if (n)
4259 {
4260 toP = frag_more (n * 2);
4261 while (n--)
4262 {
4263 md_number_to_chars (toP, (long) (*fromP), 2);
4264 toP += 2;
4265 fromP++;
4266 shorts_this_frag++;
4267 }
4268 }
4269 for (m = 0; m < the_ins.nrel; m++)
4270 {
4271 int wid;
4272
4273 wid = the_ins.reloc[m].wid;
4274 if (wid == 0)
4275 continue;
4276 the_ins.reloc[m].wid = 0;
4277 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4278
4279 fixP = fix_new_exp (frag_now,
4280 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4281 - shorts_this_frag * 2),
4282 wid,
4283 &the_ins.reloc[m].exp,
4284 the_ins.reloc[m].pcrel,
4285 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4286 the_ins.reloc[m].pic_reloc));
4287 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4288 }
4289 }
4290
4291 /* Comparison function used by qsort to rank the opcode entries by name. */
4292
4293 static int
4294 m68k_compare_opcode (const void * v1, const void * v2)
4295 {
4296 struct m68k_opcode * op1, * op2;
4297 int ret;
4298
4299 if (v1 == v2)
4300 return 0;
4301
4302 op1 = *(struct m68k_opcode **) v1;
4303 op2 = *(struct m68k_opcode **) v2;
4304
4305 /* Compare the two names. If different, return the comparison.
4306 If the same, return the order they are in the opcode table. */
4307 ret = strcmp (op1->name, op2->name);
4308 if (ret)
4309 return ret;
4310 if (op1 < op2)
4311 return -1;
4312 return 1;
4313 }
4314
4315 void
4316 md_begin (void)
4317 {
4318 const struct m68k_opcode *ins;
4319 struct m68k_incant *hack, *slak;
4320 const char *retval = 0; /* Empty string, or error msg text. */
4321 int i;
4322
4323 /* Set up hash tables with 68000 instructions.
4324 similar to what the vax assembler does. */
4325 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4326 a copy of it at runtime, adding in the information we want but isn't
4327 there. I think it'd be better to have an awk script hack the table
4328 at compile time. Or even just xstr the table and use it as-is. But
4329 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4330 names. */
4331
4332 if (flag_mri)
4333 {
4334 flag_reg_prefix_optional = 1;
4335 m68k_abspcadd = 1;
4336 if (! m68k_rel32_from_cmdline)
4337 m68k_rel32 = 0;
4338 }
4339
4340 /* First sort the opcode table into alphabetical order to seperate
4341 the order that the assembler wants to see the opcodes from the
4342 order that the disassembler wants to see them. */
4343 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4344 if (!m68k_sorted_opcodes)
4345 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4346 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4347
4348 for (i = m68k_numopcodes; i--;)
4349 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4350
4351 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4352 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4353
4354 op_hash = hash_new ();
4355
4356 obstack_begin (&robyn, 4000);
4357 for (i = 0; i < m68k_numopcodes; i++)
4358 {
4359 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4360 do
4361 {
4362 ins = m68k_sorted_opcodes[i];
4363
4364 /* We *could* ignore insns that don't match our
4365 arch here by just leaving them out of the hash. */
4366 slak->m_operands = ins->args;
4367 slak->m_opnum = strlen (slak->m_operands) / 2;
4368 slak->m_arch = ins->arch;
4369 slak->m_opcode = ins->opcode;
4370 /* This is kludgey. */
4371 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4372 if (i + 1 != m68k_numopcodes
4373 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4374 {
4375 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4376 i++;
4377 }
4378 else
4379 slak->m_next = 0;
4380 slak = slak->m_next;
4381 }
4382 while (slak);
4383
4384 retval = hash_insert (op_hash, ins->name, (char *) hack);
4385 if (retval)
4386 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4387 }
4388
4389 for (i = 0; i < m68k_numaliases; i++)
4390 {
4391 const char *name = m68k_opcode_aliases[i].primary;
4392 const char *alias = m68k_opcode_aliases[i].alias;
4393 PTR val = hash_find (op_hash, name);
4394
4395 if (!val)
4396 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4397 retval = hash_insert (op_hash, alias, val);
4398 if (retval)
4399 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4400 }
4401
4402 /* In MRI mode, all unsized branches are variable sized. Normally,
4403 they are word sized. */
4404 if (flag_mri)
4405 {
4406 static struct m68k_opcode_alias mri_aliases[] =
4407 {
4408 { "bhi", "jhi", },
4409 { "bls", "jls", },
4410 { "bcc", "jcc", },
4411 { "bcs", "jcs", },
4412 { "bne", "jne", },
4413 { "beq", "jeq", },
4414 { "bvc", "jvc", },
4415 { "bvs", "jvs", },
4416 { "bpl", "jpl", },
4417 { "bmi", "jmi", },
4418 { "bge", "jge", },
4419 { "blt", "jlt", },
4420 { "bgt", "jgt", },
4421 { "ble", "jle", },
4422 { "bra", "jra", },
4423 { "bsr", "jbsr", },
4424 };
4425
4426 for (i = 0;
4427 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4428 i++)
4429 {
4430 const char *name = mri_aliases[i].primary;
4431 const char *alias = mri_aliases[i].alias;
4432 PTR val = hash_find (op_hash, name);
4433
4434 if (!val)
4435 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4436 retval = hash_jam (op_hash, alias, val);
4437 if (retval)
4438 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4439 }
4440 }
4441
4442 for (i = 0; i < (int) sizeof (notend_table); i++)
4443 {
4444 notend_table[i] = 0;
4445 alt_notend_table[i] = 0;
4446 }
4447
4448 notend_table[','] = 1;
4449 notend_table['{'] = 1;
4450 notend_table['}'] = 1;
4451 alt_notend_table['a'] = 1;
4452 alt_notend_table['A'] = 1;
4453 alt_notend_table['d'] = 1;
4454 alt_notend_table['D'] = 1;
4455 alt_notend_table['#'] = 1;
4456 alt_notend_table['&'] = 1;
4457 alt_notend_table['f'] = 1;
4458 alt_notend_table['F'] = 1;
4459 #ifdef REGISTER_PREFIX
4460 alt_notend_table[REGISTER_PREFIX] = 1;
4461 #endif
4462
4463 /* We need to put '(' in alt_notend_table to handle
4464 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4465 alt_notend_table['('] = 1;
4466
4467 /* We need to put '@' in alt_notend_table to handle
4468 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4469 alt_notend_table['@'] = 1;
4470
4471 /* We need to put digits in alt_notend_table to handle
4472 bfextu %d0{24:1},%d0 */
4473 alt_notend_table['0'] = 1;
4474 alt_notend_table['1'] = 1;
4475 alt_notend_table['2'] = 1;
4476 alt_notend_table['3'] = 1;
4477 alt_notend_table['4'] = 1;
4478 alt_notend_table['5'] = 1;
4479 alt_notend_table['6'] = 1;
4480 alt_notend_table['7'] = 1;
4481 alt_notend_table['8'] = 1;
4482 alt_notend_table['9'] = 1;
4483
4484 #ifndef MIT_SYNTAX_ONLY
4485 /* Insert pseudo ops, these have to go into the opcode table since
4486 gas expects pseudo ops to start with a dot. */
4487 {
4488 int n = 0;
4489
4490 while (mote_pseudo_table[n].poc_name)
4491 {
4492 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4493 hash_insert (op_hash,
4494 mote_pseudo_table[n].poc_name, (char *) hack);
4495 hack->m_operands = 0;
4496 hack->m_opnum = n;
4497 n++;
4498 }
4499 }
4500 #endif
4501
4502 init_regtable ();
4503
4504 #ifdef OBJ_ELF
4505 record_alignment (text_section, 2);
4506 record_alignment (data_section, 2);
4507 record_alignment (bss_section, 2);
4508 #endif
4509 }
4510
4511 \f
4512 /* This is called when a label is defined. */
4513
4514 void
4515 m68k_frob_label (symbolS *sym)
4516 {
4517 struct label_line *n;
4518
4519 n = (struct label_line *) xmalloc (sizeof *n);
4520 n->next = labels;
4521 n->label = sym;
4522 as_where (&n->file, &n->line);
4523 n->text = 0;
4524 labels = n;
4525 current_label = n;
4526
4527 #ifdef OBJ_ELF
4528 dwarf2_emit_label (sym);
4529 #endif
4530 }
4531
4532 /* This is called when a value that is not an instruction is emitted. */
4533
4534 void
4535 m68k_flush_pending_output (void)
4536 {
4537 current_label = NULL;
4538 }
4539
4540 /* This is called at the end of the assembly, when the final value of
4541 the label is known. We warn if this is a text symbol aligned at an
4542 odd location. */
4543
4544 void
4545 m68k_frob_symbol (symbolS *sym)
4546 {
4547 if (S_GET_SEGMENT (sym) == reg_section
4548 && (int) S_GET_VALUE (sym) < 0)
4549 {
4550 S_SET_SEGMENT (sym, absolute_section);
4551 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4552 }
4553 else if ((S_GET_VALUE (sym) & 1) != 0)
4554 {
4555 struct label_line *l;
4556
4557 for (l = labels; l != NULL; l = l->next)
4558 {
4559 if (l->label == sym)
4560 {
4561 if (l->text)
4562 as_warn_where (l->file, l->line,
4563 _("text label `%s' aligned to odd boundary"),
4564 S_GET_NAME (sym));
4565 break;
4566 }
4567 }
4568 }
4569 }
4570 \f
4571 /* This is called if we go in or out of MRI mode because of the .mri
4572 pseudo-op. */
4573
4574 void
4575 m68k_mri_mode_change (int on)
4576 {
4577 if (on)
4578 {
4579 if (! flag_reg_prefix_optional)
4580 {
4581 flag_reg_prefix_optional = 1;
4582 #ifdef REGISTER_PREFIX
4583 init_regtable ();
4584 #endif
4585 }
4586 m68k_abspcadd = 1;
4587 if (! m68k_rel32_from_cmdline)
4588 m68k_rel32 = 0;
4589 }
4590 else
4591 {
4592 if (! reg_prefix_optional_seen)
4593 {
4594 #ifdef REGISTER_PREFIX_OPTIONAL
4595 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4596 #else
4597 flag_reg_prefix_optional = 0;
4598 #endif
4599 #ifdef REGISTER_PREFIX
4600 init_regtable ();
4601 #endif
4602 }
4603 m68k_abspcadd = 0;
4604 if (! m68k_rel32_from_cmdline)
4605 m68k_rel32 = 1;
4606 }
4607 }
4608
4609 /* Equal to MAX_PRECISION in atof-ieee.c. */
4610 #define MAX_LITTLENUMS 6
4611
4612 /* Turn a string in input_line_pointer into a floating point constant
4613 of type TYPE, and store the appropriate bytes in *LITP. The number
4614 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4615 returned, or NULL on OK. */
4616
4617 char *
4618 md_atof (int type, char *litP, int *sizeP)
4619 {
4620 int prec;
4621 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4622 LITTLENUM_TYPE *wordP;
4623 char *t;
4624
4625 switch (type)
4626 {
4627 case 'f':
4628 case 'F':
4629 case 's':
4630 case 'S':
4631 prec = 2;
4632 break;
4633
4634 case 'd':
4635 case 'D':
4636 case 'r':
4637 case 'R':
4638 prec = 4;
4639 break;
4640
4641 case 'x':
4642 case 'X':
4643 prec = 6;
4644 break;
4645
4646 case 'p':
4647 case 'P':
4648 prec = 6;
4649 break;
4650
4651 default:
4652 *sizeP = 0;
4653 return _("Bad call to MD_ATOF()");
4654 }
4655 t = atof_ieee (input_line_pointer, type, words);
4656 if (t)
4657 input_line_pointer = t;
4658
4659 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4660 for (wordP = words; prec--;)
4661 {
4662 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4663 litP += sizeof (LITTLENUM_TYPE);
4664 }
4665 return 0;
4666 }
4667
4668 void
4669 md_number_to_chars (char *buf, valueT val, int n)
4670 {
4671 number_to_chars_bigendian (buf, val, n);
4672 }
4673
4674 void
4675 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4676 {
4677 offsetT val = *valP;
4678 addressT upper_limit;
4679 offsetT lower_limit;
4680
4681 /* This is unnecessary but it convinces the native rs6000 compiler
4682 to generate the code we want. */
4683 char *buf = fixP->fx_frag->fr_literal;
4684 buf += fixP->fx_where;
4685 /* End ibm compiler workaround. */
4686
4687 val = SEXT (val);
4688
4689 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4690 fixP->fx_done = 1;
4691
4692 #ifdef OBJ_ELF
4693 if (fixP->fx_addsy)
4694 {
4695 memset (buf, 0, fixP->fx_size);
4696 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4697
4698 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4699 && !S_IS_DEFINED (fixP->fx_addsy)
4700 && !S_IS_WEAK (fixP->fx_addsy))
4701 S_SET_WEAK (fixP->fx_addsy);
4702 return;
4703 }
4704 #elif defined(OBJ_AOUT)
4705 /* PR gas/3041 Always put zero values into frags referencing a weak symbol. */
4706 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4707 {
4708 memset (buf, 0, fixP->fx_size);
4709 return;
4710 }
4711 #endif
4712
4713 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4714 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4715 return;
4716
4717 switch (fixP->fx_size)
4718 {
4719 /* The cast to offsetT below are necessary to make code
4720 correct for machines where ints are smaller than offsetT. */
4721 case 1:
4722 *buf++ = val;
4723 upper_limit = 0x7f;
4724 lower_limit = - (offsetT) 0x80;
4725 break;
4726 case 2:
4727 *buf++ = (val >> 8);
4728 *buf++ = val;
4729 upper_limit = 0x7fff;
4730 lower_limit = - (offsetT) 0x8000;
4731 break;
4732 case 4:
4733 *buf++ = (val >> 24);
4734 *buf++ = (val >> 16);
4735 *buf++ = (val >> 8);
4736 *buf++ = val;
4737 upper_limit = 0x7fffffff;
4738 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4739 break;
4740 default:
4741 BAD_CASE (fixP->fx_size);
4742 }
4743
4744 /* Fix up a negative reloc. */
4745 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4746 {
4747 fixP->fx_addsy = fixP->fx_subsy;
4748 fixP->fx_subsy = NULL;
4749 fixP->fx_tcbit = 1;
4750 }
4751
4752 /* For non-pc-relative values, it's conceivable we might get something
4753 like "0xff" for a byte field. So extend the upper part of the range
4754 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4755 so that we can do any range checking at all. */
4756 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4757 upper_limit = upper_limit * 2 + 1;
4758
4759 if ((addressT) val > upper_limit
4760 && (val > 0 || val < lower_limit))
4761 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4762
4763 /* A one byte PC-relative reloc means a short branch. We can't use
4764 a short branch with a value of 0 or -1, because those indicate
4765 different opcodes (branches with longer offsets). fixup_segment
4766 in write.c may have clobbered fx_pcrel, so we need to examine the
4767 reloc type. */
4768 if ((fixP->fx_pcrel
4769 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4770 && fixP->fx_size == 1
4771 && (fixP->fx_addsy == NULL
4772 || S_IS_DEFINED (fixP->fx_addsy))
4773 && (val == 0 || val == -1))
4774 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4775 }
4776
4777 /* *fragP has been relaxed to its final size, and now needs to have
4778 the bytes inside it modified to conform to the new size There is UGLY
4779 MAGIC here. ..
4780 */
4781 static void
4782 md_convert_frag_1 (fragS *fragP)
4783 {
4784 long disp;
4785 fixS *fixP;
4786
4787 /* Address in object code of the displacement. */
4788 register int object_address = fragP->fr_fix + fragP->fr_address;
4789
4790 /* Address in gas core of the place to store the displacement. */
4791 /* This convinces the native rs6000 compiler to generate the code we
4792 want. */
4793 register char *buffer_address = fragP->fr_literal;
4794 buffer_address += fragP->fr_fix;
4795 /* End ibm compiler workaround. */
4796
4797 /* The displacement of the address, from current location. */
4798 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4799 disp = (disp + fragP->fr_offset) - object_address;
4800
4801 switch (fragP->fr_subtype)
4802 {
4803 case TAB (BRANCHBWL, BYTE):
4804 case TAB (BRABSJUNC, BYTE):
4805 case TAB (BRABSJCOND, BYTE):
4806 case TAB (BRANCHBW, BYTE):
4807 know (issbyte (disp));
4808 if (disp == 0)
4809 as_bad_where (fragP->fr_file, fragP->fr_line,
4810 _("short branch with zero offset: use :w"));
4811 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4812 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4813 fixP->fx_pcrel_adjust = -1;
4814 break;
4815 case TAB (BRANCHBWL, SHORT):
4816 case TAB (BRABSJUNC, SHORT):
4817 case TAB (BRABSJCOND, SHORT):
4818 case TAB (BRANCHBW, SHORT):
4819 fragP->fr_opcode[1] = 0x00;
4820 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4821 1, RELAX_RELOC_PC16);
4822 fragP->fr_fix += 2;
4823 break;
4824 case TAB (BRANCHBWL, LONG):
4825 fragP->fr_opcode[1] = (char) 0xFF;
4826 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4827 1, RELAX_RELOC_PC32);
4828 fragP->fr_fix += 4;
4829 break;
4830 case TAB (BRABSJUNC, LONG):
4831 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4832 {
4833 if (flag_keep_pcrel)
4834 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4835 fragP->fr_opcode[0] = 0x4E;
4836 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4837 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4838 0, RELAX_RELOC_ABS32);
4839 fragP->fr_fix += 4;
4840 }
4841 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4842 {
4843 if (flag_keep_pcrel)
4844 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4845 fragP->fr_opcode[0] = 0x4E;
4846 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4847 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4848 0, RELAX_RELOC_ABS32);
4849 fragP->fr_fix += 4;
4850 }
4851 else
4852 {
4853 /* This cannot happen, because jbsr and jbra are the only two
4854 unconditional branches. */
4855 abort ();
4856 }
4857 break;
4858 case TAB (BRABSJCOND, LONG):
4859 if (flag_keep_pcrel)
4860 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4861
4862 /* Only Bcc 68000 instructions can come here
4863 Change bcc into b!cc/jmp absl long. */
4864 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4865 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4866
4867 /* JF: these used to be fr_opcode[2,3], but they may be in a
4868 different frag, in which case referring to them is a no-no.
4869 Only fr_opcode[0,1] are guaranteed to work. */
4870 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4871 *buffer_address++ = (char) 0xf9;
4872 fragP->fr_fix += 2; /* Account for jmp instruction. */
4873 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4874 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4875 fragP->fr_fix += 4;
4876 break;
4877 case TAB (FBRANCH, SHORT):
4878 know ((fragP->fr_opcode[1] & 0x40) == 0);
4879 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4880 1, RELAX_RELOC_PC16);
4881 fragP->fr_fix += 2;
4882 break;
4883 case TAB (FBRANCH, LONG):
4884 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4885 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4886 1, RELAX_RELOC_PC32);
4887 fragP->fr_fix += 4;
4888 break;
4889 case TAB (DBCCLBR, SHORT):
4890 case TAB (DBCCABSJ, SHORT):
4891 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4892 1, RELAX_RELOC_PC16);
4893 fragP->fr_fix += 2;
4894 break;
4895 case TAB (DBCCLBR, LONG):
4896 /* Only DBcc instructions can come here.
4897 Change dbcc into dbcc/bral.
4898 JF: these used to be fr_opcode[2-7], but that's wrong. */
4899 if (flag_keep_pcrel)
4900 as_fatal (_("Tried to convert DBcc to absolute jump"));
4901
4902 *buffer_address++ = 0x00; /* Branch offset = 4. */
4903 *buffer_address++ = 0x04;
4904 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4905 *buffer_address++ = 0x06;
4906 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4907 *buffer_address++ = (char) 0xff;
4908
4909 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4910 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4911 RELAX_RELOC_PC32);
4912 fragP->fr_fix += 4;
4913 break;
4914 case TAB (DBCCABSJ, LONG):
4915 /* Only DBcc instructions can come here.
4916 Change dbcc into dbcc/jmp.
4917 JF: these used to be fr_opcode[2-7], but that's wrong. */
4918 if (flag_keep_pcrel)
4919 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4920
4921 *buffer_address++ = 0x00; /* Branch offset = 4. */
4922 *buffer_address++ = 0x04;
4923 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4924 *buffer_address++ = 0x06;
4925 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4926 *buffer_address++ = (char) 0xf9;
4927
4928 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4929 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4930 RELAX_RELOC_ABS32);
4931 fragP->fr_fix += 4;
4932 break;
4933 case TAB (PCREL1632, SHORT):
4934 fragP->fr_opcode[1] &= ~0x3F;
4935 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4936 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4937 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4938 fragP->fr_fix += 2;
4939 break;
4940 case TAB (PCREL1632, LONG):
4941 /* Already set to mode 7.3; this indicates: PC indirect with
4942 suppressed index, 32-bit displacement. */
4943 *buffer_address++ = 0x01;
4944 *buffer_address++ = 0x70;
4945 fragP->fr_fix += 2;
4946 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4947 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4948 fixP->fx_pcrel_adjust = 2;
4949 fragP->fr_fix += 4;
4950 break;
4951 case TAB (PCINDEX, BYTE):
4952 assert (fragP->fr_fix >= 2);
4953 buffer_address[-2] &= ~1;
4954 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4955 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4956 fixP->fx_pcrel_adjust = 1;
4957 break;
4958 case TAB (PCINDEX, SHORT):
4959 assert (fragP->fr_fix >= 2);
4960 buffer_address[-2] |= 0x1;
4961 buffer_address[-1] = 0x20;
4962 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4963 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4964 fixP->fx_pcrel_adjust = 2;
4965 fragP->fr_fix += 2;
4966 break;
4967 case TAB (PCINDEX, LONG):
4968 assert (fragP->fr_fix >= 2);
4969 buffer_address[-2] |= 0x1;
4970 buffer_address[-1] = 0x30;
4971 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4972 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4973 fixP->fx_pcrel_adjust = 2;
4974 fragP->fr_fix += 4;
4975 break;
4976 case TAB (ABSTOPCREL, SHORT):
4977 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4978 1, RELAX_RELOC_PC16);
4979 fragP->fr_fix += 2;
4980 break;
4981 case TAB (ABSTOPCREL, LONG):
4982 if (flag_keep_pcrel)
4983 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4984 /* The thing to do here is force it to ABSOLUTE LONG, since
4985 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4986 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4987 abort ();
4988 fragP->fr_opcode[1] &= ~0x3F;
4989 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4990 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4991 0, RELAX_RELOC_ABS32);
4992 fragP->fr_fix += 4;
4993 break;
4994 }
4995 }
4996
4997 void
4998 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4999 segT sec ATTRIBUTE_UNUSED,
5000 fragS *fragP)
5001 {
5002 md_convert_frag_1 (fragP);
5003 }
5004
5005 /* Force truly undefined symbols to their maximum size, and generally set up
5006 the frag list to be relaxed
5007 */
5008 int
5009 md_estimate_size_before_relax (fragS *fragP, segT segment)
5010 {
5011 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5012 switch (fragP->fr_subtype)
5013 {
5014 case TAB (BRANCHBWL, SZ_UNDEF):
5015 case TAB (BRABSJUNC, SZ_UNDEF):
5016 case TAB (BRABSJCOND, SZ_UNDEF):
5017 {
5018 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5019 && relaxable_symbol (fragP->fr_symbol))
5020 {
5021 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5022 }
5023 else if (flag_short_refs)
5024 {
5025 /* Symbol is undefined and we want short ref. */
5026 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5027 }
5028 else
5029 {
5030 /* Symbol is still undefined. Make it LONG. */
5031 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5032 }
5033 break;
5034 }
5035
5036 case TAB (BRANCHBW, SZ_UNDEF):
5037 {
5038 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5039 && relaxable_symbol (fragP->fr_symbol))
5040 {
5041 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5042 }
5043 else
5044 {
5045 /* Symbol is undefined and we don't have long branches. */
5046 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5047 }
5048 break;
5049 }
5050
5051 case TAB (FBRANCH, SZ_UNDEF):
5052 case TAB (DBCCLBR, SZ_UNDEF):
5053 case TAB (DBCCABSJ, SZ_UNDEF):
5054 case TAB (PCREL1632, SZ_UNDEF):
5055 {
5056 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5057 && relaxable_symbol (fragP->fr_symbol))
5058 || flag_short_refs)
5059 {
5060 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5061 }
5062 else
5063 {
5064 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5065 }
5066 break;
5067 }
5068
5069 case TAB (PCINDEX, SZ_UNDEF):
5070 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5071 && relaxable_symbol (fragP->fr_symbol)))
5072 {
5073 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5074 }
5075 else
5076 {
5077 fragP->fr_subtype = TAB (PCINDEX, LONG);
5078 }
5079 break;
5080
5081 case TAB (ABSTOPCREL, SZ_UNDEF):
5082 {
5083 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5084 && relaxable_symbol (fragP->fr_symbol)))
5085 {
5086 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5087 }
5088 else
5089 {
5090 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5091 }
5092 break;
5093 }
5094
5095 default:
5096 break;
5097 }
5098
5099 /* Now that SZ_UNDEF are taken care of, check others. */
5100 switch (fragP->fr_subtype)
5101 {
5102 case TAB (BRANCHBWL, BYTE):
5103 case TAB (BRABSJUNC, BYTE):
5104 case TAB (BRABSJCOND, BYTE):
5105 case TAB (BRANCHBW, BYTE):
5106 /* We can't do a short jump to the next instruction, so in that
5107 case we force word mode. If the symbol is at the start of a
5108 frag, and it is the next frag with any data in it (usually
5109 this is just the next frag, but assembler listings may
5110 introduce empty frags), we must use word mode. */
5111 if (fragP->fr_symbol)
5112 {
5113 fragS *sym_frag;
5114
5115 sym_frag = symbol_get_frag (fragP->fr_symbol);
5116 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5117 {
5118 fragS *l;
5119
5120 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5121 if (l->fr_fix != 0)
5122 break;
5123 if (l == sym_frag)
5124 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5125 }
5126 }
5127 break;
5128 default:
5129 break;
5130 }
5131 return md_relax_table[fragP->fr_subtype].rlx_length;
5132 }
5133
5134 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5135 /* the bit-field entries in the relocation_info struct plays hell
5136 with the byte-order problems of cross-assembly. So as a hack,
5137 I added this mach. dependent ri twiddler. Ugly, but it gets
5138 you there. -KWK */
5139 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5140 are symbolnum, most sig. byte first. Last byte is broken up with
5141 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5142 nibble as nuthin. (on Sun 3 at least) */
5143 /* Translate the internal relocation information into target-specific
5144 format. */
5145 #ifdef comment
5146 void
5147 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5148 {
5149 /* This is easy. */
5150 md_number_to_chars (the_bytes, ri->r_address, 4);
5151 /* Now the fun stuff. */
5152 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5153 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5154 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5155 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5156 | ((ri->r_length << 5) & 0x60)
5157 | ((ri->r_extern << 4) & 0x10));
5158 }
5159
5160 #endif
5161
5162 #endif /* OBJ_AOUT or OBJ_BOUT */
5163
5164 #ifndef WORKING_DOT_WORD
5165 int md_short_jump_size = 4;
5166 int md_long_jump_size = 6;
5167
5168 void
5169 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5170 fragS *frag ATTRIBUTE_UNUSED,
5171 symbolS *to_symbol ATTRIBUTE_UNUSED)
5172 {
5173 valueT offset;
5174
5175 offset = to_addr - (from_addr + 2);
5176
5177 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5178 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5179 }
5180
5181 void
5182 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5183 fragS *frag, symbolS *to_symbol)
5184 {
5185 valueT offset;
5186
5187 if (!HAVE_LONG_BRANCH (current_architecture))
5188 {
5189 if (flag_keep_pcrel)
5190 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5191 offset = to_addr - S_GET_VALUE (to_symbol);
5192 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5193 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5194 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5195 0, NO_RELOC);
5196 }
5197 else
5198 {
5199 offset = to_addr - (from_addr + 2);
5200 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5201 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5202 }
5203 }
5204
5205 #endif
5206
5207 /* Different values of OK tell what its OK to return. Things that
5208 aren't OK are an error (what a shock, no?)
5209
5210 0: Everything is OK
5211 10: Absolute 1:8 only
5212 20: Absolute 0:7 only
5213 30: absolute 0:15 only
5214 40: Absolute 0:31 only
5215 50: absolute 0:127 only
5216 55: absolute -64:63 only
5217 60: absolute -128:127 only
5218 70: absolute 0:4095 only
5219 80: absolute -1, 1:7 only
5220 90: No bignums. */
5221
5222 static int
5223 get_num (struct m68k_exp *exp, int ok)
5224 {
5225 if (exp->exp.X_op == O_absent)
5226 {
5227 /* Do the same thing the VAX asm does. */
5228 op (exp) = O_constant;
5229 adds (exp) = 0;
5230 subs (exp) = 0;
5231 offs (exp) = 0;
5232 if (ok == 10)
5233 {
5234 as_warn (_("expression out of range: defaulting to 1"));
5235 offs (exp) = 1;
5236 }
5237 }
5238 else if (exp->exp.X_op == O_constant)
5239 {
5240 switch (ok)
5241 {
5242 case 10:
5243 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5244 {
5245 as_warn (_("expression out of range: defaulting to 1"));
5246 offs (exp) = 1;
5247 }
5248 break;
5249 case 20:
5250 if ((valueT) TRUNC (offs (exp)) > 7)
5251 goto outrange;
5252 break;
5253 case 30:
5254 if ((valueT) TRUNC (offs (exp)) > 15)
5255 goto outrange;
5256 break;
5257 case 40:
5258 if ((valueT) TRUNC (offs (exp)) > 32)
5259 goto outrange;
5260 break;
5261 case 50:
5262 if ((valueT) TRUNC (offs (exp)) > 127)
5263 goto outrange;
5264 break;
5265 case 55:
5266 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5267 goto outrange;
5268 break;
5269 case 60:
5270 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5271 goto outrange;
5272 break;
5273 case 70:
5274 if ((valueT) TRUNC (offs (exp)) > 4095)
5275 {
5276 outrange:
5277 as_warn (_("expression out of range: defaulting to 0"));
5278 offs (exp) = 0;
5279 }
5280 break;
5281 case 80:
5282 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5283 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5284 {
5285 as_warn (_("expression out of range: defaulting to 1"));
5286 offs (exp) = 1;
5287 }
5288 break;
5289 default:
5290 break;
5291 }
5292 }
5293 else if (exp->exp.X_op == O_big)
5294 {
5295 if (offs (exp) <= 0 /* flonum. */
5296 && (ok == 90 /* no bignums */
5297 || (ok > 10 /* Small-int ranges including 0 ok. */
5298 /* If we have a flonum zero, a zero integer should
5299 do as well (e.g., in moveq). */
5300 && generic_floating_point_number.exponent == 0
5301 && generic_floating_point_number.low[0] == 0)))
5302 {
5303 /* HACK! Turn it into a long. */
5304 LITTLENUM_TYPE words[6];
5305
5306 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5307 op (exp) = O_constant;
5308 adds (exp) = 0;
5309 subs (exp) = 0;
5310 offs (exp) = words[1] | (words[0] << 16);
5311 }
5312 else if (ok != 0)
5313 {
5314 op (exp) = O_constant;
5315 adds (exp) = 0;
5316 subs (exp) = 0;
5317 offs (exp) = (ok == 10) ? 1 : 0;
5318 as_warn (_("Can't deal with expression; defaulting to %ld"),
5319 (long) offs (exp));
5320 }
5321 }
5322 else
5323 {
5324 if (ok >= 10 && ok <= 80)
5325 {
5326 op (exp) = O_constant;
5327 adds (exp) = 0;
5328 subs (exp) = 0;
5329 offs (exp) = (ok == 10) ? 1 : 0;
5330 as_warn (_("Can't deal with expression; defaulting to %ld"),
5331 (long) offs (exp));
5332 }
5333 }
5334
5335 if (exp->size != SIZE_UNSPEC)
5336 {
5337 switch (exp->size)
5338 {
5339 case SIZE_UNSPEC:
5340 case SIZE_LONG:
5341 break;
5342 case SIZE_BYTE:
5343 if (!isbyte (offs (exp)))
5344 as_warn (_("expression doesn't fit in BYTE"));
5345 break;
5346 case SIZE_WORD:
5347 if (!isword (offs (exp)))
5348 as_warn (_("expression doesn't fit in WORD"));
5349 break;
5350 }
5351 }
5352
5353 return offs (exp);
5354 }
5355
5356 /* These are the back-ends for the various machine dependent pseudo-ops. */
5357
5358 static void
5359 s_data1 (int ignore ATTRIBUTE_UNUSED)
5360 {
5361 subseg_set (data_section, 1);
5362 demand_empty_rest_of_line ();
5363 }
5364
5365 static void
5366 s_data2 (int ignore ATTRIBUTE_UNUSED)
5367 {
5368 subseg_set (data_section, 2);
5369 demand_empty_rest_of_line ();
5370 }
5371
5372 static void
5373 s_bss (int ignore ATTRIBUTE_UNUSED)
5374 {
5375 /* We don't support putting frags in the BSS segment, we fake it
5376 by marking in_bss, then looking at s_skip for clues. */
5377
5378 subseg_set (bss_section, 0);
5379 demand_empty_rest_of_line ();
5380 }
5381
5382 static void
5383 s_even (int ignore ATTRIBUTE_UNUSED)
5384 {
5385 register int temp;
5386 register long temp_fill;
5387
5388 temp = 1; /* JF should be 2? */
5389 temp_fill = get_absolute_expression ();
5390 if (!need_pass_2) /* Never make frag if expect extra pass. */
5391 frag_align (temp, (int) temp_fill, 0);
5392 demand_empty_rest_of_line ();
5393 record_alignment (now_seg, temp);
5394 }
5395
5396 static void
5397 s_proc (int ignore ATTRIBUTE_UNUSED)
5398 {
5399 demand_empty_rest_of_line ();
5400 }
5401 \f
5402 /* Pseudo-ops handled for MRI compatibility. */
5403
5404 /* This function returns non-zero if the argument is a conditional
5405 pseudo-op. This is called when checking whether a pending
5406 alignment is needed. */
5407
5408 int
5409 m68k_conditional_pseudoop (pseudo_typeS *pop)
5410 {
5411 return (pop->poc_handler == s_mri_if
5412 || pop->poc_handler == s_mri_else);
5413 }
5414
5415 /* Handle an MRI style chip specification. */
5416
5417 static void
5418 mri_chip (void)
5419 {
5420 char *s;
5421 char c;
5422 int i;
5423
5424 s = input_line_pointer;
5425 /* We can't use get_symbol_end since the processor names are not proper
5426 symbols. */
5427 while (is_part_of_name (c = *input_line_pointer++))
5428 ;
5429 *--input_line_pointer = 0;
5430 for (i = 0; m68k_cpus[i].name; i++)
5431 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5432 break;
5433 if (!m68k_cpus[i].name)
5434 {
5435 as_bad (_("%s: unrecognized processor name"), s);
5436 *input_line_pointer = c;
5437 ignore_rest_of_line ();
5438 return;
5439 }
5440 *input_line_pointer = c;
5441
5442 if (*input_line_pointer == '/')
5443 current_architecture = 0;
5444 else
5445 current_architecture &= m68881 | m68851;
5446 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5447 control_regs = m68k_cpus[i].control_regs;
5448
5449 while (*input_line_pointer == '/')
5450 {
5451 ++input_line_pointer;
5452 s = input_line_pointer;
5453 /* We can't use get_symbol_end since the processor names are not
5454 proper symbols. */
5455 while (is_part_of_name (c = *input_line_pointer++))
5456 ;
5457 *--input_line_pointer = 0;
5458 if (strcmp (s, "68881") == 0)
5459 current_architecture |= m68881;
5460 else if (strcmp (s, "68851") == 0)
5461 current_architecture |= m68851;
5462 *input_line_pointer = c;
5463 }
5464 }
5465
5466 /* The MRI CHIP pseudo-op. */
5467
5468 static void
5469 s_chip (int ignore ATTRIBUTE_UNUSED)
5470 {
5471 char *stop = NULL;
5472 char stopc;
5473
5474 if (flag_mri)
5475 stop = mri_comment_field (&stopc);
5476 mri_chip ();
5477 if (flag_mri)
5478 mri_comment_end (stop, stopc);
5479 demand_empty_rest_of_line ();
5480 }
5481
5482 /* The MRI FOPT pseudo-op. */
5483
5484 static void
5485 s_fopt (int ignore ATTRIBUTE_UNUSED)
5486 {
5487 SKIP_WHITESPACE ();
5488
5489 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5490 {
5491 int temp;
5492
5493 input_line_pointer += 3;
5494 temp = get_absolute_expression ();
5495 if (temp < 0 || temp > 7)
5496 as_bad (_("bad coprocessor id"));
5497 else
5498 m68k_float_copnum = COP0 + temp;
5499 }
5500 else
5501 {
5502 as_bad (_("unrecognized fopt option"));
5503 ignore_rest_of_line ();
5504 return;
5505 }
5506
5507 demand_empty_rest_of_line ();
5508 }
5509
5510 /* The structure used to handle the MRI OPT pseudo-op. */
5511
5512 struct opt_action
5513 {
5514 /* The name of the option. */
5515 const char *name;
5516
5517 /* If this is not NULL, just call this function. The first argument
5518 is the ARG field of this structure, the second argument is
5519 whether the option was negated. */
5520 void (*pfn) (int arg, int on);
5521
5522 /* If this is not NULL, and the PFN field is NULL, set the variable
5523 this points to. Set it to the ARG field if the option was not
5524 negated, and the NOTARG field otherwise. */
5525 int *pvar;
5526
5527 /* The value to pass to PFN or to assign to *PVAR. */
5528 int arg;
5529
5530 /* The value to assign to *PVAR if the option is negated. If PFN is
5531 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5532 the option may not be negated. */
5533 int notarg;
5534 };
5535
5536 /* The table used to handle the MRI OPT pseudo-op. */
5537
5538 static void skip_to_comma (int, int);
5539 static void opt_nest (int, int);
5540 static void opt_chip (int, int);
5541 static void opt_list (int, int);
5542 static void opt_list_symbols (int, int);
5543
5544 static const struct opt_action opt_table[] =
5545 {
5546 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5547
5548 /* We do relaxing, so there is little use for these options. */
5549 { "b", 0, 0, 0, 0 },
5550 { "brs", 0, 0, 0, 0 },
5551 { "brb", 0, 0, 0, 0 },
5552 { "brl", 0, 0, 0, 0 },
5553 { "brw", 0, 0, 0, 0 },
5554
5555 { "c", 0, 0, 0, 0 },
5556 { "cex", 0, 0, 0, 0 },
5557 { "case", 0, &symbols_case_sensitive, 1, 0 },
5558 { "cl", 0, 0, 0, 0 },
5559 { "cre", 0, 0, 0, 0 },
5560 { "d", 0, &flag_keep_locals, 1, 0 },
5561 { "e", 0, 0, 0, 0 },
5562 { "f", 0, &flag_short_refs, 1, 0 },
5563 { "frs", 0, &flag_short_refs, 1, 0 },
5564 { "frl", 0, &flag_short_refs, 0, 1 },
5565 { "g", 0, 0, 0, 0 },
5566 { "i", 0, 0, 0, 0 },
5567 { "m", 0, 0, 0, 0 },
5568 { "mex", 0, 0, 0, 0 },
5569 { "mc", 0, 0, 0, 0 },
5570 { "md", 0, 0, 0, 0 },
5571 { "nest", opt_nest, 0, 0, 0 },
5572 { "next", skip_to_comma, 0, 0, 0 },
5573 { "o", 0, 0, 0, 0 },
5574 { "old", 0, 0, 0, 0 },
5575 { "op", skip_to_comma, 0, 0, 0 },
5576 { "pco", 0, 0, 0, 0 },
5577 { "p", opt_chip, 0, 0, 0 },
5578 { "pcr", 0, 0, 0, 0 },
5579 { "pcs", 0, 0, 0, 0 },
5580 { "r", 0, 0, 0, 0 },
5581 { "quick", 0, &m68k_quick, 1, 0 },
5582 { "rel32", 0, &m68k_rel32, 1, 0 },
5583 { "s", opt_list, 0, 0, 0 },
5584 { "t", opt_list_symbols, 0, 0, 0 },
5585 { "w", 0, &flag_no_warnings, 0, 1 },
5586 { "x", 0, 0, 0, 0 }
5587 };
5588
5589 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5590
5591 /* The MRI OPT pseudo-op. */
5592
5593 static void
5594 s_opt (int ignore ATTRIBUTE_UNUSED)
5595 {
5596 do
5597 {
5598 int t;
5599 char *s;
5600 char c;
5601 int i;
5602 const struct opt_action *o;
5603
5604 SKIP_WHITESPACE ();
5605
5606 t = 1;
5607 if (*input_line_pointer == '-')
5608 {
5609 ++input_line_pointer;
5610 t = 0;
5611 }
5612 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5613 {
5614 input_line_pointer += 2;
5615 t = 0;
5616 }
5617
5618 s = input_line_pointer;
5619 c = get_symbol_end ();
5620
5621 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5622 {
5623 if (strcasecmp (s, o->name) == 0)
5624 {
5625 if (o->pfn)
5626 {
5627 /* Restore input_line_pointer now in case the option
5628 takes arguments. */
5629 *input_line_pointer = c;
5630 (*o->pfn) (o->arg, t);
5631 }
5632 else if (o->pvar != NULL)
5633 {
5634 if (! t && o->arg == o->notarg)
5635 as_bad (_("option `%s' may not be negated"), s);
5636 *input_line_pointer = c;
5637 *o->pvar = t ? o->arg : o->notarg;
5638 }
5639 else
5640 *input_line_pointer = c;
5641 break;
5642 }
5643 }
5644 if (i >= OPTCOUNT)
5645 {
5646 as_bad (_("option `%s' not recognized"), s);
5647 *input_line_pointer = c;
5648 }
5649 }
5650 while (*input_line_pointer++ == ',');
5651
5652 /* Move back to terminating character. */
5653 --input_line_pointer;
5654 demand_empty_rest_of_line ();
5655 }
5656
5657 /* Skip ahead to a comma. This is used for OPT options which we do
5658 not support and which take arguments. */
5659
5660 static void
5661 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5662 {
5663 while (*input_line_pointer != ','
5664 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5665 ++input_line_pointer;
5666 }
5667
5668 /* Handle the OPT NEST=depth option. */
5669
5670 static void
5671 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5672 {
5673 if (*input_line_pointer != '=')
5674 {
5675 as_bad (_("bad format of OPT NEST=depth"));
5676 return;
5677 }
5678
5679 ++input_line_pointer;
5680 max_macro_nest = get_absolute_expression ();
5681 }
5682
5683 /* Handle the OPT P=chip option. */
5684
5685 static void
5686 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5687 {
5688 if (*input_line_pointer != '=')
5689 {
5690 /* This is just OPT P, which we do not support. */
5691 return;
5692 }
5693
5694 ++input_line_pointer;
5695 mri_chip ();
5696 }
5697
5698 /* Handle the OPT S option. */
5699
5700 static void
5701 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5702 {
5703 listing_list (on);
5704 }
5705
5706 /* Handle the OPT T option. */
5707
5708 static void
5709 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5710 {
5711 if (on)
5712 listing |= LISTING_SYMBOLS;
5713 else
5714 listing &= ~LISTING_SYMBOLS;
5715 }
5716
5717 /* Handle the MRI REG pseudo-op. */
5718
5719 static void
5720 s_reg (int ignore ATTRIBUTE_UNUSED)
5721 {
5722 char *s;
5723 int c;
5724 struct m68k_op rop;
5725 int mask;
5726 char *stop = NULL;
5727 char stopc;
5728
5729 if (line_label == NULL)
5730 {
5731 as_bad (_("missing label"));
5732 ignore_rest_of_line ();
5733 return;
5734 }
5735
5736 if (flag_mri)
5737 stop = mri_comment_field (&stopc);
5738
5739 SKIP_WHITESPACE ();
5740
5741 s = input_line_pointer;
5742 while (ISALNUM (*input_line_pointer)
5743 #ifdef REGISTER_PREFIX
5744 || *input_line_pointer == REGISTER_PREFIX
5745 #endif
5746 || *input_line_pointer == '/'
5747 || *input_line_pointer == '-')
5748 ++input_line_pointer;
5749 c = *input_line_pointer;
5750 *input_line_pointer = '\0';
5751
5752 if (m68k_ip_op (s, &rop) != 0)
5753 {
5754 if (rop.error == NULL)
5755 as_bad (_("bad register list"));
5756 else
5757 as_bad (_("bad register list: %s"), rop.error);
5758 *input_line_pointer = c;
5759 ignore_rest_of_line ();
5760 return;
5761 }
5762
5763 *input_line_pointer = c;
5764
5765 if (rop.mode == REGLST)
5766 mask = rop.mask;
5767 else if (rop.mode == DREG)
5768 mask = 1 << (rop.reg - DATA0);
5769 else if (rop.mode == AREG)
5770 mask = 1 << (rop.reg - ADDR0 + 8);
5771 else if (rop.mode == FPREG)
5772 mask = 1 << (rop.reg - FP0 + 16);
5773 else if (rop.mode == CONTROL
5774 && rop.reg == FPI)
5775 mask = 1 << 24;
5776 else if (rop.mode == CONTROL
5777 && rop.reg == FPS)
5778 mask = 1 << 25;
5779 else if (rop.mode == CONTROL
5780 && rop.reg == FPC)
5781 mask = 1 << 26;
5782 else
5783 {
5784 as_bad (_("bad register list"));
5785 ignore_rest_of_line ();
5786 return;
5787 }
5788
5789 S_SET_SEGMENT (line_label, reg_section);
5790 S_SET_VALUE (line_label, ~mask);
5791 symbol_set_frag (line_label, &zero_address_frag);
5792
5793 if (flag_mri)
5794 mri_comment_end (stop, stopc);
5795
5796 demand_empty_rest_of_line ();
5797 }
5798
5799 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5800
5801 struct save_opts
5802 {
5803 struct save_opts *next;
5804 int abspcadd;
5805 int symbols_case_sensitive;
5806 int keep_locals;
5807 int short_refs;
5808 int architecture;
5809 const enum m68k_register *control_regs;
5810 int quick;
5811 int rel32;
5812 int listing;
5813 int no_warnings;
5814 /* FIXME: We don't save OPT S. */
5815 };
5816
5817 /* This variable holds the stack of saved options. */
5818
5819 static struct save_opts *save_stack;
5820
5821 /* The MRI SAVE pseudo-op. */
5822
5823 static void
5824 s_save (int ignore ATTRIBUTE_UNUSED)
5825 {
5826 struct save_opts *s;
5827
5828 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5829 s->abspcadd = m68k_abspcadd;
5830 s->symbols_case_sensitive = symbols_case_sensitive;
5831 s->keep_locals = flag_keep_locals;
5832 s->short_refs = flag_short_refs;
5833 s->architecture = current_architecture;
5834 s->control_regs = control_regs;
5835 s->quick = m68k_quick;
5836 s->rel32 = m68k_rel32;
5837 s->listing = listing;
5838 s->no_warnings = flag_no_warnings;
5839
5840 s->next = save_stack;
5841 save_stack = s;
5842
5843 demand_empty_rest_of_line ();
5844 }
5845
5846 /* The MRI RESTORE pseudo-op. */
5847
5848 static void
5849 s_restore (int ignore ATTRIBUTE_UNUSED)
5850 {
5851 struct save_opts *s;
5852
5853 if (save_stack == NULL)
5854 {
5855 as_bad (_("restore without save"));
5856 ignore_rest_of_line ();
5857 return;
5858 }
5859
5860 s = save_stack;
5861 save_stack = s->next;
5862
5863 m68k_abspcadd = s->abspcadd;
5864 symbols_case_sensitive = s->symbols_case_sensitive;
5865 flag_keep_locals = s->keep_locals;
5866 flag_short_refs = s->short_refs;
5867 current_architecture = s->architecture;
5868 control_regs = s->control_regs;
5869 m68k_quick = s->quick;
5870 m68k_rel32 = s->rel32;
5871 listing = s->listing;
5872 flag_no_warnings = s->no_warnings;
5873
5874 free (s);
5875
5876 demand_empty_rest_of_line ();
5877 }
5878
5879 /* Types of MRI structured control directives. */
5880
5881 enum mri_control_type
5882 {
5883 mri_for,
5884 mri_if,
5885 mri_repeat,
5886 mri_while
5887 };
5888
5889 /* This structure is used to stack the MRI structured control
5890 directives. */
5891
5892 struct mri_control_info
5893 {
5894 /* The directive within which this one is enclosed. */
5895 struct mri_control_info *outer;
5896
5897 /* The type of directive. */
5898 enum mri_control_type type;
5899
5900 /* Whether an ELSE has been in an IF. */
5901 int else_seen;
5902
5903 /* The add or sub statement at the end of a FOR. */
5904 char *incr;
5905
5906 /* The label of the top of a FOR or REPEAT loop. */
5907 char *top;
5908
5909 /* The label to jump to for the next iteration, or the else
5910 expression of a conditional. */
5911 char *next;
5912
5913 /* The label to jump to to break out of the loop, or the label past
5914 the end of a conditional. */
5915 char *bottom;
5916 };
5917
5918 /* The stack of MRI structured control directives. */
5919
5920 static struct mri_control_info *mri_control_stack;
5921
5922 /* The current MRI structured control directive index number, used to
5923 generate label names. */
5924
5925 static int mri_control_index;
5926
5927 /* Assemble an instruction for an MRI structured control directive. */
5928
5929 static void
5930 mri_assemble (char *str)
5931 {
5932 char *s;
5933
5934 /* md_assemble expects the opcode to be in lower case. */
5935 for (s = str; *s != ' ' && *s != '\0'; s++)
5936 *s = TOLOWER (*s);
5937
5938 md_assemble (str);
5939 }
5940
5941 /* Generate a new MRI label structured control directive label name. */
5942
5943 static char *
5944 mri_control_label (void)
5945 {
5946 char *n;
5947
5948 n = (char *) xmalloc (20);
5949 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5950 ++mri_control_index;
5951 return n;
5952 }
5953
5954 /* Create a new MRI structured control directive. */
5955
5956 static struct mri_control_info *
5957 push_mri_control (enum mri_control_type type)
5958 {
5959 struct mri_control_info *n;
5960
5961 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5962
5963 n->type = type;
5964 n->else_seen = 0;
5965 if (type == mri_if || type == mri_while)
5966 n->top = NULL;
5967 else
5968 n->top = mri_control_label ();
5969 n->next = mri_control_label ();
5970 n->bottom = mri_control_label ();
5971
5972 n->outer = mri_control_stack;
5973 mri_control_stack = n;
5974
5975 return n;
5976 }
5977
5978 /* Pop off the stack of MRI structured control directives. */
5979
5980 static void
5981 pop_mri_control (void)
5982 {
5983 struct mri_control_info *n;
5984
5985 n = mri_control_stack;
5986 mri_control_stack = n->outer;
5987 if (n->top != NULL)
5988 free (n->top);
5989 free (n->next);
5990 free (n->bottom);
5991 free (n);
5992 }
5993
5994 /* Recognize a condition code in an MRI structured control expression. */
5995
5996 static int
5997 parse_mri_condition (int *pcc)
5998 {
5999 char c1, c2;
6000
6001 know (*input_line_pointer == '<');
6002
6003 ++input_line_pointer;
6004 c1 = *input_line_pointer++;
6005 c2 = *input_line_pointer++;
6006
6007 if (*input_line_pointer != '>')
6008 {
6009 as_bad (_("syntax error in structured control directive"));
6010 return 0;
6011 }
6012
6013 ++input_line_pointer;
6014 SKIP_WHITESPACE ();
6015
6016 c1 = TOLOWER (c1);
6017 c2 = TOLOWER (c2);
6018
6019 *pcc = (c1 << 8) | c2;
6020
6021 return 1;
6022 }
6023
6024 /* Parse a single operand in an MRI structured control expression. */
6025
6026 static int
6027 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6028 char **rightstart, char **rightstop)
6029 {
6030 char *s;
6031
6032 SKIP_WHITESPACE ();
6033
6034 *pcc = -1;
6035 *leftstart = NULL;
6036 *leftstop = NULL;
6037 *rightstart = NULL;
6038 *rightstop = NULL;
6039
6040 if (*input_line_pointer == '<')
6041 {
6042 /* It's just a condition code. */
6043 return parse_mri_condition (pcc);
6044 }
6045
6046 /* Look ahead for the condition code. */
6047 for (s = input_line_pointer; *s != '\0'; ++s)
6048 {
6049 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6050 break;
6051 }
6052 if (*s == '\0')
6053 {
6054 as_bad (_("missing condition code in structured control directive"));
6055 return 0;
6056 }
6057
6058 *leftstart = input_line_pointer;
6059 *leftstop = s;
6060 if (*leftstop > *leftstart
6061 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6062 --*leftstop;
6063
6064 input_line_pointer = s;
6065 if (! parse_mri_condition (pcc))
6066 return 0;
6067
6068 /* Look ahead for AND or OR or end of line. */
6069 for (s = input_line_pointer; *s != '\0'; ++s)
6070 {
6071 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6072 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6073 ^^^ ^^ */
6074 if ((s == input_line_pointer
6075 || *(s-1) == ' '
6076 || *(s-1) == '\t')
6077 && ((strncasecmp (s, "AND", 3) == 0
6078 && (s[3] == '.' || ! is_part_of_name (s[3])))
6079 || (strncasecmp (s, "OR", 2) == 0
6080 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6081 break;
6082 }
6083
6084 *rightstart = input_line_pointer;
6085 *rightstop = s;
6086 if (*rightstop > *rightstart
6087 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6088 --*rightstop;
6089
6090 input_line_pointer = s;
6091
6092 return 1;
6093 }
6094
6095 #define MCC(b1, b2) (((b1) << 8) | (b2))
6096
6097 /* Swap the sense of a condition. This changes the condition so that
6098 it generates the same result when the operands are swapped. */
6099
6100 static int
6101 swap_mri_condition (int cc)
6102 {
6103 switch (cc)
6104 {
6105 case MCC ('h', 'i'): return MCC ('c', 's');
6106 case MCC ('l', 's'): return MCC ('c', 'c');
6107 /* <HS> is an alias for <CC>. */
6108 case MCC ('h', 's'):
6109 case MCC ('c', 'c'): return MCC ('l', 's');
6110 /* <LO> is an alias for <CS>. */
6111 case MCC ('l', 'o'):
6112 case MCC ('c', 's'): return MCC ('h', 'i');
6113 case MCC ('p', 'l'): return MCC ('m', 'i');
6114 case MCC ('m', 'i'): return MCC ('p', 'l');
6115 case MCC ('g', 'e'): return MCC ('l', 'e');
6116 case MCC ('l', 't'): return MCC ('g', 't');
6117 case MCC ('g', 't'): return MCC ('l', 't');
6118 case MCC ('l', 'e'): return MCC ('g', 'e');
6119 /* Issue a warning for conditions we can not swap. */
6120 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6121 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6122 case MCC ('v', 'c'):
6123 case MCC ('v', 's'):
6124 default :
6125 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6126 (char) (cc >> 8), (char) (cc));
6127 break;
6128 }
6129 return cc;
6130 }
6131
6132 /* Reverse the sense of a condition. */
6133
6134 static int
6135 reverse_mri_condition (int cc)
6136 {
6137 switch (cc)
6138 {
6139 case MCC ('h', 'i'): return MCC ('l', 's');
6140 case MCC ('l', 's'): return MCC ('h', 'i');
6141 /* <HS> is an alias for <CC> */
6142 case MCC ('h', 's'): return MCC ('l', 'o');
6143 case MCC ('c', 'c'): return MCC ('c', 's');
6144 /* <LO> is an alias for <CS> */
6145 case MCC ('l', 'o'): return MCC ('h', 's');
6146 case MCC ('c', 's'): return MCC ('c', 'c');
6147 case MCC ('n', 'e'): return MCC ('e', 'q');
6148 case MCC ('e', 'q'): return MCC ('n', 'e');
6149 case MCC ('v', 'c'): return MCC ('v', 's');
6150 case MCC ('v', 's'): return MCC ('v', 'c');
6151 case MCC ('p', 'l'): return MCC ('m', 'i');
6152 case MCC ('m', 'i'): return MCC ('p', 'l');
6153 case MCC ('g', 'e'): return MCC ('l', 't');
6154 case MCC ('l', 't'): return MCC ('g', 'e');
6155 case MCC ('g', 't'): return MCC ('l', 'e');
6156 case MCC ('l', 'e'): return MCC ('g', 't');
6157 }
6158 return cc;
6159 }
6160
6161 /* Build an MRI structured control expression. This generates test
6162 and branch instructions. It goes to TRUELAB if the condition is
6163 true, and to FALSELAB if the condition is false. Exactly one of
6164 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6165 is the size qualifier for the expression. EXTENT is the size to
6166 use for the branch. */
6167
6168 static void
6169 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6170 char *rightstart, char *rightstop,
6171 const char *truelab, const char *falselab,
6172 int extent)
6173 {
6174 char *buf;
6175 char *s;
6176
6177 if (leftstart != NULL)
6178 {
6179 struct m68k_op leftop, rightop;
6180 char c;
6181
6182 /* Swap the compare operands, if necessary, to produce a legal
6183 m68k compare instruction. Comparing a register operand with
6184 a non-register operand requires the register to be on the
6185 right (cmp, cmpa). Comparing an immediate value with
6186 anything requires the immediate value to be on the left
6187 (cmpi). */
6188
6189 c = *leftstop;
6190 *leftstop = '\0';
6191 (void) m68k_ip_op (leftstart, &leftop);
6192 *leftstop = c;
6193
6194 c = *rightstop;
6195 *rightstop = '\0';
6196 (void) m68k_ip_op (rightstart, &rightop);
6197 *rightstop = c;
6198
6199 if (rightop.mode == IMMED
6200 || ((leftop.mode == DREG || leftop.mode == AREG)
6201 && (rightop.mode != DREG && rightop.mode != AREG)))
6202 {
6203 char *temp;
6204
6205 /* Correct conditional handling:
6206 if #1 <lt> d0 then ;means if (1 < d0)
6207 ...
6208 endi
6209
6210 should assemble to:
6211
6212 cmp #1,d0 if we do *not* swap the operands
6213 bgt true we need the swapped condition!
6214 ble false
6215 true:
6216 ...
6217 false:
6218 */
6219 temp = leftstart;
6220 leftstart = rightstart;
6221 rightstart = temp;
6222 temp = leftstop;
6223 leftstop = rightstop;
6224 rightstop = temp;
6225 }
6226 else
6227 {
6228 cc = swap_mri_condition (cc);
6229 }
6230 }
6231
6232 if (truelab == NULL)
6233 {
6234 cc = reverse_mri_condition (cc);
6235 truelab = falselab;
6236 }
6237
6238 if (leftstart != NULL)
6239 {
6240 buf = (char *) xmalloc (20
6241 + (leftstop - leftstart)
6242 + (rightstop - rightstart));
6243 s = buf;
6244 *s++ = 'c';
6245 *s++ = 'm';
6246 *s++ = 'p';
6247 if (qual != '\0')
6248 *s++ = TOLOWER (qual);
6249 *s++ = ' ';
6250 memcpy (s, leftstart, leftstop - leftstart);
6251 s += leftstop - leftstart;
6252 *s++ = ',';
6253 memcpy (s, rightstart, rightstop - rightstart);
6254 s += rightstop - rightstart;
6255 *s = '\0';
6256 mri_assemble (buf);
6257 free (buf);
6258 }
6259
6260 buf = (char *) xmalloc (20 + strlen (truelab));
6261 s = buf;
6262 *s++ = 'b';
6263 *s++ = cc >> 8;
6264 *s++ = cc & 0xff;
6265 if (extent != '\0')
6266 *s++ = TOLOWER (extent);
6267 *s++ = ' ';
6268 strcpy (s, truelab);
6269 mri_assemble (buf);
6270 free (buf);
6271 }
6272
6273 /* Parse an MRI structured control expression. This generates test
6274 and branch instructions. STOP is where the expression ends. It
6275 goes to TRUELAB if the condition is true, and to FALSELAB if the
6276 condition is false. Exactly one of TRUELAB and FALSELAB will be
6277 NULL, meaning to fall through. QUAL is the size qualifier for the
6278 expression. EXTENT is the size to use for the branch. */
6279
6280 static void
6281 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6282 const char *falselab, int extent)
6283 {
6284 int c;
6285 int cc;
6286 char *leftstart;
6287 char *leftstop;
6288 char *rightstart;
6289 char *rightstop;
6290
6291 c = *stop;
6292 *stop = '\0';
6293
6294 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6295 &rightstart, &rightstop))
6296 {
6297 *stop = c;
6298 return;
6299 }
6300
6301 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6302 {
6303 const char *flab;
6304
6305 if (falselab != NULL)
6306 flab = falselab;
6307 else
6308 flab = mri_control_label ();
6309
6310 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6311 rightstop, (const char *) NULL, flab, extent);
6312
6313 input_line_pointer += 3;
6314 if (*input_line_pointer != '.'
6315 || input_line_pointer[1] == '\0')
6316 qual = '\0';
6317 else
6318 {
6319 qual = input_line_pointer[1];
6320 input_line_pointer += 2;
6321 }
6322
6323 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6324 &rightstart, &rightstop))
6325 {
6326 *stop = c;
6327 return;
6328 }
6329
6330 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6331 rightstop, truelab, falselab, extent);
6332
6333 if (falselab == NULL)
6334 colon (flab);
6335 }
6336 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6337 {
6338 const char *tlab;
6339
6340 if (truelab != NULL)
6341 tlab = truelab;
6342 else
6343 tlab = mri_control_label ();
6344
6345 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6346 rightstop, tlab, (const char *) NULL, extent);
6347
6348 input_line_pointer += 2;
6349 if (*input_line_pointer != '.'
6350 || input_line_pointer[1] == '\0')
6351 qual = '\0';
6352 else
6353 {
6354 qual = input_line_pointer[1];
6355 input_line_pointer += 2;
6356 }
6357
6358 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6359 &rightstart, &rightstop))
6360 {
6361 *stop = c;
6362 return;
6363 }
6364
6365 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6366 rightstop, truelab, falselab, extent);
6367
6368 if (truelab == NULL)
6369 colon (tlab);
6370 }
6371 else
6372 {
6373 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6374 rightstop, truelab, falselab, extent);
6375 }
6376
6377 *stop = c;
6378 if (input_line_pointer != stop)
6379 as_bad (_("syntax error in structured control directive"));
6380 }
6381
6382 /* Handle the MRI IF pseudo-op. This may be a structured control
6383 directive, or it may be a regular assembler conditional, depending
6384 on its operands. */
6385
6386 static void
6387 s_mri_if (int qual)
6388 {
6389 char *s;
6390 int c;
6391 struct mri_control_info *n;
6392
6393 /* A structured control directive must end with THEN with an
6394 optional qualifier. */
6395 s = input_line_pointer;
6396 /* We only accept '*' as introduction of comments if preceded by white space
6397 or at first column of a line (I think this can't actually happen here?)
6398 This is important when assembling:
6399 if d0 <ne> 12(a0,d0*2) then
6400 if d0 <ne> #CONST*20 then. */
6401 while (! (is_end_of_line[(unsigned char) *s]
6402 || (flag_mri
6403 && *s == '*'
6404 && (s == input_line_pointer
6405 || *(s-1) == ' '
6406 || *(s-1) == '\t'))))
6407 ++s;
6408 --s;
6409 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6410 --s;
6411
6412 if (s - input_line_pointer > 1
6413 && s[-1] == '.')
6414 s -= 2;
6415
6416 if (s - input_line_pointer < 3
6417 || strncasecmp (s - 3, "THEN", 4) != 0)
6418 {
6419 if (qual != '\0')
6420 {
6421 as_bad (_("missing then"));
6422 ignore_rest_of_line ();
6423 return;
6424 }
6425
6426 /* It's a conditional. */
6427 s_if (O_ne);
6428 return;
6429 }
6430
6431 /* Since this might be a conditional if, this pseudo-op will be
6432 called even if we are supported to be ignoring input. Double
6433 check now. Clobber *input_line_pointer so that ignore_input
6434 thinks that this is not a special pseudo-op. */
6435 c = *input_line_pointer;
6436 *input_line_pointer = 0;
6437 if (ignore_input ())
6438 {
6439 *input_line_pointer = c;
6440 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6441 ++input_line_pointer;
6442 demand_empty_rest_of_line ();
6443 return;
6444 }
6445 *input_line_pointer = c;
6446
6447 n = push_mri_control (mri_if);
6448
6449 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6450 n->next, s[1] == '.' ? s[2] : '\0');
6451
6452 if (s[1] == '.')
6453 input_line_pointer = s + 3;
6454 else
6455 input_line_pointer = s + 1;
6456
6457 if (flag_mri)
6458 {
6459 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6460 ++input_line_pointer;
6461 }
6462
6463 demand_empty_rest_of_line ();
6464 }
6465
6466 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6467 structured IF, associate the ELSE with the IF. Otherwise, assume
6468 it is a conditional else. */
6469
6470 static void
6471 s_mri_else (int qual)
6472 {
6473 int c;
6474 char *buf;
6475 char q[2];
6476
6477 if (qual == '\0'
6478 && (mri_control_stack == NULL
6479 || mri_control_stack->type != mri_if
6480 || mri_control_stack->else_seen))
6481 {
6482 s_else (0);
6483 return;
6484 }
6485
6486 c = *input_line_pointer;
6487 *input_line_pointer = 0;
6488 if (ignore_input ())
6489 {
6490 *input_line_pointer = c;
6491 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6492 ++input_line_pointer;
6493 demand_empty_rest_of_line ();
6494 return;
6495 }
6496 *input_line_pointer = c;
6497
6498 if (mri_control_stack == NULL
6499 || mri_control_stack->type != mri_if
6500 || mri_control_stack->else_seen)
6501 {
6502 as_bad (_("else without matching if"));
6503 ignore_rest_of_line ();
6504 return;
6505 }
6506
6507 mri_control_stack->else_seen = 1;
6508
6509 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6510 q[0] = TOLOWER (qual);
6511 q[1] = '\0';
6512 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6513 mri_assemble (buf);
6514 free (buf);
6515
6516 colon (mri_control_stack->next);
6517
6518 if (flag_mri)
6519 {
6520 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6521 ++input_line_pointer;
6522 }
6523
6524 demand_empty_rest_of_line ();
6525 }
6526
6527 /* Handle the MRI ENDI pseudo-op. */
6528
6529 static void
6530 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6531 {
6532 if (mri_control_stack == NULL
6533 || mri_control_stack->type != mri_if)
6534 {
6535 as_bad (_("endi without matching if"));
6536 ignore_rest_of_line ();
6537 return;
6538 }
6539
6540 /* ignore_input will not return true for ENDI, so we don't need to
6541 worry about checking it again here. */
6542
6543 if (! mri_control_stack->else_seen)
6544 colon (mri_control_stack->next);
6545 colon (mri_control_stack->bottom);
6546
6547 pop_mri_control ();
6548
6549 if (flag_mri)
6550 {
6551 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6552 ++input_line_pointer;
6553 }
6554
6555 demand_empty_rest_of_line ();
6556 }
6557
6558 /* Handle the MRI BREAK pseudo-op. */
6559
6560 static void
6561 s_mri_break (int extent)
6562 {
6563 struct mri_control_info *n;
6564 char *buf;
6565 char ex[2];
6566
6567 n = mri_control_stack;
6568 while (n != NULL
6569 && n->type != mri_for
6570 && n->type != mri_repeat
6571 && n->type != mri_while)
6572 n = n->outer;
6573 if (n == NULL)
6574 {
6575 as_bad (_("break outside of structured loop"));
6576 ignore_rest_of_line ();
6577 return;
6578 }
6579
6580 buf = (char *) xmalloc (20 + strlen (n->bottom));
6581 ex[0] = TOLOWER (extent);
6582 ex[1] = '\0';
6583 sprintf (buf, "bra%s %s", ex, n->bottom);
6584 mri_assemble (buf);
6585 free (buf);
6586
6587 if (flag_mri)
6588 {
6589 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6590 ++input_line_pointer;
6591 }
6592
6593 demand_empty_rest_of_line ();
6594 }
6595
6596 /* Handle the MRI NEXT pseudo-op. */
6597
6598 static void
6599 s_mri_next (int extent)
6600 {
6601 struct mri_control_info *n;
6602 char *buf;
6603 char ex[2];
6604
6605 n = mri_control_stack;
6606 while (n != NULL
6607 && n->type != mri_for
6608 && n->type != mri_repeat
6609 && n->type != mri_while)
6610 n = n->outer;
6611 if (n == NULL)
6612 {
6613 as_bad (_("next outside of structured loop"));
6614 ignore_rest_of_line ();
6615 return;
6616 }
6617
6618 buf = (char *) xmalloc (20 + strlen (n->next));
6619 ex[0] = TOLOWER (extent);
6620 ex[1] = '\0';
6621 sprintf (buf, "bra%s %s", ex, n->next);
6622 mri_assemble (buf);
6623 free (buf);
6624
6625 if (flag_mri)
6626 {
6627 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6628 ++input_line_pointer;
6629 }
6630
6631 demand_empty_rest_of_line ();
6632 }
6633
6634 /* Handle the MRI FOR pseudo-op. */
6635
6636 static void
6637 s_mri_for (int qual)
6638 {
6639 const char *varstart, *varstop;
6640 const char *initstart, *initstop;
6641 const char *endstart, *endstop;
6642 const char *bystart, *bystop;
6643 int up;
6644 int by;
6645 int extent;
6646 struct mri_control_info *n;
6647 char *buf;
6648 char *s;
6649 char ex[2];
6650
6651 /* The syntax is
6652 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6653 */
6654
6655 SKIP_WHITESPACE ();
6656 varstart = input_line_pointer;
6657
6658 /* Look for the '='. */
6659 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6660 && *input_line_pointer != '=')
6661 ++input_line_pointer;
6662 if (*input_line_pointer != '=')
6663 {
6664 as_bad (_("missing ="));
6665 ignore_rest_of_line ();
6666 return;
6667 }
6668
6669 varstop = input_line_pointer;
6670 if (varstop > varstart
6671 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6672 --varstop;
6673
6674 ++input_line_pointer;
6675
6676 initstart = input_line_pointer;
6677
6678 /* Look for TO or DOWNTO. */
6679 up = 1;
6680 initstop = NULL;
6681 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6682 {
6683 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6684 && ! is_part_of_name (input_line_pointer[2]))
6685 {
6686 initstop = input_line_pointer;
6687 input_line_pointer += 2;
6688 break;
6689 }
6690 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6691 && ! is_part_of_name (input_line_pointer[6]))
6692 {
6693 initstop = input_line_pointer;
6694 up = 0;
6695 input_line_pointer += 6;
6696 break;
6697 }
6698 ++input_line_pointer;
6699 }
6700 if (initstop == NULL)
6701 {
6702 as_bad (_("missing to or downto"));
6703 ignore_rest_of_line ();
6704 return;
6705 }
6706 if (initstop > initstart
6707 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6708 --initstop;
6709
6710 SKIP_WHITESPACE ();
6711 endstart = input_line_pointer;
6712
6713 /* Look for BY or DO. */
6714 by = 0;
6715 endstop = NULL;
6716 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6717 {
6718 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6719 && ! is_part_of_name (input_line_pointer[2]))
6720 {
6721 endstop = input_line_pointer;
6722 by = 1;
6723 input_line_pointer += 2;
6724 break;
6725 }
6726 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6727 && (input_line_pointer[2] == '.'
6728 || ! is_part_of_name (input_line_pointer[2])))
6729 {
6730 endstop = input_line_pointer;
6731 input_line_pointer += 2;
6732 break;
6733 }
6734 ++input_line_pointer;
6735 }
6736 if (endstop == NULL)
6737 {
6738 as_bad (_("missing do"));
6739 ignore_rest_of_line ();
6740 return;
6741 }
6742 if (endstop > endstart
6743 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6744 --endstop;
6745
6746 if (! by)
6747 {
6748 bystart = "#1";
6749 bystop = bystart + 2;
6750 }
6751 else
6752 {
6753 SKIP_WHITESPACE ();
6754 bystart = input_line_pointer;
6755
6756 /* Look for DO. */
6757 bystop = NULL;
6758 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6759 {
6760 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6761 && (input_line_pointer[2] == '.'
6762 || ! is_part_of_name (input_line_pointer[2])))
6763 {
6764 bystop = input_line_pointer;
6765 input_line_pointer += 2;
6766 break;
6767 }
6768 ++input_line_pointer;
6769 }
6770 if (bystop == NULL)
6771 {
6772 as_bad (_("missing do"));
6773 ignore_rest_of_line ();
6774 return;
6775 }
6776 if (bystop > bystart
6777 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6778 --bystop;
6779 }
6780
6781 if (*input_line_pointer != '.')
6782 extent = '\0';
6783 else
6784 {
6785 extent = input_line_pointer[1];
6786 input_line_pointer += 2;
6787 }
6788
6789 /* We have fully parsed the FOR operands. Now build the loop. */
6790 n = push_mri_control (mri_for);
6791
6792 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6793
6794 /* Move init,var. */
6795 s = buf;
6796 *s++ = 'm';
6797 *s++ = 'o';
6798 *s++ = 'v';
6799 *s++ = 'e';
6800 if (qual != '\0')
6801 *s++ = TOLOWER (qual);
6802 *s++ = ' ';
6803 memcpy (s, initstart, initstop - initstart);
6804 s += initstop - initstart;
6805 *s++ = ',';
6806 memcpy (s, varstart, varstop - varstart);
6807 s += varstop - varstart;
6808 *s = '\0';
6809 mri_assemble (buf);
6810
6811 colon (n->top);
6812
6813 /* cmp end,var. */
6814 s = buf;
6815 *s++ = 'c';
6816 *s++ = 'm';
6817 *s++ = 'p';
6818 if (qual != '\0')
6819 *s++ = TOLOWER (qual);
6820 *s++ = ' ';
6821 memcpy (s, endstart, endstop - endstart);
6822 s += endstop - endstart;
6823 *s++ = ',';
6824 memcpy (s, varstart, varstop - varstart);
6825 s += varstop - varstart;
6826 *s = '\0';
6827 mri_assemble (buf);
6828
6829 /* bcc bottom. */
6830 ex[0] = TOLOWER (extent);
6831 ex[1] = '\0';
6832 if (up)
6833 sprintf (buf, "blt%s %s", ex, n->bottom);
6834 else
6835 sprintf (buf, "bgt%s %s", ex, n->bottom);
6836 mri_assemble (buf);
6837
6838 /* Put together the add or sub instruction used by ENDF. */
6839 s = buf;
6840 if (up)
6841 strcpy (s, "add");
6842 else
6843 strcpy (s, "sub");
6844 s += 3;
6845 if (qual != '\0')
6846 *s++ = TOLOWER (qual);
6847 *s++ = ' ';
6848 memcpy (s, bystart, bystop - bystart);
6849 s += bystop - bystart;
6850 *s++ = ',';
6851 memcpy (s, varstart, varstop - varstart);
6852 s += varstop - varstart;
6853 *s = '\0';
6854 n->incr = buf;
6855
6856 if (flag_mri)
6857 {
6858 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6859 ++input_line_pointer;
6860 }
6861
6862 demand_empty_rest_of_line ();
6863 }
6864
6865 /* Handle the MRI ENDF pseudo-op. */
6866
6867 static void
6868 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6869 {
6870 if (mri_control_stack == NULL
6871 || mri_control_stack->type != mri_for)
6872 {
6873 as_bad (_("endf without for"));
6874 ignore_rest_of_line ();
6875 return;
6876 }
6877
6878 colon (mri_control_stack->next);
6879
6880 mri_assemble (mri_control_stack->incr);
6881
6882 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6883 mri_assemble (mri_control_stack->incr);
6884
6885 free (mri_control_stack->incr);
6886
6887 colon (mri_control_stack->bottom);
6888
6889 pop_mri_control ();
6890
6891 if (flag_mri)
6892 {
6893 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6894 ++input_line_pointer;
6895 }
6896
6897 demand_empty_rest_of_line ();
6898 }
6899
6900 /* Handle the MRI REPEAT pseudo-op. */
6901
6902 static void
6903 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6904 {
6905 struct mri_control_info *n;
6906
6907 n = push_mri_control (mri_repeat);
6908 colon (n->top);
6909 if (flag_mri)
6910 {
6911 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6912 ++input_line_pointer;
6913 }
6914 demand_empty_rest_of_line ();
6915 }
6916
6917 /* Handle the MRI UNTIL pseudo-op. */
6918
6919 static void
6920 s_mri_until (int qual)
6921 {
6922 char *s;
6923
6924 if (mri_control_stack == NULL
6925 || mri_control_stack->type != mri_repeat)
6926 {
6927 as_bad (_("until without repeat"));
6928 ignore_rest_of_line ();
6929 return;
6930 }
6931
6932 colon (mri_control_stack->next);
6933
6934 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6935 ;
6936
6937 parse_mri_control_expression (s, qual, (const char *) NULL,
6938 mri_control_stack->top, '\0');
6939
6940 colon (mri_control_stack->bottom);
6941
6942 input_line_pointer = s;
6943
6944 pop_mri_control ();
6945
6946 if (flag_mri)
6947 {
6948 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6949 ++input_line_pointer;
6950 }
6951
6952 demand_empty_rest_of_line ();
6953 }
6954
6955 /* Handle the MRI WHILE pseudo-op. */
6956
6957 static void
6958 s_mri_while (int qual)
6959 {
6960 char *s;
6961
6962 struct mri_control_info *n;
6963
6964 s = input_line_pointer;
6965 /* We only accept '*' as introduction of comments if preceded by white space
6966 or at first column of a line (I think this can't actually happen here?)
6967 This is important when assembling:
6968 while d0 <ne> 12(a0,d0*2) do
6969 while d0 <ne> #CONST*20 do. */
6970 while (! (is_end_of_line[(unsigned char) *s]
6971 || (flag_mri
6972 && *s == '*'
6973 && (s == input_line_pointer
6974 || *(s-1) == ' '
6975 || *(s-1) == '\t'))))
6976 s++;
6977 --s;
6978 while (*s == ' ' || *s == '\t')
6979 --s;
6980 if (s - input_line_pointer > 1
6981 && s[-1] == '.')
6982 s -= 2;
6983 if (s - input_line_pointer < 2
6984 || strncasecmp (s - 1, "DO", 2) != 0)
6985 {
6986 as_bad (_("missing do"));
6987 ignore_rest_of_line ();
6988 return;
6989 }
6990
6991 n = push_mri_control (mri_while);
6992
6993 colon (n->next);
6994
6995 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6996 s[1] == '.' ? s[2] : '\0');
6997
6998 input_line_pointer = s + 1;
6999 if (*input_line_pointer == '.')
7000 input_line_pointer += 2;
7001
7002 if (flag_mri)
7003 {
7004 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7005 ++input_line_pointer;
7006 }
7007
7008 demand_empty_rest_of_line ();
7009 }
7010
7011 /* Handle the MRI ENDW pseudo-op. */
7012
7013 static void
7014 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7015 {
7016 char *buf;
7017
7018 if (mri_control_stack == NULL
7019 || mri_control_stack->type != mri_while)
7020 {
7021 as_bad (_("endw without while"));
7022 ignore_rest_of_line ();
7023 return;
7024 }
7025
7026 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7027 sprintf (buf, "bra %s", mri_control_stack->next);
7028 mri_assemble (buf);
7029 free (buf);
7030
7031 colon (mri_control_stack->bottom);
7032
7033 pop_mri_control ();
7034
7035 if (flag_mri)
7036 {
7037 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7038 ++input_line_pointer;
7039 }
7040
7041 demand_empty_rest_of_line ();
7042 }
7043 \f
7044 /* Parse a .cpu directive. */
7045
7046 static void
7047 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7048 {
7049 char saved_char;
7050 char *name;
7051
7052 if (initialized)
7053 {
7054 as_bad (_("already assembled instructions"));
7055 ignore_rest_of_line ();
7056 return;
7057 }
7058
7059 name = input_line_pointer;
7060 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7061 input_line_pointer++;
7062 saved_char = *input_line_pointer;
7063 *input_line_pointer = 0;
7064
7065 m68k_set_cpu (name, 1, 0);
7066
7067 *input_line_pointer = saved_char;
7068 demand_empty_rest_of_line ();
7069 return;
7070 }
7071
7072 /* Parse a .arch directive. */
7073
7074 static void
7075 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7076 {
7077 char saved_char;
7078 char *name;
7079
7080 if (initialized)
7081 {
7082 as_bad (_("already assembled instructions"));
7083 ignore_rest_of_line ();
7084 return;
7085 }
7086
7087 name = input_line_pointer;
7088 while (*input_line_pointer && *input_line_pointer != ','
7089 && !ISSPACE (*input_line_pointer))
7090 input_line_pointer++;
7091 saved_char = *input_line_pointer;
7092 *input_line_pointer = 0;
7093
7094 if (m68k_set_arch (name, 1, 0))
7095 {
7096 /* Scan extensions. */
7097 do
7098 {
7099 *input_line_pointer++ = saved_char;
7100 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7101 break;
7102 name = input_line_pointer;
7103 while (*input_line_pointer && *input_line_pointer != ','
7104 && !ISSPACE (*input_line_pointer))
7105 input_line_pointer++;
7106 saved_char = *input_line_pointer;
7107 *input_line_pointer = 0;
7108 }
7109 while (m68k_set_extension (name, 1, 0));
7110 }
7111
7112 *input_line_pointer = saved_char;
7113 demand_empty_rest_of_line ();
7114 return;
7115 }
7116 \f
7117 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7118 if none is found, the caller is responsible for emitting an error
7119 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7120 cpu name, if it begins with a '6' (possibly skipping an intervening
7121 'c'. We also allow a 'c' in the same place. if NEGATED is
7122 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7123 the option is indeed negated. */
7124
7125 static const struct m68k_cpu *
7126 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7127 int allow_m, int *negated)
7128 {
7129 /* allow negated value? */
7130 if (negated)
7131 {
7132 *negated = 0;
7133
7134 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7135 {
7136 arg += 3;
7137 *negated = 1;
7138 }
7139 }
7140
7141 /* Remove 'm' or 'mc' prefix from 68k variants. */
7142 if (allow_m)
7143 {
7144 if (arg[0] == 'm')
7145 {
7146 if (arg[1] == '6')
7147 arg += 1;
7148 else if (arg[1] == 'c' && arg[2] == '6')
7149 arg += 2;
7150 }
7151 }
7152 else if (arg[0] == 'c' && arg[1] == '6')
7153 arg += 1;
7154
7155 for (; table->name; table++)
7156 if (!strcmp (arg, table->name))
7157 {
7158 if (table->alias < -1 || table->alias > 1)
7159 as_bad (_("`%s' is deprecated, use `%s'"),
7160 table->name, table[table->alias < 0 ? 1 : -1].name);
7161 return table;
7162 }
7163 return 0;
7164 }
7165
7166 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7167
7168 static int
7169 m68k_set_cpu (char const *name, int allow_m, int silent)
7170 {
7171 const struct m68k_cpu *cpu;
7172
7173 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7174
7175 if (!cpu)
7176 {
7177 if (!silent)
7178 as_bad (_("cpu `%s' unrecognized"), name);
7179 return 0;
7180 }
7181
7182 if (selected_cpu && selected_cpu != cpu)
7183 {
7184 as_bad (_("already selected `%s' processor"),
7185 selected_cpu->name);
7186 return 0;
7187 }
7188 selected_cpu = cpu;
7189 return 1;
7190 }
7191
7192 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7193
7194 static int
7195 m68k_set_arch (char const *name, int allow_m, int silent)
7196 {
7197 const struct m68k_cpu *arch;
7198
7199 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7200
7201 if (!arch)
7202 {
7203 if (!silent)
7204 as_bad (_("architecture `%s' unrecognized"), name);
7205 return 0;
7206 }
7207
7208 if (selected_arch && selected_arch != arch)
7209 {
7210 as_bad (_("already selected `%s' architecture"),
7211 selected_arch->name);
7212 return 0;
7213 }
7214
7215 selected_arch = arch;
7216 return 1;
7217 }
7218
7219 /* Set the architecture extension, issuing errors if it is
7220 unrecognized, or invalid */
7221
7222 static int
7223 m68k_set_extension (char const *name, int allow_m, int silent)
7224 {
7225 int negated;
7226 const struct m68k_cpu *ext;
7227
7228 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7229
7230 if (!ext)
7231 {
7232 if (!silent)
7233 as_bad (_("extension `%s' unrecognized"), name);
7234 return 0;
7235 }
7236
7237 if (negated)
7238 not_current_architecture |= ext->arch;
7239 else
7240 current_architecture |= ext->arch;
7241 return 1;
7242 }
7243
7244 /* md_parse_option
7245 Invocation line includes a switch not recognized by the base assembler.
7246 */
7247
7248 #ifdef OBJ_ELF
7249 const char *md_shortopts = "lSA:m:kQ:V";
7250 #else
7251 const char *md_shortopts = "lSA:m:k";
7252 #endif
7253
7254 struct option md_longopts[] = {
7255 #define OPTION_PIC (OPTION_MD_BASE)
7256 {"pic", no_argument, NULL, OPTION_PIC},
7257 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7258 {"register-prefix-optional", no_argument, NULL,
7259 OPTION_REGISTER_PREFIX_OPTIONAL},
7260 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7261 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7262 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7263 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7264 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7265 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7266 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7267 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7268 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7269 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7270 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7271 {"pcrel", no_argument, NULL, OPTION_PCREL},
7272 {NULL, no_argument, NULL, 0}
7273 };
7274 size_t md_longopts_size = sizeof (md_longopts);
7275
7276 int
7277 md_parse_option (int c, char *arg)
7278 {
7279 switch (c)
7280 {
7281 case 'l': /* -l means keep external to 2 bit offset
7282 rather than 16 bit one. */
7283 flag_short_refs = 1;
7284 break;
7285
7286 case 'S': /* -S means that jbsr's always turn into
7287 jsr's. */
7288 flag_long_jumps = 1;
7289 break;
7290
7291 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7292 branches into absolute jumps. */
7293 flag_keep_pcrel = 1;
7294 break;
7295
7296 case OPTION_PIC:
7297 case 'k':
7298 flag_want_pic = 1;
7299 break; /* -pic, Position Independent Code. */
7300
7301 case OPTION_REGISTER_PREFIX_OPTIONAL:
7302 flag_reg_prefix_optional = 1;
7303 reg_prefix_optional_seen = 1;
7304 break;
7305
7306 /* -V: SVR4 argument to print version ID. */
7307 case 'V':
7308 print_version_id ();
7309 break;
7310
7311 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7312 should be emitted or not. FIXME: Not implemented. */
7313 case 'Q':
7314 break;
7315
7316 case OPTION_BITWISE_OR:
7317 {
7318 char *n, *t;
7319 const char *s;
7320
7321 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7322 t = n;
7323 for (s = m68k_comment_chars; *s != '\0'; s++)
7324 if (*s != '|')
7325 *t++ = *s;
7326 *t = '\0';
7327 m68k_comment_chars = n;
7328 }
7329 break;
7330
7331 case OPTION_BASE_SIZE_DEFAULT_16:
7332 m68k_index_width_default = SIZE_WORD;
7333 break;
7334
7335 case OPTION_BASE_SIZE_DEFAULT_32:
7336 m68k_index_width_default = SIZE_LONG;
7337 break;
7338
7339 case OPTION_DISP_SIZE_DEFAULT_16:
7340 m68k_rel32 = 0;
7341 m68k_rel32_from_cmdline = 1;
7342 break;
7343
7344 case OPTION_DISP_SIZE_DEFAULT_32:
7345 m68k_rel32 = 1;
7346 m68k_rel32_from_cmdline = 1;
7347 break;
7348
7349 case 'A':
7350 #if WARN_DEPRECATED
7351 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7352 arg, arg));
7353 #endif
7354 /* Intentional fall-through. */
7355 case 'm':
7356 if (!strncmp (arg, "arch=", 5))
7357 m68k_set_arch (arg + 5, 1, 0);
7358 else if (!strncmp (arg, "cpu=", 4))
7359 m68k_set_cpu (arg + 4, 1, 0);
7360 else if (m68k_set_extension (arg, 0, 1))
7361 ;
7362 else if (m68k_set_arch (arg, 0, 1))
7363 ;
7364 else if (m68k_set_cpu (arg, 0, 1))
7365 ;
7366 else
7367 return 0;
7368 break;
7369
7370 default:
7371 return 0;
7372 }
7373
7374 return 1;
7375 }
7376
7377 /* Setup tables from the selected arch and/or cpu */
7378
7379 static void
7380 m68k_init_arch (void)
7381 {
7382 if (not_current_architecture & current_architecture)
7383 {
7384 as_bad (_("architecture features both enabled and disabled"));
7385 not_current_architecture &= ~current_architecture;
7386 }
7387 if (selected_arch)
7388 {
7389 current_architecture |= selected_arch->arch;
7390 control_regs = selected_arch->control_regs;
7391 }
7392 else
7393 current_architecture |= selected_cpu->arch;
7394
7395 current_architecture &= ~not_current_architecture;
7396
7397 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7398 {
7399 /* Determine which float is really meant. */
7400 if (current_architecture & (m68k_mask & ~m68881))
7401 current_architecture ^= cfloat;
7402 else
7403 current_architecture ^= m68881;
7404 }
7405
7406 if (selected_cpu)
7407 {
7408 control_regs = selected_cpu->control_regs;
7409 if (current_architecture & ~selected_cpu->arch)
7410 {
7411 as_bad (_("selected processor does not have all features of selected architecture"));
7412 current_architecture
7413 = selected_cpu->arch & ~not_current_architecture;
7414 }
7415 }
7416
7417 if ((current_architecture & m68k_mask)
7418 && (current_architecture & ~m68k_mask))
7419 {
7420 as_bad (_ ("m68k and cf features both selected"));
7421 if (current_architecture & m68k_mask)
7422 current_architecture &= m68k_mask;
7423 else
7424 current_architecture &= ~m68k_mask;
7425 }
7426
7427 /* Permit m68881 specification with all cpus; those that can't work
7428 with a coprocessor could be doing emulation. */
7429 if (current_architecture & m68851)
7430 {
7431 if (current_architecture & m68040)
7432 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7433 }
7434 /* What other incompatibilities could we check for? */
7435
7436 if (cpu_of_arch (current_architecture) < m68020
7437 || arch_coldfire_p (current_architecture))
7438 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7439
7440 initialized = 1;
7441 }
7442
7443 void
7444 md_show_usage (FILE *stream)
7445 {
7446 const char *default_cpu = TARGET_CPU;
7447 int i;
7448 unsigned int default_arch;
7449
7450 /* Get the canonical name for the default target CPU. */
7451 if (*default_cpu == 'm')
7452 default_cpu++;
7453 for (i = 0; m68k_cpus[i].name; i++)
7454 {
7455 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7456 {
7457 default_arch = m68k_cpus[i].arch;
7458 while (m68k_cpus[i].alias > 0)
7459 i--;
7460 while (m68k_cpus[i].alias < 0)
7461 i++;
7462 default_cpu = m68k_cpus[i].name;
7463 }
7464 }
7465
7466 fprintf (stream, _("\
7467 -march=<arch> set architecture\n\
7468 -mcpu=<cpu> set cpu [default %s]\n\
7469 "), default_cpu);
7470 for (i = 0; m68k_extensions[i].name; i++)
7471 fprintf (stream, _("\
7472 -m[no-]%-16s enable/disable%s architecture extension\n\
7473 "), m68k_extensions[i].name,
7474 m68k_extensions[i].alias > 0 ? " ColdFire"
7475 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7476
7477 fprintf (stream, _("\
7478 -l use 1 word for refs to undefined symbols [default 2]\n\
7479 -pic, -k generate position independent code\n\
7480 -S turn jbsr into jsr\n\
7481 --pcrel never turn PC-relative branches into absolute jumps\n\
7482 --register-prefix-optional\n\
7483 recognize register names without prefix character\n\
7484 --bitwise-or do not treat `|' as a comment character\n\
7485 --base-size-default-16 base reg without size is 16 bits\n\
7486 --base-size-default-32 base reg without size is 32 bits (default)\n\
7487 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7488 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7489 "));
7490
7491 fprintf (stream, _("Architecture variants are: "));
7492 for (i = 0; m68k_archs[i].name; i++)
7493 {
7494 if (i)
7495 fprintf (stream, " | ");
7496 fprintf (stream, m68k_archs[i].name);
7497 }
7498 fprintf (stream, "\n");
7499
7500 fprintf (stream, _("Processor variants are: "));
7501 for (i = 0; m68k_cpus[i].name; i++)
7502 {
7503 if (i)
7504 fprintf (stream, " | ");
7505 fprintf (stream, m68k_cpus[i].name);
7506 }
7507 fprintf (stream, _("\n"));
7508 }
7509 \f
7510 #ifdef TEST2
7511
7512 /* TEST2: Test md_assemble() */
7513 /* Warning, this routine probably doesn't work anymore. */
7514 int
7515 main (void)
7516 {
7517 struct m68k_it the_ins;
7518 char buf[120];
7519 char *cp;
7520 int n;
7521
7522 m68k_ip_begin ();
7523 for (;;)
7524 {
7525 if (!gets (buf) || !*buf)
7526 break;
7527 if (buf[0] == '|' || buf[1] == '.')
7528 continue;
7529 for (cp = buf; *cp; cp++)
7530 if (*cp == '\t')
7531 *cp = ' ';
7532 if (is_label (buf))
7533 continue;
7534 memset (&the_ins, '\0', sizeof (the_ins));
7535 m68k_ip (&the_ins, buf);
7536 if (the_ins.error)
7537 {
7538 printf (_("Error %s in %s\n"), the_ins.error, buf);
7539 }
7540 else
7541 {
7542 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7543 for (n = 0; n < the_ins.numo; n++)
7544 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7545 printf (" ");
7546 print_the_insn (&the_ins.opcode[0], stdout);
7547 (void) putchar ('\n');
7548 }
7549 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7550 {
7551 if (the_ins.operands[n].error)
7552 {
7553 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7554 continue;
7555 }
7556 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7557 the_ins.operands[n].reg);
7558 if (the_ins.operands[n].b_const)
7559 printf ("Constant: '%.*s', ",
7560 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7561 the_ins.operands[n].b_const);
7562 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7563 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7564 if (the_ins.operands[n].b_iadd)
7565 printf ("Iadd: '%.*s',",
7566 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7567 the_ins.operands[n].b_iadd);
7568 putchar ('\n');
7569 }
7570 }
7571 m68k_ip_end ();
7572 return 0;
7573 }
7574
7575 int
7576 is_label (char *str)
7577 {
7578 while (*str == ' ')
7579 str++;
7580 while (*str && *str != ' ')
7581 str++;
7582 if (str[-1] == ':' || str[1] == '=')
7583 return 1;
7584 return 0;
7585 }
7586
7587 #endif
7588
7589 /* Possible states for relaxation:
7590
7591 0 0 branch offset byte (bra, etc)
7592 0 1 word
7593 0 2 long
7594
7595 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7596 1 1 word
7597 1 2 long
7598
7599 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7600 2 1 word-long
7601 2 2 long-word
7602 2 3 long-long
7603
7604 */
7605
7606 /* We have no need to default values of symbols. */
7607
7608 symbolS *
7609 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7610 {
7611 return 0;
7612 }
7613
7614 /* Round up a section size to the appropriate boundary. */
7615 valueT
7616 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7617 {
7618 #ifdef OBJ_AOUT
7619 /* For a.out, force the section size to be aligned. If we don't do
7620 this, BFD will align it for us, but it will not write out the
7621 final bytes of the section. This may be a bug in BFD, but it is
7622 easier to fix it here since that is how the other a.out targets
7623 work. */
7624 int align;
7625
7626 align = bfd_get_section_alignment (stdoutput, segment);
7627 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7628 #endif
7629
7630 return size;
7631 }
7632
7633 /* Exactly what point is a PC-relative offset relative TO?
7634 On the 68k, it is relative to the address of the first extension
7635 word. The difference between the addresses of the offset and the
7636 first extension word is stored in fx_pcrel_adjust. */
7637 long
7638 md_pcrel_from (fixS *fixP)
7639 {
7640 int adjust;
7641
7642 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7643 sign extend the value here. */
7644 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7645 if (adjust == 64)
7646 adjust = -1;
7647 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7648 }
7649
7650 #ifdef OBJ_ELF
7651 void
7652 m68k_elf_final_processing (void)
7653 {
7654 unsigned flags = 0;
7655
7656 if (arch_coldfire_fpu (current_architecture))
7657 flags |= EF_M68K_CFV4E;
7658 /* Set file-specific flags if this is a cpu32 processor. */
7659 if (cpu_of_arch (current_architecture) & cpu32)
7660 flags |= EF_M68K_CPU32;
7661 else if (cpu_of_arch (current_architecture) & fido_a)
7662 flags |= EF_M68K_FIDO;
7663 else if ((cpu_of_arch (current_architecture) & m68000up)
7664 && !(cpu_of_arch (current_architecture) & m68020up))
7665 flags |= EF_M68K_M68000;
7666
7667 if (current_architecture & mcfisa_a)
7668 {
7669 static const unsigned isa_features[][2] =
7670 {
7671 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7672 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7673 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7674 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7675 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7676 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7677 {0,0},
7678 };
7679 static const unsigned mac_features[][2] =
7680 {
7681 {EF_M68K_CF_MAC, mcfmac},
7682 {EF_M68K_CF_EMAC, mcfemac},
7683 {0,0},
7684 };
7685 unsigned ix;
7686 unsigned pattern;
7687
7688 pattern = (current_architecture
7689 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7690 for (ix = 0; isa_features[ix][1]; ix++)
7691 {
7692 if (pattern == isa_features[ix][1])
7693 {
7694 flags |= isa_features[ix][0];
7695 break;
7696 }
7697 }
7698 if (!isa_features[ix][1])
7699 {
7700 cf_bad:
7701 as_warn (_("Not a defined coldfire architecture"));
7702 }
7703 else
7704 {
7705 if (current_architecture & cfloat)
7706 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7707
7708 pattern = current_architecture & (mcfmac|mcfemac);
7709 if (pattern)
7710 {
7711 for (ix = 0; mac_features[ix][1]; ix++)
7712 {
7713 if (pattern == mac_features[ix][1])
7714 {
7715 flags |= mac_features[ix][0];
7716 break;
7717 }
7718 }
7719 if (!mac_features[ix][1])
7720 goto cf_bad;
7721 }
7722 }
7723 }
7724 elf_elfheader (stdoutput)->e_flags |= flags;
7725 }
7726 #endif
7727
7728 int
7729 tc_m68k_regname_to_dw2regnum (char *regname)
7730 {
7731 unsigned int regnum;
7732 static const char *const regnames[] =
7733 {
7734 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7735 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7736 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7737 "pc"
7738 };
7739
7740 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7741 if (strcmp (regname, regnames[regnum]) == 0)
7742 return regnum;
7743
7744 return -1;
7745 }
7746
7747 void
7748 tc_m68k_frame_initial_instructions (void)
7749 {
7750 static int sp_regno = -1;
7751
7752 if (sp_regno < 0)
7753 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7754
7755 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7756 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7757 }
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