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* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5208_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182 };
183 static const enum m68k_register mcf5213_ctrl[] = {
184 VBR, RAMBAR, FLASHBAR,
185 0
186 };
187 static const enum m68k_register mcf5216_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
189 0
190 };
191 static const enum m68k_register mcf5235_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, RAMBAR,
193 0
194 };
195 static const enum m68k_register mcf5249_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
197 0
198 };
199 static const enum m68k_register mcf5250_ctrl[] = {
200 VBR,
201 0
202 };
203 static const enum m68k_register mcf5271_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206 };
207 static const enum m68k_register mcf5272_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
209 0
210 };
211 static const enum m68k_register mcf5275_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR,
213 0
214 };
215 static const enum m68k_register mcf5282_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
217 0
218 };
219 static const enum m68k_register mcf5329_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR,
221 0
222 };
223 static const enum m68k_register mcf5373_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226 };
227 static const enum m68k_register mcfv4e_ctrl[] = {
228 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
229 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
230 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
231 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
232 0
233 };
234 #define cpu32_ctrl m68010_ctrl
235
236 static const enum m68k_register *control_regs;
237
238 /* Internal form of a 68020 instruction. */
239 struct m68k_it
240 {
241 const char *error;
242 const char *args; /* List of opcode info. */
243 int numargs;
244
245 int numo; /* Number of shorts in opcode. */
246 short opcode[11];
247
248 struct m68k_op operands[6];
249
250 int nexp; /* Number of exprs in use. */
251 struct m68k_exp exprs[4];
252
253 int nfrag; /* Number of frags we have to produce. */
254 struct
255 {
256 int fragoff; /* Where in the current opcode the frag ends. */
257 symbolS *fadd;
258 offsetT foff;
259 int fragty;
260 }
261 fragb[4];
262
263 int nrel; /* Num of reloc strucs in use. */
264 struct
265 {
266 int n;
267 expressionS exp;
268 char wid;
269 char pcrel;
270 /* In a pc relative address the difference between the address
271 of the offset and the address that the offset is relative
272 to. This depends on the addressing mode. Basically this
273 is the value to put in the offset field to address the
274 first byte of the offset, without regarding the special
275 significance of some values (in the branch instruction, for
276 example). */
277 int pcrel_fix;
278 #ifdef OBJ_ELF
279 /* Whether this expression needs special pic relocation, and if
280 so, which. */
281 enum pic_relocation pic_reloc;
282 #endif
283 }
284 reloc[5]; /* Five is enough??? */
285 };
286
287 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
288 #define float_of_arch(x) ((x) & mfloat)
289 #define mmu_of_arch(x) ((x) & mmmu)
290 #define arch_coldfire_p(x) ((x) & mcfisa_a)
291 #define arch_coldfire_fpu(x) ((x) & cfloat)
292
293 /* Macros for determining if cpu supports a specific addressing mode. */
294 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
295
296 static struct m68k_it the_ins; /* The instruction being assembled. */
297
298 #define op(ex) ((ex)->exp.X_op)
299 #define adds(ex) ((ex)->exp.X_add_symbol)
300 #define subs(ex) ((ex)->exp.X_op_symbol)
301 #define offs(ex) ((ex)->exp.X_add_number)
302
303 /* Macros for adding things to the m68k_it struct. */
304 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
305
306 /* Like addword, but goes BEFORE general operands. */
307
308 static void
309 insop (int w, const struct m68k_incant *opcode)
310 {
311 int z;
312 for (z = the_ins.numo; z > opcode->m_codenum; --z)
313 the_ins.opcode[z] = the_ins.opcode[z - 1];
314 for (z = 0; z < the_ins.nrel; z++)
315 the_ins.reloc[z].n += 2;
316 for (z = 0; z < the_ins.nfrag; z++)
317 the_ins.fragb[z].fragoff++;
318 the_ins.opcode[opcode->m_codenum] = w;
319 the_ins.numo++;
320 }
321
322 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
323 Blecch. */
324 static void
325 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
326 {
327 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
328 ? the_ins.numo * 2 - 1
329 : (width == 'b'
330 ? the_ins.numo * 2 + 1
331 : the_ins.numo * 2));
332 the_ins.reloc[the_ins.nrel].exp = exp->exp;
333 the_ins.reloc[the_ins.nrel].wid = width;
334 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
335 #ifdef OBJ_ELF
336 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
337 #endif
338 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
339 }
340
341 /* Cause an extra frag to be generated here, inserting up to 10 bytes
342 (that value is chosen in the frag_var call in md_assemble). TYPE
343 is the subtype of the frag to be generated; its primary type is
344 rs_machine_dependent.
345
346 The TYPE parameter is also used by md_convert_frag_1 and
347 md_estimate_size_before_relax. The appropriate type of fixup will
348 be emitted by md_convert_frag_1.
349
350 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
351 static void
352 add_frag (symbolS *add, offsetT off, int type)
353 {
354 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
355 the_ins.fragb[the_ins.nfrag].fadd = add;
356 the_ins.fragb[the_ins.nfrag].foff = off;
357 the_ins.fragb[the_ins.nfrag++].fragty = type;
358 }
359
360 #define isvar(ex) \
361 (op (ex) != O_constant && op (ex) != O_big)
362
363 static char *crack_operand (char *str, struct m68k_op *opP);
364 static int get_num (struct m68k_exp *exp, int ok);
365 static int reverse_16_bits (int in);
366 static int reverse_8_bits (int in);
367 static void install_gen_operand (int mode, int val);
368 static void install_operand (int mode, int val);
369 static void s_bss (int);
370 static void s_data1 (int);
371 static void s_data2 (int);
372 static void s_even (int);
373 static void s_proc (int);
374 static void s_chip (int);
375 static void s_fopt (int);
376 static void s_opt (int);
377 static void s_reg (int);
378 static void s_restore (int);
379 static void s_save (int);
380 static void s_mri_if (int);
381 static void s_mri_else (int);
382 static void s_mri_endi (int);
383 static void s_mri_break (int);
384 static void s_mri_next (int);
385 static void s_mri_for (int);
386 static void s_mri_endf (int);
387 static void s_mri_repeat (int);
388 static void s_mri_until (int);
389 static void s_mri_while (int);
390 static void s_mri_endw (int);
391 static void s_m68k_cpu (int);
392 static void s_m68k_arch (int);
393
394 struct m68k_cpu
395 {
396 unsigned long arch; /* Architecture features. */
397 const enum m68k_register *control_regs; /* Control regs on chip */
398 const char *name; /* Name */
399 int alias; /* Alias for a cannonical name. If 1, then
400 succeeds canonical name, if -1 then
401 succeeds canonical name, if <-1 ||>1 this is a
402 deprecated name, and the next/previous name
403 should be used. */
404 };
405
406 /* We hold flags for features explicitly enabled and explicitly
407 disabled. */
408 static int current_architecture;
409 static int not_current_architecture;
410 static const struct m68k_cpu *selected_arch;
411 static const struct m68k_cpu *selected_cpu;
412 static int initialized;
413
414 /* Architecture models. */
415 static const struct m68k_cpu m68k_archs[] =
416 {
417 {m68000, m68000_ctrl, "68000", 0},
418 {m68010, m68010_ctrl, "68010", 0},
419 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
420 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
421 {m68040, m68040_ctrl, "68040", 0},
422 {m68060, m68060_ctrl, "68060", 0},
423 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
424 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
425 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
426 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
427 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
428 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
429 {0,0,NULL, 0}
430 };
431
432 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
433 for either. */
434 static const struct m68k_cpu m68k_extensions[] =
435 {
436 {m68851, NULL, "68851", -1},
437 {m68881, NULL, "68881", -1},
438 {m68881, NULL, "68882", -1},
439
440 {cfloat|m68881, NULL, "float", 0},
441
442 {mcfhwdiv, NULL, "div", 1},
443 {mcfusp, NULL, "usp", 1},
444 {mcfmac, NULL, "mac", 1},
445 {mcfemac, NULL, "emac", 1},
446
447 {0,NULL,NULL, 0}
448 };
449
450 /* Processor list */
451 static const struct m68k_cpu m68k_cpus[] =
452 {
453 {m68000, m68000_ctrl, "68000", 0},
454 {m68000, m68000_ctrl, "68ec000", 1},
455 {m68000, m68000_ctrl, "68hc000", 1},
456 {m68000, m68000_ctrl, "68hc001", 1},
457 {m68000, m68000_ctrl, "68008", 1},
458 {m68000, m68000_ctrl, "68302", 1},
459 {m68000, m68000_ctrl, "68306", 1},
460 {m68000, m68000_ctrl, "68307", 1},
461 {m68000, m68000_ctrl, "68322", 1},
462 {m68000, m68000_ctrl, "68356", 1},
463 {m68010, m68010_ctrl, "68010", 0},
464 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
465 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
466 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
467 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
468 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
469 {m68040, m68040_ctrl, "68040", 0},
470 {m68040, m68040_ctrl, "68ec040", 1},
471 {m68060, m68060_ctrl, "68060", 0},
472 {m68060, m68060_ctrl, "68ec060", 1},
473
474 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
475 {cpu32|m68881, cpu32_ctrl, "68330", 1},
476 {cpu32|m68881, cpu32_ctrl, "68331", 1},
477 {cpu32|m68881, cpu32_ctrl, "68332", 1},
478 {cpu32|m68881, cpu32_ctrl, "68333", 1},
479 {cpu32|m68881, cpu32_ctrl, "68334", 1},
480 {cpu32|m68881, cpu32_ctrl, "68336", 1},
481 {cpu32|m68881, cpu32_ctrl, "68340", 1},
482 {cpu32|m68881, cpu32_ctrl, "68341", 1},
483 {cpu32|m68881, cpu32_ctrl, "68349", 1},
484 {cpu32|m68881, cpu32_ctrl, "68360", 1},
485
486 {mcfisa_a, mcf_ctrl, "5200", 0},
487 {mcfisa_a, mcf_ctrl, "5202", 1},
488 {mcfisa_a, mcf_ctrl, "5204", 1},
489 {mcfisa_a, mcf_ctrl, "5206", 1},
490
491 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
492
493 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
494 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
495
496 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
497 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
498 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
499
500 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
501 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
502 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
503
504 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
505 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
506 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
507 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
508 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
509
510 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
511 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
512
513 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
514 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
515
516 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
517
518 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
519 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
520
521 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
522 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
523 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
524 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
525
526 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
527
528 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
530 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
531 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
532
533 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
534 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
535 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
536
537 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
538
539 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
540 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
541 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
542 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
543 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
544 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
545 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
546
547 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
548 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
549 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
550 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
551 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
552 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
553 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
554
555 {0,NULL,NULL, 0}
556 };
557
558 static const struct m68k_cpu *m68k_lookup_cpu
559 (const char *, const struct m68k_cpu *, int, int *);
560 static int m68k_set_arch (const char *, int, int);
561 static int m68k_set_cpu (const char *, int, int);
562 static int m68k_set_extension (const char *, int, int);
563 static void m68k_init_arch (void);
564
565 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
566 architecture and we have a lot of relaxation modes. */
567
568 /* Macros used in the relaxation code. */
569 #define TAB(x,y) (((x) << 2) + (y))
570 #define TABTYPE(x) ((x) >> 2)
571
572 /* Relaxation states. */
573 #define BYTE 0
574 #define SHORT 1
575 #define LONG 2
576 #define SZ_UNDEF 3
577
578 /* Here are all the relaxation modes we support. First we can relax ordinary
579 branches. On 68020 and higher and on CPU32 all branch instructions take
580 three forms, so on these CPUs all branches always remain as such. When we
581 have to expand to the LONG form on a 68000, though, we substitute an
582 absolute jump instead. This is a direct replacement for unconditional
583 branches and a branch over a jump for conditional branches. However, if the
584 user requires PIC and disables this with --pcrel, we can only relax between
585 BYTE and SHORT forms, punting if that isn't enough. This gives us four
586 different relaxation modes for branches: */
587
588 #define BRANCHBWL 0 /* Branch byte, word, or long. */
589 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
590 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
591 #define BRANCHBW 3 /* Branch byte or word. */
592
593 /* We also relax coprocessor branches and DBcc's. All CPUs that support
594 coprocessor branches support them in word and long forms, so we have only
595 one relaxation mode for them. DBcc's are word only on all CPUs. We can
596 relax them to the LONG form with a branch-around sequence. This sequence
597 can use a long branch (if available) or an absolute jump (if acceptable).
598 This gives us two relaxation modes. If long branches are not available and
599 absolute jumps are not acceptable, we don't relax DBcc's. */
600
601 #define FBRANCH 4 /* Coprocessor branch. */
602 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
603 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
604
605 /* That's all for instruction relaxation. However, we also relax PC-relative
606 operands. Specifically, we have three operand relaxation modes. On the
607 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
608 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
609 two. Also PC+displacement+index operands in their simple form (with a non-
610 suppressed index without memory indirection) are supported on all CPUs, but
611 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
612 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
613 form of the PC+displacement+index operand. Finally, some absolute operands
614 can be relaxed down to 16-bit PC-relative. */
615
616 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
617 #define PCINDEX 8 /* PC + displacement + index. */
618 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
619
620 /* Note that calls to frag_var need to specify the maximum expansion
621 needed; this is currently 10 bytes for DBCC. */
622
623 /* The fields are:
624 How far Forward this mode will reach:
625 How far Backward this mode will reach:
626 How many bytes this mode will add to the size of the frag
627 Which mode to go to if the offset won't fit in this one
628
629 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
630 relax_typeS md_relax_table[] =
631 {
632 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
633 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
634 { 0, 0, 4, 0 },
635 { 1, 1, 0, 0 },
636
637 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
638 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
639 { 0, 0, 4, 0 },
640 { 1, 1, 0, 0 },
641
642 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
643 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
644 { 0, 0, 6, 0 },
645 { 1, 1, 0, 0 },
646
647 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
648 { 0, 0, 2, 0 },
649 { 1, 1, 0, 0 },
650 { 1, 1, 0, 0 },
651
652 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
653 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
654 { 0, 0, 4, 0 },
655 { 1, 1, 0, 0 },
656
657 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
658 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
659 { 0, 0, 10, 0 },
660 { 1, 1, 0, 0 },
661
662 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
663 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
664 { 0, 0, 10, 0 },
665 { 1, 1, 0, 0 },
666
667 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
668 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
669 { 0, 0, 6, 0 },
670 { 1, 1, 0, 0 },
671
672 { 125, -130, 0, TAB (PCINDEX, SHORT) },
673 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
674 { 0, 0, 4, 0 },
675 { 1, 1, 0, 0 },
676
677 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
678 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
679 { 0, 0, 4, 0 },
680 { 1, 1, 0, 0 },
681 };
682
683 /* These are the machine dependent pseudo-ops. These are included so
684 the assembler can work on the output from the SUN C compiler, which
685 generates these. */
686
687 /* This table describes all the machine specific pseudo-ops the assembler
688 has to support. The fields are:
689 pseudo-op name without dot
690 function to call to execute this pseudo-op
691 Integer arg to pass to the function. */
692 const pseudo_typeS md_pseudo_table[] =
693 {
694 {"data1", s_data1, 0},
695 {"data2", s_data2, 0},
696 {"bss", s_bss, 0},
697 {"even", s_even, 0},
698 {"skip", s_space, 0},
699 {"proc", s_proc, 0},
700 #if defined (TE_SUN3) || defined (OBJ_ELF)
701 {"align", s_align_bytes, 0},
702 #endif
703 #ifdef OBJ_ELF
704 {"swbeg", s_ignore, 0},
705 #endif
706 {"extend", float_cons, 'x'},
707 {"ldouble", float_cons, 'x'},
708
709 {"arch", s_m68k_arch, 0},
710 {"cpu", s_m68k_cpu, 0},
711
712 /* The following pseudo-ops are supported for MRI compatibility. */
713 {"chip", s_chip, 0},
714 {"comline", s_space, 1},
715 {"fopt", s_fopt, 0},
716 {"mask2", s_ignore, 0},
717 {"opt", s_opt, 0},
718 {"reg", s_reg, 0},
719 {"restore", s_restore, 0},
720 {"save", s_save, 0},
721
722 {"if", s_mri_if, 0},
723 {"if.b", s_mri_if, 'b'},
724 {"if.w", s_mri_if, 'w'},
725 {"if.l", s_mri_if, 'l'},
726 {"else", s_mri_else, 0},
727 {"else.s", s_mri_else, 's'},
728 {"else.l", s_mri_else, 'l'},
729 {"endi", s_mri_endi, 0},
730 {"break", s_mri_break, 0},
731 {"break.s", s_mri_break, 's'},
732 {"break.l", s_mri_break, 'l'},
733 {"next", s_mri_next, 0},
734 {"next.s", s_mri_next, 's'},
735 {"next.l", s_mri_next, 'l'},
736 {"for", s_mri_for, 0},
737 {"for.b", s_mri_for, 'b'},
738 {"for.w", s_mri_for, 'w'},
739 {"for.l", s_mri_for, 'l'},
740 {"endf", s_mri_endf, 0},
741 {"repeat", s_mri_repeat, 0},
742 {"until", s_mri_until, 0},
743 {"until.b", s_mri_until, 'b'},
744 {"until.w", s_mri_until, 'w'},
745 {"until.l", s_mri_until, 'l'},
746 {"while", s_mri_while, 0},
747 {"while.b", s_mri_while, 'b'},
748 {"while.w", s_mri_while, 'w'},
749 {"while.l", s_mri_while, 'l'},
750 {"endw", s_mri_endw, 0},
751
752 {0, 0, 0}
753 };
754
755 /* The mote pseudo ops are put into the opcode table, since they
756 don't start with a . they look like opcodes to gas. */
757
758 const pseudo_typeS mote_pseudo_table[] =
759 {
760
761 {"dcl", cons, 4},
762 {"dc", cons, 2},
763 {"dcw", cons, 2},
764 {"dcb", cons, 1},
765
766 {"dsl", s_space, 4},
767 {"ds", s_space, 2},
768 {"dsw", s_space, 2},
769 {"dsb", s_space, 1},
770
771 {"xdef", s_globl, 0},
772 #ifdef OBJ_ELF
773 {"align", s_align_bytes, 0},
774 #else
775 {"align", s_align_ptwo, 0},
776 #endif
777 #ifdef M68KCOFF
778 {"sect", obj_coff_section, 0},
779 {"section", obj_coff_section, 0},
780 #endif
781 {0, 0, 0}
782 };
783
784 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
785 gives identical results to a 32-bit host. */
786 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
787 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
788
789 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
790 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
791 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
792 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
793
794 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
795 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
796 #define islong(x) (1)
797
798 static char notend_table[256];
799 static char alt_notend_table[256];
800 #define notend(s) \
801 (! (notend_table[(unsigned char) *s] \
802 || (*s == ':' \
803 && alt_notend_table[(unsigned char) s[1]])))
804
805 #ifdef OBJ_ELF
806
807 /* Return zero if the reference to SYMBOL from within the same segment may
808 be relaxed. */
809
810 /* On an ELF system, we can't relax an externally visible symbol,
811 because it may be overridden by a shared library. However, if
812 TARGET_OS is "elf", then we presume that we are assembling for an
813 embedded system, in which case we don't have to worry about shared
814 libraries, and we can relax any external sym. */
815
816 #define relaxable_symbol(symbol) \
817 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
818 || S_IS_WEAK (symbol)))
819
820 /* Compute the relocation code for a fixup of SIZE bytes, using pc
821 relative relocation if PCREL is non-zero. PIC says whether a special
822 pic relocation was requested. */
823
824 static bfd_reloc_code_real_type
825 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
826 {
827 switch (pic)
828 {
829 case pic_got_pcrel:
830 switch (size)
831 {
832 case 1:
833 return BFD_RELOC_8_GOT_PCREL;
834 case 2:
835 return BFD_RELOC_16_GOT_PCREL;
836 case 4:
837 return BFD_RELOC_32_GOT_PCREL;
838 }
839 break;
840
841 case pic_got_off:
842 switch (size)
843 {
844 case 1:
845 return BFD_RELOC_8_GOTOFF;
846 case 2:
847 return BFD_RELOC_16_GOTOFF;
848 case 4:
849 return BFD_RELOC_32_GOTOFF;
850 }
851 break;
852
853 case pic_plt_pcrel:
854 switch (size)
855 {
856 case 1:
857 return BFD_RELOC_8_PLT_PCREL;
858 case 2:
859 return BFD_RELOC_16_PLT_PCREL;
860 case 4:
861 return BFD_RELOC_32_PLT_PCREL;
862 }
863 break;
864
865 case pic_plt_off:
866 switch (size)
867 {
868 case 1:
869 return BFD_RELOC_8_PLTOFF;
870 case 2:
871 return BFD_RELOC_16_PLTOFF;
872 case 4:
873 return BFD_RELOC_32_PLTOFF;
874 }
875 break;
876
877 case pic_none:
878 if (pcrel)
879 {
880 switch (size)
881 {
882 case 1:
883 return BFD_RELOC_8_PCREL;
884 case 2:
885 return BFD_RELOC_16_PCREL;
886 case 4:
887 return BFD_RELOC_32_PCREL;
888 }
889 }
890 else
891 {
892 switch (size)
893 {
894 case 1:
895 return BFD_RELOC_8;
896 case 2:
897 return BFD_RELOC_16;
898 case 4:
899 return BFD_RELOC_32;
900 }
901 }
902 }
903
904 if (pcrel)
905 {
906 if (pic == pic_none)
907 as_bad (_("Can not do %d byte pc-relative relocation"), size);
908 else
909 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
910 }
911 else
912 {
913 if (pic == pic_none)
914 as_bad (_("Can not do %d byte relocation"), size);
915 else
916 as_bad (_("Can not do %d byte pic relocation"), size);
917 }
918
919 return BFD_RELOC_NONE;
920 }
921
922 /* Here we decide which fixups can be adjusted to make them relative
923 to the beginning of the section instead of the symbol. Basically
924 we need to make sure that the dynamic relocations are done
925 correctly, so in some cases we force the original symbol to be
926 used. */
927 int
928 tc_m68k_fix_adjustable (fixS *fixP)
929 {
930 /* Adjust_reloc_syms doesn't know about the GOT. */
931 switch (fixP->fx_r_type)
932 {
933 case BFD_RELOC_8_GOT_PCREL:
934 case BFD_RELOC_16_GOT_PCREL:
935 case BFD_RELOC_32_GOT_PCREL:
936 case BFD_RELOC_8_GOTOFF:
937 case BFD_RELOC_16_GOTOFF:
938 case BFD_RELOC_32_GOTOFF:
939 case BFD_RELOC_8_PLT_PCREL:
940 case BFD_RELOC_16_PLT_PCREL:
941 case BFD_RELOC_32_PLT_PCREL:
942 case BFD_RELOC_8_PLTOFF:
943 case BFD_RELOC_16_PLTOFF:
944 case BFD_RELOC_32_PLTOFF:
945 return 0;
946
947 case BFD_RELOC_VTABLE_INHERIT:
948 case BFD_RELOC_VTABLE_ENTRY:
949 return 0;
950
951 default:
952 return 1;
953 }
954 }
955
956 #else /* !OBJ_ELF */
957
958 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
959
960 #define relaxable_symbol(symbol) 1
961
962 #endif /* OBJ_ELF */
963
964 arelent *
965 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
966 {
967 arelent *reloc;
968 bfd_reloc_code_real_type code;
969
970 /* If the tcbit is set, then this was a fixup of a negative value
971 that was never resolved. We do not have a reloc to handle this,
972 so just return. We assume that other code will have detected this
973 situation and produced a helpful error message, so we just tell the
974 user that the reloc cannot be produced. */
975 if (fixp->fx_tcbit)
976 {
977 if (fixp->fx_addsy)
978 as_bad_where (fixp->fx_file, fixp->fx_line,
979 _("Unable to produce reloc against symbol '%s'"),
980 S_GET_NAME (fixp->fx_addsy));
981 return NULL;
982 }
983
984 if (fixp->fx_r_type != BFD_RELOC_NONE)
985 {
986 code = fixp->fx_r_type;
987
988 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
989 that fixup_segment converted a non-PC relative reloc into a
990 PC relative reloc. In such a case, we need to convert the
991 reloc code. */
992 if (fixp->fx_pcrel)
993 {
994 switch (code)
995 {
996 case BFD_RELOC_8:
997 code = BFD_RELOC_8_PCREL;
998 break;
999 case BFD_RELOC_16:
1000 code = BFD_RELOC_16_PCREL;
1001 break;
1002 case BFD_RELOC_32:
1003 code = BFD_RELOC_32_PCREL;
1004 break;
1005 case BFD_RELOC_8_PCREL:
1006 case BFD_RELOC_16_PCREL:
1007 case BFD_RELOC_32_PCREL:
1008 case BFD_RELOC_8_GOT_PCREL:
1009 case BFD_RELOC_16_GOT_PCREL:
1010 case BFD_RELOC_32_GOT_PCREL:
1011 case BFD_RELOC_8_GOTOFF:
1012 case BFD_RELOC_16_GOTOFF:
1013 case BFD_RELOC_32_GOTOFF:
1014 case BFD_RELOC_8_PLT_PCREL:
1015 case BFD_RELOC_16_PLT_PCREL:
1016 case BFD_RELOC_32_PLT_PCREL:
1017 case BFD_RELOC_8_PLTOFF:
1018 case BFD_RELOC_16_PLTOFF:
1019 case BFD_RELOC_32_PLTOFF:
1020 break;
1021 default:
1022 as_bad_where (fixp->fx_file, fixp->fx_line,
1023 _("Cannot make %s relocation PC relative"),
1024 bfd_get_reloc_code_name (code));
1025 }
1026 }
1027 }
1028 else
1029 {
1030 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1031 switch (F (fixp->fx_size, fixp->fx_pcrel))
1032 {
1033 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1034 MAP (1, 0, BFD_RELOC_8);
1035 MAP (2, 0, BFD_RELOC_16);
1036 MAP (4, 0, BFD_RELOC_32);
1037 MAP (1, 1, BFD_RELOC_8_PCREL);
1038 MAP (2, 1, BFD_RELOC_16_PCREL);
1039 MAP (4, 1, BFD_RELOC_32_PCREL);
1040 default:
1041 abort ();
1042 }
1043 }
1044 #undef F
1045 #undef MAP
1046
1047 reloc = (arelent *) xmalloc (sizeof (arelent));
1048 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1049 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1050 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1051 #ifndef OBJ_ELF
1052 if (fixp->fx_pcrel)
1053 reloc->addend = fixp->fx_addnumber;
1054 else
1055 reloc->addend = 0;
1056 #else
1057 if (!fixp->fx_pcrel)
1058 reloc->addend = fixp->fx_addnumber;
1059 else
1060 reloc->addend = (section->vma
1061 /* Explicit sign extension in case char is
1062 unsigned. */
1063 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1064 + fixp->fx_addnumber
1065 + md_pcrel_from (fixp));
1066 #endif
1067
1068 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1069 assert (reloc->howto != 0);
1070
1071 return reloc;
1072 }
1073
1074 /* Handle of the OPCODE hash table. NULL means any use before
1075 m68k_ip_begin() will crash. */
1076 static struct hash_control *op_hash;
1077 \f
1078 /* Assemble an m68k instruction. */
1079
1080 static void
1081 m68k_ip (char *instring)
1082 {
1083 register char *p;
1084 register struct m68k_op *opP;
1085 register const struct m68k_incant *opcode;
1086 register const char *s;
1087 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1088 char *pdot, *pdotmove;
1089 enum m68k_size siz1, siz2;
1090 char c;
1091 int losing;
1092 int opsfound;
1093 struct m68k_op operands_backup[6];
1094 LITTLENUM_TYPE words[6];
1095 LITTLENUM_TYPE *wordp;
1096 unsigned long ok_arch = 0;
1097
1098 if (*instring == ' ')
1099 instring++; /* Skip leading whitespace. */
1100
1101 /* Scan up to end of operation-code, which MUST end in end-of-string
1102 or exactly 1 space. */
1103 pdot = 0;
1104 for (p = instring; *p != '\0'; p++)
1105 {
1106 if (*p == ' ')
1107 break;
1108 if (*p == '.')
1109 pdot = p;
1110 }
1111
1112 if (p == instring)
1113 {
1114 the_ins.error = _("No operator");
1115 return;
1116 }
1117
1118 /* p now points to the end of the opcode name, probably whitespace.
1119 Make sure the name is null terminated by clobbering the
1120 whitespace, look it up in the hash table, then fix it back.
1121 Remove a dot, first, since the opcode tables have none. */
1122 if (pdot != NULL)
1123 {
1124 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1125 *pdotmove = pdotmove[1];
1126 p--;
1127 }
1128
1129 c = *p;
1130 *p = '\0';
1131 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1132 *p = c;
1133
1134 if (pdot != NULL)
1135 {
1136 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1137 *pdotmove = pdotmove[-1];
1138 *pdot = '.';
1139 ++p;
1140 }
1141
1142 if (opcode == NULL)
1143 {
1144 the_ins.error = _("Unknown operator");
1145 return;
1146 }
1147
1148 /* Found a legitimate opcode, start matching operands. */
1149 while (*p == ' ')
1150 ++p;
1151
1152 if (opcode->m_operands == 0)
1153 {
1154 char *old = input_line_pointer;
1155 *old = '\n';
1156 input_line_pointer = p;
1157 /* Ahh - it's a motorola style psuedo op. */
1158 mote_pseudo_table[opcode->m_opnum].poc_handler
1159 (mote_pseudo_table[opcode->m_opnum].poc_val);
1160 input_line_pointer = old;
1161 *old = 0;
1162
1163 return;
1164 }
1165
1166 if (flag_mri && opcode->m_opnum == 0)
1167 {
1168 /* In MRI mode, random garbage is allowed after an instruction
1169 which accepts no operands. */
1170 the_ins.args = opcode->m_operands;
1171 the_ins.numargs = opcode->m_opnum;
1172 the_ins.numo = opcode->m_codenum;
1173 the_ins.opcode[0] = getone (opcode);
1174 the_ins.opcode[1] = gettwo (opcode);
1175 return;
1176 }
1177
1178 for (opP = &the_ins.operands[0]; *p; opP++)
1179 {
1180 p = crack_operand (p, opP);
1181
1182 if (opP->error)
1183 {
1184 the_ins.error = opP->error;
1185 return;
1186 }
1187 }
1188
1189 opsfound = opP - &the_ins.operands[0];
1190
1191 /* This ugly hack is to support the floating pt opcodes in their
1192 standard form. Essentially, we fake a first enty of type COP#1 */
1193 if (opcode->m_operands[0] == 'I')
1194 {
1195 int n;
1196
1197 for (n = opsfound; n > 0; --n)
1198 the_ins.operands[n] = the_ins.operands[n - 1];
1199
1200 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1201 the_ins.operands[0].mode = CONTROL;
1202 the_ins.operands[0].reg = m68k_float_copnum;
1203 opsfound++;
1204 }
1205
1206 /* We've got the operands. Find an opcode that'll accept them. */
1207 for (losing = 0;;)
1208 {
1209 /* If we didn't get the right number of ops, or we have no
1210 common model with this pattern then reject this pattern. */
1211
1212 ok_arch |= opcode->m_arch;
1213 if (opsfound != opcode->m_opnum
1214 || ((opcode->m_arch & current_architecture) == 0))
1215 ++losing;
1216 else
1217 {
1218 int i;
1219
1220 /* Make a copy of the operands of this insn so that
1221 we can modify them safely, should we want to. */
1222 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1223 for (i = 0; i < opsfound; i++)
1224 operands_backup[i] = the_ins.operands[i];
1225
1226 for (s = opcode->m_operands, opP = &operands_backup[0];
1227 *s && !losing;
1228 s += 2, opP++)
1229 {
1230 /* Warning: this switch is huge! */
1231 /* I've tried to organize the cases into this order:
1232 non-alpha first, then alpha by letter. Lower-case
1233 goes directly before uppercase counterpart. */
1234 /* Code with multiple case ...: gets sorted by the lowest
1235 case ... it belongs to. I hope this makes sense. */
1236 switch (*s)
1237 {
1238 case '!':
1239 switch (opP->mode)
1240 {
1241 case IMMED:
1242 case DREG:
1243 case AREG:
1244 case FPREG:
1245 case CONTROL:
1246 case AINC:
1247 case ADEC:
1248 case REGLST:
1249 losing++;
1250 break;
1251 default:
1252 break;
1253 }
1254 break;
1255
1256 case '<':
1257 switch (opP->mode)
1258 {
1259 case DREG:
1260 case AREG:
1261 case FPREG:
1262 case CONTROL:
1263 case IMMED:
1264 case ADEC:
1265 case REGLST:
1266 losing++;
1267 break;
1268 default:
1269 break;
1270 }
1271 break;
1272
1273 case '>':
1274 switch (opP->mode)
1275 {
1276 case DREG:
1277 case AREG:
1278 case FPREG:
1279 case CONTROL:
1280 case IMMED:
1281 case AINC:
1282 case REGLST:
1283 losing++;
1284 break;
1285 case ABSL:
1286 break;
1287 default:
1288 if (opP->reg == PC
1289 || opP->reg == ZPC)
1290 losing++;
1291 break;
1292 }
1293 break;
1294
1295 case 'm':
1296 switch (opP->mode)
1297 {
1298 case DREG:
1299 case AREG:
1300 case AINDR:
1301 case AINC:
1302 case ADEC:
1303 break;
1304 default:
1305 losing++;
1306 }
1307 break;
1308
1309 case 'n':
1310 switch (opP->mode)
1311 {
1312 case DISP:
1313 break;
1314 default:
1315 losing++;
1316 }
1317 break;
1318
1319 case 'o':
1320 switch (opP->mode)
1321 {
1322 case BASE:
1323 case ABSL:
1324 case IMMED:
1325 break;
1326 default:
1327 losing++;
1328 }
1329 break;
1330
1331 case 'p':
1332 switch (opP->mode)
1333 {
1334 case DREG:
1335 case AREG:
1336 case AINDR:
1337 case AINC:
1338 case ADEC:
1339 break;
1340 case DISP:
1341 if (opP->reg == PC || opP->reg == ZPC)
1342 losing++;
1343 break;
1344 default:
1345 losing++;
1346 }
1347 break;
1348
1349 case 'q':
1350 switch (opP->mode)
1351 {
1352 case DREG:
1353 case AINDR:
1354 case AINC:
1355 case ADEC:
1356 break;
1357 case DISP:
1358 if (opP->reg == PC || opP->reg == ZPC)
1359 losing++;
1360 break;
1361 default:
1362 losing++;
1363 break;
1364 }
1365 break;
1366
1367 case 'v':
1368 switch (opP->mode)
1369 {
1370 case DREG:
1371 case AINDR:
1372 case AINC:
1373 case ADEC:
1374 case ABSL:
1375 break;
1376 case DISP:
1377 if (opP->reg == PC || opP->reg == ZPC)
1378 losing++;
1379 break;
1380 default:
1381 losing++;
1382 break;
1383 }
1384 break;
1385
1386 case '#':
1387 if (opP->mode != IMMED)
1388 losing++;
1389 else if (s[1] == 'b'
1390 && ! isvar (&opP->disp)
1391 && (opP->disp.exp.X_op != O_constant
1392 || ! isbyte (opP->disp.exp.X_add_number)))
1393 losing++;
1394 else if (s[1] == 'B'
1395 && ! isvar (&opP->disp)
1396 && (opP->disp.exp.X_op != O_constant
1397 || ! issbyte (opP->disp.exp.X_add_number)))
1398 losing++;
1399 else if (s[1] == 'w'
1400 && ! isvar (&opP->disp)
1401 && (opP->disp.exp.X_op != O_constant
1402 || ! isword (opP->disp.exp.X_add_number)))
1403 losing++;
1404 else if (s[1] == 'W'
1405 && ! isvar (&opP->disp)
1406 && (opP->disp.exp.X_op != O_constant
1407 || ! issword (opP->disp.exp.X_add_number)))
1408 losing++;
1409 break;
1410
1411 case '^':
1412 case 'T':
1413 if (opP->mode != IMMED)
1414 losing++;
1415 break;
1416
1417 case '$':
1418 if (opP->mode == AREG
1419 || opP->mode == CONTROL
1420 || opP->mode == FPREG
1421 || opP->mode == IMMED
1422 || opP->mode == REGLST
1423 || (opP->mode != ABSL
1424 && (opP->reg == PC
1425 || opP->reg == ZPC)))
1426 losing++;
1427 break;
1428
1429 case '%':
1430 if (opP->mode == CONTROL
1431 || opP->mode == FPREG
1432 || opP->mode == REGLST
1433 || opP->mode == IMMED
1434 || (opP->mode != ABSL
1435 && (opP->reg == PC
1436 || opP->reg == ZPC)))
1437 losing++;
1438 break;
1439
1440 case '&':
1441 switch (opP->mode)
1442 {
1443 case DREG:
1444 case AREG:
1445 case FPREG:
1446 case CONTROL:
1447 case IMMED:
1448 case AINC:
1449 case ADEC:
1450 case REGLST:
1451 losing++;
1452 break;
1453 case ABSL:
1454 break;
1455 default:
1456 if (opP->reg == PC
1457 || opP->reg == ZPC)
1458 losing++;
1459 break;
1460 }
1461 break;
1462
1463 case '*':
1464 if (opP->mode == CONTROL
1465 || opP->mode == FPREG
1466 || opP->mode == REGLST)
1467 losing++;
1468 break;
1469
1470 case '+':
1471 if (opP->mode != AINC)
1472 losing++;
1473 break;
1474
1475 case '-':
1476 if (opP->mode != ADEC)
1477 losing++;
1478 break;
1479
1480 case '/':
1481 switch (opP->mode)
1482 {
1483 case AREG:
1484 case CONTROL:
1485 case FPREG:
1486 case AINC:
1487 case ADEC:
1488 case IMMED:
1489 case REGLST:
1490 losing++;
1491 break;
1492 default:
1493 break;
1494 }
1495 break;
1496
1497 case ';':
1498 switch (opP->mode)
1499 {
1500 case AREG:
1501 case CONTROL:
1502 case FPREG:
1503 case REGLST:
1504 losing++;
1505 break;
1506 default:
1507 break;
1508 }
1509 break;
1510
1511 case '?':
1512 switch (opP->mode)
1513 {
1514 case AREG:
1515 case CONTROL:
1516 case FPREG:
1517 case AINC:
1518 case ADEC:
1519 case IMMED:
1520 case REGLST:
1521 losing++;
1522 break;
1523 case ABSL:
1524 break;
1525 default:
1526 if (opP->reg == PC || opP->reg == ZPC)
1527 losing++;
1528 break;
1529 }
1530 break;
1531
1532 case '@':
1533 switch (opP->mode)
1534 {
1535 case AREG:
1536 case CONTROL:
1537 case FPREG:
1538 case IMMED:
1539 case REGLST:
1540 losing++;
1541 break;
1542 default:
1543 break;
1544 }
1545 break;
1546
1547 case '~': /* For now! (JF FOO is this right?) */
1548 switch (opP->mode)
1549 {
1550 case DREG:
1551 case AREG:
1552 case CONTROL:
1553 case FPREG:
1554 case IMMED:
1555 case REGLST:
1556 losing++;
1557 break;
1558 case ABSL:
1559 break;
1560 default:
1561 if (opP->reg == PC
1562 || opP->reg == ZPC)
1563 losing++;
1564 break;
1565 }
1566 break;
1567
1568 case '3':
1569 if (opP->mode != CONTROL
1570 || (opP->reg != TT0 && opP->reg != TT1))
1571 losing++;
1572 break;
1573
1574 case 'A':
1575 if (opP->mode != AREG)
1576 losing++;
1577 break;
1578
1579 case 'a':
1580 if (opP->mode != AINDR)
1581 ++losing;
1582 break;
1583
1584 case '4':
1585 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1586 && (opP->mode != DISP
1587 || opP->reg < ADDR0
1588 || opP->reg > ADDR7))
1589 ++losing;
1590 break;
1591
1592 case 'B': /* FOO */
1593 if (opP->mode != ABSL
1594 || (flag_long_jumps
1595 && strncmp (instring, "jbsr", 4) == 0))
1596 losing++;
1597 break;
1598
1599 case 'b':
1600 switch (opP->mode)
1601 {
1602 case IMMED:
1603 case ABSL:
1604 case AREG:
1605 case FPREG:
1606 case CONTROL:
1607 case POST:
1608 case PRE:
1609 case REGLST:
1610 losing++;
1611 break;
1612 default:
1613 break;
1614 }
1615 break;
1616
1617 case 'C':
1618 if (opP->mode != CONTROL || opP->reg != CCR)
1619 losing++;
1620 break;
1621
1622 case 'd':
1623 if (opP->mode != DISP
1624 || opP->reg < ADDR0
1625 || opP->reg > ADDR7)
1626 losing++;
1627 break;
1628
1629 case 'D':
1630 if (opP->mode != DREG)
1631 losing++;
1632 break;
1633
1634 case 'E':
1635 if (opP->reg != ACC)
1636 losing++;
1637 break;
1638
1639 case 'e':
1640 if (opP->reg != ACC && opP->reg != ACC1
1641 && opP->reg != ACC2 && opP->reg != ACC3)
1642 losing++;
1643 break;
1644
1645 case 'F':
1646 if (opP->mode != FPREG)
1647 losing++;
1648 break;
1649
1650 case 'G':
1651 if (opP->reg != MACSR)
1652 losing++;
1653 break;
1654
1655 case 'g':
1656 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1657 losing++;
1658 break;
1659
1660 case 'H':
1661 if (opP->reg != MASK)
1662 losing++;
1663 break;
1664
1665 case 'I':
1666 if (opP->mode != CONTROL
1667 || opP->reg < COP0
1668 || opP->reg > COP7)
1669 losing++;
1670 break;
1671
1672 case 'i':
1673 if (opP->mode != LSH && opP->mode != RSH)
1674 losing++;
1675 break;
1676
1677 case 'J':
1678 if (opP->mode != CONTROL
1679 || opP->reg < USP
1680 || opP->reg > last_movec_reg
1681 || !control_regs)
1682 losing++;
1683 else
1684 {
1685 const enum m68k_register *rp;
1686
1687 for (rp = control_regs; *rp; rp++)
1688 if (*rp == opP->reg)
1689 break;
1690 if (*rp == 0)
1691 losing++;
1692 }
1693 break;
1694
1695 case 'k':
1696 if (opP->mode != IMMED)
1697 losing++;
1698 break;
1699
1700 case 'l':
1701 case 'L':
1702 if (opP->mode == DREG
1703 || opP->mode == AREG
1704 || opP->mode == FPREG)
1705 {
1706 if (s[1] == '8')
1707 losing++;
1708 else
1709 {
1710 switch (opP->mode)
1711 {
1712 case DREG:
1713 opP->mask = 1 << (opP->reg - DATA0);
1714 break;
1715 case AREG:
1716 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1717 break;
1718 case FPREG:
1719 opP->mask = 1 << (opP->reg - FP0 + 16);
1720 break;
1721 default:
1722 abort ();
1723 }
1724 opP->mode = REGLST;
1725 }
1726 }
1727 else if (opP->mode == CONTROL)
1728 {
1729 if (s[1] != '8')
1730 losing++;
1731 else
1732 {
1733 switch (opP->reg)
1734 {
1735 case FPI:
1736 opP->mask = 1 << 24;
1737 break;
1738 case FPS:
1739 opP->mask = 1 << 25;
1740 break;
1741 case FPC:
1742 opP->mask = 1 << 26;
1743 break;
1744 default:
1745 losing++;
1746 break;
1747 }
1748 opP->mode = REGLST;
1749 }
1750 }
1751 else if (opP->mode != REGLST)
1752 losing++;
1753 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1754 losing++;
1755 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1756 losing++;
1757 break;
1758
1759 case 'M':
1760 if (opP->mode != IMMED)
1761 losing++;
1762 else if (opP->disp.exp.X_op != O_constant
1763 || ! issbyte (opP->disp.exp.X_add_number))
1764 losing++;
1765 else if (! m68k_quick
1766 && instring[3] != 'q'
1767 && instring[4] != 'q')
1768 losing++;
1769 break;
1770
1771 case 'O':
1772 if (opP->mode != DREG
1773 && opP->mode != IMMED
1774 && opP->mode != ABSL)
1775 losing++;
1776 break;
1777
1778 case 'Q':
1779 if (opP->mode != IMMED)
1780 losing++;
1781 else if (opP->disp.exp.X_op != O_constant
1782 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1783 losing++;
1784 else if (! m68k_quick
1785 && (strncmp (instring, "add", 3) == 0
1786 || strncmp (instring, "sub", 3) == 0)
1787 && instring[3] != 'q')
1788 losing++;
1789 break;
1790
1791 case 'R':
1792 if (opP->mode != DREG && opP->mode != AREG)
1793 losing++;
1794 break;
1795
1796 case 'r':
1797 if (opP->mode != AINDR
1798 && (opP->mode != BASE
1799 || (opP->reg != 0
1800 && opP->reg != ZADDR0)
1801 || opP->disp.exp.X_op != O_absent
1802 || ((opP->index.reg < DATA0
1803 || opP->index.reg > DATA7)
1804 && (opP->index.reg < ADDR0
1805 || opP->index.reg > ADDR7))
1806 || opP->index.size != SIZE_UNSPEC
1807 || opP->index.scale != 1))
1808 losing++;
1809 break;
1810
1811 case 's':
1812 if (opP->mode != CONTROL
1813 || ! (opP->reg == FPI
1814 || opP->reg == FPS
1815 || opP->reg == FPC))
1816 losing++;
1817 break;
1818
1819 case 'S':
1820 if (opP->mode != CONTROL || opP->reg != SR)
1821 losing++;
1822 break;
1823
1824 case 't':
1825 if (opP->mode != IMMED)
1826 losing++;
1827 else if (opP->disp.exp.X_op != O_constant
1828 || TRUNC (opP->disp.exp.X_add_number) > 7)
1829 losing++;
1830 break;
1831
1832 case 'U':
1833 if (opP->mode != CONTROL || opP->reg != USP)
1834 losing++;
1835 break;
1836
1837 case 'x':
1838 if (opP->mode != IMMED)
1839 losing++;
1840 else if (opP->disp.exp.X_op != O_constant
1841 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1842 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1843 losing++;
1844 break;
1845
1846 /* JF these are out of order. We could put them
1847 in order if we were willing to put up with
1848 bunches of #ifdef m68851s in the code.
1849
1850 Don't forget that you need these operands
1851 to use 68030 MMU instructions. */
1852 #ifndef NO_68851
1853 /* Memory addressing mode used by pflushr. */
1854 case '|':
1855 if (opP->mode == CONTROL
1856 || opP->mode == FPREG
1857 || opP->mode == DREG
1858 || opP->mode == AREG
1859 || opP->mode == REGLST)
1860 losing++;
1861 /* We should accept immediate operands, but they
1862 supposedly have to be quad word, and we don't
1863 handle that. I would like to see what a Motorola
1864 assembler does before doing something here. */
1865 if (opP->mode == IMMED)
1866 losing++;
1867 break;
1868
1869 case 'f':
1870 if (opP->mode != CONTROL
1871 || (opP->reg != SFC && opP->reg != DFC))
1872 losing++;
1873 break;
1874
1875 case '0':
1876 if (opP->mode != CONTROL || opP->reg != TC)
1877 losing++;
1878 break;
1879
1880 case '1':
1881 if (opP->mode != CONTROL || opP->reg != AC)
1882 losing++;
1883 break;
1884
1885 case '2':
1886 if (opP->mode != CONTROL
1887 || (opP->reg != CAL
1888 && opP->reg != VAL
1889 && opP->reg != SCC))
1890 losing++;
1891 break;
1892
1893 case 'V':
1894 if (opP->mode != CONTROL
1895 || opP->reg != VAL)
1896 losing++;
1897 break;
1898
1899 case 'W':
1900 if (opP->mode != CONTROL
1901 || (opP->reg != DRP
1902 && opP->reg != SRP
1903 && opP->reg != CRP))
1904 losing++;
1905 break;
1906
1907 case 'w':
1908 switch (opP->mode)
1909 {
1910 case IMMED:
1911 case ABSL:
1912 case AREG:
1913 case DREG:
1914 case FPREG:
1915 case CONTROL:
1916 case POST:
1917 case PRE:
1918 case REGLST:
1919 losing++;
1920 break;
1921 default:
1922 break;
1923 }
1924 break;
1925
1926 case 'X':
1927 if (opP->mode != CONTROL
1928 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1929 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1930 losing++;
1931 break;
1932
1933 case 'Y':
1934 if (opP->mode != CONTROL || opP->reg != PSR)
1935 losing++;
1936 break;
1937
1938 case 'Z':
1939 if (opP->mode != CONTROL || opP->reg != PCSR)
1940 losing++;
1941 break;
1942 #endif
1943 case 'c':
1944 if (opP->mode != CONTROL
1945 || (opP->reg != NC
1946 && opP->reg != IC
1947 && opP->reg != DC
1948 && opP->reg != BC))
1949 losing++;
1950 break;
1951
1952 case '_':
1953 if (opP->mode != ABSL)
1954 ++losing;
1955 break;
1956
1957 case 'u':
1958 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1959 losing++;
1960 /* FIXME: kludge instead of fixing parser:
1961 upper/lower registers are *not* CONTROL
1962 registers, but ordinary ones. */
1963 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1964 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1965 opP->mode = DREG;
1966 else
1967 opP->mode = AREG;
1968 break;
1969
1970 case 'y':
1971 if (!(opP->mode == AINDR
1972 || (opP->mode == DISP
1973 && !(opP->reg == PC || opP->reg == ZPC))))
1974 losing++;
1975 break;
1976
1977 case 'z':
1978 if (!(opP->mode == AINDR || opP->mode == DISP))
1979 losing++;
1980 break;
1981
1982 default:
1983 abort ();
1984 }
1985
1986 if (losing)
1987 break;
1988 }
1989
1990 /* Since we have found the correct instruction, copy
1991 in the modifications that we may have made. */
1992 if (!losing)
1993 for (i = 0; i < opsfound; i++)
1994 the_ins.operands[i] = operands_backup[i];
1995 }
1996
1997 if (!losing)
1998 break;
1999
2000 opcode = opcode->m_next;
2001
2002 if (!opcode)
2003 {
2004 if (ok_arch
2005 && !(ok_arch & current_architecture))
2006 {
2007 const struct m68k_cpu *cpu;
2008 int any = 0;
2009 size_t space = 400;
2010 char *buf = xmalloc (space + 1);
2011 size_t len;
2012 int paren = 1;
2013
2014 the_ins.error = buf;
2015 /* Make sure there's a NUL at the end of the buffer -- strncpy
2016 won't write one when it runs out of buffer */
2017 buf[space] = 0;
2018 #define APPEND(STRING) \
2019 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2020
2021 APPEND (_("invalid instruction for this architecture; needs "));
2022 switch (ok_arch)
2023 {
2024 case mcfisa_a:
2025 APPEND (_("ColdFire ISA_A"));
2026 break;
2027 case mcfhwdiv:
2028 APPEND (_("ColdFire hardware divide"));
2029 break;
2030 case mcfisa_aa:
2031 APPEND (_("ColdFire ISA_A+"));
2032 break;
2033 case mcfisa_b:
2034 APPEND (_("ColdFire ISA_B"));
2035 break;
2036 case cfloat:
2037 APPEND (_("ColdFire fpu"));
2038 break;
2039 case mfloat:
2040 APPEND (_("M68K fpu"));
2041 break;
2042 case mmmu:
2043 APPEND (_("M68K mmu"));
2044 break;
2045 case m68020up:
2046 APPEND (_("68020 or higher"));
2047 break;
2048 case m68000up:
2049 APPEND (_("68000 or higher"));
2050 break;
2051 case m68010up:
2052 APPEND (_("68010 or higher"));
2053 break;
2054 default:
2055 paren = 0;
2056 }
2057 if (paren)
2058 APPEND (" (");
2059
2060 for (cpu = m68k_cpus; cpu->name; cpu++)
2061 if (!cpu->alias && (cpu->arch & ok_arch))
2062 {
2063 const struct m68k_cpu *alias;
2064
2065 if (any)
2066 APPEND (", ");
2067 any = 0;
2068 APPEND (cpu->name);
2069 APPEND (" [");
2070 if (cpu != m68k_cpus)
2071 for (alias = cpu - 1; alias->alias; alias--)
2072 {
2073 if (any)
2074 APPEND (", ");
2075 APPEND (alias->name);
2076 any = 1;
2077 }
2078 for (alias = cpu + 1; alias->alias; alias++)
2079 {
2080 if (any)
2081 APPEND (", ");
2082 APPEND (alias->name);
2083 any = 1;
2084 }
2085
2086 APPEND ("]");
2087 any = 1;
2088 }
2089 if (paren)
2090 APPEND (")");
2091 #undef APPEND
2092 if (!space)
2093 {
2094 /* we ran out of space, so replace the end of the list
2095 with ellipsis. */
2096 buf -= 4;
2097 while (*buf != ' ')
2098 buf--;
2099 strcpy (buf, " ...");
2100 }
2101 }
2102 else
2103 the_ins.error = _("operands mismatch");
2104 return;
2105 }
2106
2107 losing = 0;
2108 }
2109
2110 /* Now assemble it. */
2111 the_ins.args = opcode->m_operands;
2112 the_ins.numargs = opcode->m_opnum;
2113 the_ins.numo = opcode->m_codenum;
2114 the_ins.opcode[0] = getone (opcode);
2115 the_ins.opcode[1] = gettwo (opcode);
2116
2117 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2118 {
2119 /* This switch is a doozy.
2120 Watch the first step; its a big one! */
2121 switch (s[0])
2122 {
2123
2124 case '*':
2125 case '~':
2126 case '%':
2127 case ';':
2128 case '@':
2129 case '!':
2130 case '&':
2131 case '$':
2132 case '?':
2133 case '/':
2134 case '<':
2135 case '>':
2136 case 'b':
2137 case 'm':
2138 case 'n':
2139 case 'o':
2140 case 'p':
2141 case 'q':
2142 case 'v':
2143 case 'w':
2144 case 'y':
2145 case 'z':
2146 case '4':
2147 #ifndef NO_68851
2148 case '|':
2149 #endif
2150 switch (opP->mode)
2151 {
2152 case IMMED:
2153 tmpreg = 0x3c; /* 7.4 */
2154 if (strchr ("bwl", s[1]))
2155 nextword = get_num (&opP->disp, 90);
2156 else
2157 nextword = get_num (&opP->disp, 0);
2158 if (isvar (&opP->disp))
2159 add_fix (s[1], &opP->disp, 0, 0);
2160 switch (s[1])
2161 {
2162 case 'b':
2163 if (!isbyte (nextword))
2164 opP->error = _("operand out of range");
2165 addword (nextword);
2166 baseo = 0;
2167 break;
2168 case 'w':
2169 if (!isword (nextword))
2170 opP->error = _("operand out of range");
2171 addword (nextword);
2172 baseo = 0;
2173 break;
2174 case 'W':
2175 if (!issword (nextword))
2176 opP->error = _("operand out of range");
2177 addword (nextword);
2178 baseo = 0;
2179 break;
2180 case 'l':
2181 addword (nextword >> 16);
2182 addword (nextword);
2183 baseo = 0;
2184 break;
2185
2186 case 'f':
2187 baseo = 2;
2188 outro = 8;
2189 break;
2190 case 'F':
2191 baseo = 4;
2192 outro = 11;
2193 break;
2194 case 'x':
2195 baseo = 6;
2196 outro = 15;
2197 break;
2198 case 'p':
2199 baseo = 6;
2200 outro = -1;
2201 break;
2202 default:
2203 abort ();
2204 }
2205 if (!baseo)
2206 break;
2207
2208 /* We gotta put out some float. */
2209 if (op (&opP->disp) != O_big)
2210 {
2211 valueT val;
2212 int gencnt;
2213
2214 /* Can other cases happen here? */
2215 if (op (&opP->disp) != O_constant)
2216 abort ();
2217
2218 val = (valueT) offs (&opP->disp);
2219 gencnt = 0;
2220 do
2221 {
2222 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2223 val >>= LITTLENUM_NUMBER_OF_BITS;
2224 ++gencnt;
2225 }
2226 while (val != 0);
2227 offs (&opP->disp) = gencnt;
2228 }
2229 if (offs (&opP->disp) > 0)
2230 {
2231 if (offs (&opP->disp) > baseo)
2232 {
2233 as_warn (_("Bignum too big for %c format; truncated"),
2234 s[1]);
2235 offs (&opP->disp) = baseo;
2236 }
2237 baseo -= offs (&opP->disp);
2238 while (baseo--)
2239 addword (0);
2240 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2241 offs (&opP->disp)--;
2242 --wordp)
2243 addword (*wordp);
2244 break;
2245 }
2246 gen_to_words (words, baseo, (long) outro);
2247 for (wordp = words; baseo--; wordp++)
2248 addword (*wordp);
2249 break;
2250 case DREG:
2251 tmpreg = opP->reg - DATA; /* 0.dreg */
2252 break;
2253 case AREG:
2254 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2255 break;
2256 case AINDR:
2257 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2258 break;
2259 case ADEC:
2260 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2261 break;
2262 case AINC:
2263 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2264 break;
2265 case DISP:
2266
2267 nextword = get_num (&opP->disp, 90);
2268
2269 /* Convert mode 5 addressing with a zero offset into
2270 mode 2 addressing to reduce the instruction size by a
2271 word. */
2272 if (! isvar (&opP->disp)
2273 && (nextword == 0)
2274 && (opP->disp.size == SIZE_UNSPEC)
2275 && (opP->reg >= ADDR0)
2276 && (opP->reg <= ADDR7))
2277 {
2278 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2279 break;
2280 }
2281
2282 if (opP->reg == PC
2283 && ! isvar (&opP->disp)
2284 && m68k_abspcadd)
2285 {
2286 opP->disp.exp.X_op = O_symbol;
2287 opP->disp.exp.X_add_symbol =
2288 section_symbol (absolute_section);
2289 }
2290
2291 /* Force into index mode. Hope this works. */
2292
2293 /* We do the first bit for 32-bit displacements, and the
2294 second bit for 16 bit ones. It is possible that we
2295 should make the default be WORD instead of LONG, but
2296 I think that'd break GCC, so we put up with a little
2297 inefficiency for the sake of working output. */
2298
2299 if (!issword (nextword)
2300 || (isvar (&opP->disp)
2301 && ((opP->disp.size == SIZE_UNSPEC
2302 && flag_short_refs == 0
2303 && cpu_of_arch (current_architecture) >= m68020
2304 && ! arch_coldfire_p (current_architecture))
2305 || opP->disp.size == SIZE_LONG)))
2306 {
2307 if (cpu_of_arch (current_architecture) < m68020
2308 || arch_coldfire_p (current_architecture))
2309 opP->error =
2310 _("displacement too large for this architecture; needs 68020 or higher");
2311 if (opP->reg == PC)
2312 tmpreg = 0x3B; /* 7.3 */
2313 else
2314 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2315 if (isvar (&opP->disp))
2316 {
2317 if (opP->reg == PC)
2318 {
2319 if (opP->disp.size == SIZE_LONG
2320 #ifdef OBJ_ELF
2321 /* If the displacement needs pic
2322 relocation it cannot be relaxed. */
2323 || opP->disp.pic_reloc != pic_none
2324 #endif
2325 )
2326 {
2327 addword (0x0170);
2328 add_fix ('l', &opP->disp, 1, 2);
2329 }
2330 else
2331 {
2332 add_frag (adds (&opP->disp),
2333 SEXT (offs (&opP->disp)),
2334 TAB (PCREL1632, SZ_UNDEF));
2335 break;
2336 }
2337 }
2338 else
2339 {
2340 addword (0x0170);
2341 add_fix ('l', &opP->disp, 0, 0);
2342 }
2343 }
2344 else
2345 addword (0x0170);
2346 addword (nextword >> 16);
2347 }
2348 else
2349 {
2350 if (opP->reg == PC)
2351 tmpreg = 0x3A; /* 7.2 */
2352 else
2353 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2354
2355 if (isvar (&opP->disp))
2356 {
2357 if (opP->reg == PC)
2358 {
2359 add_fix ('w', &opP->disp, 1, 0);
2360 }
2361 else
2362 add_fix ('w', &opP->disp, 0, 0);
2363 }
2364 }
2365 addword (nextword);
2366 break;
2367
2368 case POST:
2369 case PRE:
2370 case BASE:
2371 nextword = 0;
2372 baseo = get_num (&opP->disp, 90);
2373 if (opP->mode == POST || opP->mode == PRE)
2374 outro = get_num (&opP->odisp, 90);
2375 /* Figure out the `addressing mode'.
2376 Also turn on the BASE_DISABLE bit, if needed. */
2377 if (opP->reg == PC || opP->reg == ZPC)
2378 {
2379 tmpreg = 0x3b; /* 7.3 */
2380 if (opP->reg == ZPC)
2381 nextword |= 0x80;
2382 }
2383 else if (opP->reg == 0)
2384 {
2385 nextword |= 0x80;
2386 tmpreg = 0x30; /* 6.garbage */
2387 }
2388 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2389 {
2390 nextword |= 0x80;
2391 tmpreg = 0x30 + opP->reg - ZADDR0;
2392 }
2393 else
2394 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2395
2396 siz1 = opP->disp.size;
2397 if (opP->mode == POST || opP->mode == PRE)
2398 siz2 = opP->odisp.size;
2399 else
2400 siz2 = SIZE_UNSPEC;
2401
2402 /* Index register stuff. */
2403 if (opP->index.reg != 0
2404 && opP->index.reg >= DATA
2405 && opP->index.reg <= ADDR7)
2406 {
2407 nextword |= (opP->index.reg - DATA) << 12;
2408
2409 if (opP->index.size == SIZE_LONG
2410 || (opP->index.size == SIZE_UNSPEC
2411 && m68k_index_width_default == SIZE_LONG))
2412 nextword |= 0x800;
2413
2414 if ((opP->index.scale != 1
2415 && cpu_of_arch (current_architecture) < m68020)
2416 || (opP->index.scale == 8
2417 && (arch_coldfire_p (current_architecture)
2418 && !arch_coldfire_fpu (current_architecture))))
2419 {
2420 opP->error =
2421 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2422 }
2423
2424 if (arch_coldfire_p (current_architecture)
2425 && opP->index.size == SIZE_WORD)
2426 opP->error = _("invalid index size for coldfire");
2427
2428 switch (opP->index.scale)
2429 {
2430 case 1:
2431 break;
2432 case 2:
2433 nextword |= 0x200;
2434 break;
2435 case 4:
2436 nextword |= 0x400;
2437 break;
2438 case 8:
2439 nextword |= 0x600;
2440 break;
2441 default:
2442 abort ();
2443 }
2444 /* IF its simple,
2445 GET US OUT OF HERE! */
2446
2447 /* Must be INDEX, with an index register. Address
2448 register cannot be ZERO-PC, and either :b was
2449 forced, or we know it will fit. For a 68000 or
2450 68010, force this mode anyways, because the
2451 larger modes aren't supported. */
2452 if (opP->mode == BASE
2453 && ((opP->reg >= ADDR0
2454 && opP->reg <= ADDR7)
2455 || opP->reg == PC))
2456 {
2457 if (siz1 == SIZE_BYTE
2458 || cpu_of_arch (current_architecture) < m68020
2459 || arch_coldfire_p (current_architecture)
2460 || (siz1 == SIZE_UNSPEC
2461 && ! isvar (&opP->disp)
2462 && issbyte (baseo)))
2463 {
2464 nextword += baseo & 0xff;
2465 addword (nextword);
2466 if (isvar (&opP->disp))
2467 {
2468 /* Do a byte relocation. If it doesn't
2469 fit (possible on m68000) let the
2470 fixup processing complain later. */
2471 if (opP->reg == PC)
2472 add_fix ('B', &opP->disp, 1, 1);
2473 else
2474 add_fix ('B', &opP->disp, 0, 0);
2475 }
2476 else if (siz1 != SIZE_BYTE)
2477 {
2478 if (siz1 != SIZE_UNSPEC)
2479 as_warn (_("Forcing byte displacement"));
2480 if (! issbyte (baseo))
2481 opP->error = _("byte displacement out of range");
2482 }
2483
2484 break;
2485 }
2486 else if (siz1 == SIZE_UNSPEC
2487 && opP->reg == PC
2488 && isvar (&opP->disp)
2489 && subs (&opP->disp) == NULL
2490 #ifdef OBJ_ELF
2491 /* If the displacement needs pic
2492 relocation it cannot be relaxed. */
2493 && opP->disp.pic_reloc == pic_none
2494 #endif
2495 )
2496 {
2497 /* The code in md_convert_frag_1 needs to be
2498 able to adjust nextword. Call frag_grow
2499 to ensure that we have enough space in
2500 the frag obstack to make all the bytes
2501 contiguous. */
2502 frag_grow (14);
2503 nextword += baseo & 0xff;
2504 addword (nextword);
2505 add_frag (adds (&opP->disp),
2506 SEXT (offs (&opP->disp)),
2507 TAB (PCINDEX, SZ_UNDEF));
2508
2509 break;
2510 }
2511 }
2512 }
2513 else
2514 {
2515 nextword |= 0x40; /* No index reg. */
2516 if (opP->index.reg >= ZDATA0
2517 && opP->index.reg <= ZDATA7)
2518 nextword |= (opP->index.reg - ZDATA0) << 12;
2519 else if (opP->index.reg >= ZADDR0
2520 || opP->index.reg <= ZADDR7)
2521 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2522 }
2523
2524 /* It isn't simple. */
2525
2526 if (cpu_of_arch (current_architecture) < m68020
2527 || arch_coldfire_p (current_architecture))
2528 opP->error =
2529 _("invalid operand mode for this architecture; needs 68020 or higher");
2530
2531 nextword |= 0x100;
2532 /* If the guy specified a width, we assume that it is
2533 wide enough. Maybe it isn't. If so, we lose. */
2534 switch (siz1)
2535 {
2536 case SIZE_UNSPEC:
2537 if (isvar (&opP->disp)
2538 ? m68k_rel32
2539 : ! issword (baseo))
2540 {
2541 siz1 = SIZE_LONG;
2542 nextword |= 0x30;
2543 }
2544 else if (! isvar (&opP->disp) && baseo == 0)
2545 nextword |= 0x10;
2546 else
2547 {
2548 nextword |= 0x20;
2549 siz1 = SIZE_WORD;
2550 }
2551 break;
2552 case SIZE_BYTE:
2553 as_warn (_(":b not permitted; defaulting to :w"));
2554 /* Fall through. */
2555 case SIZE_WORD:
2556 nextword |= 0x20;
2557 break;
2558 case SIZE_LONG:
2559 nextword |= 0x30;
2560 break;
2561 }
2562
2563 /* Figure out inner displacement stuff. */
2564 if (opP->mode == POST || opP->mode == PRE)
2565 {
2566 if (cpu_of_arch (current_architecture) & cpu32)
2567 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2568 switch (siz2)
2569 {
2570 case SIZE_UNSPEC:
2571 if (isvar (&opP->odisp)
2572 ? m68k_rel32
2573 : ! issword (outro))
2574 {
2575 siz2 = SIZE_LONG;
2576 nextword |= 0x3;
2577 }
2578 else if (! isvar (&opP->odisp) && outro == 0)
2579 nextword |= 0x1;
2580 else
2581 {
2582 nextword |= 0x2;
2583 siz2 = SIZE_WORD;
2584 }
2585 break;
2586 case 1:
2587 as_warn (_(":b not permitted; defaulting to :w"));
2588 /* Fall through. */
2589 case 2:
2590 nextword |= 0x2;
2591 break;
2592 case 3:
2593 nextword |= 0x3;
2594 break;
2595 }
2596 if (opP->mode == POST
2597 && (nextword & 0x40) == 0)
2598 nextword |= 0x04;
2599 }
2600 addword (nextword);
2601
2602 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2603 {
2604 if (opP->reg == PC || opP->reg == ZPC)
2605 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2606 else
2607 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2608 }
2609 if (siz1 == SIZE_LONG)
2610 addword (baseo >> 16);
2611 if (siz1 != SIZE_UNSPEC)
2612 addword (baseo);
2613
2614 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2615 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2616 if (siz2 == SIZE_LONG)
2617 addword (outro >> 16);
2618 if (siz2 != SIZE_UNSPEC)
2619 addword (outro);
2620
2621 break;
2622
2623 case ABSL:
2624 nextword = get_num (&opP->disp, 90);
2625 switch (opP->disp.size)
2626 {
2627 default:
2628 abort ();
2629 case SIZE_UNSPEC:
2630 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2631 {
2632 tmpreg = 0x38; /* 7.0 */
2633 addword (nextword);
2634 break;
2635 }
2636 if (isvar (&opP->disp)
2637 && !subs (&opP->disp)
2638 && adds (&opP->disp)
2639 #ifdef OBJ_ELF
2640 /* If the displacement needs pic relocation it
2641 cannot be relaxed. */
2642 && opP->disp.pic_reloc == pic_none
2643 #endif
2644 && !flag_long_jumps
2645 && !strchr ("~%&$?", s[0]))
2646 {
2647 tmpreg = 0x3A; /* 7.2 */
2648 add_frag (adds (&opP->disp),
2649 SEXT (offs (&opP->disp)),
2650 TAB (ABSTOPCREL, SZ_UNDEF));
2651 break;
2652 }
2653 /* Fall through into long. */
2654 case SIZE_LONG:
2655 if (isvar (&opP->disp))
2656 add_fix ('l', &opP->disp, 0, 0);
2657
2658 tmpreg = 0x39;/* 7.1 mode */
2659 addword (nextword >> 16);
2660 addword (nextword);
2661 break;
2662
2663 case SIZE_BYTE:
2664 as_bad (_("unsupported byte value; use a different suffix"));
2665 /* Fall through. */
2666
2667 case SIZE_WORD:
2668 if (isvar (&opP->disp))
2669 add_fix ('w', &opP->disp, 0, 0);
2670
2671 tmpreg = 0x38;/* 7.0 mode */
2672 addword (nextword);
2673 break;
2674 }
2675 break;
2676 case CONTROL:
2677 case FPREG:
2678 default:
2679 as_bad (_("unknown/incorrect operand"));
2680 /* abort (); */
2681 }
2682
2683 /* If s[0] is '4', then this is for the mac instructions
2684 that can have a trailing_ampersand set. If so, set 0x100
2685 bit on tmpreg so install_gen_operand can check for it and
2686 set the appropriate bit (word2, bit 5). */
2687 if (s[0] == '4')
2688 {
2689 if (opP->trailing_ampersand)
2690 tmpreg |= 0x100;
2691 }
2692 install_gen_operand (s[1], tmpreg);
2693 break;
2694
2695 case '#':
2696 case '^':
2697 switch (s[1])
2698 { /* JF: I hate floating point! */
2699 case 'j':
2700 tmpreg = 70;
2701 break;
2702 case '8':
2703 tmpreg = 20;
2704 break;
2705 case 'C':
2706 tmpreg = 50;
2707 break;
2708 case '3':
2709 default:
2710 tmpreg = 90;
2711 break;
2712 }
2713 tmpreg = get_num (&opP->disp, tmpreg);
2714 if (isvar (&opP->disp))
2715 add_fix (s[1], &opP->disp, 0, 0);
2716 switch (s[1])
2717 {
2718 case 'b': /* Danger: These do no check for
2719 certain types of overflow.
2720 user beware! */
2721 if (!isbyte (tmpreg))
2722 opP->error = _("out of range");
2723 insop (tmpreg, opcode);
2724 if (isvar (&opP->disp))
2725 the_ins.reloc[the_ins.nrel - 1].n =
2726 (opcode->m_codenum) * 2 + 1;
2727 break;
2728 case 'B':
2729 if (!issbyte (tmpreg))
2730 opP->error = _("out of range");
2731 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2732 if (isvar (&opP->disp))
2733 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2734 break;
2735 case 'w':
2736 if (!isword (tmpreg))
2737 opP->error = _("out of range");
2738 insop (tmpreg, opcode);
2739 if (isvar (&opP->disp))
2740 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2741 break;
2742 case 'W':
2743 if (!issword (tmpreg))
2744 opP->error = _("out of range");
2745 insop (tmpreg, opcode);
2746 if (isvar (&opP->disp))
2747 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2748 break;
2749 case 'l':
2750 /* Because of the way insop works, we put these two out
2751 backwards. */
2752 insop (tmpreg, opcode);
2753 insop (tmpreg >> 16, opcode);
2754 if (isvar (&opP->disp))
2755 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2756 break;
2757 case '3':
2758 tmpreg &= 0xFF;
2759 case '8':
2760 case 'C':
2761 case 'j':
2762 install_operand (s[1], tmpreg);
2763 break;
2764 default:
2765 abort ();
2766 }
2767 break;
2768
2769 case '+':
2770 case '-':
2771 case 'A':
2772 case 'a':
2773 install_operand (s[1], opP->reg - ADDR);
2774 break;
2775
2776 case 'B':
2777 tmpreg = get_num (&opP->disp, 90);
2778 switch (s[1])
2779 {
2780 case 'B':
2781 add_fix ('B', &opP->disp, 1, -1);
2782 break;
2783 case 'W':
2784 add_fix ('w', &opP->disp, 1, 0);
2785 addword (0);
2786 break;
2787 case 'L':
2788 long_branch:
2789 if (! HAVE_LONG_BRANCH (current_architecture))
2790 as_warn (_("Can't use long branches on 68000/68010/5200"));
2791 the_ins.opcode[0] |= 0xff;
2792 add_fix ('l', &opP->disp, 1, 0);
2793 addword (0);
2794 addword (0);
2795 break;
2796 case 'g':
2797 if (subs (&opP->disp)) /* We can't relax it. */
2798 goto long_branch;
2799
2800 #ifdef OBJ_ELF
2801 /* If the displacement needs pic relocation it cannot be
2802 relaxed. */
2803 if (opP->disp.pic_reloc != pic_none)
2804 goto long_branch;
2805 #endif
2806 /* This could either be a symbol, or an absolute
2807 address. If it's an absolute address, turn it into
2808 an absolute jump right here and keep it out of the
2809 relaxer. */
2810 if (adds (&opP->disp) == 0)
2811 {
2812 if (the_ins.opcode[0] == 0x6000) /* jbra */
2813 the_ins.opcode[0] = 0x4EF9;
2814 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2815 the_ins.opcode[0] = 0x4EB9;
2816 else /* jCC */
2817 {
2818 the_ins.opcode[0] ^= 0x0100;
2819 the_ins.opcode[0] |= 0x0006;
2820 addword (0x4EF9);
2821 }
2822 add_fix ('l', &opP->disp, 0, 0);
2823 addword (0);
2824 addword (0);
2825 break;
2826 }
2827
2828 /* Now we know it's going into the relaxer. Now figure
2829 out which mode. We try in this order of preference:
2830 long branch, absolute jump, byte/word branches only. */
2831 if (HAVE_LONG_BRANCH (current_architecture))
2832 add_frag (adds (&opP->disp),
2833 SEXT (offs (&opP->disp)),
2834 TAB (BRANCHBWL, SZ_UNDEF));
2835 else if (! flag_keep_pcrel)
2836 {
2837 if ((the_ins.opcode[0] == 0x6000)
2838 || (the_ins.opcode[0] == 0x6100))
2839 add_frag (adds (&opP->disp),
2840 SEXT (offs (&opP->disp)),
2841 TAB (BRABSJUNC, SZ_UNDEF));
2842 else
2843 add_frag (adds (&opP->disp),
2844 SEXT (offs (&opP->disp)),
2845 TAB (BRABSJCOND, SZ_UNDEF));
2846 }
2847 else
2848 add_frag (adds (&opP->disp),
2849 SEXT (offs (&opP->disp)),
2850 TAB (BRANCHBW, SZ_UNDEF));
2851 break;
2852 case 'w':
2853 if (isvar (&opP->disp))
2854 {
2855 /* Check for DBcc instructions. We can relax them,
2856 but only if we have long branches and/or absolute
2857 jumps. */
2858 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2859 && (HAVE_LONG_BRANCH (current_architecture)
2860 || (! flag_keep_pcrel)))
2861 {
2862 if (HAVE_LONG_BRANCH (current_architecture))
2863 add_frag (adds (&opP->disp),
2864 SEXT (offs (&opP->disp)),
2865 TAB (DBCCLBR, SZ_UNDEF));
2866 else
2867 add_frag (adds (&opP->disp),
2868 SEXT (offs (&opP->disp)),
2869 TAB (DBCCABSJ, SZ_UNDEF));
2870 break;
2871 }
2872 add_fix ('w', &opP->disp, 1, 0);
2873 }
2874 addword (0);
2875 break;
2876 case 'C': /* Fixed size LONG coproc branches. */
2877 add_fix ('l', &opP->disp, 1, 0);
2878 addword (0);
2879 addword (0);
2880 break;
2881 case 'c': /* Var size Coprocesssor branches. */
2882 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2883 {
2884 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2885 add_fix ('l', &opP->disp, 1, 0);
2886 addword (0);
2887 addword (0);
2888 }
2889 else
2890 add_frag (adds (&opP->disp),
2891 SEXT (offs (&opP->disp)),
2892 TAB (FBRANCH, SZ_UNDEF));
2893 break;
2894 default:
2895 abort ();
2896 }
2897 break;
2898
2899 case 'C': /* Ignore it. */
2900 break;
2901
2902 case 'd': /* JF this is a kludge. */
2903 install_operand ('s', opP->reg - ADDR);
2904 tmpreg = get_num (&opP->disp, 90);
2905 if (!issword (tmpreg))
2906 {
2907 as_warn (_("Expression out of range, using 0"));
2908 tmpreg = 0;
2909 }
2910 addword (tmpreg);
2911 break;
2912
2913 case 'D':
2914 install_operand (s[1], opP->reg - DATA);
2915 break;
2916
2917 case 'e': /* EMAC ACCx, reg/reg. */
2918 install_operand (s[1], opP->reg - ACC);
2919 break;
2920
2921 case 'E': /* Ignore it. */
2922 break;
2923
2924 case 'F':
2925 install_operand (s[1], opP->reg - FP0);
2926 break;
2927
2928 case 'g': /* EMAC ACCEXTx. */
2929 install_operand (s[1], opP->reg - ACCEXT01);
2930 break;
2931
2932 case 'G': /* Ignore it. */
2933 case 'H':
2934 break;
2935
2936 case 'I':
2937 tmpreg = opP->reg - COP0;
2938 install_operand (s[1], tmpreg);
2939 break;
2940
2941 case 'i': /* MAC/EMAC scale factor. */
2942 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2943 break;
2944
2945 case 'J': /* JF foo. */
2946 switch (opP->reg)
2947 {
2948 case SFC:
2949 tmpreg = 0x000;
2950 break;
2951 case DFC:
2952 tmpreg = 0x001;
2953 break;
2954 case CACR:
2955 tmpreg = 0x002;
2956 break;
2957 case TC:
2958 tmpreg = 0x003;
2959 break;
2960 case ACR0:
2961 case ITT0:
2962 tmpreg = 0x004;
2963 break;
2964 case ACR1:
2965 case ITT1:
2966 tmpreg = 0x005;
2967 break;
2968 case ACR2:
2969 case DTT0:
2970 tmpreg = 0x006;
2971 break;
2972 case ACR3:
2973 case DTT1:
2974 tmpreg = 0x007;
2975 break;
2976 case BUSCR:
2977 tmpreg = 0x008;
2978 break;
2979
2980 case USP:
2981 tmpreg = 0x800;
2982 break;
2983 case VBR:
2984 tmpreg = 0x801;
2985 break;
2986 case CAAR:
2987 tmpreg = 0x802;
2988 break;
2989 case MSP:
2990 tmpreg = 0x803;
2991 break;
2992 case ISP:
2993 tmpreg = 0x804;
2994 break;
2995 case MMUSR:
2996 tmpreg = 0x805;
2997 break;
2998 case URP:
2999 tmpreg = 0x806;
3000 break;
3001 case SRP:
3002 tmpreg = 0x807;
3003 break;
3004 case PCR:
3005 tmpreg = 0x808;
3006 break;
3007 case ROMBAR:
3008 tmpreg = 0xC00;
3009 break;
3010 case ROMBAR1:
3011 tmpreg = 0xC01;
3012 break;
3013 case FLASHBAR:
3014 case RAMBAR0:
3015 tmpreg = 0xC04;
3016 break;
3017 case RAMBAR:
3018 case RAMBAR1:
3019 tmpreg = 0xC05;
3020 break;
3021 case MPCR:
3022 tmpreg = 0xC0C;
3023 break;
3024 case EDRAMBAR:
3025 tmpreg = 0xC0D;
3026 break;
3027 case MBAR0:
3028 case MBAR2:
3029 case SECMBAR:
3030 tmpreg = 0xC0E;
3031 break;
3032 case MBAR1:
3033 case MBAR:
3034 tmpreg = 0xC0F;
3035 break;
3036 case PCR1U0:
3037 tmpreg = 0xD02;
3038 break;
3039 case PCR1L0:
3040 tmpreg = 0xD03;
3041 break;
3042 case PCR2U0:
3043 tmpreg = 0xD04;
3044 break;
3045 case PCR2L0:
3046 tmpreg = 0xD05;
3047 break;
3048 case PCR3U0:
3049 tmpreg = 0xD06;
3050 break;
3051 case PCR3L0:
3052 tmpreg = 0xD07;
3053 break;
3054 case PCR1L1:
3055 tmpreg = 0xD0A;
3056 break;
3057 case PCR1U1:
3058 tmpreg = 0xD0B;
3059 break;
3060 case PCR2L1:
3061 tmpreg = 0xD0C;
3062 break;
3063 case PCR2U1:
3064 tmpreg = 0xD0D;
3065 break;
3066 case PCR3L1:
3067 tmpreg = 0xD0E;
3068 break;
3069 case PCR3U1:
3070 tmpreg = 0xD0F;
3071 break;
3072 default:
3073 abort ();
3074 }
3075 install_operand (s[1], tmpreg);
3076 break;
3077
3078 case 'k':
3079 tmpreg = get_num (&opP->disp, 55);
3080 install_operand (s[1], tmpreg & 0x7f);
3081 break;
3082
3083 case 'l':
3084 tmpreg = opP->mask;
3085 if (s[1] == 'w')
3086 {
3087 if (tmpreg & 0x7FF0000)
3088 as_bad (_("Floating point register in register list"));
3089 insop (reverse_16_bits (tmpreg), opcode);
3090 }
3091 else
3092 {
3093 if (tmpreg & 0x700FFFF)
3094 as_bad (_("Wrong register in floating-point reglist"));
3095 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3096 }
3097 break;
3098
3099 case 'L':
3100 tmpreg = opP->mask;
3101 if (s[1] == 'w')
3102 {
3103 if (tmpreg & 0x7FF0000)
3104 as_bad (_("Floating point register in register list"));
3105 insop (tmpreg, opcode);
3106 }
3107 else if (s[1] == '8')
3108 {
3109 if (tmpreg & 0x0FFFFFF)
3110 as_bad (_("incorrect register in reglist"));
3111 install_operand (s[1], tmpreg >> 24);
3112 }
3113 else
3114 {
3115 if (tmpreg & 0x700FFFF)
3116 as_bad (_("wrong register in floating-point reglist"));
3117 else
3118 install_operand (s[1], tmpreg >> 16);
3119 }
3120 break;
3121
3122 case 'M':
3123 install_operand (s[1], get_num (&opP->disp, 60));
3124 break;
3125
3126 case 'O':
3127 tmpreg = ((opP->mode == DREG)
3128 ? 0x20 + (int) (opP->reg - DATA)
3129 : (get_num (&opP->disp, 40) & 0x1F));
3130 install_operand (s[1], tmpreg);
3131 break;
3132
3133 case 'Q':
3134 tmpreg = get_num (&opP->disp, 10);
3135 if (tmpreg == 8)
3136 tmpreg = 0;
3137 install_operand (s[1], tmpreg);
3138 break;
3139
3140 case 'R':
3141 /* This depends on the fact that ADDR registers are eight
3142 more than their corresponding DATA regs, so the result
3143 will have the ADDR_REG bit set. */
3144 install_operand (s[1], opP->reg - DATA);
3145 break;
3146
3147 case 'r':
3148 if (opP->mode == AINDR)
3149 install_operand (s[1], opP->reg - DATA);
3150 else
3151 install_operand (s[1], opP->index.reg - DATA);
3152 break;
3153
3154 case 's':
3155 if (opP->reg == FPI)
3156 tmpreg = 0x1;
3157 else if (opP->reg == FPS)
3158 tmpreg = 0x2;
3159 else if (opP->reg == FPC)
3160 tmpreg = 0x4;
3161 else
3162 abort ();
3163 install_operand (s[1], tmpreg);
3164 break;
3165
3166 case 'S': /* Ignore it. */
3167 break;
3168
3169 case 'T':
3170 install_operand (s[1], get_num (&opP->disp, 30));
3171 break;
3172
3173 case 'U': /* Ignore it. */
3174 break;
3175
3176 case 'c':
3177 switch (opP->reg)
3178 {
3179 case NC:
3180 tmpreg = 0;
3181 break;
3182 case DC:
3183 tmpreg = 1;
3184 break;
3185 case IC:
3186 tmpreg = 2;
3187 break;
3188 case BC:
3189 tmpreg = 3;
3190 break;
3191 default:
3192 as_fatal (_("failed sanity check"));
3193 } /* switch on cache token. */
3194 install_operand (s[1], tmpreg);
3195 break;
3196 #ifndef NO_68851
3197 /* JF: These are out of order, I fear. */
3198 case 'f':
3199 switch (opP->reg)
3200 {
3201 case SFC:
3202 tmpreg = 0;
3203 break;
3204 case DFC:
3205 tmpreg = 1;
3206 break;
3207 default:
3208 abort ();
3209 }
3210 install_operand (s[1], tmpreg);
3211 break;
3212
3213 case '0':
3214 case '1':
3215 case '2':
3216 switch (opP->reg)
3217 {
3218 case TC:
3219 tmpreg = 0;
3220 break;
3221 case CAL:
3222 tmpreg = 4;
3223 break;
3224 case VAL:
3225 tmpreg = 5;
3226 break;
3227 case SCC:
3228 tmpreg = 6;
3229 break;
3230 case AC:
3231 tmpreg = 7;
3232 break;
3233 default:
3234 abort ();
3235 }
3236 install_operand (s[1], tmpreg);
3237 break;
3238
3239 case 'V':
3240 if (opP->reg == VAL)
3241 break;
3242 abort ();
3243
3244 case 'W':
3245 switch (opP->reg)
3246 {
3247 case DRP:
3248 tmpreg = 1;
3249 break;
3250 case SRP:
3251 tmpreg = 2;
3252 break;
3253 case CRP:
3254 tmpreg = 3;
3255 break;
3256 default:
3257 abort ();
3258 }
3259 install_operand (s[1], tmpreg);
3260 break;
3261
3262 case 'X':
3263 switch (opP->reg)
3264 {
3265 case BAD:
3266 case BAD + 1:
3267 case BAD + 2:
3268 case BAD + 3:
3269 case BAD + 4:
3270 case BAD + 5:
3271 case BAD + 6:
3272 case BAD + 7:
3273 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3274 break;
3275
3276 case BAC:
3277 case BAC + 1:
3278 case BAC + 2:
3279 case BAC + 3:
3280 case BAC + 4:
3281 case BAC + 5:
3282 case BAC + 6:
3283 case BAC + 7:
3284 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3285 break;
3286
3287 default:
3288 abort ();
3289 }
3290 install_operand (s[1], tmpreg);
3291 break;
3292 case 'Y':
3293 know (opP->reg == PSR);
3294 break;
3295 case 'Z':
3296 know (opP->reg == PCSR);
3297 break;
3298 #endif /* m68851 */
3299 case '3':
3300 switch (opP->reg)
3301 {
3302 case TT0:
3303 tmpreg = 2;
3304 break;
3305 case TT1:
3306 tmpreg = 3;
3307 break;
3308 default:
3309 abort ();
3310 }
3311 install_operand (s[1], tmpreg);
3312 break;
3313 case 't':
3314 tmpreg = get_num (&opP->disp, 20);
3315 install_operand (s[1], tmpreg);
3316 break;
3317 case '_': /* used only for move16 absolute 32-bit address. */
3318 if (isvar (&opP->disp))
3319 add_fix ('l', &opP->disp, 0, 0);
3320 tmpreg = get_num (&opP->disp, 90);
3321 addword (tmpreg >> 16);
3322 addword (tmpreg & 0xFFFF);
3323 break;
3324 case 'u':
3325 install_operand (s[1], opP->reg - DATA0L);
3326 opP->reg -= (DATA0L);
3327 opP->reg &= 0x0F; /* remove upper/lower bit. */
3328 break;
3329 case 'x':
3330 tmpreg = get_num (&opP->disp, 80);
3331 if (tmpreg == -1)
3332 tmpreg = 0;
3333 install_operand (s[1], tmpreg);
3334 break;
3335 default:
3336 abort ();
3337 }
3338 }
3339
3340 /* By the time whe get here (FINALLY) the_ins contains the complete
3341 instruction, ready to be emitted. . . */
3342 }
3343
3344 static int
3345 reverse_16_bits (int in)
3346 {
3347 int out = 0;
3348 int n;
3349
3350 static int mask[16] =
3351 {
3352 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3353 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3354 };
3355 for (n = 0; n < 16; n++)
3356 {
3357 if (in & mask[n])
3358 out |= mask[15 - n];
3359 }
3360 return out;
3361 } /* reverse_16_bits() */
3362
3363 static int
3364 reverse_8_bits (int in)
3365 {
3366 int out = 0;
3367 int n;
3368
3369 static int mask[8] =
3370 {
3371 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3372 };
3373
3374 for (n = 0; n < 8; n++)
3375 {
3376 if (in & mask[n])
3377 out |= mask[7 - n];
3378 }
3379 return out;
3380 } /* reverse_8_bits() */
3381
3382 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3383 (that value is chosen in the frag_var call in md_assemble). TYPE
3384 is the subtype of the frag to be generated; its primary type is
3385 rs_machine_dependent.
3386
3387 The TYPE parameter is also used by md_convert_frag_1 and
3388 md_estimate_size_before_relax. The appropriate type of fixup will
3389 be emitted by md_convert_frag_1.
3390
3391 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3392 static void
3393 install_operand (int mode, int val)
3394 {
3395 switch (mode)
3396 {
3397 case 's':
3398 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3399 break;
3400 case 'd':
3401 the_ins.opcode[0] |= val << 9;
3402 break;
3403 case '1':
3404 the_ins.opcode[1] |= val << 12;
3405 break;
3406 case '2':
3407 the_ins.opcode[1] |= val << 6;
3408 break;
3409 case '3':
3410 the_ins.opcode[1] |= val;
3411 break;
3412 case '4':
3413 the_ins.opcode[2] |= val << 12;
3414 break;
3415 case '5':
3416 the_ins.opcode[2] |= val << 6;
3417 break;
3418 case '6':
3419 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3420 three words long! */
3421 the_ins.numo++;
3422 the_ins.opcode[2] |= val;
3423 break;
3424 case '7':
3425 the_ins.opcode[1] |= val << 7;
3426 break;
3427 case '8':
3428 the_ins.opcode[1] |= val << 10;
3429 break;
3430 #ifndef NO_68851
3431 case '9':
3432 the_ins.opcode[1] |= val << 5;
3433 break;
3434 #endif
3435
3436 case 't':
3437 the_ins.opcode[1] |= (val << 10) | (val << 7);
3438 break;
3439 case 'D':
3440 the_ins.opcode[1] |= (val << 12) | val;
3441 break;
3442 case 'g':
3443 the_ins.opcode[0] |= val = 0xff;
3444 break;
3445 case 'i':
3446 the_ins.opcode[0] |= val << 9;
3447 break;
3448 case 'C':
3449 the_ins.opcode[1] |= val;
3450 break;
3451 case 'j':
3452 the_ins.opcode[1] |= val;
3453 the_ins.numo++; /* What a hack. */
3454 break;
3455 case 'k':
3456 the_ins.opcode[1] |= val << 4;
3457 break;
3458 case 'b':
3459 case 'w':
3460 case 'W':
3461 case 'l':
3462 break;
3463 case 'e':
3464 the_ins.opcode[0] |= (val << 6);
3465 break;
3466 case 'L':
3467 the_ins.opcode[1] = (val >> 16);
3468 the_ins.opcode[2] = val & 0xffff;
3469 break;
3470 case 'm':
3471 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3472 the_ins.opcode[0] |= ((val & 0x7) << 9);
3473 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3474 break;
3475 case 'n': /* MAC/EMAC Rx on !load. */
3476 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3477 the_ins.opcode[0] |= ((val & 0x7) << 9);
3478 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3479 break;
3480 case 'o': /* MAC/EMAC Rx on load. */
3481 the_ins.opcode[1] |= val << 12;
3482 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3483 break;
3484 case 'M': /* MAC/EMAC Ry on !load. */
3485 the_ins.opcode[0] |= (val & 0xF);
3486 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3487 break;
3488 case 'N': /* MAC/EMAC Ry on load. */
3489 the_ins.opcode[1] |= (val & 0xF);
3490 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3491 break;
3492 case 'h':
3493 the_ins.opcode[1] |= ((val != 1) << 10);
3494 break;
3495 case 'F':
3496 the_ins.opcode[0] |= ((val & 0x3) << 9);
3497 break;
3498 case 'f':
3499 the_ins.opcode[0] |= ((val & 0x3) << 0);
3500 break;
3501 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3502 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3503 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3504 break;
3505 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3506 the_ins.opcode[0] |= ((val & 0x1) << 7);
3507 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3508 break;
3509 case 'I':
3510 the_ins.opcode[1] |= ((val & 0x3) << 9);
3511 break;
3512 case ']':
3513 the_ins.opcode[0] |= (val & 0x1) <<10;
3514 break;
3515 case 'c':
3516 default:
3517 as_fatal (_("failed sanity check."));
3518 }
3519 }
3520
3521 static void
3522 install_gen_operand (int mode, int val)
3523 {
3524 switch (mode)
3525 {
3526 case '/': /* Special for mask loads for mac/msac insns with
3527 possible mask; trailing_ampersend set in bit 8. */
3528 the_ins.opcode[0] |= (val & 0x3f);
3529 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3530 break;
3531 case 's':
3532 the_ins.opcode[0] |= val;
3533 break;
3534 case 'd':
3535 /* This is a kludge!!! */
3536 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3537 break;
3538 case 'b':
3539 case 'w':
3540 case 'l':
3541 case 'f':
3542 case 'F':
3543 case 'x':
3544 case 'p':
3545 the_ins.opcode[0] |= val;
3546 break;
3547 /* more stuff goes here. */
3548 default:
3549 as_fatal (_("failed sanity check."));
3550 }
3551 }
3552
3553 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3554 then deal with the bitfield hack. */
3555
3556 static char *
3557 crack_operand (char *str, struct m68k_op *opP)
3558 {
3559 register int parens;
3560 register int c;
3561 register char *beg_str;
3562 int inquote = 0;
3563
3564 if (!str)
3565 {
3566 return str;
3567 }
3568 beg_str = str;
3569 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3570 {
3571 if (! inquote)
3572 {
3573 if (*str == '(')
3574 parens++;
3575 else if (*str == ')')
3576 {
3577 if (!parens)
3578 { /* ERROR. */
3579 opP->error = _("Extra )");
3580 return str;
3581 }
3582 --parens;
3583 }
3584 }
3585 if (flag_mri && *str == '\'')
3586 inquote = ! inquote;
3587 }
3588 if (!*str && parens)
3589 { /* ERROR. */
3590 opP->error = _("Missing )");
3591 return str;
3592 }
3593 c = *str;
3594 *str = '\0';
3595 if (m68k_ip_op (beg_str, opP) != 0)
3596 {
3597 *str = c;
3598 return str;
3599 }
3600 *str = c;
3601 if (c == '}')
3602 c = *++str; /* JF bitfield hack. */
3603 if (c)
3604 {
3605 c = *++str;
3606 if (!c)
3607 as_bad (_("Missing operand"));
3608 }
3609
3610 /* Detect MRI REG symbols and convert them to REGLSTs. */
3611 if (opP->mode == CONTROL && (int)opP->reg < 0)
3612 {
3613 opP->mode = REGLST;
3614 opP->mask = ~(int)opP->reg;
3615 opP->reg = 0;
3616 }
3617
3618 return str;
3619 }
3620
3621 /* This is the guts of the machine-dependent assembler. STR points to a
3622 machine dependent instruction. This function is supposed to emit
3623 the frags/bytes it assembles to.
3624 */
3625
3626 static void
3627 insert_reg (const char *regname, int regnum)
3628 {
3629 char buf[100];
3630 int i;
3631
3632 #ifdef REGISTER_PREFIX
3633 if (!flag_reg_prefix_optional)
3634 {
3635 buf[0] = REGISTER_PREFIX;
3636 strcpy (buf + 1, regname);
3637 regname = buf;
3638 }
3639 #endif
3640
3641 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3642 &zero_address_frag));
3643
3644 for (i = 0; regname[i]; i++)
3645 buf[i] = TOUPPER (regname[i]);
3646 buf[i] = '\0';
3647
3648 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3649 &zero_address_frag));
3650 }
3651
3652 struct init_entry
3653 {
3654 const char *name;
3655 int number;
3656 };
3657
3658 static const struct init_entry init_table[] =
3659 {
3660 { "d0", DATA0 },
3661 { "d1", DATA1 },
3662 { "d2", DATA2 },
3663 { "d3", DATA3 },
3664 { "d4", DATA4 },
3665 { "d5", DATA5 },
3666 { "d6", DATA6 },
3667 { "d7", DATA7 },
3668 { "a0", ADDR0 },
3669 { "a1", ADDR1 },
3670 { "a2", ADDR2 },
3671 { "a3", ADDR3 },
3672 { "a4", ADDR4 },
3673 { "a5", ADDR5 },
3674 { "a6", ADDR6 },
3675 { "fp", ADDR6 },
3676 { "a7", ADDR7 },
3677 { "sp", ADDR7 },
3678 { "ssp", ADDR7 },
3679 { "fp0", FP0 },
3680 { "fp1", FP1 },
3681 { "fp2", FP2 },
3682 { "fp3", FP3 },
3683 { "fp4", FP4 },
3684 { "fp5", FP5 },
3685 { "fp6", FP6 },
3686 { "fp7", FP7 },
3687 { "fpi", FPI },
3688 { "fpiar", FPI },
3689 { "fpc", FPI },
3690 { "fps", FPS },
3691 { "fpsr", FPS },
3692 { "fpc", FPC },
3693 { "fpcr", FPC },
3694 { "control", FPC },
3695 { "status", FPS },
3696 { "iaddr", FPI },
3697
3698 { "cop0", COP0 },
3699 { "cop1", COP1 },
3700 { "cop2", COP2 },
3701 { "cop3", COP3 },
3702 { "cop4", COP4 },
3703 { "cop5", COP5 },
3704 { "cop6", COP6 },
3705 { "cop7", COP7 },
3706 { "pc", PC },
3707 { "zpc", ZPC },
3708 { "sr", SR },
3709
3710 { "ccr", CCR },
3711 { "cc", CCR },
3712
3713 { "acc", ACC },
3714 { "acc0", ACC },
3715 { "acc1", ACC1 },
3716 { "acc2", ACC2 },
3717 { "acc3", ACC3 },
3718 { "accext01", ACCEXT01 },
3719 { "accext23", ACCEXT23 },
3720 { "macsr", MACSR },
3721 { "mask", MASK },
3722
3723 /* Control registers. */
3724 { "sfc", SFC }, /* Source Function Code. */
3725 { "sfcr", SFC },
3726 { "dfc", DFC }, /* Destination Function Code. */
3727 { "dfcr", DFC },
3728 { "cacr", CACR }, /* Cache Control Register. */
3729 { "caar", CAAR }, /* Cache Address Register. */
3730
3731 { "usp", USP }, /* User Stack Pointer. */
3732 { "vbr", VBR }, /* Vector Base Register. */
3733 { "msp", MSP }, /* Master Stack Pointer. */
3734 { "isp", ISP }, /* Interrupt Stack Pointer. */
3735
3736 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3737 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3738 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3739 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3740
3741 /* 68ec040 versions of same */
3742 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3743 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3744 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3745 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3746
3747 /* mcf5200 versions of same. The ColdFire programmer's reference
3748 manual indicated that the order is 2,3,0,1, but Ken Rose
3749 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3750 { "acr0", ACR0 }, /* Access Control Unit 0. */
3751 { "acr1", ACR1 }, /* Access Control Unit 1. */
3752 { "acr2", ACR2 }, /* Access Control Unit 2. */
3753 { "acr3", ACR3 }, /* Access Control Unit 3. */
3754
3755 { "tc", TC }, /* MMU Translation Control Register. */
3756 { "tcr", TC },
3757
3758 { "mmusr", MMUSR }, /* MMU Status Register. */
3759 { "srp", SRP }, /* User Root Pointer. */
3760 { "urp", URP }, /* Supervisor Root Pointer. */
3761
3762 { "buscr", BUSCR },
3763 { "pcr", PCR },
3764
3765 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3766 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3767 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3768 { "mbar", MBAR }, /* Module Base Address Register. */
3769
3770 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3771 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3772 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3773 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3774 { "mpcr", MPCR }, /* mcfv4e registers. */
3775 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3776 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3777 { "asid", TC }, /* mcfv4e registers. */
3778 { "mmubar", BUSCR }, /* mcfv4e registers. */
3779 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3780 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3781 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3782 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3783 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3784 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3785 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3786 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3787 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3788 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3789 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3790 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3791
3792 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3793 { "rambar", RAMBAR }, /* mcf528x registers. */
3794
3795 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3796 /* End of control registers. */
3797
3798 { "ac", AC },
3799 { "bc", BC },
3800 { "cal", CAL },
3801 { "crp", CRP },
3802 { "drp", DRP },
3803 { "pcsr", PCSR },
3804 { "psr", PSR },
3805 { "scc", SCC },
3806 { "val", VAL },
3807 { "bad0", BAD0 },
3808 { "bad1", BAD1 },
3809 { "bad2", BAD2 },
3810 { "bad3", BAD3 },
3811 { "bad4", BAD4 },
3812 { "bad5", BAD5 },
3813 { "bad6", BAD6 },
3814 { "bad7", BAD7 },
3815 { "bac0", BAC0 },
3816 { "bac1", BAC1 },
3817 { "bac2", BAC2 },
3818 { "bac3", BAC3 },
3819 { "bac4", BAC4 },
3820 { "bac5", BAC5 },
3821 { "bac6", BAC6 },
3822 { "bac7", BAC7 },
3823
3824 { "ic", IC },
3825 { "dc", DC },
3826 { "nc", NC },
3827
3828 { "tt0", TT0 },
3829 { "tt1", TT1 },
3830 /* 68ec030 versions of same. */
3831 { "ac0", TT0 },
3832 { "ac1", TT1 },
3833 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3834 { "acusr", PSR },
3835
3836 /* Suppressed data and address registers. */
3837 { "zd0", ZDATA0 },
3838 { "zd1", ZDATA1 },
3839 { "zd2", ZDATA2 },
3840 { "zd3", ZDATA3 },
3841 { "zd4", ZDATA4 },
3842 { "zd5", ZDATA5 },
3843 { "zd6", ZDATA6 },
3844 { "zd7", ZDATA7 },
3845 { "za0", ZADDR0 },
3846 { "za1", ZADDR1 },
3847 { "za2", ZADDR2 },
3848 { "za3", ZADDR3 },
3849 { "za4", ZADDR4 },
3850 { "za5", ZADDR5 },
3851 { "za6", ZADDR6 },
3852 { "za7", ZADDR7 },
3853
3854 /* Upper and lower data and address registers, used by macw and msacw. */
3855 { "d0l", DATA0L },
3856 { "d1l", DATA1L },
3857 { "d2l", DATA2L },
3858 { "d3l", DATA3L },
3859 { "d4l", DATA4L },
3860 { "d5l", DATA5L },
3861 { "d6l", DATA6L },
3862 { "d7l", DATA7L },
3863
3864 { "a0l", ADDR0L },
3865 { "a1l", ADDR1L },
3866 { "a2l", ADDR2L },
3867 { "a3l", ADDR3L },
3868 { "a4l", ADDR4L },
3869 { "a5l", ADDR5L },
3870 { "a6l", ADDR6L },
3871 { "a7l", ADDR7L },
3872
3873 { "d0u", DATA0U },
3874 { "d1u", DATA1U },
3875 { "d2u", DATA2U },
3876 { "d3u", DATA3U },
3877 { "d4u", DATA4U },
3878 { "d5u", DATA5U },
3879 { "d6u", DATA6U },
3880 { "d7u", DATA7U },
3881
3882 { "a0u", ADDR0U },
3883 { "a1u", ADDR1U },
3884 { "a2u", ADDR2U },
3885 { "a3u", ADDR3U },
3886 { "a4u", ADDR4U },
3887 { "a5u", ADDR5U },
3888 { "a6u", ADDR6U },
3889 { "a7u", ADDR7U },
3890
3891 { 0, 0 }
3892 };
3893
3894 static void
3895 init_regtable (void)
3896 {
3897 int i;
3898 for (i = 0; init_table[i].name; i++)
3899 insert_reg (init_table[i].name, init_table[i].number);
3900 }
3901
3902 void
3903 md_assemble (char *str)
3904 {
3905 const char *er;
3906 short *fromP;
3907 char *toP = NULL;
3908 int m, n = 0;
3909 char *to_beg_P;
3910 int shorts_this_frag;
3911 fixS *fixP;
3912
3913 if (!selected_cpu && !selected_arch)
3914 {
3915 /* We've not selected an architecture yet. Set the default
3916 now. We do this lazily so that an initial .cpu or .arch directive
3917 can specify. */
3918 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3919 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3920 }
3921 if (!initialized)
3922 m68k_init_arch ();
3923
3924 /* In MRI mode, the instruction and operands are separated by a
3925 space. Anything following the operands is a comment. The label
3926 has already been removed. */
3927 if (flag_mri)
3928 {
3929 char *s;
3930 int fields = 0;
3931 int infield = 0;
3932 int inquote = 0;
3933
3934 for (s = str; *s != '\0'; s++)
3935 {
3936 if ((*s == ' ' || *s == '\t') && ! inquote)
3937 {
3938 if (infield)
3939 {
3940 ++fields;
3941 if (fields >= 2)
3942 {
3943 *s = '\0';
3944 break;
3945 }
3946 infield = 0;
3947 }
3948 }
3949 else
3950 {
3951 if (! infield)
3952 infield = 1;
3953 if (*s == '\'')
3954 inquote = ! inquote;
3955 }
3956 }
3957 }
3958
3959 memset (&the_ins, '\0', sizeof (the_ins));
3960 m68k_ip (str);
3961 er = the_ins.error;
3962 if (!er)
3963 {
3964 for (n = 0; n < the_ins.numargs; n++)
3965 if (the_ins.operands[n].error)
3966 {
3967 er = the_ins.operands[n].error;
3968 break;
3969 }
3970 }
3971 if (er)
3972 {
3973 as_bad (_("%s -- statement `%s' ignored"), er, str);
3974 return;
3975 }
3976
3977 /* If there is a current label, record that it marks an instruction. */
3978 if (current_label != NULL)
3979 {
3980 current_label->text = 1;
3981 current_label = NULL;
3982 }
3983
3984 #ifdef OBJ_ELF
3985 /* Tie dwarf2 debug info to the address at the start of the insn. */
3986 dwarf2_emit_insn (0);
3987 #endif
3988
3989 if (the_ins.nfrag == 0)
3990 {
3991 /* No frag hacking involved; just put it out. */
3992 toP = frag_more (2 * the_ins.numo);
3993 fromP = &the_ins.opcode[0];
3994 for (m = the_ins.numo; m; --m)
3995 {
3996 md_number_to_chars (toP, (long) (*fromP), 2);
3997 toP += 2;
3998 fromP++;
3999 }
4000 /* Put out symbol-dependent info. */
4001 for (m = 0; m < the_ins.nrel; m++)
4002 {
4003 switch (the_ins.reloc[m].wid)
4004 {
4005 case 'B':
4006 n = 1;
4007 break;
4008 case 'b':
4009 n = 1;
4010 break;
4011 case '3':
4012 n = 1;
4013 break;
4014 case 'w':
4015 case 'W':
4016 n = 2;
4017 break;
4018 case 'l':
4019 n = 4;
4020 break;
4021 default:
4022 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4023 the_ins.reloc[m].wid);
4024 }
4025
4026 fixP = fix_new_exp (frag_now,
4027 ((toP - frag_now->fr_literal)
4028 - the_ins.numo * 2 + the_ins.reloc[m].n),
4029 n,
4030 &the_ins.reloc[m].exp,
4031 the_ins.reloc[m].pcrel,
4032 get_reloc_code (n, the_ins.reloc[m].pcrel,
4033 the_ins.reloc[m].pic_reloc));
4034 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4035 if (the_ins.reloc[m].wid == 'B')
4036 fixP->fx_signed = 1;
4037 }
4038 return;
4039 }
4040
4041 /* There's some frag hacking. */
4042 {
4043 /* Calculate the max frag size. */
4044 int wid;
4045
4046 wid = 2 * the_ins.fragb[0].fragoff;
4047 for (n = 1; n < the_ins.nfrag; n++)
4048 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4049 /* frag_var part. */
4050 wid += 10;
4051 /* Make sure the whole insn fits in one chunk, in particular that
4052 the var part is attached, as we access one byte before the
4053 variable frag for byte branches. */
4054 frag_grow (wid);
4055 }
4056
4057 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4058 {
4059 int wid;
4060
4061 if (n == 0)
4062 wid = 2 * the_ins.fragb[n].fragoff;
4063 else
4064 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4065 toP = frag_more (wid);
4066 to_beg_P = toP;
4067 shorts_this_frag = 0;
4068 for (m = wid / 2; m; --m)
4069 {
4070 md_number_to_chars (toP, (long) (*fromP), 2);
4071 toP += 2;
4072 fromP++;
4073 shorts_this_frag++;
4074 }
4075 for (m = 0; m < the_ins.nrel; m++)
4076 {
4077 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4078 {
4079 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4080 break;
4081 }
4082 wid = the_ins.reloc[m].wid;
4083 if (wid == 0)
4084 continue;
4085 the_ins.reloc[m].wid = 0;
4086 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4087
4088 fixP = fix_new_exp (frag_now,
4089 ((toP - frag_now->fr_literal)
4090 - the_ins.numo * 2 + the_ins.reloc[m].n),
4091 wid,
4092 &the_ins.reloc[m].exp,
4093 the_ins.reloc[m].pcrel,
4094 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4095 the_ins.reloc[m].pic_reloc));
4096 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4097 }
4098 (void) frag_var (rs_machine_dependent, 10, 0,
4099 (relax_substateT) (the_ins.fragb[n].fragty),
4100 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4101 }
4102 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4103 shorts_this_frag = 0;
4104 if (n)
4105 {
4106 toP = frag_more (n * 2);
4107 while (n--)
4108 {
4109 md_number_to_chars (toP, (long) (*fromP), 2);
4110 toP += 2;
4111 fromP++;
4112 shorts_this_frag++;
4113 }
4114 }
4115 for (m = 0; m < the_ins.nrel; m++)
4116 {
4117 int wid;
4118
4119 wid = the_ins.reloc[m].wid;
4120 if (wid == 0)
4121 continue;
4122 the_ins.reloc[m].wid = 0;
4123 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4124
4125 fixP = fix_new_exp (frag_now,
4126 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4127 - shorts_this_frag * 2),
4128 wid,
4129 &the_ins.reloc[m].exp,
4130 the_ins.reloc[m].pcrel,
4131 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4132 the_ins.reloc[m].pic_reloc));
4133 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4134 }
4135 }
4136
4137 /* Comparison function used by qsort to rank the opcode entries by name. */
4138
4139 static int
4140 m68k_compare_opcode (const void * v1, const void * v2)
4141 {
4142 struct m68k_opcode * op1, * op2;
4143 int ret;
4144
4145 if (v1 == v2)
4146 return 0;
4147
4148 op1 = *(struct m68k_opcode **) v1;
4149 op2 = *(struct m68k_opcode **) v2;
4150
4151 /* Compare the two names. If different, return the comparison.
4152 If the same, return the order they are in the opcode table. */
4153 ret = strcmp (op1->name, op2->name);
4154 if (ret)
4155 return ret;
4156 if (op1 < op2)
4157 return -1;
4158 return 1;
4159 }
4160
4161 void
4162 md_begin (void)
4163 {
4164 const struct m68k_opcode *ins;
4165 struct m68k_incant *hack, *slak;
4166 const char *retval = 0; /* Empty string, or error msg text. */
4167 int i;
4168
4169 /* Set up hash tables with 68000 instructions.
4170 similar to what the vax assembler does. */
4171 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4172 a copy of it at runtime, adding in the information we want but isn't
4173 there. I think it'd be better to have an awk script hack the table
4174 at compile time. Or even just xstr the table and use it as-is. But
4175 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4176 names. */
4177
4178 if (flag_mri)
4179 {
4180 flag_reg_prefix_optional = 1;
4181 m68k_abspcadd = 1;
4182 if (! m68k_rel32_from_cmdline)
4183 m68k_rel32 = 0;
4184 }
4185
4186 /* First sort the opcode table into alphabetical order to seperate
4187 the order that the assembler wants to see the opcodes from the
4188 order that the disassembler wants to see them. */
4189 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4190 if (!m68k_sorted_opcodes)
4191 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4192 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4193
4194 for (i = m68k_numopcodes; i--;)
4195 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4196
4197 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4198 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4199
4200 op_hash = hash_new ();
4201
4202 obstack_begin (&robyn, 4000);
4203 for (i = 0; i < m68k_numopcodes; i++)
4204 {
4205 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4206 do
4207 {
4208 ins = m68k_sorted_opcodes[i];
4209
4210 /* We *could* ignore insns that don't match our
4211 arch here by just leaving them out of the hash. */
4212 slak->m_operands = ins->args;
4213 slak->m_opnum = strlen (slak->m_operands) / 2;
4214 slak->m_arch = ins->arch;
4215 slak->m_opcode = ins->opcode;
4216 /* This is kludgey. */
4217 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4218 if (i + 1 != m68k_numopcodes
4219 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4220 {
4221 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4222 i++;
4223 }
4224 else
4225 slak->m_next = 0;
4226 slak = slak->m_next;
4227 }
4228 while (slak);
4229
4230 retval = hash_insert (op_hash, ins->name, (char *) hack);
4231 if (retval)
4232 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4233 }
4234
4235 for (i = 0; i < m68k_numaliases; i++)
4236 {
4237 const char *name = m68k_opcode_aliases[i].primary;
4238 const char *alias = m68k_opcode_aliases[i].alias;
4239 PTR val = hash_find (op_hash, name);
4240
4241 if (!val)
4242 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4243 retval = hash_insert (op_hash, alias, val);
4244 if (retval)
4245 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4246 }
4247
4248 /* In MRI mode, all unsized branches are variable sized. Normally,
4249 they are word sized. */
4250 if (flag_mri)
4251 {
4252 static struct m68k_opcode_alias mri_aliases[] =
4253 {
4254 { "bhi", "jhi", },
4255 { "bls", "jls", },
4256 { "bcc", "jcc", },
4257 { "bcs", "jcs", },
4258 { "bne", "jne", },
4259 { "beq", "jeq", },
4260 { "bvc", "jvc", },
4261 { "bvs", "jvs", },
4262 { "bpl", "jpl", },
4263 { "bmi", "jmi", },
4264 { "bge", "jge", },
4265 { "blt", "jlt", },
4266 { "bgt", "jgt", },
4267 { "ble", "jle", },
4268 { "bra", "jra", },
4269 { "bsr", "jbsr", },
4270 };
4271
4272 for (i = 0;
4273 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4274 i++)
4275 {
4276 const char *name = mri_aliases[i].primary;
4277 const char *alias = mri_aliases[i].alias;
4278 PTR val = hash_find (op_hash, name);
4279
4280 if (!val)
4281 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4282 retval = hash_jam (op_hash, alias, val);
4283 if (retval)
4284 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4285 }
4286 }
4287
4288 for (i = 0; i < (int) sizeof (notend_table); i++)
4289 {
4290 notend_table[i] = 0;
4291 alt_notend_table[i] = 0;
4292 }
4293
4294 notend_table[','] = 1;
4295 notend_table['{'] = 1;
4296 notend_table['}'] = 1;
4297 alt_notend_table['a'] = 1;
4298 alt_notend_table['A'] = 1;
4299 alt_notend_table['d'] = 1;
4300 alt_notend_table['D'] = 1;
4301 alt_notend_table['#'] = 1;
4302 alt_notend_table['&'] = 1;
4303 alt_notend_table['f'] = 1;
4304 alt_notend_table['F'] = 1;
4305 #ifdef REGISTER_PREFIX
4306 alt_notend_table[REGISTER_PREFIX] = 1;
4307 #endif
4308
4309 /* We need to put '(' in alt_notend_table to handle
4310 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4311 alt_notend_table['('] = 1;
4312
4313 /* We need to put '@' in alt_notend_table to handle
4314 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4315 alt_notend_table['@'] = 1;
4316
4317 /* We need to put digits in alt_notend_table to handle
4318 bfextu %d0{24:1},%d0 */
4319 alt_notend_table['0'] = 1;
4320 alt_notend_table['1'] = 1;
4321 alt_notend_table['2'] = 1;
4322 alt_notend_table['3'] = 1;
4323 alt_notend_table['4'] = 1;
4324 alt_notend_table['5'] = 1;
4325 alt_notend_table['6'] = 1;
4326 alt_notend_table['7'] = 1;
4327 alt_notend_table['8'] = 1;
4328 alt_notend_table['9'] = 1;
4329
4330 #ifndef MIT_SYNTAX_ONLY
4331 /* Insert pseudo ops, these have to go into the opcode table since
4332 gas expects pseudo ops to start with a dot. */
4333 {
4334 int n = 0;
4335
4336 while (mote_pseudo_table[n].poc_name)
4337 {
4338 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4339 hash_insert (op_hash,
4340 mote_pseudo_table[n].poc_name, (char *) hack);
4341 hack->m_operands = 0;
4342 hack->m_opnum = n;
4343 n++;
4344 }
4345 }
4346 #endif
4347
4348 init_regtable ();
4349
4350 #ifdef OBJ_ELF
4351 record_alignment (text_section, 2);
4352 record_alignment (data_section, 2);
4353 record_alignment (bss_section, 2);
4354 #endif
4355 }
4356
4357 \f
4358 /* This is called when a label is defined. */
4359
4360 void
4361 m68k_frob_label (symbolS *sym)
4362 {
4363 struct label_line *n;
4364
4365 n = (struct label_line *) xmalloc (sizeof *n);
4366 n->next = labels;
4367 n->label = sym;
4368 as_where (&n->file, &n->line);
4369 n->text = 0;
4370 labels = n;
4371 current_label = n;
4372
4373 #ifdef OBJ_ELF
4374 dwarf2_emit_label (sym);
4375 #endif
4376 }
4377
4378 /* This is called when a value that is not an instruction is emitted. */
4379
4380 void
4381 m68k_flush_pending_output (void)
4382 {
4383 current_label = NULL;
4384 }
4385
4386 /* This is called at the end of the assembly, when the final value of
4387 the label is known. We warn if this is a text symbol aligned at an
4388 odd location. */
4389
4390 void
4391 m68k_frob_symbol (symbolS *sym)
4392 {
4393 if (S_GET_SEGMENT (sym) == reg_section
4394 && (int) S_GET_VALUE (sym) < 0)
4395 {
4396 S_SET_SEGMENT (sym, absolute_section);
4397 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4398 }
4399 else if ((S_GET_VALUE (sym) & 1) != 0)
4400 {
4401 struct label_line *l;
4402
4403 for (l = labels; l != NULL; l = l->next)
4404 {
4405 if (l->label == sym)
4406 {
4407 if (l->text)
4408 as_warn_where (l->file, l->line,
4409 _("text label `%s' aligned to odd boundary"),
4410 S_GET_NAME (sym));
4411 break;
4412 }
4413 }
4414 }
4415 }
4416 \f
4417 /* This is called if we go in or out of MRI mode because of the .mri
4418 pseudo-op. */
4419
4420 void
4421 m68k_mri_mode_change (int on)
4422 {
4423 if (on)
4424 {
4425 if (! flag_reg_prefix_optional)
4426 {
4427 flag_reg_prefix_optional = 1;
4428 #ifdef REGISTER_PREFIX
4429 init_regtable ();
4430 #endif
4431 }
4432 m68k_abspcadd = 1;
4433 if (! m68k_rel32_from_cmdline)
4434 m68k_rel32 = 0;
4435 }
4436 else
4437 {
4438 if (! reg_prefix_optional_seen)
4439 {
4440 #ifdef REGISTER_PREFIX_OPTIONAL
4441 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4442 #else
4443 flag_reg_prefix_optional = 0;
4444 #endif
4445 #ifdef REGISTER_PREFIX
4446 init_regtable ();
4447 #endif
4448 }
4449 m68k_abspcadd = 0;
4450 if (! m68k_rel32_from_cmdline)
4451 m68k_rel32 = 1;
4452 }
4453 }
4454
4455 /* Equal to MAX_PRECISION in atof-ieee.c. */
4456 #define MAX_LITTLENUMS 6
4457
4458 /* Turn a string in input_line_pointer into a floating point constant
4459 of type TYPE, and store the appropriate bytes in *LITP. The number
4460 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4461 returned, or NULL on OK. */
4462
4463 char *
4464 md_atof (int type, char *litP, int *sizeP)
4465 {
4466 int prec;
4467 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4468 LITTLENUM_TYPE *wordP;
4469 char *t;
4470
4471 switch (type)
4472 {
4473 case 'f':
4474 case 'F':
4475 case 's':
4476 case 'S':
4477 prec = 2;
4478 break;
4479
4480 case 'd':
4481 case 'D':
4482 case 'r':
4483 case 'R':
4484 prec = 4;
4485 break;
4486
4487 case 'x':
4488 case 'X':
4489 prec = 6;
4490 break;
4491
4492 case 'p':
4493 case 'P':
4494 prec = 6;
4495 break;
4496
4497 default:
4498 *sizeP = 0;
4499 return _("Bad call to MD_ATOF()");
4500 }
4501 t = atof_ieee (input_line_pointer, type, words);
4502 if (t)
4503 input_line_pointer = t;
4504
4505 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4506 for (wordP = words; prec--;)
4507 {
4508 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4509 litP += sizeof (LITTLENUM_TYPE);
4510 }
4511 return 0;
4512 }
4513
4514 void
4515 md_number_to_chars (char *buf, valueT val, int n)
4516 {
4517 number_to_chars_bigendian (buf, val, n);
4518 }
4519
4520 void
4521 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4522 {
4523 offsetT val = *valP;
4524 addressT upper_limit;
4525 offsetT lower_limit;
4526
4527 /* This is unnecessary but it convinces the native rs6000 compiler
4528 to generate the code we want. */
4529 char *buf = fixP->fx_frag->fr_literal;
4530 buf += fixP->fx_where;
4531 /* End ibm compiler workaround. */
4532
4533 val = SEXT (val);
4534
4535 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4536 fixP->fx_done = 1;
4537
4538 #ifdef OBJ_ELF
4539 if (fixP->fx_addsy)
4540 {
4541 memset (buf, 0, fixP->fx_size);
4542 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4543
4544 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4545 && !S_IS_DEFINED (fixP->fx_addsy)
4546 && !S_IS_WEAK (fixP->fx_addsy))
4547 S_SET_WEAK (fixP->fx_addsy);
4548 return;
4549 }
4550 #endif
4551
4552 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4553 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4554 return;
4555
4556 switch (fixP->fx_size)
4557 {
4558 /* The cast to offsetT below are necessary to make code
4559 correct for machines where ints are smaller than offsetT. */
4560 case 1:
4561 *buf++ = val;
4562 upper_limit = 0x7f;
4563 lower_limit = - (offsetT) 0x80;
4564 break;
4565 case 2:
4566 *buf++ = (val >> 8);
4567 *buf++ = val;
4568 upper_limit = 0x7fff;
4569 lower_limit = - (offsetT) 0x8000;
4570 break;
4571 case 4:
4572 *buf++ = (val >> 24);
4573 *buf++ = (val >> 16);
4574 *buf++ = (val >> 8);
4575 *buf++ = val;
4576 upper_limit = 0x7fffffff;
4577 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4578 break;
4579 default:
4580 BAD_CASE (fixP->fx_size);
4581 }
4582
4583 /* Fix up a negative reloc. */
4584 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4585 {
4586 fixP->fx_addsy = fixP->fx_subsy;
4587 fixP->fx_subsy = NULL;
4588 fixP->fx_tcbit = 1;
4589 }
4590
4591 /* For non-pc-relative values, it's conceivable we might get something
4592 like "0xff" for a byte field. So extend the upper part of the range
4593 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4594 so that we can do any range checking at all. */
4595 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4596 upper_limit = upper_limit * 2 + 1;
4597
4598 if ((addressT) val > upper_limit
4599 && (val > 0 || val < lower_limit))
4600 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4601
4602 /* A one byte PC-relative reloc means a short branch. We can't use
4603 a short branch with a value of 0 or -1, because those indicate
4604 different opcodes (branches with longer offsets). fixup_segment
4605 in write.c may have clobbered fx_pcrel, so we need to examine the
4606 reloc type. */
4607 if ((fixP->fx_pcrel
4608 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4609 && fixP->fx_size == 1
4610 && (fixP->fx_addsy == NULL
4611 || S_IS_DEFINED (fixP->fx_addsy))
4612 && (val == 0 || val == -1))
4613 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4614 }
4615
4616 /* *fragP has been relaxed to its final size, and now needs to have
4617 the bytes inside it modified to conform to the new size There is UGLY
4618 MAGIC here. ..
4619 */
4620 static void
4621 md_convert_frag_1 (fragS *fragP)
4622 {
4623 long disp;
4624 fixS *fixP;
4625
4626 /* Address in object code of the displacement. */
4627 register int object_address = fragP->fr_fix + fragP->fr_address;
4628
4629 /* Address in gas core of the place to store the displacement. */
4630 /* This convinces the native rs6000 compiler to generate the code we
4631 want. */
4632 register char *buffer_address = fragP->fr_literal;
4633 buffer_address += fragP->fr_fix;
4634 /* End ibm compiler workaround. */
4635
4636 /* The displacement of the address, from current location. */
4637 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4638 disp = (disp + fragP->fr_offset) - object_address;
4639
4640 switch (fragP->fr_subtype)
4641 {
4642 case TAB (BRANCHBWL, BYTE):
4643 case TAB (BRABSJUNC, BYTE):
4644 case TAB (BRABSJCOND, BYTE):
4645 case TAB (BRANCHBW, BYTE):
4646 know (issbyte (disp));
4647 if (disp == 0)
4648 as_bad_where (fragP->fr_file, fragP->fr_line,
4649 _("short branch with zero offset: use :w"));
4650 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4651 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4652 fixP->fx_pcrel_adjust = -1;
4653 break;
4654 case TAB (BRANCHBWL, SHORT):
4655 case TAB (BRABSJUNC, SHORT):
4656 case TAB (BRABSJCOND, SHORT):
4657 case TAB (BRANCHBW, SHORT):
4658 fragP->fr_opcode[1] = 0x00;
4659 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4660 1, RELAX_RELOC_PC16);
4661 fragP->fr_fix += 2;
4662 break;
4663 case TAB (BRANCHBWL, LONG):
4664 fragP->fr_opcode[1] = (char) 0xFF;
4665 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4666 1, RELAX_RELOC_PC32);
4667 fragP->fr_fix += 4;
4668 break;
4669 case TAB (BRABSJUNC, LONG):
4670 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4671 {
4672 if (flag_keep_pcrel)
4673 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4674 fragP->fr_opcode[0] = 0x4E;
4675 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4676 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4677 0, RELAX_RELOC_ABS32);
4678 fragP->fr_fix += 4;
4679 }
4680 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4681 {
4682 if (flag_keep_pcrel)
4683 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4684 fragP->fr_opcode[0] = 0x4E;
4685 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4686 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4687 0, RELAX_RELOC_ABS32);
4688 fragP->fr_fix += 4;
4689 }
4690 else
4691 {
4692 /* This cannot happen, because jbsr and jbra are the only two
4693 unconditional branches. */
4694 abort ();
4695 }
4696 break;
4697 case TAB (BRABSJCOND, LONG):
4698 if (flag_keep_pcrel)
4699 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4700
4701 /* Only Bcc 68000 instructions can come here
4702 Change bcc into b!cc/jmp absl long. */
4703 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4704 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4705
4706 /* JF: these used to be fr_opcode[2,3], but they may be in a
4707 different frag, in which case referring to them is a no-no.
4708 Only fr_opcode[0,1] are guaranteed to work. */
4709 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4710 *buffer_address++ = (char) 0xf9;
4711 fragP->fr_fix += 2; /* Account for jmp instruction. */
4712 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4713 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4714 fragP->fr_fix += 4;
4715 break;
4716 case TAB (FBRANCH, SHORT):
4717 know ((fragP->fr_opcode[1] & 0x40) == 0);
4718 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4719 1, RELAX_RELOC_PC16);
4720 fragP->fr_fix += 2;
4721 break;
4722 case TAB (FBRANCH, LONG):
4723 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4724 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4725 1, RELAX_RELOC_PC32);
4726 fragP->fr_fix += 4;
4727 break;
4728 case TAB (DBCCLBR, SHORT):
4729 case TAB (DBCCABSJ, SHORT):
4730 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4731 1, RELAX_RELOC_PC16);
4732 fragP->fr_fix += 2;
4733 break;
4734 case TAB (DBCCLBR, LONG):
4735 /* Only DBcc instructions can come here.
4736 Change dbcc into dbcc/bral.
4737 JF: these used to be fr_opcode[2-7], but that's wrong. */
4738 if (flag_keep_pcrel)
4739 as_fatal (_("Tried to convert DBcc to absolute jump"));
4740
4741 *buffer_address++ = 0x00; /* Branch offset = 4. */
4742 *buffer_address++ = 0x04;
4743 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4744 *buffer_address++ = 0x06;
4745 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4746 *buffer_address++ = (char) 0xff;
4747
4748 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4749 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4750 RELAX_RELOC_PC32);
4751 fragP->fr_fix += 4;
4752 break;
4753 case TAB (DBCCABSJ, LONG):
4754 /* Only DBcc instructions can come here.
4755 Change dbcc into dbcc/jmp.
4756 JF: these used to be fr_opcode[2-7], but that's wrong. */
4757 if (flag_keep_pcrel)
4758 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4759
4760 *buffer_address++ = 0x00; /* Branch offset = 4. */
4761 *buffer_address++ = 0x04;
4762 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4763 *buffer_address++ = 0x06;
4764 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4765 *buffer_address++ = (char) 0xf9;
4766
4767 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4768 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4769 RELAX_RELOC_ABS32);
4770 fragP->fr_fix += 4;
4771 break;
4772 case TAB (PCREL1632, SHORT):
4773 fragP->fr_opcode[1] &= ~0x3F;
4774 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4775 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4776 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4777 fragP->fr_fix += 2;
4778 break;
4779 case TAB (PCREL1632, LONG):
4780 /* Already set to mode 7.3; this indicates: PC indirect with
4781 suppressed index, 32-bit displacement. */
4782 *buffer_address++ = 0x01;
4783 *buffer_address++ = 0x70;
4784 fragP->fr_fix += 2;
4785 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4786 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4787 fixP->fx_pcrel_adjust = 2;
4788 fragP->fr_fix += 4;
4789 break;
4790 case TAB (PCINDEX, BYTE):
4791 assert (fragP->fr_fix >= 2);
4792 buffer_address[-2] &= ~1;
4793 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4794 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4795 fixP->fx_pcrel_adjust = 1;
4796 break;
4797 case TAB (PCINDEX, SHORT):
4798 assert (fragP->fr_fix >= 2);
4799 buffer_address[-2] |= 0x1;
4800 buffer_address[-1] = 0x20;
4801 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4802 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4803 fixP->fx_pcrel_adjust = 2;
4804 fragP->fr_fix += 2;
4805 break;
4806 case TAB (PCINDEX, LONG):
4807 assert (fragP->fr_fix >= 2);
4808 buffer_address[-2] |= 0x1;
4809 buffer_address[-1] = 0x30;
4810 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4811 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4812 fixP->fx_pcrel_adjust = 2;
4813 fragP->fr_fix += 4;
4814 break;
4815 case TAB (ABSTOPCREL, SHORT):
4816 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4817 1, RELAX_RELOC_PC16);
4818 fragP->fr_fix += 2;
4819 break;
4820 case TAB (ABSTOPCREL, LONG):
4821 if (flag_keep_pcrel)
4822 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4823 /* The thing to do here is force it to ABSOLUTE LONG, since
4824 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4825 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4826 abort ();
4827 fragP->fr_opcode[1] &= ~0x3F;
4828 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4829 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4830 0, RELAX_RELOC_ABS32);
4831 fragP->fr_fix += 4;
4832 break;
4833 }
4834 }
4835
4836 void
4837 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4838 segT sec ATTRIBUTE_UNUSED,
4839 fragS *fragP)
4840 {
4841 md_convert_frag_1 (fragP);
4842 }
4843
4844 /* Force truly undefined symbols to their maximum size, and generally set up
4845 the frag list to be relaxed
4846 */
4847 int
4848 md_estimate_size_before_relax (fragS *fragP, segT segment)
4849 {
4850 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4851 switch (fragP->fr_subtype)
4852 {
4853 case TAB (BRANCHBWL, SZ_UNDEF):
4854 case TAB (BRABSJUNC, SZ_UNDEF):
4855 case TAB (BRABSJCOND, SZ_UNDEF):
4856 {
4857 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4858 && relaxable_symbol (fragP->fr_symbol))
4859 {
4860 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4861 }
4862 else if (flag_short_refs)
4863 {
4864 /* Symbol is undefined and we want short ref. */
4865 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4866 }
4867 else
4868 {
4869 /* Symbol is still undefined. Make it LONG. */
4870 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4871 }
4872 break;
4873 }
4874
4875 case TAB (BRANCHBW, SZ_UNDEF):
4876 {
4877 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4878 && relaxable_symbol (fragP->fr_symbol))
4879 {
4880 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4881 }
4882 else
4883 {
4884 /* Symbol is undefined and we don't have long branches. */
4885 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4886 }
4887 break;
4888 }
4889
4890 case TAB (FBRANCH, SZ_UNDEF):
4891 case TAB (DBCCLBR, SZ_UNDEF):
4892 case TAB (DBCCABSJ, SZ_UNDEF):
4893 case TAB (PCREL1632, SZ_UNDEF):
4894 {
4895 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4896 && relaxable_symbol (fragP->fr_symbol))
4897 || flag_short_refs)
4898 {
4899 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4900 }
4901 else
4902 {
4903 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4904 }
4905 break;
4906 }
4907
4908 case TAB (PCINDEX, SZ_UNDEF):
4909 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4910 && relaxable_symbol (fragP->fr_symbol)))
4911 {
4912 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4913 }
4914 else
4915 {
4916 fragP->fr_subtype = TAB (PCINDEX, LONG);
4917 }
4918 break;
4919
4920 case TAB (ABSTOPCREL, SZ_UNDEF):
4921 {
4922 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4923 && relaxable_symbol (fragP->fr_symbol)))
4924 {
4925 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4926 }
4927 else
4928 {
4929 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4930 }
4931 break;
4932 }
4933
4934 default:
4935 break;
4936 }
4937
4938 /* Now that SZ_UNDEF are taken care of, check others. */
4939 switch (fragP->fr_subtype)
4940 {
4941 case TAB (BRANCHBWL, BYTE):
4942 case TAB (BRABSJUNC, BYTE):
4943 case TAB (BRABSJCOND, BYTE):
4944 case TAB (BRANCHBW, BYTE):
4945 /* We can't do a short jump to the next instruction, so in that
4946 case we force word mode. If the symbol is at the start of a
4947 frag, and it is the next frag with any data in it (usually
4948 this is just the next frag, but assembler listings may
4949 introduce empty frags), we must use word mode. */
4950 if (fragP->fr_symbol)
4951 {
4952 fragS *sym_frag;
4953
4954 sym_frag = symbol_get_frag (fragP->fr_symbol);
4955 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4956 {
4957 fragS *l;
4958
4959 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
4960 if (l->fr_fix != 0)
4961 break;
4962 if (l == sym_frag)
4963 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4964 }
4965 }
4966 break;
4967 default:
4968 break;
4969 }
4970 return md_relax_table[fragP->fr_subtype].rlx_length;
4971 }
4972
4973 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4974 /* the bit-field entries in the relocation_info struct plays hell
4975 with the byte-order problems of cross-assembly. So as a hack,
4976 I added this mach. dependent ri twiddler. Ugly, but it gets
4977 you there. -KWK */
4978 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4979 are symbolnum, most sig. byte first. Last byte is broken up with
4980 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4981 nibble as nuthin. (on Sun 3 at least) */
4982 /* Translate the internal relocation information into target-specific
4983 format. */
4984 #ifdef comment
4985 void
4986 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
4987 {
4988 /* This is easy. */
4989 md_number_to_chars (the_bytes, ri->r_address, 4);
4990 /* Now the fun stuff. */
4991 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4992 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4993 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4994 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
4995 | ((ri->r_length << 5) & 0x60)
4996 | ((ri->r_extern << 4) & 0x10));
4997 }
4998
4999 #endif
5000
5001 #endif /* OBJ_AOUT or OBJ_BOUT */
5002
5003 #ifndef WORKING_DOT_WORD
5004 int md_short_jump_size = 4;
5005 int md_long_jump_size = 6;
5006
5007 void
5008 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5009 fragS *frag ATTRIBUTE_UNUSED,
5010 symbolS *to_symbol ATTRIBUTE_UNUSED)
5011 {
5012 valueT offset;
5013
5014 offset = to_addr - (from_addr + 2);
5015
5016 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5017 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5018 }
5019
5020 void
5021 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5022 fragS *frag, symbolS *to_symbol)
5023 {
5024 valueT offset;
5025
5026 if (!HAVE_LONG_BRANCH (current_architecture))
5027 {
5028 if (flag_keep_pcrel)
5029 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5030 offset = to_addr - S_GET_VALUE (to_symbol);
5031 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5032 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5033 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5034 0, NO_RELOC);
5035 }
5036 else
5037 {
5038 offset = to_addr - (from_addr + 2);
5039 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5040 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5041 }
5042 }
5043
5044 #endif
5045
5046 /* Different values of OK tell what its OK to return. Things that
5047 aren't OK are an error (what a shock, no?)
5048
5049 0: Everything is OK
5050 10: Absolute 1:8 only
5051 20: Absolute 0:7 only
5052 30: absolute 0:15 only
5053 40: Absolute 0:31 only
5054 50: absolute 0:127 only
5055 55: absolute -64:63 only
5056 60: absolute -128:127 only
5057 70: absolute 0:4095 only
5058 80: absolute -1, 1:7 only
5059 90: No bignums. */
5060
5061 static int
5062 get_num (struct m68k_exp *exp, int ok)
5063 {
5064 if (exp->exp.X_op == O_absent)
5065 {
5066 /* Do the same thing the VAX asm does. */
5067 op (exp) = O_constant;
5068 adds (exp) = 0;
5069 subs (exp) = 0;
5070 offs (exp) = 0;
5071 if (ok == 10)
5072 {
5073 as_warn (_("expression out of range: defaulting to 1"));
5074 offs (exp) = 1;
5075 }
5076 }
5077 else if (exp->exp.X_op == O_constant)
5078 {
5079 switch (ok)
5080 {
5081 case 10:
5082 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5083 {
5084 as_warn (_("expression out of range: defaulting to 1"));
5085 offs (exp) = 1;
5086 }
5087 break;
5088 case 20:
5089 if ((valueT) TRUNC (offs (exp)) > 7)
5090 goto outrange;
5091 break;
5092 case 30:
5093 if ((valueT) TRUNC (offs (exp)) > 15)
5094 goto outrange;
5095 break;
5096 case 40:
5097 if ((valueT) TRUNC (offs (exp)) > 32)
5098 goto outrange;
5099 break;
5100 case 50:
5101 if ((valueT) TRUNC (offs (exp)) > 127)
5102 goto outrange;
5103 break;
5104 case 55:
5105 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5106 goto outrange;
5107 break;
5108 case 60:
5109 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5110 goto outrange;
5111 break;
5112 case 70:
5113 if ((valueT) TRUNC (offs (exp)) > 4095)
5114 {
5115 outrange:
5116 as_warn (_("expression out of range: defaulting to 0"));
5117 offs (exp) = 0;
5118 }
5119 break;
5120 case 80:
5121 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5122 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5123 {
5124 as_warn (_("expression out of range: defaulting to 1"));
5125 offs (exp) = 1;
5126 }
5127 break;
5128 default:
5129 break;
5130 }
5131 }
5132 else if (exp->exp.X_op == O_big)
5133 {
5134 if (offs (exp) <= 0 /* flonum. */
5135 && (ok == 90 /* no bignums */
5136 || (ok > 10 /* Small-int ranges including 0 ok. */
5137 /* If we have a flonum zero, a zero integer should
5138 do as well (e.g., in moveq). */
5139 && generic_floating_point_number.exponent == 0
5140 && generic_floating_point_number.low[0] == 0)))
5141 {
5142 /* HACK! Turn it into a long. */
5143 LITTLENUM_TYPE words[6];
5144
5145 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5146 op (exp) = O_constant;
5147 adds (exp) = 0;
5148 subs (exp) = 0;
5149 offs (exp) = words[1] | (words[0] << 16);
5150 }
5151 else if (ok != 0)
5152 {
5153 op (exp) = O_constant;
5154 adds (exp) = 0;
5155 subs (exp) = 0;
5156 offs (exp) = (ok == 10) ? 1 : 0;
5157 as_warn (_("Can't deal with expression; defaulting to %ld"),
5158 (long) offs (exp));
5159 }
5160 }
5161 else
5162 {
5163 if (ok >= 10 && ok <= 80)
5164 {
5165 op (exp) = O_constant;
5166 adds (exp) = 0;
5167 subs (exp) = 0;
5168 offs (exp) = (ok == 10) ? 1 : 0;
5169 as_warn (_("Can't deal with expression; defaulting to %ld"),
5170 (long) offs (exp));
5171 }
5172 }
5173
5174 if (exp->size != SIZE_UNSPEC)
5175 {
5176 switch (exp->size)
5177 {
5178 case SIZE_UNSPEC:
5179 case SIZE_LONG:
5180 break;
5181 case SIZE_BYTE:
5182 if (!isbyte (offs (exp)))
5183 as_warn (_("expression doesn't fit in BYTE"));
5184 break;
5185 case SIZE_WORD:
5186 if (!isword (offs (exp)))
5187 as_warn (_("expression doesn't fit in WORD"));
5188 break;
5189 }
5190 }
5191
5192 return offs (exp);
5193 }
5194
5195 /* These are the back-ends for the various machine dependent pseudo-ops. */
5196
5197 static void
5198 s_data1 (int ignore ATTRIBUTE_UNUSED)
5199 {
5200 subseg_set (data_section, 1);
5201 demand_empty_rest_of_line ();
5202 }
5203
5204 static void
5205 s_data2 (int ignore ATTRIBUTE_UNUSED)
5206 {
5207 subseg_set (data_section, 2);
5208 demand_empty_rest_of_line ();
5209 }
5210
5211 static void
5212 s_bss (int ignore ATTRIBUTE_UNUSED)
5213 {
5214 /* We don't support putting frags in the BSS segment, we fake it
5215 by marking in_bss, then looking at s_skip for clues. */
5216
5217 subseg_set (bss_section, 0);
5218 demand_empty_rest_of_line ();
5219 }
5220
5221 static void
5222 s_even (int ignore ATTRIBUTE_UNUSED)
5223 {
5224 register int temp;
5225 register long temp_fill;
5226
5227 temp = 1; /* JF should be 2? */
5228 temp_fill = get_absolute_expression ();
5229 if (!need_pass_2) /* Never make frag if expect extra pass. */
5230 frag_align (temp, (int) temp_fill, 0);
5231 demand_empty_rest_of_line ();
5232 record_alignment (now_seg, temp);
5233 }
5234
5235 static void
5236 s_proc (int ignore ATTRIBUTE_UNUSED)
5237 {
5238 demand_empty_rest_of_line ();
5239 }
5240 \f
5241 /* Pseudo-ops handled for MRI compatibility. */
5242
5243 /* This function returns non-zero if the argument is a conditional
5244 pseudo-op. This is called when checking whether a pending
5245 alignment is needed. */
5246
5247 int
5248 m68k_conditional_pseudoop (pseudo_typeS *pop)
5249 {
5250 return (pop->poc_handler == s_mri_if
5251 || pop->poc_handler == s_mri_else);
5252 }
5253
5254 /* Handle an MRI style chip specification. */
5255
5256 static void
5257 mri_chip (void)
5258 {
5259 char *s;
5260 char c;
5261 int i;
5262
5263 s = input_line_pointer;
5264 /* We can't use get_symbol_end since the processor names are not proper
5265 symbols. */
5266 while (is_part_of_name (c = *input_line_pointer++))
5267 ;
5268 *--input_line_pointer = 0;
5269 for (i = 0; m68k_cpus[i].name; i++)
5270 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5271 break;
5272 if (!m68k_cpus[i].name)
5273 {
5274 as_bad (_("%s: unrecognized processor name"), s);
5275 *input_line_pointer = c;
5276 ignore_rest_of_line ();
5277 return;
5278 }
5279 *input_line_pointer = c;
5280
5281 if (*input_line_pointer == '/')
5282 current_architecture = 0;
5283 else
5284 current_architecture &= m68881 | m68851;
5285 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5286 control_regs = m68k_cpus[i].control_regs;
5287
5288 while (*input_line_pointer == '/')
5289 {
5290 ++input_line_pointer;
5291 s = input_line_pointer;
5292 /* We can't use get_symbol_end since the processor names are not
5293 proper symbols. */
5294 while (is_part_of_name (c = *input_line_pointer++))
5295 ;
5296 *--input_line_pointer = 0;
5297 if (strcmp (s, "68881") == 0)
5298 current_architecture |= m68881;
5299 else if (strcmp (s, "68851") == 0)
5300 current_architecture |= m68851;
5301 *input_line_pointer = c;
5302 }
5303 }
5304
5305 /* The MRI CHIP pseudo-op. */
5306
5307 static void
5308 s_chip (int ignore ATTRIBUTE_UNUSED)
5309 {
5310 char *stop = NULL;
5311 char stopc;
5312
5313 if (flag_mri)
5314 stop = mri_comment_field (&stopc);
5315 mri_chip ();
5316 if (flag_mri)
5317 mri_comment_end (stop, stopc);
5318 demand_empty_rest_of_line ();
5319 }
5320
5321 /* The MRI FOPT pseudo-op. */
5322
5323 static void
5324 s_fopt (int ignore ATTRIBUTE_UNUSED)
5325 {
5326 SKIP_WHITESPACE ();
5327
5328 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5329 {
5330 int temp;
5331
5332 input_line_pointer += 3;
5333 temp = get_absolute_expression ();
5334 if (temp < 0 || temp > 7)
5335 as_bad (_("bad coprocessor id"));
5336 else
5337 m68k_float_copnum = COP0 + temp;
5338 }
5339 else
5340 {
5341 as_bad (_("unrecognized fopt option"));
5342 ignore_rest_of_line ();
5343 return;
5344 }
5345
5346 demand_empty_rest_of_line ();
5347 }
5348
5349 /* The structure used to handle the MRI OPT pseudo-op. */
5350
5351 struct opt_action
5352 {
5353 /* The name of the option. */
5354 const char *name;
5355
5356 /* If this is not NULL, just call this function. The first argument
5357 is the ARG field of this structure, the second argument is
5358 whether the option was negated. */
5359 void (*pfn) (int arg, int on);
5360
5361 /* If this is not NULL, and the PFN field is NULL, set the variable
5362 this points to. Set it to the ARG field if the option was not
5363 negated, and the NOTARG field otherwise. */
5364 int *pvar;
5365
5366 /* The value to pass to PFN or to assign to *PVAR. */
5367 int arg;
5368
5369 /* The value to assign to *PVAR if the option is negated. If PFN is
5370 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5371 the option may not be negated. */
5372 int notarg;
5373 };
5374
5375 /* The table used to handle the MRI OPT pseudo-op. */
5376
5377 static void skip_to_comma (int, int);
5378 static void opt_nest (int, int);
5379 static void opt_chip (int, int);
5380 static void opt_list (int, int);
5381 static void opt_list_symbols (int, int);
5382
5383 static const struct opt_action opt_table[] =
5384 {
5385 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5386
5387 /* We do relaxing, so there is little use for these options. */
5388 { "b", 0, 0, 0, 0 },
5389 { "brs", 0, 0, 0, 0 },
5390 { "brb", 0, 0, 0, 0 },
5391 { "brl", 0, 0, 0, 0 },
5392 { "brw", 0, 0, 0, 0 },
5393
5394 { "c", 0, 0, 0, 0 },
5395 { "cex", 0, 0, 0, 0 },
5396 { "case", 0, &symbols_case_sensitive, 1, 0 },
5397 { "cl", 0, 0, 0, 0 },
5398 { "cre", 0, 0, 0, 0 },
5399 { "d", 0, &flag_keep_locals, 1, 0 },
5400 { "e", 0, 0, 0, 0 },
5401 { "f", 0, &flag_short_refs, 1, 0 },
5402 { "frs", 0, &flag_short_refs, 1, 0 },
5403 { "frl", 0, &flag_short_refs, 0, 1 },
5404 { "g", 0, 0, 0, 0 },
5405 { "i", 0, 0, 0, 0 },
5406 { "m", 0, 0, 0, 0 },
5407 { "mex", 0, 0, 0, 0 },
5408 { "mc", 0, 0, 0, 0 },
5409 { "md", 0, 0, 0, 0 },
5410 { "nest", opt_nest, 0, 0, 0 },
5411 { "next", skip_to_comma, 0, 0, 0 },
5412 { "o", 0, 0, 0, 0 },
5413 { "old", 0, 0, 0, 0 },
5414 { "op", skip_to_comma, 0, 0, 0 },
5415 { "pco", 0, 0, 0, 0 },
5416 { "p", opt_chip, 0, 0, 0 },
5417 { "pcr", 0, 0, 0, 0 },
5418 { "pcs", 0, 0, 0, 0 },
5419 { "r", 0, 0, 0, 0 },
5420 { "quick", 0, &m68k_quick, 1, 0 },
5421 { "rel32", 0, &m68k_rel32, 1, 0 },
5422 { "s", opt_list, 0, 0, 0 },
5423 { "t", opt_list_symbols, 0, 0, 0 },
5424 { "w", 0, &flag_no_warnings, 0, 1 },
5425 { "x", 0, 0, 0, 0 }
5426 };
5427
5428 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5429
5430 /* The MRI OPT pseudo-op. */
5431
5432 static void
5433 s_opt (int ignore ATTRIBUTE_UNUSED)
5434 {
5435 do
5436 {
5437 int t;
5438 char *s;
5439 char c;
5440 int i;
5441 const struct opt_action *o;
5442
5443 SKIP_WHITESPACE ();
5444
5445 t = 1;
5446 if (*input_line_pointer == '-')
5447 {
5448 ++input_line_pointer;
5449 t = 0;
5450 }
5451 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5452 {
5453 input_line_pointer += 2;
5454 t = 0;
5455 }
5456
5457 s = input_line_pointer;
5458 c = get_symbol_end ();
5459
5460 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5461 {
5462 if (strcasecmp (s, o->name) == 0)
5463 {
5464 if (o->pfn)
5465 {
5466 /* Restore input_line_pointer now in case the option
5467 takes arguments. */
5468 *input_line_pointer = c;
5469 (*o->pfn) (o->arg, t);
5470 }
5471 else if (o->pvar != NULL)
5472 {
5473 if (! t && o->arg == o->notarg)
5474 as_bad (_("option `%s' may not be negated"), s);
5475 *input_line_pointer = c;
5476 *o->pvar = t ? o->arg : o->notarg;
5477 }
5478 else
5479 *input_line_pointer = c;
5480 break;
5481 }
5482 }
5483 if (i >= OPTCOUNT)
5484 {
5485 as_bad (_("option `%s' not recognized"), s);
5486 *input_line_pointer = c;
5487 }
5488 }
5489 while (*input_line_pointer++ == ',');
5490
5491 /* Move back to terminating character. */
5492 --input_line_pointer;
5493 demand_empty_rest_of_line ();
5494 }
5495
5496 /* Skip ahead to a comma. This is used for OPT options which we do
5497 not support and which take arguments. */
5498
5499 static void
5500 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5501 {
5502 while (*input_line_pointer != ','
5503 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5504 ++input_line_pointer;
5505 }
5506
5507 /* Handle the OPT NEST=depth option. */
5508
5509 static void
5510 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5511 {
5512 if (*input_line_pointer != '=')
5513 {
5514 as_bad (_("bad format of OPT NEST=depth"));
5515 return;
5516 }
5517
5518 ++input_line_pointer;
5519 max_macro_nest = get_absolute_expression ();
5520 }
5521
5522 /* Handle the OPT P=chip option. */
5523
5524 static void
5525 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5526 {
5527 if (*input_line_pointer != '=')
5528 {
5529 /* This is just OPT P, which we do not support. */
5530 return;
5531 }
5532
5533 ++input_line_pointer;
5534 mri_chip ();
5535 }
5536
5537 /* Handle the OPT S option. */
5538
5539 static void
5540 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5541 {
5542 listing_list (on);
5543 }
5544
5545 /* Handle the OPT T option. */
5546
5547 static void
5548 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5549 {
5550 if (on)
5551 listing |= LISTING_SYMBOLS;
5552 else
5553 listing &= ~LISTING_SYMBOLS;
5554 }
5555
5556 /* Handle the MRI REG pseudo-op. */
5557
5558 static void
5559 s_reg (int ignore ATTRIBUTE_UNUSED)
5560 {
5561 char *s;
5562 int c;
5563 struct m68k_op rop;
5564 int mask;
5565 char *stop = NULL;
5566 char stopc;
5567
5568 if (line_label == NULL)
5569 {
5570 as_bad (_("missing label"));
5571 ignore_rest_of_line ();
5572 return;
5573 }
5574
5575 if (flag_mri)
5576 stop = mri_comment_field (&stopc);
5577
5578 SKIP_WHITESPACE ();
5579
5580 s = input_line_pointer;
5581 while (ISALNUM (*input_line_pointer)
5582 #ifdef REGISTER_PREFIX
5583 || *input_line_pointer == REGISTER_PREFIX
5584 #endif
5585 || *input_line_pointer == '/'
5586 || *input_line_pointer == '-')
5587 ++input_line_pointer;
5588 c = *input_line_pointer;
5589 *input_line_pointer = '\0';
5590
5591 if (m68k_ip_op (s, &rop) != 0)
5592 {
5593 if (rop.error == NULL)
5594 as_bad (_("bad register list"));
5595 else
5596 as_bad (_("bad register list: %s"), rop.error);
5597 *input_line_pointer = c;
5598 ignore_rest_of_line ();
5599 return;
5600 }
5601
5602 *input_line_pointer = c;
5603
5604 if (rop.mode == REGLST)
5605 mask = rop.mask;
5606 else if (rop.mode == DREG)
5607 mask = 1 << (rop.reg - DATA0);
5608 else if (rop.mode == AREG)
5609 mask = 1 << (rop.reg - ADDR0 + 8);
5610 else if (rop.mode == FPREG)
5611 mask = 1 << (rop.reg - FP0 + 16);
5612 else if (rop.mode == CONTROL
5613 && rop.reg == FPI)
5614 mask = 1 << 24;
5615 else if (rop.mode == CONTROL
5616 && rop.reg == FPS)
5617 mask = 1 << 25;
5618 else if (rop.mode == CONTROL
5619 && rop.reg == FPC)
5620 mask = 1 << 26;
5621 else
5622 {
5623 as_bad (_("bad register list"));
5624 ignore_rest_of_line ();
5625 return;
5626 }
5627
5628 S_SET_SEGMENT (line_label, reg_section);
5629 S_SET_VALUE (line_label, ~mask);
5630 symbol_set_frag (line_label, &zero_address_frag);
5631
5632 if (flag_mri)
5633 mri_comment_end (stop, stopc);
5634
5635 demand_empty_rest_of_line ();
5636 }
5637
5638 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5639
5640 struct save_opts
5641 {
5642 struct save_opts *next;
5643 int abspcadd;
5644 int symbols_case_sensitive;
5645 int keep_locals;
5646 int short_refs;
5647 int architecture;
5648 const enum m68k_register *control_regs;
5649 int quick;
5650 int rel32;
5651 int listing;
5652 int no_warnings;
5653 /* FIXME: We don't save OPT S. */
5654 };
5655
5656 /* This variable holds the stack of saved options. */
5657
5658 static struct save_opts *save_stack;
5659
5660 /* The MRI SAVE pseudo-op. */
5661
5662 static void
5663 s_save (int ignore ATTRIBUTE_UNUSED)
5664 {
5665 struct save_opts *s;
5666
5667 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5668 s->abspcadd = m68k_abspcadd;
5669 s->symbols_case_sensitive = symbols_case_sensitive;
5670 s->keep_locals = flag_keep_locals;
5671 s->short_refs = flag_short_refs;
5672 s->architecture = current_architecture;
5673 s->control_regs = control_regs;
5674 s->quick = m68k_quick;
5675 s->rel32 = m68k_rel32;
5676 s->listing = listing;
5677 s->no_warnings = flag_no_warnings;
5678
5679 s->next = save_stack;
5680 save_stack = s;
5681
5682 demand_empty_rest_of_line ();
5683 }
5684
5685 /* The MRI RESTORE pseudo-op. */
5686
5687 static void
5688 s_restore (int ignore ATTRIBUTE_UNUSED)
5689 {
5690 struct save_opts *s;
5691
5692 if (save_stack == NULL)
5693 {
5694 as_bad (_("restore without save"));
5695 ignore_rest_of_line ();
5696 return;
5697 }
5698
5699 s = save_stack;
5700 save_stack = s->next;
5701
5702 m68k_abspcadd = s->abspcadd;
5703 symbols_case_sensitive = s->symbols_case_sensitive;
5704 flag_keep_locals = s->keep_locals;
5705 flag_short_refs = s->short_refs;
5706 current_architecture = s->architecture;
5707 control_regs = s->control_regs;
5708 m68k_quick = s->quick;
5709 m68k_rel32 = s->rel32;
5710 listing = s->listing;
5711 flag_no_warnings = s->no_warnings;
5712
5713 free (s);
5714
5715 demand_empty_rest_of_line ();
5716 }
5717
5718 /* Types of MRI structured control directives. */
5719
5720 enum mri_control_type
5721 {
5722 mri_for,
5723 mri_if,
5724 mri_repeat,
5725 mri_while
5726 };
5727
5728 /* This structure is used to stack the MRI structured control
5729 directives. */
5730
5731 struct mri_control_info
5732 {
5733 /* The directive within which this one is enclosed. */
5734 struct mri_control_info *outer;
5735
5736 /* The type of directive. */
5737 enum mri_control_type type;
5738
5739 /* Whether an ELSE has been in an IF. */
5740 int else_seen;
5741
5742 /* The add or sub statement at the end of a FOR. */
5743 char *incr;
5744
5745 /* The label of the top of a FOR or REPEAT loop. */
5746 char *top;
5747
5748 /* The label to jump to for the next iteration, or the else
5749 expression of a conditional. */
5750 char *next;
5751
5752 /* The label to jump to to break out of the loop, or the label past
5753 the end of a conditional. */
5754 char *bottom;
5755 };
5756
5757 /* The stack of MRI structured control directives. */
5758
5759 static struct mri_control_info *mri_control_stack;
5760
5761 /* The current MRI structured control directive index number, used to
5762 generate label names. */
5763
5764 static int mri_control_index;
5765
5766 /* Assemble an instruction for an MRI structured control directive. */
5767
5768 static void
5769 mri_assemble (char *str)
5770 {
5771 char *s;
5772
5773 /* md_assemble expects the opcode to be in lower case. */
5774 for (s = str; *s != ' ' && *s != '\0'; s++)
5775 *s = TOLOWER (*s);
5776
5777 md_assemble (str);
5778 }
5779
5780 /* Generate a new MRI label structured control directive label name. */
5781
5782 static char *
5783 mri_control_label (void)
5784 {
5785 char *n;
5786
5787 n = (char *) xmalloc (20);
5788 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5789 ++mri_control_index;
5790 return n;
5791 }
5792
5793 /* Create a new MRI structured control directive. */
5794
5795 static struct mri_control_info *
5796 push_mri_control (enum mri_control_type type)
5797 {
5798 struct mri_control_info *n;
5799
5800 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5801
5802 n->type = type;
5803 n->else_seen = 0;
5804 if (type == mri_if || type == mri_while)
5805 n->top = NULL;
5806 else
5807 n->top = mri_control_label ();
5808 n->next = mri_control_label ();
5809 n->bottom = mri_control_label ();
5810
5811 n->outer = mri_control_stack;
5812 mri_control_stack = n;
5813
5814 return n;
5815 }
5816
5817 /* Pop off the stack of MRI structured control directives. */
5818
5819 static void
5820 pop_mri_control (void)
5821 {
5822 struct mri_control_info *n;
5823
5824 n = mri_control_stack;
5825 mri_control_stack = n->outer;
5826 if (n->top != NULL)
5827 free (n->top);
5828 free (n->next);
5829 free (n->bottom);
5830 free (n);
5831 }
5832
5833 /* Recognize a condition code in an MRI structured control expression. */
5834
5835 static int
5836 parse_mri_condition (int *pcc)
5837 {
5838 char c1, c2;
5839
5840 know (*input_line_pointer == '<');
5841
5842 ++input_line_pointer;
5843 c1 = *input_line_pointer++;
5844 c2 = *input_line_pointer++;
5845
5846 if (*input_line_pointer != '>')
5847 {
5848 as_bad (_("syntax error in structured control directive"));
5849 return 0;
5850 }
5851
5852 ++input_line_pointer;
5853 SKIP_WHITESPACE ();
5854
5855 c1 = TOLOWER (c1);
5856 c2 = TOLOWER (c2);
5857
5858 *pcc = (c1 << 8) | c2;
5859
5860 return 1;
5861 }
5862
5863 /* Parse a single operand in an MRI structured control expression. */
5864
5865 static int
5866 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5867 char **rightstart, char **rightstop)
5868 {
5869 char *s;
5870
5871 SKIP_WHITESPACE ();
5872
5873 *pcc = -1;
5874 *leftstart = NULL;
5875 *leftstop = NULL;
5876 *rightstart = NULL;
5877 *rightstop = NULL;
5878
5879 if (*input_line_pointer == '<')
5880 {
5881 /* It's just a condition code. */
5882 return parse_mri_condition (pcc);
5883 }
5884
5885 /* Look ahead for the condition code. */
5886 for (s = input_line_pointer; *s != '\0'; ++s)
5887 {
5888 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5889 break;
5890 }
5891 if (*s == '\0')
5892 {
5893 as_bad (_("missing condition code in structured control directive"));
5894 return 0;
5895 }
5896
5897 *leftstart = input_line_pointer;
5898 *leftstop = s;
5899 if (*leftstop > *leftstart
5900 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5901 --*leftstop;
5902
5903 input_line_pointer = s;
5904 if (! parse_mri_condition (pcc))
5905 return 0;
5906
5907 /* Look ahead for AND or OR or end of line. */
5908 for (s = input_line_pointer; *s != '\0'; ++s)
5909 {
5910 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5911 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5912 ^^^ ^^ */
5913 if ((s == input_line_pointer
5914 || *(s-1) == ' '
5915 || *(s-1) == '\t')
5916 && ((strncasecmp (s, "AND", 3) == 0
5917 && (s[3] == '.' || ! is_part_of_name (s[3])))
5918 || (strncasecmp (s, "OR", 2) == 0
5919 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5920 break;
5921 }
5922
5923 *rightstart = input_line_pointer;
5924 *rightstop = s;
5925 if (*rightstop > *rightstart
5926 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5927 --*rightstop;
5928
5929 input_line_pointer = s;
5930
5931 return 1;
5932 }
5933
5934 #define MCC(b1, b2) (((b1) << 8) | (b2))
5935
5936 /* Swap the sense of a condition. This changes the condition so that
5937 it generates the same result when the operands are swapped. */
5938
5939 static int
5940 swap_mri_condition (int cc)
5941 {
5942 switch (cc)
5943 {
5944 case MCC ('h', 'i'): return MCC ('c', 's');
5945 case MCC ('l', 's'): return MCC ('c', 'c');
5946 /* <HS> is an alias for <CC>. */
5947 case MCC ('h', 's'):
5948 case MCC ('c', 'c'): return MCC ('l', 's');
5949 /* <LO> is an alias for <CS>. */
5950 case MCC ('l', 'o'):
5951 case MCC ('c', 's'): return MCC ('h', 'i');
5952 case MCC ('p', 'l'): return MCC ('m', 'i');
5953 case MCC ('m', 'i'): return MCC ('p', 'l');
5954 case MCC ('g', 'e'): return MCC ('l', 'e');
5955 case MCC ('l', 't'): return MCC ('g', 't');
5956 case MCC ('g', 't'): return MCC ('l', 't');
5957 case MCC ('l', 'e'): return MCC ('g', 'e');
5958 /* Issue a warning for conditions we can not swap. */
5959 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5960 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5961 case MCC ('v', 'c'):
5962 case MCC ('v', 's'):
5963 default :
5964 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5965 (char) (cc >> 8), (char) (cc));
5966 break;
5967 }
5968 return cc;
5969 }
5970
5971 /* Reverse the sense of a condition. */
5972
5973 static int
5974 reverse_mri_condition (int cc)
5975 {
5976 switch (cc)
5977 {
5978 case MCC ('h', 'i'): return MCC ('l', 's');
5979 case MCC ('l', 's'): return MCC ('h', 'i');
5980 /* <HS> is an alias for <CC> */
5981 case MCC ('h', 's'): return MCC ('l', 'o');
5982 case MCC ('c', 'c'): return MCC ('c', 's');
5983 /* <LO> is an alias for <CS> */
5984 case MCC ('l', 'o'): return MCC ('h', 's');
5985 case MCC ('c', 's'): return MCC ('c', 'c');
5986 case MCC ('n', 'e'): return MCC ('e', 'q');
5987 case MCC ('e', 'q'): return MCC ('n', 'e');
5988 case MCC ('v', 'c'): return MCC ('v', 's');
5989 case MCC ('v', 's'): return MCC ('v', 'c');
5990 case MCC ('p', 'l'): return MCC ('m', 'i');
5991 case MCC ('m', 'i'): return MCC ('p', 'l');
5992 case MCC ('g', 'e'): return MCC ('l', 't');
5993 case MCC ('l', 't'): return MCC ('g', 'e');
5994 case MCC ('g', 't'): return MCC ('l', 'e');
5995 case MCC ('l', 'e'): return MCC ('g', 't');
5996 }
5997 return cc;
5998 }
5999
6000 /* Build an MRI structured control expression. This generates test
6001 and branch instructions. It goes to TRUELAB if the condition is
6002 true, and to FALSELAB if the condition is false. Exactly one of
6003 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6004 is the size qualifier for the expression. EXTENT is the size to
6005 use for the branch. */
6006
6007 static void
6008 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6009 char *rightstart, char *rightstop,
6010 const char *truelab, const char *falselab,
6011 int extent)
6012 {
6013 char *buf;
6014 char *s;
6015
6016 if (leftstart != NULL)
6017 {
6018 struct m68k_op leftop, rightop;
6019 char c;
6020
6021 /* Swap the compare operands, if necessary, to produce a legal
6022 m68k compare instruction. Comparing a register operand with
6023 a non-register operand requires the register to be on the
6024 right (cmp, cmpa). Comparing an immediate value with
6025 anything requires the immediate value to be on the left
6026 (cmpi). */
6027
6028 c = *leftstop;
6029 *leftstop = '\0';
6030 (void) m68k_ip_op (leftstart, &leftop);
6031 *leftstop = c;
6032
6033 c = *rightstop;
6034 *rightstop = '\0';
6035 (void) m68k_ip_op (rightstart, &rightop);
6036 *rightstop = c;
6037
6038 if (rightop.mode == IMMED
6039 || ((leftop.mode == DREG || leftop.mode == AREG)
6040 && (rightop.mode != DREG && rightop.mode != AREG)))
6041 {
6042 char *temp;
6043
6044 /* Correct conditional handling:
6045 if #1 <lt> d0 then ;means if (1 < d0)
6046 ...
6047 endi
6048
6049 should assemble to:
6050
6051 cmp #1,d0 if we do *not* swap the operands
6052 bgt true we need the swapped condition!
6053 ble false
6054 true:
6055 ...
6056 false:
6057 */
6058 temp = leftstart;
6059 leftstart = rightstart;
6060 rightstart = temp;
6061 temp = leftstop;
6062 leftstop = rightstop;
6063 rightstop = temp;
6064 }
6065 else
6066 {
6067 cc = swap_mri_condition (cc);
6068 }
6069 }
6070
6071 if (truelab == NULL)
6072 {
6073 cc = reverse_mri_condition (cc);
6074 truelab = falselab;
6075 }
6076
6077 if (leftstart != NULL)
6078 {
6079 buf = (char *) xmalloc (20
6080 + (leftstop - leftstart)
6081 + (rightstop - rightstart));
6082 s = buf;
6083 *s++ = 'c';
6084 *s++ = 'm';
6085 *s++ = 'p';
6086 if (qual != '\0')
6087 *s++ = TOLOWER (qual);
6088 *s++ = ' ';
6089 memcpy (s, leftstart, leftstop - leftstart);
6090 s += leftstop - leftstart;
6091 *s++ = ',';
6092 memcpy (s, rightstart, rightstop - rightstart);
6093 s += rightstop - rightstart;
6094 *s = '\0';
6095 mri_assemble (buf);
6096 free (buf);
6097 }
6098
6099 buf = (char *) xmalloc (20 + strlen (truelab));
6100 s = buf;
6101 *s++ = 'b';
6102 *s++ = cc >> 8;
6103 *s++ = cc & 0xff;
6104 if (extent != '\0')
6105 *s++ = TOLOWER (extent);
6106 *s++ = ' ';
6107 strcpy (s, truelab);
6108 mri_assemble (buf);
6109 free (buf);
6110 }
6111
6112 /* Parse an MRI structured control expression. This generates test
6113 and branch instructions. STOP is where the expression ends. It
6114 goes to TRUELAB if the condition is true, and to FALSELAB if the
6115 condition is false. Exactly one of TRUELAB and FALSELAB will be
6116 NULL, meaning to fall through. QUAL is the size qualifier for the
6117 expression. EXTENT is the size to use for the branch. */
6118
6119 static void
6120 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6121 const char *falselab, int extent)
6122 {
6123 int c;
6124 int cc;
6125 char *leftstart;
6126 char *leftstop;
6127 char *rightstart;
6128 char *rightstop;
6129
6130 c = *stop;
6131 *stop = '\0';
6132
6133 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6134 &rightstart, &rightstop))
6135 {
6136 *stop = c;
6137 return;
6138 }
6139
6140 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6141 {
6142 const char *flab;
6143
6144 if (falselab != NULL)
6145 flab = falselab;
6146 else
6147 flab = mri_control_label ();
6148
6149 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6150 rightstop, (const char *) NULL, flab, extent);
6151
6152 input_line_pointer += 3;
6153 if (*input_line_pointer != '.'
6154 || input_line_pointer[1] == '\0')
6155 qual = '\0';
6156 else
6157 {
6158 qual = input_line_pointer[1];
6159 input_line_pointer += 2;
6160 }
6161
6162 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6163 &rightstart, &rightstop))
6164 {
6165 *stop = c;
6166 return;
6167 }
6168
6169 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6170 rightstop, truelab, falselab, extent);
6171
6172 if (falselab == NULL)
6173 colon (flab);
6174 }
6175 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6176 {
6177 const char *tlab;
6178
6179 if (truelab != NULL)
6180 tlab = truelab;
6181 else
6182 tlab = mri_control_label ();
6183
6184 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6185 rightstop, tlab, (const char *) NULL, extent);
6186
6187 input_line_pointer += 2;
6188 if (*input_line_pointer != '.'
6189 || input_line_pointer[1] == '\0')
6190 qual = '\0';
6191 else
6192 {
6193 qual = input_line_pointer[1];
6194 input_line_pointer += 2;
6195 }
6196
6197 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6198 &rightstart, &rightstop))
6199 {
6200 *stop = c;
6201 return;
6202 }
6203
6204 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6205 rightstop, truelab, falselab, extent);
6206
6207 if (truelab == NULL)
6208 colon (tlab);
6209 }
6210 else
6211 {
6212 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6213 rightstop, truelab, falselab, extent);
6214 }
6215
6216 *stop = c;
6217 if (input_line_pointer != stop)
6218 as_bad (_("syntax error in structured control directive"));
6219 }
6220
6221 /* Handle the MRI IF pseudo-op. This may be a structured control
6222 directive, or it may be a regular assembler conditional, depending
6223 on its operands. */
6224
6225 static void
6226 s_mri_if (int qual)
6227 {
6228 char *s;
6229 int c;
6230 struct mri_control_info *n;
6231
6232 /* A structured control directive must end with THEN with an
6233 optional qualifier. */
6234 s = input_line_pointer;
6235 /* We only accept '*' as introduction of comments if preceded by white space
6236 or at first column of a line (I think this can't actually happen here?)
6237 This is important when assembling:
6238 if d0 <ne> 12(a0,d0*2) then
6239 if d0 <ne> #CONST*20 then. */
6240 while (! (is_end_of_line[(unsigned char) *s]
6241 || (flag_mri
6242 && *s == '*'
6243 && (s == input_line_pointer
6244 || *(s-1) == ' '
6245 || *(s-1) == '\t'))))
6246 ++s;
6247 --s;
6248 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6249 --s;
6250
6251 if (s - input_line_pointer > 1
6252 && s[-1] == '.')
6253 s -= 2;
6254
6255 if (s - input_line_pointer < 3
6256 || strncasecmp (s - 3, "THEN", 4) != 0)
6257 {
6258 if (qual != '\0')
6259 {
6260 as_bad (_("missing then"));
6261 ignore_rest_of_line ();
6262 return;
6263 }
6264
6265 /* It's a conditional. */
6266 s_if (O_ne);
6267 return;
6268 }
6269
6270 /* Since this might be a conditional if, this pseudo-op will be
6271 called even if we are supported to be ignoring input. Double
6272 check now. Clobber *input_line_pointer so that ignore_input
6273 thinks that this is not a special pseudo-op. */
6274 c = *input_line_pointer;
6275 *input_line_pointer = 0;
6276 if (ignore_input ())
6277 {
6278 *input_line_pointer = c;
6279 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6280 ++input_line_pointer;
6281 demand_empty_rest_of_line ();
6282 return;
6283 }
6284 *input_line_pointer = c;
6285
6286 n = push_mri_control (mri_if);
6287
6288 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6289 n->next, s[1] == '.' ? s[2] : '\0');
6290
6291 if (s[1] == '.')
6292 input_line_pointer = s + 3;
6293 else
6294 input_line_pointer = s + 1;
6295
6296 if (flag_mri)
6297 {
6298 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6299 ++input_line_pointer;
6300 }
6301
6302 demand_empty_rest_of_line ();
6303 }
6304
6305 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6306 structured IF, associate the ELSE with the IF. Otherwise, assume
6307 it is a conditional else. */
6308
6309 static void
6310 s_mri_else (int qual)
6311 {
6312 int c;
6313 char *buf;
6314 char q[2];
6315
6316 if (qual == '\0'
6317 && (mri_control_stack == NULL
6318 || mri_control_stack->type != mri_if
6319 || mri_control_stack->else_seen))
6320 {
6321 s_else (0);
6322 return;
6323 }
6324
6325 c = *input_line_pointer;
6326 *input_line_pointer = 0;
6327 if (ignore_input ())
6328 {
6329 *input_line_pointer = c;
6330 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6331 ++input_line_pointer;
6332 demand_empty_rest_of_line ();
6333 return;
6334 }
6335 *input_line_pointer = c;
6336
6337 if (mri_control_stack == NULL
6338 || mri_control_stack->type != mri_if
6339 || mri_control_stack->else_seen)
6340 {
6341 as_bad (_("else without matching if"));
6342 ignore_rest_of_line ();
6343 return;
6344 }
6345
6346 mri_control_stack->else_seen = 1;
6347
6348 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6349 q[0] = TOLOWER (qual);
6350 q[1] = '\0';
6351 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6352 mri_assemble (buf);
6353 free (buf);
6354
6355 colon (mri_control_stack->next);
6356
6357 if (flag_mri)
6358 {
6359 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6360 ++input_line_pointer;
6361 }
6362
6363 demand_empty_rest_of_line ();
6364 }
6365
6366 /* Handle the MRI ENDI pseudo-op. */
6367
6368 static void
6369 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6370 {
6371 if (mri_control_stack == NULL
6372 || mri_control_stack->type != mri_if)
6373 {
6374 as_bad (_("endi without matching if"));
6375 ignore_rest_of_line ();
6376 return;
6377 }
6378
6379 /* ignore_input will not return true for ENDI, so we don't need to
6380 worry about checking it again here. */
6381
6382 if (! mri_control_stack->else_seen)
6383 colon (mri_control_stack->next);
6384 colon (mri_control_stack->bottom);
6385
6386 pop_mri_control ();
6387
6388 if (flag_mri)
6389 {
6390 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6391 ++input_line_pointer;
6392 }
6393
6394 demand_empty_rest_of_line ();
6395 }
6396
6397 /* Handle the MRI BREAK pseudo-op. */
6398
6399 static void
6400 s_mri_break (int extent)
6401 {
6402 struct mri_control_info *n;
6403 char *buf;
6404 char ex[2];
6405
6406 n = mri_control_stack;
6407 while (n != NULL
6408 && n->type != mri_for
6409 && n->type != mri_repeat
6410 && n->type != mri_while)
6411 n = n->outer;
6412 if (n == NULL)
6413 {
6414 as_bad (_("break outside of structured loop"));
6415 ignore_rest_of_line ();
6416 return;
6417 }
6418
6419 buf = (char *) xmalloc (20 + strlen (n->bottom));
6420 ex[0] = TOLOWER (extent);
6421 ex[1] = '\0';
6422 sprintf (buf, "bra%s %s", ex, n->bottom);
6423 mri_assemble (buf);
6424 free (buf);
6425
6426 if (flag_mri)
6427 {
6428 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6429 ++input_line_pointer;
6430 }
6431
6432 demand_empty_rest_of_line ();
6433 }
6434
6435 /* Handle the MRI NEXT pseudo-op. */
6436
6437 static void
6438 s_mri_next (int extent)
6439 {
6440 struct mri_control_info *n;
6441 char *buf;
6442 char ex[2];
6443
6444 n = mri_control_stack;
6445 while (n != NULL
6446 && n->type != mri_for
6447 && n->type != mri_repeat
6448 && n->type != mri_while)
6449 n = n->outer;
6450 if (n == NULL)
6451 {
6452 as_bad (_("next outside of structured loop"));
6453 ignore_rest_of_line ();
6454 return;
6455 }
6456
6457 buf = (char *) xmalloc (20 + strlen (n->next));
6458 ex[0] = TOLOWER (extent);
6459 ex[1] = '\0';
6460 sprintf (buf, "bra%s %s", ex, n->next);
6461 mri_assemble (buf);
6462 free (buf);
6463
6464 if (flag_mri)
6465 {
6466 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6467 ++input_line_pointer;
6468 }
6469
6470 demand_empty_rest_of_line ();
6471 }
6472
6473 /* Handle the MRI FOR pseudo-op. */
6474
6475 static void
6476 s_mri_for (int qual)
6477 {
6478 const char *varstart, *varstop;
6479 const char *initstart, *initstop;
6480 const char *endstart, *endstop;
6481 const char *bystart, *bystop;
6482 int up;
6483 int by;
6484 int extent;
6485 struct mri_control_info *n;
6486 char *buf;
6487 char *s;
6488 char ex[2];
6489
6490 /* The syntax is
6491 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6492 */
6493
6494 SKIP_WHITESPACE ();
6495 varstart = input_line_pointer;
6496
6497 /* Look for the '='. */
6498 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6499 && *input_line_pointer != '=')
6500 ++input_line_pointer;
6501 if (*input_line_pointer != '=')
6502 {
6503 as_bad (_("missing ="));
6504 ignore_rest_of_line ();
6505 return;
6506 }
6507
6508 varstop = input_line_pointer;
6509 if (varstop > varstart
6510 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6511 --varstop;
6512
6513 ++input_line_pointer;
6514
6515 initstart = input_line_pointer;
6516
6517 /* Look for TO or DOWNTO. */
6518 up = 1;
6519 initstop = NULL;
6520 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6521 {
6522 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6523 && ! is_part_of_name (input_line_pointer[2]))
6524 {
6525 initstop = input_line_pointer;
6526 input_line_pointer += 2;
6527 break;
6528 }
6529 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6530 && ! is_part_of_name (input_line_pointer[6]))
6531 {
6532 initstop = input_line_pointer;
6533 up = 0;
6534 input_line_pointer += 6;
6535 break;
6536 }
6537 ++input_line_pointer;
6538 }
6539 if (initstop == NULL)
6540 {
6541 as_bad (_("missing to or downto"));
6542 ignore_rest_of_line ();
6543 return;
6544 }
6545 if (initstop > initstart
6546 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6547 --initstop;
6548
6549 SKIP_WHITESPACE ();
6550 endstart = input_line_pointer;
6551
6552 /* Look for BY or DO. */
6553 by = 0;
6554 endstop = NULL;
6555 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6556 {
6557 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6558 && ! is_part_of_name (input_line_pointer[2]))
6559 {
6560 endstop = input_line_pointer;
6561 by = 1;
6562 input_line_pointer += 2;
6563 break;
6564 }
6565 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6566 && (input_line_pointer[2] == '.'
6567 || ! is_part_of_name (input_line_pointer[2])))
6568 {
6569 endstop = input_line_pointer;
6570 input_line_pointer += 2;
6571 break;
6572 }
6573 ++input_line_pointer;
6574 }
6575 if (endstop == NULL)
6576 {
6577 as_bad (_("missing do"));
6578 ignore_rest_of_line ();
6579 return;
6580 }
6581 if (endstop > endstart
6582 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6583 --endstop;
6584
6585 if (! by)
6586 {
6587 bystart = "#1";
6588 bystop = bystart + 2;
6589 }
6590 else
6591 {
6592 SKIP_WHITESPACE ();
6593 bystart = input_line_pointer;
6594
6595 /* Look for DO. */
6596 bystop = NULL;
6597 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6598 {
6599 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6600 && (input_line_pointer[2] == '.'
6601 || ! is_part_of_name (input_line_pointer[2])))
6602 {
6603 bystop = input_line_pointer;
6604 input_line_pointer += 2;
6605 break;
6606 }
6607 ++input_line_pointer;
6608 }
6609 if (bystop == NULL)
6610 {
6611 as_bad (_("missing do"));
6612 ignore_rest_of_line ();
6613 return;
6614 }
6615 if (bystop > bystart
6616 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6617 --bystop;
6618 }
6619
6620 if (*input_line_pointer != '.')
6621 extent = '\0';
6622 else
6623 {
6624 extent = input_line_pointer[1];
6625 input_line_pointer += 2;
6626 }
6627
6628 /* We have fully parsed the FOR operands. Now build the loop. */
6629 n = push_mri_control (mri_for);
6630
6631 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6632
6633 /* Move init,var. */
6634 s = buf;
6635 *s++ = 'm';
6636 *s++ = 'o';
6637 *s++ = 'v';
6638 *s++ = 'e';
6639 if (qual != '\0')
6640 *s++ = TOLOWER (qual);
6641 *s++ = ' ';
6642 memcpy (s, initstart, initstop - initstart);
6643 s += initstop - initstart;
6644 *s++ = ',';
6645 memcpy (s, varstart, varstop - varstart);
6646 s += varstop - varstart;
6647 *s = '\0';
6648 mri_assemble (buf);
6649
6650 colon (n->top);
6651
6652 /* cmp end,var. */
6653 s = buf;
6654 *s++ = 'c';
6655 *s++ = 'm';
6656 *s++ = 'p';
6657 if (qual != '\0')
6658 *s++ = TOLOWER (qual);
6659 *s++ = ' ';
6660 memcpy (s, endstart, endstop - endstart);
6661 s += endstop - endstart;
6662 *s++ = ',';
6663 memcpy (s, varstart, varstop - varstart);
6664 s += varstop - varstart;
6665 *s = '\0';
6666 mri_assemble (buf);
6667
6668 /* bcc bottom. */
6669 ex[0] = TOLOWER (extent);
6670 ex[1] = '\0';
6671 if (up)
6672 sprintf (buf, "blt%s %s", ex, n->bottom);
6673 else
6674 sprintf (buf, "bgt%s %s", ex, n->bottom);
6675 mri_assemble (buf);
6676
6677 /* Put together the add or sub instruction used by ENDF. */
6678 s = buf;
6679 if (up)
6680 strcpy (s, "add");
6681 else
6682 strcpy (s, "sub");
6683 s += 3;
6684 if (qual != '\0')
6685 *s++ = TOLOWER (qual);
6686 *s++ = ' ';
6687 memcpy (s, bystart, bystop - bystart);
6688 s += bystop - bystart;
6689 *s++ = ',';
6690 memcpy (s, varstart, varstop - varstart);
6691 s += varstop - varstart;
6692 *s = '\0';
6693 n->incr = buf;
6694
6695 if (flag_mri)
6696 {
6697 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6698 ++input_line_pointer;
6699 }
6700
6701 demand_empty_rest_of_line ();
6702 }
6703
6704 /* Handle the MRI ENDF pseudo-op. */
6705
6706 static void
6707 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6708 {
6709 if (mri_control_stack == NULL
6710 || mri_control_stack->type != mri_for)
6711 {
6712 as_bad (_("endf without for"));
6713 ignore_rest_of_line ();
6714 return;
6715 }
6716
6717 colon (mri_control_stack->next);
6718
6719 mri_assemble (mri_control_stack->incr);
6720
6721 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6722 mri_assemble (mri_control_stack->incr);
6723
6724 free (mri_control_stack->incr);
6725
6726 colon (mri_control_stack->bottom);
6727
6728 pop_mri_control ();
6729
6730 if (flag_mri)
6731 {
6732 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6733 ++input_line_pointer;
6734 }
6735
6736 demand_empty_rest_of_line ();
6737 }
6738
6739 /* Handle the MRI REPEAT pseudo-op. */
6740
6741 static void
6742 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6743 {
6744 struct mri_control_info *n;
6745
6746 n = push_mri_control (mri_repeat);
6747 colon (n->top);
6748 if (flag_mri)
6749 {
6750 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6751 ++input_line_pointer;
6752 }
6753 demand_empty_rest_of_line ();
6754 }
6755
6756 /* Handle the MRI UNTIL pseudo-op. */
6757
6758 static void
6759 s_mri_until (int qual)
6760 {
6761 char *s;
6762
6763 if (mri_control_stack == NULL
6764 || mri_control_stack->type != mri_repeat)
6765 {
6766 as_bad (_("until without repeat"));
6767 ignore_rest_of_line ();
6768 return;
6769 }
6770
6771 colon (mri_control_stack->next);
6772
6773 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6774 ;
6775
6776 parse_mri_control_expression (s, qual, (const char *) NULL,
6777 mri_control_stack->top, '\0');
6778
6779 colon (mri_control_stack->bottom);
6780
6781 input_line_pointer = s;
6782
6783 pop_mri_control ();
6784
6785 if (flag_mri)
6786 {
6787 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6788 ++input_line_pointer;
6789 }
6790
6791 demand_empty_rest_of_line ();
6792 }
6793
6794 /* Handle the MRI WHILE pseudo-op. */
6795
6796 static void
6797 s_mri_while (int qual)
6798 {
6799 char *s;
6800
6801 struct mri_control_info *n;
6802
6803 s = input_line_pointer;
6804 /* We only accept '*' as introduction of comments if preceded by white space
6805 or at first column of a line (I think this can't actually happen here?)
6806 This is important when assembling:
6807 while d0 <ne> 12(a0,d0*2) do
6808 while d0 <ne> #CONST*20 do. */
6809 while (! (is_end_of_line[(unsigned char) *s]
6810 || (flag_mri
6811 && *s == '*'
6812 && (s == input_line_pointer
6813 || *(s-1) == ' '
6814 || *(s-1) == '\t'))))
6815 s++;
6816 --s;
6817 while (*s == ' ' || *s == '\t')
6818 --s;
6819 if (s - input_line_pointer > 1
6820 && s[-1] == '.')
6821 s -= 2;
6822 if (s - input_line_pointer < 2
6823 || strncasecmp (s - 1, "DO", 2) != 0)
6824 {
6825 as_bad (_("missing do"));
6826 ignore_rest_of_line ();
6827 return;
6828 }
6829
6830 n = push_mri_control (mri_while);
6831
6832 colon (n->next);
6833
6834 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6835 s[1] == '.' ? s[2] : '\0');
6836
6837 input_line_pointer = s + 1;
6838 if (*input_line_pointer == '.')
6839 input_line_pointer += 2;
6840
6841 if (flag_mri)
6842 {
6843 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6844 ++input_line_pointer;
6845 }
6846
6847 demand_empty_rest_of_line ();
6848 }
6849
6850 /* Handle the MRI ENDW pseudo-op. */
6851
6852 static void
6853 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6854 {
6855 char *buf;
6856
6857 if (mri_control_stack == NULL
6858 || mri_control_stack->type != mri_while)
6859 {
6860 as_bad (_("endw without while"));
6861 ignore_rest_of_line ();
6862 return;
6863 }
6864
6865 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6866 sprintf (buf, "bra %s", mri_control_stack->next);
6867 mri_assemble (buf);
6868 free (buf);
6869
6870 colon (mri_control_stack->bottom);
6871
6872 pop_mri_control ();
6873
6874 if (flag_mri)
6875 {
6876 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6877 ++input_line_pointer;
6878 }
6879
6880 demand_empty_rest_of_line ();
6881 }
6882 \f
6883 /* Parse a .cpu directive. */
6884
6885 static void
6886 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6887 {
6888 char saved_char;
6889 char *name;
6890
6891 if (initialized)
6892 {
6893 as_bad (_("already assembled instructions"));
6894 ignore_rest_of_line ();
6895 return;
6896 }
6897
6898 name = input_line_pointer;
6899 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6900 input_line_pointer++;
6901 saved_char = *input_line_pointer;
6902 *input_line_pointer = 0;
6903
6904 m68k_set_cpu (name, 1, 0);
6905
6906 *input_line_pointer = saved_char;
6907 demand_empty_rest_of_line ();
6908 return;
6909 }
6910
6911 /* Parse a .arch directive. */
6912
6913 static void
6914 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6915 {
6916 char saved_char;
6917 char *name;
6918
6919 if (initialized)
6920 {
6921 as_bad (_("already assembled instructions"));
6922 ignore_rest_of_line ();
6923 return;
6924 }
6925
6926 name = input_line_pointer;
6927 while (*input_line_pointer && *input_line_pointer != ','
6928 && !ISSPACE (*input_line_pointer))
6929 input_line_pointer++;
6930 saved_char = *input_line_pointer;
6931 *input_line_pointer = 0;
6932
6933 if (m68k_set_arch (name, 1, 0))
6934 {
6935 /* Scan extensions. */
6936 do
6937 {
6938 *input_line_pointer++ = saved_char;
6939 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6940 break;
6941 name = input_line_pointer;
6942 while (*input_line_pointer && *input_line_pointer != ','
6943 && !ISSPACE (*input_line_pointer))
6944 input_line_pointer++;
6945 saved_char = *input_line_pointer;
6946 *input_line_pointer = 0;
6947 }
6948 while (m68k_set_extension (name, 1, 0));
6949 }
6950
6951 *input_line_pointer = saved_char;
6952 demand_empty_rest_of_line ();
6953 return;
6954 }
6955 \f
6956 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
6957 if none is found, the caller is responsible for emitting an error
6958 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
6959 cpu name, if it begins with a '6' (possibly skipping an intervening
6960 'c'. We also allow a 'c' in the same place. if NEGATED is
6961 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
6962 the option is indeed negated. */
6963
6964 static const struct m68k_cpu *
6965 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
6966 int allow_m, int *negated)
6967 {
6968 /* allow negated value? */
6969 if (negated)
6970 {
6971 *negated = 0;
6972
6973 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6974 {
6975 arg += 3;
6976 *negated = 1;
6977 }
6978 }
6979
6980 /* Remove 'm' or 'mc' prefix from 68k variants. */
6981 if (allow_m)
6982 {
6983 if (arg[0] == 'm')
6984 {
6985 if (arg[1] == '6')
6986 arg += 1;
6987 else if (arg[1] == 'c' && arg[2] == '6')
6988 arg += 2;
6989 }
6990 }
6991 else if (arg[0] == 'c' && arg[1] == '6')
6992 arg += 1;
6993
6994 for (; table->name; table++)
6995 if (!strcmp (arg, table->name))
6996 {
6997 if (table->alias < -1 || table->alias > 1)
6998 as_bad (_("`%s' is deprecated, use `%s'"),
6999 table->name, table[table->alias < 0 ? 1 : -1].name);
7000 return table;
7001 }
7002 return 0;
7003 }
7004
7005 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7006
7007 static int
7008 m68k_set_cpu (char const *name, int allow_m, int silent)
7009 {
7010 const struct m68k_cpu *cpu;
7011
7012 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7013
7014 if (!cpu)
7015 {
7016 if (!silent)
7017 as_bad (_("cpu `%s' unrecognized"), name);
7018 return 0;
7019 }
7020
7021 if (selected_cpu && selected_cpu != cpu)
7022 {
7023 as_bad (_("already selected `%s' processor"),
7024 selected_cpu->name);
7025 return 0;
7026 }
7027 selected_cpu = cpu;
7028 return 1;
7029 }
7030
7031 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7032
7033 static int
7034 m68k_set_arch (char const *name, int allow_m, int silent)
7035 {
7036 const struct m68k_cpu *arch;
7037
7038 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7039
7040 if (!arch)
7041 {
7042 if (!silent)
7043 as_bad (_("architecture `%s' unrecognized"), name);
7044 return 0;
7045 }
7046
7047 if (selected_arch && selected_arch != arch)
7048 {
7049 as_bad (_("already selected `%s' architecture"),
7050 selected_arch->name);
7051 return 0;
7052 }
7053
7054 selected_arch = arch;
7055 return 1;
7056 }
7057
7058 /* Set the architecture extension, issuing errors if it is
7059 unrecognized, or invalid */
7060
7061 static int
7062 m68k_set_extension (char const *name, int allow_m, int silent)
7063 {
7064 int negated;
7065 const struct m68k_cpu *ext;
7066
7067 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7068
7069 if (!ext)
7070 {
7071 if (!silent)
7072 as_bad (_("extension `%s' unrecognized"), name);
7073 return 0;
7074 }
7075
7076 if (negated)
7077 not_current_architecture |= ext->arch;
7078 else
7079 current_architecture |= ext->arch;
7080 return 1;
7081 }
7082
7083 /* md_parse_option
7084 Invocation line includes a switch not recognized by the base assembler.
7085 */
7086
7087 #ifdef OBJ_ELF
7088 const char *md_shortopts = "lSA:m:kQ:V";
7089 #else
7090 const char *md_shortopts = "lSA:m:k";
7091 #endif
7092
7093 struct option md_longopts[] = {
7094 #define OPTION_PIC (OPTION_MD_BASE)
7095 {"pic", no_argument, NULL, OPTION_PIC},
7096 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7097 {"register-prefix-optional", no_argument, NULL,
7098 OPTION_REGISTER_PREFIX_OPTIONAL},
7099 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7100 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7101 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7102 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7103 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7104 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7105 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7106 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7107 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7108 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7109 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7110 {"pcrel", no_argument, NULL, OPTION_PCREL},
7111 {NULL, no_argument, NULL, 0}
7112 };
7113 size_t md_longopts_size = sizeof (md_longopts);
7114
7115 int
7116 md_parse_option (int c, char *arg)
7117 {
7118 switch (c)
7119 {
7120 case 'l': /* -l means keep external to 2 bit offset
7121 rather than 16 bit one. */
7122 flag_short_refs = 1;
7123 break;
7124
7125 case 'S': /* -S means that jbsr's always turn into
7126 jsr's. */
7127 flag_long_jumps = 1;
7128 break;
7129
7130 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7131 branches into absolute jumps. */
7132 flag_keep_pcrel = 1;
7133 break;
7134
7135 case OPTION_PIC:
7136 case 'k':
7137 flag_want_pic = 1;
7138 break; /* -pic, Position Independent Code. */
7139
7140 case OPTION_REGISTER_PREFIX_OPTIONAL:
7141 flag_reg_prefix_optional = 1;
7142 reg_prefix_optional_seen = 1;
7143 break;
7144
7145 /* -V: SVR4 argument to print version ID. */
7146 case 'V':
7147 print_version_id ();
7148 break;
7149
7150 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7151 should be emitted or not. FIXME: Not implemented. */
7152 case 'Q':
7153 break;
7154
7155 case OPTION_BITWISE_OR:
7156 {
7157 char *n, *t;
7158 const char *s;
7159
7160 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7161 t = n;
7162 for (s = m68k_comment_chars; *s != '\0'; s++)
7163 if (*s != '|')
7164 *t++ = *s;
7165 *t = '\0';
7166 m68k_comment_chars = n;
7167 }
7168 break;
7169
7170 case OPTION_BASE_SIZE_DEFAULT_16:
7171 m68k_index_width_default = SIZE_WORD;
7172 break;
7173
7174 case OPTION_BASE_SIZE_DEFAULT_32:
7175 m68k_index_width_default = SIZE_LONG;
7176 break;
7177
7178 case OPTION_DISP_SIZE_DEFAULT_16:
7179 m68k_rel32 = 0;
7180 m68k_rel32_from_cmdline = 1;
7181 break;
7182
7183 case OPTION_DISP_SIZE_DEFAULT_32:
7184 m68k_rel32 = 1;
7185 m68k_rel32_from_cmdline = 1;
7186 break;
7187
7188 case 'A':
7189 #if WARN_DEPRECATED
7190 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7191 arg, arg));
7192 #endif
7193 /* Intentional fall-through. */
7194 case 'm':
7195 if (!strncmp (arg, "arch=", 5))
7196 m68k_set_arch (arg + 5, 1, 0);
7197 else if (!strncmp (arg, "cpu=", 4))
7198 m68k_set_cpu (arg + 4, 1, 0);
7199 else if (m68k_set_extension (arg, 0, 1))
7200 ;
7201 else if (m68k_set_arch (arg, 0, 1))
7202 ;
7203 else if (m68k_set_cpu (arg, 0, 1))
7204 ;
7205 else
7206 return 0;
7207 break;
7208
7209 default:
7210 return 0;
7211 }
7212
7213 return 1;
7214 }
7215
7216 /* Setup tables from the selected arch and/or cpu */
7217
7218 static void
7219 m68k_init_arch (void)
7220 {
7221 if (not_current_architecture & current_architecture)
7222 {
7223 as_bad (_("architecture features both enabled and disabled"));
7224 not_current_architecture &= ~current_architecture;
7225 }
7226 if (selected_arch)
7227 {
7228 current_architecture |= selected_arch->arch;
7229 control_regs = selected_arch->control_regs;
7230 }
7231 else
7232 current_architecture |= selected_cpu->arch;
7233
7234 current_architecture &= ~not_current_architecture;
7235
7236 if (selected_cpu)
7237 {
7238 control_regs = selected_cpu->control_regs;
7239 if (current_architecture & ~selected_cpu->arch)
7240 {
7241 as_bad (_("selected processor does not have all features of selected architecture"));
7242 current_architecture
7243 = selected_cpu->arch & ~not_current_architecture;
7244 }
7245 }
7246
7247 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7248 {
7249 /* Determine which float is really meant. */
7250 if (current_architecture & (m68k_mask & ~m68881))
7251 current_architecture ^= cfloat;
7252 else
7253 current_architecture ^= m68881;
7254 }
7255
7256 if ((current_architecture & m68k_mask)
7257 && (current_architecture & ~m68k_mask))
7258 {
7259 as_bad (_ ("m68k and cf features both selected"));
7260 if (current_architecture & m68k_mask)
7261 current_architecture &= m68k_mask;
7262 else
7263 current_architecture &= ~m68k_mask;
7264 }
7265
7266 /* Permit m68881 specification with all cpus; those that can't work
7267 with a coprocessor could be doing emulation. */
7268 if (current_architecture & m68851)
7269 {
7270 if (current_architecture & m68040)
7271 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7272 }
7273 /* What other incompatibilities could we check for? */
7274
7275 if (cpu_of_arch (current_architecture) < m68020
7276 || arch_coldfire_p (current_architecture))
7277 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7278
7279 initialized = 1;
7280 }
7281
7282 void
7283 md_show_usage (FILE *stream)
7284 {
7285 const char *default_cpu = TARGET_CPU;
7286 int i;
7287 unsigned int default_arch;
7288
7289 /* Get the canonical name for the default target CPU. */
7290 if (*default_cpu == 'm')
7291 default_cpu++;
7292 for (i = 0; m68k_cpus[i].name; i++)
7293 {
7294 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7295 {
7296 default_arch = m68k_cpus[i].arch;
7297 while (m68k_cpus[i].alias > 0)
7298 i--;
7299 while (m68k_cpus[i].alias < 0)
7300 i++;
7301 default_cpu = m68k_cpus[i].name;
7302 }
7303 }
7304
7305 fprintf (stream, _("\
7306 -march=<arch> set architecture\n\
7307 -mcpu=<cpu> set cpu [default %s]\n\
7308 "), default_cpu);
7309 for (i = 0; m68k_extensions[i].name; i++)
7310 fprintf (stream, _("\
7311 -m[no-]%-16s enable/disable%s architecture extension\n\
7312 "), m68k_extensions[i].name,
7313 m68k_extensions[i].alias > 0 ? " ColdFire"
7314 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7315
7316 fprintf (stream, _("\
7317 -l use 1 word for refs to undefined symbols [default 2]\n\
7318 -pic, -k generate position independent code\n\
7319 -S turn jbsr into jsr\n\
7320 --pcrel never turn PC-relative branches into absolute jumps\n\
7321 --register-prefix-optional\n\
7322 recognize register names without prefix character\n\
7323 --bitwise-or do not treat `|' as a comment character\n\
7324 --base-size-default-16 base reg without size is 16 bits\n\
7325 --base-size-default-32 base reg without size is 32 bits (default)\n\
7326 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7327 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7328 "));
7329
7330 fprintf (stream, _("Architecture variants are: "));
7331 for (i = 0; m68k_archs[i].name; i++)
7332 {
7333 if (i)
7334 fprintf (stream, " | ");
7335 fprintf (stream, m68k_archs[i].name);
7336 }
7337 fprintf (stream, "\n");
7338
7339 fprintf (stream, _("Processor variants are: "));
7340 for (i = 0; m68k_cpus[i].name; i++)
7341 {
7342 if (i)
7343 fprintf (stream, " | ");
7344 fprintf (stream, m68k_cpus[i].name);
7345 }
7346 fprintf (stream, _("\n"));
7347 }
7348 \f
7349 #ifdef TEST2
7350
7351 /* TEST2: Test md_assemble() */
7352 /* Warning, this routine probably doesn't work anymore. */
7353 int
7354 main (void)
7355 {
7356 struct m68k_it the_ins;
7357 char buf[120];
7358 char *cp;
7359 int n;
7360
7361 m68k_ip_begin ();
7362 for (;;)
7363 {
7364 if (!gets (buf) || !*buf)
7365 break;
7366 if (buf[0] == '|' || buf[1] == '.')
7367 continue;
7368 for (cp = buf; *cp; cp++)
7369 if (*cp == '\t')
7370 *cp = ' ';
7371 if (is_label (buf))
7372 continue;
7373 memset (&the_ins, '\0', sizeof (the_ins));
7374 m68k_ip (&the_ins, buf);
7375 if (the_ins.error)
7376 {
7377 printf (_("Error %s in %s\n"), the_ins.error, buf);
7378 }
7379 else
7380 {
7381 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7382 for (n = 0; n < the_ins.numo; n++)
7383 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7384 printf (" ");
7385 print_the_insn (&the_ins.opcode[0], stdout);
7386 (void) putchar ('\n');
7387 }
7388 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7389 {
7390 if (the_ins.operands[n].error)
7391 {
7392 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7393 continue;
7394 }
7395 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7396 the_ins.operands[n].reg);
7397 if (the_ins.operands[n].b_const)
7398 printf ("Constant: '%.*s', ",
7399 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7400 the_ins.operands[n].b_const);
7401 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7402 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7403 if (the_ins.operands[n].b_iadd)
7404 printf ("Iadd: '%.*s',",
7405 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7406 the_ins.operands[n].b_iadd);
7407 putchar ('\n');
7408 }
7409 }
7410 m68k_ip_end ();
7411 return 0;
7412 }
7413
7414 int
7415 is_label (char *str)
7416 {
7417 while (*str == ' ')
7418 str++;
7419 while (*str && *str != ' ')
7420 str++;
7421 if (str[-1] == ':' || str[1] == '=')
7422 return 1;
7423 return 0;
7424 }
7425
7426 #endif
7427
7428 /* Possible states for relaxation:
7429
7430 0 0 branch offset byte (bra, etc)
7431 0 1 word
7432 0 2 long
7433
7434 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7435 1 1 word
7436 1 2 long
7437
7438 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7439 2 1 word-long
7440 2 2 long-word
7441 2 3 long-long
7442
7443 */
7444
7445 /* We have no need to default values of symbols. */
7446
7447 symbolS *
7448 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7449 {
7450 return 0;
7451 }
7452
7453 /* Round up a section size to the appropriate boundary. */
7454 valueT
7455 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7456 {
7457 #ifdef OBJ_AOUT
7458 /* For a.out, force the section size to be aligned. If we don't do
7459 this, BFD will align it for us, but it will not write out the
7460 final bytes of the section. This may be a bug in BFD, but it is
7461 easier to fix it here since that is how the other a.out targets
7462 work. */
7463 int align;
7464
7465 align = bfd_get_section_alignment (stdoutput, segment);
7466 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7467 #endif
7468
7469 return size;
7470 }
7471
7472 /* Exactly what point is a PC-relative offset relative TO?
7473 On the 68k, it is relative to the address of the first extension
7474 word. The difference between the addresses of the offset and the
7475 first extension word is stored in fx_pcrel_adjust. */
7476 long
7477 md_pcrel_from (fixS *fixP)
7478 {
7479 int adjust;
7480
7481 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7482 sign extend the value here. */
7483 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7484 if (adjust == 64)
7485 adjust = -1;
7486 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7487 }
7488
7489 #ifdef OBJ_ELF
7490 void
7491 m68k_elf_final_processing (void)
7492 {
7493 unsigned flags = 0;
7494
7495 if (arch_coldfire_fpu (current_architecture))
7496 flags |= EF_M68K_CFV4E;
7497 /* Set file-specific flags if this is a cpu32 processor. */
7498 if (cpu_of_arch (current_architecture) & cpu32)
7499 flags |= EF_M68K_CPU32;
7500 else if ((cpu_of_arch (current_architecture) & m68000up)
7501 && !(cpu_of_arch (current_architecture) & m68020up))
7502 flags |= EF_M68K_M68000;
7503
7504 if (current_architecture & mcfisa_a)
7505 {
7506 static const unsigned isa_features[][2] =
7507 {
7508 {EF_M68K_ISA_A_NODIV, mcfisa_a},
7509 {EF_M68K_ISA_A, mcfisa_a|mcfhwdiv},
7510 {EF_M68K_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7511 {EF_M68K_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7512 {EF_M68K_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7513 {0,0},
7514 };
7515 static const unsigned mac_features[][2] =
7516 {
7517 {EF_M68K_MAC, mcfmac},
7518 {EF_M68K_EMAC, mcfemac},
7519 {0,0},
7520 };
7521 unsigned ix;
7522 unsigned pattern;
7523
7524 pattern = (current_architecture
7525 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7526 for (ix = 0; isa_features[ix][1]; ix++)
7527 {
7528 if (pattern == isa_features[ix][1])
7529 {
7530 flags |= isa_features[ix][0];
7531 break;
7532 }
7533 }
7534 if (!isa_features[ix][1])
7535 {
7536 cf_bad:
7537 as_warn (_("Not a defined coldfire architecture"));
7538 }
7539 else
7540 {
7541 if (current_architecture & cfloat)
7542 flags |= EF_M68K_FLOAT | EF_M68K_CFV4E;
7543
7544 pattern = current_architecture & (mcfmac|mcfemac);
7545 if (pattern)
7546 {
7547 for (ix = 0; mac_features[ix][1]; ix++)
7548 {
7549 if (pattern == mac_features[ix][1])
7550 {
7551 flags |= mac_features[ix][0];
7552 break;
7553 }
7554 }
7555 if (!mac_features[ix][1])
7556 goto cf_bad;
7557 }
7558 }
7559 }
7560 elf_elfheader (stdoutput)->e_flags |= flags;
7561 }
7562 #endif
7563
7564 int
7565 tc_m68k_regname_to_dw2regnum (const char *regname)
7566 {
7567 unsigned int regnum;
7568 static const char *const regnames[] =
7569 {
7570 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7571 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7572 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7573 "pc"
7574 };
7575
7576 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7577 if (strcmp (regname, regnames[regnum]) == 0)
7578 return regnum;
7579
7580 return -1;
7581 }
7582
7583 void
7584 tc_m68k_frame_initial_instructions (void)
7585 {
7586 static int sp_regno = -1;
7587
7588 if (sp_regno < 0)
7589 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7590
7591 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7592 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7593 }
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