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1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf51qe_ctrl[] = {
180 VBR,
181 0
182 };
183 static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
185 0
186 };
187 static const enum m68k_register mcf5208_ctrl[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
189 0
190 };
191 static const enum m68k_register mcf5210a_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
193 0
194 };
195 static const enum m68k_register mcf5213_ctrl[] = {
196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
197 0
198 };
199 static const enum m68k_register mcf5216_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf52235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5225_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5235_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
217 0
218 };
219 static const enum m68k_register mcf5249_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
221 0
222 };
223 static const enum m68k_register mcf5250_ctrl[] = {
224 VBR,
225 0
226 };
227 static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
229 0
230 };
231 static const enum m68k_register mcf5271_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
233 0
234 };
235 static const enum m68k_register mcf5272_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
237 0
238 };
239 static const enum m68k_register mcf5275_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5282_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
245 0
246 };
247 static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
249 0
250 };
251 static const enum m68k_register mcf5329_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcf5373_ctrl[] = {
256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
257 0
258 };
259 static const enum m68k_register mcfv4e_ctrl[] = {
260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
262 MBAR, SECMBAR,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
268 /* Legacy names */
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
273 0
274 };
275 static const enum m68k_register mcf5407_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
277 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
278 /* Legacy names */
279 TC /* ASID */,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
282 0
283 };
284 static const enum m68k_register mcf54455_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR1, MBAR,
287 /* Legacy names */
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
291 0
292 };
293 static const enum m68k_register mcf5475_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
296 /* Legacy names */
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
300 0
301 };
302 static const enum m68k_register mcf5485_ctrl[] = {
303 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
304 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
305 /* Legacy names */
306 TC /* ASID */, BUSCR /* MMUBAR */,
307 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
308 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
309 0
310 };
311 static const enum m68k_register fido_ctrl[] = {
312 SFC, DFC, USP, VBR, CAC, MBB,
313 0
314 };
315 #define cpu32_ctrl m68010_ctrl
316
317 static const enum m68k_register *control_regs;
318
319 /* Internal form of a 68020 instruction. */
320 struct m68k_it
321 {
322 const char *error;
323 const char *args; /* List of opcode info. */
324 int numargs;
325
326 int numo; /* Number of shorts in opcode. */
327 short opcode[11];
328
329 struct m68k_op operands[6];
330
331 int nexp; /* Number of exprs in use. */
332 struct m68k_exp exprs[4];
333
334 int nfrag; /* Number of frags we have to produce. */
335 struct
336 {
337 int fragoff; /* Where in the current opcode the frag ends. */
338 symbolS *fadd;
339 offsetT foff;
340 int fragty;
341 }
342 fragb[4];
343
344 int nrel; /* Num of reloc strucs in use. */
345 struct
346 {
347 int n;
348 expressionS exp;
349 char wid;
350 char pcrel;
351 /* In a pc relative address the difference between the address
352 of the offset and the address that the offset is relative
353 to. This depends on the addressing mode. Basically this
354 is the value to put in the offset field to address the
355 first byte of the offset, without regarding the special
356 significance of some values (in the branch instruction, for
357 example). */
358 int pcrel_fix;
359 #ifdef OBJ_ELF
360 /* Whether this expression needs special pic relocation, and if
361 so, which. */
362 enum pic_relocation pic_reloc;
363 #endif
364 }
365 reloc[5]; /* Five is enough??? */
366 };
367
368 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
369 #define float_of_arch(x) ((x) & mfloat)
370 #define mmu_of_arch(x) ((x) & mmmu)
371 #define arch_coldfire_p(x) ((x) & mcfisa_a)
372 #define arch_coldfire_fpu(x) ((x) & cfloat)
373
374 /* Macros for determining if cpu supports a specific addressing mode. */
375 #define HAVE_LONG_DISP(x) \
376 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377 #define HAVE_LONG_CALL(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_COND(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_BRANCH(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
383
384 static struct m68k_it the_ins; /* The instruction being assembled. */
385
386 #define op(ex) ((ex)->exp.X_op)
387 #define adds(ex) ((ex)->exp.X_add_symbol)
388 #define subs(ex) ((ex)->exp.X_op_symbol)
389 #define offs(ex) ((ex)->exp.X_add_number)
390
391 /* Macros for adding things to the m68k_it struct. */
392 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
393
394 /* Like addword, but goes BEFORE general operands. */
395
396 static void
397 insop (int w, const struct m68k_incant *opcode)
398 {
399 int z;
400 for (z = the_ins.numo; z > opcode->m_codenum; --z)
401 the_ins.opcode[z] = the_ins.opcode[z - 1];
402 for (z = 0; z < the_ins.nrel; z++)
403 the_ins.reloc[z].n += 2;
404 for (z = 0; z < the_ins.nfrag; z++)
405 the_ins.fragb[z].fragoff++;
406 the_ins.opcode[opcode->m_codenum] = w;
407 the_ins.numo++;
408 }
409
410 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
411 Blecch. */
412 static void
413 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
414 {
415 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
416 ? the_ins.numo * 2 - 1
417 : (width == 'b'
418 ? the_ins.numo * 2 + 1
419 : the_ins.numo * 2));
420 the_ins.reloc[the_ins.nrel].exp = exp->exp;
421 the_ins.reloc[the_ins.nrel].wid = width;
422 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
423 #ifdef OBJ_ELF
424 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
425 #endif
426 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
427 }
428
429 /* Cause an extra frag to be generated here, inserting up to 10 bytes
430 (that value is chosen in the frag_var call in md_assemble). TYPE
431 is the subtype of the frag to be generated; its primary type is
432 rs_machine_dependent.
433
434 The TYPE parameter is also used by md_convert_frag_1 and
435 md_estimate_size_before_relax. The appropriate type of fixup will
436 be emitted by md_convert_frag_1.
437
438 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
439 static void
440 add_frag (symbolS *add, offsetT off, int type)
441 {
442 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
443 the_ins.fragb[the_ins.nfrag].fadd = add;
444 the_ins.fragb[the_ins.nfrag].foff = off;
445 the_ins.fragb[the_ins.nfrag++].fragty = type;
446 }
447
448 #define isvar(ex) \
449 (op (ex) != O_constant && op (ex) != O_big)
450
451 static char *crack_operand (char *str, struct m68k_op *opP);
452 static int get_num (struct m68k_exp *exp, int ok);
453 static int reverse_16_bits (int in);
454 static int reverse_8_bits (int in);
455 static void install_gen_operand (int mode, int val);
456 static void install_operand (int mode, int val);
457 static void s_bss (int);
458 static void s_data1 (int);
459 static void s_data2 (int);
460 static void s_even (int);
461 static void s_proc (int);
462 static void s_chip (int);
463 static void s_fopt (int);
464 static void s_opt (int);
465 static void s_reg (int);
466 static void s_restore (int);
467 static void s_save (int);
468 static void s_mri_if (int);
469 static void s_mri_else (int);
470 static void s_mri_endi (int);
471 static void s_mri_break (int);
472 static void s_mri_next (int);
473 static void s_mri_for (int);
474 static void s_mri_endf (int);
475 static void s_mri_repeat (int);
476 static void s_mri_until (int);
477 static void s_mri_while (int);
478 static void s_mri_endw (int);
479 static void s_m68k_cpu (int);
480 static void s_m68k_arch (int);
481
482 struct m68k_cpu
483 {
484 unsigned long arch; /* Architecture features. */
485 const enum m68k_register *control_regs; /* Control regs on chip */
486 const char *name; /* Name */
487 int alias; /* Alias for a cannonical name. If 1, then
488 succeeds canonical name, if -1 then
489 succeeds canonical name, if <-1 ||>1 this is a
490 deprecated name, and the next/previous name
491 should be used. */
492 };
493
494 /* We hold flags for features explicitly enabled and explicitly
495 disabled. */
496 static int current_architecture;
497 static int not_current_architecture;
498 static const struct m68k_cpu *selected_arch;
499 static const struct m68k_cpu *selected_cpu;
500 static int initialized;
501
502 /* Architecture models. */
503 static const struct m68k_cpu m68k_archs[] =
504 {
505 {m68000, m68000_ctrl, "68000", 0},
506 {m68010, m68010_ctrl, "68010", 0},
507 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
508 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
509 {m68040, m68040_ctrl, "68040", 0},
510 {m68060, m68060_ctrl, "68060", 0},
511 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
512 {fido_a, fido_ctrl, "fidoa", 0},
513 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
514 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
519 {0,0,NULL, 0}
520 };
521
522 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
523 for either. */
524 static const struct m68k_cpu m68k_extensions[] =
525 {
526 {m68851, NULL, "68851", -1},
527 {m68881, NULL, "68881", -1},
528 {m68881, NULL, "68882", -1},
529
530 {cfloat|m68881, NULL, "float", 0},
531
532 {mcfhwdiv, NULL, "div", 1},
533 {mcfusp, NULL, "usp", 1},
534 {mcfmac, NULL, "mac", 1},
535 {mcfemac, NULL, "emac", 1},
536
537 {0,NULL,NULL, 0}
538 };
539
540 /* Processor list */
541 static const struct m68k_cpu m68k_cpus[] =
542 {
543 {m68000, m68000_ctrl, "68000", 0},
544 {m68000, m68000_ctrl, "68ec000", 1},
545 {m68000, m68000_ctrl, "68hc000", 1},
546 {m68000, m68000_ctrl, "68hc001", 1},
547 {m68000, m68000_ctrl, "68008", 1},
548 {m68000, m68000_ctrl, "68302", 1},
549 {m68000, m68000_ctrl, "68306", 1},
550 {m68000, m68000_ctrl, "68307", 1},
551 {m68000, m68000_ctrl, "68322", 1},
552 {m68000, m68000_ctrl, "68356", 1},
553 {m68010, m68010_ctrl, "68010", 0},
554 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
555 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
556 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
557 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
558 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
559 {m68040, m68040_ctrl, "68040", 0},
560 {m68040, m68040_ctrl, "68ec040", 1},
561 {m68060, m68060_ctrl, "68060", 0},
562 {m68060, m68060_ctrl, "68ec060", 1},
563
564 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
565 {cpu32|m68881, cpu32_ctrl, "68330", 1},
566 {cpu32|m68881, cpu32_ctrl, "68331", 1},
567 {cpu32|m68881, cpu32_ctrl, "68332", 1},
568 {cpu32|m68881, cpu32_ctrl, "68333", 1},
569 {cpu32|m68881, cpu32_ctrl, "68334", 1},
570 {cpu32|m68881, cpu32_ctrl, "68336", 1},
571 {cpu32|m68881, cpu32_ctrl, "68340", 1},
572 {cpu32|m68881, cpu32_ctrl, "68341", 1},
573 {cpu32|m68881, cpu32_ctrl, "68349", 1},
574 {cpu32|m68881, cpu32_ctrl, "68360", 1},
575
576 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
577
578 {mcfisa_a, mcf_ctrl, "5200", 0},
579 {mcfisa_a, mcf_ctrl, "5202", 1},
580 {mcfisa_a, mcf_ctrl, "5204", 1},
581 {mcfisa_a, mcf5206_ctrl, "5206", 1},
582
583 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
584
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
587
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
590
591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
594
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
598
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
601
602 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
606
607 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
615
616 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
617 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
618 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
619
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
622
623 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
627
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
632
633 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
634
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
639
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
643
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
645
646 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
647 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
648 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
649 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
650 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
651 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
652
653 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
660
661 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
662 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
666 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
668
669 {fido_a, fido_ctrl, "fidoa", 0},
670 {fido_a, fido_ctrl, "fido", 1},
671
672 {0,NULL,NULL, 0}
673 };
674
675 static const struct m68k_cpu *m68k_lookup_cpu
676 (const char *, const struct m68k_cpu *, int, int *);
677 static int m68k_set_arch (const char *, int, int);
678 static int m68k_set_cpu (const char *, int, int);
679 static int m68k_set_extension (const char *, int, int);
680 static void m68k_init_arch (void);
681
682 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
683 architecture and we have a lot of relaxation modes. */
684
685 /* Macros used in the relaxation code. */
686 #define TAB(x,y) (((x) << 2) + (y))
687 #define TABTYPE(x) ((x) >> 2)
688
689 /* Relaxation states. */
690 #define BYTE 0
691 #define SHORT 1
692 #define LONG 2
693 #define SZ_UNDEF 3
694
695 /* Here are all the relaxation modes we support. First we can relax ordinary
696 branches. On 68020 and higher and on CPU32 all branch instructions take
697 three forms, so on these CPUs all branches always remain as such. When we
698 have to expand to the LONG form on a 68000, though, we substitute an
699 absolute jump instead. This is a direct replacement for unconditional
700 branches and a branch over a jump for conditional branches. However, if the
701 user requires PIC and disables this with --pcrel, we can only relax between
702 BYTE and SHORT forms, punting if that isn't enough. This gives us four
703 different relaxation modes for branches: */
704
705 #define BRANCHBWL 0 /* Branch byte, word, or long. */
706 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
707 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
708 #define BRANCHBW 3 /* Branch byte or word. */
709
710 /* We also relax coprocessor branches and DBcc's. All CPUs that support
711 coprocessor branches support them in word and long forms, so we have only
712 one relaxation mode for them. DBcc's are word only on all CPUs. We can
713 relax them to the LONG form with a branch-around sequence. This sequence
714 can use a long branch (if available) or an absolute jump (if acceptable).
715 This gives us two relaxation modes. If long branches are not available and
716 absolute jumps are not acceptable, we don't relax DBcc's. */
717
718 #define FBRANCH 4 /* Coprocessor branch. */
719 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
720 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
721
722 /* That's all for instruction relaxation. However, we also relax PC-relative
723 operands. Specifically, we have three operand relaxation modes. On the
724 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
725 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
726 two. Also PC+displacement+index operands in their simple form (with a non-
727 suppressed index without memory indirection) are supported on all CPUs, but
728 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
729 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
730 form of the PC+displacement+index operand. Finally, some absolute operands
731 can be relaxed down to 16-bit PC-relative. */
732
733 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
734 #define PCINDEX 8 /* PC + displacement + index. */
735 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
736
737 /* Note that calls to frag_var need to specify the maximum expansion
738 needed; this is currently 10 bytes for DBCC. */
739
740 /* The fields are:
741 How far Forward this mode will reach:
742 How far Backward this mode will reach:
743 How many bytes this mode will add to the size of the frag
744 Which mode to go to if the offset won't fit in this one
745
746 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
747 relax_typeS md_relax_table[] =
748 {
749 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
750 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
751 { 0, 0, 4, 0 },
752 { 1, 1, 0, 0 },
753
754 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
755 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
756 { 0, 0, 4, 0 },
757 { 1, 1, 0, 0 },
758
759 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
760 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
761 { 0, 0, 6, 0 },
762 { 1, 1, 0, 0 },
763
764 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
765 { 0, 0, 2, 0 },
766 { 1, 1, 0, 0 },
767 { 1, 1, 0, 0 },
768
769 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
771 { 0, 0, 4, 0 },
772 { 1, 1, 0, 0 },
773
774 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
775 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
776 { 0, 0, 10, 0 },
777 { 1, 1, 0, 0 },
778
779 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
781 { 0, 0, 10, 0 },
782 { 1, 1, 0, 0 },
783
784 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
785 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
786 { 0, 0, 6, 0 },
787 { 1, 1, 0, 0 },
788
789 { 125, -130, 0, TAB (PCINDEX, SHORT) },
790 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
791 { 0, 0, 4, 0 },
792 { 1, 1, 0, 0 },
793
794 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
795 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
796 { 0, 0, 4, 0 },
797 { 1, 1, 0, 0 },
798 };
799
800 /* These are the machine dependent pseudo-ops. These are included so
801 the assembler can work on the output from the SUN C compiler, which
802 generates these. */
803
804 /* This table describes all the machine specific pseudo-ops the assembler
805 has to support. The fields are:
806 pseudo-op name without dot
807 function to call to execute this pseudo-op
808 Integer arg to pass to the function. */
809 const pseudo_typeS md_pseudo_table[] =
810 {
811 {"data1", s_data1, 0},
812 {"data2", s_data2, 0},
813 {"bss", s_bss, 0},
814 {"even", s_even, 0},
815 {"skip", s_space, 0},
816 {"proc", s_proc, 0},
817 #if defined (TE_SUN3) || defined (OBJ_ELF)
818 {"align", s_align_bytes, 0},
819 #endif
820 #ifdef OBJ_ELF
821 {"swbeg", s_ignore, 0},
822 #endif
823 {"extend", float_cons, 'x'},
824 {"ldouble", float_cons, 'x'},
825
826 {"arch", s_m68k_arch, 0},
827 {"cpu", s_m68k_cpu, 0},
828
829 /* The following pseudo-ops are supported for MRI compatibility. */
830 {"chip", s_chip, 0},
831 {"comline", s_space, 1},
832 {"fopt", s_fopt, 0},
833 {"mask2", s_ignore, 0},
834 {"opt", s_opt, 0},
835 {"reg", s_reg, 0},
836 {"restore", s_restore, 0},
837 {"save", s_save, 0},
838
839 {"if", s_mri_if, 0},
840 {"if.b", s_mri_if, 'b'},
841 {"if.w", s_mri_if, 'w'},
842 {"if.l", s_mri_if, 'l'},
843 {"else", s_mri_else, 0},
844 {"else.s", s_mri_else, 's'},
845 {"else.l", s_mri_else, 'l'},
846 {"endi", s_mri_endi, 0},
847 {"break", s_mri_break, 0},
848 {"break.s", s_mri_break, 's'},
849 {"break.l", s_mri_break, 'l'},
850 {"next", s_mri_next, 0},
851 {"next.s", s_mri_next, 's'},
852 {"next.l", s_mri_next, 'l'},
853 {"for", s_mri_for, 0},
854 {"for.b", s_mri_for, 'b'},
855 {"for.w", s_mri_for, 'w'},
856 {"for.l", s_mri_for, 'l'},
857 {"endf", s_mri_endf, 0},
858 {"repeat", s_mri_repeat, 0},
859 {"until", s_mri_until, 0},
860 {"until.b", s_mri_until, 'b'},
861 {"until.w", s_mri_until, 'w'},
862 {"until.l", s_mri_until, 'l'},
863 {"while", s_mri_while, 0},
864 {"while.b", s_mri_while, 'b'},
865 {"while.w", s_mri_while, 'w'},
866 {"while.l", s_mri_while, 'l'},
867 {"endw", s_mri_endw, 0},
868
869 {0, 0, 0}
870 };
871
872 /* The mote pseudo ops are put into the opcode table, since they
873 don't start with a . they look like opcodes to gas. */
874
875 const pseudo_typeS mote_pseudo_table[] =
876 {
877
878 {"dcl", cons, 4},
879 {"dc", cons, 2},
880 {"dcw", cons, 2},
881 {"dcb", cons, 1},
882
883 {"dsl", s_space, 4},
884 {"ds", s_space, 2},
885 {"dsw", s_space, 2},
886 {"dsb", s_space, 1},
887
888 {"xdef", s_globl, 0},
889 #ifdef OBJ_ELF
890 {"align", s_align_bytes, 0},
891 #else
892 {"align", s_align_ptwo, 0},
893 #endif
894 #ifdef M68KCOFF
895 {"sect", obj_coff_section, 0},
896 {"section", obj_coff_section, 0},
897 #endif
898 {0, 0, 0}
899 };
900
901 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
902 gives identical results to a 32-bit host. */
903 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
904 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
905
906 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
907 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
908 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
909 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
910
911 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
912 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
913 #define islong(x) (1)
914
915 static char notend_table[256];
916 static char alt_notend_table[256];
917 #define notend(s) \
918 (! (notend_table[(unsigned char) *s] \
919 || (*s == ':' \
920 && alt_notend_table[(unsigned char) s[1]])))
921
922 #ifdef OBJ_ELF
923
924 /* Return zero if the reference to SYMBOL from within the same segment may
925 be relaxed. */
926
927 /* On an ELF system, we can't relax an externally visible symbol,
928 because it may be overridden by a shared library. However, if
929 TARGET_OS is "elf", then we presume that we are assembling for an
930 embedded system, in which case we don't have to worry about shared
931 libraries, and we can relax any external sym. */
932
933 #define relaxable_symbol(symbol) \
934 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
935 || S_IS_WEAK (symbol)))
936
937 /* Compute the relocation code for a fixup of SIZE bytes, using pc
938 relative relocation if PCREL is non-zero. PIC says whether a special
939 pic relocation was requested. */
940
941 static bfd_reloc_code_real_type
942 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
943 {
944 switch (pic)
945 {
946 case pic_got_pcrel:
947 switch (size)
948 {
949 case 1:
950 return BFD_RELOC_8_GOT_PCREL;
951 case 2:
952 return BFD_RELOC_16_GOT_PCREL;
953 case 4:
954 return BFD_RELOC_32_GOT_PCREL;
955 }
956 break;
957
958 case pic_got_off:
959 switch (size)
960 {
961 case 1:
962 return BFD_RELOC_8_GOTOFF;
963 case 2:
964 return BFD_RELOC_16_GOTOFF;
965 case 4:
966 return BFD_RELOC_32_GOTOFF;
967 }
968 break;
969
970 case pic_plt_pcrel:
971 switch (size)
972 {
973 case 1:
974 return BFD_RELOC_8_PLT_PCREL;
975 case 2:
976 return BFD_RELOC_16_PLT_PCREL;
977 case 4:
978 return BFD_RELOC_32_PLT_PCREL;
979 }
980 break;
981
982 case pic_plt_off:
983 switch (size)
984 {
985 case 1:
986 return BFD_RELOC_8_PLTOFF;
987 case 2:
988 return BFD_RELOC_16_PLTOFF;
989 case 4:
990 return BFD_RELOC_32_PLTOFF;
991 }
992 break;
993
994 case pic_none:
995 if (pcrel)
996 {
997 switch (size)
998 {
999 case 1:
1000 return BFD_RELOC_8_PCREL;
1001 case 2:
1002 return BFD_RELOC_16_PCREL;
1003 case 4:
1004 return BFD_RELOC_32_PCREL;
1005 }
1006 }
1007 else
1008 {
1009 switch (size)
1010 {
1011 case 1:
1012 return BFD_RELOC_8;
1013 case 2:
1014 return BFD_RELOC_16;
1015 case 4:
1016 return BFD_RELOC_32;
1017 }
1018 }
1019 }
1020
1021 if (pcrel)
1022 {
1023 if (pic == pic_none)
1024 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1025 else
1026 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1027 }
1028 else
1029 {
1030 if (pic == pic_none)
1031 as_bad (_("Can not do %d byte relocation"), size);
1032 else
1033 as_bad (_("Can not do %d byte pic relocation"), size);
1034 }
1035
1036 return BFD_RELOC_NONE;
1037 }
1038
1039 /* Here we decide which fixups can be adjusted to make them relative
1040 to the beginning of the section instead of the symbol. Basically
1041 we need to make sure that the dynamic relocations are done
1042 correctly, so in some cases we force the original symbol to be
1043 used. */
1044 int
1045 tc_m68k_fix_adjustable (fixS *fixP)
1046 {
1047 /* Adjust_reloc_syms doesn't know about the GOT. */
1048 switch (fixP->fx_r_type)
1049 {
1050 case BFD_RELOC_8_GOT_PCREL:
1051 case BFD_RELOC_16_GOT_PCREL:
1052 case BFD_RELOC_32_GOT_PCREL:
1053 case BFD_RELOC_8_GOTOFF:
1054 case BFD_RELOC_16_GOTOFF:
1055 case BFD_RELOC_32_GOTOFF:
1056 case BFD_RELOC_8_PLT_PCREL:
1057 case BFD_RELOC_16_PLT_PCREL:
1058 case BFD_RELOC_32_PLT_PCREL:
1059 case BFD_RELOC_8_PLTOFF:
1060 case BFD_RELOC_16_PLTOFF:
1061 case BFD_RELOC_32_PLTOFF:
1062 return 0;
1063
1064 case BFD_RELOC_VTABLE_INHERIT:
1065 case BFD_RELOC_VTABLE_ENTRY:
1066 return 0;
1067
1068 default:
1069 return 1;
1070 }
1071 }
1072
1073 #else /* !OBJ_ELF */
1074
1075 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1076
1077 /* PR gas/3041 Weak symbols are not relaxable
1078 because they must be treated as extern. */
1079 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1080
1081 #endif /* OBJ_ELF */
1082
1083 arelent *
1084 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1085 {
1086 arelent *reloc;
1087 bfd_reloc_code_real_type code;
1088
1089 /* If the tcbit is set, then this was a fixup of a negative value
1090 that was never resolved. We do not have a reloc to handle this,
1091 so just return. We assume that other code will have detected this
1092 situation and produced a helpful error message, so we just tell the
1093 user that the reloc cannot be produced. */
1094 if (fixp->fx_tcbit)
1095 {
1096 if (fixp->fx_addsy)
1097 as_bad_where (fixp->fx_file, fixp->fx_line,
1098 _("Unable to produce reloc against symbol '%s'"),
1099 S_GET_NAME (fixp->fx_addsy));
1100 return NULL;
1101 }
1102
1103 if (fixp->fx_r_type != BFD_RELOC_NONE)
1104 {
1105 code = fixp->fx_r_type;
1106
1107 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1108 that fixup_segment converted a non-PC relative reloc into a
1109 PC relative reloc. In such a case, we need to convert the
1110 reloc code. */
1111 if (fixp->fx_pcrel)
1112 {
1113 switch (code)
1114 {
1115 case BFD_RELOC_8:
1116 code = BFD_RELOC_8_PCREL;
1117 break;
1118 case BFD_RELOC_16:
1119 code = BFD_RELOC_16_PCREL;
1120 break;
1121 case BFD_RELOC_32:
1122 code = BFD_RELOC_32_PCREL;
1123 break;
1124 case BFD_RELOC_8_PCREL:
1125 case BFD_RELOC_16_PCREL:
1126 case BFD_RELOC_32_PCREL:
1127 case BFD_RELOC_8_GOT_PCREL:
1128 case BFD_RELOC_16_GOT_PCREL:
1129 case BFD_RELOC_32_GOT_PCREL:
1130 case BFD_RELOC_8_GOTOFF:
1131 case BFD_RELOC_16_GOTOFF:
1132 case BFD_RELOC_32_GOTOFF:
1133 case BFD_RELOC_8_PLT_PCREL:
1134 case BFD_RELOC_16_PLT_PCREL:
1135 case BFD_RELOC_32_PLT_PCREL:
1136 case BFD_RELOC_8_PLTOFF:
1137 case BFD_RELOC_16_PLTOFF:
1138 case BFD_RELOC_32_PLTOFF:
1139 break;
1140 default:
1141 as_bad_where (fixp->fx_file, fixp->fx_line,
1142 _("Cannot make %s relocation PC relative"),
1143 bfd_get_reloc_code_name (code));
1144 }
1145 }
1146 }
1147 else
1148 {
1149 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1150 switch (F (fixp->fx_size, fixp->fx_pcrel))
1151 {
1152 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1153 MAP (1, 0, BFD_RELOC_8);
1154 MAP (2, 0, BFD_RELOC_16);
1155 MAP (4, 0, BFD_RELOC_32);
1156 MAP (1, 1, BFD_RELOC_8_PCREL);
1157 MAP (2, 1, BFD_RELOC_16_PCREL);
1158 MAP (4, 1, BFD_RELOC_32_PCREL);
1159 default:
1160 abort ();
1161 }
1162 }
1163 #undef F
1164 #undef MAP
1165
1166 reloc = (arelent *) xmalloc (sizeof (arelent));
1167 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1168 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1169 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1170 #ifndef OBJ_ELF
1171 if (fixp->fx_pcrel)
1172 reloc->addend = fixp->fx_addnumber;
1173 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1174 && fixp->fx_addsy
1175 && S_IS_WEAK (fixp->fx_addsy)
1176 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1177 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1178 to put the symbol offset into frags referencing a weak symbol. */
1179 reloc->addend = fixp->fx_addnumber
1180 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1181 else
1182 reloc->addend = 0;
1183 #else
1184 if (!fixp->fx_pcrel)
1185 reloc->addend = fixp->fx_addnumber;
1186 else
1187 reloc->addend = (section->vma
1188 /* Explicit sign extension in case char is
1189 unsigned. */
1190 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1191 + fixp->fx_addnumber
1192 + md_pcrel_from (fixp));
1193 #endif
1194
1195 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1196 assert (reloc->howto != 0);
1197
1198 return reloc;
1199 }
1200
1201 /* Handle of the OPCODE hash table. NULL means any use before
1202 m68k_ip_begin() will crash. */
1203 static struct hash_control *op_hash;
1204 \f
1205 /* Assemble an m68k instruction. */
1206
1207 static void
1208 m68k_ip (char *instring)
1209 {
1210 register char *p;
1211 register struct m68k_op *opP;
1212 register const struct m68k_incant *opcode;
1213 register const char *s;
1214 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1215 char *pdot, *pdotmove;
1216 enum m68k_size siz1, siz2;
1217 char c;
1218 int losing;
1219 int opsfound;
1220 struct m68k_op operands_backup[6];
1221 LITTLENUM_TYPE words[6];
1222 LITTLENUM_TYPE *wordp;
1223 unsigned long ok_arch = 0;
1224
1225 if (*instring == ' ')
1226 instring++; /* Skip leading whitespace. */
1227
1228 /* Scan up to end of operation-code, which MUST end in end-of-string
1229 or exactly 1 space. */
1230 pdot = 0;
1231 for (p = instring; *p != '\0'; p++)
1232 {
1233 if (*p == ' ')
1234 break;
1235 if (*p == '.')
1236 pdot = p;
1237 }
1238
1239 if (p == instring)
1240 {
1241 the_ins.error = _("No operator");
1242 return;
1243 }
1244
1245 /* p now points to the end of the opcode name, probably whitespace.
1246 Make sure the name is null terminated by clobbering the
1247 whitespace, look it up in the hash table, then fix it back.
1248 Remove a dot, first, since the opcode tables have none. */
1249 if (pdot != NULL)
1250 {
1251 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1252 *pdotmove = pdotmove[1];
1253 p--;
1254 }
1255
1256 c = *p;
1257 *p = '\0';
1258 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1259 *p = c;
1260
1261 if (pdot != NULL)
1262 {
1263 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1264 *pdotmove = pdotmove[-1];
1265 *pdot = '.';
1266 ++p;
1267 }
1268
1269 if (opcode == NULL)
1270 {
1271 the_ins.error = _("Unknown operator");
1272 return;
1273 }
1274
1275 /* Found a legitimate opcode, start matching operands. */
1276 while (*p == ' ')
1277 ++p;
1278
1279 if (opcode->m_operands == 0)
1280 {
1281 char *old = input_line_pointer;
1282 *old = '\n';
1283 input_line_pointer = p;
1284 /* Ahh - it's a motorola style psuedo op. */
1285 mote_pseudo_table[opcode->m_opnum].poc_handler
1286 (mote_pseudo_table[opcode->m_opnum].poc_val);
1287 input_line_pointer = old;
1288 *old = 0;
1289
1290 return;
1291 }
1292
1293 if (flag_mri && opcode->m_opnum == 0)
1294 {
1295 /* In MRI mode, random garbage is allowed after an instruction
1296 which accepts no operands. */
1297 the_ins.args = opcode->m_operands;
1298 the_ins.numargs = opcode->m_opnum;
1299 the_ins.numo = opcode->m_codenum;
1300 the_ins.opcode[0] = getone (opcode);
1301 the_ins.opcode[1] = gettwo (opcode);
1302 return;
1303 }
1304
1305 for (opP = &the_ins.operands[0]; *p; opP++)
1306 {
1307 p = crack_operand (p, opP);
1308
1309 if (opP->error)
1310 {
1311 the_ins.error = opP->error;
1312 return;
1313 }
1314 }
1315
1316 opsfound = opP - &the_ins.operands[0];
1317
1318 /* This ugly hack is to support the floating pt opcodes in their
1319 standard form. Essentially, we fake a first enty of type COP#1 */
1320 if (opcode->m_operands[0] == 'I')
1321 {
1322 int n;
1323
1324 for (n = opsfound; n > 0; --n)
1325 the_ins.operands[n] = the_ins.operands[n - 1];
1326
1327 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1328 the_ins.operands[0].mode = CONTROL;
1329 the_ins.operands[0].reg = m68k_float_copnum;
1330 opsfound++;
1331 }
1332
1333 /* We've got the operands. Find an opcode that'll accept them. */
1334 for (losing = 0;;)
1335 {
1336 /* If we didn't get the right number of ops, or we have no
1337 common model with this pattern then reject this pattern. */
1338
1339 ok_arch |= opcode->m_arch;
1340 if (opsfound != opcode->m_opnum
1341 || ((opcode->m_arch & current_architecture) == 0))
1342 ++losing;
1343 else
1344 {
1345 int i;
1346
1347 /* Make a copy of the operands of this insn so that
1348 we can modify them safely, should we want to. */
1349 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1350 for (i = 0; i < opsfound; i++)
1351 operands_backup[i] = the_ins.operands[i];
1352
1353 for (s = opcode->m_operands, opP = &operands_backup[0];
1354 *s && !losing;
1355 s += 2, opP++)
1356 {
1357 /* Warning: this switch is huge! */
1358 /* I've tried to organize the cases into this order:
1359 non-alpha first, then alpha by letter. Lower-case
1360 goes directly before uppercase counterpart. */
1361 /* Code with multiple case ...: gets sorted by the lowest
1362 case ... it belongs to. I hope this makes sense. */
1363 switch (*s)
1364 {
1365 case '!':
1366 switch (opP->mode)
1367 {
1368 case IMMED:
1369 case DREG:
1370 case AREG:
1371 case FPREG:
1372 case CONTROL:
1373 case AINC:
1374 case ADEC:
1375 case REGLST:
1376 losing++;
1377 break;
1378 default:
1379 break;
1380 }
1381 break;
1382
1383 case '<':
1384 switch (opP->mode)
1385 {
1386 case DREG:
1387 case AREG:
1388 case FPREG:
1389 case CONTROL:
1390 case IMMED:
1391 case ADEC:
1392 case REGLST:
1393 losing++;
1394 break;
1395 default:
1396 break;
1397 }
1398 break;
1399
1400 case '>':
1401 switch (opP->mode)
1402 {
1403 case DREG:
1404 case AREG:
1405 case FPREG:
1406 case CONTROL:
1407 case IMMED:
1408 case AINC:
1409 case REGLST:
1410 losing++;
1411 break;
1412 case ABSL:
1413 break;
1414 default:
1415 if (opP->reg == PC
1416 || opP->reg == ZPC)
1417 losing++;
1418 break;
1419 }
1420 break;
1421
1422 case 'm':
1423 switch (opP->mode)
1424 {
1425 case DREG:
1426 case AREG:
1427 case AINDR:
1428 case AINC:
1429 case ADEC:
1430 break;
1431 default:
1432 losing++;
1433 }
1434 break;
1435
1436 case 'n':
1437 switch (opP->mode)
1438 {
1439 case DISP:
1440 break;
1441 default:
1442 losing++;
1443 }
1444 break;
1445
1446 case 'o':
1447 switch (opP->mode)
1448 {
1449 case BASE:
1450 case ABSL:
1451 case IMMED:
1452 break;
1453 default:
1454 losing++;
1455 }
1456 break;
1457
1458 case 'p':
1459 switch (opP->mode)
1460 {
1461 case DREG:
1462 case AREG:
1463 case AINDR:
1464 case AINC:
1465 case ADEC:
1466 break;
1467 case DISP:
1468 if (opP->reg == PC || opP->reg == ZPC)
1469 losing++;
1470 break;
1471 default:
1472 losing++;
1473 }
1474 break;
1475
1476 case 'q':
1477 switch (opP->mode)
1478 {
1479 case DREG:
1480 case AINDR:
1481 case AINC:
1482 case ADEC:
1483 break;
1484 case DISP:
1485 if (opP->reg == PC || opP->reg == ZPC)
1486 losing++;
1487 break;
1488 default:
1489 losing++;
1490 break;
1491 }
1492 break;
1493
1494 case 'v':
1495 switch (opP->mode)
1496 {
1497 case DREG:
1498 case AINDR:
1499 case AINC:
1500 case ADEC:
1501 case ABSL:
1502 break;
1503 case DISP:
1504 if (opP->reg == PC || opP->reg == ZPC)
1505 losing++;
1506 break;
1507 default:
1508 losing++;
1509 break;
1510 }
1511 break;
1512
1513 case '#':
1514 if (opP->mode != IMMED)
1515 losing++;
1516 else if (s[1] == 'b'
1517 && ! isvar (&opP->disp)
1518 && (opP->disp.exp.X_op != O_constant
1519 || ! isbyte (opP->disp.exp.X_add_number)))
1520 losing++;
1521 else if (s[1] == 'B'
1522 && ! isvar (&opP->disp)
1523 && (opP->disp.exp.X_op != O_constant
1524 || ! issbyte (opP->disp.exp.X_add_number)))
1525 losing++;
1526 else if (s[1] == 'w'
1527 && ! isvar (&opP->disp)
1528 && (opP->disp.exp.X_op != O_constant
1529 || ! isword (opP->disp.exp.X_add_number)))
1530 losing++;
1531 else if (s[1] == 'W'
1532 && ! isvar (&opP->disp)
1533 && (opP->disp.exp.X_op != O_constant
1534 || ! issword (opP->disp.exp.X_add_number)))
1535 losing++;
1536 break;
1537
1538 case '^':
1539 case 'T':
1540 if (opP->mode != IMMED)
1541 losing++;
1542 break;
1543
1544 case '$':
1545 if (opP->mode == AREG
1546 || opP->mode == CONTROL
1547 || opP->mode == FPREG
1548 || opP->mode == IMMED
1549 || opP->mode == REGLST
1550 || (opP->mode != ABSL
1551 && (opP->reg == PC
1552 || opP->reg == ZPC)))
1553 losing++;
1554 break;
1555
1556 case '%':
1557 if (opP->mode == CONTROL
1558 || opP->mode == FPREG
1559 || opP->mode == REGLST
1560 || opP->mode == IMMED
1561 || (opP->mode != ABSL
1562 && (opP->reg == PC
1563 || opP->reg == ZPC)))
1564 losing++;
1565 break;
1566
1567 case '&':
1568 switch (opP->mode)
1569 {
1570 case DREG:
1571 case AREG:
1572 case FPREG:
1573 case CONTROL:
1574 case IMMED:
1575 case AINC:
1576 case ADEC:
1577 case REGLST:
1578 losing++;
1579 break;
1580 case ABSL:
1581 break;
1582 default:
1583 if (opP->reg == PC
1584 || opP->reg == ZPC)
1585 losing++;
1586 break;
1587 }
1588 break;
1589
1590 case '*':
1591 if (opP->mode == CONTROL
1592 || opP->mode == FPREG
1593 || opP->mode == REGLST)
1594 losing++;
1595 break;
1596
1597 case '+':
1598 if (opP->mode != AINC)
1599 losing++;
1600 break;
1601
1602 case '-':
1603 if (opP->mode != ADEC)
1604 losing++;
1605 break;
1606
1607 case '/':
1608 switch (opP->mode)
1609 {
1610 case AREG:
1611 case CONTROL:
1612 case FPREG:
1613 case AINC:
1614 case ADEC:
1615 case IMMED:
1616 case REGLST:
1617 losing++;
1618 break;
1619 default:
1620 break;
1621 }
1622 break;
1623
1624 case ';':
1625 switch (opP->mode)
1626 {
1627 case AREG:
1628 case CONTROL:
1629 case FPREG:
1630 case REGLST:
1631 losing++;
1632 break;
1633 default:
1634 break;
1635 }
1636 break;
1637
1638 case '?':
1639 switch (opP->mode)
1640 {
1641 case AREG:
1642 case CONTROL:
1643 case FPREG:
1644 case AINC:
1645 case ADEC:
1646 case IMMED:
1647 case REGLST:
1648 losing++;
1649 break;
1650 case ABSL:
1651 break;
1652 default:
1653 if (opP->reg == PC || opP->reg == ZPC)
1654 losing++;
1655 break;
1656 }
1657 break;
1658
1659 case '@':
1660 switch (opP->mode)
1661 {
1662 case AREG:
1663 case CONTROL:
1664 case FPREG:
1665 case IMMED:
1666 case REGLST:
1667 losing++;
1668 break;
1669 default:
1670 break;
1671 }
1672 break;
1673
1674 case '~': /* For now! (JF FOO is this right?) */
1675 switch (opP->mode)
1676 {
1677 case DREG:
1678 case AREG:
1679 case CONTROL:
1680 case FPREG:
1681 case IMMED:
1682 case REGLST:
1683 losing++;
1684 break;
1685 case ABSL:
1686 break;
1687 default:
1688 if (opP->reg == PC
1689 || opP->reg == ZPC)
1690 losing++;
1691 break;
1692 }
1693 break;
1694
1695 case '3':
1696 if (opP->mode != CONTROL
1697 || (opP->reg != TT0 && opP->reg != TT1))
1698 losing++;
1699 break;
1700
1701 case 'A':
1702 if (opP->mode != AREG)
1703 losing++;
1704 break;
1705
1706 case 'a':
1707 if (opP->mode != AINDR)
1708 ++losing;
1709 break;
1710
1711 case '4':
1712 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1713 && (opP->mode != DISP
1714 || opP->reg < ADDR0
1715 || opP->reg > ADDR7))
1716 ++losing;
1717 break;
1718
1719 case 'B': /* FOO */
1720 if (opP->mode != ABSL
1721 || (flag_long_jumps
1722 && strncmp (instring, "jbsr", 4) == 0))
1723 losing++;
1724 break;
1725
1726 case 'b':
1727 switch (opP->mode)
1728 {
1729 case IMMED:
1730 case ABSL:
1731 case AREG:
1732 case FPREG:
1733 case CONTROL:
1734 case POST:
1735 case PRE:
1736 case REGLST:
1737 losing++;
1738 break;
1739 default:
1740 break;
1741 }
1742 break;
1743
1744 case 'C':
1745 if (opP->mode != CONTROL || opP->reg != CCR)
1746 losing++;
1747 break;
1748
1749 case 'd':
1750 if (opP->mode != DISP
1751 || opP->reg < ADDR0
1752 || opP->reg > ADDR7)
1753 losing++;
1754 break;
1755
1756 case 'D':
1757 if (opP->mode != DREG)
1758 losing++;
1759 break;
1760
1761 case 'E':
1762 if (opP->reg != ACC)
1763 losing++;
1764 break;
1765
1766 case 'e':
1767 if (opP->reg != ACC && opP->reg != ACC1
1768 && opP->reg != ACC2 && opP->reg != ACC3)
1769 losing++;
1770 break;
1771
1772 case 'F':
1773 if (opP->mode != FPREG)
1774 losing++;
1775 break;
1776
1777 case 'G':
1778 if (opP->reg != MACSR)
1779 losing++;
1780 break;
1781
1782 case 'g':
1783 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1784 losing++;
1785 break;
1786
1787 case 'H':
1788 if (opP->reg != MASK)
1789 losing++;
1790 break;
1791
1792 case 'I':
1793 if (opP->mode != CONTROL
1794 || opP->reg < COP0
1795 || opP->reg > COP7)
1796 losing++;
1797 break;
1798
1799 case 'i':
1800 if (opP->mode != LSH && opP->mode != RSH)
1801 losing++;
1802 break;
1803
1804 case 'J':
1805 if (opP->mode != CONTROL
1806 || opP->reg < USP
1807 || opP->reg > last_movec_reg
1808 || !control_regs)
1809 losing++;
1810 else
1811 {
1812 const enum m68k_register *rp;
1813
1814 for (rp = control_regs; *rp; rp++)
1815 {
1816 if (*rp == opP->reg)
1817 break;
1818 /* In most CPUs RAMBAR refers to control reg
1819 c05 (RAMBAR1), but a few CPUs have it
1820 refer to c04 (RAMBAR0). */
1821 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1822 {
1823 opP->reg = RAMBAR_ALT;
1824 break;
1825 }
1826 }
1827 if (*rp == 0)
1828 losing++;
1829 }
1830 break;
1831
1832 case 'k':
1833 if (opP->mode != IMMED)
1834 losing++;
1835 break;
1836
1837 case 'l':
1838 case 'L':
1839 if (opP->mode == DREG
1840 || opP->mode == AREG
1841 || opP->mode == FPREG)
1842 {
1843 if (s[1] == '8')
1844 losing++;
1845 else
1846 {
1847 switch (opP->mode)
1848 {
1849 case DREG:
1850 opP->mask = 1 << (opP->reg - DATA0);
1851 break;
1852 case AREG:
1853 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1854 break;
1855 case FPREG:
1856 opP->mask = 1 << (opP->reg - FP0 + 16);
1857 break;
1858 default:
1859 abort ();
1860 }
1861 opP->mode = REGLST;
1862 }
1863 }
1864 else if (opP->mode == CONTROL)
1865 {
1866 if (s[1] != '8')
1867 losing++;
1868 else
1869 {
1870 switch (opP->reg)
1871 {
1872 case FPI:
1873 opP->mask = 1 << 24;
1874 break;
1875 case FPS:
1876 opP->mask = 1 << 25;
1877 break;
1878 case FPC:
1879 opP->mask = 1 << 26;
1880 break;
1881 default:
1882 losing++;
1883 break;
1884 }
1885 opP->mode = REGLST;
1886 }
1887 }
1888 else if (opP->mode != REGLST)
1889 losing++;
1890 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1891 losing++;
1892 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1893 losing++;
1894 break;
1895
1896 case 'M':
1897 if (opP->mode != IMMED)
1898 losing++;
1899 else if (opP->disp.exp.X_op != O_constant
1900 || ! issbyte (opP->disp.exp.X_add_number))
1901 losing++;
1902 else if (! m68k_quick
1903 && instring[3] != 'q'
1904 && instring[4] != 'q')
1905 losing++;
1906 break;
1907
1908 case 'O':
1909 if (opP->mode != DREG
1910 && opP->mode != IMMED
1911 && opP->mode != ABSL)
1912 losing++;
1913 break;
1914
1915 case 'Q':
1916 if (opP->mode != IMMED)
1917 losing++;
1918 else if (opP->disp.exp.X_op != O_constant
1919 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1920 losing++;
1921 else if (! m68k_quick
1922 && (strncmp (instring, "add", 3) == 0
1923 || strncmp (instring, "sub", 3) == 0)
1924 && instring[3] != 'q')
1925 losing++;
1926 break;
1927
1928 case 'R':
1929 if (opP->mode != DREG && opP->mode != AREG)
1930 losing++;
1931 break;
1932
1933 case 'r':
1934 if (opP->mode != AINDR
1935 && (opP->mode != BASE
1936 || (opP->reg != 0
1937 && opP->reg != ZADDR0)
1938 || opP->disp.exp.X_op != O_absent
1939 || ((opP->index.reg < DATA0
1940 || opP->index.reg > DATA7)
1941 && (opP->index.reg < ADDR0
1942 || opP->index.reg > ADDR7))
1943 || opP->index.size != SIZE_UNSPEC
1944 || opP->index.scale != 1))
1945 losing++;
1946 break;
1947
1948 case 's':
1949 if (opP->mode != CONTROL
1950 || ! (opP->reg == FPI
1951 || opP->reg == FPS
1952 || opP->reg == FPC))
1953 losing++;
1954 break;
1955
1956 case 'S':
1957 if (opP->mode != CONTROL || opP->reg != SR)
1958 losing++;
1959 break;
1960
1961 case 't':
1962 if (opP->mode != IMMED)
1963 losing++;
1964 else if (opP->disp.exp.X_op != O_constant
1965 || TRUNC (opP->disp.exp.X_add_number) > 7)
1966 losing++;
1967 break;
1968
1969 case 'U':
1970 if (opP->mode != CONTROL || opP->reg != USP)
1971 losing++;
1972 break;
1973
1974 case 'x':
1975 if (opP->mode != IMMED)
1976 losing++;
1977 else if (opP->disp.exp.X_op != O_constant
1978 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1979 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1980 losing++;
1981 break;
1982
1983 case 'j':
1984 if (opP->mode != IMMED)
1985 losing++;
1986 else if (opP->disp.exp.X_op != O_constant
1987 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1988 losing++;
1989 break;
1990
1991 case 'K':
1992 if (opP->mode != IMMED)
1993 losing++;
1994 else if (opP->disp.exp.X_op != O_constant
1995 || TRUNC (opP->disp.exp.X_add_number) > 511)
1996 losing++;
1997 break;
1998
1999 /* JF these are out of order. We could put them
2000 in order if we were willing to put up with
2001 bunches of #ifdef m68851s in the code.
2002
2003 Don't forget that you need these operands
2004 to use 68030 MMU instructions. */
2005 #ifndef NO_68851
2006 /* Memory addressing mode used by pflushr. */
2007 case '|':
2008 if (opP->mode == CONTROL
2009 || opP->mode == FPREG
2010 || opP->mode == DREG
2011 || opP->mode == AREG
2012 || opP->mode == REGLST)
2013 losing++;
2014 /* We should accept immediate operands, but they
2015 supposedly have to be quad word, and we don't
2016 handle that. I would like to see what a Motorola
2017 assembler does before doing something here. */
2018 if (opP->mode == IMMED)
2019 losing++;
2020 break;
2021
2022 case 'f':
2023 if (opP->mode != CONTROL
2024 || (opP->reg != SFC && opP->reg != DFC))
2025 losing++;
2026 break;
2027
2028 case '0':
2029 if (opP->mode != CONTROL || opP->reg != TC)
2030 losing++;
2031 break;
2032
2033 case '1':
2034 if (opP->mode != CONTROL || opP->reg != AC)
2035 losing++;
2036 break;
2037
2038 case '2':
2039 if (opP->mode != CONTROL
2040 || (opP->reg != CAL
2041 && opP->reg != VAL
2042 && opP->reg != SCC))
2043 losing++;
2044 break;
2045
2046 case 'V':
2047 if (opP->mode != CONTROL
2048 || opP->reg != VAL)
2049 losing++;
2050 break;
2051
2052 case 'W':
2053 if (opP->mode != CONTROL
2054 || (opP->reg != DRP
2055 && opP->reg != SRP
2056 && opP->reg != CRP))
2057 losing++;
2058 break;
2059
2060 case 'w':
2061 switch (opP->mode)
2062 {
2063 case IMMED:
2064 case ABSL:
2065 case AREG:
2066 case DREG:
2067 case FPREG:
2068 case CONTROL:
2069 case POST:
2070 case PRE:
2071 case REGLST:
2072 losing++;
2073 break;
2074 default:
2075 break;
2076 }
2077 break;
2078
2079 case 'X':
2080 if (opP->mode != CONTROL
2081 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2082 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2083 losing++;
2084 break;
2085
2086 case 'Y':
2087 if (opP->mode != CONTROL || opP->reg != PSR)
2088 losing++;
2089 break;
2090
2091 case 'Z':
2092 if (opP->mode != CONTROL || opP->reg != PCSR)
2093 losing++;
2094 break;
2095 #endif
2096 case 'c':
2097 if (opP->mode != CONTROL
2098 || (opP->reg != NC
2099 && opP->reg != IC
2100 && opP->reg != DC
2101 && opP->reg != BC))
2102 losing++;
2103 break;
2104
2105 case '_':
2106 if (opP->mode != ABSL)
2107 ++losing;
2108 break;
2109
2110 case 'u':
2111 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2112 losing++;
2113 /* FIXME: kludge instead of fixing parser:
2114 upper/lower registers are *not* CONTROL
2115 registers, but ordinary ones. */
2116 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2117 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2118 opP->mode = DREG;
2119 else
2120 opP->mode = AREG;
2121 break;
2122
2123 case 'y':
2124 if (!(opP->mode == AINDR
2125 || (opP->mode == DISP
2126 && !(opP->reg == PC || opP->reg == ZPC))))
2127 losing++;
2128 break;
2129
2130 case 'z':
2131 if (!(opP->mode == AINDR || opP->mode == DISP))
2132 losing++;
2133 break;
2134
2135 default:
2136 abort ();
2137 }
2138
2139 if (losing)
2140 break;
2141 }
2142
2143 /* Since we have found the correct instruction, copy
2144 in the modifications that we may have made. */
2145 if (!losing)
2146 for (i = 0; i < opsfound; i++)
2147 the_ins.operands[i] = operands_backup[i];
2148 }
2149
2150 if (!losing)
2151 break;
2152
2153 opcode = opcode->m_next;
2154
2155 if (!opcode)
2156 {
2157 if (ok_arch
2158 && !(ok_arch & current_architecture))
2159 {
2160 const struct m68k_cpu *cpu;
2161 int any = 0;
2162 size_t space = 400;
2163 char *buf = xmalloc (space + 1);
2164 size_t len;
2165 int paren = 1;
2166
2167 the_ins.error = buf;
2168 /* Make sure there's a NUL at the end of the buffer -- strncpy
2169 won't write one when it runs out of buffer */
2170 buf[space] = 0;
2171 #define APPEND(STRING) \
2172 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2173
2174 APPEND (_("invalid instruction for this architecture; needs "));
2175 switch (ok_arch)
2176 {
2177 case mcfisa_a:
2178 APPEND (_("ColdFire ISA_A"));
2179 break;
2180 case mcfhwdiv:
2181 APPEND (_("ColdFire hardware divide"));
2182 break;
2183 case mcfisa_aa:
2184 APPEND (_("ColdFire ISA_A+"));
2185 break;
2186 case mcfisa_b:
2187 APPEND (_("ColdFire ISA_B"));
2188 break;
2189 case mcfisa_c:
2190 APPEND (_("ColdFire ISA_C"));
2191 break;
2192 case cfloat:
2193 APPEND (_("ColdFire fpu"));
2194 break;
2195 case mfloat:
2196 APPEND (_("M68K fpu"));
2197 break;
2198 case mmmu:
2199 APPEND (_("M68K mmu"));
2200 break;
2201 case m68020up:
2202 APPEND (_("68020 or higher"));
2203 break;
2204 case m68000up:
2205 APPEND (_("68000 or higher"));
2206 break;
2207 case m68010up:
2208 APPEND (_("68010 or higher"));
2209 break;
2210 default:
2211 paren = 0;
2212 }
2213 if (paren)
2214 APPEND (" (");
2215
2216 for (cpu = m68k_cpus; cpu->name; cpu++)
2217 if (!cpu->alias && (cpu->arch & ok_arch))
2218 {
2219 const struct m68k_cpu *alias;
2220 int seen_master = 0;
2221
2222 if (any)
2223 APPEND (", ");
2224 any = 0;
2225 APPEND (cpu->name);
2226 for (alias = cpu; alias != m68k_cpus; alias--)
2227 if (alias[-1].alias >= 0)
2228 break;
2229 for (; !seen_master || alias->alias > 0; alias++)
2230 {
2231 if (!alias->alias)
2232 seen_master = 1;
2233 else
2234 {
2235 if (any)
2236 APPEND (", ");
2237 else
2238 APPEND (" [");
2239 APPEND (alias->name);
2240 any = 1;
2241 }
2242 }
2243 if (any)
2244 APPEND ("]");
2245 any = 1;
2246 }
2247 if (paren)
2248 APPEND (")");
2249 #undef APPEND
2250 if (!space)
2251 {
2252 /* we ran out of space, so replace the end of the list
2253 with ellipsis. */
2254 buf -= 4;
2255 while (*buf != ' ')
2256 buf--;
2257 strcpy (buf, " ...");
2258 }
2259 }
2260 else
2261 the_ins.error = _("operands mismatch");
2262 return;
2263 }
2264
2265 losing = 0;
2266 }
2267
2268 /* Now assemble it. */
2269 the_ins.args = opcode->m_operands;
2270 the_ins.numargs = opcode->m_opnum;
2271 the_ins.numo = opcode->m_codenum;
2272 the_ins.opcode[0] = getone (opcode);
2273 the_ins.opcode[1] = gettwo (opcode);
2274
2275 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2276 {
2277 int have_disp = 0;
2278
2279 /* This switch is a doozy.
2280 Watch the first step; its a big one! */
2281 switch (s[0])
2282 {
2283
2284 case '*':
2285 case '~':
2286 case '%':
2287 case ';':
2288 case '@':
2289 case '!':
2290 case '&':
2291 case '$':
2292 case '?':
2293 case '/':
2294 case '<':
2295 case '>':
2296 case 'b':
2297 case 'm':
2298 case 'n':
2299 case 'o':
2300 case 'p':
2301 case 'q':
2302 case 'v':
2303 case 'w':
2304 case 'y':
2305 case 'z':
2306 case '4':
2307 #ifndef NO_68851
2308 case '|':
2309 #endif
2310 switch (opP->mode)
2311 {
2312 case IMMED:
2313 tmpreg = 0x3c; /* 7.4 */
2314 if (strchr ("bwl", s[1]))
2315 nextword = get_num (&opP->disp, 90);
2316 else
2317 nextword = get_num (&opP->disp, 0);
2318 if (isvar (&opP->disp))
2319 add_fix (s[1], &opP->disp, 0, 0);
2320 switch (s[1])
2321 {
2322 case 'b':
2323 if (!isbyte (nextword))
2324 opP->error = _("operand out of range");
2325 addword (nextword);
2326 baseo = 0;
2327 break;
2328 case 'w':
2329 if (!isword (nextword))
2330 opP->error = _("operand out of range");
2331 addword (nextword);
2332 baseo = 0;
2333 break;
2334 case 'W':
2335 if (!issword (nextword))
2336 opP->error = _("operand out of range");
2337 addword (nextword);
2338 baseo = 0;
2339 break;
2340 case 'l':
2341 addword (nextword >> 16);
2342 addword (nextword);
2343 baseo = 0;
2344 break;
2345
2346 case 'f':
2347 baseo = 2;
2348 outro = 8;
2349 break;
2350 case 'F':
2351 baseo = 4;
2352 outro = 11;
2353 break;
2354 case 'x':
2355 baseo = 6;
2356 outro = 15;
2357 break;
2358 case 'p':
2359 baseo = 6;
2360 outro = -1;
2361 break;
2362 default:
2363 abort ();
2364 }
2365 if (!baseo)
2366 break;
2367
2368 /* We gotta put out some float. */
2369 if (op (&opP->disp) != O_big)
2370 {
2371 valueT val;
2372 int gencnt;
2373
2374 /* Can other cases happen here? */
2375 if (op (&opP->disp) != O_constant)
2376 abort ();
2377
2378 val = (valueT) offs (&opP->disp);
2379 gencnt = 0;
2380 do
2381 {
2382 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2383 val >>= LITTLENUM_NUMBER_OF_BITS;
2384 ++gencnt;
2385 }
2386 while (val != 0);
2387 offs (&opP->disp) = gencnt;
2388 }
2389 if (offs (&opP->disp) > 0)
2390 {
2391 if (offs (&opP->disp) > baseo)
2392 {
2393 as_warn (_("Bignum too big for %c format; truncated"),
2394 s[1]);
2395 offs (&opP->disp) = baseo;
2396 }
2397 baseo -= offs (&opP->disp);
2398 while (baseo--)
2399 addword (0);
2400 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2401 offs (&opP->disp)--;
2402 --wordp)
2403 addword (*wordp);
2404 break;
2405 }
2406 gen_to_words (words, baseo, (long) outro);
2407 for (wordp = words; baseo--; wordp++)
2408 addword (*wordp);
2409 break;
2410 case DREG:
2411 tmpreg = opP->reg - DATA; /* 0.dreg */
2412 break;
2413 case AREG:
2414 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2415 break;
2416 case AINDR:
2417 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2418 break;
2419 case ADEC:
2420 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2421 break;
2422 case AINC:
2423 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2424 break;
2425 case DISP:
2426
2427 nextword = get_num (&opP->disp, 90);
2428
2429 /* Convert mode 5 addressing with a zero offset into
2430 mode 2 addressing to reduce the instruction size by a
2431 word. */
2432 if (! isvar (&opP->disp)
2433 && (nextword == 0)
2434 && (opP->disp.size == SIZE_UNSPEC)
2435 && (opP->reg >= ADDR0)
2436 && (opP->reg <= ADDR7))
2437 {
2438 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2439 break;
2440 }
2441
2442 if (opP->reg == PC
2443 && ! isvar (&opP->disp)
2444 && m68k_abspcadd)
2445 {
2446 opP->disp.exp.X_op = O_symbol;
2447 opP->disp.exp.X_add_symbol =
2448 section_symbol (absolute_section);
2449 }
2450
2451 /* Force into index mode. Hope this works. */
2452
2453 /* We do the first bit for 32-bit displacements, and the
2454 second bit for 16 bit ones. It is possible that we
2455 should make the default be WORD instead of LONG, but
2456 I think that'd break GCC, so we put up with a little
2457 inefficiency for the sake of working output. */
2458
2459 if (!issword (nextword)
2460 || (isvar (&opP->disp)
2461 && ((opP->disp.size == SIZE_UNSPEC
2462 && flag_short_refs == 0
2463 && cpu_of_arch (current_architecture) >= m68020
2464 && ! arch_coldfire_p (current_architecture))
2465 || opP->disp.size == SIZE_LONG)))
2466 {
2467 if (cpu_of_arch (current_architecture) < m68020
2468 || arch_coldfire_p (current_architecture))
2469 opP->error =
2470 _("displacement too large for this architecture; needs 68020 or higher");
2471 if (opP->reg == PC)
2472 tmpreg = 0x3B; /* 7.3 */
2473 else
2474 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2475 if (isvar (&opP->disp))
2476 {
2477 if (opP->reg == PC)
2478 {
2479 if (opP->disp.size == SIZE_LONG
2480 #ifdef OBJ_ELF
2481 /* If the displacement needs pic
2482 relocation it cannot be relaxed. */
2483 || opP->disp.pic_reloc != pic_none
2484 #endif
2485 )
2486 {
2487 addword (0x0170);
2488 add_fix ('l', &opP->disp, 1, 2);
2489 }
2490 else
2491 {
2492 add_frag (adds (&opP->disp),
2493 SEXT (offs (&opP->disp)),
2494 TAB (PCREL1632, SZ_UNDEF));
2495 break;
2496 }
2497 }
2498 else
2499 {
2500 addword (0x0170);
2501 add_fix ('l', &opP->disp, 0, 0);
2502 }
2503 }
2504 else
2505 addword (0x0170);
2506 addword (nextword >> 16);
2507 }
2508 else
2509 {
2510 if (opP->reg == PC)
2511 tmpreg = 0x3A; /* 7.2 */
2512 else
2513 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2514
2515 if (isvar (&opP->disp))
2516 {
2517 if (opP->reg == PC)
2518 {
2519 add_fix ('w', &opP->disp, 1, 0);
2520 }
2521 else
2522 add_fix ('w', &opP->disp, 0, 0);
2523 }
2524 }
2525 addword (nextword);
2526 break;
2527
2528 case POST:
2529 case PRE:
2530 case BASE:
2531 nextword = 0;
2532 baseo = get_num (&opP->disp, 90);
2533 if (opP->mode == POST || opP->mode == PRE)
2534 outro = get_num (&opP->odisp, 90);
2535 /* Figure out the `addressing mode'.
2536 Also turn on the BASE_DISABLE bit, if needed. */
2537 if (opP->reg == PC || opP->reg == ZPC)
2538 {
2539 tmpreg = 0x3b; /* 7.3 */
2540 if (opP->reg == ZPC)
2541 nextword |= 0x80;
2542 }
2543 else if (opP->reg == 0)
2544 {
2545 nextword |= 0x80;
2546 tmpreg = 0x30; /* 6.garbage */
2547 }
2548 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2549 {
2550 nextword |= 0x80;
2551 tmpreg = 0x30 + opP->reg - ZADDR0;
2552 }
2553 else
2554 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2555
2556 siz1 = opP->disp.size;
2557 if (opP->mode == POST || opP->mode == PRE)
2558 siz2 = opP->odisp.size;
2559 else
2560 siz2 = SIZE_UNSPEC;
2561
2562 /* Index register stuff. */
2563 if (opP->index.reg != 0
2564 && opP->index.reg >= DATA
2565 && opP->index.reg <= ADDR7)
2566 {
2567 nextword |= (opP->index.reg - DATA) << 12;
2568
2569 if (opP->index.size == SIZE_LONG
2570 || (opP->index.size == SIZE_UNSPEC
2571 && m68k_index_width_default == SIZE_LONG))
2572 nextword |= 0x800;
2573
2574 if ((opP->index.scale != 1
2575 && cpu_of_arch (current_architecture) < m68020)
2576 || (opP->index.scale == 8
2577 && (arch_coldfire_p (current_architecture)
2578 && !arch_coldfire_fpu (current_architecture))))
2579 {
2580 opP->error =
2581 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2582 }
2583
2584 if (arch_coldfire_p (current_architecture)
2585 && opP->index.size == SIZE_WORD)
2586 opP->error = _("invalid index size for coldfire");
2587
2588 switch (opP->index.scale)
2589 {
2590 case 1:
2591 break;
2592 case 2:
2593 nextword |= 0x200;
2594 break;
2595 case 4:
2596 nextword |= 0x400;
2597 break;
2598 case 8:
2599 nextword |= 0x600;
2600 break;
2601 default:
2602 abort ();
2603 }
2604 /* IF its simple,
2605 GET US OUT OF HERE! */
2606
2607 /* Must be INDEX, with an index register. Address
2608 register cannot be ZERO-PC, and either :b was
2609 forced, or we know it will fit. For a 68000 or
2610 68010, force this mode anyways, because the
2611 larger modes aren't supported. */
2612 if (opP->mode == BASE
2613 && ((opP->reg >= ADDR0
2614 && opP->reg <= ADDR7)
2615 || opP->reg == PC))
2616 {
2617 if (siz1 == SIZE_BYTE
2618 || cpu_of_arch (current_architecture) < m68020
2619 || arch_coldfire_p (current_architecture)
2620 || (siz1 == SIZE_UNSPEC
2621 && ! isvar (&opP->disp)
2622 && issbyte (baseo)))
2623 {
2624 nextword += baseo & 0xff;
2625 addword (nextword);
2626 if (isvar (&opP->disp))
2627 {
2628 /* Do a byte relocation. If it doesn't
2629 fit (possible on m68000) let the
2630 fixup processing complain later. */
2631 if (opP->reg == PC)
2632 add_fix ('B', &opP->disp, 1, 1);
2633 else
2634 add_fix ('B', &opP->disp, 0, 0);
2635 }
2636 else if (siz1 != SIZE_BYTE)
2637 {
2638 if (siz1 != SIZE_UNSPEC)
2639 as_warn (_("Forcing byte displacement"));
2640 if (! issbyte (baseo))
2641 opP->error = _("byte displacement out of range");
2642 }
2643
2644 break;
2645 }
2646 else if (siz1 == SIZE_UNSPEC
2647 && opP->reg == PC
2648 && isvar (&opP->disp)
2649 && subs (&opP->disp) == NULL
2650 #ifdef OBJ_ELF
2651 /* If the displacement needs pic
2652 relocation it cannot be relaxed. */
2653 && opP->disp.pic_reloc == pic_none
2654 #endif
2655 )
2656 {
2657 /* The code in md_convert_frag_1 needs to be
2658 able to adjust nextword. Call frag_grow
2659 to ensure that we have enough space in
2660 the frag obstack to make all the bytes
2661 contiguous. */
2662 frag_grow (14);
2663 nextword += baseo & 0xff;
2664 addword (nextword);
2665 add_frag (adds (&opP->disp),
2666 SEXT (offs (&opP->disp)),
2667 TAB (PCINDEX, SZ_UNDEF));
2668
2669 break;
2670 }
2671 }
2672 }
2673 else
2674 {
2675 nextword |= 0x40; /* No index reg. */
2676 if (opP->index.reg >= ZDATA0
2677 && opP->index.reg <= ZDATA7)
2678 nextword |= (opP->index.reg - ZDATA0) << 12;
2679 else if (opP->index.reg >= ZADDR0
2680 || opP->index.reg <= ZADDR7)
2681 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2682 }
2683
2684 /* It isn't simple. */
2685
2686 if (cpu_of_arch (current_architecture) < m68020
2687 || arch_coldfire_p (current_architecture))
2688 opP->error =
2689 _("invalid operand mode for this architecture; needs 68020 or higher");
2690
2691 nextword |= 0x100;
2692 /* If the guy specified a width, we assume that it is
2693 wide enough. Maybe it isn't. If so, we lose. */
2694 switch (siz1)
2695 {
2696 case SIZE_UNSPEC:
2697 if (isvar (&opP->disp)
2698 ? m68k_rel32
2699 : ! issword (baseo))
2700 {
2701 siz1 = SIZE_LONG;
2702 nextword |= 0x30;
2703 }
2704 else if (! isvar (&opP->disp) && baseo == 0)
2705 nextword |= 0x10;
2706 else
2707 {
2708 nextword |= 0x20;
2709 siz1 = SIZE_WORD;
2710 }
2711 break;
2712 case SIZE_BYTE:
2713 as_warn (_(":b not permitted; defaulting to :w"));
2714 /* Fall through. */
2715 case SIZE_WORD:
2716 nextword |= 0x20;
2717 break;
2718 case SIZE_LONG:
2719 nextword |= 0x30;
2720 break;
2721 }
2722
2723 /* Figure out inner displacement stuff. */
2724 if (opP->mode == POST || opP->mode == PRE)
2725 {
2726 if (cpu_of_arch (current_architecture) & cpu32)
2727 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2728 switch (siz2)
2729 {
2730 case SIZE_UNSPEC:
2731 if (isvar (&opP->odisp)
2732 ? m68k_rel32
2733 : ! issword (outro))
2734 {
2735 siz2 = SIZE_LONG;
2736 nextword |= 0x3;
2737 }
2738 else if (! isvar (&opP->odisp) && outro == 0)
2739 nextword |= 0x1;
2740 else
2741 {
2742 nextword |= 0x2;
2743 siz2 = SIZE_WORD;
2744 }
2745 break;
2746 case 1:
2747 as_warn (_(":b not permitted; defaulting to :w"));
2748 /* Fall through. */
2749 case 2:
2750 nextword |= 0x2;
2751 break;
2752 case 3:
2753 nextword |= 0x3;
2754 break;
2755 }
2756 if (opP->mode == POST
2757 && (nextword & 0x40) == 0)
2758 nextword |= 0x04;
2759 }
2760 addword (nextword);
2761
2762 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2763 {
2764 if (opP->reg == PC || opP->reg == ZPC)
2765 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2766 else
2767 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2768 }
2769 if (siz1 == SIZE_LONG)
2770 addword (baseo >> 16);
2771 if (siz1 != SIZE_UNSPEC)
2772 addword (baseo);
2773
2774 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2775 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2776 if (siz2 == SIZE_LONG)
2777 addword (outro >> 16);
2778 if (siz2 != SIZE_UNSPEC)
2779 addword (outro);
2780
2781 break;
2782
2783 case ABSL:
2784 nextword = get_num (&opP->disp, 90);
2785 switch (opP->disp.size)
2786 {
2787 default:
2788 abort ();
2789 case SIZE_UNSPEC:
2790 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2791 {
2792 tmpreg = 0x38; /* 7.0 */
2793 addword (nextword);
2794 break;
2795 }
2796 if (isvar (&opP->disp)
2797 && !subs (&opP->disp)
2798 && adds (&opP->disp)
2799 #ifdef OBJ_ELF
2800 /* If the displacement needs pic relocation it
2801 cannot be relaxed. */
2802 && opP->disp.pic_reloc == pic_none
2803 #endif
2804 && !flag_long_jumps
2805 && !strchr ("~%&$?", s[0]))
2806 {
2807 tmpreg = 0x3A; /* 7.2 */
2808 add_frag (adds (&opP->disp),
2809 SEXT (offs (&opP->disp)),
2810 TAB (ABSTOPCREL, SZ_UNDEF));
2811 break;
2812 }
2813 /* Fall through into long. */
2814 case SIZE_LONG:
2815 if (isvar (&opP->disp))
2816 add_fix ('l', &opP->disp, 0, 0);
2817
2818 tmpreg = 0x39;/* 7.1 mode */
2819 addword (nextword >> 16);
2820 addword (nextword);
2821 break;
2822
2823 case SIZE_BYTE:
2824 as_bad (_("unsupported byte value; use a different suffix"));
2825 /* Fall through. */
2826
2827 case SIZE_WORD:
2828 if (isvar (&opP->disp))
2829 add_fix ('w', &opP->disp, 0, 0);
2830
2831 tmpreg = 0x38;/* 7.0 mode */
2832 addword (nextword);
2833 break;
2834 }
2835 break;
2836 case CONTROL:
2837 case FPREG:
2838 default:
2839 as_bad (_("unknown/incorrect operand"));
2840 /* abort (); */
2841 }
2842
2843 /* If s[0] is '4', then this is for the mac instructions
2844 that can have a trailing_ampersand set. If so, set 0x100
2845 bit on tmpreg so install_gen_operand can check for it and
2846 set the appropriate bit (word2, bit 5). */
2847 if (s[0] == '4')
2848 {
2849 if (opP->trailing_ampersand)
2850 tmpreg |= 0x100;
2851 }
2852 install_gen_operand (s[1], tmpreg);
2853 break;
2854
2855 case '#':
2856 case '^':
2857 switch (s[1])
2858 { /* JF: I hate floating point! */
2859 case 'j':
2860 tmpreg = 70;
2861 break;
2862 case '8':
2863 tmpreg = 20;
2864 break;
2865 case 'C':
2866 tmpreg = 50;
2867 break;
2868 case '3':
2869 default:
2870 tmpreg = 90;
2871 break;
2872 }
2873 tmpreg = get_num (&opP->disp, tmpreg);
2874 if (isvar (&opP->disp))
2875 add_fix (s[1], &opP->disp, 0, 0);
2876 switch (s[1])
2877 {
2878 case 'b': /* Danger: These do no check for
2879 certain types of overflow.
2880 user beware! */
2881 if (!isbyte (tmpreg))
2882 opP->error = _("out of range");
2883 insop (tmpreg, opcode);
2884 if (isvar (&opP->disp))
2885 the_ins.reloc[the_ins.nrel - 1].n =
2886 (opcode->m_codenum) * 2 + 1;
2887 break;
2888 case 'B':
2889 if (!issbyte (tmpreg))
2890 opP->error = _("out of range");
2891 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2892 if (isvar (&opP->disp))
2893 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2894 break;
2895 case 'w':
2896 if (!isword (tmpreg))
2897 opP->error = _("out of range");
2898 insop (tmpreg, opcode);
2899 if (isvar (&opP->disp))
2900 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2901 break;
2902 case 'W':
2903 if (!issword (tmpreg))
2904 opP->error = _("out of range");
2905 insop (tmpreg, opcode);
2906 if (isvar (&opP->disp))
2907 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2908 break;
2909 case 'l':
2910 /* Because of the way insop works, we put these two out
2911 backwards. */
2912 insop (tmpreg, opcode);
2913 insop (tmpreg >> 16, opcode);
2914 if (isvar (&opP->disp))
2915 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2916 break;
2917 case '3':
2918 tmpreg &= 0xFF;
2919 case '8':
2920 case 'C':
2921 case 'j':
2922 install_operand (s[1], tmpreg);
2923 break;
2924 default:
2925 abort ();
2926 }
2927 break;
2928
2929 case '+':
2930 case '-':
2931 case 'A':
2932 case 'a':
2933 install_operand (s[1], opP->reg - ADDR);
2934 break;
2935
2936 case 'B':
2937 tmpreg = get_num (&opP->disp, 90);
2938
2939 switch (s[1])
2940 {
2941 case 'B':
2942 add_fix ('B', &opP->disp, 1, -1);
2943 break;
2944 case 'W':
2945 add_fix ('w', &opP->disp, 1, 0);
2946 addword (0);
2947 break;
2948 case 'L':
2949 long_branch:
2950 the_ins.opcode[0] |= 0xff;
2951 add_fix ('l', &opP->disp, 1, 0);
2952 addword (0);
2953 addword (0);
2954 break;
2955 case 'g': /* Conditional branch */
2956 have_disp = HAVE_LONG_CALL (current_architecture);
2957 goto var_branch;
2958
2959 case 'b': /* Unconditional branch */
2960 have_disp = HAVE_LONG_BRANCH (current_architecture);
2961 goto var_branch;
2962
2963 case 's': /* Unconditional subroutine */
2964 have_disp = HAVE_LONG_CALL (current_architecture);
2965
2966 var_branch:
2967 if (subs (&opP->disp) /* We can't relax it. */
2968 #ifdef OBJ_ELF
2969 /* If the displacement needs pic relocation it cannot be
2970 relaxed. */
2971 || opP->disp.pic_reloc != pic_none
2972 #endif
2973 || 0)
2974 {
2975 if (!have_disp)
2976 as_warn (_("Can't use long branches on this architecture"));
2977 goto long_branch;
2978 }
2979
2980 /* This could either be a symbol, or an absolute
2981 address. If it's an absolute address, turn it into
2982 an absolute jump right here and keep it out of the
2983 relaxer. */
2984 if (adds (&opP->disp) == 0)
2985 {
2986 if (the_ins.opcode[0] == 0x6000) /* jbra */
2987 the_ins.opcode[0] = 0x4EF9;
2988 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2989 the_ins.opcode[0] = 0x4EB9;
2990 else /* jCC */
2991 {
2992 the_ins.opcode[0] ^= 0x0100;
2993 the_ins.opcode[0] |= 0x0006;
2994 addword (0x4EF9);
2995 }
2996 add_fix ('l', &opP->disp, 0, 0);
2997 addword (0);
2998 addword (0);
2999 break;
3000 }
3001
3002 /* Now we know it's going into the relaxer. Now figure
3003 out which mode. We try in this order of preference:
3004 long branch, absolute jump, byte/word branches only. */
3005 if (have_disp)
3006 add_frag (adds (&opP->disp),
3007 SEXT (offs (&opP->disp)),
3008 TAB (BRANCHBWL, SZ_UNDEF));
3009 else if (! flag_keep_pcrel)
3010 {
3011 if ((the_ins.opcode[0] == 0x6000)
3012 || (the_ins.opcode[0] == 0x6100))
3013 add_frag (adds (&opP->disp),
3014 SEXT (offs (&opP->disp)),
3015 TAB (BRABSJUNC, SZ_UNDEF));
3016 else
3017 add_frag (adds (&opP->disp),
3018 SEXT (offs (&opP->disp)),
3019 TAB (BRABSJCOND, SZ_UNDEF));
3020 }
3021 else
3022 add_frag (adds (&opP->disp),
3023 SEXT (offs (&opP->disp)),
3024 TAB (BRANCHBW, SZ_UNDEF));
3025 break;
3026 case 'w':
3027 if (isvar (&opP->disp))
3028 {
3029 /* Check for DBcc instructions. We can relax them,
3030 but only if we have long branches and/or absolute
3031 jumps. */
3032 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3033 && (HAVE_LONG_BRANCH (current_architecture)
3034 || ! flag_keep_pcrel))
3035 {
3036 if (HAVE_LONG_BRANCH (current_architecture))
3037 add_frag (adds (&opP->disp),
3038 SEXT (offs (&opP->disp)),
3039 TAB (DBCCLBR, SZ_UNDEF));
3040 else
3041 add_frag (adds (&opP->disp),
3042 SEXT (offs (&opP->disp)),
3043 TAB (DBCCABSJ, SZ_UNDEF));
3044 break;
3045 }
3046 add_fix ('w', &opP->disp, 1, 0);
3047 }
3048 addword (0);
3049 break;
3050 case 'C': /* Fixed size LONG coproc branches. */
3051 add_fix ('l', &opP->disp, 1, 0);
3052 addword (0);
3053 addword (0);
3054 break;
3055 case 'c': /* Var size Coprocesssor branches. */
3056 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3057 {
3058 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3059 add_fix ('l', &opP->disp, 1, 0);
3060 addword (0);
3061 addword (0);
3062 }
3063 else
3064 add_frag (adds (&opP->disp),
3065 SEXT (offs (&opP->disp)),
3066 TAB (FBRANCH, SZ_UNDEF));
3067 break;
3068 default:
3069 abort ();
3070 }
3071 break;
3072
3073 case 'C': /* Ignore it. */
3074 break;
3075
3076 case 'd': /* JF this is a kludge. */
3077 install_operand ('s', opP->reg - ADDR);
3078 tmpreg = get_num (&opP->disp, 90);
3079 if (!issword (tmpreg))
3080 {
3081 as_warn (_("Expression out of range, using 0"));
3082 tmpreg = 0;
3083 }
3084 addword (tmpreg);
3085 break;
3086
3087 case 'D':
3088 install_operand (s[1], opP->reg - DATA);
3089 break;
3090
3091 case 'e': /* EMAC ACCx, reg/reg. */
3092 install_operand (s[1], opP->reg - ACC);
3093 break;
3094
3095 case 'E': /* Ignore it. */
3096 break;
3097
3098 case 'F':
3099 install_operand (s[1], opP->reg - FP0);
3100 break;
3101
3102 case 'g': /* EMAC ACCEXTx. */
3103 install_operand (s[1], opP->reg - ACCEXT01);
3104 break;
3105
3106 case 'G': /* Ignore it. */
3107 case 'H':
3108 break;
3109
3110 case 'I':
3111 tmpreg = opP->reg - COP0;
3112 install_operand (s[1], tmpreg);
3113 break;
3114
3115 case 'i': /* MAC/EMAC scale factor. */
3116 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3117 break;
3118
3119 case 'J': /* JF foo. */
3120 switch (opP->reg)
3121 {
3122 case SFC:
3123 tmpreg = 0x000;
3124 break;
3125 case DFC:
3126 tmpreg = 0x001;
3127 break;
3128 case CACR:
3129 tmpreg = 0x002;
3130 break;
3131 case TC:
3132 case ASID:
3133 tmpreg = 0x003;
3134 break;
3135 case ACR0:
3136 case ITT0:
3137 tmpreg = 0x004;
3138 break;
3139 case ACR1:
3140 case ITT1:
3141 tmpreg = 0x005;
3142 break;
3143 case ACR2:
3144 case DTT0:
3145 tmpreg = 0x006;
3146 break;
3147 case ACR3:
3148 case DTT1:
3149 tmpreg = 0x007;
3150 break;
3151 case BUSCR:
3152 case MMUBAR:
3153 tmpreg = 0x008;
3154 break;
3155
3156 case USP:
3157 tmpreg = 0x800;
3158 break;
3159 case VBR:
3160 tmpreg = 0x801;
3161 break;
3162 case CAAR:
3163 tmpreg = 0x802;
3164 break;
3165 case MSP:
3166 tmpreg = 0x803;
3167 break;
3168 case ISP:
3169 tmpreg = 0x804;
3170 break;
3171 case MMUSR:
3172 tmpreg = 0x805;
3173 break;
3174 case URP:
3175 tmpreg = 0x806;
3176 break;
3177 case SRP:
3178 tmpreg = 0x807;
3179 break;
3180 case PCR:
3181 tmpreg = 0x808;
3182 break;
3183 case ROMBAR:
3184 case ROMBAR0:
3185 tmpreg = 0xC00;
3186 break;
3187 case ROMBAR1:
3188 tmpreg = 0xC01;
3189 break;
3190 case FLASHBAR:
3191 case RAMBAR0:
3192 case RAMBAR_ALT:
3193 tmpreg = 0xC04;
3194 break;
3195 case RAMBAR:
3196 case RAMBAR1:
3197 tmpreg = 0xC05;
3198 break;
3199 case MPCR:
3200 tmpreg = 0xC0C;
3201 break;
3202 case EDRAMBAR:
3203 tmpreg = 0xC0D;
3204 break;
3205 case MBAR0:
3206 case MBAR2:
3207 case SECMBAR:
3208 tmpreg = 0xC0E;
3209 break;
3210 case MBAR1:
3211 case MBAR:
3212 tmpreg = 0xC0F;
3213 break;
3214 case PCR1U0:
3215 tmpreg = 0xD02;
3216 break;
3217 case PCR1L0:
3218 tmpreg = 0xD03;
3219 break;
3220 case PCR2U0:
3221 tmpreg = 0xD04;
3222 break;
3223 case PCR2L0:
3224 tmpreg = 0xD05;
3225 break;
3226 case PCR3U0:
3227 tmpreg = 0xD06;
3228 break;
3229 case PCR3L0:
3230 tmpreg = 0xD07;
3231 break;
3232 case PCR1L1:
3233 tmpreg = 0xD0A;
3234 break;
3235 case PCR1U1:
3236 tmpreg = 0xD0B;
3237 break;
3238 case PCR2L1:
3239 tmpreg = 0xD0C;
3240 break;
3241 case PCR2U1:
3242 tmpreg = 0xD0D;
3243 break;
3244 case PCR3L1:
3245 tmpreg = 0xD0E;
3246 break;
3247 case PCR3U1:
3248 tmpreg = 0xD0F;
3249 break;
3250 case CAC:
3251 tmpreg = 0xFFE;
3252 break;
3253 case MBB:
3254 tmpreg = 0xFFF;
3255 break;
3256 default:
3257 abort ();
3258 }
3259 install_operand (s[1], tmpreg);
3260 break;
3261
3262 case 'k':
3263 tmpreg = get_num (&opP->disp, 55);
3264 install_operand (s[1], tmpreg & 0x7f);
3265 break;
3266
3267 case 'l':
3268 tmpreg = opP->mask;
3269 if (s[1] == 'w')
3270 {
3271 if (tmpreg & 0x7FF0000)
3272 as_bad (_("Floating point register in register list"));
3273 insop (reverse_16_bits (tmpreg), opcode);
3274 }
3275 else
3276 {
3277 if (tmpreg & 0x700FFFF)
3278 as_bad (_("Wrong register in floating-point reglist"));
3279 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3280 }
3281 break;
3282
3283 case 'L':
3284 tmpreg = opP->mask;
3285 if (s[1] == 'w')
3286 {
3287 if (tmpreg & 0x7FF0000)
3288 as_bad (_("Floating point register in register list"));
3289 insop (tmpreg, opcode);
3290 }
3291 else if (s[1] == '8')
3292 {
3293 if (tmpreg & 0x0FFFFFF)
3294 as_bad (_("incorrect register in reglist"));
3295 install_operand (s[1], tmpreg >> 24);
3296 }
3297 else
3298 {
3299 if (tmpreg & 0x700FFFF)
3300 as_bad (_("wrong register in floating-point reglist"));
3301 else
3302 install_operand (s[1], tmpreg >> 16);
3303 }
3304 break;
3305
3306 case 'M':
3307 install_operand (s[1], get_num (&opP->disp, 60));
3308 break;
3309
3310 case 'O':
3311 tmpreg = ((opP->mode == DREG)
3312 ? 0x20 + (int) (opP->reg - DATA)
3313 : (get_num (&opP->disp, 40) & 0x1F));
3314 install_operand (s[1], tmpreg);
3315 break;
3316
3317 case 'Q':
3318 tmpreg = get_num (&opP->disp, 10);
3319 if (tmpreg == 8)
3320 tmpreg = 0;
3321 install_operand (s[1], tmpreg);
3322 break;
3323
3324 case 'R':
3325 /* This depends on the fact that ADDR registers are eight
3326 more than their corresponding DATA regs, so the result
3327 will have the ADDR_REG bit set. */
3328 install_operand (s[1], opP->reg - DATA);
3329 break;
3330
3331 case 'r':
3332 if (opP->mode == AINDR)
3333 install_operand (s[1], opP->reg - DATA);
3334 else
3335 install_operand (s[1], opP->index.reg - DATA);
3336 break;
3337
3338 case 's':
3339 if (opP->reg == FPI)
3340 tmpreg = 0x1;
3341 else if (opP->reg == FPS)
3342 tmpreg = 0x2;
3343 else if (opP->reg == FPC)
3344 tmpreg = 0x4;
3345 else
3346 abort ();
3347 install_operand (s[1], tmpreg);
3348 break;
3349
3350 case 'S': /* Ignore it. */
3351 break;
3352
3353 case 'T':
3354 install_operand (s[1], get_num (&opP->disp, 30));
3355 break;
3356
3357 case 'U': /* Ignore it. */
3358 break;
3359
3360 case 'c':
3361 switch (opP->reg)
3362 {
3363 case NC:
3364 tmpreg = 0;
3365 break;
3366 case DC:
3367 tmpreg = 1;
3368 break;
3369 case IC:
3370 tmpreg = 2;
3371 break;
3372 case BC:
3373 tmpreg = 3;
3374 break;
3375 default:
3376 as_fatal (_("failed sanity check"));
3377 } /* switch on cache token. */
3378 install_operand (s[1], tmpreg);
3379 break;
3380 #ifndef NO_68851
3381 /* JF: These are out of order, I fear. */
3382 case 'f':
3383 switch (opP->reg)
3384 {
3385 case SFC:
3386 tmpreg = 0;
3387 break;
3388 case DFC:
3389 tmpreg = 1;
3390 break;
3391 default:
3392 abort ();
3393 }
3394 install_operand (s[1], tmpreg);
3395 break;
3396
3397 case '0':
3398 case '1':
3399 case '2':
3400 switch (opP->reg)
3401 {
3402 case TC:
3403 tmpreg = 0;
3404 break;
3405 case CAL:
3406 tmpreg = 4;
3407 break;
3408 case VAL:
3409 tmpreg = 5;
3410 break;
3411 case SCC:
3412 tmpreg = 6;
3413 break;
3414 case AC:
3415 tmpreg = 7;
3416 break;
3417 default:
3418 abort ();
3419 }
3420 install_operand (s[1], tmpreg);
3421 break;
3422
3423 case 'V':
3424 if (opP->reg == VAL)
3425 break;
3426 abort ();
3427
3428 case 'W':
3429 switch (opP->reg)
3430 {
3431 case DRP:
3432 tmpreg = 1;
3433 break;
3434 case SRP:
3435 tmpreg = 2;
3436 break;
3437 case CRP:
3438 tmpreg = 3;
3439 break;
3440 default:
3441 abort ();
3442 }
3443 install_operand (s[1], tmpreg);
3444 break;
3445
3446 case 'X':
3447 switch (opP->reg)
3448 {
3449 case BAD:
3450 case BAD + 1:
3451 case BAD + 2:
3452 case BAD + 3:
3453 case BAD + 4:
3454 case BAD + 5:
3455 case BAD + 6:
3456 case BAD + 7:
3457 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3458 break;
3459
3460 case BAC:
3461 case BAC + 1:
3462 case BAC + 2:
3463 case BAC + 3:
3464 case BAC + 4:
3465 case BAC + 5:
3466 case BAC + 6:
3467 case BAC + 7:
3468 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3469 break;
3470
3471 default:
3472 abort ();
3473 }
3474 install_operand (s[1], tmpreg);
3475 break;
3476 case 'Y':
3477 know (opP->reg == PSR);
3478 break;
3479 case 'Z':
3480 know (opP->reg == PCSR);
3481 break;
3482 #endif /* m68851 */
3483 case '3':
3484 switch (opP->reg)
3485 {
3486 case TT0:
3487 tmpreg = 2;
3488 break;
3489 case TT1:
3490 tmpreg = 3;
3491 break;
3492 default:
3493 abort ();
3494 }
3495 install_operand (s[1], tmpreg);
3496 break;
3497 case 't':
3498 tmpreg = get_num (&opP->disp, 20);
3499 install_operand (s[1], tmpreg);
3500 break;
3501 case '_': /* used only for move16 absolute 32-bit address. */
3502 if (isvar (&opP->disp))
3503 add_fix ('l', &opP->disp, 0, 0);
3504 tmpreg = get_num (&opP->disp, 90);
3505 addword (tmpreg >> 16);
3506 addword (tmpreg & 0xFFFF);
3507 break;
3508 case 'u':
3509 install_operand (s[1], opP->reg - DATA0L);
3510 opP->reg -= (DATA0L);
3511 opP->reg &= 0x0F; /* remove upper/lower bit. */
3512 break;
3513 case 'x':
3514 tmpreg = get_num (&opP->disp, 80);
3515 if (tmpreg == -1)
3516 tmpreg = 0;
3517 install_operand (s[1], tmpreg);
3518 break;
3519 case 'j':
3520 tmpreg = get_num (&opP->disp, 10);
3521 install_operand (s[1], tmpreg - 1);
3522 break;
3523 case 'K':
3524 tmpreg = get_num (&opP->disp, 65);
3525 install_operand (s[1], tmpreg);
3526 break;
3527 default:
3528 abort ();
3529 }
3530 }
3531
3532 /* By the time whe get here (FINALLY) the_ins contains the complete
3533 instruction, ready to be emitted. . . */
3534 }
3535
3536 static int
3537 reverse_16_bits (int in)
3538 {
3539 int out = 0;
3540 int n;
3541
3542 static int mask[16] =
3543 {
3544 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3545 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3546 };
3547 for (n = 0; n < 16; n++)
3548 {
3549 if (in & mask[n])
3550 out |= mask[15 - n];
3551 }
3552 return out;
3553 } /* reverse_16_bits() */
3554
3555 static int
3556 reverse_8_bits (int in)
3557 {
3558 int out = 0;
3559 int n;
3560
3561 static int mask[8] =
3562 {
3563 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3564 };
3565
3566 for (n = 0; n < 8; n++)
3567 {
3568 if (in & mask[n])
3569 out |= mask[7 - n];
3570 }
3571 return out;
3572 } /* reverse_8_bits() */
3573
3574 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3575 (that value is chosen in the frag_var call in md_assemble). TYPE
3576 is the subtype of the frag to be generated; its primary type is
3577 rs_machine_dependent.
3578
3579 The TYPE parameter is also used by md_convert_frag_1 and
3580 md_estimate_size_before_relax. The appropriate type of fixup will
3581 be emitted by md_convert_frag_1.
3582
3583 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3584 static void
3585 install_operand (int mode, int val)
3586 {
3587 switch (mode)
3588 {
3589 case 's':
3590 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3591 break;
3592 case 'd':
3593 the_ins.opcode[0] |= val << 9;
3594 break;
3595 case 'E':
3596 the_ins.opcode[1] |= val << 9;
3597 break;
3598 case '1':
3599 the_ins.opcode[1] |= val << 12;
3600 break;
3601 case '2':
3602 the_ins.opcode[1] |= val << 6;
3603 break;
3604 case '3':
3605 the_ins.opcode[1] |= val;
3606 break;
3607 case '4':
3608 the_ins.opcode[2] |= val << 12;
3609 break;
3610 case '5':
3611 the_ins.opcode[2] |= val << 6;
3612 break;
3613 case '6':
3614 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3615 three words long! */
3616 the_ins.numo++;
3617 the_ins.opcode[2] |= val;
3618 break;
3619 case '7':
3620 the_ins.opcode[1] |= val << 7;
3621 break;
3622 case '8':
3623 the_ins.opcode[1] |= val << 10;
3624 break;
3625 #ifndef NO_68851
3626 case '9':
3627 the_ins.opcode[1] |= val << 5;
3628 break;
3629 #endif
3630
3631 case 't':
3632 the_ins.opcode[1] |= (val << 10) | (val << 7);
3633 break;
3634 case 'D':
3635 the_ins.opcode[1] |= (val << 12) | val;
3636 break;
3637 case 'g':
3638 the_ins.opcode[0] |= val = 0xff;
3639 break;
3640 case 'i':
3641 the_ins.opcode[0] |= val << 9;
3642 break;
3643 case 'C':
3644 the_ins.opcode[1] |= val;
3645 break;
3646 case 'j':
3647 the_ins.opcode[1] |= val;
3648 the_ins.numo++; /* What a hack. */
3649 break;
3650 case 'k':
3651 the_ins.opcode[1] |= val << 4;
3652 break;
3653 case 'b':
3654 case 'w':
3655 case 'W':
3656 case 'l':
3657 break;
3658 case 'e':
3659 the_ins.opcode[0] |= (val << 6);
3660 break;
3661 case 'L':
3662 the_ins.opcode[1] = (val >> 16);
3663 the_ins.opcode[2] = val & 0xffff;
3664 break;
3665 case 'm':
3666 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3667 the_ins.opcode[0] |= ((val & 0x7) << 9);
3668 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3669 break;
3670 case 'n': /* MAC/EMAC Rx on !load. */
3671 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3672 the_ins.opcode[0] |= ((val & 0x7) << 9);
3673 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3674 break;
3675 case 'o': /* MAC/EMAC Rx on load. */
3676 the_ins.opcode[1] |= val << 12;
3677 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3678 break;
3679 case 'M': /* MAC/EMAC Ry on !load. */
3680 the_ins.opcode[0] |= (val & 0xF);
3681 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3682 break;
3683 case 'N': /* MAC/EMAC Ry on load. */
3684 the_ins.opcode[1] |= (val & 0xF);
3685 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3686 break;
3687 case 'h':
3688 the_ins.opcode[1] |= ((val != 1) << 10);
3689 break;
3690 case 'F':
3691 the_ins.opcode[0] |= ((val & 0x3) << 9);
3692 break;
3693 case 'f':
3694 the_ins.opcode[0] |= ((val & 0x3) << 0);
3695 break;
3696 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3697 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3698 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3699 break;
3700 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3701 the_ins.opcode[0] |= ((val & 0x1) << 7);
3702 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3703 break;
3704 case 'I':
3705 the_ins.opcode[1] |= ((val & 0x3) << 9);
3706 break;
3707 case ']':
3708 the_ins.opcode[0] |= (val & 0x1) <<10;
3709 break;
3710 case 'c':
3711 default:
3712 as_fatal (_("failed sanity check."));
3713 }
3714 }
3715
3716 static void
3717 install_gen_operand (int mode, int val)
3718 {
3719 switch (mode)
3720 {
3721 case '/': /* Special for mask loads for mac/msac insns with
3722 possible mask; trailing_ampersend set in bit 8. */
3723 the_ins.opcode[0] |= (val & 0x3f);
3724 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3725 break;
3726 case 's':
3727 the_ins.opcode[0] |= val;
3728 break;
3729 case 'd':
3730 /* This is a kludge!!! */
3731 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3732 break;
3733 case 'b':
3734 case 'w':
3735 case 'l':
3736 case 'f':
3737 case 'F':
3738 case 'x':
3739 case 'p':
3740 the_ins.opcode[0] |= val;
3741 break;
3742 /* more stuff goes here. */
3743 default:
3744 as_fatal (_("failed sanity check."));
3745 }
3746 }
3747
3748 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3749 then deal with the bitfield hack. */
3750
3751 static char *
3752 crack_operand (char *str, struct m68k_op *opP)
3753 {
3754 register int parens;
3755 register int c;
3756 register char *beg_str;
3757 int inquote = 0;
3758
3759 if (!str)
3760 {
3761 return str;
3762 }
3763 beg_str = str;
3764 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3765 {
3766 if (! inquote)
3767 {
3768 if (*str == '(')
3769 parens++;
3770 else if (*str == ')')
3771 {
3772 if (!parens)
3773 { /* ERROR. */
3774 opP->error = _("Extra )");
3775 return str;
3776 }
3777 --parens;
3778 }
3779 }
3780 if (flag_mri && *str == '\'')
3781 inquote = ! inquote;
3782 }
3783 if (!*str && parens)
3784 { /* ERROR. */
3785 opP->error = _("Missing )");
3786 return str;
3787 }
3788 c = *str;
3789 *str = '\0';
3790 if (m68k_ip_op (beg_str, opP) != 0)
3791 {
3792 *str = c;
3793 return str;
3794 }
3795 *str = c;
3796 if (c == '}')
3797 c = *++str; /* JF bitfield hack. */
3798 if (c)
3799 {
3800 c = *++str;
3801 if (!c)
3802 as_bad (_("Missing operand"));
3803 }
3804
3805 /* Detect MRI REG symbols and convert them to REGLSTs. */
3806 if (opP->mode == CONTROL && (int)opP->reg < 0)
3807 {
3808 opP->mode = REGLST;
3809 opP->mask = ~(int)opP->reg;
3810 opP->reg = 0;
3811 }
3812
3813 return str;
3814 }
3815
3816 /* This is the guts of the machine-dependent assembler. STR points to a
3817 machine dependent instruction. This function is supposed to emit
3818 the frags/bytes it assembles to.
3819 */
3820
3821 static void
3822 insert_reg (const char *regname, int regnum)
3823 {
3824 char buf[100];
3825 int i;
3826
3827 #ifdef REGISTER_PREFIX
3828 if (!flag_reg_prefix_optional)
3829 {
3830 buf[0] = REGISTER_PREFIX;
3831 strcpy (buf + 1, regname);
3832 regname = buf;
3833 }
3834 #endif
3835
3836 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3837 &zero_address_frag));
3838
3839 for (i = 0; regname[i]; i++)
3840 buf[i] = TOUPPER (regname[i]);
3841 buf[i] = '\0';
3842
3843 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3844 &zero_address_frag));
3845 }
3846
3847 struct init_entry
3848 {
3849 const char *name;
3850 int number;
3851 };
3852
3853 static const struct init_entry init_table[] =
3854 {
3855 { "d0", DATA0 },
3856 { "d1", DATA1 },
3857 { "d2", DATA2 },
3858 { "d3", DATA3 },
3859 { "d4", DATA4 },
3860 { "d5", DATA5 },
3861 { "d6", DATA6 },
3862 { "d7", DATA7 },
3863 { "a0", ADDR0 },
3864 { "a1", ADDR1 },
3865 { "a2", ADDR2 },
3866 { "a3", ADDR3 },
3867 { "a4", ADDR4 },
3868 { "a5", ADDR5 },
3869 { "a6", ADDR6 },
3870 { "fp", ADDR6 },
3871 { "a7", ADDR7 },
3872 { "sp", ADDR7 },
3873 { "ssp", ADDR7 },
3874 { "fp0", FP0 },
3875 { "fp1", FP1 },
3876 { "fp2", FP2 },
3877 { "fp3", FP3 },
3878 { "fp4", FP4 },
3879 { "fp5", FP5 },
3880 { "fp6", FP6 },
3881 { "fp7", FP7 },
3882 { "fpi", FPI },
3883 { "fpiar", FPI },
3884 { "fpc", FPI },
3885 { "fps", FPS },
3886 { "fpsr", FPS },
3887 { "fpc", FPC },
3888 { "fpcr", FPC },
3889 { "control", FPC },
3890 { "status", FPS },
3891 { "iaddr", FPI },
3892
3893 { "cop0", COP0 },
3894 { "cop1", COP1 },
3895 { "cop2", COP2 },
3896 { "cop3", COP3 },
3897 { "cop4", COP4 },
3898 { "cop5", COP5 },
3899 { "cop6", COP6 },
3900 { "cop7", COP7 },
3901 { "pc", PC },
3902 { "zpc", ZPC },
3903 { "sr", SR },
3904
3905 { "ccr", CCR },
3906 { "cc", CCR },
3907
3908 { "acc", ACC },
3909 { "acc0", ACC },
3910 { "acc1", ACC1 },
3911 { "acc2", ACC2 },
3912 { "acc3", ACC3 },
3913 { "accext01", ACCEXT01 },
3914 { "accext23", ACCEXT23 },
3915 { "macsr", MACSR },
3916 { "mask", MASK },
3917
3918 /* Control registers. */
3919 { "sfc", SFC }, /* Source Function Code. */
3920 { "sfcr", SFC },
3921 { "dfc", DFC }, /* Destination Function Code. */
3922 { "dfcr", DFC },
3923 { "cacr", CACR }, /* Cache Control Register. */
3924 { "caar", CAAR }, /* Cache Address Register. */
3925
3926 { "usp", USP }, /* User Stack Pointer. */
3927 { "vbr", VBR }, /* Vector Base Register. */
3928 { "msp", MSP }, /* Master Stack Pointer. */
3929 { "isp", ISP }, /* Interrupt Stack Pointer. */
3930
3931 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3932 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3933 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3934 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3935
3936 /* 68ec040 versions of same */
3937 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3938 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3939 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3940 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3941
3942 /* Coldfire versions of same. The ColdFire programmer's reference
3943 manual indicated that the order is 2,3,0,1, but Ken Rose
3944 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3945 { "acr0", ACR0 }, /* Access Control Unit 0. */
3946 { "acr1", ACR1 }, /* Access Control Unit 1. */
3947 { "acr2", ACR2 }, /* Access Control Unit 2. */
3948 { "acr3", ACR3 }, /* Access Control Unit 3. */
3949
3950 { "tc", TC }, /* MMU Translation Control Register. */
3951 { "tcr", TC },
3952 { "asid", ASID },
3953
3954 { "mmusr", MMUSR }, /* MMU Status Register. */
3955 { "srp", SRP }, /* User Root Pointer. */
3956 { "urp", URP }, /* Supervisor Root Pointer. */
3957
3958 { "buscr", BUSCR },
3959 { "mmubar", MMUBAR },
3960 { "pcr", PCR },
3961
3962 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3963 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3964 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3965 { "mbar", MBAR }, /* Module Base Address Register. */
3966
3967 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3968 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3969 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3970 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3971 { "mpcr", MPCR }, /* mcfv4e registers. */
3972 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3973 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3974 { "asid", TC }, /* mcfv4e registers. */
3975 { "mmubar", BUSCR }, /* mcfv4e registers. */
3976 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3977 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3978 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3979 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3980 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3981 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3982 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3983 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3984 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3985 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3986 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3987 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3988
3989 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3990 { "rambar", RAMBAR }, /* mcf528x registers. */
3991
3992 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3993
3994 { "cac", CAC }, /* fido registers. */
3995 { "mbb", MBB }, /* fido registers. */
3996 /* End of control registers. */
3997
3998 { "ac", AC },
3999 { "bc", BC },
4000 { "cal", CAL },
4001 { "crp", CRP },
4002 { "drp", DRP },
4003 { "pcsr", PCSR },
4004 { "psr", PSR },
4005 { "scc", SCC },
4006 { "val", VAL },
4007 { "bad0", BAD0 },
4008 { "bad1", BAD1 },
4009 { "bad2", BAD2 },
4010 { "bad3", BAD3 },
4011 { "bad4", BAD4 },
4012 { "bad5", BAD5 },
4013 { "bad6", BAD6 },
4014 { "bad7", BAD7 },
4015 { "bac0", BAC0 },
4016 { "bac1", BAC1 },
4017 { "bac2", BAC2 },
4018 { "bac3", BAC3 },
4019 { "bac4", BAC4 },
4020 { "bac5", BAC5 },
4021 { "bac6", BAC6 },
4022 { "bac7", BAC7 },
4023
4024 { "ic", IC },
4025 { "dc", DC },
4026 { "nc", NC },
4027
4028 { "tt0", TT0 },
4029 { "tt1", TT1 },
4030 /* 68ec030 versions of same. */
4031 { "ac0", TT0 },
4032 { "ac1", TT1 },
4033 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4034 { "acusr", PSR },
4035
4036 /* Suppressed data and address registers. */
4037 { "zd0", ZDATA0 },
4038 { "zd1", ZDATA1 },
4039 { "zd2", ZDATA2 },
4040 { "zd3", ZDATA3 },
4041 { "zd4", ZDATA4 },
4042 { "zd5", ZDATA5 },
4043 { "zd6", ZDATA6 },
4044 { "zd7", ZDATA7 },
4045 { "za0", ZADDR0 },
4046 { "za1", ZADDR1 },
4047 { "za2", ZADDR2 },
4048 { "za3", ZADDR3 },
4049 { "za4", ZADDR4 },
4050 { "za5", ZADDR5 },
4051 { "za6", ZADDR6 },
4052 { "za7", ZADDR7 },
4053
4054 /* Upper and lower data and address registers, used by macw and msacw. */
4055 { "d0l", DATA0L },
4056 { "d1l", DATA1L },
4057 { "d2l", DATA2L },
4058 { "d3l", DATA3L },
4059 { "d4l", DATA4L },
4060 { "d5l", DATA5L },
4061 { "d6l", DATA6L },
4062 { "d7l", DATA7L },
4063
4064 { "a0l", ADDR0L },
4065 { "a1l", ADDR1L },
4066 { "a2l", ADDR2L },
4067 { "a3l", ADDR3L },
4068 { "a4l", ADDR4L },
4069 { "a5l", ADDR5L },
4070 { "a6l", ADDR6L },
4071 { "a7l", ADDR7L },
4072
4073 { "d0u", DATA0U },
4074 { "d1u", DATA1U },
4075 { "d2u", DATA2U },
4076 { "d3u", DATA3U },
4077 { "d4u", DATA4U },
4078 { "d5u", DATA5U },
4079 { "d6u", DATA6U },
4080 { "d7u", DATA7U },
4081
4082 { "a0u", ADDR0U },
4083 { "a1u", ADDR1U },
4084 { "a2u", ADDR2U },
4085 { "a3u", ADDR3U },
4086 { "a4u", ADDR4U },
4087 { "a5u", ADDR5U },
4088 { "a6u", ADDR6U },
4089 { "a7u", ADDR7U },
4090
4091 { 0, 0 }
4092 };
4093
4094 static void
4095 init_regtable (void)
4096 {
4097 int i;
4098 for (i = 0; init_table[i].name; i++)
4099 insert_reg (init_table[i].name, init_table[i].number);
4100 }
4101
4102 void
4103 md_assemble (char *str)
4104 {
4105 const char *er;
4106 short *fromP;
4107 char *toP = NULL;
4108 int m, n = 0;
4109 char *to_beg_P;
4110 int shorts_this_frag;
4111 fixS *fixP;
4112
4113 if (!selected_cpu && !selected_arch)
4114 {
4115 /* We've not selected an architecture yet. Set the default
4116 now. We do this lazily so that an initial .cpu or .arch directive
4117 can specify. */
4118 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4119 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4120 }
4121 if (!initialized)
4122 m68k_init_arch ();
4123
4124 /* In MRI mode, the instruction and operands are separated by a
4125 space. Anything following the operands is a comment. The label
4126 has already been removed. */
4127 if (flag_mri)
4128 {
4129 char *s;
4130 int fields = 0;
4131 int infield = 0;
4132 int inquote = 0;
4133
4134 for (s = str; *s != '\0'; s++)
4135 {
4136 if ((*s == ' ' || *s == '\t') && ! inquote)
4137 {
4138 if (infield)
4139 {
4140 ++fields;
4141 if (fields >= 2)
4142 {
4143 *s = '\0';
4144 break;
4145 }
4146 infield = 0;
4147 }
4148 }
4149 else
4150 {
4151 if (! infield)
4152 infield = 1;
4153 if (*s == '\'')
4154 inquote = ! inquote;
4155 }
4156 }
4157 }
4158
4159 memset (&the_ins, '\0', sizeof (the_ins));
4160 m68k_ip (str);
4161 er = the_ins.error;
4162 if (!er)
4163 {
4164 for (n = 0; n < the_ins.numargs; n++)
4165 if (the_ins.operands[n].error)
4166 {
4167 er = the_ins.operands[n].error;
4168 break;
4169 }
4170 }
4171 if (er)
4172 {
4173 as_bad (_("%s -- statement `%s' ignored"), er, str);
4174 return;
4175 }
4176
4177 /* If there is a current label, record that it marks an instruction. */
4178 if (current_label != NULL)
4179 {
4180 current_label->text = 1;
4181 current_label = NULL;
4182 }
4183
4184 #ifdef OBJ_ELF
4185 /* Tie dwarf2 debug info to the address at the start of the insn. */
4186 dwarf2_emit_insn (0);
4187 #endif
4188
4189 if (the_ins.nfrag == 0)
4190 {
4191 /* No frag hacking involved; just put it out. */
4192 toP = frag_more (2 * the_ins.numo);
4193 fromP = &the_ins.opcode[0];
4194 for (m = the_ins.numo; m; --m)
4195 {
4196 md_number_to_chars (toP, (long) (*fromP), 2);
4197 toP += 2;
4198 fromP++;
4199 }
4200 /* Put out symbol-dependent info. */
4201 for (m = 0; m < the_ins.nrel; m++)
4202 {
4203 switch (the_ins.reloc[m].wid)
4204 {
4205 case 'B':
4206 n = 1;
4207 break;
4208 case 'b':
4209 n = 1;
4210 break;
4211 case '3':
4212 n = 1;
4213 break;
4214 case 'w':
4215 case 'W':
4216 n = 2;
4217 break;
4218 case 'l':
4219 n = 4;
4220 break;
4221 default:
4222 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4223 the_ins.reloc[m].wid);
4224 }
4225
4226 fixP = fix_new_exp (frag_now,
4227 ((toP - frag_now->fr_literal)
4228 - the_ins.numo * 2 + the_ins.reloc[m].n),
4229 n,
4230 &the_ins.reloc[m].exp,
4231 the_ins.reloc[m].pcrel,
4232 get_reloc_code (n, the_ins.reloc[m].pcrel,
4233 the_ins.reloc[m].pic_reloc));
4234 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4235 if (the_ins.reloc[m].wid == 'B')
4236 fixP->fx_signed = 1;
4237 }
4238 return;
4239 }
4240
4241 /* There's some frag hacking. */
4242 {
4243 /* Calculate the max frag size. */
4244 int wid;
4245
4246 wid = 2 * the_ins.fragb[0].fragoff;
4247 for (n = 1; n < the_ins.nfrag; n++)
4248 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4249 /* frag_var part. */
4250 wid += 10;
4251 /* Make sure the whole insn fits in one chunk, in particular that
4252 the var part is attached, as we access one byte before the
4253 variable frag for byte branches. */
4254 frag_grow (wid);
4255 }
4256
4257 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4258 {
4259 int wid;
4260
4261 if (n == 0)
4262 wid = 2 * the_ins.fragb[n].fragoff;
4263 else
4264 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4265 toP = frag_more (wid);
4266 to_beg_P = toP;
4267 shorts_this_frag = 0;
4268 for (m = wid / 2; m; --m)
4269 {
4270 md_number_to_chars (toP, (long) (*fromP), 2);
4271 toP += 2;
4272 fromP++;
4273 shorts_this_frag++;
4274 }
4275 for (m = 0; m < the_ins.nrel; m++)
4276 {
4277 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4278 {
4279 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4280 break;
4281 }
4282 wid = the_ins.reloc[m].wid;
4283 if (wid == 0)
4284 continue;
4285 the_ins.reloc[m].wid = 0;
4286 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4287
4288 fixP = fix_new_exp (frag_now,
4289 ((toP - frag_now->fr_literal)
4290 - the_ins.numo * 2 + the_ins.reloc[m].n),
4291 wid,
4292 &the_ins.reloc[m].exp,
4293 the_ins.reloc[m].pcrel,
4294 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4295 the_ins.reloc[m].pic_reloc));
4296 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4297 }
4298 (void) frag_var (rs_machine_dependent, 10, 0,
4299 (relax_substateT) (the_ins.fragb[n].fragty),
4300 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4301 }
4302 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4303 shorts_this_frag = 0;
4304 if (n)
4305 {
4306 toP = frag_more (n * 2);
4307 while (n--)
4308 {
4309 md_number_to_chars (toP, (long) (*fromP), 2);
4310 toP += 2;
4311 fromP++;
4312 shorts_this_frag++;
4313 }
4314 }
4315 for (m = 0; m < the_ins.nrel; m++)
4316 {
4317 int wid;
4318
4319 wid = the_ins.reloc[m].wid;
4320 if (wid == 0)
4321 continue;
4322 the_ins.reloc[m].wid = 0;
4323 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4324
4325 fixP = fix_new_exp (frag_now,
4326 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4327 - shorts_this_frag * 2),
4328 wid,
4329 &the_ins.reloc[m].exp,
4330 the_ins.reloc[m].pcrel,
4331 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4332 the_ins.reloc[m].pic_reloc));
4333 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4334 }
4335 }
4336
4337 /* Comparison function used by qsort to rank the opcode entries by name. */
4338
4339 static int
4340 m68k_compare_opcode (const void * v1, const void * v2)
4341 {
4342 struct m68k_opcode * op1, * op2;
4343 int ret;
4344
4345 if (v1 == v2)
4346 return 0;
4347
4348 op1 = *(struct m68k_opcode **) v1;
4349 op2 = *(struct m68k_opcode **) v2;
4350
4351 /* Compare the two names. If different, return the comparison.
4352 If the same, return the order they are in the opcode table. */
4353 ret = strcmp (op1->name, op2->name);
4354 if (ret)
4355 return ret;
4356 if (op1 < op2)
4357 return -1;
4358 return 1;
4359 }
4360
4361 void
4362 md_begin (void)
4363 {
4364 const struct m68k_opcode *ins;
4365 struct m68k_incant *hack, *slak;
4366 const char *retval = 0; /* Empty string, or error msg text. */
4367 int i;
4368
4369 /* Set up hash tables with 68000 instructions.
4370 similar to what the vax assembler does. */
4371 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4372 a copy of it at runtime, adding in the information we want but isn't
4373 there. I think it'd be better to have an awk script hack the table
4374 at compile time. Or even just xstr the table and use it as-is. But
4375 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4376 names. */
4377
4378 if (flag_mri)
4379 {
4380 flag_reg_prefix_optional = 1;
4381 m68k_abspcadd = 1;
4382 if (! m68k_rel32_from_cmdline)
4383 m68k_rel32 = 0;
4384 }
4385
4386 /* First sort the opcode table into alphabetical order to seperate
4387 the order that the assembler wants to see the opcodes from the
4388 order that the disassembler wants to see them. */
4389 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4390 if (!m68k_sorted_opcodes)
4391 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4392 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4393
4394 for (i = m68k_numopcodes; i--;)
4395 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4396
4397 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4398 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4399
4400 op_hash = hash_new ();
4401
4402 obstack_begin (&robyn, 4000);
4403 for (i = 0; i < m68k_numopcodes; i++)
4404 {
4405 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4406 do
4407 {
4408 ins = m68k_sorted_opcodes[i];
4409
4410 /* We must enter all insns into the table, because .arch and
4411 .cpu directives can change things. */
4412 slak->m_operands = ins->args;
4413 slak->m_arch = ins->arch;
4414 slak->m_opcode = ins->opcode;
4415
4416 /* In most cases we can determine the number of opcode words
4417 by checking the second word of the mask. Unfortunately
4418 some instructions have 2 opcode words, but no fixed bits
4419 in the second word. A leading dot in the operands
4420 string also indicates 2 opcodes. */
4421 if (*slak->m_operands == '.')
4422 {
4423 slak->m_operands++;
4424 slak->m_codenum = 2;
4425 }
4426 else if (ins->match & 0xffffL)
4427 slak->m_codenum = 2;
4428 else
4429 slak->m_codenum = 1;
4430 slak->m_opnum = strlen (slak->m_operands) / 2;
4431
4432 if (i + 1 != m68k_numopcodes
4433 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4434 {
4435 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4436 i++;
4437 }
4438 else
4439 slak->m_next = 0;
4440 slak = slak->m_next;
4441 }
4442 while (slak);
4443
4444 retval = hash_insert (op_hash, ins->name, (char *) hack);
4445 if (retval)
4446 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4447 }
4448
4449 for (i = 0; i < m68k_numaliases; i++)
4450 {
4451 const char *name = m68k_opcode_aliases[i].primary;
4452 const char *alias = m68k_opcode_aliases[i].alias;
4453 PTR val = hash_find (op_hash, name);
4454
4455 if (!val)
4456 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4457 retval = hash_insert (op_hash, alias, val);
4458 if (retval)
4459 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4460 }
4461
4462 /* In MRI mode, all unsized branches are variable sized. Normally,
4463 they are word sized. */
4464 if (flag_mri)
4465 {
4466 static struct m68k_opcode_alias mri_aliases[] =
4467 {
4468 { "bhi", "jhi", },
4469 { "bls", "jls", },
4470 { "bcc", "jcc", },
4471 { "bcs", "jcs", },
4472 { "bne", "jne", },
4473 { "beq", "jeq", },
4474 { "bvc", "jvc", },
4475 { "bvs", "jvs", },
4476 { "bpl", "jpl", },
4477 { "bmi", "jmi", },
4478 { "bge", "jge", },
4479 { "blt", "jlt", },
4480 { "bgt", "jgt", },
4481 { "ble", "jle", },
4482 { "bra", "jra", },
4483 { "bsr", "jbsr", },
4484 };
4485
4486 for (i = 0;
4487 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4488 i++)
4489 {
4490 const char *name = mri_aliases[i].primary;
4491 const char *alias = mri_aliases[i].alias;
4492 PTR val = hash_find (op_hash, name);
4493
4494 if (!val)
4495 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4496 retval = hash_jam (op_hash, alias, val);
4497 if (retval)
4498 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4499 }
4500 }
4501
4502 for (i = 0; i < (int) sizeof (notend_table); i++)
4503 {
4504 notend_table[i] = 0;
4505 alt_notend_table[i] = 0;
4506 }
4507
4508 notend_table[','] = 1;
4509 notend_table['{'] = 1;
4510 notend_table['}'] = 1;
4511 alt_notend_table['a'] = 1;
4512 alt_notend_table['A'] = 1;
4513 alt_notend_table['d'] = 1;
4514 alt_notend_table['D'] = 1;
4515 alt_notend_table['#'] = 1;
4516 alt_notend_table['&'] = 1;
4517 alt_notend_table['f'] = 1;
4518 alt_notend_table['F'] = 1;
4519 #ifdef REGISTER_PREFIX
4520 alt_notend_table[REGISTER_PREFIX] = 1;
4521 #endif
4522
4523 /* We need to put '(' in alt_notend_table to handle
4524 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4525 alt_notend_table['('] = 1;
4526
4527 /* We need to put '@' in alt_notend_table to handle
4528 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4529 alt_notend_table['@'] = 1;
4530
4531 /* We need to put digits in alt_notend_table to handle
4532 bfextu %d0{24:1},%d0 */
4533 alt_notend_table['0'] = 1;
4534 alt_notend_table['1'] = 1;
4535 alt_notend_table['2'] = 1;
4536 alt_notend_table['3'] = 1;
4537 alt_notend_table['4'] = 1;
4538 alt_notend_table['5'] = 1;
4539 alt_notend_table['6'] = 1;
4540 alt_notend_table['7'] = 1;
4541 alt_notend_table['8'] = 1;
4542 alt_notend_table['9'] = 1;
4543
4544 #ifndef MIT_SYNTAX_ONLY
4545 /* Insert pseudo ops, these have to go into the opcode table since
4546 gas expects pseudo ops to start with a dot. */
4547 {
4548 int n = 0;
4549
4550 while (mote_pseudo_table[n].poc_name)
4551 {
4552 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4553 hash_insert (op_hash,
4554 mote_pseudo_table[n].poc_name, (char *) hack);
4555 hack->m_operands = 0;
4556 hack->m_opnum = n;
4557 n++;
4558 }
4559 }
4560 #endif
4561
4562 init_regtable ();
4563
4564 #ifdef OBJ_ELF
4565 record_alignment (text_section, 2);
4566 record_alignment (data_section, 2);
4567 record_alignment (bss_section, 2);
4568 #endif
4569 }
4570
4571 \f
4572 /* This is called when a label is defined. */
4573
4574 void
4575 m68k_frob_label (symbolS *sym)
4576 {
4577 struct label_line *n;
4578
4579 n = (struct label_line *) xmalloc (sizeof *n);
4580 n->next = labels;
4581 n->label = sym;
4582 as_where (&n->file, &n->line);
4583 n->text = 0;
4584 labels = n;
4585 current_label = n;
4586
4587 #ifdef OBJ_ELF
4588 dwarf2_emit_label (sym);
4589 #endif
4590 }
4591
4592 /* This is called when a value that is not an instruction is emitted. */
4593
4594 void
4595 m68k_flush_pending_output (void)
4596 {
4597 current_label = NULL;
4598 }
4599
4600 /* This is called at the end of the assembly, when the final value of
4601 the label is known. We warn if this is a text symbol aligned at an
4602 odd location. */
4603
4604 void
4605 m68k_frob_symbol (symbolS *sym)
4606 {
4607 if (S_GET_SEGMENT (sym) == reg_section
4608 && (int) S_GET_VALUE (sym) < 0)
4609 {
4610 S_SET_SEGMENT (sym, absolute_section);
4611 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4612 }
4613 else if ((S_GET_VALUE (sym) & 1) != 0)
4614 {
4615 struct label_line *l;
4616
4617 for (l = labels; l != NULL; l = l->next)
4618 {
4619 if (l->label == sym)
4620 {
4621 if (l->text)
4622 as_warn_where (l->file, l->line,
4623 _("text label `%s' aligned to odd boundary"),
4624 S_GET_NAME (sym));
4625 break;
4626 }
4627 }
4628 }
4629 }
4630 \f
4631 /* This is called if we go in or out of MRI mode because of the .mri
4632 pseudo-op. */
4633
4634 void
4635 m68k_mri_mode_change (int on)
4636 {
4637 if (on)
4638 {
4639 if (! flag_reg_prefix_optional)
4640 {
4641 flag_reg_prefix_optional = 1;
4642 #ifdef REGISTER_PREFIX
4643 init_regtable ();
4644 #endif
4645 }
4646 m68k_abspcadd = 1;
4647 if (! m68k_rel32_from_cmdline)
4648 m68k_rel32 = 0;
4649 }
4650 else
4651 {
4652 if (! reg_prefix_optional_seen)
4653 {
4654 #ifdef REGISTER_PREFIX_OPTIONAL
4655 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4656 #else
4657 flag_reg_prefix_optional = 0;
4658 #endif
4659 #ifdef REGISTER_PREFIX
4660 init_regtable ();
4661 #endif
4662 }
4663 m68k_abspcadd = 0;
4664 if (! m68k_rel32_from_cmdline)
4665 m68k_rel32 = 1;
4666 }
4667 }
4668
4669 /* Equal to MAX_PRECISION in atof-ieee.c. */
4670 #define MAX_LITTLENUMS 6
4671
4672 /* Turn a string in input_line_pointer into a floating point constant
4673 of type TYPE, and store the appropriate bytes in *LITP. The number
4674 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4675 returned, or NULL on OK. */
4676
4677 char *
4678 md_atof (int type, char *litP, int *sizeP)
4679 {
4680 int prec;
4681 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4682 LITTLENUM_TYPE *wordP;
4683 char *t;
4684
4685 switch (type)
4686 {
4687 case 'f':
4688 case 'F':
4689 case 's':
4690 case 'S':
4691 prec = 2;
4692 break;
4693
4694 case 'd':
4695 case 'D':
4696 case 'r':
4697 case 'R':
4698 prec = 4;
4699 break;
4700
4701 case 'x':
4702 case 'X':
4703 prec = 6;
4704 break;
4705
4706 case 'p':
4707 case 'P':
4708 prec = 6;
4709 break;
4710
4711 default:
4712 *sizeP = 0;
4713 return _("Bad call to MD_ATOF()");
4714 }
4715 t = atof_ieee (input_line_pointer, type, words);
4716 if (t)
4717 input_line_pointer = t;
4718
4719 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4720 for (wordP = words; prec--;)
4721 {
4722 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4723 litP += sizeof (LITTLENUM_TYPE);
4724 }
4725 return 0;
4726 }
4727
4728 void
4729 md_number_to_chars (char *buf, valueT val, int n)
4730 {
4731 number_to_chars_bigendian (buf, val, n);
4732 }
4733
4734 void
4735 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4736 {
4737 offsetT val = *valP;
4738 addressT upper_limit;
4739 offsetT lower_limit;
4740
4741 /* This is unnecessary but it convinces the native rs6000 compiler
4742 to generate the code we want. */
4743 char *buf = fixP->fx_frag->fr_literal;
4744 buf += fixP->fx_where;
4745 /* End ibm compiler workaround. */
4746
4747 val = SEXT (val);
4748
4749 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4750 fixP->fx_done = 1;
4751
4752 #ifdef OBJ_ELF
4753 if (fixP->fx_addsy)
4754 {
4755 memset (buf, 0, fixP->fx_size);
4756 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4757
4758 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4759 && !S_IS_DEFINED (fixP->fx_addsy)
4760 && !S_IS_WEAK (fixP->fx_addsy))
4761 S_SET_WEAK (fixP->fx_addsy);
4762 return;
4763 }
4764 #elif defined(OBJ_AOUT)
4765 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4766 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4767 {
4768 memset (buf, 0, fixP->fx_size);
4769 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4770 return;
4771 }
4772 #endif
4773
4774 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4775 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4776 return;
4777
4778 switch (fixP->fx_size)
4779 {
4780 /* The cast to offsetT below are necessary to make code
4781 correct for machines where ints are smaller than offsetT. */
4782 case 1:
4783 *buf++ = val;
4784 upper_limit = 0x7f;
4785 lower_limit = - (offsetT) 0x80;
4786 break;
4787 case 2:
4788 *buf++ = (val >> 8);
4789 *buf++ = val;
4790 upper_limit = 0x7fff;
4791 lower_limit = - (offsetT) 0x8000;
4792 break;
4793 case 4:
4794 *buf++ = (val >> 24);
4795 *buf++ = (val >> 16);
4796 *buf++ = (val >> 8);
4797 *buf++ = val;
4798 upper_limit = 0x7fffffff;
4799 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4800 break;
4801 default:
4802 BAD_CASE (fixP->fx_size);
4803 }
4804
4805 /* Fix up a negative reloc. */
4806 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4807 {
4808 fixP->fx_addsy = fixP->fx_subsy;
4809 fixP->fx_subsy = NULL;
4810 fixP->fx_tcbit = 1;
4811 }
4812
4813 /* For non-pc-relative values, it's conceivable we might get something
4814 like "0xff" for a byte field. So extend the upper part of the range
4815 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4816 so that we can do any range checking at all. */
4817 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4818 upper_limit = upper_limit * 2 + 1;
4819
4820 if ((addressT) val > upper_limit
4821 && (val > 0 || val < lower_limit))
4822 as_bad_where (fixP->fx_file, fixP->fx_line,
4823 _("value %ld out of range"), (long)val);
4824
4825 /* A one byte PC-relative reloc means a short branch. We can't use
4826 a short branch with a value of 0 or -1, because those indicate
4827 different opcodes (branches with longer offsets). fixup_segment
4828 in write.c may have clobbered fx_pcrel, so we need to examine the
4829 reloc type. */
4830 if ((fixP->fx_pcrel
4831 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4832 && fixP->fx_size == 1
4833 && (fixP->fx_addsy == NULL
4834 || S_IS_DEFINED (fixP->fx_addsy))
4835 && (val == 0 || val == -1))
4836 as_bad_where (fixP->fx_file, fixP->fx_line,
4837 _("invalid byte branch offset"));
4838 }
4839
4840 /* *fragP has been relaxed to its final size, and now needs to have
4841 the bytes inside it modified to conform to the new size There is UGLY
4842 MAGIC here. ..
4843 */
4844 static void
4845 md_convert_frag_1 (fragS *fragP)
4846 {
4847 long disp;
4848 fixS *fixP = NULL;
4849
4850 /* Address in object code of the displacement. */
4851 register int object_address = fragP->fr_fix + fragP->fr_address;
4852
4853 /* Address in gas core of the place to store the displacement. */
4854 /* This convinces the native rs6000 compiler to generate the code we
4855 want. */
4856 register char *buffer_address = fragP->fr_literal;
4857 buffer_address += fragP->fr_fix;
4858 /* End ibm compiler workaround. */
4859
4860 /* The displacement of the address, from current location. */
4861 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4862 disp = (disp + fragP->fr_offset) - object_address;
4863
4864 switch (fragP->fr_subtype)
4865 {
4866 case TAB (BRANCHBWL, BYTE):
4867 case TAB (BRABSJUNC, BYTE):
4868 case TAB (BRABSJCOND, BYTE):
4869 case TAB (BRANCHBW, BYTE):
4870 know (issbyte (disp));
4871 if (disp == 0)
4872 as_bad_where (fragP->fr_file, fragP->fr_line,
4873 _("short branch with zero offset: use :w"));
4874 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4875 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4876 fixP->fx_pcrel_adjust = -1;
4877 break;
4878 case TAB (BRANCHBWL, SHORT):
4879 case TAB (BRABSJUNC, SHORT):
4880 case TAB (BRABSJCOND, SHORT):
4881 case TAB (BRANCHBW, SHORT):
4882 fragP->fr_opcode[1] = 0x00;
4883 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4884 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4885 fragP->fr_fix += 2;
4886 break;
4887 case TAB (BRANCHBWL, LONG):
4888 fragP->fr_opcode[1] = (char) 0xFF;
4889 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4890 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4891 fragP->fr_fix += 4;
4892 break;
4893 case TAB (BRABSJUNC, LONG):
4894 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4895 {
4896 if (flag_keep_pcrel)
4897 as_bad_where (fragP->fr_file, fragP->fr_line,
4898 _("Conversion of PC relative BSR to absolute JSR"));
4899 fragP->fr_opcode[0] = 0x4E;
4900 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4901 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4902 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4903 fragP->fr_fix += 4;
4904 }
4905 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4906 {
4907 if (flag_keep_pcrel)
4908 as_bad_where (fragP->fr_file, fragP->fr_line,
4909 _("Conversion of PC relative branch to absolute jump"));
4910 fragP->fr_opcode[0] = 0x4E;
4911 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4912 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4913 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4914 fragP->fr_fix += 4;
4915 }
4916 else
4917 {
4918 /* This cannot happen, because jbsr and jbra are the only two
4919 unconditional branches. */
4920 abort ();
4921 }
4922 break;
4923 case TAB (BRABSJCOND, LONG):
4924 if (flag_keep_pcrel)
4925 as_bad_where (fragP->fr_file, fragP->fr_line,
4926 _("Conversion of PC relative conditional branch to absolute jump"));
4927
4928 /* Only Bcc 68000 instructions can come here
4929 Change bcc into b!cc/jmp absl long. */
4930 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4931 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4932
4933 /* JF: these used to be fr_opcode[2,3], but they may be in a
4934 different frag, in which case referring to them is a no-no.
4935 Only fr_opcode[0,1] are guaranteed to work. */
4936 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4937 *buffer_address++ = (char) 0xf9;
4938 fragP->fr_fix += 2; /* Account for jmp instruction. */
4939 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4940 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4941 fragP->fr_fix += 4;
4942 break;
4943 case TAB (FBRANCH, SHORT):
4944 know ((fragP->fr_opcode[1] & 0x40) == 0);
4945 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4946 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4947 fragP->fr_fix += 2;
4948 break;
4949 case TAB (FBRANCH, LONG):
4950 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4951 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4952 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4953 fragP->fr_fix += 4;
4954 break;
4955 case TAB (DBCCLBR, SHORT):
4956 case TAB (DBCCABSJ, SHORT):
4957 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4958 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4959 fragP->fr_fix += 2;
4960 break;
4961 case TAB (DBCCLBR, LONG):
4962 /* Only DBcc instructions can come here.
4963 Change dbcc into dbcc/bral.
4964 JF: these used to be fr_opcode[2-7], but that's wrong. */
4965 if (flag_keep_pcrel)
4966 as_bad_where (fragP->fr_file, fragP->fr_line,
4967 _("Conversion of DBcc to absolute jump"));
4968
4969 *buffer_address++ = 0x00; /* Branch offset = 4. */
4970 *buffer_address++ = 0x04;
4971 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4972 *buffer_address++ = 0x06;
4973 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4974 *buffer_address++ = (char) 0xff;
4975
4976 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4977 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4978 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4979 fragP->fr_fix += 4;
4980 break;
4981 case TAB (DBCCABSJ, LONG):
4982 /* Only DBcc instructions can come here.
4983 Change dbcc into dbcc/jmp.
4984 JF: these used to be fr_opcode[2-7], but that's wrong. */
4985 if (flag_keep_pcrel)
4986 as_bad_where (fragP->fr_file, fragP->fr_line,
4987 _("Conversion of PC relative conditional branch to absolute jump"));
4988
4989 *buffer_address++ = 0x00; /* Branch offset = 4. */
4990 *buffer_address++ = 0x04;
4991 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4992 *buffer_address++ = 0x06;
4993 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4994 *buffer_address++ = (char) 0xf9;
4995
4996 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4997 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4998 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4999 fragP->fr_fix += 4;
5000 break;
5001 case TAB (PCREL1632, SHORT):
5002 fragP->fr_opcode[1] &= ~0x3F;
5003 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5004 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5005 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5006 fragP->fr_fix += 2;
5007 break;
5008 case TAB (PCREL1632, LONG):
5009 /* Already set to mode 7.3; this indicates: PC indirect with
5010 suppressed index, 32-bit displacement. */
5011 *buffer_address++ = 0x01;
5012 *buffer_address++ = 0x70;
5013 fragP->fr_fix += 2;
5014 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5015 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5016 fixP->fx_pcrel_adjust = 2;
5017 fragP->fr_fix += 4;
5018 break;
5019 case TAB (PCINDEX, BYTE):
5020 assert (fragP->fr_fix >= 2);
5021 buffer_address[-2] &= ~1;
5022 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5023 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5024 fixP->fx_pcrel_adjust = 1;
5025 break;
5026 case TAB (PCINDEX, SHORT):
5027 assert (fragP->fr_fix >= 2);
5028 buffer_address[-2] |= 0x1;
5029 buffer_address[-1] = 0x20;
5030 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5031 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5032 fixP->fx_pcrel_adjust = 2;
5033 fragP->fr_fix += 2;
5034 break;
5035 case TAB (PCINDEX, LONG):
5036 assert (fragP->fr_fix >= 2);
5037 buffer_address[-2] |= 0x1;
5038 buffer_address[-1] = 0x30;
5039 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5040 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5041 fixP->fx_pcrel_adjust = 2;
5042 fragP->fr_fix += 4;
5043 break;
5044 case TAB (ABSTOPCREL, SHORT):
5045 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5046 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5047 fragP->fr_fix += 2;
5048 break;
5049 case TAB (ABSTOPCREL, LONG):
5050 if (flag_keep_pcrel)
5051 as_fatal (_("Conversion of PC relative displacement to absolute"));
5052 /* The thing to do here is force it to ABSOLUTE LONG, since
5053 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5054 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5055 abort ();
5056 fragP->fr_opcode[1] &= ~0x3F;
5057 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5058 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5059 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5060 fragP->fr_fix += 4;
5061 break;
5062 }
5063 if (fixP)
5064 {
5065 fixP->fx_file = fragP->fr_file;
5066 fixP->fx_line = fragP->fr_line;
5067 }
5068 }
5069
5070 void
5071 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5072 segT sec ATTRIBUTE_UNUSED,
5073 fragS *fragP)
5074 {
5075 md_convert_frag_1 (fragP);
5076 }
5077
5078 /* Force truly undefined symbols to their maximum size, and generally set up
5079 the frag list to be relaxed
5080 */
5081 int
5082 md_estimate_size_before_relax (fragS *fragP, segT segment)
5083 {
5084 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5085 switch (fragP->fr_subtype)
5086 {
5087 case TAB (BRANCHBWL, SZ_UNDEF):
5088 case TAB (BRABSJUNC, SZ_UNDEF):
5089 case TAB (BRABSJCOND, SZ_UNDEF):
5090 {
5091 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5092 && relaxable_symbol (fragP->fr_symbol))
5093 {
5094 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5095 }
5096 else if (flag_short_refs)
5097 {
5098 /* Symbol is undefined and we want short ref. */
5099 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5100 }
5101 else
5102 {
5103 /* Symbol is still undefined. Make it LONG. */
5104 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5105 }
5106 break;
5107 }
5108
5109 case TAB (BRANCHBW, SZ_UNDEF):
5110 {
5111 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5112 && relaxable_symbol (fragP->fr_symbol))
5113 {
5114 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5115 }
5116 else
5117 {
5118 /* Symbol is undefined and we don't have long branches. */
5119 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5120 }
5121 break;
5122 }
5123
5124 case TAB (FBRANCH, SZ_UNDEF):
5125 case TAB (DBCCLBR, SZ_UNDEF):
5126 case TAB (DBCCABSJ, SZ_UNDEF):
5127 case TAB (PCREL1632, SZ_UNDEF):
5128 {
5129 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5130 && relaxable_symbol (fragP->fr_symbol))
5131 || flag_short_refs)
5132 {
5133 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5134 }
5135 else
5136 {
5137 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5138 }
5139 break;
5140 }
5141
5142 case TAB (PCINDEX, SZ_UNDEF):
5143 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5144 && relaxable_symbol (fragP->fr_symbol)))
5145 {
5146 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5147 }
5148 else
5149 {
5150 fragP->fr_subtype = TAB (PCINDEX, LONG);
5151 }
5152 break;
5153
5154 case TAB (ABSTOPCREL, SZ_UNDEF):
5155 {
5156 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5157 && relaxable_symbol (fragP->fr_symbol)))
5158 {
5159 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5160 }
5161 else
5162 {
5163 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5164 }
5165 break;
5166 }
5167
5168 default:
5169 break;
5170 }
5171
5172 /* Now that SZ_UNDEF are taken care of, check others. */
5173 switch (fragP->fr_subtype)
5174 {
5175 case TAB (BRANCHBWL, BYTE):
5176 case TAB (BRABSJUNC, BYTE):
5177 case TAB (BRABSJCOND, BYTE):
5178 case TAB (BRANCHBW, BYTE):
5179 /* We can't do a short jump to the next instruction, so in that
5180 case we force word mode. If the symbol is at the start of a
5181 frag, and it is the next frag with any data in it (usually
5182 this is just the next frag, but assembler listings may
5183 introduce empty frags), we must use word mode. */
5184 if (fragP->fr_symbol)
5185 {
5186 fragS *sym_frag;
5187
5188 sym_frag = symbol_get_frag (fragP->fr_symbol);
5189 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5190 {
5191 fragS *l;
5192
5193 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5194 if (l->fr_fix != 0)
5195 break;
5196 if (l == sym_frag)
5197 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5198 }
5199 }
5200 break;
5201 default:
5202 break;
5203 }
5204 return md_relax_table[fragP->fr_subtype].rlx_length;
5205 }
5206
5207 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5208 /* the bit-field entries in the relocation_info struct plays hell
5209 with the byte-order problems of cross-assembly. So as a hack,
5210 I added this mach. dependent ri twiddler. Ugly, but it gets
5211 you there. -KWK */
5212 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5213 are symbolnum, most sig. byte first. Last byte is broken up with
5214 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5215 nibble as nuthin. (on Sun 3 at least) */
5216 /* Translate the internal relocation information into target-specific
5217 format. */
5218 #ifdef comment
5219 void
5220 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5221 {
5222 /* This is easy. */
5223 md_number_to_chars (the_bytes, ri->r_address, 4);
5224 /* Now the fun stuff. */
5225 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5226 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5227 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5228 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5229 | ((ri->r_length << 5) & 0x60)
5230 | ((ri->r_extern << 4) & 0x10));
5231 }
5232
5233 #endif
5234
5235 #endif /* OBJ_AOUT or OBJ_BOUT */
5236
5237 #ifndef WORKING_DOT_WORD
5238 int md_short_jump_size = 4;
5239 int md_long_jump_size = 6;
5240
5241 void
5242 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5243 fragS *frag ATTRIBUTE_UNUSED,
5244 symbolS *to_symbol ATTRIBUTE_UNUSED)
5245 {
5246 valueT offset;
5247
5248 offset = to_addr - (from_addr + 2);
5249
5250 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5251 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5252 }
5253
5254 void
5255 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5256 fragS *frag, symbolS *to_symbol)
5257 {
5258 valueT offset;
5259
5260 if (!HAVE_LONG_BRANCH (current_architecture))
5261 {
5262 if (flag_keep_pcrel)
5263 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5264 offset = to_addr - S_GET_VALUE (to_symbol);
5265 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5266 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5267 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5268 0, NO_RELOC);
5269 }
5270 else
5271 {
5272 offset = to_addr - (from_addr + 2);
5273 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5274 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5275 }
5276 }
5277
5278 #endif
5279
5280 /* Different values of OK tell what its OK to return. Things that
5281 aren't OK are an error (what a shock, no?)
5282
5283 0: Everything is OK
5284 10: Absolute 1:8 only
5285 20: Absolute 0:7 only
5286 30: absolute 0:15 only
5287 40: Absolute 0:31 only
5288 50: absolute 0:127 only
5289 55: absolute -64:63 only
5290 60: absolute -128:127 only
5291 65: absolute 0:511 only
5292 70: absolute 0:4095 only
5293 80: absolute -1, 1:7 only
5294 90: No bignums. */
5295
5296 static int
5297 get_num (struct m68k_exp *exp, int ok)
5298 {
5299 if (exp->exp.X_op == O_absent)
5300 {
5301 /* Do the same thing the VAX asm does. */
5302 op (exp) = O_constant;
5303 adds (exp) = 0;
5304 subs (exp) = 0;
5305 offs (exp) = 0;
5306 if (ok == 10)
5307 {
5308 as_warn (_("expression out of range: defaulting to 1"));
5309 offs (exp) = 1;
5310 }
5311 }
5312 else if (exp->exp.X_op == O_constant)
5313 {
5314 switch (ok)
5315 {
5316 case 10:
5317 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5318 {
5319 as_warn (_("expression out of range: defaulting to 1"));
5320 offs (exp) = 1;
5321 }
5322 break;
5323 case 20:
5324 if ((valueT) TRUNC (offs (exp)) > 7)
5325 goto outrange;
5326 break;
5327 case 30:
5328 if ((valueT) TRUNC (offs (exp)) > 15)
5329 goto outrange;
5330 break;
5331 case 40:
5332 if ((valueT) TRUNC (offs (exp)) > 32)
5333 goto outrange;
5334 break;
5335 case 50:
5336 if ((valueT) TRUNC (offs (exp)) > 127)
5337 goto outrange;
5338 break;
5339 case 55:
5340 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5341 goto outrange;
5342 break;
5343 case 60:
5344 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5345 goto outrange;
5346 break;
5347 case 65:
5348 if ((valueT) TRUNC (offs (exp)) > 511)
5349 goto outrange;
5350 break;
5351 case 70:
5352 if ((valueT) TRUNC (offs (exp)) > 4095)
5353 {
5354 outrange:
5355 as_warn (_("expression out of range: defaulting to 0"));
5356 offs (exp) = 0;
5357 }
5358 break;
5359 case 80:
5360 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5361 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5362 {
5363 as_warn (_("expression out of range: defaulting to 1"));
5364 offs (exp) = 1;
5365 }
5366 break;
5367 default:
5368 break;
5369 }
5370 }
5371 else if (exp->exp.X_op == O_big)
5372 {
5373 if (offs (exp) <= 0 /* flonum. */
5374 && (ok == 90 /* no bignums */
5375 || (ok > 10 /* Small-int ranges including 0 ok. */
5376 /* If we have a flonum zero, a zero integer should
5377 do as well (e.g., in moveq). */
5378 && generic_floating_point_number.exponent == 0
5379 && generic_floating_point_number.low[0] == 0)))
5380 {
5381 /* HACK! Turn it into a long. */
5382 LITTLENUM_TYPE words[6];
5383
5384 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5385 op (exp) = O_constant;
5386 adds (exp) = 0;
5387 subs (exp) = 0;
5388 offs (exp) = words[1] | (words[0] << 16);
5389 }
5390 else if (ok != 0)
5391 {
5392 op (exp) = O_constant;
5393 adds (exp) = 0;
5394 subs (exp) = 0;
5395 offs (exp) = (ok == 10) ? 1 : 0;
5396 as_warn (_("Can't deal with expression; defaulting to %ld"),
5397 (long) offs (exp));
5398 }
5399 }
5400 else
5401 {
5402 if (ok >= 10 && ok <= 80)
5403 {
5404 op (exp) = O_constant;
5405 adds (exp) = 0;
5406 subs (exp) = 0;
5407 offs (exp) = (ok == 10) ? 1 : 0;
5408 as_warn (_("Can't deal with expression; defaulting to %ld"),
5409 (long) offs (exp));
5410 }
5411 }
5412
5413 if (exp->size != SIZE_UNSPEC)
5414 {
5415 switch (exp->size)
5416 {
5417 case SIZE_UNSPEC:
5418 case SIZE_LONG:
5419 break;
5420 case SIZE_BYTE:
5421 if (!isbyte (offs (exp)))
5422 as_warn (_("expression doesn't fit in BYTE"));
5423 break;
5424 case SIZE_WORD:
5425 if (!isword (offs (exp)))
5426 as_warn (_("expression doesn't fit in WORD"));
5427 break;
5428 }
5429 }
5430
5431 return offs (exp);
5432 }
5433
5434 /* These are the back-ends for the various machine dependent pseudo-ops. */
5435
5436 static void
5437 s_data1 (int ignore ATTRIBUTE_UNUSED)
5438 {
5439 subseg_set (data_section, 1);
5440 demand_empty_rest_of_line ();
5441 }
5442
5443 static void
5444 s_data2 (int ignore ATTRIBUTE_UNUSED)
5445 {
5446 subseg_set (data_section, 2);
5447 demand_empty_rest_of_line ();
5448 }
5449
5450 static void
5451 s_bss (int ignore ATTRIBUTE_UNUSED)
5452 {
5453 /* We don't support putting frags in the BSS segment, we fake it
5454 by marking in_bss, then looking at s_skip for clues. */
5455
5456 subseg_set (bss_section, 0);
5457 demand_empty_rest_of_line ();
5458 }
5459
5460 static void
5461 s_even (int ignore ATTRIBUTE_UNUSED)
5462 {
5463 register int temp;
5464 register long temp_fill;
5465
5466 temp = 1; /* JF should be 2? */
5467 temp_fill = get_absolute_expression ();
5468 if (!need_pass_2) /* Never make frag if expect extra pass. */
5469 frag_align (temp, (int) temp_fill, 0);
5470 demand_empty_rest_of_line ();
5471 record_alignment (now_seg, temp);
5472 }
5473
5474 static void
5475 s_proc (int ignore ATTRIBUTE_UNUSED)
5476 {
5477 demand_empty_rest_of_line ();
5478 }
5479 \f
5480 /* Pseudo-ops handled for MRI compatibility. */
5481
5482 /* This function returns non-zero if the argument is a conditional
5483 pseudo-op. This is called when checking whether a pending
5484 alignment is needed. */
5485
5486 int
5487 m68k_conditional_pseudoop (pseudo_typeS *pop)
5488 {
5489 return (pop->poc_handler == s_mri_if
5490 || pop->poc_handler == s_mri_else);
5491 }
5492
5493 /* Handle an MRI style chip specification. */
5494
5495 static void
5496 mri_chip (void)
5497 {
5498 char *s;
5499 char c;
5500 int i;
5501
5502 s = input_line_pointer;
5503 /* We can't use get_symbol_end since the processor names are not proper
5504 symbols. */
5505 while (is_part_of_name (c = *input_line_pointer++))
5506 ;
5507 *--input_line_pointer = 0;
5508 for (i = 0; m68k_cpus[i].name; i++)
5509 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5510 break;
5511 if (!m68k_cpus[i].name)
5512 {
5513 as_bad (_("%s: unrecognized processor name"), s);
5514 *input_line_pointer = c;
5515 ignore_rest_of_line ();
5516 return;
5517 }
5518 *input_line_pointer = c;
5519
5520 if (*input_line_pointer == '/')
5521 current_architecture = 0;
5522 else
5523 current_architecture &= m68881 | m68851;
5524 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5525 control_regs = m68k_cpus[i].control_regs;
5526
5527 while (*input_line_pointer == '/')
5528 {
5529 ++input_line_pointer;
5530 s = input_line_pointer;
5531 /* We can't use get_symbol_end since the processor names are not
5532 proper symbols. */
5533 while (is_part_of_name (c = *input_line_pointer++))
5534 ;
5535 *--input_line_pointer = 0;
5536 if (strcmp (s, "68881") == 0)
5537 current_architecture |= m68881;
5538 else if (strcmp (s, "68851") == 0)
5539 current_architecture |= m68851;
5540 *input_line_pointer = c;
5541 }
5542 }
5543
5544 /* The MRI CHIP pseudo-op. */
5545
5546 static void
5547 s_chip (int ignore ATTRIBUTE_UNUSED)
5548 {
5549 char *stop = NULL;
5550 char stopc;
5551
5552 if (flag_mri)
5553 stop = mri_comment_field (&stopc);
5554 mri_chip ();
5555 if (flag_mri)
5556 mri_comment_end (stop, stopc);
5557 demand_empty_rest_of_line ();
5558 }
5559
5560 /* The MRI FOPT pseudo-op. */
5561
5562 static void
5563 s_fopt (int ignore ATTRIBUTE_UNUSED)
5564 {
5565 SKIP_WHITESPACE ();
5566
5567 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5568 {
5569 int temp;
5570
5571 input_line_pointer += 3;
5572 temp = get_absolute_expression ();
5573 if (temp < 0 || temp > 7)
5574 as_bad (_("bad coprocessor id"));
5575 else
5576 m68k_float_copnum = COP0 + temp;
5577 }
5578 else
5579 {
5580 as_bad (_("unrecognized fopt option"));
5581 ignore_rest_of_line ();
5582 return;
5583 }
5584
5585 demand_empty_rest_of_line ();
5586 }
5587
5588 /* The structure used to handle the MRI OPT pseudo-op. */
5589
5590 struct opt_action
5591 {
5592 /* The name of the option. */
5593 const char *name;
5594
5595 /* If this is not NULL, just call this function. The first argument
5596 is the ARG field of this structure, the second argument is
5597 whether the option was negated. */
5598 void (*pfn) (int arg, int on);
5599
5600 /* If this is not NULL, and the PFN field is NULL, set the variable
5601 this points to. Set it to the ARG field if the option was not
5602 negated, and the NOTARG field otherwise. */
5603 int *pvar;
5604
5605 /* The value to pass to PFN or to assign to *PVAR. */
5606 int arg;
5607
5608 /* The value to assign to *PVAR if the option is negated. If PFN is
5609 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5610 the option may not be negated. */
5611 int notarg;
5612 };
5613
5614 /* The table used to handle the MRI OPT pseudo-op. */
5615
5616 static void skip_to_comma (int, int);
5617 static void opt_nest (int, int);
5618 static void opt_chip (int, int);
5619 static void opt_list (int, int);
5620 static void opt_list_symbols (int, int);
5621
5622 static const struct opt_action opt_table[] =
5623 {
5624 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5625
5626 /* We do relaxing, so there is little use for these options. */
5627 { "b", 0, 0, 0, 0 },
5628 { "brs", 0, 0, 0, 0 },
5629 { "brb", 0, 0, 0, 0 },
5630 { "brl", 0, 0, 0, 0 },
5631 { "brw", 0, 0, 0, 0 },
5632
5633 { "c", 0, 0, 0, 0 },
5634 { "cex", 0, 0, 0, 0 },
5635 { "case", 0, &symbols_case_sensitive, 1, 0 },
5636 { "cl", 0, 0, 0, 0 },
5637 { "cre", 0, 0, 0, 0 },
5638 { "d", 0, &flag_keep_locals, 1, 0 },
5639 { "e", 0, 0, 0, 0 },
5640 { "f", 0, &flag_short_refs, 1, 0 },
5641 { "frs", 0, &flag_short_refs, 1, 0 },
5642 { "frl", 0, &flag_short_refs, 0, 1 },
5643 { "g", 0, 0, 0, 0 },
5644 { "i", 0, 0, 0, 0 },
5645 { "m", 0, 0, 0, 0 },
5646 { "mex", 0, 0, 0, 0 },
5647 { "mc", 0, 0, 0, 0 },
5648 { "md", 0, 0, 0, 0 },
5649 { "nest", opt_nest, 0, 0, 0 },
5650 { "next", skip_to_comma, 0, 0, 0 },
5651 { "o", 0, 0, 0, 0 },
5652 { "old", 0, 0, 0, 0 },
5653 { "op", skip_to_comma, 0, 0, 0 },
5654 { "pco", 0, 0, 0, 0 },
5655 { "p", opt_chip, 0, 0, 0 },
5656 { "pcr", 0, 0, 0, 0 },
5657 { "pcs", 0, 0, 0, 0 },
5658 { "r", 0, 0, 0, 0 },
5659 { "quick", 0, &m68k_quick, 1, 0 },
5660 { "rel32", 0, &m68k_rel32, 1, 0 },
5661 { "s", opt_list, 0, 0, 0 },
5662 { "t", opt_list_symbols, 0, 0, 0 },
5663 { "w", 0, &flag_no_warnings, 0, 1 },
5664 { "x", 0, 0, 0, 0 }
5665 };
5666
5667 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5668
5669 /* The MRI OPT pseudo-op. */
5670
5671 static void
5672 s_opt (int ignore ATTRIBUTE_UNUSED)
5673 {
5674 do
5675 {
5676 int t;
5677 char *s;
5678 char c;
5679 int i;
5680 const struct opt_action *o;
5681
5682 SKIP_WHITESPACE ();
5683
5684 t = 1;
5685 if (*input_line_pointer == '-')
5686 {
5687 ++input_line_pointer;
5688 t = 0;
5689 }
5690 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5691 {
5692 input_line_pointer += 2;
5693 t = 0;
5694 }
5695
5696 s = input_line_pointer;
5697 c = get_symbol_end ();
5698
5699 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5700 {
5701 if (strcasecmp (s, o->name) == 0)
5702 {
5703 if (o->pfn)
5704 {
5705 /* Restore input_line_pointer now in case the option
5706 takes arguments. */
5707 *input_line_pointer = c;
5708 (*o->pfn) (o->arg, t);
5709 }
5710 else if (o->pvar != NULL)
5711 {
5712 if (! t && o->arg == o->notarg)
5713 as_bad (_("option `%s' may not be negated"), s);
5714 *input_line_pointer = c;
5715 *o->pvar = t ? o->arg : o->notarg;
5716 }
5717 else
5718 *input_line_pointer = c;
5719 break;
5720 }
5721 }
5722 if (i >= OPTCOUNT)
5723 {
5724 as_bad (_("option `%s' not recognized"), s);
5725 *input_line_pointer = c;
5726 }
5727 }
5728 while (*input_line_pointer++ == ',');
5729
5730 /* Move back to terminating character. */
5731 --input_line_pointer;
5732 demand_empty_rest_of_line ();
5733 }
5734
5735 /* Skip ahead to a comma. This is used for OPT options which we do
5736 not support and which take arguments. */
5737
5738 static void
5739 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5740 {
5741 while (*input_line_pointer != ','
5742 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5743 ++input_line_pointer;
5744 }
5745
5746 /* Handle the OPT NEST=depth option. */
5747
5748 static void
5749 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5750 {
5751 if (*input_line_pointer != '=')
5752 {
5753 as_bad (_("bad format of OPT NEST=depth"));
5754 return;
5755 }
5756
5757 ++input_line_pointer;
5758 max_macro_nest = get_absolute_expression ();
5759 }
5760
5761 /* Handle the OPT P=chip option. */
5762
5763 static void
5764 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5765 {
5766 if (*input_line_pointer != '=')
5767 {
5768 /* This is just OPT P, which we do not support. */
5769 return;
5770 }
5771
5772 ++input_line_pointer;
5773 mri_chip ();
5774 }
5775
5776 /* Handle the OPT S option. */
5777
5778 static void
5779 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5780 {
5781 listing_list (on);
5782 }
5783
5784 /* Handle the OPT T option. */
5785
5786 static void
5787 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5788 {
5789 if (on)
5790 listing |= LISTING_SYMBOLS;
5791 else
5792 listing &= ~LISTING_SYMBOLS;
5793 }
5794
5795 /* Handle the MRI REG pseudo-op. */
5796
5797 static void
5798 s_reg (int ignore ATTRIBUTE_UNUSED)
5799 {
5800 char *s;
5801 int c;
5802 struct m68k_op rop;
5803 int mask;
5804 char *stop = NULL;
5805 char stopc;
5806
5807 if (line_label == NULL)
5808 {
5809 as_bad (_("missing label"));
5810 ignore_rest_of_line ();
5811 return;
5812 }
5813
5814 if (flag_mri)
5815 stop = mri_comment_field (&stopc);
5816
5817 SKIP_WHITESPACE ();
5818
5819 s = input_line_pointer;
5820 while (ISALNUM (*input_line_pointer)
5821 #ifdef REGISTER_PREFIX
5822 || *input_line_pointer == REGISTER_PREFIX
5823 #endif
5824 || *input_line_pointer == '/'
5825 || *input_line_pointer == '-')
5826 ++input_line_pointer;
5827 c = *input_line_pointer;
5828 *input_line_pointer = '\0';
5829
5830 if (m68k_ip_op (s, &rop) != 0)
5831 {
5832 if (rop.error == NULL)
5833 as_bad (_("bad register list"));
5834 else
5835 as_bad (_("bad register list: %s"), rop.error);
5836 *input_line_pointer = c;
5837 ignore_rest_of_line ();
5838 return;
5839 }
5840
5841 *input_line_pointer = c;
5842
5843 if (rop.mode == REGLST)
5844 mask = rop.mask;
5845 else if (rop.mode == DREG)
5846 mask = 1 << (rop.reg - DATA0);
5847 else if (rop.mode == AREG)
5848 mask = 1 << (rop.reg - ADDR0 + 8);
5849 else if (rop.mode == FPREG)
5850 mask = 1 << (rop.reg - FP0 + 16);
5851 else if (rop.mode == CONTROL
5852 && rop.reg == FPI)
5853 mask = 1 << 24;
5854 else if (rop.mode == CONTROL
5855 && rop.reg == FPS)
5856 mask = 1 << 25;
5857 else if (rop.mode == CONTROL
5858 && rop.reg == FPC)
5859 mask = 1 << 26;
5860 else
5861 {
5862 as_bad (_("bad register list"));
5863 ignore_rest_of_line ();
5864 return;
5865 }
5866
5867 S_SET_SEGMENT (line_label, reg_section);
5868 S_SET_VALUE (line_label, ~mask);
5869 symbol_set_frag (line_label, &zero_address_frag);
5870
5871 if (flag_mri)
5872 mri_comment_end (stop, stopc);
5873
5874 demand_empty_rest_of_line ();
5875 }
5876
5877 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5878
5879 struct save_opts
5880 {
5881 struct save_opts *next;
5882 int abspcadd;
5883 int symbols_case_sensitive;
5884 int keep_locals;
5885 int short_refs;
5886 int architecture;
5887 const enum m68k_register *control_regs;
5888 int quick;
5889 int rel32;
5890 int listing;
5891 int no_warnings;
5892 /* FIXME: We don't save OPT S. */
5893 };
5894
5895 /* This variable holds the stack of saved options. */
5896
5897 static struct save_opts *save_stack;
5898
5899 /* The MRI SAVE pseudo-op. */
5900
5901 static void
5902 s_save (int ignore ATTRIBUTE_UNUSED)
5903 {
5904 struct save_opts *s;
5905
5906 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5907 s->abspcadd = m68k_abspcadd;
5908 s->symbols_case_sensitive = symbols_case_sensitive;
5909 s->keep_locals = flag_keep_locals;
5910 s->short_refs = flag_short_refs;
5911 s->architecture = current_architecture;
5912 s->control_regs = control_regs;
5913 s->quick = m68k_quick;
5914 s->rel32 = m68k_rel32;
5915 s->listing = listing;
5916 s->no_warnings = flag_no_warnings;
5917
5918 s->next = save_stack;
5919 save_stack = s;
5920
5921 demand_empty_rest_of_line ();
5922 }
5923
5924 /* The MRI RESTORE pseudo-op. */
5925
5926 static void
5927 s_restore (int ignore ATTRIBUTE_UNUSED)
5928 {
5929 struct save_opts *s;
5930
5931 if (save_stack == NULL)
5932 {
5933 as_bad (_("restore without save"));
5934 ignore_rest_of_line ();
5935 return;
5936 }
5937
5938 s = save_stack;
5939 save_stack = s->next;
5940
5941 m68k_abspcadd = s->abspcadd;
5942 symbols_case_sensitive = s->symbols_case_sensitive;
5943 flag_keep_locals = s->keep_locals;
5944 flag_short_refs = s->short_refs;
5945 current_architecture = s->architecture;
5946 control_regs = s->control_regs;
5947 m68k_quick = s->quick;
5948 m68k_rel32 = s->rel32;
5949 listing = s->listing;
5950 flag_no_warnings = s->no_warnings;
5951
5952 free (s);
5953
5954 demand_empty_rest_of_line ();
5955 }
5956
5957 /* Types of MRI structured control directives. */
5958
5959 enum mri_control_type
5960 {
5961 mri_for,
5962 mri_if,
5963 mri_repeat,
5964 mri_while
5965 };
5966
5967 /* This structure is used to stack the MRI structured control
5968 directives. */
5969
5970 struct mri_control_info
5971 {
5972 /* The directive within which this one is enclosed. */
5973 struct mri_control_info *outer;
5974
5975 /* The type of directive. */
5976 enum mri_control_type type;
5977
5978 /* Whether an ELSE has been in an IF. */
5979 int else_seen;
5980
5981 /* The add or sub statement at the end of a FOR. */
5982 char *incr;
5983
5984 /* The label of the top of a FOR or REPEAT loop. */
5985 char *top;
5986
5987 /* The label to jump to for the next iteration, or the else
5988 expression of a conditional. */
5989 char *next;
5990
5991 /* The label to jump to to break out of the loop, or the label past
5992 the end of a conditional. */
5993 char *bottom;
5994 };
5995
5996 /* The stack of MRI structured control directives. */
5997
5998 static struct mri_control_info *mri_control_stack;
5999
6000 /* The current MRI structured control directive index number, used to
6001 generate label names. */
6002
6003 static int mri_control_index;
6004
6005 /* Assemble an instruction for an MRI structured control directive. */
6006
6007 static void
6008 mri_assemble (char *str)
6009 {
6010 char *s;
6011
6012 /* md_assemble expects the opcode to be in lower case. */
6013 for (s = str; *s != ' ' && *s != '\0'; s++)
6014 *s = TOLOWER (*s);
6015
6016 md_assemble (str);
6017 }
6018
6019 /* Generate a new MRI label structured control directive label name. */
6020
6021 static char *
6022 mri_control_label (void)
6023 {
6024 char *n;
6025
6026 n = (char *) xmalloc (20);
6027 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6028 ++mri_control_index;
6029 return n;
6030 }
6031
6032 /* Create a new MRI structured control directive. */
6033
6034 static struct mri_control_info *
6035 push_mri_control (enum mri_control_type type)
6036 {
6037 struct mri_control_info *n;
6038
6039 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6040
6041 n->type = type;
6042 n->else_seen = 0;
6043 if (type == mri_if || type == mri_while)
6044 n->top = NULL;
6045 else
6046 n->top = mri_control_label ();
6047 n->next = mri_control_label ();
6048 n->bottom = mri_control_label ();
6049
6050 n->outer = mri_control_stack;
6051 mri_control_stack = n;
6052
6053 return n;
6054 }
6055
6056 /* Pop off the stack of MRI structured control directives. */
6057
6058 static void
6059 pop_mri_control (void)
6060 {
6061 struct mri_control_info *n;
6062
6063 n = mri_control_stack;
6064 mri_control_stack = n->outer;
6065 if (n->top != NULL)
6066 free (n->top);
6067 free (n->next);
6068 free (n->bottom);
6069 free (n);
6070 }
6071
6072 /* Recognize a condition code in an MRI structured control expression. */
6073
6074 static int
6075 parse_mri_condition (int *pcc)
6076 {
6077 char c1, c2;
6078
6079 know (*input_line_pointer == '<');
6080
6081 ++input_line_pointer;
6082 c1 = *input_line_pointer++;
6083 c2 = *input_line_pointer++;
6084
6085 if (*input_line_pointer != '>')
6086 {
6087 as_bad (_("syntax error in structured control directive"));
6088 return 0;
6089 }
6090
6091 ++input_line_pointer;
6092 SKIP_WHITESPACE ();
6093
6094 c1 = TOLOWER (c1);
6095 c2 = TOLOWER (c2);
6096
6097 *pcc = (c1 << 8) | c2;
6098
6099 return 1;
6100 }
6101
6102 /* Parse a single operand in an MRI structured control expression. */
6103
6104 static int
6105 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6106 char **rightstart, char **rightstop)
6107 {
6108 char *s;
6109
6110 SKIP_WHITESPACE ();
6111
6112 *pcc = -1;
6113 *leftstart = NULL;
6114 *leftstop = NULL;
6115 *rightstart = NULL;
6116 *rightstop = NULL;
6117
6118 if (*input_line_pointer == '<')
6119 {
6120 /* It's just a condition code. */
6121 return parse_mri_condition (pcc);
6122 }
6123
6124 /* Look ahead for the condition code. */
6125 for (s = input_line_pointer; *s != '\0'; ++s)
6126 {
6127 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6128 break;
6129 }
6130 if (*s == '\0')
6131 {
6132 as_bad (_("missing condition code in structured control directive"));
6133 return 0;
6134 }
6135
6136 *leftstart = input_line_pointer;
6137 *leftstop = s;
6138 if (*leftstop > *leftstart
6139 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6140 --*leftstop;
6141
6142 input_line_pointer = s;
6143 if (! parse_mri_condition (pcc))
6144 return 0;
6145
6146 /* Look ahead for AND or OR or end of line. */
6147 for (s = input_line_pointer; *s != '\0'; ++s)
6148 {
6149 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6150 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6151 ^^^ ^^ */
6152 if ((s == input_line_pointer
6153 || *(s-1) == ' '
6154 || *(s-1) == '\t')
6155 && ((strncasecmp (s, "AND", 3) == 0
6156 && (s[3] == '.' || ! is_part_of_name (s[3])))
6157 || (strncasecmp (s, "OR", 2) == 0
6158 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6159 break;
6160 }
6161
6162 *rightstart = input_line_pointer;
6163 *rightstop = s;
6164 if (*rightstop > *rightstart
6165 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6166 --*rightstop;
6167
6168 input_line_pointer = s;
6169
6170 return 1;
6171 }
6172
6173 #define MCC(b1, b2) (((b1) << 8) | (b2))
6174
6175 /* Swap the sense of a condition. This changes the condition so that
6176 it generates the same result when the operands are swapped. */
6177
6178 static int
6179 swap_mri_condition (int cc)
6180 {
6181 switch (cc)
6182 {
6183 case MCC ('h', 'i'): return MCC ('c', 's');
6184 case MCC ('l', 's'): return MCC ('c', 'c');
6185 /* <HS> is an alias for <CC>. */
6186 case MCC ('h', 's'):
6187 case MCC ('c', 'c'): return MCC ('l', 's');
6188 /* <LO> is an alias for <CS>. */
6189 case MCC ('l', 'o'):
6190 case MCC ('c', 's'): return MCC ('h', 'i');
6191 case MCC ('p', 'l'): return MCC ('m', 'i');
6192 case MCC ('m', 'i'): return MCC ('p', 'l');
6193 case MCC ('g', 'e'): return MCC ('l', 'e');
6194 case MCC ('l', 't'): return MCC ('g', 't');
6195 case MCC ('g', 't'): return MCC ('l', 't');
6196 case MCC ('l', 'e'): return MCC ('g', 'e');
6197 /* Issue a warning for conditions we can not swap. */
6198 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6199 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6200 case MCC ('v', 'c'):
6201 case MCC ('v', 's'):
6202 default :
6203 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6204 (char) (cc >> 8), (char) (cc));
6205 break;
6206 }
6207 return cc;
6208 }
6209
6210 /* Reverse the sense of a condition. */
6211
6212 static int
6213 reverse_mri_condition (int cc)
6214 {
6215 switch (cc)
6216 {
6217 case MCC ('h', 'i'): return MCC ('l', 's');
6218 case MCC ('l', 's'): return MCC ('h', 'i');
6219 /* <HS> is an alias for <CC> */
6220 case MCC ('h', 's'): return MCC ('l', 'o');
6221 case MCC ('c', 'c'): return MCC ('c', 's');
6222 /* <LO> is an alias for <CS> */
6223 case MCC ('l', 'o'): return MCC ('h', 's');
6224 case MCC ('c', 's'): return MCC ('c', 'c');
6225 case MCC ('n', 'e'): return MCC ('e', 'q');
6226 case MCC ('e', 'q'): return MCC ('n', 'e');
6227 case MCC ('v', 'c'): return MCC ('v', 's');
6228 case MCC ('v', 's'): return MCC ('v', 'c');
6229 case MCC ('p', 'l'): return MCC ('m', 'i');
6230 case MCC ('m', 'i'): return MCC ('p', 'l');
6231 case MCC ('g', 'e'): return MCC ('l', 't');
6232 case MCC ('l', 't'): return MCC ('g', 'e');
6233 case MCC ('g', 't'): return MCC ('l', 'e');
6234 case MCC ('l', 'e'): return MCC ('g', 't');
6235 }
6236 return cc;
6237 }
6238
6239 /* Build an MRI structured control expression. This generates test
6240 and branch instructions. It goes to TRUELAB if the condition is
6241 true, and to FALSELAB if the condition is false. Exactly one of
6242 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6243 is the size qualifier for the expression. EXTENT is the size to
6244 use for the branch. */
6245
6246 static void
6247 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6248 char *rightstart, char *rightstop,
6249 const char *truelab, const char *falselab,
6250 int extent)
6251 {
6252 char *buf;
6253 char *s;
6254
6255 if (leftstart != NULL)
6256 {
6257 struct m68k_op leftop, rightop;
6258 char c;
6259
6260 /* Swap the compare operands, if necessary, to produce a legal
6261 m68k compare instruction. Comparing a register operand with
6262 a non-register operand requires the register to be on the
6263 right (cmp, cmpa). Comparing an immediate value with
6264 anything requires the immediate value to be on the left
6265 (cmpi). */
6266
6267 c = *leftstop;
6268 *leftstop = '\0';
6269 (void) m68k_ip_op (leftstart, &leftop);
6270 *leftstop = c;
6271
6272 c = *rightstop;
6273 *rightstop = '\0';
6274 (void) m68k_ip_op (rightstart, &rightop);
6275 *rightstop = c;
6276
6277 if (rightop.mode == IMMED
6278 || ((leftop.mode == DREG || leftop.mode == AREG)
6279 && (rightop.mode != DREG && rightop.mode != AREG)))
6280 {
6281 char *temp;
6282
6283 /* Correct conditional handling:
6284 if #1 <lt> d0 then ;means if (1 < d0)
6285 ...
6286 endi
6287
6288 should assemble to:
6289
6290 cmp #1,d0 if we do *not* swap the operands
6291 bgt true we need the swapped condition!
6292 ble false
6293 true:
6294 ...
6295 false:
6296 */
6297 temp = leftstart;
6298 leftstart = rightstart;
6299 rightstart = temp;
6300 temp = leftstop;
6301 leftstop = rightstop;
6302 rightstop = temp;
6303 }
6304 else
6305 {
6306 cc = swap_mri_condition (cc);
6307 }
6308 }
6309
6310 if (truelab == NULL)
6311 {
6312 cc = reverse_mri_condition (cc);
6313 truelab = falselab;
6314 }
6315
6316 if (leftstart != NULL)
6317 {
6318 buf = (char *) xmalloc (20
6319 + (leftstop - leftstart)
6320 + (rightstop - rightstart));
6321 s = buf;
6322 *s++ = 'c';
6323 *s++ = 'm';
6324 *s++ = 'p';
6325 if (qual != '\0')
6326 *s++ = TOLOWER (qual);
6327 *s++ = ' ';
6328 memcpy (s, leftstart, leftstop - leftstart);
6329 s += leftstop - leftstart;
6330 *s++ = ',';
6331 memcpy (s, rightstart, rightstop - rightstart);
6332 s += rightstop - rightstart;
6333 *s = '\0';
6334 mri_assemble (buf);
6335 free (buf);
6336 }
6337
6338 buf = (char *) xmalloc (20 + strlen (truelab));
6339 s = buf;
6340 *s++ = 'b';
6341 *s++ = cc >> 8;
6342 *s++ = cc & 0xff;
6343 if (extent != '\0')
6344 *s++ = TOLOWER (extent);
6345 *s++ = ' ';
6346 strcpy (s, truelab);
6347 mri_assemble (buf);
6348 free (buf);
6349 }
6350
6351 /* Parse an MRI structured control expression. This generates test
6352 and branch instructions. STOP is where the expression ends. It
6353 goes to TRUELAB if the condition is true, and to FALSELAB if the
6354 condition is false. Exactly one of TRUELAB and FALSELAB will be
6355 NULL, meaning to fall through. QUAL is the size qualifier for the
6356 expression. EXTENT is the size to use for the branch. */
6357
6358 static void
6359 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6360 const char *falselab, int extent)
6361 {
6362 int c;
6363 int cc;
6364 char *leftstart;
6365 char *leftstop;
6366 char *rightstart;
6367 char *rightstop;
6368
6369 c = *stop;
6370 *stop = '\0';
6371
6372 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6373 &rightstart, &rightstop))
6374 {
6375 *stop = c;
6376 return;
6377 }
6378
6379 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6380 {
6381 const char *flab;
6382
6383 if (falselab != NULL)
6384 flab = falselab;
6385 else
6386 flab = mri_control_label ();
6387
6388 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6389 rightstop, (const char *) NULL, flab, extent);
6390
6391 input_line_pointer += 3;
6392 if (*input_line_pointer != '.'
6393 || input_line_pointer[1] == '\0')
6394 qual = '\0';
6395 else
6396 {
6397 qual = input_line_pointer[1];
6398 input_line_pointer += 2;
6399 }
6400
6401 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6402 &rightstart, &rightstop))
6403 {
6404 *stop = c;
6405 return;
6406 }
6407
6408 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6409 rightstop, truelab, falselab, extent);
6410
6411 if (falselab == NULL)
6412 colon (flab);
6413 }
6414 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6415 {
6416 const char *tlab;
6417
6418 if (truelab != NULL)
6419 tlab = truelab;
6420 else
6421 tlab = mri_control_label ();
6422
6423 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6424 rightstop, tlab, (const char *) NULL, extent);
6425
6426 input_line_pointer += 2;
6427 if (*input_line_pointer != '.'
6428 || input_line_pointer[1] == '\0')
6429 qual = '\0';
6430 else
6431 {
6432 qual = input_line_pointer[1];
6433 input_line_pointer += 2;
6434 }
6435
6436 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6437 &rightstart, &rightstop))
6438 {
6439 *stop = c;
6440 return;
6441 }
6442
6443 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6444 rightstop, truelab, falselab, extent);
6445
6446 if (truelab == NULL)
6447 colon (tlab);
6448 }
6449 else
6450 {
6451 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6452 rightstop, truelab, falselab, extent);
6453 }
6454
6455 *stop = c;
6456 if (input_line_pointer != stop)
6457 as_bad (_("syntax error in structured control directive"));
6458 }
6459
6460 /* Handle the MRI IF pseudo-op. This may be a structured control
6461 directive, or it may be a regular assembler conditional, depending
6462 on its operands. */
6463
6464 static void
6465 s_mri_if (int qual)
6466 {
6467 char *s;
6468 int c;
6469 struct mri_control_info *n;
6470
6471 /* A structured control directive must end with THEN with an
6472 optional qualifier. */
6473 s = input_line_pointer;
6474 /* We only accept '*' as introduction of comments if preceded by white space
6475 or at first column of a line (I think this can't actually happen here?)
6476 This is important when assembling:
6477 if d0 <ne> 12(a0,d0*2) then
6478 if d0 <ne> #CONST*20 then. */
6479 while (! (is_end_of_line[(unsigned char) *s]
6480 || (flag_mri
6481 && *s == '*'
6482 && (s == input_line_pointer
6483 || *(s-1) == ' '
6484 || *(s-1) == '\t'))))
6485 ++s;
6486 --s;
6487 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6488 --s;
6489
6490 if (s - input_line_pointer > 1
6491 && s[-1] == '.')
6492 s -= 2;
6493
6494 if (s - input_line_pointer < 3
6495 || strncasecmp (s - 3, "THEN", 4) != 0)
6496 {
6497 if (qual != '\0')
6498 {
6499 as_bad (_("missing then"));
6500 ignore_rest_of_line ();
6501 return;
6502 }
6503
6504 /* It's a conditional. */
6505 s_if (O_ne);
6506 return;
6507 }
6508
6509 /* Since this might be a conditional if, this pseudo-op will be
6510 called even if we are supported to be ignoring input. Double
6511 check now. Clobber *input_line_pointer so that ignore_input
6512 thinks that this is not a special pseudo-op. */
6513 c = *input_line_pointer;
6514 *input_line_pointer = 0;
6515 if (ignore_input ())
6516 {
6517 *input_line_pointer = c;
6518 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6519 ++input_line_pointer;
6520 demand_empty_rest_of_line ();
6521 return;
6522 }
6523 *input_line_pointer = c;
6524
6525 n = push_mri_control (mri_if);
6526
6527 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6528 n->next, s[1] == '.' ? s[2] : '\0');
6529
6530 if (s[1] == '.')
6531 input_line_pointer = s + 3;
6532 else
6533 input_line_pointer = s + 1;
6534
6535 if (flag_mri)
6536 {
6537 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6538 ++input_line_pointer;
6539 }
6540
6541 demand_empty_rest_of_line ();
6542 }
6543
6544 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6545 structured IF, associate the ELSE with the IF. Otherwise, assume
6546 it is a conditional else. */
6547
6548 static void
6549 s_mri_else (int qual)
6550 {
6551 int c;
6552 char *buf;
6553 char q[2];
6554
6555 if (qual == '\0'
6556 && (mri_control_stack == NULL
6557 || mri_control_stack->type != mri_if
6558 || mri_control_stack->else_seen))
6559 {
6560 s_else (0);
6561 return;
6562 }
6563
6564 c = *input_line_pointer;
6565 *input_line_pointer = 0;
6566 if (ignore_input ())
6567 {
6568 *input_line_pointer = c;
6569 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6570 ++input_line_pointer;
6571 demand_empty_rest_of_line ();
6572 return;
6573 }
6574 *input_line_pointer = c;
6575
6576 if (mri_control_stack == NULL
6577 || mri_control_stack->type != mri_if
6578 || mri_control_stack->else_seen)
6579 {
6580 as_bad (_("else without matching if"));
6581 ignore_rest_of_line ();
6582 return;
6583 }
6584
6585 mri_control_stack->else_seen = 1;
6586
6587 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6588 q[0] = TOLOWER (qual);
6589 q[1] = '\0';
6590 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6591 mri_assemble (buf);
6592 free (buf);
6593
6594 colon (mri_control_stack->next);
6595
6596 if (flag_mri)
6597 {
6598 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6599 ++input_line_pointer;
6600 }
6601
6602 demand_empty_rest_of_line ();
6603 }
6604
6605 /* Handle the MRI ENDI pseudo-op. */
6606
6607 static void
6608 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6609 {
6610 if (mri_control_stack == NULL
6611 || mri_control_stack->type != mri_if)
6612 {
6613 as_bad (_("endi without matching if"));
6614 ignore_rest_of_line ();
6615 return;
6616 }
6617
6618 /* ignore_input will not return true for ENDI, so we don't need to
6619 worry about checking it again here. */
6620
6621 if (! mri_control_stack->else_seen)
6622 colon (mri_control_stack->next);
6623 colon (mri_control_stack->bottom);
6624
6625 pop_mri_control ();
6626
6627 if (flag_mri)
6628 {
6629 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6630 ++input_line_pointer;
6631 }
6632
6633 demand_empty_rest_of_line ();
6634 }
6635
6636 /* Handle the MRI BREAK pseudo-op. */
6637
6638 static void
6639 s_mri_break (int extent)
6640 {
6641 struct mri_control_info *n;
6642 char *buf;
6643 char ex[2];
6644
6645 n = mri_control_stack;
6646 while (n != NULL
6647 && n->type != mri_for
6648 && n->type != mri_repeat
6649 && n->type != mri_while)
6650 n = n->outer;
6651 if (n == NULL)
6652 {
6653 as_bad (_("break outside of structured loop"));
6654 ignore_rest_of_line ();
6655 return;
6656 }
6657
6658 buf = (char *) xmalloc (20 + strlen (n->bottom));
6659 ex[0] = TOLOWER (extent);
6660 ex[1] = '\0';
6661 sprintf (buf, "bra%s %s", ex, n->bottom);
6662 mri_assemble (buf);
6663 free (buf);
6664
6665 if (flag_mri)
6666 {
6667 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6668 ++input_line_pointer;
6669 }
6670
6671 demand_empty_rest_of_line ();
6672 }
6673
6674 /* Handle the MRI NEXT pseudo-op. */
6675
6676 static void
6677 s_mri_next (int extent)
6678 {
6679 struct mri_control_info *n;
6680 char *buf;
6681 char ex[2];
6682
6683 n = mri_control_stack;
6684 while (n != NULL
6685 && n->type != mri_for
6686 && n->type != mri_repeat
6687 && n->type != mri_while)
6688 n = n->outer;
6689 if (n == NULL)
6690 {
6691 as_bad (_("next outside of structured loop"));
6692 ignore_rest_of_line ();
6693 return;
6694 }
6695
6696 buf = (char *) xmalloc (20 + strlen (n->next));
6697 ex[0] = TOLOWER (extent);
6698 ex[1] = '\0';
6699 sprintf (buf, "bra%s %s", ex, n->next);
6700 mri_assemble (buf);
6701 free (buf);
6702
6703 if (flag_mri)
6704 {
6705 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6706 ++input_line_pointer;
6707 }
6708
6709 demand_empty_rest_of_line ();
6710 }
6711
6712 /* Handle the MRI FOR pseudo-op. */
6713
6714 static void
6715 s_mri_for (int qual)
6716 {
6717 const char *varstart, *varstop;
6718 const char *initstart, *initstop;
6719 const char *endstart, *endstop;
6720 const char *bystart, *bystop;
6721 int up;
6722 int by;
6723 int extent;
6724 struct mri_control_info *n;
6725 char *buf;
6726 char *s;
6727 char ex[2];
6728
6729 /* The syntax is
6730 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6731 */
6732
6733 SKIP_WHITESPACE ();
6734 varstart = input_line_pointer;
6735
6736 /* Look for the '='. */
6737 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6738 && *input_line_pointer != '=')
6739 ++input_line_pointer;
6740 if (*input_line_pointer != '=')
6741 {
6742 as_bad (_("missing ="));
6743 ignore_rest_of_line ();
6744 return;
6745 }
6746
6747 varstop = input_line_pointer;
6748 if (varstop > varstart
6749 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6750 --varstop;
6751
6752 ++input_line_pointer;
6753
6754 initstart = input_line_pointer;
6755
6756 /* Look for TO or DOWNTO. */
6757 up = 1;
6758 initstop = NULL;
6759 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6760 {
6761 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6762 && ! is_part_of_name (input_line_pointer[2]))
6763 {
6764 initstop = input_line_pointer;
6765 input_line_pointer += 2;
6766 break;
6767 }
6768 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6769 && ! is_part_of_name (input_line_pointer[6]))
6770 {
6771 initstop = input_line_pointer;
6772 up = 0;
6773 input_line_pointer += 6;
6774 break;
6775 }
6776 ++input_line_pointer;
6777 }
6778 if (initstop == NULL)
6779 {
6780 as_bad (_("missing to or downto"));
6781 ignore_rest_of_line ();
6782 return;
6783 }
6784 if (initstop > initstart
6785 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6786 --initstop;
6787
6788 SKIP_WHITESPACE ();
6789 endstart = input_line_pointer;
6790
6791 /* Look for BY or DO. */
6792 by = 0;
6793 endstop = NULL;
6794 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6795 {
6796 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6797 && ! is_part_of_name (input_line_pointer[2]))
6798 {
6799 endstop = input_line_pointer;
6800 by = 1;
6801 input_line_pointer += 2;
6802 break;
6803 }
6804 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6805 && (input_line_pointer[2] == '.'
6806 || ! is_part_of_name (input_line_pointer[2])))
6807 {
6808 endstop = input_line_pointer;
6809 input_line_pointer += 2;
6810 break;
6811 }
6812 ++input_line_pointer;
6813 }
6814 if (endstop == NULL)
6815 {
6816 as_bad (_("missing do"));
6817 ignore_rest_of_line ();
6818 return;
6819 }
6820 if (endstop > endstart
6821 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6822 --endstop;
6823
6824 if (! by)
6825 {
6826 bystart = "#1";
6827 bystop = bystart + 2;
6828 }
6829 else
6830 {
6831 SKIP_WHITESPACE ();
6832 bystart = input_line_pointer;
6833
6834 /* Look for DO. */
6835 bystop = NULL;
6836 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6837 {
6838 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6839 && (input_line_pointer[2] == '.'
6840 || ! is_part_of_name (input_line_pointer[2])))
6841 {
6842 bystop = input_line_pointer;
6843 input_line_pointer += 2;
6844 break;
6845 }
6846 ++input_line_pointer;
6847 }
6848 if (bystop == NULL)
6849 {
6850 as_bad (_("missing do"));
6851 ignore_rest_of_line ();
6852 return;
6853 }
6854 if (bystop > bystart
6855 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6856 --bystop;
6857 }
6858
6859 if (*input_line_pointer != '.')
6860 extent = '\0';
6861 else
6862 {
6863 extent = input_line_pointer[1];
6864 input_line_pointer += 2;
6865 }
6866
6867 /* We have fully parsed the FOR operands. Now build the loop. */
6868 n = push_mri_control (mri_for);
6869
6870 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6871
6872 /* Move init,var. */
6873 s = buf;
6874 *s++ = 'm';
6875 *s++ = 'o';
6876 *s++ = 'v';
6877 *s++ = 'e';
6878 if (qual != '\0')
6879 *s++ = TOLOWER (qual);
6880 *s++ = ' ';
6881 memcpy (s, initstart, initstop - initstart);
6882 s += initstop - initstart;
6883 *s++ = ',';
6884 memcpy (s, varstart, varstop - varstart);
6885 s += varstop - varstart;
6886 *s = '\0';
6887 mri_assemble (buf);
6888
6889 colon (n->top);
6890
6891 /* cmp end,var. */
6892 s = buf;
6893 *s++ = 'c';
6894 *s++ = 'm';
6895 *s++ = 'p';
6896 if (qual != '\0')
6897 *s++ = TOLOWER (qual);
6898 *s++ = ' ';
6899 memcpy (s, endstart, endstop - endstart);
6900 s += endstop - endstart;
6901 *s++ = ',';
6902 memcpy (s, varstart, varstop - varstart);
6903 s += varstop - varstart;
6904 *s = '\0';
6905 mri_assemble (buf);
6906
6907 /* bcc bottom. */
6908 ex[0] = TOLOWER (extent);
6909 ex[1] = '\0';
6910 if (up)
6911 sprintf (buf, "blt%s %s", ex, n->bottom);
6912 else
6913 sprintf (buf, "bgt%s %s", ex, n->bottom);
6914 mri_assemble (buf);
6915
6916 /* Put together the add or sub instruction used by ENDF. */
6917 s = buf;
6918 if (up)
6919 strcpy (s, "add");
6920 else
6921 strcpy (s, "sub");
6922 s += 3;
6923 if (qual != '\0')
6924 *s++ = TOLOWER (qual);
6925 *s++ = ' ';
6926 memcpy (s, bystart, bystop - bystart);
6927 s += bystop - bystart;
6928 *s++ = ',';
6929 memcpy (s, varstart, varstop - varstart);
6930 s += varstop - varstart;
6931 *s = '\0';
6932 n->incr = buf;
6933
6934 if (flag_mri)
6935 {
6936 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6937 ++input_line_pointer;
6938 }
6939
6940 demand_empty_rest_of_line ();
6941 }
6942
6943 /* Handle the MRI ENDF pseudo-op. */
6944
6945 static void
6946 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6947 {
6948 if (mri_control_stack == NULL
6949 || mri_control_stack->type != mri_for)
6950 {
6951 as_bad (_("endf without for"));
6952 ignore_rest_of_line ();
6953 return;
6954 }
6955
6956 colon (mri_control_stack->next);
6957
6958 mri_assemble (mri_control_stack->incr);
6959
6960 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6961 mri_assemble (mri_control_stack->incr);
6962
6963 free (mri_control_stack->incr);
6964
6965 colon (mri_control_stack->bottom);
6966
6967 pop_mri_control ();
6968
6969 if (flag_mri)
6970 {
6971 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6972 ++input_line_pointer;
6973 }
6974
6975 demand_empty_rest_of_line ();
6976 }
6977
6978 /* Handle the MRI REPEAT pseudo-op. */
6979
6980 static void
6981 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6982 {
6983 struct mri_control_info *n;
6984
6985 n = push_mri_control (mri_repeat);
6986 colon (n->top);
6987 if (flag_mri)
6988 {
6989 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6990 ++input_line_pointer;
6991 }
6992 demand_empty_rest_of_line ();
6993 }
6994
6995 /* Handle the MRI UNTIL pseudo-op. */
6996
6997 static void
6998 s_mri_until (int qual)
6999 {
7000 char *s;
7001
7002 if (mri_control_stack == NULL
7003 || mri_control_stack->type != mri_repeat)
7004 {
7005 as_bad (_("until without repeat"));
7006 ignore_rest_of_line ();
7007 return;
7008 }
7009
7010 colon (mri_control_stack->next);
7011
7012 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7013 ;
7014
7015 parse_mri_control_expression (s, qual, (const char *) NULL,
7016 mri_control_stack->top, '\0');
7017
7018 colon (mri_control_stack->bottom);
7019
7020 input_line_pointer = s;
7021
7022 pop_mri_control ();
7023
7024 if (flag_mri)
7025 {
7026 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7027 ++input_line_pointer;
7028 }
7029
7030 demand_empty_rest_of_line ();
7031 }
7032
7033 /* Handle the MRI WHILE pseudo-op. */
7034
7035 static void
7036 s_mri_while (int qual)
7037 {
7038 char *s;
7039
7040 struct mri_control_info *n;
7041
7042 s = input_line_pointer;
7043 /* We only accept '*' as introduction of comments if preceded by white space
7044 or at first column of a line (I think this can't actually happen here?)
7045 This is important when assembling:
7046 while d0 <ne> 12(a0,d0*2) do
7047 while d0 <ne> #CONST*20 do. */
7048 while (! (is_end_of_line[(unsigned char) *s]
7049 || (flag_mri
7050 && *s == '*'
7051 && (s == input_line_pointer
7052 || *(s-1) == ' '
7053 || *(s-1) == '\t'))))
7054 s++;
7055 --s;
7056 while (*s == ' ' || *s == '\t')
7057 --s;
7058 if (s - input_line_pointer > 1
7059 && s[-1] == '.')
7060 s -= 2;
7061 if (s - input_line_pointer < 2
7062 || strncasecmp (s - 1, "DO", 2) != 0)
7063 {
7064 as_bad (_("missing do"));
7065 ignore_rest_of_line ();
7066 return;
7067 }
7068
7069 n = push_mri_control (mri_while);
7070
7071 colon (n->next);
7072
7073 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7074 s[1] == '.' ? s[2] : '\0');
7075
7076 input_line_pointer = s + 1;
7077 if (*input_line_pointer == '.')
7078 input_line_pointer += 2;
7079
7080 if (flag_mri)
7081 {
7082 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7083 ++input_line_pointer;
7084 }
7085
7086 demand_empty_rest_of_line ();
7087 }
7088
7089 /* Handle the MRI ENDW pseudo-op. */
7090
7091 static void
7092 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7093 {
7094 char *buf;
7095
7096 if (mri_control_stack == NULL
7097 || mri_control_stack->type != mri_while)
7098 {
7099 as_bad (_("endw without while"));
7100 ignore_rest_of_line ();
7101 return;
7102 }
7103
7104 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7105 sprintf (buf, "bra %s", mri_control_stack->next);
7106 mri_assemble (buf);
7107 free (buf);
7108
7109 colon (mri_control_stack->bottom);
7110
7111 pop_mri_control ();
7112
7113 if (flag_mri)
7114 {
7115 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7116 ++input_line_pointer;
7117 }
7118
7119 demand_empty_rest_of_line ();
7120 }
7121 \f
7122 /* Parse a .cpu directive. */
7123
7124 static void
7125 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7126 {
7127 char saved_char;
7128 char *name;
7129
7130 if (initialized)
7131 {
7132 as_bad (_("already assembled instructions"));
7133 ignore_rest_of_line ();
7134 return;
7135 }
7136
7137 name = input_line_pointer;
7138 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7139 input_line_pointer++;
7140 saved_char = *input_line_pointer;
7141 *input_line_pointer = 0;
7142
7143 m68k_set_cpu (name, 1, 0);
7144
7145 *input_line_pointer = saved_char;
7146 demand_empty_rest_of_line ();
7147 return;
7148 }
7149
7150 /* Parse a .arch directive. */
7151
7152 static void
7153 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7154 {
7155 char saved_char;
7156 char *name;
7157
7158 if (initialized)
7159 {
7160 as_bad (_("already assembled instructions"));
7161 ignore_rest_of_line ();
7162 return;
7163 }
7164
7165 name = input_line_pointer;
7166 while (*input_line_pointer && *input_line_pointer != ','
7167 && !ISSPACE (*input_line_pointer))
7168 input_line_pointer++;
7169 saved_char = *input_line_pointer;
7170 *input_line_pointer = 0;
7171
7172 if (m68k_set_arch (name, 1, 0))
7173 {
7174 /* Scan extensions. */
7175 do
7176 {
7177 *input_line_pointer++ = saved_char;
7178 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7179 break;
7180 name = input_line_pointer;
7181 while (*input_line_pointer && *input_line_pointer != ','
7182 && !ISSPACE (*input_line_pointer))
7183 input_line_pointer++;
7184 saved_char = *input_line_pointer;
7185 *input_line_pointer = 0;
7186 }
7187 while (m68k_set_extension (name, 1, 0));
7188 }
7189
7190 *input_line_pointer = saved_char;
7191 demand_empty_rest_of_line ();
7192 return;
7193 }
7194 \f
7195 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7196 if none is found, the caller is responsible for emitting an error
7197 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7198 cpu name, if it begins with a '6' (possibly skipping an intervening
7199 'c'. We also allow a 'c' in the same place. if NEGATED is
7200 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7201 the option is indeed negated. */
7202
7203 static const struct m68k_cpu *
7204 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7205 int allow_m, int *negated)
7206 {
7207 /* allow negated value? */
7208 if (negated)
7209 {
7210 *negated = 0;
7211
7212 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7213 {
7214 arg += 3;
7215 *negated = 1;
7216 }
7217 }
7218
7219 /* Remove 'm' or 'mc' prefix from 68k variants. */
7220 if (allow_m)
7221 {
7222 if (arg[0] == 'm')
7223 {
7224 if (arg[1] == '6')
7225 arg += 1;
7226 else if (arg[1] == 'c' && arg[2] == '6')
7227 arg += 2;
7228 }
7229 }
7230 else if (arg[0] == 'c' && arg[1] == '6')
7231 arg += 1;
7232
7233 for (; table->name; table++)
7234 if (!strcmp (arg, table->name))
7235 {
7236 if (table->alias < -1 || table->alias > 1)
7237 as_bad (_("`%s' is deprecated, use `%s'"),
7238 table->name, table[table->alias < 0 ? 1 : -1].name);
7239 return table;
7240 }
7241 return 0;
7242 }
7243
7244 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7245
7246 static int
7247 m68k_set_cpu (char const *name, int allow_m, int silent)
7248 {
7249 const struct m68k_cpu *cpu;
7250
7251 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7252
7253 if (!cpu)
7254 {
7255 if (!silent)
7256 as_bad (_("cpu `%s' unrecognized"), name);
7257 return 0;
7258 }
7259
7260 if (selected_cpu && selected_cpu != cpu)
7261 {
7262 as_bad (_("already selected `%s' processor"),
7263 selected_cpu->name);
7264 return 0;
7265 }
7266 selected_cpu = cpu;
7267 return 1;
7268 }
7269
7270 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7271
7272 static int
7273 m68k_set_arch (char const *name, int allow_m, int silent)
7274 {
7275 const struct m68k_cpu *arch;
7276
7277 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7278
7279 if (!arch)
7280 {
7281 if (!silent)
7282 as_bad (_("architecture `%s' unrecognized"), name);
7283 return 0;
7284 }
7285
7286 if (selected_arch && selected_arch != arch)
7287 {
7288 as_bad (_("already selected `%s' architecture"),
7289 selected_arch->name);
7290 return 0;
7291 }
7292
7293 selected_arch = arch;
7294 return 1;
7295 }
7296
7297 /* Set the architecture extension, issuing errors if it is
7298 unrecognized, or invalid */
7299
7300 static int
7301 m68k_set_extension (char const *name, int allow_m, int silent)
7302 {
7303 int negated;
7304 const struct m68k_cpu *ext;
7305
7306 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7307
7308 if (!ext)
7309 {
7310 if (!silent)
7311 as_bad (_("extension `%s' unrecognized"), name);
7312 return 0;
7313 }
7314
7315 if (negated)
7316 not_current_architecture |= ext->arch;
7317 else
7318 current_architecture |= ext->arch;
7319 return 1;
7320 }
7321
7322 /* md_parse_option
7323 Invocation line includes a switch not recognized by the base assembler.
7324 */
7325
7326 #ifdef OBJ_ELF
7327 const char *md_shortopts = "lSA:m:kQ:V";
7328 #else
7329 const char *md_shortopts = "lSA:m:k";
7330 #endif
7331
7332 struct option md_longopts[] = {
7333 #define OPTION_PIC (OPTION_MD_BASE)
7334 {"pic", no_argument, NULL, OPTION_PIC},
7335 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7336 {"register-prefix-optional", no_argument, NULL,
7337 OPTION_REGISTER_PREFIX_OPTIONAL},
7338 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7339 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7340 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7341 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7342 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7343 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7344 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7345 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7346 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7347 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7348 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7349 {"pcrel", no_argument, NULL, OPTION_PCREL},
7350 {NULL, no_argument, NULL, 0}
7351 };
7352 size_t md_longopts_size = sizeof (md_longopts);
7353
7354 int
7355 md_parse_option (int c, char *arg)
7356 {
7357 switch (c)
7358 {
7359 case 'l': /* -l means keep external to 2 bit offset
7360 rather than 16 bit one. */
7361 flag_short_refs = 1;
7362 break;
7363
7364 case 'S': /* -S means that jbsr's always turn into
7365 jsr's. */
7366 flag_long_jumps = 1;
7367 break;
7368
7369 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7370 branches into absolute jumps. */
7371 flag_keep_pcrel = 1;
7372 break;
7373
7374 case OPTION_PIC:
7375 case 'k':
7376 flag_want_pic = 1;
7377 break; /* -pic, Position Independent Code. */
7378
7379 case OPTION_REGISTER_PREFIX_OPTIONAL:
7380 flag_reg_prefix_optional = 1;
7381 reg_prefix_optional_seen = 1;
7382 break;
7383
7384 /* -V: SVR4 argument to print version ID. */
7385 case 'V':
7386 print_version_id ();
7387 break;
7388
7389 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7390 should be emitted or not. FIXME: Not implemented. */
7391 case 'Q':
7392 break;
7393
7394 case OPTION_BITWISE_OR:
7395 {
7396 char *n, *t;
7397 const char *s;
7398
7399 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7400 t = n;
7401 for (s = m68k_comment_chars; *s != '\0'; s++)
7402 if (*s != '|')
7403 *t++ = *s;
7404 *t = '\0';
7405 m68k_comment_chars = n;
7406 }
7407 break;
7408
7409 case OPTION_BASE_SIZE_DEFAULT_16:
7410 m68k_index_width_default = SIZE_WORD;
7411 break;
7412
7413 case OPTION_BASE_SIZE_DEFAULT_32:
7414 m68k_index_width_default = SIZE_LONG;
7415 break;
7416
7417 case OPTION_DISP_SIZE_DEFAULT_16:
7418 m68k_rel32 = 0;
7419 m68k_rel32_from_cmdline = 1;
7420 break;
7421
7422 case OPTION_DISP_SIZE_DEFAULT_32:
7423 m68k_rel32 = 1;
7424 m68k_rel32_from_cmdline = 1;
7425 break;
7426
7427 case 'A':
7428 #if WARN_DEPRECATED
7429 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7430 arg, arg));
7431 #endif
7432 /* Intentional fall-through. */
7433 case 'm':
7434 if (!strncmp (arg, "arch=", 5))
7435 m68k_set_arch (arg + 5, 1, 0);
7436 else if (!strncmp (arg, "cpu=", 4))
7437 m68k_set_cpu (arg + 4, 1, 0);
7438 else if (m68k_set_extension (arg, 0, 1))
7439 ;
7440 else if (m68k_set_arch (arg, 0, 1))
7441 ;
7442 else if (m68k_set_cpu (arg, 0, 1))
7443 ;
7444 else
7445 return 0;
7446 break;
7447
7448 default:
7449 return 0;
7450 }
7451
7452 return 1;
7453 }
7454
7455 /* Setup tables from the selected arch and/or cpu */
7456
7457 static void
7458 m68k_init_arch (void)
7459 {
7460 if (not_current_architecture & current_architecture)
7461 {
7462 as_bad (_("architecture features both enabled and disabled"));
7463 not_current_architecture &= ~current_architecture;
7464 }
7465 if (selected_arch)
7466 {
7467 current_architecture |= selected_arch->arch;
7468 control_regs = selected_arch->control_regs;
7469 }
7470 else
7471 current_architecture |= selected_cpu->arch;
7472
7473 current_architecture &= ~not_current_architecture;
7474
7475 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7476 {
7477 /* Determine which float is really meant. */
7478 if (current_architecture & (m68k_mask & ~m68881))
7479 current_architecture ^= cfloat;
7480 else
7481 current_architecture ^= m68881;
7482 }
7483
7484 if (selected_cpu)
7485 {
7486 control_regs = selected_cpu->control_regs;
7487 if (current_architecture & ~selected_cpu->arch)
7488 {
7489 as_bad (_("selected processor does not have all features of selected architecture"));
7490 current_architecture
7491 = selected_cpu->arch & ~not_current_architecture;
7492 }
7493 }
7494
7495 if ((current_architecture & m68k_mask)
7496 && (current_architecture & ~m68k_mask))
7497 {
7498 as_bad (_ ("m68k and cf features both selected"));
7499 if (current_architecture & m68k_mask)
7500 current_architecture &= m68k_mask;
7501 else
7502 current_architecture &= ~m68k_mask;
7503 }
7504
7505 /* Permit m68881 specification with all cpus; those that can't work
7506 with a coprocessor could be doing emulation. */
7507 if (current_architecture & m68851)
7508 {
7509 if (current_architecture & m68040)
7510 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7511 }
7512 /* What other incompatibilities could we check for? */
7513
7514 if (cpu_of_arch (current_architecture) < m68020
7515 || arch_coldfire_p (current_architecture))
7516 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7517
7518 initialized = 1;
7519 }
7520
7521 void
7522 md_show_usage (FILE *stream)
7523 {
7524 const char *default_cpu = TARGET_CPU;
7525 int i;
7526 unsigned int default_arch;
7527
7528 /* Get the canonical name for the default target CPU. */
7529 if (*default_cpu == 'm')
7530 default_cpu++;
7531 for (i = 0; m68k_cpus[i].name; i++)
7532 {
7533 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7534 {
7535 default_arch = m68k_cpus[i].arch;
7536 while (m68k_cpus[i].alias > 0)
7537 i--;
7538 while (m68k_cpus[i].alias < 0)
7539 i++;
7540 default_cpu = m68k_cpus[i].name;
7541 }
7542 }
7543
7544 fprintf (stream, _("\
7545 -march=<arch> set architecture\n\
7546 -mcpu=<cpu> set cpu [default %s]\n\
7547 "), default_cpu);
7548 for (i = 0; m68k_extensions[i].name; i++)
7549 fprintf (stream, _("\
7550 -m[no-]%-16s enable/disable%s architecture extension\n\
7551 "), m68k_extensions[i].name,
7552 m68k_extensions[i].alias > 0 ? " ColdFire"
7553 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7554
7555 fprintf (stream, _("\
7556 -l use 1 word for refs to undefined symbols [default 2]\n\
7557 -pic, -k generate position independent code\n\
7558 -S turn jbsr into jsr\n\
7559 --pcrel never turn PC-relative branches into absolute jumps\n\
7560 --register-prefix-optional\n\
7561 recognize register names without prefix character\n\
7562 --bitwise-or do not treat `|' as a comment character\n\
7563 --base-size-default-16 base reg without size is 16 bits\n\
7564 --base-size-default-32 base reg without size is 32 bits (default)\n\
7565 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7566 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7567 "));
7568
7569 fprintf (stream, _("Architecture variants are: "));
7570 for (i = 0; m68k_archs[i].name; i++)
7571 {
7572 if (i)
7573 fprintf (stream, " | ");
7574 fprintf (stream, m68k_archs[i].name);
7575 }
7576 fprintf (stream, "\n");
7577
7578 fprintf (stream, _("Processor variants are: "));
7579 for (i = 0; m68k_cpus[i].name; i++)
7580 {
7581 if (i)
7582 fprintf (stream, " | ");
7583 fprintf (stream, m68k_cpus[i].name);
7584 }
7585 fprintf (stream, _("\n"));
7586 }
7587 \f
7588 #ifdef TEST2
7589
7590 /* TEST2: Test md_assemble() */
7591 /* Warning, this routine probably doesn't work anymore. */
7592 int
7593 main (void)
7594 {
7595 struct m68k_it the_ins;
7596 char buf[120];
7597 char *cp;
7598 int n;
7599
7600 m68k_ip_begin ();
7601 for (;;)
7602 {
7603 if (!gets (buf) || !*buf)
7604 break;
7605 if (buf[0] == '|' || buf[1] == '.')
7606 continue;
7607 for (cp = buf; *cp; cp++)
7608 if (*cp == '\t')
7609 *cp = ' ';
7610 if (is_label (buf))
7611 continue;
7612 memset (&the_ins, '\0', sizeof (the_ins));
7613 m68k_ip (&the_ins, buf);
7614 if (the_ins.error)
7615 {
7616 printf (_("Error %s in %s\n"), the_ins.error, buf);
7617 }
7618 else
7619 {
7620 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7621 for (n = 0; n < the_ins.numo; n++)
7622 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7623 printf (" ");
7624 print_the_insn (&the_ins.opcode[0], stdout);
7625 (void) putchar ('\n');
7626 }
7627 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7628 {
7629 if (the_ins.operands[n].error)
7630 {
7631 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7632 continue;
7633 }
7634 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7635 the_ins.operands[n].reg);
7636 if (the_ins.operands[n].b_const)
7637 printf ("Constant: '%.*s', ",
7638 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7639 the_ins.operands[n].b_const);
7640 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7641 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7642 if (the_ins.operands[n].b_iadd)
7643 printf ("Iadd: '%.*s',",
7644 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7645 the_ins.operands[n].b_iadd);
7646 putchar ('\n');
7647 }
7648 }
7649 m68k_ip_end ();
7650 return 0;
7651 }
7652
7653 int
7654 is_label (char *str)
7655 {
7656 while (*str == ' ')
7657 str++;
7658 while (*str && *str != ' ')
7659 str++;
7660 if (str[-1] == ':' || str[1] == '=')
7661 return 1;
7662 return 0;
7663 }
7664
7665 #endif
7666
7667 /* Possible states for relaxation:
7668
7669 0 0 branch offset byte (bra, etc)
7670 0 1 word
7671 0 2 long
7672
7673 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7674 1 1 word
7675 1 2 long
7676
7677 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7678 2 1 word-long
7679 2 2 long-word
7680 2 3 long-long
7681
7682 */
7683
7684 /* We have no need to default values of symbols. */
7685
7686 symbolS *
7687 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7688 {
7689 return 0;
7690 }
7691
7692 /* Round up a section size to the appropriate boundary. */
7693 valueT
7694 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7695 {
7696 #ifdef OBJ_AOUT
7697 /* For a.out, force the section size to be aligned. If we don't do
7698 this, BFD will align it for us, but it will not write out the
7699 final bytes of the section. This may be a bug in BFD, but it is
7700 easier to fix it here since that is how the other a.out targets
7701 work. */
7702 int align;
7703
7704 align = bfd_get_section_alignment (stdoutput, segment);
7705 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7706 #endif
7707
7708 return size;
7709 }
7710
7711 /* Exactly what point is a PC-relative offset relative TO?
7712 On the 68k, it is relative to the address of the first extension
7713 word. The difference between the addresses of the offset and the
7714 first extension word is stored in fx_pcrel_adjust. */
7715 long
7716 md_pcrel_from (fixS *fixP)
7717 {
7718 int adjust;
7719
7720 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7721 sign extend the value here. */
7722 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7723 if (adjust == 64)
7724 adjust = -1;
7725 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7726 }
7727
7728 #ifdef OBJ_ELF
7729 void
7730 m68k_elf_final_processing (void)
7731 {
7732 unsigned flags = 0;
7733
7734 if (arch_coldfire_fpu (current_architecture))
7735 flags |= EF_M68K_CFV4E;
7736 /* Set file-specific flags if this is a cpu32 processor. */
7737 if (cpu_of_arch (current_architecture) & cpu32)
7738 flags |= EF_M68K_CPU32;
7739 else if (cpu_of_arch (current_architecture) & fido_a)
7740 flags |= EF_M68K_FIDO;
7741 else if ((cpu_of_arch (current_architecture) & m68000up)
7742 && !(cpu_of_arch (current_architecture) & m68020up))
7743 flags |= EF_M68K_M68000;
7744
7745 if (current_architecture & mcfisa_a)
7746 {
7747 static const unsigned isa_features[][2] =
7748 {
7749 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7750 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7751 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7752 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7753 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7754 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7755 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7756 {0,0},
7757 };
7758 static const unsigned mac_features[][2] =
7759 {
7760 {EF_M68K_CF_MAC, mcfmac},
7761 {EF_M68K_CF_EMAC, mcfemac},
7762 {0,0},
7763 };
7764 unsigned ix;
7765 unsigned pattern;
7766
7767 pattern = (current_architecture
7768 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7769 for (ix = 0; isa_features[ix][1]; ix++)
7770 {
7771 if (pattern == isa_features[ix][1])
7772 {
7773 flags |= isa_features[ix][0];
7774 break;
7775 }
7776 }
7777 if (!isa_features[ix][1])
7778 {
7779 cf_bad:
7780 as_warn (_("Not a defined coldfire architecture"));
7781 }
7782 else
7783 {
7784 if (current_architecture & cfloat)
7785 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7786
7787 pattern = current_architecture & (mcfmac|mcfemac);
7788 if (pattern)
7789 {
7790 for (ix = 0; mac_features[ix][1]; ix++)
7791 {
7792 if (pattern == mac_features[ix][1])
7793 {
7794 flags |= mac_features[ix][0];
7795 break;
7796 }
7797 }
7798 if (!mac_features[ix][1])
7799 goto cf_bad;
7800 }
7801 }
7802 }
7803 elf_elfheader (stdoutput)->e_flags |= flags;
7804 }
7805 #endif
7806
7807 int
7808 tc_m68k_regname_to_dw2regnum (char *regname)
7809 {
7810 unsigned int regnum;
7811 static const char *const regnames[] =
7812 {
7813 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7814 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7815 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7816 "pc"
7817 };
7818
7819 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7820 if (strcmp (regname, regnames[regnum]) == 0)
7821 return regnum;
7822
7823 return -1;
7824 }
7825
7826 void
7827 tc_m68k_frame_initial_instructions (void)
7828 {
7829 static int sp_regno = -1;
7830
7831 if (sp_regno < 0)
7832 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7833
7834 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7835 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7836 }
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