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* config/tc-m68k.c (mcf5210a_ctrl, mcf52235_ctrl, mcf5225_ctrl): New.
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5208_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182 };
183 static const enum m68k_register mcf5210a_ctrl[] = {
184 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
185 0
186 };
187 static const enum m68k_register mcf5213_ctrl[] = {
188 VBR, RAMBAR, FLASHBAR,
189 0
190 };
191 static const enum m68k_register mcf5216_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
193 0
194 };
195 static const enum m68k_register mcf52235_ctrl[] = {
196 VBR, FLASHBAR, RAMBAR,
197 0
198 };
199 static const enum m68k_register mcf5225_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR,
201 0
202 };
203 static const enum m68k_register mcf5235_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206 };
207 static const enum m68k_register mcf5249_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
209 0
210 };
211 static const enum m68k_register mcf5250_ctrl[] = {
212 VBR,
213 0
214 };
215 static const enum m68k_register mcf5271_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR,
217 0
218 };
219 static const enum m68k_register mcf5272_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
221 0
222 };
223 static const enum m68k_register mcf5275_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226 };
227 static const enum m68k_register mcf5282_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
229 0
230 };
231 static const enum m68k_register mcf5329_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR,
233 0
234 };
235 static const enum m68k_register mcf5373_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR,
237 0
238 };
239 static const enum m68k_register mcfv4e_ctrl[] = {
240 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
241 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
242 MBAR, SECMBAR,
243 MPCR /* Multiprocessor Control register */,
244 EDRAMBAR /* Embedded DRAM Base Address Register */,
245 /* Permutation control registers. */
246 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
247 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
248 /* Legacy names */
249 TC /* ASID */, BUSCR /* MMUBAR */,
250 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
251 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
252 ROMBAR /* ROMBAR0 */,
253 0
254 };
255 static const enum m68k_register mcf5475_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
258 /* Legacy names */
259 TC /* ASID */, BUSCR /* MMUBAR */,
260 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
261 MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
262 0
263 };
264 static const enum m68k_register mcf5485_ctrl[] = {
265 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
266 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
267 /* Legacy names */
268 TC /* ASID */, BUSCR /* MMUBAR */,
269 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
270 MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
271 0
272 };
273 static const enum m68k_register fido_ctrl[] = {
274 SFC, DFC, USP, VBR, CAC, MBB,
275 0
276 };
277 #define cpu32_ctrl m68010_ctrl
278
279 static const enum m68k_register *control_regs;
280
281 /* Internal form of a 68020 instruction. */
282 struct m68k_it
283 {
284 const char *error;
285 const char *args; /* List of opcode info. */
286 int numargs;
287
288 int numo; /* Number of shorts in opcode. */
289 short opcode[11];
290
291 struct m68k_op operands[6];
292
293 int nexp; /* Number of exprs in use. */
294 struct m68k_exp exprs[4];
295
296 int nfrag; /* Number of frags we have to produce. */
297 struct
298 {
299 int fragoff; /* Where in the current opcode the frag ends. */
300 symbolS *fadd;
301 offsetT foff;
302 int fragty;
303 }
304 fragb[4];
305
306 int nrel; /* Num of reloc strucs in use. */
307 struct
308 {
309 int n;
310 expressionS exp;
311 char wid;
312 char pcrel;
313 /* In a pc relative address the difference between the address
314 of the offset and the address that the offset is relative
315 to. This depends on the addressing mode. Basically this
316 is the value to put in the offset field to address the
317 first byte of the offset, without regarding the special
318 significance of some values (in the branch instruction, for
319 example). */
320 int pcrel_fix;
321 #ifdef OBJ_ELF
322 /* Whether this expression needs special pic relocation, and if
323 so, which. */
324 enum pic_relocation pic_reloc;
325 #endif
326 }
327 reloc[5]; /* Five is enough??? */
328 };
329
330 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
331 #define float_of_arch(x) ((x) & mfloat)
332 #define mmu_of_arch(x) ((x) & mmmu)
333 #define arch_coldfire_p(x) ((x) & mcfisa_a)
334 #define arch_coldfire_fpu(x) ((x) & cfloat)
335
336 /* Macros for determining if cpu supports a specific addressing mode. */
337 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
338
339 static struct m68k_it the_ins; /* The instruction being assembled. */
340
341 #define op(ex) ((ex)->exp.X_op)
342 #define adds(ex) ((ex)->exp.X_add_symbol)
343 #define subs(ex) ((ex)->exp.X_op_symbol)
344 #define offs(ex) ((ex)->exp.X_add_number)
345
346 /* Macros for adding things to the m68k_it struct. */
347 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
348
349 /* Like addword, but goes BEFORE general operands. */
350
351 static void
352 insop (int w, const struct m68k_incant *opcode)
353 {
354 int z;
355 for (z = the_ins.numo; z > opcode->m_codenum; --z)
356 the_ins.opcode[z] = the_ins.opcode[z - 1];
357 for (z = 0; z < the_ins.nrel; z++)
358 the_ins.reloc[z].n += 2;
359 for (z = 0; z < the_ins.nfrag; z++)
360 the_ins.fragb[z].fragoff++;
361 the_ins.opcode[opcode->m_codenum] = w;
362 the_ins.numo++;
363 }
364
365 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
366 Blecch. */
367 static void
368 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
369 {
370 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
371 ? the_ins.numo * 2 - 1
372 : (width == 'b'
373 ? the_ins.numo * 2 + 1
374 : the_ins.numo * 2));
375 the_ins.reloc[the_ins.nrel].exp = exp->exp;
376 the_ins.reloc[the_ins.nrel].wid = width;
377 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
378 #ifdef OBJ_ELF
379 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
380 #endif
381 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
382 }
383
384 /* Cause an extra frag to be generated here, inserting up to 10 bytes
385 (that value is chosen in the frag_var call in md_assemble). TYPE
386 is the subtype of the frag to be generated; its primary type is
387 rs_machine_dependent.
388
389 The TYPE parameter is also used by md_convert_frag_1 and
390 md_estimate_size_before_relax. The appropriate type of fixup will
391 be emitted by md_convert_frag_1.
392
393 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
394 static void
395 add_frag (symbolS *add, offsetT off, int type)
396 {
397 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
398 the_ins.fragb[the_ins.nfrag].fadd = add;
399 the_ins.fragb[the_ins.nfrag].foff = off;
400 the_ins.fragb[the_ins.nfrag++].fragty = type;
401 }
402
403 #define isvar(ex) \
404 (op (ex) != O_constant && op (ex) != O_big)
405
406 static char *crack_operand (char *str, struct m68k_op *opP);
407 static int get_num (struct m68k_exp *exp, int ok);
408 static int reverse_16_bits (int in);
409 static int reverse_8_bits (int in);
410 static void install_gen_operand (int mode, int val);
411 static void install_operand (int mode, int val);
412 static void s_bss (int);
413 static void s_data1 (int);
414 static void s_data2 (int);
415 static void s_even (int);
416 static void s_proc (int);
417 static void s_chip (int);
418 static void s_fopt (int);
419 static void s_opt (int);
420 static void s_reg (int);
421 static void s_restore (int);
422 static void s_save (int);
423 static void s_mri_if (int);
424 static void s_mri_else (int);
425 static void s_mri_endi (int);
426 static void s_mri_break (int);
427 static void s_mri_next (int);
428 static void s_mri_for (int);
429 static void s_mri_endf (int);
430 static void s_mri_repeat (int);
431 static void s_mri_until (int);
432 static void s_mri_while (int);
433 static void s_mri_endw (int);
434 static void s_m68k_cpu (int);
435 static void s_m68k_arch (int);
436
437 struct m68k_cpu
438 {
439 unsigned long arch; /* Architecture features. */
440 const enum m68k_register *control_regs; /* Control regs on chip */
441 const char *name; /* Name */
442 int alias; /* Alias for a cannonical name. If 1, then
443 succeeds canonical name, if -1 then
444 succeeds canonical name, if <-1 ||>1 this is a
445 deprecated name, and the next/previous name
446 should be used. */
447 };
448
449 /* We hold flags for features explicitly enabled and explicitly
450 disabled. */
451 static int current_architecture;
452 static int not_current_architecture;
453 static const struct m68k_cpu *selected_arch;
454 static const struct m68k_cpu *selected_cpu;
455 static int initialized;
456
457 /* Architecture models. */
458 static const struct m68k_cpu m68k_archs[] =
459 {
460 {m68000, m68000_ctrl, "68000", 0},
461 {m68010, m68010_ctrl, "68010", 0},
462 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
463 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
464 {m68040, m68040_ctrl, "68040", 0},
465 {m68060, m68060_ctrl, "68060", 0},
466 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
467 {fido_a, fido_ctrl, "fidoa", 0},
468 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
469 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
470 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
471 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
472 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
473 {0,0,NULL, 0}
474 };
475
476 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
477 for either. */
478 static const struct m68k_cpu m68k_extensions[] =
479 {
480 {m68851, NULL, "68851", -1},
481 {m68881, NULL, "68881", -1},
482 {m68881, NULL, "68882", -1},
483
484 {cfloat|m68881, NULL, "float", 0},
485
486 {mcfhwdiv, NULL, "div", 1},
487 {mcfusp, NULL, "usp", 1},
488 {mcfmac, NULL, "mac", 1},
489 {mcfemac, NULL, "emac", 1},
490
491 {0,NULL,NULL, 0}
492 };
493
494 /* Processor list */
495 static const struct m68k_cpu m68k_cpus[] =
496 {
497 {m68000, m68000_ctrl, "68000", 0},
498 {m68000, m68000_ctrl, "68ec000", 1},
499 {m68000, m68000_ctrl, "68hc000", 1},
500 {m68000, m68000_ctrl, "68hc001", 1},
501 {m68000, m68000_ctrl, "68008", 1},
502 {m68000, m68000_ctrl, "68302", 1},
503 {m68000, m68000_ctrl, "68306", 1},
504 {m68000, m68000_ctrl, "68307", 1},
505 {m68000, m68000_ctrl, "68322", 1},
506 {m68000, m68000_ctrl, "68356", 1},
507 {m68010, m68010_ctrl, "68010", 0},
508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
509 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
510 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
511 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
512 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
513 {m68040, m68040_ctrl, "68040", 0},
514 {m68040, m68040_ctrl, "68ec040", 1},
515 {m68060, m68060_ctrl, "68060", 0},
516 {m68060, m68060_ctrl, "68ec060", 1},
517
518 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
519 {cpu32|m68881, cpu32_ctrl, "68330", 1},
520 {cpu32|m68881, cpu32_ctrl, "68331", 1},
521 {cpu32|m68881, cpu32_ctrl, "68332", 1},
522 {cpu32|m68881, cpu32_ctrl, "68333", 1},
523 {cpu32|m68881, cpu32_ctrl, "68334", 1},
524 {cpu32|m68881, cpu32_ctrl, "68336", 1},
525 {cpu32|m68881, cpu32_ctrl, "68340", 1},
526 {cpu32|m68881, cpu32_ctrl, "68341", 1},
527 {cpu32|m68881, cpu32_ctrl, "68349", 1},
528 {cpu32|m68881, cpu32_ctrl, "68360", 1},
529
530 {mcfisa_a, mcf_ctrl, "5200", 0},
531 {mcfisa_a, mcf_ctrl, "5202", 1},
532 {mcfisa_a, mcf_ctrl, "5204", 1},
533 {mcfisa_a, mcf_ctrl, "5206", 1},
534
535 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
536
537 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
538 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
539
540 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
541 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
542
543 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
544 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
545 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
546
547 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
548 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
549 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
550
551 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
552 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
554 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
555
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
557 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
558
559 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
560 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
561 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
562 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
563 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
564
565 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
566 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
567
568 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
569 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
570
571 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
572
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
574 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
579 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
580
581 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
582
583 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
587
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
591
592 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
593
594 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
595 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
596 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
597 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
598 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
599 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
600 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
601
602 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
603 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
604 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
605 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
606 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
607 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
608 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
609
610 {fido_a, fido_ctrl, "fido", 1},
611
612 {0,NULL,NULL, 0}
613 };
614
615 static const struct m68k_cpu *m68k_lookup_cpu
616 (const char *, const struct m68k_cpu *, int, int *);
617 static int m68k_set_arch (const char *, int, int);
618 static int m68k_set_cpu (const char *, int, int);
619 static int m68k_set_extension (const char *, int, int);
620 static void m68k_init_arch (void);
621
622 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
623 architecture and we have a lot of relaxation modes. */
624
625 /* Macros used in the relaxation code. */
626 #define TAB(x,y) (((x) << 2) + (y))
627 #define TABTYPE(x) ((x) >> 2)
628
629 /* Relaxation states. */
630 #define BYTE 0
631 #define SHORT 1
632 #define LONG 2
633 #define SZ_UNDEF 3
634
635 /* Here are all the relaxation modes we support. First we can relax ordinary
636 branches. On 68020 and higher and on CPU32 all branch instructions take
637 three forms, so on these CPUs all branches always remain as such. When we
638 have to expand to the LONG form on a 68000, though, we substitute an
639 absolute jump instead. This is a direct replacement for unconditional
640 branches and a branch over a jump for conditional branches. However, if the
641 user requires PIC and disables this with --pcrel, we can only relax between
642 BYTE and SHORT forms, punting if that isn't enough. This gives us four
643 different relaxation modes for branches: */
644
645 #define BRANCHBWL 0 /* Branch byte, word, or long. */
646 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
647 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
648 #define BRANCHBW 3 /* Branch byte or word. */
649
650 /* We also relax coprocessor branches and DBcc's. All CPUs that support
651 coprocessor branches support them in word and long forms, so we have only
652 one relaxation mode for them. DBcc's are word only on all CPUs. We can
653 relax them to the LONG form with a branch-around sequence. This sequence
654 can use a long branch (if available) or an absolute jump (if acceptable).
655 This gives us two relaxation modes. If long branches are not available and
656 absolute jumps are not acceptable, we don't relax DBcc's. */
657
658 #define FBRANCH 4 /* Coprocessor branch. */
659 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
660 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
661
662 /* That's all for instruction relaxation. However, we also relax PC-relative
663 operands. Specifically, we have three operand relaxation modes. On the
664 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
665 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
666 two. Also PC+displacement+index operands in their simple form (with a non-
667 suppressed index without memory indirection) are supported on all CPUs, but
668 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
669 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
670 form of the PC+displacement+index operand. Finally, some absolute operands
671 can be relaxed down to 16-bit PC-relative. */
672
673 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
674 #define PCINDEX 8 /* PC + displacement + index. */
675 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
676
677 /* Note that calls to frag_var need to specify the maximum expansion
678 needed; this is currently 10 bytes for DBCC. */
679
680 /* The fields are:
681 How far Forward this mode will reach:
682 How far Backward this mode will reach:
683 How many bytes this mode will add to the size of the frag
684 Which mode to go to if the offset won't fit in this one
685
686 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
687 relax_typeS md_relax_table[] =
688 {
689 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
690 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
691 { 0, 0, 4, 0 },
692 { 1, 1, 0, 0 },
693
694 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
695 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
696 { 0, 0, 4, 0 },
697 { 1, 1, 0, 0 },
698
699 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
700 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
701 { 0, 0, 6, 0 },
702 { 1, 1, 0, 0 },
703
704 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
705 { 0, 0, 2, 0 },
706 { 1, 1, 0, 0 },
707 { 1, 1, 0, 0 },
708
709 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
710 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
711 { 0, 0, 4, 0 },
712 { 1, 1, 0, 0 },
713
714 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
715 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
716 { 0, 0, 10, 0 },
717 { 1, 1, 0, 0 },
718
719 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
720 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
721 { 0, 0, 10, 0 },
722 { 1, 1, 0, 0 },
723
724 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
725 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
726 { 0, 0, 6, 0 },
727 { 1, 1, 0, 0 },
728
729 { 125, -130, 0, TAB (PCINDEX, SHORT) },
730 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
731 { 0, 0, 4, 0 },
732 { 1, 1, 0, 0 },
733
734 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
735 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
736 { 0, 0, 4, 0 },
737 { 1, 1, 0, 0 },
738 };
739
740 /* These are the machine dependent pseudo-ops. These are included so
741 the assembler can work on the output from the SUN C compiler, which
742 generates these. */
743
744 /* This table describes all the machine specific pseudo-ops the assembler
745 has to support. The fields are:
746 pseudo-op name without dot
747 function to call to execute this pseudo-op
748 Integer arg to pass to the function. */
749 const pseudo_typeS md_pseudo_table[] =
750 {
751 {"data1", s_data1, 0},
752 {"data2", s_data2, 0},
753 {"bss", s_bss, 0},
754 {"even", s_even, 0},
755 {"skip", s_space, 0},
756 {"proc", s_proc, 0},
757 #if defined (TE_SUN3) || defined (OBJ_ELF)
758 {"align", s_align_bytes, 0},
759 #endif
760 #ifdef OBJ_ELF
761 {"swbeg", s_ignore, 0},
762 #endif
763 {"extend", float_cons, 'x'},
764 {"ldouble", float_cons, 'x'},
765
766 {"arch", s_m68k_arch, 0},
767 {"cpu", s_m68k_cpu, 0},
768
769 /* The following pseudo-ops are supported for MRI compatibility. */
770 {"chip", s_chip, 0},
771 {"comline", s_space, 1},
772 {"fopt", s_fopt, 0},
773 {"mask2", s_ignore, 0},
774 {"opt", s_opt, 0},
775 {"reg", s_reg, 0},
776 {"restore", s_restore, 0},
777 {"save", s_save, 0},
778
779 {"if", s_mri_if, 0},
780 {"if.b", s_mri_if, 'b'},
781 {"if.w", s_mri_if, 'w'},
782 {"if.l", s_mri_if, 'l'},
783 {"else", s_mri_else, 0},
784 {"else.s", s_mri_else, 's'},
785 {"else.l", s_mri_else, 'l'},
786 {"endi", s_mri_endi, 0},
787 {"break", s_mri_break, 0},
788 {"break.s", s_mri_break, 's'},
789 {"break.l", s_mri_break, 'l'},
790 {"next", s_mri_next, 0},
791 {"next.s", s_mri_next, 's'},
792 {"next.l", s_mri_next, 'l'},
793 {"for", s_mri_for, 0},
794 {"for.b", s_mri_for, 'b'},
795 {"for.w", s_mri_for, 'w'},
796 {"for.l", s_mri_for, 'l'},
797 {"endf", s_mri_endf, 0},
798 {"repeat", s_mri_repeat, 0},
799 {"until", s_mri_until, 0},
800 {"until.b", s_mri_until, 'b'},
801 {"until.w", s_mri_until, 'w'},
802 {"until.l", s_mri_until, 'l'},
803 {"while", s_mri_while, 0},
804 {"while.b", s_mri_while, 'b'},
805 {"while.w", s_mri_while, 'w'},
806 {"while.l", s_mri_while, 'l'},
807 {"endw", s_mri_endw, 0},
808
809 {0, 0, 0}
810 };
811
812 /* The mote pseudo ops are put into the opcode table, since they
813 don't start with a . they look like opcodes to gas. */
814
815 const pseudo_typeS mote_pseudo_table[] =
816 {
817
818 {"dcl", cons, 4},
819 {"dc", cons, 2},
820 {"dcw", cons, 2},
821 {"dcb", cons, 1},
822
823 {"dsl", s_space, 4},
824 {"ds", s_space, 2},
825 {"dsw", s_space, 2},
826 {"dsb", s_space, 1},
827
828 {"xdef", s_globl, 0},
829 #ifdef OBJ_ELF
830 {"align", s_align_bytes, 0},
831 #else
832 {"align", s_align_ptwo, 0},
833 #endif
834 #ifdef M68KCOFF
835 {"sect", obj_coff_section, 0},
836 {"section", obj_coff_section, 0},
837 #endif
838 {0, 0, 0}
839 };
840
841 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
842 gives identical results to a 32-bit host. */
843 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
844 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
845
846 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
847 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
848 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
849 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
850
851 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
852 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
853 #define islong(x) (1)
854
855 static char notend_table[256];
856 static char alt_notend_table[256];
857 #define notend(s) \
858 (! (notend_table[(unsigned char) *s] \
859 || (*s == ':' \
860 && alt_notend_table[(unsigned char) s[1]])))
861
862 #ifdef OBJ_ELF
863
864 /* Return zero if the reference to SYMBOL from within the same segment may
865 be relaxed. */
866
867 /* On an ELF system, we can't relax an externally visible symbol,
868 because it may be overridden by a shared library. However, if
869 TARGET_OS is "elf", then we presume that we are assembling for an
870 embedded system, in which case we don't have to worry about shared
871 libraries, and we can relax any external sym. */
872
873 #define relaxable_symbol(symbol) \
874 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
875 || S_IS_WEAK (symbol)))
876
877 /* Compute the relocation code for a fixup of SIZE bytes, using pc
878 relative relocation if PCREL is non-zero. PIC says whether a special
879 pic relocation was requested. */
880
881 static bfd_reloc_code_real_type
882 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
883 {
884 switch (pic)
885 {
886 case pic_got_pcrel:
887 switch (size)
888 {
889 case 1:
890 return BFD_RELOC_8_GOT_PCREL;
891 case 2:
892 return BFD_RELOC_16_GOT_PCREL;
893 case 4:
894 return BFD_RELOC_32_GOT_PCREL;
895 }
896 break;
897
898 case pic_got_off:
899 switch (size)
900 {
901 case 1:
902 return BFD_RELOC_8_GOTOFF;
903 case 2:
904 return BFD_RELOC_16_GOTOFF;
905 case 4:
906 return BFD_RELOC_32_GOTOFF;
907 }
908 break;
909
910 case pic_plt_pcrel:
911 switch (size)
912 {
913 case 1:
914 return BFD_RELOC_8_PLT_PCREL;
915 case 2:
916 return BFD_RELOC_16_PLT_PCREL;
917 case 4:
918 return BFD_RELOC_32_PLT_PCREL;
919 }
920 break;
921
922 case pic_plt_off:
923 switch (size)
924 {
925 case 1:
926 return BFD_RELOC_8_PLTOFF;
927 case 2:
928 return BFD_RELOC_16_PLTOFF;
929 case 4:
930 return BFD_RELOC_32_PLTOFF;
931 }
932 break;
933
934 case pic_none:
935 if (pcrel)
936 {
937 switch (size)
938 {
939 case 1:
940 return BFD_RELOC_8_PCREL;
941 case 2:
942 return BFD_RELOC_16_PCREL;
943 case 4:
944 return BFD_RELOC_32_PCREL;
945 }
946 }
947 else
948 {
949 switch (size)
950 {
951 case 1:
952 return BFD_RELOC_8;
953 case 2:
954 return BFD_RELOC_16;
955 case 4:
956 return BFD_RELOC_32;
957 }
958 }
959 }
960
961 if (pcrel)
962 {
963 if (pic == pic_none)
964 as_bad (_("Can not do %d byte pc-relative relocation"), size);
965 else
966 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
967 }
968 else
969 {
970 if (pic == pic_none)
971 as_bad (_("Can not do %d byte relocation"), size);
972 else
973 as_bad (_("Can not do %d byte pic relocation"), size);
974 }
975
976 return BFD_RELOC_NONE;
977 }
978
979 /* Here we decide which fixups can be adjusted to make them relative
980 to the beginning of the section instead of the symbol. Basically
981 we need to make sure that the dynamic relocations are done
982 correctly, so in some cases we force the original symbol to be
983 used. */
984 int
985 tc_m68k_fix_adjustable (fixS *fixP)
986 {
987 /* Adjust_reloc_syms doesn't know about the GOT. */
988 switch (fixP->fx_r_type)
989 {
990 case BFD_RELOC_8_GOT_PCREL:
991 case BFD_RELOC_16_GOT_PCREL:
992 case BFD_RELOC_32_GOT_PCREL:
993 case BFD_RELOC_8_GOTOFF:
994 case BFD_RELOC_16_GOTOFF:
995 case BFD_RELOC_32_GOTOFF:
996 case BFD_RELOC_8_PLT_PCREL:
997 case BFD_RELOC_16_PLT_PCREL:
998 case BFD_RELOC_32_PLT_PCREL:
999 case BFD_RELOC_8_PLTOFF:
1000 case BFD_RELOC_16_PLTOFF:
1001 case BFD_RELOC_32_PLTOFF:
1002 return 0;
1003
1004 case BFD_RELOC_VTABLE_INHERIT:
1005 case BFD_RELOC_VTABLE_ENTRY:
1006 return 0;
1007
1008 default:
1009 return 1;
1010 }
1011 }
1012
1013 #else /* !OBJ_ELF */
1014
1015 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1016
1017 #define relaxable_symbol(symbol) 1
1018
1019 #endif /* OBJ_ELF */
1020
1021 arelent *
1022 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1023 {
1024 arelent *reloc;
1025 bfd_reloc_code_real_type code;
1026
1027 /* If the tcbit is set, then this was a fixup of a negative value
1028 that was never resolved. We do not have a reloc to handle this,
1029 so just return. We assume that other code will have detected this
1030 situation and produced a helpful error message, so we just tell the
1031 user that the reloc cannot be produced. */
1032 if (fixp->fx_tcbit)
1033 {
1034 if (fixp->fx_addsy)
1035 as_bad_where (fixp->fx_file, fixp->fx_line,
1036 _("Unable to produce reloc against symbol '%s'"),
1037 S_GET_NAME (fixp->fx_addsy));
1038 return NULL;
1039 }
1040
1041 if (fixp->fx_r_type != BFD_RELOC_NONE)
1042 {
1043 code = fixp->fx_r_type;
1044
1045 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1046 that fixup_segment converted a non-PC relative reloc into a
1047 PC relative reloc. In such a case, we need to convert the
1048 reloc code. */
1049 if (fixp->fx_pcrel)
1050 {
1051 switch (code)
1052 {
1053 case BFD_RELOC_8:
1054 code = BFD_RELOC_8_PCREL;
1055 break;
1056 case BFD_RELOC_16:
1057 code = BFD_RELOC_16_PCREL;
1058 break;
1059 case BFD_RELOC_32:
1060 code = BFD_RELOC_32_PCREL;
1061 break;
1062 case BFD_RELOC_8_PCREL:
1063 case BFD_RELOC_16_PCREL:
1064 case BFD_RELOC_32_PCREL:
1065 case BFD_RELOC_8_GOT_PCREL:
1066 case BFD_RELOC_16_GOT_PCREL:
1067 case BFD_RELOC_32_GOT_PCREL:
1068 case BFD_RELOC_8_GOTOFF:
1069 case BFD_RELOC_16_GOTOFF:
1070 case BFD_RELOC_32_GOTOFF:
1071 case BFD_RELOC_8_PLT_PCREL:
1072 case BFD_RELOC_16_PLT_PCREL:
1073 case BFD_RELOC_32_PLT_PCREL:
1074 case BFD_RELOC_8_PLTOFF:
1075 case BFD_RELOC_16_PLTOFF:
1076 case BFD_RELOC_32_PLTOFF:
1077 break;
1078 default:
1079 as_bad_where (fixp->fx_file, fixp->fx_line,
1080 _("Cannot make %s relocation PC relative"),
1081 bfd_get_reloc_code_name (code));
1082 }
1083 }
1084 }
1085 else
1086 {
1087 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1088 switch (F (fixp->fx_size, fixp->fx_pcrel))
1089 {
1090 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1091 MAP (1, 0, BFD_RELOC_8);
1092 MAP (2, 0, BFD_RELOC_16);
1093 MAP (4, 0, BFD_RELOC_32);
1094 MAP (1, 1, BFD_RELOC_8_PCREL);
1095 MAP (2, 1, BFD_RELOC_16_PCREL);
1096 MAP (4, 1, BFD_RELOC_32_PCREL);
1097 default:
1098 abort ();
1099 }
1100 }
1101 #undef F
1102 #undef MAP
1103
1104 reloc = (arelent *) xmalloc (sizeof (arelent));
1105 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1106 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1107 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1108 #ifndef OBJ_ELF
1109 if (fixp->fx_pcrel)
1110 reloc->addend = fixp->fx_addnumber;
1111 else
1112 reloc->addend = 0;
1113 #else
1114 if (!fixp->fx_pcrel)
1115 reloc->addend = fixp->fx_addnumber;
1116 else
1117 reloc->addend = (section->vma
1118 /* Explicit sign extension in case char is
1119 unsigned. */
1120 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1121 + fixp->fx_addnumber
1122 + md_pcrel_from (fixp));
1123 #endif
1124
1125 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1126 assert (reloc->howto != 0);
1127
1128 return reloc;
1129 }
1130
1131 /* Handle of the OPCODE hash table. NULL means any use before
1132 m68k_ip_begin() will crash. */
1133 static struct hash_control *op_hash;
1134 \f
1135 /* Assemble an m68k instruction. */
1136
1137 static void
1138 m68k_ip (char *instring)
1139 {
1140 register char *p;
1141 register struct m68k_op *opP;
1142 register const struct m68k_incant *opcode;
1143 register const char *s;
1144 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1145 char *pdot, *pdotmove;
1146 enum m68k_size siz1, siz2;
1147 char c;
1148 int losing;
1149 int opsfound;
1150 struct m68k_op operands_backup[6];
1151 LITTLENUM_TYPE words[6];
1152 LITTLENUM_TYPE *wordp;
1153 unsigned long ok_arch = 0;
1154
1155 if (*instring == ' ')
1156 instring++; /* Skip leading whitespace. */
1157
1158 /* Scan up to end of operation-code, which MUST end in end-of-string
1159 or exactly 1 space. */
1160 pdot = 0;
1161 for (p = instring; *p != '\0'; p++)
1162 {
1163 if (*p == ' ')
1164 break;
1165 if (*p == '.')
1166 pdot = p;
1167 }
1168
1169 if (p == instring)
1170 {
1171 the_ins.error = _("No operator");
1172 return;
1173 }
1174
1175 /* p now points to the end of the opcode name, probably whitespace.
1176 Make sure the name is null terminated by clobbering the
1177 whitespace, look it up in the hash table, then fix it back.
1178 Remove a dot, first, since the opcode tables have none. */
1179 if (pdot != NULL)
1180 {
1181 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1182 *pdotmove = pdotmove[1];
1183 p--;
1184 }
1185
1186 c = *p;
1187 *p = '\0';
1188 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1189 *p = c;
1190
1191 if (pdot != NULL)
1192 {
1193 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1194 *pdotmove = pdotmove[-1];
1195 *pdot = '.';
1196 ++p;
1197 }
1198
1199 if (opcode == NULL)
1200 {
1201 the_ins.error = _("Unknown operator");
1202 return;
1203 }
1204
1205 /* Found a legitimate opcode, start matching operands. */
1206 while (*p == ' ')
1207 ++p;
1208
1209 if (opcode->m_operands == 0)
1210 {
1211 char *old = input_line_pointer;
1212 *old = '\n';
1213 input_line_pointer = p;
1214 /* Ahh - it's a motorola style psuedo op. */
1215 mote_pseudo_table[opcode->m_opnum].poc_handler
1216 (mote_pseudo_table[opcode->m_opnum].poc_val);
1217 input_line_pointer = old;
1218 *old = 0;
1219
1220 return;
1221 }
1222
1223 if (flag_mri && opcode->m_opnum == 0)
1224 {
1225 /* In MRI mode, random garbage is allowed after an instruction
1226 which accepts no operands. */
1227 the_ins.args = opcode->m_operands;
1228 the_ins.numargs = opcode->m_opnum;
1229 the_ins.numo = opcode->m_codenum;
1230 the_ins.opcode[0] = getone (opcode);
1231 the_ins.opcode[1] = gettwo (opcode);
1232 return;
1233 }
1234
1235 for (opP = &the_ins.operands[0]; *p; opP++)
1236 {
1237 p = crack_operand (p, opP);
1238
1239 if (opP->error)
1240 {
1241 the_ins.error = opP->error;
1242 return;
1243 }
1244 }
1245
1246 opsfound = opP - &the_ins.operands[0];
1247
1248 /* This ugly hack is to support the floating pt opcodes in their
1249 standard form. Essentially, we fake a first enty of type COP#1 */
1250 if (opcode->m_operands[0] == 'I')
1251 {
1252 int n;
1253
1254 for (n = opsfound; n > 0; --n)
1255 the_ins.operands[n] = the_ins.operands[n - 1];
1256
1257 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1258 the_ins.operands[0].mode = CONTROL;
1259 the_ins.operands[0].reg = m68k_float_copnum;
1260 opsfound++;
1261 }
1262
1263 /* We've got the operands. Find an opcode that'll accept them. */
1264 for (losing = 0;;)
1265 {
1266 /* If we didn't get the right number of ops, or we have no
1267 common model with this pattern then reject this pattern. */
1268
1269 ok_arch |= opcode->m_arch;
1270 if (opsfound != opcode->m_opnum
1271 || ((opcode->m_arch & current_architecture) == 0))
1272 ++losing;
1273 else
1274 {
1275 int i;
1276
1277 /* Make a copy of the operands of this insn so that
1278 we can modify them safely, should we want to. */
1279 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1280 for (i = 0; i < opsfound; i++)
1281 operands_backup[i] = the_ins.operands[i];
1282
1283 for (s = opcode->m_operands, opP = &operands_backup[0];
1284 *s && !losing;
1285 s += 2, opP++)
1286 {
1287 /* Warning: this switch is huge! */
1288 /* I've tried to organize the cases into this order:
1289 non-alpha first, then alpha by letter. Lower-case
1290 goes directly before uppercase counterpart. */
1291 /* Code with multiple case ...: gets sorted by the lowest
1292 case ... it belongs to. I hope this makes sense. */
1293 switch (*s)
1294 {
1295 case '!':
1296 switch (opP->mode)
1297 {
1298 case IMMED:
1299 case DREG:
1300 case AREG:
1301 case FPREG:
1302 case CONTROL:
1303 case AINC:
1304 case ADEC:
1305 case REGLST:
1306 losing++;
1307 break;
1308 default:
1309 break;
1310 }
1311 break;
1312
1313 case '<':
1314 switch (opP->mode)
1315 {
1316 case DREG:
1317 case AREG:
1318 case FPREG:
1319 case CONTROL:
1320 case IMMED:
1321 case ADEC:
1322 case REGLST:
1323 losing++;
1324 break;
1325 default:
1326 break;
1327 }
1328 break;
1329
1330 case '>':
1331 switch (opP->mode)
1332 {
1333 case DREG:
1334 case AREG:
1335 case FPREG:
1336 case CONTROL:
1337 case IMMED:
1338 case AINC:
1339 case REGLST:
1340 losing++;
1341 break;
1342 case ABSL:
1343 break;
1344 default:
1345 if (opP->reg == PC
1346 || opP->reg == ZPC)
1347 losing++;
1348 break;
1349 }
1350 break;
1351
1352 case 'm':
1353 switch (opP->mode)
1354 {
1355 case DREG:
1356 case AREG:
1357 case AINDR:
1358 case AINC:
1359 case ADEC:
1360 break;
1361 default:
1362 losing++;
1363 }
1364 break;
1365
1366 case 'n':
1367 switch (opP->mode)
1368 {
1369 case DISP:
1370 break;
1371 default:
1372 losing++;
1373 }
1374 break;
1375
1376 case 'o':
1377 switch (opP->mode)
1378 {
1379 case BASE:
1380 case ABSL:
1381 case IMMED:
1382 break;
1383 default:
1384 losing++;
1385 }
1386 break;
1387
1388 case 'p':
1389 switch (opP->mode)
1390 {
1391 case DREG:
1392 case AREG:
1393 case AINDR:
1394 case AINC:
1395 case ADEC:
1396 break;
1397 case DISP:
1398 if (opP->reg == PC || opP->reg == ZPC)
1399 losing++;
1400 break;
1401 default:
1402 losing++;
1403 }
1404 break;
1405
1406 case 'q':
1407 switch (opP->mode)
1408 {
1409 case DREG:
1410 case AINDR:
1411 case AINC:
1412 case ADEC:
1413 break;
1414 case DISP:
1415 if (opP->reg == PC || opP->reg == ZPC)
1416 losing++;
1417 break;
1418 default:
1419 losing++;
1420 break;
1421 }
1422 break;
1423
1424 case 'v':
1425 switch (opP->mode)
1426 {
1427 case DREG:
1428 case AINDR:
1429 case AINC:
1430 case ADEC:
1431 case ABSL:
1432 break;
1433 case DISP:
1434 if (opP->reg == PC || opP->reg == ZPC)
1435 losing++;
1436 break;
1437 default:
1438 losing++;
1439 break;
1440 }
1441 break;
1442
1443 case '#':
1444 if (opP->mode != IMMED)
1445 losing++;
1446 else if (s[1] == 'b'
1447 && ! isvar (&opP->disp)
1448 && (opP->disp.exp.X_op != O_constant
1449 || ! isbyte (opP->disp.exp.X_add_number)))
1450 losing++;
1451 else if (s[1] == 'B'
1452 && ! isvar (&opP->disp)
1453 && (opP->disp.exp.X_op != O_constant
1454 || ! issbyte (opP->disp.exp.X_add_number)))
1455 losing++;
1456 else if (s[1] == 'w'
1457 && ! isvar (&opP->disp)
1458 && (opP->disp.exp.X_op != O_constant
1459 || ! isword (opP->disp.exp.X_add_number)))
1460 losing++;
1461 else if (s[1] == 'W'
1462 && ! isvar (&opP->disp)
1463 && (opP->disp.exp.X_op != O_constant
1464 || ! issword (opP->disp.exp.X_add_number)))
1465 losing++;
1466 break;
1467
1468 case '^':
1469 case 'T':
1470 if (opP->mode != IMMED)
1471 losing++;
1472 break;
1473
1474 case '$':
1475 if (opP->mode == AREG
1476 || opP->mode == CONTROL
1477 || opP->mode == FPREG
1478 || opP->mode == IMMED
1479 || opP->mode == REGLST
1480 || (opP->mode != ABSL
1481 && (opP->reg == PC
1482 || opP->reg == ZPC)))
1483 losing++;
1484 break;
1485
1486 case '%':
1487 if (opP->mode == CONTROL
1488 || opP->mode == FPREG
1489 || opP->mode == REGLST
1490 || opP->mode == IMMED
1491 || (opP->mode != ABSL
1492 && (opP->reg == PC
1493 || opP->reg == ZPC)))
1494 losing++;
1495 break;
1496
1497 case '&':
1498 switch (opP->mode)
1499 {
1500 case DREG:
1501 case AREG:
1502 case FPREG:
1503 case CONTROL:
1504 case IMMED:
1505 case AINC:
1506 case ADEC:
1507 case REGLST:
1508 losing++;
1509 break;
1510 case ABSL:
1511 break;
1512 default:
1513 if (opP->reg == PC
1514 || opP->reg == ZPC)
1515 losing++;
1516 break;
1517 }
1518 break;
1519
1520 case '*':
1521 if (opP->mode == CONTROL
1522 || opP->mode == FPREG
1523 || opP->mode == REGLST)
1524 losing++;
1525 break;
1526
1527 case '+':
1528 if (opP->mode != AINC)
1529 losing++;
1530 break;
1531
1532 case '-':
1533 if (opP->mode != ADEC)
1534 losing++;
1535 break;
1536
1537 case '/':
1538 switch (opP->mode)
1539 {
1540 case AREG:
1541 case CONTROL:
1542 case FPREG:
1543 case AINC:
1544 case ADEC:
1545 case IMMED:
1546 case REGLST:
1547 losing++;
1548 break;
1549 default:
1550 break;
1551 }
1552 break;
1553
1554 case ';':
1555 switch (opP->mode)
1556 {
1557 case AREG:
1558 case CONTROL:
1559 case FPREG:
1560 case REGLST:
1561 losing++;
1562 break;
1563 default:
1564 break;
1565 }
1566 break;
1567
1568 case '?':
1569 switch (opP->mode)
1570 {
1571 case AREG:
1572 case CONTROL:
1573 case FPREG:
1574 case AINC:
1575 case ADEC:
1576 case IMMED:
1577 case REGLST:
1578 losing++;
1579 break;
1580 case ABSL:
1581 break;
1582 default:
1583 if (opP->reg == PC || opP->reg == ZPC)
1584 losing++;
1585 break;
1586 }
1587 break;
1588
1589 case '@':
1590 switch (opP->mode)
1591 {
1592 case AREG:
1593 case CONTROL:
1594 case FPREG:
1595 case IMMED:
1596 case REGLST:
1597 losing++;
1598 break;
1599 default:
1600 break;
1601 }
1602 break;
1603
1604 case '~': /* For now! (JF FOO is this right?) */
1605 switch (opP->mode)
1606 {
1607 case DREG:
1608 case AREG:
1609 case CONTROL:
1610 case FPREG:
1611 case IMMED:
1612 case REGLST:
1613 losing++;
1614 break;
1615 case ABSL:
1616 break;
1617 default:
1618 if (opP->reg == PC
1619 || opP->reg == ZPC)
1620 losing++;
1621 break;
1622 }
1623 break;
1624
1625 case '3':
1626 if (opP->mode != CONTROL
1627 || (opP->reg != TT0 && opP->reg != TT1))
1628 losing++;
1629 break;
1630
1631 case 'A':
1632 if (opP->mode != AREG)
1633 losing++;
1634 break;
1635
1636 case 'a':
1637 if (opP->mode != AINDR)
1638 ++losing;
1639 break;
1640
1641 case '4':
1642 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1643 && (opP->mode != DISP
1644 || opP->reg < ADDR0
1645 || opP->reg > ADDR7))
1646 ++losing;
1647 break;
1648
1649 case 'B': /* FOO */
1650 if (opP->mode != ABSL
1651 || (flag_long_jumps
1652 && strncmp (instring, "jbsr", 4) == 0))
1653 losing++;
1654 break;
1655
1656 case 'b':
1657 switch (opP->mode)
1658 {
1659 case IMMED:
1660 case ABSL:
1661 case AREG:
1662 case FPREG:
1663 case CONTROL:
1664 case POST:
1665 case PRE:
1666 case REGLST:
1667 losing++;
1668 break;
1669 default:
1670 break;
1671 }
1672 break;
1673
1674 case 'C':
1675 if (opP->mode != CONTROL || opP->reg != CCR)
1676 losing++;
1677 break;
1678
1679 case 'd':
1680 if (opP->mode != DISP
1681 || opP->reg < ADDR0
1682 || opP->reg > ADDR7)
1683 losing++;
1684 break;
1685
1686 case 'D':
1687 if (opP->mode != DREG)
1688 losing++;
1689 break;
1690
1691 case 'E':
1692 if (opP->reg != ACC)
1693 losing++;
1694 break;
1695
1696 case 'e':
1697 if (opP->reg != ACC && opP->reg != ACC1
1698 && opP->reg != ACC2 && opP->reg != ACC3)
1699 losing++;
1700 break;
1701
1702 case 'F':
1703 if (opP->mode != FPREG)
1704 losing++;
1705 break;
1706
1707 case 'G':
1708 if (opP->reg != MACSR)
1709 losing++;
1710 break;
1711
1712 case 'g':
1713 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1714 losing++;
1715 break;
1716
1717 case 'H':
1718 if (opP->reg != MASK)
1719 losing++;
1720 break;
1721
1722 case 'I':
1723 if (opP->mode != CONTROL
1724 || opP->reg < COP0
1725 || opP->reg > COP7)
1726 losing++;
1727 break;
1728
1729 case 'i':
1730 if (opP->mode != LSH && opP->mode != RSH)
1731 losing++;
1732 break;
1733
1734 case 'J':
1735 if (opP->mode != CONTROL
1736 || opP->reg < USP
1737 || opP->reg > last_movec_reg
1738 || !control_regs)
1739 losing++;
1740 else
1741 {
1742 const enum m68k_register *rp;
1743
1744 for (rp = control_regs; *rp; rp++)
1745 if (*rp == opP->reg)
1746 break;
1747 if (*rp == 0)
1748 losing++;
1749 }
1750 break;
1751
1752 case 'k':
1753 if (opP->mode != IMMED)
1754 losing++;
1755 break;
1756
1757 case 'l':
1758 case 'L':
1759 if (opP->mode == DREG
1760 || opP->mode == AREG
1761 || opP->mode == FPREG)
1762 {
1763 if (s[1] == '8')
1764 losing++;
1765 else
1766 {
1767 switch (opP->mode)
1768 {
1769 case DREG:
1770 opP->mask = 1 << (opP->reg - DATA0);
1771 break;
1772 case AREG:
1773 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1774 break;
1775 case FPREG:
1776 opP->mask = 1 << (opP->reg - FP0 + 16);
1777 break;
1778 default:
1779 abort ();
1780 }
1781 opP->mode = REGLST;
1782 }
1783 }
1784 else if (opP->mode == CONTROL)
1785 {
1786 if (s[1] != '8')
1787 losing++;
1788 else
1789 {
1790 switch (opP->reg)
1791 {
1792 case FPI:
1793 opP->mask = 1 << 24;
1794 break;
1795 case FPS:
1796 opP->mask = 1 << 25;
1797 break;
1798 case FPC:
1799 opP->mask = 1 << 26;
1800 break;
1801 default:
1802 losing++;
1803 break;
1804 }
1805 opP->mode = REGLST;
1806 }
1807 }
1808 else if (opP->mode != REGLST)
1809 losing++;
1810 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1811 losing++;
1812 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1813 losing++;
1814 break;
1815
1816 case 'M':
1817 if (opP->mode != IMMED)
1818 losing++;
1819 else if (opP->disp.exp.X_op != O_constant
1820 || ! issbyte (opP->disp.exp.X_add_number))
1821 losing++;
1822 else if (! m68k_quick
1823 && instring[3] != 'q'
1824 && instring[4] != 'q')
1825 losing++;
1826 break;
1827
1828 case 'O':
1829 if (opP->mode != DREG
1830 && opP->mode != IMMED
1831 && opP->mode != ABSL)
1832 losing++;
1833 break;
1834
1835 case 'Q':
1836 if (opP->mode != IMMED)
1837 losing++;
1838 else if (opP->disp.exp.X_op != O_constant
1839 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1840 losing++;
1841 else if (! m68k_quick
1842 && (strncmp (instring, "add", 3) == 0
1843 || strncmp (instring, "sub", 3) == 0)
1844 && instring[3] != 'q')
1845 losing++;
1846 break;
1847
1848 case 'R':
1849 if (opP->mode != DREG && opP->mode != AREG)
1850 losing++;
1851 break;
1852
1853 case 'r':
1854 if (opP->mode != AINDR
1855 && (opP->mode != BASE
1856 || (opP->reg != 0
1857 && opP->reg != ZADDR0)
1858 || opP->disp.exp.X_op != O_absent
1859 || ((opP->index.reg < DATA0
1860 || opP->index.reg > DATA7)
1861 && (opP->index.reg < ADDR0
1862 || opP->index.reg > ADDR7))
1863 || opP->index.size != SIZE_UNSPEC
1864 || opP->index.scale != 1))
1865 losing++;
1866 break;
1867
1868 case 's':
1869 if (opP->mode != CONTROL
1870 || ! (opP->reg == FPI
1871 || opP->reg == FPS
1872 || opP->reg == FPC))
1873 losing++;
1874 break;
1875
1876 case 'S':
1877 if (opP->mode != CONTROL || opP->reg != SR)
1878 losing++;
1879 break;
1880
1881 case 't':
1882 if (opP->mode != IMMED)
1883 losing++;
1884 else if (opP->disp.exp.X_op != O_constant
1885 || TRUNC (opP->disp.exp.X_add_number) > 7)
1886 losing++;
1887 break;
1888
1889 case 'U':
1890 if (opP->mode != CONTROL || opP->reg != USP)
1891 losing++;
1892 break;
1893
1894 case 'x':
1895 if (opP->mode != IMMED)
1896 losing++;
1897 else if (opP->disp.exp.X_op != O_constant
1898 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1899 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1900 losing++;
1901 break;
1902
1903 /* JF these are out of order. We could put them
1904 in order if we were willing to put up with
1905 bunches of #ifdef m68851s in the code.
1906
1907 Don't forget that you need these operands
1908 to use 68030 MMU instructions. */
1909 #ifndef NO_68851
1910 /* Memory addressing mode used by pflushr. */
1911 case '|':
1912 if (opP->mode == CONTROL
1913 || opP->mode == FPREG
1914 || opP->mode == DREG
1915 || opP->mode == AREG
1916 || opP->mode == REGLST)
1917 losing++;
1918 /* We should accept immediate operands, but they
1919 supposedly have to be quad word, and we don't
1920 handle that. I would like to see what a Motorola
1921 assembler does before doing something here. */
1922 if (opP->mode == IMMED)
1923 losing++;
1924 break;
1925
1926 case 'f':
1927 if (opP->mode != CONTROL
1928 || (opP->reg != SFC && opP->reg != DFC))
1929 losing++;
1930 break;
1931
1932 case '0':
1933 if (opP->mode != CONTROL || opP->reg != TC)
1934 losing++;
1935 break;
1936
1937 case '1':
1938 if (opP->mode != CONTROL || opP->reg != AC)
1939 losing++;
1940 break;
1941
1942 case '2':
1943 if (opP->mode != CONTROL
1944 || (opP->reg != CAL
1945 && opP->reg != VAL
1946 && opP->reg != SCC))
1947 losing++;
1948 break;
1949
1950 case 'V':
1951 if (opP->mode != CONTROL
1952 || opP->reg != VAL)
1953 losing++;
1954 break;
1955
1956 case 'W':
1957 if (opP->mode != CONTROL
1958 || (opP->reg != DRP
1959 && opP->reg != SRP
1960 && opP->reg != CRP))
1961 losing++;
1962 break;
1963
1964 case 'w':
1965 switch (opP->mode)
1966 {
1967 case IMMED:
1968 case ABSL:
1969 case AREG:
1970 case DREG:
1971 case FPREG:
1972 case CONTROL:
1973 case POST:
1974 case PRE:
1975 case REGLST:
1976 losing++;
1977 break;
1978 default:
1979 break;
1980 }
1981 break;
1982
1983 case 'X':
1984 if (opP->mode != CONTROL
1985 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1986 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1987 losing++;
1988 break;
1989
1990 case 'Y':
1991 if (opP->mode != CONTROL || opP->reg != PSR)
1992 losing++;
1993 break;
1994
1995 case 'Z':
1996 if (opP->mode != CONTROL || opP->reg != PCSR)
1997 losing++;
1998 break;
1999 #endif
2000 case 'c':
2001 if (opP->mode != CONTROL
2002 || (opP->reg != NC
2003 && opP->reg != IC
2004 && opP->reg != DC
2005 && opP->reg != BC))
2006 losing++;
2007 break;
2008
2009 case '_':
2010 if (opP->mode != ABSL)
2011 ++losing;
2012 break;
2013
2014 case 'u':
2015 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2016 losing++;
2017 /* FIXME: kludge instead of fixing parser:
2018 upper/lower registers are *not* CONTROL
2019 registers, but ordinary ones. */
2020 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2021 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2022 opP->mode = DREG;
2023 else
2024 opP->mode = AREG;
2025 break;
2026
2027 case 'y':
2028 if (!(opP->mode == AINDR
2029 || (opP->mode == DISP
2030 && !(opP->reg == PC || opP->reg == ZPC))))
2031 losing++;
2032 break;
2033
2034 case 'z':
2035 if (!(opP->mode == AINDR || opP->mode == DISP))
2036 losing++;
2037 break;
2038
2039 default:
2040 abort ();
2041 }
2042
2043 if (losing)
2044 break;
2045 }
2046
2047 /* Since we have found the correct instruction, copy
2048 in the modifications that we may have made. */
2049 if (!losing)
2050 for (i = 0; i < opsfound; i++)
2051 the_ins.operands[i] = operands_backup[i];
2052 }
2053
2054 if (!losing)
2055 break;
2056
2057 opcode = opcode->m_next;
2058
2059 if (!opcode)
2060 {
2061 if (ok_arch
2062 && !(ok_arch & current_architecture))
2063 {
2064 const struct m68k_cpu *cpu;
2065 int any = 0;
2066 size_t space = 400;
2067 char *buf = xmalloc (space + 1);
2068 size_t len;
2069 int paren = 1;
2070
2071 the_ins.error = buf;
2072 /* Make sure there's a NUL at the end of the buffer -- strncpy
2073 won't write one when it runs out of buffer */
2074 buf[space] = 0;
2075 #define APPEND(STRING) \
2076 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2077
2078 APPEND (_("invalid instruction for this architecture; needs "));
2079 switch (ok_arch)
2080 {
2081 case mcfisa_a:
2082 APPEND (_("ColdFire ISA_A"));
2083 break;
2084 case mcfhwdiv:
2085 APPEND (_("ColdFire hardware divide"));
2086 break;
2087 case mcfisa_aa:
2088 APPEND (_("ColdFire ISA_A+"));
2089 break;
2090 case mcfisa_b:
2091 APPEND (_("ColdFire ISA_B"));
2092 break;
2093 case cfloat:
2094 APPEND (_("ColdFire fpu"));
2095 break;
2096 case mfloat:
2097 APPEND (_("M68K fpu"));
2098 break;
2099 case mmmu:
2100 APPEND (_("M68K mmu"));
2101 break;
2102 case m68020up:
2103 APPEND (_("68020 or higher"));
2104 break;
2105 case m68000up:
2106 APPEND (_("68000 or higher"));
2107 break;
2108 case m68010up:
2109 APPEND (_("68010 or higher"));
2110 break;
2111 default:
2112 paren = 0;
2113 }
2114 if (paren)
2115 APPEND (" (");
2116
2117 for (cpu = m68k_cpus; cpu->name; cpu++)
2118 if (!cpu->alias && (cpu->arch & ok_arch))
2119 {
2120 const struct m68k_cpu *alias;
2121 int seen_master = 0;
2122
2123 if (any)
2124 APPEND (", ");
2125 any = 0;
2126 APPEND (cpu->name);
2127 for (alias = cpu; alias != m68k_cpus; alias--)
2128 if (alias[-1].alias >= 0)
2129 break;
2130 for (; !seen_master || alias->alias > 0; alias++)
2131 {
2132 if (!alias->alias)
2133 seen_master = 1;
2134 else
2135 {
2136 if (any)
2137 APPEND (", ");
2138 else
2139 APPEND (" [");
2140 APPEND (alias->name);
2141 any = 1;
2142 }
2143 }
2144 if (any)
2145 APPEND ("]");
2146 any = 1;
2147 }
2148 if (paren)
2149 APPEND (")");
2150 #undef APPEND
2151 if (!space)
2152 {
2153 /* we ran out of space, so replace the end of the list
2154 with ellipsis. */
2155 buf -= 4;
2156 while (*buf != ' ')
2157 buf--;
2158 strcpy (buf, " ...");
2159 }
2160 }
2161 else
2162 the_ins.error = _("operands mismatch");
2163 return;
2164 }
2165
2166 losing = 0;
2167 }
2168
2169 /* Now assemble it. */
2170 the_ins.args = opcode->m_operands;
2171 the_ins.numargs = opcode->m_opnum;
2172 the_ins.numo = opcode->m_codenum;
2173 the_ins.opcode[0] = getone (opcode);
2174 the_ins.opcode[1] = gettwo (opcode);
2175
2176 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2177 {
2178 /* This switch is a doozy.
2179 Watch the first step; its a big one! */
2180 switch (s[0])
2181 {
2182
2183 case '*':
2184 case '~':
2185 case '%':
2186 case ';':
2187 case '@':
2188 case '!':
2189 case '&':
2190 case '$':
2191 case '?':
2192 case '/':
2193 case '<':
2194 case '>':
2195 case 'b':
2196 case 'm':
2197 case 'n':
2198 case 'o':
2199 case 'p':
2200 case 'q':
2201 case 'v':
2202 case 'w':
2203 case 'y':
2204 case 'z':
2205 case '4':
2206 #ifndef NO_68851
2207 case '|':
2208 #endif
2209 switch (opP->mode)
2210 {
2211 case IMMED:
2212 tmpreg = 0x3c; /* 7.4 */
2213 if (strchr ("bwl", s[1]))
2214 nextword = get_num (&opP->disp, 90);
2215 else
2216 nextword = get_num (&opP->disp, 0);
2217 if (isvar (&opP->disp))
2218 add_fix (s[1], &opP->disp, 0, 0);
2219 switch (s[1])
2220 {
2221 case 'b':
2222 if (!isbyte (nextword))
2223 opP->error = _("operand out of range");
2224 addword (nextword);
2225 baseo = 0;
2226 break;
2227 case 'w':
2228 if (!isword (nextword))
2229 opP->error = _("operand out of range");
2230 addword (nextword);
2231 baseo = 0;
2232 break;
2233 case 'W':
2234 if (!issword (nextword))
2235 opP->error = _("operand out of range");
2236 addword (nextword);
2237 baseo = 0;
2238 break;
2239 case 'l':
2240 addword (nextword >> 16);
2241 addword (nextword);
2242 baseo = 0;
2243 break;
2244
2245 case 'f':
2246 baseo = 2;
2247 outro = 8;
2248 break;
2249 case 'F':
2250 baseo = 4;
2251 outro = 11;
2252 break;
2253 case 'x':
2254 baseo = 6;
2255 outro = 15;
2256 break;
2257 case 'p':
2258 baseo = 6;
2259 outro = -1;
2260 break;
2261 default:
2262 abort ();
2263 }
2264 if (!baseo)
2265 break;
2266
2267 /* We gotta put out some float. */
2268 if (op (&opP->disp) != O_big)
2269 {
2270 valueT val;
2271 int gencnt;
2272
2273 /* Can other cases happen here? */
2274 if (op (&opP->disp) != O_constant)
2275 abort ();
2276
2277 val = (valueT) offs (&opP->disp);
2278 gencnt = 0;
2279 do
2280 {
2281 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2282 val >>= LITTLENUM_NUMBER_OF_BITS;
2283 ++gencnt;
2284 }
2285 while (val != 0);
2286 offs (&opP->disp) = gencnt;
2287 }
2288 if (offs (&opP->disp) > 0)
2289 {
2290 if (offs (&opP->disp) > baseo)
2291 {
2292 as_warn (_("Bignum too big for %c format; truncated"),
2293 s[1]);
2294 offs (&opP->disp) = baseo;
2295 }
2296 baseo -= offs (&opP->disp);
2297 while (baseo--)
2298 addword (0);
2299 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2300 offs (&opP->disp)--;
2301 --wordp)
2302 addword (*wordp);
2303 break;
2304 }
2305 gen_to_words (words, baseo, (long) outro);
2306 for (wordp = words; baseo--; wordp++)
2307 addword (*wordp);
2308 break;
2309 case DREG:
2310 tmpreg = opP->reg - DATA; /* 0.dreg */
2311 break;
2312 case AREG:
2313 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2314 break;
2315 case AINDR:
2316 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2317 break;
2318 case ADEC:
2319 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2320 break;
2321 case AINC:
2322 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2323 break;
2324 case DISP:
2325
2326 nextword = get_num (&opP->disp, 90);
2327
2328 /* Convert mode 5 addressing with a zero offset into
2329 mode 2 addressing to reduce the instruction size by a
2330 word. */
2331 if (! isvar (&opP->disp)
2332 && (nextword == 0)
2333 && (opP->disp.size == SIZE_UNSPEC)
2334 && (opP->reg >= ADDR0)
2335 && (opP->reg <= ADDR7))
2336 {
2337 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2338 break;
2339 }
2340
2341 if (opP->reg == PC
2342 && ! isvar (&opP->disp)
2343 && m68k_abspcadd)
2344 {
2345 opP->disp.exp.X_op = O_symbol;
2346 opP->disp.exp.X_add_symbol =
2347 section_symbol (absolute_section);
2348 }
2349
2350 /* Force into index mode. Hope this works. */
2351
2352 /* We do the first bit for 32-bit displacements, and the
2353 second bit for 16 bit ones. It is possible that we
2354 should make the default be WORD instead of LONG, but
2355 I think that'd break GCC, so we put up with a little
2356 inefficiency for the sake of working output. */
2357
2358 if (!issword (nextword)
2359 || (isvar (&opP->disp)
2360 && ((opP->disp.size == SIZE_UNSPEC
2361 && flag_short_refs == 0
2362 && cpu_of_arch (current_architecture) >= m68020
2363 && ! arch_coldfire_p (current_architecture))
2364 || opP->disp.size == SIZE_LONG)))
2365 {
2366 if (cpu_of_arch (current_architecture) < m68020
2367 || arch_coldfire_p (current_architecture))
2368 opP->error =
2369 _("displacement too large for this architecture; needs 68020 or higher");
2370 if (opP->reg == PC)
2371 tmpreg = 0x3B; /* 7.3 */
2372 else
2373 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2374 if (isvar (&opP->disp))
2375 {
2376 if (opP->reg == PC)
2377 {
2378 if (opP->disp.size == SIZE_LONG
2379 #ifdef OBJ_ELF
2380 /* If the displacement needs pic
2381 relocation it cannot be relaxed. */
2382 || opP->disp.pic_reloc != pic_none
2383 #endif
2384 )
2385 {
2386 addword (0x0170);
2387 add_fix ('l', &opP->disp, 1, 2);
2388 }
2389 else
2390 {
2391 add_frag (adds (&opP->disp),
2392 SEXT (offs (&opP->disp)),
2393 TAB (PCREL1632, SZ_UNDEF));
2394 break;
2395 }
2396 }
2397 else
2398 {
2399 addword (0x0170);
2400 add_fix ('l', &opP->disp, 0, 0);
2401 }
2402 }
2403 else
2404 addword (0x0170);
2405 addword (nextword >> 16);
2406 }
2407 else
2408 {
2409 if (opP->reg == PC)
2410 tmpreg = 0x3A; /* 7.2 */
2411 else
2412 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2413
2414 if (isvar (&opP->disp))
2415 {
2416 if (opP->reg == PC)
2417 {
2418 add_fix ('w', &opP->disp, 1, 0);
2419 }
2420 else
2421 add_fix ('w', &opP->disp, 0, 0);
2422 }
2423 }
2424 addword (nextword);
2425 break;
2426
2427 case POST:
2428 case PRE:
2429 case BASE:
2430 nextword = 0;
2431 baseo = get_num (&opP->disp, 90);
2432 if (opP->mode == POST || opP->mode == PRE)
2433 outro = get_num (&opP->odisp, 90);
2434 /* Figure out the `addressing mode'.
2435 Also turn on the BASE_DISABLE bit, if needed. */
2436 if (opP->reg == PC || opP->reg == ZPC)
2437 {
2438 tmpreg = 0x3b; /* 7.3 */
2439 if (opP->reg == ZPC)
2440 nextword |= 0x80;
2441 }
2442 else if (opP->reg == 0)
2443 {
2444 nextword |= 0x80;
2445 tmpreg = 0x30; /* 6.garbage */
2446 }
2447 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2448 {
2449 nextword |= 0x80;
2450 tmpreg = 0x30 + opP->reg - ZADDR0;
2451 }
2452 else
2453 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2454
2455 siz1 = opP->disp.size;
2456 if (opP->mode == POST || opP->mode == PRE)
2457 siz2 = opP->odisp.size;
2458 else
2459 siz2 = SIZE_UNSPEC;
2460
2461 /* Index register stuff. */
2462 if (opP->index.reg != 0
2463 && opP->index.reg >= DATA
2464 && opP->index.reg <= ADDR7)
2465 {
2466 nextword |= (opP->index.reg - DATA) << 12;
2467
2468 if (opP->index.size == SIZE_LONG
2469 || (opP->index.size == SIZE_UNSPEC
2470 && m68k_index_width_default == SIZE_LONG))
2471 nextword |= 0x800;
2472
2473 if ((opP->index.scale != 1
2474 && cpu_of_arch (current_architecture) < m68020)
2475 || (opP->index.scale == 8
2476 && (arch_coldfire_p (current_architecture)
2477 && !arch_coldfire_fpu (current_architecture))))
2478 {
2479 opP->error =
2480 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2481 }
2482
2483 if (arch_coldfire_p (current_architecture)
2484 && opP->index.size == SIZE_WORD)
2485 opP->error = _("invalid index size for coldfire");
2486
2487 switch (opP->index.scale)
2488 {
2489 case 1:
2490 break;
2491 case 2:
2492 nextword |= 0x200;
2493 break;
2494 case 4:
2495 nextword |= 0x400;
2496 break;
2497 case 8:
2498 nextword |= 0x600;
2499 break;
2500 default:
2501 abort ();
2502 }
2503 /* IF its simple,
2504 GET US OUT OF HERE! */
2505
2506 /* Must be INDEX, with an index register. Address
2507 register cannot be ZERO-PC, and either :b was
2508 forced, or we know it will fit. For a 68000 or
2509 68010, force this mode anyways, because the
2510 larger modes aren't supported. */
2511 if (opP->mode == BASE
2512 && ((opP->reg >= ADDR0
2513 && opP->reg <= ADDR7)
2514 || opP->reg == PC))
2515 {
2516 if (siz1 == SIZE_BYTE
2517 || cpu_of_arch (current_architecture) < m68020
2518 || arch_coldfire_p (current_architecture)
2519 || (siz1 == SIZE_UNSPEC
2520 && ! isvar (&opP->disp)
2521 && issbyte (baseo)))
2522 {
2523 nextword += baseo & 0xff;
2524 addword (nextword);
2525 if (isvar (&opP->disp))
2526 {
2527 /* Do a byte relocation. If it doesn't
2528 fit (possible on m68000) let the
2529 fixup processing complain later. */
2530 if (opP->reg == PC)
2531 add_fix ('B', &opP->disp, 1, 1);
2532 else
2533 add_fix ('B', &opP->disp, 0, 0);
2534 }
2535 else if (siz1 != SIZE_BYTE)
2536 {
2537 if (siz1 != SIZE_UNSPEC)
2538 as_warn (_("Forcing byte displacement"));
2539 if (! issbyte (baseo))
2540 opP->error = _("byte displacement out of range");
2541 }
2542
2543 break;
2544 }
2545 else if (siz1 == SIZE_UNSPEC
2546 && opP->reg == PC
2547 && isvar (&opP->disp)
2548 && subs (&opP->disp) == NULL
2549 #ifdef OBJ_ELF
2550 /* If the displacement needs pic
2551 relocation it cannot be relaxed. */
2552 && opP->disp.pic_reloc == pic_none
2553 #endif
2554 )
2555 {
2556 /* The code in md_convert_frag_1 needs to be
2557 able to adjust nextword. Call frag_grow
2558 to ensure that we have enough space in
2559 the frag obstack to make all the bytes
2560 contiguous. */
2561 frag_grow (14);
2562 nextword += baseo & 0xff;
2563 addword (nextword);
2564 add_frag (adds (&opP->disp),
2565 SEXT (offs (&opP->disp)),
2566 TAB (PCINDEX, SZ_UNDEF));
2567
2568 break;
2569 }
2570 }
2571 }
2572 else
2573 {
2574 nextword |= 0x40; /* No index reg. */
2575 if (opP->index.reg >= ZDATA0
2576 && opP->index.reg <= ZDATA7)
2577 nextword |= (opP->index.reg - ZDATA0) << 12;
2578 else if (opP->index.reg >= ZADDR0
2579 || opP->index.reg <= ZADDR7)
2580 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2581 }
2582
2583 /* It isn't simple. */
2584
2585 if (cpu_of_arch (current_architecture) < m68020
2586 || arch_coldfire_p (current_architecture))
2587 opP->error =
2588 _("invalid operand mode for this architecture; needs 68020 or higher");
2589
2590 nextword |= 0x100;
2591 /* If the guy specified a width, we assume that it is
2592 wide enough. Maybe it isn't. If so, we lose. */
2593 switch (siz1)
2594 {
2595 case SIZE_UNSPEC:
2596 if (isvar (&opP->disp)
2597 ? m68k_rel32
2598 : ! issword (baseo))
2599 {
2600 siz1 = SIZE_LONG;
2601 nextword |= 0x30;
2602 }
2603 else if (! isvar (&opP->disp) && baseo == 0)
2604 nextword |= 0x10;
2605 else
2606 {
2607 nextword |= 0x20;
2608 siz1 = SIZE_WORD;
2609 }
2610 break;
2611 case SIZE_BYTE:
2612 as_warn (_(":b not permitted; defaulting to :w"));
2613 /* Fall through. */
2614 case SIZE_WORD:
2615 nextword |= 0x20;
2616 break;
2617 case SIZE_LONG:
2618 nextword |= 0x30;
2619 break;
2620 }
2621
2622 /* Figure out inner displacement stuff. */
2623 if (opP->mode == POST || opP->mode == PRE)
2624 {
2625 if (cpu_of_arch (current_architecture) & cpu32)
2626 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2627 switch (siz2)
2628 {
2629 case SIZE_UNSPEC:
2630 if (isvar (&opP->odisp)
2631 ? m68k_rel32
2632 : ! issword (outro))
2633 {
2634 siz2 = SIZE_LONG;
2635 nextword |= 0x3;
2636 }
2637 else if (! isvar (&opP->odisp) && outro == 0)
2638 nextword |= 0x1;
2639 else
2640 {
2641 nextword |= 0x2;
2642 siz2 = SIZE_WORD;
2643 }
2644 break;
2645 case 1:
2646 as_warn (_(":b not permitted; defaulting to :w"));
2647 /* Fall through. */
2648 case 2:
2649 nextword |= 0x2;
2650 break;
2651 case 3:
2652 nextword |= 0x3;
2653 break;
2654 }
2655 if (opP->mode == POST
2656 && (nextword & 0x40) == 0)
2657 nextword |= 0x04;
2658 }
2659 addword (nextword);
2660
2661 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2662 {
2663 if (opP->reg == PC || opP->reg == ZPC)
2664 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2665 else
2666 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2667 }
2668 if (siz1 == SIZE_LONG)
2669 addword (baseo >> 16);
2670 if (siz1 != SIZE_UNSPEC)
2671 addword (baseo);
2672
2673 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2674 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2675 if (siz2 == SIZE_LONG)
2676 addword (outro >> 16);
2677 if (siz2 != SIZE_UNSPEC)
2678 addword (outro);
2679
2680 break;
2681
2682 case ABSL:
2683 nextword = get_num (&opP->disp, 90);
2684 switch (opP->disp.size)
2685 {
2686 default:
2687 abort ();
2688 case SIZE_UNSPEC:
2689 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2690 {
2691 tmpreg = 0x38; /* 7.0 */
2692 addword (nextword);
2693 break;
2694 }
2695 if (isvar (&opP->disp)
2696 && !subs (&opP->disp)
2697 && adds (&opP->disp)
2698 #ifdef OBJ_ELF
2699 /* If the displacement needs pic relocation it
2700 cannot be relaxed. */
2701 && opP->disp.pic_reloc == pic_none
2702 #endif
2703 && !flag_long_jumps
2704 && !strchr ("~%&$?", s[0]))
2705 {
2706 tmpreg = 0x3A; /* 7.2 */
2707 add_frag (adds (&opP->disp),
2708 SEXT (offs (&opP->disp)),
2709 TAB (ABSTOPCREL, SZ_UNDEF));
2710 break;
2711 }
2712 /* Fall through into long. */
2713 case SIZE_LONG:
2714 if (isvar (&opP->disp))
2715 add_fix ('l', &opP->disp, 0, 0);
2716
2717 tmpreg = 0x39;/* 7.1 mode */
2718 addword (nextword >> 16);
2719 addword (nextword);
2720 break;
2721
2722 case SIZE_BYTE:
2723 as_bad (_("unsupported byte value; use a different suffix"));
2724 /* Fall through. */
2725
2726 case SIZE_WORD:
2727 if (isvar (&opP->disp))
2728 add_fix ('w', &opP->disp, 0, 0);
2729
2730 tmpreg = 0x38;/* 7.0 mode */
2731 addword (nextword);
2732 break;
2733 }
2734 break;
2735 case CONTROL:
2736 case FPREG:
2737 default:
2738 as_bad (_("unknown/incorrect operand"));
2739 /* abort (); */
2740 }
2741
2742 /* If s[0] is '4', then this is for the mac instructions
2743 that can have a trailing_ampersand set. If so, set 0x100
2744 bit on tmpreg so install_gen_operand can check for it and
2745 set the appropriate bit (word2, bit 5). */
2746 if (s[0] == '4')
2747 {
2748 if (opP->trailing_ampersand)
2749 tmpreg |= 0x100;
2750 }
2751 install_gen_operand (s[1], tmpreg);
2752 break;
2753
2754 case '#':
2755 case '^':
2756 switch (s[1])
2757 { /* JF: I hate floating point! */
2758 case 'j':
2759 tmpreg = 70;
2760 break;
2761 case '8':
2762 tmpreg = 20;
2763 break;
2764 case 'C':
2765 tmpreg = 50;
2766 break;
2767 case '3':
2768 default:
2769 tmpreg = 90;
2770 break;
2771 }
2772 tmpreg = get_num (&opP->disp, tmpreg);
2773 if (isvar (&opP->disp))
2774 add_fix (s[1], &opP->disp, 0, 0);
2775 switch (s[1])
2776 {
2777 case 'b': /* Danger: These do no check for
2778 certain types of overflow.
2779 user beware! */
2780 if (!isbyte (tmpreg))
2781 opP->error = _("out of range");
2782 insop (tmpreg, opcode);
2783 if (isvar (&opP->disp))
2784 the_ins.reloc[the_ins.nrel - 1].n =
2785 (opcode->m_codenum) * 2 + 1;
2786 break;
2787 case 'B':
2788 if (!issbyte (tmpreg))
2789 opP->error = _("out of range");
2790 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2791 if (isvar (&opP->disp))
2792 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2793 break;
2794 case 'w':
2795 if (!isword (tmpreg))
2796 opP->error = _("out of range");
2797 insop (tmpreg, opcode);
2798 if (isvar (&opP->disp))
2799 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2800 break;
2801 case 'W':
2802 if (!issword (tmpreg))
2803 opP->error = _("out of range");
2804 insop (tmpreg, opcode);
2805 if (isvar (&opP->disp))
2806 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2807 break;
2808 case 'l':
2809 /* Because of the way insop works, we put these two out
2810 backwards. */
2811 insop (tmpreg, opcode);
2812 insop (tmpreg >> 16, opcode);
2813 if (isvar (&opP->disp))
2814 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2815 break;
2816 case '3':
2817 tmpreg &= 0xFF;
2818 case '8':
2819 case 'C':
2820 case 'j':
2821 install_operand (s[1], tmpreg);
2822 break;
2823 default:
2824 abort ();
2825 }
2826 break;
2827
2828 case '+':
2829 case '-':
2830 case 'A':
2831 case 'a':
2832 install_operand (s[1], opP->reg - ADDR);
2833 break;
2834
2835 case 'B':
2836 tmpreg = get_num (&opP->disp, 90);
2837 switch (s[1])
2838 {
2839 case 'B':
2840 add_fix ('B', &opP->disp, 1, -1);
2841 break;
2842 case 'W':
2843 add_fix ('w', &opP->disp, 1, 0);
2844 addword (0);
2845 break;
2846 case 'L':
2847 long_branch:
2848 if (! HAVE_LONG_BRANCH (current_architecture))
2849 as_warn (_("Can't use long branches on 68000/68010/5200"));
2850 the_ins.opcode[0] |= 0xff;
2851 add_fix ('l', &opP->disp, 1, 0);
2852 addword (0);
2853 addword (0);
2854 break;
2855 case 'g':
2856 if (subs (&opP->disp)) /* We can't relax it. */
2857 goto long_branch;
2858
2859 #ifdef OBJ_ELF
2860 /* If the displacement needs pic relocation it cannot be
2861 relaxed. */
2862 if (opP->disp.pic_reloc != pic_none)
2863 goto long_branch;
2864 #endif
2865 /* This could either be a symbol, or an absolute
2866 address. If it's an absolute address, turn it into
2867 an absolute jump right here and keep it out of the
2868 relaxer. */
2869 if (adds (&opP->disp) == 0)
2870 {
2871 if (the_ins.opcode[0] == 0x6000) /* jbra */
2872 the_ins.opcode[0] = 0x4EF9;
2873 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2874 the_ins.opcode[0] = 0x4EB9;
2875 else /* jCC */
2876 {
2877 the_ins.opcode[0] ^= 0x0100;
2878 the_ins.opcode[0] |= 0x0006;
2879 addword (0x4EF9);
2880 }
2881 add_fix ('l', &opP->disp, 0, 0);
2882 addword (0);
2883 addword (0);
2884 break;
2885 }
2886
2887 /* Now we know it's going into the relaxer. Now figure
2888 out which mode. We try in this order of preference:
2889 long branch, absolute jump, byte/word branches only. */
2890 if (HAVE_LONG_BRANCH (current_architecture))
2891 add_frag (adds (&opP->disp),
2892 SEXT (offs (&opP->disp)),
2893 TAB (BRANCHBWL, SZ_UNDEF));
2894 else if (! flag_keep_pcrel)
2895 {
2896 if ((the_ins.opcode[0] == 0x6000)
2897 || (the_ins.opcode[0] == 0x6100))
2898 add_frag (adds (&opP->disp),
2899 SEXT (offs (&opP->disp)),
2900 TAB (BRABSJUNC, SZ_UNDEF));
2901 else
2902 add_frag (adds (&opP->disp),
2903 SEXT (offs (&opP->disp)),
2904 TAB (BRABSJCOND, SZ_UNDEF));
2905 }
2906 else
2907 add_frag (adds (&opP->disp),
2908 SEXT (offs (&opP->disp)),
2909 TAB (BRANCHBW, SZ_UNDEF));
2910 break;
2911 case 'w':
2912 if (isvar (&opP->disp))
2913 {
2914 /* Check for DBcc instructions. We can relax them,
2915 but only if we have long branches and/or absolute
2916 jumps. */
2917 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2918 && (HAVE_LONG_BRANCH (current_architecture)
2919 || (! flag_keep_pcrel)))
2920 {
2921 if (HAVE_LONG_BRANCH (current_architecture))
2922 add_frag (adds (&opP->disp),
2923 SEXT (offs (&opP->disp)),
2924 TAB (DBCCLBR, SZ_UNDEF));
2925 else
2926 add_frag (adds (&opP->disp),
2927 SEXT (offs (&opP->disp)),
2928 TAB (DBCCABSJ, SZ_UNDEF));
2929 break;
2930 }
2931 add_fix ('w', &opP->disp, 1, 0);
2932 }
2933 addword (0);
2934 break;
2935 case 'C': /* Fixed size LONG coproc branches. */
2936 add_fix ('l', &opP->disp, 1, 0);
2937 addword (0);
2938 addword (0);
2939 break;
2940 case 'c': /* Var size Coprocesssor branches. */
2941 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2942 {
2943 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2944 add_fix ('l', &opP->disp, 1, 0);
2945 addword (0);
2946 addword (0);
2947 }
2948 else
2949 add_frag (adds (&opP->disp),
2950 SEXT (offs (&opP->disp)),
2951 TAB (FBRANCH, SZ_UNDEF));
2952 break;
2953 default:
2954 abort ();
2955 }
2956 break;
2957
2958 case 'C': /* Ignore it. */
2959 break;
2960
2961 case 'd': /* JF this is a kludge. */
2962 install_operand ('s', opP->reg - ADDR);
2963 tmpreg = get_num (&opP->disp, 90);
2964 if (!issword (tmpreg))
2965 {
2966 as_warn (_("Expression out of range, using 0"));
2967 tmpreg = 0;
2968 }
2969 addword (tmpreg);
2970 break;
2971
2972 case 'D':
2973 install_operand (s[1], opP->reg - DATA);
2974 break;
2975
2976 case 'e': /* EMAC ACCx, reg/reg. */
2977 install_operand (s[1], opP->reg - ACC);
2978 break;
2979
2980 case 'E': /* Ignore it. */
2981 break;
2982
2983 case 'F':
2984 install_operand (s[1], opP->reg - FP0);
2985 break;
2986
2987 case 'g': /* EMAC ACCEXTx. */
2988 install_operand (s[1], opP->reg - ACCEXT01);
2989 break;
2990
2991 case 'G': /* Ignore it. */
2992 case 'H':
2993 break;
2994
2995 case 'I':
2996 tmpreg = opP->reg - COP0;
2997 install_operand (s[1], tmpreg);
2998 break;
2999
3000 case 'i': /* MAC/EMAC scale factor. */
3001 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3002 break;
3003
3004 case 'J': /* JF foo. */
3005 switch (opP->reg)
3006 {
3007 case SFC:
3008 tmpreg = 0x000;
3009 break;
3010 case DFC:
3011 tmpreg = 0x001;
3012 break;
3013 case CACR:
3014 tmpreg = 0x002;
3015 break;
3016 case TC:
3017 case ASID:
3018 tmpreg = 0x003;
3019 break;
3020 case ACR0:
3021 case ITT0:
3022 tmpreg = 0x004;
3023 break;
3024 case ACR1:
3025 case ITT1:
3026 tmpreg = 0x005;
3027 break;
3028 case ACR2:
3029 case DTT0:
3030 tmpreg = 0x006;
3031 break;
3032 case ACR3:
3033 case DTT1:
3034 tmpreg = 0x007;
3035 break;
3036 case BUSCR:
3037 case MMUBAR:
3038 tmpreg = 0x008;
3039 break;
3040
3041 case USP:
3042 tmpreg = 0x800;
3043 break;
3044 case VBR:
3045 tmpreg = 0x801;
3046 break;
3047 case CAAR:
3048 tmpreg = 0x802;
3049 break;
3050 case MSP:
3051 tmpreg = 0x803;
3052 break;
3053 case ISP:
3054 tmpreg = 0x804;
3055 break;
3056 case MMUSR:
3057 tmpreg = 0x805;
3058 break;
3059 case URP:
3060 tmpreg = 0x806;
3061 break;
3062 case SRP:
3063 tmpreg = 0x807;
3064 break;
3065 case PCR:
3066 tmpreg = 0x808;
3067 break;
3068 case ROMBAR:
3069 case ROMBAR0:
3070 tmpreg = 0xC00;
3071 break;
3072 case ROMBAR1:
3073 tmpreg = 0xC01;
3074 break;
3075 case FLASHBAR:
3076 case RAMBAR0:
3077 tmpreg = 0xC04;
3078 break;
3079 case RAMBAR:
3080 case RAMBAR1:
3081 tmpreg = 0xC05;
3082 break;
3083 case MPCR:
3084 tmpreg = 0xC0C;
3085 break;
3086 case EDRAMBAR:
3087 tmpreg = 0xC0D;
3088 break;
3089 case MBAR0:
3090 case MBAR2:
3091 case SECMBAR:
3092 tmpreg = 0xC0E;
3093 break;
3094 case MBAR1:
3095 case MBAR:
3096 tmpreg = 0xC0F;
3097 break;
3098 case PCR1U0:
3099 tmpreg = 0xD02;
3100 break;
3101 case PCR1L0:
3102 tmpreg = 0xD03;
3103 break;
3104 case PCR2U0:
3105 tmpreg = 0xD04;
3106 break;
3107 case PCR2L0:
3108 tmpreg = 0xD05;
3109 break;
3110 case PCR3U0:
3111 tmpreg = 0xD06;
3112 break;
3113 case PCR3L0:
3114 tmpreg = 0xD07;
3115 break;
3116 case PCR1L1:
3117 tmpreg = 0xD0A;
3118 break;
3119 case PCR1U1:
3120 tmpreg = 0xD0B;
3121 break;
3122 case PCR2L1:
3123 tmpreg = 0xD0C;
3124 break;
3125 case PCR2U1:
3126 tmpreg = 0xD0D;
3127 break;
3128 case PCR3L1:
3129 tmpreg = 0xD0E;
3130 break;
3131 case PCR3U1:
3132 tmpreg = 0xD0F;
3133 break;
3134 case CAC:
3135 tmpreg = 0xFFE;
3136 break;
3137 case MBB:
3138 tmpreg = 0xFFF;
3139 break;
3140 default:
3141 abort ();
3142 }
3143 install_operand (s[1], tmpreg);
3144 break;
3145
3146 case 'k':
3147 tmpreg = get_num (&opP->disp, 55);
3148 install_operand (s[1], tmpreg & 0x7f);
3149 break;
3150
3151 case 'l':
3152 tmpreg = opP->mask;
3153 if (s[1] == 'w')
3154 {
3155 if (tmpreg & 0x7FF0000)
3156 as_bad (_("Floating point register in register list"));
3157 insop (reverse_16_bits (tmpreg), opcode);
3158 }
3159 else
3160 {
3161 if (tmpreg & 0x700FFFF)
3162 as_bad (_("Wrong register in floating-point reglist"));
3163 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3164 }
3165 break;
3166
3167 case 'L':
3168 tmpreg = opP->mask;
3169 if (s[1] == 'w')
3170 {
3171 if (tmpreg & 0x7FF0000)
3172 as_bad (_("Floating point register in register list"));
3173 insop (tmpreg, opcode);
3174 }
3175 else if (s[1] == '8')
3176 {
3177 if (tmpreg & 0x0FFFFFF)
3178 as_bad (_("incorrect register in reglist"));
3179 install_operand (s[1], tmpreg >> 24);
3180 }
3181 else
3182 {
3183 if (tmpreg & 0x700FFFF)
3184 as_bad (_("wrong register in floating-point reglist"));
3185 else
3186 install_operand (s[1], tmpreg >> 16);
3187 }
3188 break;
3189
3190 case 'M':
3191 install_operand (s[1], get_num (&opP->disp, 60));
3192 break;
3193
3194 case 'O':
3195 tmpreg = ((opP->mode == DREG)
3196 ? 0x20 + (int) (opP->reg - DATA)
3197 : (get_num (&opP->disp, 40) & 0x1F));
3198 install_operand (s[1], tmpreg);
3199 break;
3200
3201 case 'Q':
3202 tmpreg = get_num (&opP->disp, 10);
3203 if (tmpreg == 8)
3204 tmpreg = 0;
3205 install_operand (s[1], tmpreg);
3206 break;
3207
3208 case 'R':
3209 /* This depends on the fact that ADDR registers are eight
3210 more than their corresponding DATA regs, so the result
3211 will have the ADDR_REG bit set. */
3212 install_operand (s[1], opP->reg - DATA);
3213 break;
3214
3215 case 'r':
3216 if (opP->mode == AINDR)
3217 install_operand (s[1], opP->reg - DATA);
3218 else
3219 install_operand (s[1], opP->index.reg - DATA);
3220 break;
3221
3222 case 's':
3223 if (opP->reg == FPI)
3224 tmpreg = 0x1;
3225 else if (opP->reg == FPS)
3226 tmpreg = 0x2;
3227 else if (opP->reg == FPC)
3228 tmpreg = 0x4;
3229 else
3230 abort ();
3231 install_operand (s[1], tmpreg);
3232 break;
3233
3234 case 'S': /* Ignore it. */
3235 break;
3236
3237 case 'T':
3238 install_operand (s[1], get_num (&opP->disp, 30));
3239 break;
3240
3241 case 'U': /* Ignore it. */
3242 break;
3243
3244 case 'c':
3245 switch (opP->reg)
3246 {
3247 case NC:
3248 tmpreg = 0;
3249 break;
3250 case DC:
3251 tmpreg = 1;
3252 break;
3253 case IC:
3254 tmpreg = 2;
3255 break;
3256 case BC:
3257 tmpreg = 3;
3258 break;
3259 default:
3260 as_fatal (_("failed sanity check"));
3261 } /* switch on cache token. */
3262 install_operand (s[1], tmpreg);
3263 break;
3264 #ifndef NO_68851
3265 /* JF: These are out of order, I fear. */
3266 case 'f':
3267 switch (opP->reg)
3268 {
3269 case SFC:
3270 tmpreg = 0;
3271 break;
3272 case DFC:
3273 tmpreg = 1;
3274 break;
3275 default:
3276 abort ();
3277 }
3278 install_operand (s[1], tmpreg);
3279 break;
3280
3281 case '0':
3282 case '1':
3283 case '2':
3284 switch (opP->reg)
3285 {
3286 case TC:
3287 tmpreg = 0;
3288 break;
3289 case CAL:
3290 tmpreg = 4;
3291 break;
3292 case VAL:
3293 tmpreg = 5;
3294 break;
3295 case SCC:
3296 tmpreg = 6;
3297 break;
3298 case AC:
3299 tmpreg = 7;
3300 break;
3301 default:
3302 abort ();
3303 }
3304 install_operand (s[1], tmpreg);
3305 break;
3306
3307 case 'V':
3308 if (opP->reg == VAL)
3309 break;
3310 abort ();
3311
3312 case 'W':
3313 switch (opP->reg)
3314 {
3315 case DRP:
3316 tmpreg = 1;
3317 break;
3318 case SRP:
3319 tmpreg = 2;
3320 break;
3321 case CRP:
3322 tmpreg = 3;
3323 break;
3324 default:
3325 abort ();
3326 }
3327 install_operand (s[1], tmpreg);
3328 break;
3329
3330 case 'X':
3331 switch (opP->reg)
3332 {
3333 case BAD:
3334 case BAD + 1:
3335 case BAD + 2:
3336 case BAD + 3:
3337 case BAD + 4:
3338 case BAD + 5:
3339 case BAD + 6:
3340 case BAD + 7:
3341 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3342 break;
3343
3344 case BAC:
3345 case BAC + 1:
3346 case BAC + 2:
3347 case BAC + 3:
3348 case BAC + 4:
3349 case BAC + 5:
3350 case BAC + 6:
3351 case BAC + 7:
3352 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3353 break;
3354
3355 default:
3356 abort ();
3357 }
3358 install_operand (s[1], tmpreg);
3359 break;
3360 case 'Y':
3361 know (opP->reg == PSR);
3362 break;
3363 case 'Z':
3364 know (opP->reg == PCSR);
3365 break;
3366 #endif /* m68851 */
3367 case '3':
3368 switch (opP->reg)
3369 {
3370 case TT0:
3371 tmpreg = 2;
3372 break;
3373 case TT1:
3374 tmpreg = 3;
3375 break;
3376 default:
3377 abort ();
3378 }
3379 install_operand (s[1], tmpreg);
3380 break;
3381 case 't':
3382 tmpreg = get_num (&opP->disp, 20);
3383 install_operand (s[1], tmpreg);
3384 break;
3385 case '_': /* used only for move16 absolute 32-bit address. */
3386 if (isvar (&opP->disp))
3387 add_fix ('l', &opP->disp, 0, 0);
3388 tmpreg = get_num (&opP->disp, 90);
3389 addword (tmpreg >> 16);
3390 addword (tmpreg & 0xFFFF);
3391 break;
3392 case 'u':
3393 install_operand (s[1], opP->reg - DATA0L);
3394 opP->reg -= (DATA0L);
3395 opP->reg &= 0x0F; /* remove upper/lower bit. */
3396 break;
3397 case 'x':
3398 tmpreg = get_num (&opP->disp, 80);
3399 if (tmpreg == -1)
3400 tmpreg = 0;
3401 install_operand (s[1], tmpreg);
3402 break;
3403 default:
3404 abort ();
3405 }
3406 }
3407
3408 /* By the time whe get here (FINALLY) the_ins contains the complete
3409 instruction, ready to be emitted. . . */
3410 }
3411
3412 static int
3413 reverse_16_bits (int in)
3414 {
3415 int out = 0;
3416 int n;
3417
3418 static int mask[16] =
3419 {
3420 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3421 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3422 };
3423 for (n = 0; n < 16; n++)
3424 {
3425 if (in & mask[n])
3426 out |= mask[15 - n];
3427 }
3428 return out;
3429 } /* reverse_16_bits() */
3430
3431 static int
3432 reverse_8_bits (int in)
3433 {
3434 int out = 0;
3435 int n;
3436
3437 static int mask[8] =
3438 {
3439 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3440 };
3441
3442 for (n = 0; n < 8; n++)
3443 {
3444 if (in & mask[n])
3445 out |= mask[7 - n];
3446 }
3447 return out;
3448 } /* reverse_8_bits() */
3449
3450 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3451 (that value is chosen in the frag_var call in md_assemble). TYPE
3452 is the subtype of the frag to be generated; its primary type is
3453 rs_machine_dependent.
3454
3455 The TYPE parameter is also used by md_convert_frag_1 and
3456 md_estimate_size_before_relax. The appropriate type of fixup will
3457 be emitted by md_convert_frag_1.
3458
3459 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3460 static void
3461 install_operand (int mode, int val)
3462 {
3463 switch (mode)
3464 {
3465 case 's':
3466 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3467 break;
3468 case 'd':
3469 the_ins.opcode[0] |= val << 9;
3470 break;
3471 case '1':
3472 the_ins.opcode[1] |= val << 12;
3473 break;
3474 case '2':
3475 the_ins.opcode[1] |= val << 6;
3476 break;
3477 case '3':
3478 the_ins.opcode[1] |= val;
3479 break;
3480 case '4':
3481 the_ins.opcode[2] |= val << 12;
3482 break;
3483 case '5':
3484 the_ins.opcode[2] |= val << 6;
3485 break;
3486 case '6':
3487 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3488 three words long! */
3489 the_ins.numo++;
3490 the_ins.opcode[2] |= val;
3491 break;
3492 case '7':
3493 the_ins.opcode[1] |= val << 7;
3494 break;
3495 case '8':
3496 the_ins.opcode[1] |= val << 10;
3497 break;
3498 #ifndef NO_68851
3499 case '9':
3500 the_ins.opcode[1] |= val << 5;
3501 break;
3502 #endif
3503
3504 case 't':
3505 the_ins.opcode[1] |= (val << 10) | (val << 7);
3506 break;
3507 case 'D':
3508 the_ins.opcode[1] |= (val << 12) | val;
3509 break;
3510 case 'g':
3511 the_ins.opcode[0] |= val = 0xff;
3512 break;
3513 case 'i':
3514 the_ins.opcode[0] |= val << 9;
3515 break;
3516 case 'C':
3517 the_ins.opcode[1] |= val;
3518 break;
3519 case 'j':
3520 the_ins.opcode[1] |= val;
3521 the_ins.numo++; /* What a hack. */
3522 break;
3523 case 'k':
3524 the_ins.opcode[1] |= val << 4;
3525 break;
3526 case 'b':
3527 case 'w':
3528 case 'W':
3529 case 'l':
3530 break;
3531 case 'e':
3532 the_ins.opcode[0] |= (val << 6);
3533 break;
3534 case 'L':
3535 the_ins.opcode[1] = (val >> 16);
3536 the_ins.opcode[2] = val & 0xffff;
3537 break;
3538 case 'm':
3539 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3540 the_ins.opcode[0] |= ((val & 0x7) << 9);
3541 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3542 break;
3543 case 'n': /* MAC/EMAC Rx on !load. */
3544 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3545 the_ins.opcode[0] |= ((val & 0x7) << 9);
3546 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3547 break;
3548 case 'o': /* MAC/EMAC Rx on load. */
3549 the_ins.opcode[1] |= val << 12;
3550 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3551 break;
3552 case 'M': /* MAC/EMAC Ry on !load. */
3553 the_ins.opcode[0] |= (val & 0xF);
3554 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3555 break;
3556 case 'N': /* MAC/EMAC Ry on load. */
3557 the_ins.opcode[1] |= (val & 0xF);
3558 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3559 break;
3560 case 'h':
3561 the_ins.opcode[1] |= ((val != 1) << 10);
3562 break;
3563 case 'F':
3564 the_ins.opcode[0] |= ((val & 0x3) << 9);
3565 break;
3566 case 'f':
3567 the_ins.opcode[0] |= ((val & 0x3) << 0);
3568 break;
3569 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3570 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3571 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3572 break;
3573 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3574 the_ins.opcode[0] |= ((val & 0x1) << 7);
3575 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3576 break;
3577 case 'I':
3578 the_ins.opcode[1] |= ((val & 0x3) << 9);
3579 break;
3580 case ']':
3581 the_ins.opcode[0] |= (val & 0x1) <<10;
3582 break;
3583 case 'c':
3584 default:
3585 as_fatal (_("failed sanity check."));
3586 }
3587 }
3588
3589 static void
3590 install_gen_operand (int mode, int val)
3591 {
3592 switch (mode)
3593 {
3594 case '/': /* Special for mask loads for mac/msac insns with
3595 possible mask; trailing_ampersend set in bit 8. */
3596 the_ins.opcode[0] |= (val & 0x3f);
3597 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3598 break;
3599 case 's':
3600 the_ins.opcode[0] |= val;
3601 break;
3602 case 'd':
3603 /* This is a kludge!!! */
3604 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3605 break;
3606 case 'b':
3607 case 'w':
3608 case 'l':
3609 case 'f':
3610 case 'F':
3611 case 'x':
3612 case 'p':
3613 the_ins.opcode[0] |= val;
3614 break;
3615 /* more stuff goes here. */
3616 default:
3617 as_fatal (_("failed sanity check."));
3618 }
3619 }
3620
3621 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3622 then deal with the bitfield hack. */
3623
3624 static char *
3625 crack_operand (char *str, struct m68k_op *opP)
3626 {
3627 register int parens;
3628 register int c;
3629 register char *beg_str;
3630 int inquote = 0;
3631
3632 if (!str)
3633 {
3634 return str;
3635 }
3636 beg_str = str;
3637 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3638 {
3639 if (! inquote)
3640 {
3641 if (*str == '(')
3642 parens++;
3643 else if (*str == ')')
3644 {
3645 if (!parens)
3646 { /* ERROR. */
3647 opP->error = _("Extra )");
3648 return str;
3649 }
3650 --parens;
3651 }
3652 }
3653 if (flag_mri && *str == '\'')
3654 inquote = ! inquote;
3655 }
3656 if (!*str && parens)
3657 { /* ERROR. */
3658 opP->error = _("Missing )");
3659 return str;
3660 }
3661 c = *str;
3662 *str = '\0';
3663 if (m68k_ip_op (beg_str, opP) != 0)
3664 {
3665 *str = c;
3666 return str;
3667 }
3668 *str = c;
3669 if (c == '}')
3670 c = *++str; /* JF bitfield hack. */
3671 if (c)
3672 {
3673 c = *++str;
3674 if (!c)
3675 as_bad (_("Missing operand"));
3676 }
3677
3678 /* Detect MRI REG symbols and convert them to REGLSTs. */
3679 if (opP->mode == CONTROL && (int)opP->reg < 0)
3680 {
3681 opP->mode = REGLST;
3682 opP->mask = ~(int)opP->reg;
3683 opP->reg = 0;
3684 }
3685
3686 return str;
3687 }
3688
3689 /* This is the guts of the machine-dependent assembler. STR points to a
3690 machine dependent instruction. This function is supposed to emit
3691 the frags/bytes it assembles to.
3692 */
3693
3694 static void
3695 insert_reg (const char *regname, int regnum)
3696 {
3697 char buf[100];
3698 int i;
3699
3700 #ifdef REGISTER_PREFIX
3701 if (!flag_reg_prefix_optional)
3702 {
3703 buf[0] = REGISTER_PREFIX;
3704 strcpy (buf + 1, regname);
3705 regname = buf;
3706 }
3707 #endif
3708
3709 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3710 &zero_address_frag));
3711
3712 for (i = 0; regname[i]; i++)
3713 buf[i] = TOUPPER (regname[i]);
3714 buf[i] = '\0';
3715
3716 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3717 &zero_address_frag));
3718 }
3719
3720 struct init_entry
3721 {
3722 const char *name;
3723 int number;
3724 };
3725
3726 static const struct init_entry init_table[] =
3727 {
3728 { "d0", DATA0 },
3729 { "d1", DATA1 },
3730 { "d2", DATA2 },
3731 { "d3", DATA3 },
3732 { "d4", DATA4 },
3733 { "d5", DATA5 },
3734 { "d6", DATA6 },
3735 { "d7", DATA7 },
3736 { "a0", ADDR0 },
3737 { "a1", ADDR1 },
3738 { "a2", ADDR2 },
3739 { "a3", ADDR3 },
3740 { "a4", ADDR4 },
3741 { "a5", ADDR5 },
3742 { "a6", ADDR6 },
3743 { "fp", ADDR6 },
3744 { "a7", ADDR7 },
3745 { "sp", ADDR7 },
3746 { "ssp", ADDR7 },
3747 { "fp0", FP0 },
3748 { "fp1", FP1 },
3749 { "fp2", FP2 },
3750 { "fp3", FP3 },
3751 { "fp4", FP4 },
3752 { "fp5", FP5 },
3753 { "fp6", FP6 },
3754 { "fp7", FP7 },
3755 { "fpi", FPI },
3756 { "fpiar", FPI },
3757 { "fpc", FPI },
3758 { "fps", FPS },
3759 { "fpsr", FPS },
3760 { "fpc", FPC },
3761 { "fpcr", FPC },
3762 { "control", FPC },
3763 { "status", FPS },
3764 { "iaddr", FPI },
3765
3766 { "cop0", COP0 },
3767 { "cop1", COP1 },
3768 { "cop2", COP2 },
3769 { "cop3", COP3 },
3770 { "cop4", COP4 },
3771 { "cop5", COP5 },
3772 { "cop6", COP6 },
3773 { "cop7", COP7 },
3774 { "pc", PC },
3775 { "zpc", ZPC },
3776 { "sr", SR },
3777
3778 { "ccr", CCR },
3779 { "cc", CCR },
3780
3781 { "acc", ACC },
3782 { "acc0", ACC },
3783 { "acc1", ACC1 },
3784 { "acc2", ACC2 },
3785 { "acc3", ACC3 },
3786 { "accext01", ACCEXT01 },
3787 { "accext23", ACCEXT23 },
3788 { "macsr", MACSR },
3789 { "mask", MASK },
3790
3791 /* Control registers. */
3792 { "sfc", SFC }, /* Source Function Code. */
3793 { "sfcr", SFC },
3794 { "dfc", DFC }, /* Destination Function Code. */
3795 { "dfcr", DFC },
3796 { "cacr", CACR }, /* Cache Control Register. */
3797 { "caar", CAAR }, /* Cache Address Register. */
3798
3799 { "usp", USP }, /* User Stack Pointer. */
3800 { "vbr", VBR }, /* Vector Base Register. */
3801 { "msp", MSP }, /* Master Stack Pointer. */
3802 { "isp", ISP }, /* Interrupt Stack Pointer. */
3803
3804 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3805 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3806 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3807 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3808
3809 /* 68ec040 versions of same */
3810 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3811 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3812 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3813 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3814
3815 /* Coldfire versions of same. The ColdFire programmer's reference
3816 manual indicated that the order is 2,3,0,1, but Ken Rose
3817 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3818 { "acr0", ACR0 }, /* Access Control Unit 0. */
3819 { "acr1", ACR1 }, /* Access Control Unit 1. */
3820 { "acr2", ACR2 }, /* Access Control Unit 2. */
3821 { "acr3", ACR3 }, /* Access Control Unit 3. */
3822
3823 { "tc", TC }, /* MMU Translation Control Register. */
3824 { "tcr", TC },
3825 { "asid", ASID },
3826
3827 { "mmusr", MMUSR }, /* MMU Status Register. */
3828 { "srp", SRP }, /* User Root Pointer. */
3829 { "urp", URP }, /* Supervisor Root Pointer. */
3830
3831 { "buscr", BUSCR },
3832 { "mmubar", MMUBAR },
3833 { "pcr", PCR },
3834
3835 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3836 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3837 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3838 { "mbar", MBAR }, /* Module Base Address Register. */
3839
3840 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3841 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3842 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3843 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3844 { "mpcr", MPCR }, /* mcfv4e registers. */
3845 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3846 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3847 { "asid", TC }, /* mcfv4e registers. */
3848 { "mmubar", BUSCR }, /* mcfv4e registers. */
3849 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3850 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3851 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3852 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3853 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3854 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3855 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3856 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3857 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3858 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3859 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3860 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3861
3862 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3863 { "rambar", RAMBAR }, /* mcf528x registers. */
3864
3865 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3866
3867 { "cac", CAC }, /* fido registers. */
3868 { "mbb", MBB }, /* fido registers. */
3869 /* End of control registers. */
3870
3871 { "ac", AC },
3872 { "bc", BC },
3873 { "cal", CAL },
3874 { "crp", CRP },
3875 { "drp", DRP },
3876 { "pcsr", PCSR },
3877 { "psr", PSR },
3878 { "scc", SCC },
3879 { "val", VAL },
3880 { "bad0", BAD0 },
3881 { "bad1", BAD1 },
3882 { "bad2", BAD2 },
3883 { "bad3", BAD3 },
3884 { "bad4", BAD4 },
3885 { "bad5", BAD5 },
3886 { "bad6", BAD6 },
3887 { "bad7", BAD7 },
3888 { "bac0", BAC0 },
3889 { "bac1", BAC1 },
3890 { "bac2", BAC2 },
3891 { "bac3", BAC3 },
3892 { "bac4", BAC4 },
3893 { "bac5", BAC5 },
3894 { "bac6", BAC6 },
3895 { "bac7", BAC7 },
3896
3897 { "ic", IC },
3898 { "dc", DC },
3899 { "nc", NC },
3900
3901 { "tt0", TT0 },
3902 { "tt1", TT1 },
3903 /* 68ec030 versions of same. */
3904 { "ac0", TT0 },
3905 { "ac1", TT1 },
3906 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3907 { "acusr", PSR },
3908
3909 /* Suppressed data and address registers. */
3910 { "zd0", ZDATA0 },
3911 { "zd1", ZDATA1 },
3912 { "zd2", ZDATA2 },
3913 { "zd3", ZDATA3 },
3914 { "zd4", ZDATA4 },
3915 { "zd5", ZDATA5 },
3916 { "zd6", ZDATA6 },
3917 { "zd7", ZDATA7 },
3918 { "za0", ZADDR0 },
3919 { "za1", ZADDR1 },
3920 { "za2", ZADDR2 },
3921 { "za3", ZADDR3 },
3922 { "za4", ZADDR4 },
3923 { "za5", ZADDR5 },
3924 { "za6", ZADDR6 },
3925 { "za7", ZADDR7 },
3926
3927 /* Upper and lower data and address registers, used by macw and msacw. */
3928 { "d0l", DATA0L },
3929 { "d1l", DATA1L },
3930 { "d2l", DATA2L },
3931 { "d3l", DATA3L },
3932 { "d4l", DATA4L },
3933 { "d5l", DATA5L },
3934 { "d6l", DATA6L },
3935 { "d7l", DATA7L },
3936
3937 { "a0l", ADDR0L },
3938 { "a1l", ADDR1L },
3939 { "a2l", ADDR2L },
3940 { "a3l", ADDR3L },
3941 { "a4l", ADDR4L },
3942 { "a5l", ADDR5L },
3943 { "a6l", ADDR6L },
3944 { "a7l", ADDR7L },
3945
3946 { "d0u", DATA0U },
3947 { "d1u", DATA1U },
3948 { "d2u", DATA2U },
3949 { "d3u", DATA3U },
3950 { "d4u", DATA4U },
3951 { "d5u", DATA5U },
3952 { "d6u", DATA6U },
3953 { "d7u", DATA7U },
3954
3955 { "a0u", ADDR0U },
3956 { "a1u", ADDR1U },
3957 { "a2u", ADDR2U },
3958 { "a3u", ADDR3U },
3959 { "a4u", ADDR4U },
3960 { "a5u", ADDR5U },
3961 { "a6u", ADDR6U },
3962 { "a7u", ADDR7U },
3963
3964 { 0, 0 }
3965 };
3966
3967 static void
3968 init_regtable (void)
3969 {
3970 int i;
3971 for (i = 0; init_table[i].name; i++)
3972 insert_reg (init_table[i].name, init_table[i].number);
3973 }
3974
3975 void
3976 md_assemble (char *str)
3977 {
3978 const char *er;
3979 short *fromP;
3980 char *toP = NULL;
3981 int m, n = 0;
3982 char *to_beg_P;
3983 int shorts_this_frag;
3984 fixS *fixP;
3985
3986 if (!selected_cpu && !selected_arch)
3987 {
3988 /* We've not selected an architecture yet. Set the default
3989 now. We do this lazily so that an initial .cpu or .arch directive
3990 can specify. */
3991 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3992 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3993 }
3994 if (!initialized)
3995 m68k_init_arch ();
3996
3997 /* In MRI mode, the instruction and operands are separated by a
3998 space. Anything following the operands is a comment. The label
3999 has already been removed. */
4000 if (flag_mri)
4001 {
4002 char *s;
4003 int fields = 0;
4004 int infield = 0;
4005 int inquote = 0;
4006
4007 for (s = str; *s != '\0'; s++)
4008 {
4009 if ((*s == ' ' || *s == '\t') && ! inquote)
4010 {
4011 if (infield)
4012 {
4013 ++fields;
4014 if (fields >= 2)
4015 {
4016 *s = '\0';
4017 break;
4018 }
4019 infield = 0;
4020 }
4021 }
4022 else
4023 {
4024 if (! infield)
4025 infield = 1;
4026 if (*s == '\'')
4027 inquote = ! inquote;
4028 }
4029 }
4030 }
4031
4032 memset (&the_ins, '\0', sizeof (the_ins));
4033 m68k_ip (str);
4034 er = the_ins.error;
4035 if (!er)
4036 {
4037 for (n = 0; n < the_ins.numargs; n++)
4038 if (the_ins.operands[n].error)
4039 {
4040 er = the_ins.operands[n].error;
4041 break;
4042 }
4043 }
4044 if (er)
4045 {
4046 as_bad (_("%s -- statement `%s' ignored"), er, str);
4047 return;
4048 }
4049
4050 /* If there is a current label, record that it marks an instruction. */
4051 if (current_label != NULL)
4052 {
4053 current_label->text = 1;
4054 current_label = NULL;
4055 }
4056
4057 #ifdef OBJ_ELF
4058 /* Tie dwarf2 debug info to the address at the start of the insn. */
4059 dwarf2_emit_insn (0);
4060 #endif
4061
4062 if (the_ins.nfrag == 0)
4063 {
4064 /* No frag hacking involved; just put it out. */
4065 toP = frag_more (2 * the_ins.numo);
4066 fromP = &the_ins.opcode[0];
4067 for (m = the_ins.numo; m; --m)
4068 {
4069 md_number_to_chars (toP, (long) (*fromP), 2);
4070 toP += 2;
4071 fromP++;
4072 }
4073 /* Put out symbol-dependent info. */
4074 for (m = 0; m < the_ins.nrel; m++)
4075 {
4076 switch (the_ins.reloc[m].wid)
4077 {
4078 case 'B':
4079 n = 1;
4080 break;
4081 case 'b':
4082 n = 1;
4083 break;
4084 case '3':
4085 n = 1;
4086 break;
4087 case 'w':
4088 case 'W':
4089 n = 2;
4090 break;
4091 case 'l':
4092 n = 4;
4093 break;
4094 default:
4095 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4096 the_ins.reloc[m].wid);
4097 }
4098
4099 fixP = fix_new_exp (frag_now,
4100 ((toP - frag_now->fr_literal)
4101 - the_ins.numo * 2 + the_ins.reloc[m].n),
4102 n,
4103 &the_ins.reloc[m].exp,
4104 the_ins.reloc[m].pcrel,
4105 get_reloc_code (n, the_ins.reloc[m].pcrel,
4106 the_ins.reloc[m].pic_reloc));
4107 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4108 if (the_ins.reloc[m].wid == 'B')
4109 fixP->fx_signed = 1;
4110 }
4111 return;
4112 }
4113
4114 /* There's some frag hacking. */
4115 {
4116 /* Calculate the max frag size. */
4117 int wid;
4118
4119 wid = 2 * the_ins.fragb[0].fragoff;
4120 for (n = 1; n < the_ins.nfrag; n++)
4121 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4122 /* frag_var part. */
4123 wid += 10;
4124 /* Make sure the whole insn fits in one chunk, in particular that
4125 the var part is attached, as we access one byte before the
4126 variable frag for byte branches. */
4127 frag_grow (wid);
4128 }
4129
4130 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4131 {
4132 int wid;
4133
4134 if (n == 0)
4135 wid = 2 * the_ins.fragb[n].fragoff;
4136 else
4137 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4138 toP = frag_more (wid);
4139 to_beg_P = toP;
4140 shorts_this_frag = 0;
4141 for (m = wid / 2; m; --m)
4142 {
4143 md_number_to_chars (toP, (long) (*fromP), 2);
4144 toP += 2;
4145 fromP++;
4146 shorts_this_frag++;
4147 }
4148 for (m = 0; m < the_ins.nrel; m++)
4149 {
4150 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4151 {
4152 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4153 break;
4154 }
4155 wid = the_ins.reloc[m].wid;
4156 if (wid == 0)
4157 continue;
4158 the_ins.reloc[m].wid = 0;
4159 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4160
4161 fixP = fix_new_exp (frag_now,
4162 ((toP - frag_now->fr_literal)
4163 - the_ins.numo * 2 + the_ins.reloc[m].n),
4164 wid,
4165 &the_ins.reloc[m].exp,
4166 the_ins.reloc[m].pcrel,
4167 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4168 the_ins.reloc[m].pic_reloc));
4169 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4170 }
4171 (void) frag_var (rs_machine_dependent, 10, 0,
4172 (relax_substateT) (the_ins.fragb[n].fragty),
4173 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4174 }
4175 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4176 shorts_this_frag = 0;
4177 if (n)
4178 {
4179 toP = frag_more (n * 2);
4180 while (n--)
4181 {
4182 md_number_to_chars (toP, (long) (*fromP), 2);
4183 toP += 2;
4184 fromP++;
4185 shorts_this_frag++;
4186 }
4187 }
4188 for (m = 0; m < the_ins.nrel; m++)
4189 {
4190 int wid;
4191
4192 wid = the_ins.reloc[m].wid;
4193 if (wid == 0)
4194 continue;
4195 the_ins.reloc[m].wid = 0;
4196 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4197
4198 fixP = fix_new_exp (frag_now,
4199 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4200 - shorts_this_frag * 2),
4201 wid,
4202 &the_ins.reloc[m].exp,
4203 the_ins.reloc[m].pcrel,
4204 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4205 the_ins.reloc[m].pic_reloc));
4206 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4207 }
4208 }
4209
4210 /* Comparison function used by qsort to rank the opcode entries by name. */
4211
4212 static int
4213 m68k_compare_opcode (const void * v1, const void * v2)
4214 {
4215 struct m68k_opcode * op1, * op2;
4216 int ret;
4217
4218 if (v1 == v2)
4219 return 0;
4220
4221 op1 = *(struct m68k_opcode **) v1;
4222 op2 = *(struct m68k_opcode **) v2;
4223
4224 /* Compare the two names. If different, return the comparison.
4225 If the same, return the order they are in the opcode table. */
4226 ret = strcmp (op1->name, op2->name);
4227 if (ret)
4228 return ret;
4229 if (op1 < op2)
4230 return -1;
4231 return 1;
4232 }
4233
4234 void
4235 md_begin (void)
4236 {
4237 const struct m68k_opcode *ins;
4238 struct m68k_incant *hack, *slak;
4239 const char *retval = 0; /* Empty string, or error msg text. */
4240 int i;
4241
4242 /* Set up hash tables with 68000 instructions.
4243 similar to what the vax assembler does. */
4244 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4245 a copy of it at runtime, adding in the information we want but isn't
4246 there. I think it'd be better to have an awk script hack the table
4247 at compile time. Or even just xstr the table and use it as-is. But
4248 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4249 names. */
4250
4251 if (flag_mri)
4252 {
4253 flag_reg_prefix_optional = 1;
4254 m68k_abspcadd = 1;
4255 if (! m68k_rel32_from_cmdline)
4256 m68k_rel32 = 0;
4257 }
4258
4259 /* First sort the opcode table into alphabetical order to seperate
4260 the order that the assembler wants to see the opcodes from the
4261 order that the disassembler wants to see them. */
4262 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4263 if (!m68k_sorted_opcodes)
4264 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4265 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4266
4267 for (i = m68k_numopcodes; i--;)
4268 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4269
4270 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4271 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4272
4273 op_hash = hash_new ();
4274
4275 obstack_begin (&robyn, 4000);
4276 for (i = 0; i < m68k_numopcodes; i++)
4277 {
4278 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4279 do
4280 {
4281 ins = m68k_sorted_opcodes[i];
4282
4283 /* We *could* ignore insns that don't match our
4284 arch here by just leaving them out of the hash. */
4285 slak->m_operands = ins->args;
4286 slak->m_opnum = strlen (slak->m_operands) / 2;
4287 slak->m_arch = ins->arch;
4288 slak->m_opcode = ins->opcode;
4289 /* This is kludgey. */
4290 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4291 if (i + 1 != m68k_numopcodes
4292 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4293 {
4294 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4295 i++;
4296 }
4297 else
4298 slak->m_next = 0;
4299 slak = slak->m_next;
4300 }
4301 while (slak);
4302
4303 retval = hash_insert (op_hash, ins->name, (char *) hack);
4304 if (retval)
4305 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4306 }
4307
4308 for (i = 0; i < m68k_numaliases; i++)
4309 {
4310 const char *name = m68k_opcode_aliases[i].primary;
4311 const char *alias = m68k_opcode_aliases[i].alias;
4312 PTR val = hash_find (op_hash, name);
4313
4314 if (!val)
4315 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4316 retval = hash_insert (op_hash, alias, val);
4317 if (retval)
4318 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4319 }
4320
4321 /* In MRI mode, all unsized branches are variable sized. Normally,
4322 they are word sized. */
4323 if (flag_mri)
4324 {
4325 static struct m68k_opcode_alias mri_aliases[] =
4326 {
4327 { "bhi", "jhi", },
4328 { "bls", "jls", },
4329 { "bcc", "jcc", },
4330 { "bcs", "jcs", },
4331 { "bne", "jne", },
4332 { "beq", "jeq", },
4333 { "bvc", "jvc", },
4334 { "bvs", "jvs", },
4335 { "bpl", "jpl", },
4336 { "bmi", "jmi", },
4337 { "bge", "jge", },
4338 { "blt", "jlt", },
4339 { "bgt", "jgt", },
4340 { "ble", "jle", },
4341 { "bra", "jra", },
4342 { "bsr", "jbsr", },
4343 };
4344
4345 for (i = 0;
4346 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4347 i++)
4348 {
4349 const char *name = mri_aliases[i].primary;
4350 const char *alias = mri_aliases[i].alias;
4351 PTR val = hash_find (op_hash, name);
4352
4353 if (!val)
4354 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4355 retval = hash_jam (op_hash, alias, val);
4356 if (retval)
4357 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4358 }
4359 }
4360
4361 for (i = 0; i < (int) sizeof (notend_table); i++)
4362 {
4363 notend_table[i] = 0;
4364 alt_notend_table[i] = 0;
4365 }
4366
4367 notend_table[','] = 1;
4368 notend_table['{'] = 1;
4369 notend_table['}'] = 1;
4370 alt_notend_table['a'] = 1;
4371 alt_notend_table['A'] = 1;
4372 alt_notend_table['d'] = 1;
4373 alt_notend_table['D'] = 1;
4374 alt_notend_table['#'] = 1;
4375 alt_notend_table['&'] = 1;
4376 alt_notend_table['f'] = 1;
4377 alt_notend_table['F'] = 1;
4378 #ifdef REGISTER_PREFIX
4379 alt_notend_table[REGISTER_PREFIX] = 1;
4380 #endif
4381
4382 /* We need to put '(' in alt_notend_table to handle
4383 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4384 alt_notend_table['('] = 1;
4385
4386 /* We need to put '@' in alt_notend_table to handle
4387 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4388 alt_notend_table['@'] = 1;
4389
4390 /* We need to put digits in alt_notend_table to handle
4391 bfextu %d0{24:1},%d0 */
4392 alt_notend_table['0'] = 1;
4393 alt_notend_table['1'] = 1;
4394 alt_notend_table['2'] = 1;
4395 alt_notend_table['3'] = 1;
4396 alt_notend_table['4'] = 1;
4397 alt_notend_table['5'] = 1;
4398 alt_notend_table['6'] = 1;
4399 alt_notend_table['7'] = 1;
4400 alt_notend_table['8'] = 1;
4401 alt_notend_table['9'] = 1;
4402
4403 #ifndef MIT_SYNTAX_ONLY
4404 /* Insert pseudo ops, these have to go into the opcode table since
4405 gas expects pseudo ops to start with a dot. */
4406 {
4407 int n = 0;
4408
4409 while (mote_pseudo_table[n].poc_name)
4410 {
4411 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4412 hash_insert (op_hash,
4413 mote_pseudo_table[n].poc_name, (char *) hack);
4414 hack->m_operands = 0;
4415 hack->m_opnum = n;
4416 n++;
4417 }
4418 }
4419 #endif
4420
4421 init_regtable ();
4422
4423 #ifdef OBJ_ELF
4424 record_alignment (text_section, 2);
4425 record_alignment (data_section, 2);
4426 record_alignment (bss_section, 2);
4427 #endif
4428 }
4429
4430 \f
4431 /* This is called when a label is defined. */
4432
4433 void
4434 m68k_frob_label (symbolS *sym)
4435 {
4436 struct label_line *n;
4437
4438 n = (struct label_line *) xmalloc (sizeof *n);
4439 n->next = labels;
4440 n->label = sym;
4441 as_where (&n->file, &n->line);
4442 n->text = 0;
4443 labels = n;
4444 current_label = n;
4445
4446 #ifdef OBJ_ELF
4447 dwarf2_emit_label (sym);
4448 #endif
4449 }
4450
4451 /* This is called when a value that is not an instruction is emitted. */
4452
4453 void
4454 m68k_flush_pending_output (void)
4455 {
4456 current_label = NULL;
4457 }
4458
4459 /* This is called at the end of the assembly, when the final value of
4460 the label is known. We warn if this is a text symbol aligned at an
4461 odd location. */
4462
4463 void
4464 m68k_frob_symbol (symbolS *sym)
4465 {
4466 if (S_GET_SEGMENT (sym) == reg_section
4467 && (int) S_GET_VALUE (sym) < 0)
4468 {
4469 S_SET_SEGMENT (sym, absolute_section);
4470 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4471 }
4472 else if ((S_GET_VALUE (sym) & 1) != 0)
4473 {
4474 struct label_line *l;
4475
4476 for (l = labels; l != NULL; l = l->next)
4477 {
4478 if (l->label == sym)
4479 {
4480 if (l->text)
4481 as_warn_where (l->file, l->line,
4482 _("text label `%s' aligned to odd boundary"),
4483 S_GET_NAME (sym));
4484 break;
4485 }
4486 }
4487 }
4488 }
4489 \f
4490 /* This is called if we go in or out of MRI mode because of the .mri
4491 pseudo-op. */
4492
4493 void
4494 m68k_mri_mode_change (int on)
4495 {
4496 if (on)
4497 {
4498 if (! flag_reg_prefix_optional)
4499 {
4500 flag_reg_prefix_optional = 1;
4501 #ifdef REGISTER_PREFIX
4502 init_regtable ();
4503 #endif
4504 }
4505 m68k_abspcadd = 1;
4506 if (! m68k_rel32_from_cmdline)
4507 m68k_rel32 = 0;
4508 }
4509 else
4510 {
4511 if (! reg_prefix_optional_seen)
4512 {
4513 #ifdef REGISTER_PREFIX_OPTIONAL
4514 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4515 #else
4516 flag_reg_prefix_optional = 0;
4517 #endif
4518 #ifdef REGISTER_PREFIX
4519 init_regtable ();
4520 #endif
4521 }
4522 m68k_abspcadd = 0;
4523 if (! m68k_rel32_from_cmdline)
4524 m68k_rel32 = 1;
4525 }
4526 }
4527
4528 /* Equal to MAX_PRECISION in atof-ieee.c. */
4529 #define MAX_LITTLENUMS 6
4530
4531 /* Turn a string in input_line_pointer into a floating point constant
4532 of type TYPE, and store the appropriate bytes in *LITP. The number
4533 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4534 returned, or NULL on OK. */
4535
4536 char *
4537 md_atof (int type, char *litP, int *sizeP)
4538 {
4539 int prec;
4540 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4541 LITTLENUM_TYPE *wordP;
4542 char *t;
4543
4544 switch (type)
4545 {
4546 case 'f':
4547 case 'F':
4548 case 's':
4549 case 'S':
4550 prec = 2;
4551 break;
4552
4553 case 'd':
4554 case 'D':
4555 case 'r':
4556 case 'R':
4557 prec = 4;
4558 break;
4559
4560 case 'x':
4561 case 'X':
4562 prec = 6;
4563 break;
4564
4565 case 'p':
4566 case 'P':
4567 prec = 6;
4568 break;
4569
4570 default:
4571 *sizeP = 0;
4572 return _("Bad call to MD_ATOF()");
4573 }
4574 t = atof_ieee (input_line_pointer, type, words);
4575 if (t)
4576 input_line_pointer = t;
4577
4578 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4579 for (wordP = words; prec--;)
4580 {
4581 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4582 litP += sizeof (LITTLENUM_TYPE);
4583 }
4584 return 0;
4585 }
4586
4587 void
4588 md_number_to_chars (char *buf, valueT val, int n)
4589 {
4590 number_to_chars_bigendian (buf, val, n);
4591 }
4592
4593 void
4594 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4595 {
4596 offsetT val = *valP;
4597 addressT upper_limit;
4598 offsetT lower_limit;
4599
4600 /* This is unnecessary but it convinces the native rs6000 compiler
4601 to generate the code we want. */
4602 char *buf = fixP->fx_frag->fr_literal;
4603 buf += fixP->fx_where;
4604 /* End ibm compiler workaround. */
4605
4606 val = SEXT (val);
4607
4608 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4609 fixP->fx_done = 1;
4610
4611 #ifdef OBJ_ELF
4612 if (fixP->fx_addsy)
4613 {
4614 memset (buf, 0, fixP->fx_size);
4615 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4616
4617 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4618 && !S_IS_DEFINED (fixP->fx_addsy)
4619 && !S_IS_WEAK (fixP->fx_addsy))
4620 S_SET_WEAK (fixP->fx_addsy);
4621 return;
4622 }
4623 #endif
4624
4625 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4626 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4627 return;
4628
4629 switch (fixP->fx_size)
4630 {
4631 /* The cast to offsetT below are necessary to make code
4632 correct for machines where ints are smaller than offsetT. */
4633 case 1:
4634 *buf++ = val;
4635 upper_limit = 0x7f;
4636 lower_limit = - (offsetT) 0x80;
4637 break;
4638 case 2:
4639 *buf++ = (val >> 8);
4640 *buf++ = val;
4641 upper_limit = 0x7fff;
4642 lower_limit = - (offsetT) 0x8000;
4643 break;
4644 case 4:
4645 *buf++ = (val >> 24);
4646 *buf++ = (val >> 16);
4647 *buf++ = (val >> 8);
4648 *buf++ = val;
4649 upper_limit = 0x7fffffff;
4650 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4651 break;
4652 default:
4653 BAD_CASE (fixP->fx_size);
4654 }
4655
4656 /* Fix up a negative reloc. */
4657 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4658 {
4659 fixP->fx_addsy = fixP->fx_subsy;
4660 fixP->fx_subsy = NULL;
4661 fixP->fx_tcbit = 1;
4662 }
4663
4664 /* For non-pc-relative values, it's conceivable we might get something
4665 like "0xff" for a byte field. So extend the upper part of the range
4666 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4667 so that we can do any range checking at all. */
4668 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4669 upper_limit = upper_limit * 2 + 1;
4670
4671 if ((addressT) val > upper_limit
4672 && (val > 0 || val < lower_limit))
4673 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4674
4675 /* A one byte PC-relative reloc means a short branch. We can't use
4676 a short branch with a value of 0 or -1, because those indicate
4677 different opcodes (branches with longer offsets). fixup_segment
4678 in write.c may have clobbered fx_pcrel, so we need to examine the
4679 reloc type. */
4680 if ((fixP->fx_pcrel
4681 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4682 && fixP->fx_size == 1
4683 && (fixP->fx_addsy == NULL
4684 || S_IS_DEFINED (fixP->fx_addsy))
4685 && (val == 0 || val == -1))
4686 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4687 }
4688
4689 /* *fragP has been relaxed to its final size, and now needs to have
4690 the bytes inside it modified to conform to the new size There is UGLY
4691 MAGIC here. ..
4692 */
4693 static void
4694 md_convert_frag_1 (fragS *fragP)
4695 {
4696 long disp;
4697 fixS *fixP;
4698
4699 /* Address in object code of the displacement. */
4700 register int object_address = fragP->fr_fix + fragP->fr_address;
4701
4702 /* Address in gas core of the place to store the displacement. */
4703 /* This convinces the native rs6000 compiler to generate the code we
4704 want. */
4705 register char *buffer_address = fragP->fr_literal;
4706 buffer_address += fragP->fr_fix;
4707 /* End ibm compiler workaround. */
4708
4709 /* The displacement of the address, from current location. */
4710 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4711 disp = (disp + fragP->fr_offset) - object_address;
4712
4713 switch (fragP->fr_subtype)
4714 {
4715 case TAB (BRANCHBWL, BYTE):
4716 case TAB (BRABSJUNC, BYTE):
4717 case TAB (BRABSJCOND, BYTE):
4718 case TAB (BRANCHBW, BYTE):
4719 know (issbyte (disp));
4720 if (disp == 0)
4721 as_bad_where (fragP->fr_file, fragP->fr_line,
4722 _("short branch with zero offset: use :w"));
4723 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4724 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4725 fixP->fx_pcrel_adjust = -1;
4726 break;
4727 case TAB (BRANCHBWL, SHORT):
4728 case TAB (BRABSJUNC, SHORT):
4729 case TAB (BRABSJCOND, SHORT):
4730 case TAB (BRANCHBW, SHORT):
4731 fragP->fr_opcode[1] = 0x00;
4732 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4733 1, RELAX_RELOC_PC16);
4734 fragP->fr_fix += 2;
4735 break;
4736 case TAB (BRANCHBWL, LONG):
4737 fragP->fr_opcode[1] = (char) 0xFF;
4738 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4739 1, RELAX_RELOC_PC32);
4740 fragP->fr_fix += 4;
4741 break;
4742 case TAB (BRABSJUNC, LONG):
4743 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4744 {
4745 if (flag_keep_pcrel)
4746 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4747 fragP->fr_opcode[0] = 0x4E;
4748 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4749 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4750 0, RELAX_RELOC_ABS32);
4751 fragP->fr_fix += 4;
4752 }
4753 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4754 {
4755 if (flag_keep_pcrel)
4756 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4757 fragP->fr_opcode[0] = 0x4E;
4758 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4759 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4760 0, RELAX_RELOC_ABS32);
4761 fragP->fr_fix += 4;
4762 }
4763 else
4764 {
4765 /* This cannot happen, because jbsr and jbra are the only two
4766 unconditional branches. */
4767 abort ();
4768 }
4769 break;
4770 case TAB (BRABSJCOND, LONG):
4771 if (flag_keep_pcrel)
4772 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4773
4774 /* Only Bcc 68000 instructions can come here
4775 Change bcc into b!cc/jmp absl long. */
4776 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4777 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4778
4779 /* JF: these used to be fr_opcode[2,3], but they may be in a
4780 different frag, in which case referring to them is a no-no.
4781 Only fr_opcode[0,1] are guaranteed to work. */
4782 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4783 *buffer_address++ = (char) 0xf9;
4784 fragP->fr_fix += 2; /* Account for jmp instruction. */
4785 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4786 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4787 fragP->fr_fix += 4;
4788 break;
4789 case TAB (FBRANCH, SHORT):
4790 know ((fragP->fr_opcode[1] & 0x40) == 0);
4791 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4792 1, RELAX_RELOC_PC16);
4793 fragP->fr_fix += 2;
4794 break;
4795 case TAB (FBRANCH, LONG):
4796 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4797 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4798 1, RELAX_RELOC_PC32);
4799 fragP->fr_fix += 4;
4800 break;
4801 case TAB (DBCCLBR, SHORT):
4802 case TAB (DBCCABSJ, SHORT):
4803 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4804 1, RELAX_RELOC_PC16);
4805 fragP->fr_fix += 2;
4806 break;
4807 case TAB (DBCCLBR, LONG):
4808 /* Only DBcc instructions can come here.
4809 Change dbcc into dbcc/bral.
4810 JF: these used to be fr_opcode[2-7], but that's wrong. */
4811 if (flag_keep_pcrel)
4812 as_fatal (_("Tried to convert DBcc to absolute jump"));
4813
4814 *buffer_address++ = 0x00; /* Branch offset = 4. */
4815 *buffer_address++ = 0x04;
4816 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4817 *buffer_address++ = 0x06;
4818 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4819 *buffer_address++ = (char) 0xff;
4820
4821 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4822 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4823 RELAX_RELOC_PC32);
4824 fragP->fr_fix += 4;
4825 break;
4826 case TAB (DBCCABSJ, LONG):
4827 /* Only DBcc instructions can come here.
4828 Change dbcc into dbcc/jmp.
4829 JF: these used to be fr_opcode[2-7], but that's wrong. */
4830 if (flag_keep_pcrel)
4831 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4832
4833 *buffer_address++ = 0x00; /* Branch offset = 4. */
4834 *buffer_address++ = 0x04;
4835 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4836 *buffer_address++ = 0x06;
4837 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4838 *buffer_address++ = (char) 0xf9;
4839
4840 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4841 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4842 RELAX_RELOC_ABS32);
4843 fragP->fr_fix += 4;
4844 break;
4845 case TAB (PCREL1632, SHORT):
4846 fragP->fr_opcode[1] &= ~0x3F;
4847 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4848 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4849 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4850 fragP->fr_fix += 2;
4851 break;
4852 case TAB (PCREL1632, LONG):
4853 /* Already set to mode 7.3; this indicates: PC indirect with
4854 suppressed index, 32-bit displacement. */
4855 *buffer_address++ = 0x01;
4856 *buffer_address++ = 0x70;
4857 fragP->fr_fix += 2;
4858 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4859 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4860 fixP->fx_pcrel_adjust = 2;
4861 fragP->fr_fix += 4;
4862 break;
4863 case TAB (PCINDEX, BYTE):
4864 assert (fragP->fr_fix >= 2);
4865 buffer_address[-2] &= ~1;
4866 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4867 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4868 fixP->fx_pcrel_adjust = 1;
4869 break;
4870 case TAB (PCINDEX, SHORT):
4871 assert (fragP->fr_fix >= 2);
4872 buffer_address[-2] |= 0x1;
4873 buffer_address[-1] = 0x20;
4874 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4875 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4876 fixP->fx_pcrel_adjust = 2;
4877 fragP->fr_fix += 2;
4878 break;
4879 case TAB (PCINDEX, LONG):
4880 assert (fragP->fr_fix >= 2);
4881 buffer_address[-2] |= 0x1;
4882 buffer_address[-1] = 0x30;
4883 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4884 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4885 fixP->fx_pcrel_adjust = 2;
4886 fragP->fr_fix += 4;
4887 break;
4888 case TAB (ABSTOPCREL, SHORT):
4889 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4890 1, RELAX_RELOC_PC16);
4891 fragP->fr_fix += 2;
4892 break;
4893 case TAB (ABSTOPCREL, LONG):
4894 if (flag_keep_pcrel)
4895 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4896 /* The thing to do here is force it to ABSOLUTE LONG, since
4897 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4898 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4899 abort ();
4900 fragP->fr_opcode[1] &= ~0x3F;
4901 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4902 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4903 0, RELAX_RELOC_ABS32);
4904 fragP->fr_fix += 4;
4905 break;
4906 }
4907 }
4908
4909 void
4910 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4911 segT sec ATTRIBUTE_UNUSED,
4912 fragS *fragP)
4913 {
4914 md_convert_frag_1 (fragP);
4915 }
4916
4917 /* Force truly undefined symbols to their maximum size, and generally set up
4918 the frag list to be relaxed
4919 */
4920 int
4921 md_estimate_size_before_relax (fragS *fragP, segT segment)
4922 {
4923 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4924 switch (fragP->fr_subtype)
4925 {
4926 case TAB (BRANCHBWL, SZ_UNDEF):
4927 case TAB (BRABSJUNC, SZ_UNDEF):
4928 case TAB (BRABSJCOND, SZ_UNDEF):
4929 {
4930 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4931 && relaxable_symbol (fragP->fr_symbol))
4932 {
4933 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4934 }
4935 else if (flag_short_refs)
4936 {
4937 /* Symbol is undefined and we want short ref. */
4938 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4939 }
4940 else
4941 {
4942 /* Symbol is still undefined. Make it LONG. */
4943 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4944 }
4945 break;
4946 }
4947
4948 case TAB (BRANCHBW, SZ_UNDEF):
4949 {
4950 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4951 && relaxable_symbol (fragP->fr_symbol))
4952 {
4953 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4954 }
4955 else
4956 {
4957 /* Symbol is undefined and we don't have long branches. */
4958 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4959 }
4960 break;
4961 }
4962
4963 case TAB (FBRANCH, SZ_UNDEF):
4964 case TAB (DBCCLBR, SZ_UNDEF):
4965 case TAB (DBCCABSJ, SZ_UNDEF):
4966 case TAB (PCREL1632, SZ_UNDEF):
4967 {
4968 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4969 && relaxable_symbol (fragP->fr_symbol))
4970 || flag_short_refs)
4971 {
4972 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4973 }
4974 else
4975 {
4976 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4977 }
4978 break;
4979 }
4980
4981 case TAB (PCINDEX, SZ_UNDEF):
4982 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4983 && relaxable_symbol (fragP->fr_symbol)))
4984 {
4985 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4986 }
4987 else
4988 {
4989 fragP->fr_subtype = TAB (PCINDEX, LONG);
4990 }
4991 break;
4992
4993 case TAB (ABSTOPCREL, SZ_UNDEF):
4994 {
4995 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4996 && relaxable_symbol (fragP->fr_symbol)))
4997 {
4998 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4999 }
5000 else
5001 {
5002 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5003 }
5004 break;
5005 }
5006
5007 default:
5008 break;
5009 }
5010
5011 /* Now that SZ_UNDEF are taken care of, check others. */
5012 switch (fragP->fr_subtype)
5013 {
5014 case TAB (BRANCHBWL, BYTE):
5015 case TAB (BRABSJUNC, BYTE):
5016 case TAB (BRABSJCOND, BYTE):
5017 case TAB (BRANCHBW, BYTE):
5018 /* We can't do a short jump to the next instruction, so in that
5019 case we force word mode. If the symbol is at the start of a
5020 frag, and it is the next frag with any data in it (usually
5021 this is just the next frag, but assembler listings may
5022 introduce empty frags), we must use word mode. */
5023 if (fragP->fr_symbol)
5024 {
5025 fragS *sym_frag;
5026
5027 sym_frag = symbol_get_frag (fragP->fr_symbol);
5028 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5029 {
5030 fragS *l;
5031
5032 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5033 if (l->fr_fix != 0)
5034 break;
5035 if (l == sym_frag)
5036 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5037 }
5038 }
5039 break;
5040 default:
5041 break;
5042 }
5043 return md_relax_table[fragP->fr_subtype].rlx_length;
5044 }
5045
5046 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5047 /* the bit-field entries in the relocation_info struct plays hell
5048 with the byte-order problems of cross-assembly. So as a hack,
5049 I added this mach. dependent ri twiddler. Ugly, but it gets
5050 you there. -KWK */
5051 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5052 are symbolnum, most sig. byte first. Last byte is broken up with
5053 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5054 nibble as nuthin. (on Sun 3 at least) */
5055 /* Translate the internal relocation information into target-specific
5056 format. */
5057 #ifdef comment
5058 void
5059 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5060 {
5061 /* This is easy. */
5062 md_number_to_chars (the_bytes, ri->r_address, 4);
5063 /* Now the fun stuff. */
5064 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5065 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5066 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5067 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5068 | ((ri->r_length << 5) & 0x60)
5069 | ((ri->r_extern << 4) & 0x10));
5070 }
5071
5072 #endif
5073
5074 #endif /* OBJ_AOUT or OBJ_BOUT */
5075
5076 #ifndef WORKING_DOT_WORD
5077 int md_short_jump_size = 4;
5078 int md_long_jump_size = 6;
5079
5080 void
5081 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5082 fragS *frag ATTRIBUTE_UNUSED,
5083 symbolS *to_symbol ATTRIBUTE_UNUSED)
5084 {
5085 valueT offset;
5086
5087 offset = to_addr - (from_addr + 2);
5088
5089 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5090 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5091 }
5092
5093 void
5094 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5095 fragS *frag, symbolS *to_symbol)
5096 {
5097 valueT offset;
5098
5099 if (!HAVE_LONG_BRANCH (current_architecture))
5100 {
5101 if (flag_keep_pcrel)
5102 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5103 offset = to_addr - S_GET_VALUE (to_symbol);
5104 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5105 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5106 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5107 0, NO_RELOC);
5108 }
5109 else
5110 {
5111 offset = to_addr - (from_addr + 2);
5112 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5113 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5114 }
5115 }
5116
5117 #endif
5118
5119 /* Different values of OK tell what its OK to return. Things that
5120 aren't OK are an error (what a shock, no?)
5121
5122 0: Everything is OK
5123 10: Absolute 1:8 only
5124 20: Absolute 0:7 only
5125 30: absolute 0:15 only
5126 40: Absolute 0:31 only
5127 50: absolute 0:127 only
5128 55: absolute -64:63 only
5129 60: absolute -128:127 only
5130 70: absolute 0:4095 only
5131 80: absolute -1, 1:7 only
5132 90: No bignums. */
5133
5134 static int
5135 get_num (struct m68k_exp *exp, int ok)
5136 {
5137 if (exp->exp.X_op == O_absent)
5138 {
5139 /* Do the same thing the VAX asm does. */
5140 op (exp) = O_constant;
5141 adds (exp) = 0;
5142 subs (exp) = 0;
5143 offs (exp) = 0;
5144 if (ok == 10)
5145 {
5146 as_warn (_("expression out of range: defaulting to 1"));
5147 offs (exp) = 1;
5148 }
5149 }
5150 else if (exp->exp.X_op == O_constant)
5151 {
5152 switch (ok)
5153 {
5154 case 10:
5155 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5156 {
5157 as_warn (_("expression out of range: defaulting to 1"));
5158 offs (exp) = 1;
5159 }
5160 break;
5161 case 20:
5162 if ((valueT) TRUNC (offs (exp)) > 7)
5163 goto outrange;
5164 break;
5165 case 30:
5166 if ((valueT) TRUNC (offs (exp)) > 15)
5167 goto outrange;
5168 break;
5169 case 40:
5170 if ((valueT) TRUNC (offs (exp)) > 32)
5171 goto outrange;
5172 break;
5173 case 50:
5174 if ((valueT) TRUNC (offs (exp)) > 127)
5175 goto outrange;
5176 break;
5177 case 55:
5178 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5179 goto outrange;
5180 break;
5181 case 60:
5182 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5183 goto outrange;
5184 break;
5185 case 70:
5186 if ((valueT) TRUNC (offs (exp)) > 4095)
5187 {
5188 outrange:
5189 as_warn (_("expression out of range: defaulting to 0"));
5190 offs (exp) = 0;
5191 }
5192 break;
5193 case 80:
5194 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5195 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5196 {
5197 as_warn (_("expression out of range: defaulting to 1"));
5198 offs (exp) = 1;
5199 }
5200 break;
5201 default:
5202 break;
5203 }
5204 }
5205 else if (exp->exp.X_op == O_big)
5206 {
5207 if (offs (exp) <= 0 /* flonum. */
5208 && (ok == 90 /* no bignums */
5209 || (ok > 10 /* Small-int ranges including 0 ok. */
5210 /* If we have a flonum zero, a zero integer should
5211 do as well (e.g., in moveq). */
5212 && generic_floating_point_number.exponent == 0
5213 && generic_floating_point_number.low[0] == 0)))
5214 {
5215 /* HACK! Turn it into a long. */
5216 LITTLENUM_TYPE words[6];
5217
5218 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5219 op (exp) = O_constant;
5220 adds (exp) = 0;
5221 subs (exp) = 0;
5222 offs (exp) = words[1] | (words[0] << 16);
5223 }
5224 else if (ok != 0)
5225 {
5226 op (exp) = O_constant;
5227 adds (exp) = 0;
5228 subs (exp) = 0;
5229 offs (exp) = (ok == 10) ? 1 : 0;
5230 as_warn (_("Can't deal with expression; defaulting to %ld"),
5231 (long) offs (exp));
5232 }
5233 }
5234 else
5235 {
5236 if (ok >= 10 && ok <= 80)
5237 {
5238 op (exp) = O_constant;
5239 adds (exp) = 0;
5240 subs (exp) = 0;
5241 offs (exp) = (ok == 10) ? 1 : 0;
5242 as_warn (_("Can't deal with expression; defaulting to %ld"),
5243 (long) offs (exp));
5244 }
5245 }
5246
5247 if (exp->size != SIZE_UNSPEC)
5248 {
5249 switch (exp->size)
5250 {
5251 case SIZE_UNSPEC:
5252 case SIZE_LONG:
5253 break;
5254 case SIZE_BYTE:
5255 if (!isbyte (offs (exp)))
5256 as_warn (_("expression doesn't fit in BYTE"));
5257 break;
5258 case SIZE_WORD:
5259 if (!isword (offs (exp)))
5260 as_warn (_("expression doesn't fit in WORD"));
5261 break;
5262 }
5263 }
5264
5265 return offs (exp);
5266 }
5267
5268 /* These are the back-ends for the various machine dependent pseudo-ops. */
5269
5270 static void
5271 s_data1 (int ignore ATTRIBUTE_UNUSED)
5272 {
5273 subseg_set (data_section, 1);
5274 demand_empty_rest_of_line ();
5275 }
5276
5277 static void
5278 s_data2 (int ignore ATTRIBUTE_UNUSED)
5279 {
5280 subseg_set (data_section, 2);
5281 demand_empty_rest_of_line ();
5282 }
5283
5284 static void
5285 s_bss (int ignore ATTRIBUTE_UNUSED)
5286 {
5287 /* We don't support putting frags in the BSS segment, we fake it
5288 by marking in_bss, then looking at s_skip for clues. */
5289
5290 subseg_set (bss_section, 0);
5291 demand_empty_rest_of_line ();
5292 }
5293
5294 static void
5295 s_even (int ignore ATTRIBUTE_UNUSED)
5296 {
5297 register int temp;
5298 register long temp_fill;
5299
5300 temp = 1; /* JF should be 2? */
5301 temp_fill = get_absolute_expression ();
5302 if (!need_pass_2) /* Never make frag if expect extra pass. */
5303 frag_align (temp, (int) temp_fill, 0);
5304 demand_empty_rest_of_line ();
5305 record_alignment (now_seg, temp);
5306 }
5307
5308 static void
5309 s_proc (int ignore ATTRIBUTE_UNUSED)
5310 {
5311 demand_empty_rest_of_line ();
5312 }
5313 \f
5314 /* Pseudo-ops handled for MRI compatibility. */
5315
5316 /* This function returns non-zero if the argument is a conditional
5317 pseudo-op. This is called when checking whether a pending
5318 alignment is needed. */
5319
5320 int
5321 m68k_conditional_pseudoop (pseudo_typeS *pop)
5322 {
5323 return (pop->poc_handler == s_mri_if
5324 || pop->poc_handler == s_mri_else);
5325 }
5326
5327 /* Handle an MRI style chip specification. */
5328
5329 static void
5330 mri_chip (void)
5331 {
5332 char *s;
5333 char c;
5334 int i;
5335
5336 s = input_line_pointer;
5337 /* We can't use get_symbol_end since the processor names are not proper
5338 symbols. */
5339 while (is_part_of_name (c = *input_line_pointer++))
5340 ;
5341 *--input_line_pointer = 0;
5342 for (i = 0; m68k_cpus[i].name; i++)
5343 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5344 break;
5345 if (!m68k_cpus[i].name)
5346 {
5347 as_bad (_("%s: unrecognized processor name"), s);
5348 *input_line_pointer = c;
5349 ignore_rest_of_line ();
5350 return;
5351 }
5352 *input_line_pointer = c;
5353
5354 if (*input_line_pointer == '/')
5355 current_architecture = 0;
5356 else
5357 current_architecture &= m68881 | m68851;
5358 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5359 control_regs = m68k_cpus[i].control_regs;
5360
5361 while (*input_line_pointer == '/')
5362 {
5363 ++input_line_pointer;
5364 s = input_line_pointer;
5365 /* We can't use get_symbol_end since the processor names are not
5366 proper symbols. */
5367 while (is_part_of_name (c = *input_line_pointer++))
5368 ;
5369 *--input_line_pointer = 0;
5370 if (strcmp (s, "68881") == 0)
5371 current_architecture |= m68881;
5372 else if (strcmp (s, "68851") == 0)
5373 current_architecture |= m68851;
5374 *input_line_pointer = c;
5375 }
5376 }
5377
5378 /* The MRI CHIP pseudo-op. */
5379
5380 static void
5381 s_chip (int ignore ATTRIBUTE_UNUSED)
5382 {
5383 char *stop = NULL;
5384 char stopc;
5385
5386 if (flag_mri)
5387 stop = mri_comment_field (&stopc);
5388 mri_chip ();
5389 if (flag_mri)
5390 mri_comment_end (stop, stopc);
5391 demand_empty_rest_of_line ();
5392 }
5393
5394 /* The MRI FOPT pseudo-op. */
5395
5396 static void
5397 s_fopt (int ignore ATTRIBUTE_UNUSED)
5398 {
5399 SKIP_WHITESPACE ();
5400
5401 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5402 {
5403 int temp;
5404
5405 input_line_pointer += 3;
5406 temp = get_absolute_expression ();
5407 if (temp < 0 || temp > 7)
5408 as_bad (_("bad coprocessor id"));
5409 else
5410 m68k_float_copnum = COP0 + temp;
5411 }
5412 else
5413 {
5414 as_bad (_("unrecognized fopt option"));
5415 ignore_rest_of_line ();
5416 return;
5417 }
5418
5419 demand_empty_rest_of_line ();
5420 }
5421
5422 /* The structure used to handle the MRI OPT pseudo-op. */
5423
5424 struct opt_action
5425 {
5426 /* The name of the option. */
5427 const char *name;
5428
5429 /* If this is not NULL, just call this function. The first argument
5430 is the ARG field of this structure, the second argument is
5431 whether the option was negated. */
5432 void (*pfn) (int arg, int on);
5433
5434 /* If this is not NULL, and the PFN field is NULL, set the variable
5435 this points to. Set it to the ARG field if the option was not
5436 negated, and the NOTARG field otherwise. */
5437 int *pvar;
5438
5439 /* The value to pass to PFN or to assign to *PVAR. */
5440 int arg;
5441
5442 /* The value to assign to *PVAR if the option is negated. If PFN is
5443 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5444 the option may not be negated. */
5445 int notarg;
5446 };
5447
5448 /* The table used to handle the MRI OPT pseudo-op. */
5449
5450 static void skip_to_comma (int, int);
5451 static void opt_nest (int, int);
5452 static void opt_chip (int, int);
5453 static void opt_list (int, int);
5454 static void opt_list_symbols (int, int);
5455
5456 static const struct opt_action opt_table[] =
5457 {
5458 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5459
5460 /* We do relaxing, so there is little use for these options. */
5461 { "b", 0, 0, 0, 0 },
5462 { "brs", 0, 0, 0, 0 },
5463 { "brb", 0, 0, 0, 0 },
5464 { "brl", 0, 0, 0, 0 },
5465 { "brw", 0, 0, 0, 0 },
5466
5467 { "c", 0, 0, 0, 0 },
5468 { "cex", 0, 0, 0, 0 },
5469 { "case", 0, &symbols_case_sensitive, 1, 0 },
5470 { "cl", 0, 0, 0, 0 },
5471 { "cre", 0, 0, 0, 0 },
5472 { "d", 0, &flag_keep_locals, 1, 0 },
5473 { "e", 0, 0, 0, 0 },
5474 { "f", 0, &flag_short_refs, 1, 0 },
5475 { "frs", 0, &flag_short_refs, 1, 0 },
5476 { "frl", 0, &flag_short_refs, 0, 1 },
5477 { "g", 0, 0, 0, 0 },
5478 { "i", 0, 0, 0, 0 },
5479 { "m", 0, 0, 0, 0 },
5480 { "mex", 0, 0, 0, 0 },
5481 { "mc", 0, 0, 0, 0 },
5482 { "md", 0, 0, 0, 0 },
5483 { "nest", opt_nest, 0, 0, 0 },
5484 { "next", skip_to_comma, 0, 0, 0 },
5485 { "o", 0, 0, 0, 0 },
5486 { "old", 0, 0, 0, 0 },
5487 { "op", skip_to_comma, 0, 0, 0 },
5488 { "pco", 0, 0, 0, 0 },
5489 { "p", opt_chip, 0, 0, 0 },
5490 { "pcr", 0, 0, 0, 0 },
5491 { "pcs", 0, 0, 0, 0 },
5492 { "r", 0, 0, 0, 0 },
5493 { "quick", 0, &m68k_quick, 1, 0 },
5494 { "rel32", 0, &m68k_rel32, 1, 0 },
5495 { "s", opt_list, 0, 0, 0 },
5496 { "t", opt_list_symbols, 0, 0, 0 },
5497 { "w", 0, &flag_no_warnings, 0, 1 },
5498 { "x", 0, 0, 0, 0 }
5499 };
5500
5501 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5502
5503 /* The MRI OPT pseudo-op. */
5504
5505 static void
5506 s_opt (int ignore ATTRIBUTE_UNUSED)
5507 {
5508 do
5509 {
5510 int t;
5511 char *s;
5512 char c;
5513 int i;
5514 const struct opt_action *o;
5515
5516 SKIP_WHITESPACE ();
5517
5518 t = 1;
5519 if (*input_line_pointer == '-')
5520 {
5521 ++input_line_pointer;
5522 t = 0;
5523 }
5524 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5525 {
5526 input_line_pointer += 2;
5527 t = 0;
5528 }
5529
5530 s = input_line_pointer;
5531 c = get_symbol_end ();
5532
5533 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5534 {
5535 if (strcasecmp (s, o->name) == 0)
5536 {
5537 if (o->pfn)
5538 {
5539 /* Restore input_line_pointer now in case the option
5540 takes arguments. */
5541 *input_line_pointer = c;
5542 (*o->pfn) (o->arg, t);
5543 }
5544 else if (o->pvar != NULL)
5545 {
5546 if (! t && o->arg == o->notarg)
5547 as_bad (_("option `%s' may not be negated"), s);
5548 *input_line_pointer = c;
5549 *o->pvar = t ? o->arg : o->notarg;
5550 }
5551 else
5552 *input_line_pointer = c;
5553 break;
5554 }
5555 }
5556 if (i >= OPTCOUNT)
5557 {
5558 as_bad (_("option `%s' not recognized"), s);
5559 *input_line_pointer = c;
5560 }
5561 }
5562 while (*input_line_pointer++ == ',');
5563
5564 /* Move back to terminating character. */
5565 --input_line_pointer;
5566 demand_empty_rest_of_line ();
5567 }
5568
5569 /* Skip ahead to a comma. This is used for OPT options which we do
5570 not support and which take arguments. */
5571
5572 static void
5573 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5574 {
5575 while (*input_line_pointer != ','
5576 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5577 ++input_line_pointer;
5578 }
5579
5580 /* Handle the OPT NEST=depth option. */
5581
5582 static void
5583 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5584 {
5585 if (*input_line_pointer != '=')
5586 {
5587 as_bad (_("bad format of OPT NEST=depth"));
5588 return;
5589 }
5590
5591 ++input_line_pointer;
5592 max_macro_nest = get_absolute_expression ();
5593 }
5594
5595 /* Handle the OPT P=chip option. */
5596
5597 static void
5598 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5599 {
5600 if (*input_line_pointer != '=')
5601 {
5602 /* This is just OPT P, which we do not support. */
5603 return;
5604 }
5605
5606 ++input_line_pointer;
5607 mri_chip ();
5608 }
5609
5610 /* Handle the OPT S option. */
5611
5612 static void
5613 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5614 {
5615 listing_list (on);
5616 }
5617
5618 /* Handle the OPT T option. */
5619
5620 static void
5621 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5622 {
5623 if (on)
5624 listing |= LISTING_SYMBOLS;
5625 else
5626 listing &= ~LISTING_SYMBOLS;
5627 }
5628
5629 /* Handle the MRI REG pseudo-op. */
5630
5631 static void
5632 s_reg (int ignore ATTRIBUTE_UNUSED)
5633 {
5634 char *s;
5635 int c;
5636 struct m68k_op rop;
5637 int mask;
5638 char *stop = NULL;
5639 char stopc;
5640
5641 if (line_label == NULL)
5642 {
5643 as_bad (_("missing label"));
5644 ignore_rest_of_line ();
5645 return;
5646 }
5647
5648 if (flag_mri)
5649 stop = mri_comment_field (&stopc);
5650
5651 SKIP_WHITESPACE ();
5652
5653 s = input_line_pointer;
5654 while (ISALNUM (*input_line_pointer)
5655 #ifdef REGISTER_PREFIX
5656 || *input_line_pointer == REGISTER_PREFIX
5657 #endif
5658 || *input_line_pointer == '/'
5659 || *input_line_pointer == '-')
5660 ++input_line_pointer;
5661 c = *input_line_pointer;
5662 *input_line_pointer = '\0';
5663
5664 if (m68k_ip_op (s, &rop) != 0)
5665 {
5666 if (rop.error == NULL)
5667 as_bad (_("bad register list"));
5668 else
5669 as_bad (_("bad register list: %s"), rop.error);
5670 *input_line_pointer = c;
5671 ignore_rest_of_line ();
5672 return;
5673 }
5674
5675 *input_line_pointer = c;
5676
5677 if (rop.mode == REGLST)
5678 mask = rop.mask;
5679 else if (rop.mode == DREG)
5680 mask = 1 << (rop.reg - DATA0);
5681 else if (rop.mode == AREG)
5682 mask = 1 << (rop.reg - ADDR0 + 8);
5683 else if (rop.mode == FPREG)
5684 mask = 1 << (rop.reg - FP0 + 16);
5685 else if (rop.mode == CONTROL
5686 && rop.reg == FPI)
5687 mask = 1 << 24;
5688 else if (rop.mode == CONTROL
5689 && rop.reg == FPS)
5690 mask = 1 << 25;
5691 else if (rop.mode == CONTROL
5692 && rop.reg == FPC)
5693 mask = 1 << 26;
5694 else
5695 {
5696 as_bad (_("bad register list"));
5697 ignore_rest_of_line ();
5698 return;
5699 }
5700
5701 S_SET_SEGMENT (line_label, reg_section);
5702 S_SET_VALUE (line_label, ~mask);
5703 symbol_set_frag (line_label, &zero_address_frag);
5704
5705 if (flag_mri)
5706 mri_comment_end (stop, stopc);
5707
5708 demand_empty_rest_of_line ();
5709 }
5710
5711 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5712
5713 struct save_opts
5714 {
5715 struct save_opts *next;
5716 int abspcadd;
5717 int symbols_case_sensitive;
5718 int keep_locals;
5719 int short_refs;
5720 int architecture;
5721 const enum m68k_register *control_regs;
5722 int quick;
5723 int rel32;
5724 int listing;
5725 int no_warnings;
5726 /* FIXME: We don't save OPT S. */
5727 };
5728
5729 /* This variable holds the stack of saved options. */
5730
5731 static struct save_opts *save_stack;
5732
5733 /* The MRI SAVE pseudo-op. */
5734
5735 static void
5736 s_save (int ignore ATTRIBUTE_UNUSED)
5737 {
5738 struct save_opts *s;
5739
5740 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5741 s->abspcadd = m68k_abspcadd;
5742 s->symbols_case_sensitive = symbols_case_sensitive;
5743 s->keep_locals = flag_keep_locals;
5744 s->short_refs = flag_short_refs;
5745 s->architecture = current_architecture;
5746 s->control_regs = control_regs;
5747 s->quick = m68k_quick;
5748 s->rel32 = m68k_rel32;
5749 s->listing = listing;
5750 s->no_warnings = flag_no_warnings;
5751
5752 s->next = save_stack;
5753 save_stack = s;
5754
5755 demand_empty_rest_of_line ();
5756 }
5757
5758 /* The MRI RESTORE pseudo-op. */
5759
5760 static void
5761 s_restore (int ignore ATTRIBUTE_UNUSED)
5762 {
5763 struct save_opts *s;
5764
5765 if (save_stack == NULL)
5766 {
5767 as_bad (_("restore without save"));
5768 ignore_rest_of_line ();
5769 return;
5770 }
5771
5772 s = save_stack;
5773 save_stack = s->next;
5774
5775 m68k_abspcadd = s->abspcadd;
5776 symbols_case_sensitive = s->symbols_case_sensitive;
5777 flag_keep_locals = s->keep_locals;
5778 flag_short_refs = s->short_refs;
5779 current_architecture = s->architecture;
5780 control_regs = s->control_regs;
5781 m68k_quick = s->quick;
5782 m68k_rel32 = s->rel32;
5783 listing = s->listing;
5784 flag_no_warnings = s->no_warnings;
5785
5786 free (s);
5787
5788 demand_empty_rest_of_line ();
5789 }
5790
5791 /* Types of MRI structured control directives. */
5792
5793 enum mri_control_type
5794 {
5795 mri_for,
5796 mri_if,
5797 mri_repeat,
5798 mri_while
5799 };
5800
5801 /* This structure is used to stack the MRI structured control
5802 directives. */
5803
5804 struct mri_control_info
5805 {
5806 /* The directive within which this one is enclosed. */
5807 struct mri_control_info *outer;
5808
5809 /* The type of directive. */
5810 enum mri_control_type type;
5811
5812 /* Whether an ELSE has been in an IF. */
5813 int else_seen;
5814
5815 /* The add or sub statement at the end of a FOR. */
5816 char *incr;
5817
5818 /* The label of the top of a FOR or REPEAT loop. */
5819 char *top;
5820
5821 /* The label to jump to for the next iteration, or the else
5822 expression of a conditional. */
5823 char *next;
5824
5825 /* The label to jump to to break out of the loop, or the label past
5826 the end of a conditional. */
5827 char *bottom;
5828 };
5829
5830 /* The stack of MRI structured control directives. */
5831
5832 static struct mri_control_info *mri_control_stack;
5833
5834 /* The current MRI structured control directive index number, used to
5835 generate label names. */
5836
5837 static int mri_control_index;
5838
5839 /* Assemble an instruction for an MRI structured control directive. */
5840
5841 static void
5842 mri_assemble (char *str)
5843 {
5844 char *s;
5845
5846 /* md_assemble expects the opcode to be in lower case. */
5847 for (s = str; *s != ' ' && *s != '\0'; s++)
5848 *s = TOLOWER (*s);
5849
5850 md_assemble (str);
5851 }
5852
5853 /* Generate a new MRI label structured control directive label name. */
5854
5855 static char *
5856 mri_control_label (void)
5857 {
5858 char *n;
5859
5860 n = (char *) xmalloc (20);
5861 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5862 ++mri_control_index;
5863 return n;
5864 }
5865
5866 /* Create a new MRI structured control directive. */
5867
5868 static struct mri_control_info *
5869 push_mri_control (enum mri_control_type type)
5870 {
5871 struct mri_control_info *n;
5872
5873 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5874
5875 n->type = type;
5876 n->else_seen = 0;
5877 if (type == mri_if || type == mri_while)
5878 n->top = NULL;
5879 else
5880 n->top = mri_control_label ();
5881 n->next = mri_control_label ();
5882 n->bottom = mri_control_label ();
5883
5884 n->outer = mri_control_stack;
5885 mri_control_stack = n;
5886
5887 return n;
5888 }
5889
5890 /* Pop off the stack of MRI structured control directives. */
5891
5892 static void
5893 pop_mri_control (void)
5894 {
5895 struct mri_control_info *n;
5896
5897 n = mri_control_stack;
5898 mri_control_stack = n->outer;
5899 if (n->top != NULL)
5900 free (n->top);
5901 free (n->next);
5902 free (n->bottom);
5903 free (n);
5904 }
5905
5906 /* Recognize a condition code in an MRI structured control expression. */
5907
5908 static int
5909 parse_mri_condition (int *pcc)
5910 {
5911 char c1, c2;
5912
5913 know (*input_line_pointer == '<');
5914
5915 ++input_line_pointer;
5916 c1 = *input_line_pointer++;
5917 c2 = *input_line_pointer++;
5918
5919 if (*input_line_pointer != '>')
5920 {
5921 as_bad (_("syntax error in structured control directive"));
5922 return 0;
5923 }
5924
5925 ++input_line_pointer;
5926 SKIP_WHITESPACE ();
5927
5928 c1 = TOLOWER (c1);
5929 c2 = TOLOWER (c2);
5930
5931 *pcc = (c1 << 8) | c2;
5932
5933 return 1;
5934 }
5935
5936 /* Parse a single operand in an MRI structured control expression. */
5937
5938 static int
5939 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5940 char **rightstart, char **rightstop)
5941 {
5942 char *s;
5943
5944 SKIP_WHITESPACE ();
5945
5946 *pcc = -1;
5947 *leftstart = NULL;
5948 *leftstop = NULL;
5949 *rightstart = NULL;
5950 *rightstop = NULL;
5951
5952 if (*input_line_pointer == '<')
5953 {
5954 /* It's just a condition code. */
5955 return parse_mri_condition (pcc);
5956 }
5957
5958 /* Look ahead for the condition code. */
5959 for (s = input_line_pointer; *s != '\0'; ++s)
5960 {
5961 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5962 break;
5963 }
5964 if (*s == '\0')
5965 {
5966 as_bad (_("missing condition code in structured control directive"));
5967 return 0;
5968 }
5969
5970 *leftstart = input_line_pointer;
5971 *leftstop = s;
5972 if (*leftstop > *leftstart
5973 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5974 --*leftstop;
5975
5976 input_line_pointer = s;
5977 if (! parse_mri_condition (pcc))
5978 return 0;
5979
5980 /* Look ahead for AND or OR or end of line. */
5981 for (s = input_line_pointer; *s != '\0'; ++s)
5982 {
5983 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5984 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5985 ^^^ ^^ */
5986 if ((s == input_line_pointer
5987 || *(s-1) == ' '
5988 || *(s-1) == '\t')
5989 && ((strncasecmp (s, "AND", 3) == 0
5990 && (s[3] == '.' || ! is_part_of_name (s[3])))
5991 || (strncasecmp (s, "OR", 2) == 0
5992 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5993 break;
5994 }
5995
5996 *rightstart = input_line_pointer;
5997 *rightstop = s;
5998 if (*rightstop > *rightstart
5999 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6000 --*rightstop;
6001
6002 input_line_pointer = s;
6003
6004 return 1;
6005 }
6006
6007 #define MCC(b1, b2) (((b1) << 8) | (b2))
6008
6009 /* Swap the sense of a condition. This changes the condition so that
6010 it generates the same result when the operands are swapped. */
6011
6012 static int
6013 swap_mri_condition (int cc)
6014 {
6015 switch (cc)
6016 {
6017 case MCC ('h', 'i'): return MCC ('c', 's');
6018 case MCC ('l', 's'): return MCC ('c', 'c');
6019 /* <HS> is an alias for <CC>. */
6020 case MCC ('h', 's'):
6021 case MCC ('c', 'c'): return MCC ('l', 's');
6022 /* <LO> is an alias for <CS>. */
6023 case MCC ('l', 'o'):
6024 case MCC ('c', 's'): return MCC ('h', 'i');
6025 case MCC ('p', 'l'): return MCC ('m', 'i');
6026 case MCC ('m', 'i'): return MCC ('p', 'l');
6027 case MCC ('g', 'e'): return MCC ('l', 'e');
6028 case MCC ('l', 't'): return MCC ('g', 't');
6029 case MCC ('g', 't'): return MCC ('l', 't');
6030 case MCC ('l', 'e'): return MCC ('g', 'e');
6031 /* Issue a warning for conditions we can not swap. */
6032 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6033 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6034 case MCC ('v', 'c'):
6035 case MCC ('v', 's'):
6036 default :
6037 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6038 (char) (cc >> 8), (char) (cc));
6039 break;
6040 }
6041 return cc;
6042 }
6043
6044 /* Reverse the sense of a condition. */
6045
6046 static int
6047 reverse_mri_condition (int cc)
6048 {
6049 switch (cc)
6050 {
6051 case MCC ('h', 'i'): return MCC ('l', 's');
6052 case MCC ('l', 's'): return MCC ('h', 'i');
6053 /* <HS> is an alias for <CC> */
6054 case MCC ('h', 's'): return MCC ('l', 'o');
6055 case MCC ('c', 'c'): return MCC ('c', 's');
6056 /* <LO> is an alias for <CS> */
6057 case MCC ('l', 'o'): return MCC ('h', 's');
6058 case MCC ('c', 's'): return MCC ('c', 'c');
6059 case MCC ('n', 'e'): return MCC ('e', 'q');
6060 case MCC ('e', 'q'): return MCC ('n', 'e');
6061 case MCC ('v', 'c'): return MCC ('v', 's');
6062 case MCC ('v', 's'): return MCC ('v', 'c');
6063 case MCC ('p', 'l'): return MCC ('m', 'i');
6064 case MCC ('m', 'i'): return MCC ('p', 'l');
6065 case MCC ('g', 'e'): return MCC ('l', 't');
6066 case MCC ('l', 't'): return MCC ('g', 'e');
6067 case MCC ('g', 't'): return MCC ('l', 'e');
6068 case MCC ('l', 'e'): return MCC ('g', 't');
6069 }
6070 return cc;
6071 }
6072
6073 /* Build an MRI structured control expression. This generates test
6074 and branch instructions. It goes to TRUELAB if the condition is
6075 true, and to FALSELAB if the condition is false. Exactly one of
6076 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6077 is the size qualifier for the expression. EXTENT is the size to
6078 use for the branch. */
6079
6080 static void
6081 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6082 char *rightstart, char *rightstop,
6083 const char *truelab, const char *falselab,
6084 int extent)
6085 {
6086 char *buf;
6087 char *s;
6088
6089 if (leftstart != NULL)
6090 {
6091 struct m68k_op leftop, rightop;
6092 char c;
6093
6094 /* Swap the compare operands, if necessary, to produce a legal
6095 m68k compare instruction. Comparing a register operand with
6096 a non-register operand requires the register to be on the
6097 right (cmp, cmpa). Comparing an immediate value with
6098 anything requires the immediate value to be on the left
6099 (cmpi). */
6100
6101 c = *leftstop;
6102 *leftstop = '\0';
6103 (void) m68k_ip_op (leftstart, &leftop);
6104 *leftstop = c;
6105
6106 c = *rightstop;
6107 *rightstop = '\0';
6108 (void) m68k_ip_op (rightstart, &rightop);
6109 *rightstop = c;
6110
6111 if (rightop.mode == IMMED
6112 || ((leftop.mode == DREG || leftop.mode == AREG)
6113 && (rightop.mode != DREG && rightop.mode != AREG)))
6114 {
6115 char *temp;
6116
6117 /* Correct conditional handling:
6118 if #1 <lt> d0 then ;means if (1 < d0)
6119 ...
6120 endi
6121
6122 should assemble to:
6123
6124 cmp #1,d0 if we do *not* swap the operands
6125 bgt true we need the swapped condition!
6126 ble false
6127 true:
6128 ...
6129 false:
6130 */
6131 temp = leftstart;
6132 leftstart = rightstart;
6133 rightstart = temp;
6134 temp = leftstop;
6135 leftstop = rightstop;
6136 rightstop = temp;
6137 }
6138 else
6139 {
6140 cc = swap_mri_condition (cc);
6141 }
6142 }
6143
6144 if (truelab == NULL)
6145 {
6146 cc = reverse_mri_condition (cc);
6147 truelab = falselab;
6148 }
6149
6150 if (leftstart != NULL)
6151 {
6152 buf = (char *) xmalloc (20
6153 + (leftstop - leftstart)
6154 + (rightstop - rightstart));
6155 s = buf;
6156 *s++ = 'c';
6157 *s++ = 'm';
6158 *s++ = 'p';
6159 if (qual != '\0')
6160 *s++ = TOLOWER (qual);
6161 *s++ = ' ';
6162 memcpy (s, leftstart, leftstop - leftstart);
6163 s += leftstop - leftstart;
6164 *s++ = ',';
6165 memcpy (s, rightstart, rightstop - rightstart);
6166 s += rightstop - rightstart;
6167 *s = '\0';
6168 mri_assemble (buf);
6169 free (buf);
6170 }
6171
6172 buf = (char *) xmalloc (20 + strlen (truelab));
6173 s = buf;
6174 *s++ = 'b';
6175 *s++ = cc >> 8;
6176 *s++ = cc & 0xff;
6177 if (extent != '\0')
6178 *s++ = TOLOWER (extent);
6179 *s++ = ' ';
6180 strcpy (s, truelab);
6181 mri_assemble (buf);
6182 free (buf);
6183 }
6184
6185 /* Parse an MRI structured control expression. This generates test
6186 and branch instructions. STOP is where the expression ends. It
6187 goes to TRUELAB if the condition is true, and to FALSELAB if the
6188 condition is false. Exactly one of TRUELAB and FALSELAB will be
6189 NULL, meaning to fall through. QUAL is the size qualifier for the
6190 expression. EXTENT is the size to use for the branch. */
6191
6192 static void
6193 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6194 const char *falselab, int extent)
6195 {
6196 int c;
6197 int cc;
6198 char *leftstart;
6199 char *leftstop;
6200 char *rightstart;
6201 char *rightstop;
6202
6203 c = *stop;
6204 *stop = '\0';
6205
6206 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6207 &rightstart, &rightstop))
6208 {
6209 *stop = c;
6210 return;
6211 }
6212
6213 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6214 {
6215 const char *flab;
6216
6217 if (falselab != NULL)
6218 flab = falselab;
6219 else
6220 flab = mri_control_label ();
6221
6222 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6223 rightstop, (const char *) NULL, flab, extent);
6224
6225 input_line_pointer += 3;
6226 if (*input_line_pointer != '.'
6227 || input_line_pointer[1] == '\0')
6228 qual = '\0';
6229 else
6230 {
6231 qual = input_line_pointer[1];
6232 input_line_pointer += 2;
6233 }
6234
6235 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6236 &rightstart, &rightstop))
6237 {
6238 *stop = c;
6239 return;
6240 }
6241
6242 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6243 rightstop, truelab, falselab, extent);
6244
6245 if (falselab == NULL)
6246 colon (flab);
6247 }
6248 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6249 {
6250 const char *tlab;
6251
6252 if (truelab != NULL)
6253 tlab = truelab;
6254 else
6255 tlab = mri_control_label ();
6256
6257 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6258 rightstop, tlab, (const char *) NULL, extent);
6259
6260 input_line_pointer += 2;
6261 if (*input_line_pointer != '.'
6262 || input_line_pointer[1] == '\0')
6263 qual = '\0';
6264 else
6265 {
6266 qual = input_line_pointer[1];
6267 input_line_pointer += 2;
6268 }
6269
6270 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6271 &rightstart, &rightstop))
6272 {
6273 *stop = c;
6274 return;
6275 }
6276
6277 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6278 rightstop, truelab, falselab, extent);
6279
6280 if (truelab == NULL)
6281 colon (tlab);
6282 }
6283 else
6284 {
6285 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6286 rightstop, truelab, falselab, extent);
6287 }
6288
6289 *stop = c;
6290 if (input_line_pointer != stop)
6291 as_bad (_("syntax error in structured control directive"));
6292 }
6293
6294 /* Handle the MRI IF pseudo-op. This may be a structured control
6295 directive, or it may be a regular assembler conditional, depending
6296 on its operands. */
6297
6298 static void
6299 s_mri_if (int qual)
6300 {
6301 char *s;
6302 int c;
6303 struct mri_control_info *n;
6304
6305 /* A structured control directive must end with THEN with an
6306 optional qualifier. */
6307 s = input_line_pointer;
6308 /* We only accept '*' as introduction of comments if preceded by white space
6309 or at first column of a line (I think this can't actually happen here?)
6310 This is important when assembling:
6311 if d0 <ne> 12(a0,d0*2) then
6312 if d0 <ne> #CONST*20 then. */
6313 while (! (is_end_of_line[(unsigned char) *s]
6314 || (flag_mri
6315 && *s == '*'
6316 && (s == input_line_pointer
6317 || *(s-1) == ' '
6318 || *(s-1) == '\t'))))
6319 ++s;
6320 --s;
6321 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6322 --s;
6323
6324 if (s - input_line_pointer > 1
6325 && s[-1] == '.')
6326 s -= 2;
6327
6328 if (s - input_line_pointer < 3
6329 || strncasecmp (s - 3, "THEN", 4) != 0)
6330 {
6331 if (qual != '\0')
6332 {
6333 as_bad (_("missing then"));
6334 ignore_rest_of_line ();
6335 return;
6336 }
6337
6338 /* It's a conditional. */
6339 s_if (O_ne);
6340 return;
6341 }
6342
6343 /* Since this might be a conditional if, this pseudo-op will be
6344 called even if we are supported to be ignoring input. Double
6345 check now. Clobber *input_line_pointer so that ignore_input
6346 thinks that this is not a special pseudo-op. */
6347 c = *input_line_pointer;
6348 *input_line_pointer = 0;
6349 if (ignore_input ())
6350 {
6351 *input_line_pointer = c;
6352 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6353 ++input_line_pointer;
6354 demand_empty_rest_of_line ();
6355 return;
6356 }
6357 *input_line_pointer = c;
6358
6359 n = push_mri_control (mri_if);
6360
6361 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6362 n->next, s[1] == '.' ? s[2] : '\0');
6363
6364 if (s[1] == '.')
6365 input_line_pointer = s + 3;
6366 else
6367 input_line_pointer = s + 1;
6368
6369 if (flag_mri)
6370 {
6371 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6372 ++input_line_pointer;
6373 }
6374
6375 demand_empty_rest_of_line ();
6376 }
6377
6378 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6379 structured IF, associate the ELSE with the IF. Otherwise, assume
6380 it is a conditional else. */
6381
6382 static void
6383 s_mri_else (int qual)
6384 {
6385 int c;
6386 char *buf;
6387 char q[2];
6388
6389 if (qual == '\0'
6390 && (mri_control_stack == NULL
6391 || mri_control_stack->type != mri_if
6392 || mri_control_stack->else_seen))
6393 {
6394 s_else (0);
6395 return;
6396 }
6397
6398 c = *input_line_pointer;
6399 *input_line_pointer = 0;
6400 if (ignore_input ())
6401 {
6402 *input_line_pointer = c;
6403 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6404 ++input_line_pointer;
6405 demand_empty_rest_of_line ();
6406 return;
6407 }
6408 *input_line_pointer = c;
6409
6410 if (mri_control_stack == NULL
6411 || mri_control_stack->type != mri_if
6412 || mri_control_stack->else_seen)
6413 {
6414 as_bad (_("else without matching if"));
6415 ignore_rest_of_line ();
6416 return;
6417 }
6418
6419 mri_control_stack->else_seen = 1;
6420
6421 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6422 q[0] = TOLOWER (qual);
6423 q[1] = '\0';
6424 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6425 mri_assemble (buf);
6426 free (buf);
6427
6428 colon (mri_control_stack->next);
6429
6430 if (flag_mri)
6431 {
6432 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6433 ++input_line_pointer;
6434 }
6435
6436 demand_empty_rest_of_line ();
6437 }
6438
6439 /* Handle the MRI ENDI pseudo-op. */
6440
6441 static void
6442 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6443 {
6444 if (mri_control_stack == NULL
6445 || mri_control_stack->type != mri_if)
6446 {
6447 as_bad (_("endi without matching if"));
6448 ignore_rest_of_line ();
6449 return;
6450 }
6451
6452 /* ignore_input will not return true for ENDI, so we don't need to
6453 worry about checking it again here. */
6454
6455 if (! mri_control_stack->else_seen)
6456 colon (mri_control_stack->next);
6457 colon (mri_control_stack->bottom);
6458
6459 pop_mri_control ();
6460
6461 if (flag_mri)
6462 {
6463 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6464 ++input_line_pointer;
6465 }
6466
6467 demand_empty_rest_of_line ();
6468 }
6469
6470 /* Handle the MRI BREAK pseudo-op. */
6471
6472 static void
6473 s_mri_break (int extent)
6474 {
6475 struct mri_control_info *n;
6476 char *buf;
6477 char ex[2];
6478
6479 n = mri_control_stack;
6480 while (n != NULL
6481 && n->type != mri_for
6482 && n->type != mri_repeat
6483 && n->type != mri_while)
6484 n = n->outer;
6485 if (n == NULL)
6486 {
6487 as_bad (_("break outside of structured loop"));
6488 ignore_rest_of_line ();
6489 return;
6490 }
6491
6492 buf = (char *) xmalloc (20 + strlen (n->bottom));
6493 ex[0] = TOLOWER (extent);
6494 ex[1] = '\0';
6495 sprintf (buf, "bra%s %s", ex, n->bottom);
6496 mri_assemble (buf);
6497 free (buf);
6498
6499 if (flag_mri)
6500 {
6501 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6502 ++input_line_pointer;
6503 }
6504
6505 demand_empty_rest_of_line ();
6506 }
6507
6508 /* Handle the MRI NEXT pseudo-op. */
6509
6510 static void
6511 s_mri_next (int extent)
6512 {
6513 struct mri_control_info *n;
6514 char *buf;
6515 char ex[2];
6516
6517 n = mri_control_stack;
6518 while (n != NULL
6519 && n->type != mri_for
6520 && n->type != mri_repeat
6521 && n->type != mri_while)
6522 n = n->outer;
6523 if (n == NULL)
6524 {
6525 as_bad (_("next outside of structured loop"));
6526 ignore_rest_of_line ();
6527 return;
6528 }
6529
6530 buf = (char *) xmalloc (20 + strlen (n->next));
6531 ex[0] = TOLOWER (extent);
6532 ex[1] = '\0';
6533 sprintf (buf, "bra%s %s", ex, n->next);
6534 mri_assemble (buf);
6535 free (buf);
6536
6537 if (flag_mri)
6538 {
6539 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6540 ++input_line_pointer;
6541 }
6542
6543 demand_empty_rest_of_line ();
6544 }
6545
6546 /* Handle the MRI FOR pseudo-op. */
6547
6548 static void
6549 s_mri_for (int qual)
6550 {
6551 const char *varstart, *varstop;
6552 const char *initstart, *initstop;
6553 const char *endstart, *endstop;
6554 const char *bystart, *bystop;
6555 int up;
6556 int by;
6557 int extent;
6558 struct mri_control_info *n;
6559 char *buf;
6560 char *s;
6561 char ex[2];
6562
6563 /* The syntax is
6564 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6565 */
6566
6567 SKIP_WHITESPACE ();
6568 varstart = input_line_pointer;
6569
6570 /* Look for the '='. */
6571 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6572 && *input_line_pointer != '=')
6573 ++input_line_pointer;
6574 if (*input_line_pointer != '=')
6575 {
6576 as_bad (_("missing ="));
6577 ignore_rest_of_line ();
6578 return;
6579 }
6580
6581 varstop = input_line_pointer;
6582 if (varstop > varstart
6583 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6584 --varstop;
6585
6586 ++input_line_pointer;
6587
6588 initstart = input_line_pointer;
6589
6590 /* Look for TO or DOWNTO. */
6591 up = 1;
6592 initstop = NULL;
6593 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6594 {
6595 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6596 && ! is_part_of_name (input_line_pointer[2]))
6597 {
6598 initstop = input_line_pointer;
6599 input_line_pointer += 2;
6600 break;
6601 }
6602 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6603 && ! is_part_of_name (input_line_pointer[6]))
6604 {
6605 initstop = input_line_pointer;
6606 up = 0;
6607 input_line_pointer += 6;
6608 break;
6609 }
6610 ++input_line_pointer;
6611 }
6612 if (initstop == NULL)
6613 {
6614 as_bad (_("missing to or downto"));
6615 ignore_rest_of_line ();
6616 return;
6617 }
6618 if (initstop > initstart
6619 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6620 --initstop;
6621
6622 SKIP_WHITESPACE ();
6623 endstart = input_line_pointer;
6624
6625 /* Look for BY or DO. */
6626 by = 0;
6627 endstop = NULL;
6628 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6629 {
6630 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6631 && ! is_part_of_name (input_line_pointer[2]))
6632 {
6633 endstop = input_line_pointer;
6634 by = 1;
6635 input_line_pointer += 2;
6636 break;
6637 }
6638 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6639 && (input_line_pointer[2] == '.'
6640 || ! is_part_of_name (input_line_pointer[2])))
6641 {
6642 endstop = input_line_pointer;
6643 input_line_pointer += 2;
6644 break;
6645 }
6646 ++input_line_pointer;
6647 }
6648 if (endstop == NULL)
6649 {
6650 as_bad (_("missing do"));
6651 ignore_rest_of_line ();
6652 return;
6653 }
6654 if (endstop > endstart
6655 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6656 --endstop;
6657
6658 if (! by)
6659 {
6660 bystart = "#1";
6661 bystop = bystart + 2;
6662 }
6663 else
6664 {
6665 SKIP_WHITESPACE ();
6666 bystart = input_line_pointer;
6667
6668 /* Look for DO. */
6669 bystop = NULL;
6670 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6671 {
6672 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6673 && (input_line_pointer[2] == '.'
6674 || ! is_part_of_name (input_line_pointer[2])))
6675 {
6676 bystop = input_line_pointer;
6677 input_line_pointer += 2;
6678 break;
6679 }
6680 ++input_line_pointer;
6681 }
6682 if (bystop == NULL)
6683 {
6684 as_bad (_("missing do"));
6685 ignore_rest_of_line ();
6686 return;
6687 }
6688 if (bystop > bystart
6689 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6690 --bystop;
6691 }
6692
6693 if (*input_line_pointer != '.')
6694 extent = '\0';
6695 else
6696 {
6697 extent = input_line_pointer[1];
6698 input_line_pointer += 2;
6699 }
6700
6701 /* We have fully parsed the FOR operands. Now build the loop. */
6702 n = push_mri_control (mri_for);
6703
6704 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6705
6706 /* Move init,var. */
6707 s = buf;
6708 *s++ = 'm';
6709 *s++ = 'o';
6710 *s++ = 'v';
6711 *s++ = 'e';
6712 if (qual != '\0')
6713 *s++ = TOLOWER (qual);
6714 *s++ = ' ';
6715 memcpy (s, initstart, initstop - initstart);
6716 s += initstop - initstart;
6717 *s++ = ',';
6718 memcpy (s, varstart, varstop - varstart);
6719 s += varstop - varstart;
6720 *s = '\0';
6721 mri_assemble (buf);
6722
6723 colon (n->top);
6724
6725 /* cmp end,var. */
6726 s = buf;
6727 *s++ = 'c';
6728 *s++ = 'm';
6729 *s++ = 'p';
6730 if (qual != '\0')
6731 *s++ = TOLOWER (qual);
6732 *s++ = ' ';
6733 memcpy (s, endstart, endstop - endstart);
6734 s += endstop - endstart;
6735 *s++ = ',';
6736 memcpy (s, varstart, varstop - varstart);
6737 s += varstop - varstart;
6738 *s = '\0';
6739 mri_assemble (buf);
6740
6741 /* bcc bottom. */
6742 ex[0] = TOLOWER (extent);
6743 ex[1] = '\0';
6744 if (up)
6745 sprintf (buf, "blt%s %s", ex, n->bottom);
6746 else
6747 sprintf (buf, "bgt%s %s", ex, n->bottom);
6748 mri_assemble (buf);
6749
6750 /* Put together the add or sub instruction used by ENDF. */
6751 s = buf;
6752 if (up)
6753 strcpy (s, "add");
6754 else
6755 strcpy (s, "sub");
6756 s += 3;
6757 if (qual != '\0')
6758 *s++ = TOLOWER (qual);
6759 *s++ = ' ';
6760 memcpy (s, bystart, bystop - bystart);
6761 s += bystop - bystart;
6762 *s++ = ',';
6763 memcpy (s, varstart, varstop - varstart);
6764 s += varstop - varstart;
6765 *s = '\0';
6766 n->incr = buf;
6767
6768 if (flag_mri)
6769 {
6770 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6771 ++input_line_pointer;
6772 }
6773
6774 demand_empty_rest_of_line ();
6775 }
6776
6777 /* Handle the MRI ENDF pseudo-op. */
6778
6779 static void
6780 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6781 {
6782 if (mri_control_stack == NULL
6783 || mri_control_stack->type != mri_for)
6784 {
6785 as_bad (_("endf without for"));
6786 ignore_rest_of_line ();
6787 return;
6788 }
6789
6790 colon (mri_control_stack->next);
6791
6792 mri_assemble (mri_control_stack->incr);
6793
6794 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6795 mri_assemble (mri_control_stack->incr);
6796
6797 free (mri_control_stack->incr);
6798
6799 colon (mri_control_stack->bottom);
6800
6801 pop_mri_control ();
6802
6803 if (flag_mri)
6804 {
6805 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6806 ++input_line_pointer;
6807 }
6808
6809 demand_empty_rest_of_line ();
6810 }
6811
6812 /* Handle the MRI REPEAT pseudo-op. */
6813
6814 static void
6815 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6816 {
6817 struct mri_control_info *n;
6818
6819 n = push_mri_control (mri_repeat);
6820 colon (n->top);
6821 if (flag_mri)
6822 {
6823 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6824 ++input_line_pointer;
6825 }
6826 demand_empty_rest_of_line ();
6827 }
6828
6829 /* Handle the MRI UNTIL pseudo-op. */
6830
6831 static void
6832 s_mri_until (int qual)
6833 {
6834 char *s;
6835
6836 if (mri_control_stack == NULL
6837 || mri_control_stack->type != mri_repeat)
6838 {
6839 as_bad (_("until without repeat"));
6840 ignore_rest_of_line ();
6841 return;
6842 }
6843
6844 colon (mri_control_stack->next);
6845
6846 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6847 ;
6848
6849 parse_mri_control_expression (s, qual, (const char *) NULL,
6850 mri_control_stack->top, '\0');
6851
6852 colon (mri_control_stack->bottom);
6853
6854 input_line_pointer = s;
6855
6856 pop_mri_control ();
6857
6858 if (flag_mri)
6859 {
6860 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6861 ++input_line_pointer;
6862 }
6863
6864 demand_empty_rest_of_line ();
6865 }
6866
6867 /* Handle the MRI WHILE pseudo-op. */
6868
6869 static void
6870 s_mri_while (int qual)
6871 {
6872 char *s;
6873
6874 struct mri_control_info *n;
6875
6876 s = input_line_pointer;
6877 /* We only accept '*' as introduction of comments if preceded by white space
6878 or at first column of a line (I think this can't actually happen here?)
6879 This is important when assembling:
6880 while d0 <ne> 12(a0,d0*2) do
6881 while d0 <ne> #CONST*20 do. */
6882 while (! (is_end_of_line[(unsigned char) *s]
6883 || (flag_mri
6884 && *s == '*'
6885 && (s == input_line_pointer
6886 || *(s-1) == ' '
6887 || *(s-1) == '\t'))))
6888 s++;
6889 --s;
6890 while (*s == ' ' || *s == '\t')
6891 --s;
6892 if (s - input_line_pointer > 1
6893 && s[-1] == '.')
6894 s -= 2;
6895 if (s - input_line_pointer < 2
6896 || strncasecmp (s - 1, "DO", 2) != 0)
6897 {
6898 as_bad (_("missing do"));
6899 ignore_rest_of_line ();
6900 return;
6901 }
6902
6903 n = push_mri_control (mri_while);
6904
6905 colon (n->next);
6906
6907 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6908 s[1] == '.' ? s[2] : '\0');
6909
6910 input_line_pointer = s + 1;
6911 if (*input_line_pointer == '.')
6912 input_line_pointer += 2;
6913
6914 if (flag_mri)
6915 {
6916 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6917 ++input_line_pointer;
6918 }
6919
6920 demand_empty_rest_of_line ();
6921 }
6922
6923 /* Handle the MRI ENDW pseudo-op. */
6924
6925 static void
6926 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6927 {
6928 char *buf;
6929
6930 if (mri_control_stack == NULL
6931 || mri_control_stack->type != mri_while)
6932 {
6933 as_bad (_("endw without while"));
6934 ignore_rest_of_line ();
6935 return;
6936 }
6937
6938 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6939 sprintf (buf, "bra %s", mri_control_stack->next);
6940 mri_assemble (buf);
6941 free (buf);
6942
6943 colon (mri_control_stack->bottom);
6944
6945 pop_mri_control ();
6946
6947 if (flag_mri)
6948 {
6949 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6950 ++input_line_pointer;
6951 }
6952
6953 demand_empty_rest_of_line ();
6954 }
6955 \f
6956 /* Parse a .cpu directive. */
6957
6958 static void
6959 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6960 {
6961 char saved_char;
6962 char *name;
6963
6964 if (initialized)
6965 {
6966 as_bad (_("already assembled instructions"));
6967 ignore_rest_of_line ();
6968 return;
6969 }
6970
6971 name = input_line_pointer;
6972 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6973 input_line_pointer++;
6974 saved_char = *input_line_pointer;
6975 *input_line_pointer = 0;
6976
6977 m68k_set_cpu (name, 1, 0);
6978
6979 *input_line_pointer = saved_char;
6980 demand_empty_rest_of_line ();
6981 return;
6982 }
6983
6984 /* Parse a .arch directive. */
6985
6986 static void
6987 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6988 {
6989 char saved_char;
6990 char *name;
6991
6992 if (initialized)
6993 {
6994 as_bad (_("already assembled instructions"));
6995 ignore_rest_of_line ();
6996 return;
6997 }
6998
6999 name = input_line_pointer;
7000 while (*input_line_pointer && *input_line_pointer != ','
7001 && !ISSPACE (*input_line_pointer))
7002 input_line_pointer++;
7003 saved_char = *input_line_pointer;
7004 *input_line_pointer = 0;
7005
7006 if (m68k_set_arch (name, 1, 0))
7007 {
7008 /* Scan extensions. */
7009 do
7010 {
7011 *input_line_pointer++ = saved_char;
7012 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7013 break;
7014 name = input_line_pointer;
7015 while (*input_line_pointer && *input_line_pointer != ','
7016 && !ISSPACE (*input_line_pointer))
7017 input_line_pointer++;
7018 saved_char = *input_line_pointer;
7019 *input_line_pointer = 0;
7020 }
7021 while (m68k_set_extension (name, 1, 0));
7022 }
7023
7024 *input_line_pointer = saved_char;
7025 demand_empty_rest_of_line ();
7026 return;
7027 }
7028 \f
7029 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7030 if none is found, the caller is responsible for emitting an error
7031 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7032 cpu name, if it begins with a '6' (possibly skipping an intervening
7033 'c'. We also allow a 'c' in the same place. if NEGATED is
7034 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7035 the option is indeed negated. */
7036
7037 static const struct m68k_cpu *
7038 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7039 int allow_m, int *negated)
7040 {
7041 /* allow negated value? */
7042 if (negated)
7043 {
7044 *negated = 0;
7045
7046 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7047 {
7048 arg += 3;
7049 *negated = 1;
7050 }
7051 }
7052
7053 /* Remove 'm' or 'mc' prefix from 68k variants. */
7054 if (allow_m)
7055 {
7056 if (arg[0] == 'm')
7057 {
7058 if (arg[1] == '6')
7059 arg += 1;
7060 else if (arg[1] == 'c' && arg[2] == '6')
7061 arg += 2;
7062 }
7063 }
7064 else if (arg[0] == 'c' && arg[1] == '6')
7065 arg += 1;
7066
7067 for (; table->name; table++)
7068 if (!strcmp (arg, table->name))
7069 {
7070 if (table->alias < -1 || table->alias > 1)
7071 as_bad (_("`%s' is deprecated, use `%s'"),
7072 table->name, table[table->alias < 0 ? 1 : -1].name);
7073 return table;
7074 }
7075 return 0;
7076 }
7077
7078 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7079
7080 static int
7081 m68k_set_cpu (char const *name, int allow_m, int silent)
7082 {
7083 const struct m68k_cpu *cpu;
7084
7085 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7086
7087 if (!cpu)
7088 {
7089 if (!silent)
7090 as_bad (_("cpu `%s' unrecognized"), name);
7091 return 0;
7092 }
7093
7094 if (selected_cpu && selected_cpu != cpu)
7095 {
7096 as_bad (_("already selected `%s' processor"),
7097 selected_cpu->name);
7098 return 0;
7099 }
7100 selected_cpu = cpu;
7101 return 1;
7102 }
7103
7104 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7105
7106 static int
7107 m68k_set_arch (char const *name, int allow_m, int silent)
7108 {
7109 const struct m68k_cpu *arch;
7110
7111 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7112
7113 if (!arch)
7114 {
7115 if (!silent)
7116 as_bad (_("architecture `%s' unrecognized"), name);
7117 return 0;
7118 }
7119
7120 if (selected_arch && selected_arch != arch)
7121 {
7122 as_bad (_("already selected `%s' architecture"),
7123 selected_arch->name);
7124 return 0;
7125 }
7126
7127 selected_arch = arch;
7128 return 1;
7129 }
7130
7131 /* Set the architecture extension, issuing errors if it is
7132 unrecognized, or invalid */
7133
7134 static int
7135 m68k_set_extension (char const *name, int allow_m, int silent)
7136 {
7137 int negated;
7138 const struct m68k_cpu *ext;
7139
7140 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7141
7142 if (!ext)
7143 {
7144 if (!silent)
7145 as_bad (_("extension `%s' unrecognized"), name);
7146 return 0;
7147 }
7148
7149 if (negated)
7150 not_current_architecture |= ext->arch;
7151 else
7152 current_architecture |= ext->arch;
7153 return 1;
7154 }
7155
7156 /* md_parse_option
7157 Invocation line includes a switch not recognized by the base assembler.
7158 */
7159
7160 #ifdef OBJ_ELF
7161 const char *md_shortopts = "lSA:m:kQ:V";
7162 #else
7163 const char *md_shortopts = "lSA:m:k";
7164 #endif
7165
7166 struct option md_longopts[] = {
7167 #define OPTION_PIC (OPTION_MD_BASE)
7168 {"pic", no_argument, NULL, OPTION_PIC},
7169 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7170 {"register-prefix-optional", no_argument, NULL,
7171 OPTION_REGISTER_PREFIX_OPTIONAL},
7172 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7173 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7174 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7175 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7176 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7177 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7178 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7179 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7180 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7181 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7182 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7183 {"pcrel", no_argument, NULL, OPTION_PCREL},
7184 {NULL, no_argument, NULL, 0}
7185 };
7186 size_t md_longopts_size = sizeof (md_longopts);
7187
7188 int
7189 md_parse_option (int c, char *arg)
7190 {
7191 switch (c)
7192 {
7193 case 'l': /* -l means keep external to 2 bit offset
7194 rather than 16 bit one. */
7195 flag_short_refs = 1;
7196 break;
7197
7198 case 'S': /* -S means that jbsr's always turn into
7199 jsr's. */
7200 flag_long_jumps = 1;
7201 break;
7202
7203 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7204 branches into absolute jumps. */
7205 flag_keep_pcrel = 1;
7206 break;
7207
7208 case OPTION_PIC:
7209 case 'k':
7210 flag_want_pic = 1;
7211 break; /* -pic, Position Independent Code. */
7212
7213 case OPTION_REGISTER_PREFIX_OPTIONAL:
7214 flag_reg_prefix_optional = 1;
7215 reg_prefix_optional_seen = 1;
7216 break;
7217
7218 /* -V: SVR4 argument to print version ID. */
7219 case 'V':
7220 print_version_id ();
7221 break;
7222
7223 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7224 should be emitted or not. FIXME: Not implemented. */
7225 case 'Q':
7226 break;
7227
7228 case OPTION_BITWISE_OR:
7229 {
7230 char *n, *t;
7231 const char *s;
7232
7233 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7234 t = n;
7235 for (s = m68k_comment_chars; *s != '\0'; s++)
7236 if (*s != '|')
7237 *t++ = *s;
7238 *t = '\0';
7239 m68k_comment_chars = n;
7240 }
7241 break;
7242
7243 case OPTION_BASE_SIZE_DEFAULT_16:
7244 m68k_index_width_default = SIZE_WORD;
7245 break;
7246
7247 case OPTION_BASE_SIZE_DEFAULT_32:
7248 m68k_index_width_default = SIZE_LONG;
7249 break;
7250
7251 case OPTION_DISP_SIZE_DEFAULT_16:
7252 m68k_rel32 = 0;
7253 m68k_rel32_from_cmdline = 1;
7254 break;
7255
7256 case OPTION_DISP_SIZE_DEFAULT_32:
7257 m68k_rel32 = 1;
7258 m68k_rel32_from_cmdline = 1;
7259 break;
7260
7261 case 'A':
7262 #if WARN_DEPRECATED
7263 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7264 arg, arg));
7265 #endif
7266 /* Intentional fall-through. */
7267 case 'm':
7268 if (!strncmp (arg, "arch=", 5))
7269 m68k_set_arch (arg + 5, 1, 0);
7270 else if (!strncmp (arg, "cpu=", 4))
7271 m68k_set_cpu (arg + 4, 1, 0);
7272 else if (m68k_set_extension (arg, 0, 1))
7273 ;
7274 else if (m68k_set_arch (arg, 0, 1))
7275 ;
7276 else if (m68k_set_cpu (arg, 0, 1))
7277 ;
7278 else
7279 return 0;
7280 break;
7281
7282 default:
7283 return 0;
7284 }
7285
7286 return 1;
7287 }
7288
7289 /* Setup tables from the selected arch and/or cpu */
7290
7291 static void
7292 m68k_init_arch (void)
7293 {
7294 if (not_current_architecture & current_architecture)
7295 {
7296 as_bad (_("architecture features both enabled and disabled"));
7297 not_current_architecture &= ~current_architecture;
7298 }
7299 if (selected_arch)
7300 {
7301 current_architecture |= selected_arch->arch;
7302 control_regs = selected_arch->control_regs;
7303 }
7304 else
7305 current_architecture |= selected_cpu->arch;
7306
7307 current_architecture &= ~not_current_architecture;
7308
7309 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7310 {
7311 /* Determine which float is really meant. */
7312 if (current_architecture & (m68k_mask & ~m68881))
7313 current_architecture ^= cfloat;
7314 else
7315 current_architecture ^= m68881;
7316 }
7317
7318 if (selected_cpu)
7319 {
7320 control_regs = selected_cpu->control_regs;
7321 if (current_architecture & ~selected_cpu->arch)
7322 {
7323 as_bad (_("selected processor does not have all features of selected architecture"));
7324 current_architecture
7325 = selected_cpu->arch & ~not_current_architecture;
7326 }
7327 }
7328
7329 if ((current_architecture & m68k_mask)
7330 && (current_architecture & ~m68k_mask))
7331 {
7332 as_bad (_ ("m68k and cf features both selected"));
7333 if (current_architecture & m68k_mask)
7334 current_architecture &= m68k_mask;
7335 else
7336 current_architecture &= ~m68k_mask;
7337 }
7338
7339 /* Permit m68881 specification with all cpus; those that can't work
7340 with a coprocessor could be doing emulation. */
7341 if (current_architecture & m68851)
7342 {
7343 if (current_architecture & m68040)
7344 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7345 }
7346 /* What other incompatibilities could we check for? */
7347
7348 if (cpu_of_arch (current_architecture) < m68020
7349 || arch_coldfire_p (current_architecture))
7350 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7351
7352 initialized = 1;
7353 }
7354
7355 void
7356 md_show_usage (FILE *stream)
7357 {
7358 const char *default_cpu = TARGET_CPU;
7359 int i;
7360 unsigned int default_arch;
7361
7362 /* Get the canonical name for the default target CPU. */
7363 if (*default_cpu == 'm')
7364 default_cpu++;
7365 for (i = 0; m68k_cpus[i].name; i++)
7366 {
7367 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7368 {
7369 default_arch = m68k_cpus[i].arch;
7370 while (m68k_cpus[i].alias > 0)
7371 i--;
7372 while (m68k_cpus[i].alias < 0)
7373 i++;
7374 default_cpu = m68k_cpus[i].name;
7375 }
7376 }
7377
7378 fprintf (stream, _("\
7379 -march=<arch> set architecture\n\
7380 -mcpu=<cpu> set cpu [default %s]\n\
7381 "), default_cpu);
7382 for (i = 0; m68k_extensions[i].name; i++)
7383 fprintf (stream, _("\
7384 -m[no-]%-16s enable/disable%s architecture extension\n\
7385 "), m68k_extensions[i].name,
7386 m68k_extensions[i].alias > 0 ? " ColdFire"
7387 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7388
7389 fprintf (stream, _("\
7390 -l use 1 word for refs to undefined symbols [default 2]\n\
7391 -pic, -k generate position independent code\n\
7392 -S turn jbsr into jsr\n\
7393 --pcrel never turn PC-relative branches into absolute jumps\n\
7394 --register-prefix-optional\n\
7395 recognize register names without prefix character\n\
7396 --bitwise-or do not treat `|' as a comment character\n\
7397 --base-size-default-16 base reg without size is 16 bits\n\
7398 --base-size-default-32 base reg without size is 32 bits (default)\n\
7399 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7400 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7401 "));
7402
7403 fprintf (stream, _("Architecture variants are: "));
7404 for (i = 0; m68k_archs[i].name; i++)
7405 {
7406 if (i)
7407 fprintf (stream, " | ");
7408 fprintf (stream, m68k_archs[i].name);
7409 }
7410 fprintf (stream, "\n");
7411
7412 fprintf (stream, _("Processor variants are: "));
7413 for (i = 0; m68k_cpus[i].name; i++)
7414 {
7415 if (i)
7416 fprintf (stream, " | ");
7417 fprintf (stream, m68k_cpus[i].name);
7418 }
7419 fprintf (stream, _("\n"));
7420 }
7421 \f
7422 #ifdef TEST2
7423
7424 /* TEST2: Test md_assemble() */
7425 /* Warning, this routine probably doesn't work anymore. */
7426 int
7427 main (void)
7428 {
7429 struct m68k_it the_ins;
7430 char buf[120];
7431 char *cp;
7432 int n;
7433
7434 m68k_ip_begin ();
7435 for (;;)
7436 {
7437 if (!gets (buf) || !*buf)
7438 break;
7439 if (buf[0] == '|' || buf[1] == '.')
7440 continue;
7441 for (cp = buf; *cp; cp++)
7442 if (*cp == '\t')
7443 *cp = ' ';
7444 if (is_label (buf))
7445 continue;
7446 memset (&the_ins, '\0', sizeof (the_ins));
7447 m68k_ip (&the_ins, buf);
7448 if (the_ins.error)
7449 {
7450 printf (_("Error %s in %s\n"), the_ins.error, buf);
7451 }
7452 else
7453 {
7454 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7455 for (n = 0; n < the_ins.numo; n++)
7456 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7457 printf (" ");
7458 print_the_insn (&the_ins.opcode[0], stdout);
7459 (void) putchar ('\n');
7460 }
7461 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7462 {
7463 if (the_ins.operands[n].error)
7464 {
7465 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7466 continue;
7467 }
7468 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7469 the_ins.operands[n].reg);
7470 if (the_ins.operands[n].b_const)
7471 printf ("Constant: '%.*s', ",
7472 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7473 the_ins.operands[n].b_const);
7474 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7475 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7476 if (the_ins.operands[n].b_iadd)
7477 printf ("Iadd: '%.*s',",
7478 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7479 the_ins.operands[n].b_iadd);
7480 putchar ('\n');
7481 }
7482 }
7483 m68k_ip_end ();
7484 return 0;
7485 }
7486
7487 int
7488 is_label (char *str)
7489 {
7490 while (*str == ' ')
7491 str++;
7492 while (*str && *str != ' ')
7493 str++;
7494 if (str[-1] == ':' || str[1] == '=')
7495 return 1;
7496 return 0;
7497 }
7498
7499 #endif
7500
7501 /* Possible states for relaxation:
7502
7503 0 0 branch offset byte (bra, etc)
7504 0 1 word
7505 0 2 long
7506
7507 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7508 1 1 word
7509 1 2 long
7510
7511 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7512 2 1 word-long
7513 2 2 long-word
7514 2 3 long-long
7515
7516 */
7517
7518 /* We have no need to default values of symbols. */
7519
7520 symbolS *
7521 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7522 {
7523 return 0;
7524 }
7525
7526 /* Round up a section size to the appropriate boundary. */
7527 valueT
7528 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7529 {
7530 #ifdef OBJ_AOUT
7531 /* For a.out, force the section size to be aligned. If we don't do
7532 this, BFD will align it for us, but it will not write out the
7533 final bytes of the section. This may be a bug in BFD, but it is
7534 easier to fix it here since that is how the other a.out targets
7535 work. */
7536 int align;
7537
7538 align = bfd_get_section_alignment (stdoutput, segment);
7539 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7540 #endif
7541
7542 return size;
7543 }
7544
7545 /* Exactly what point is a PC-relative offset relative TO?
7546 On the 68k, it is relative to the address of the first extension
7547 word. The difference between the addresses of the offset and the
7548 first extension word is stored in fx_pcrel_adjust. */
7549 long
7550 md_pcrel_from (fixS *fixP)
7551 {
7552 int adjust;
7553
7554 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7555 sign extend the value here. */
7556 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7557 if (adjust == 64)
7558 adjust = -1;
7559 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7560 }
7561
7562 #ifdef OBJ_ELF
7563 void
7564 m68k_elf_final_processing (void)
7565 {
7566 unsigned flags = 0;
7567
7568 if (arch_coldfire_fpu (current_architecture))
7569 flags |= EF_M68K_CFV4E;
7570 /* Set file-specific flags if this is a cpu32 processor. */
7571 if (cpu_of_arch (current_architecture) & cpu32)
7572 flags |= EF_M68K_CPU32;
7573 else if (cpu_of_arch (current_architecture) & fido_a)
7574 flags |= EF_M68K_FIDO;
7575 else if ((cpu_of_arch (current_architecture) & m68000up)
7576 && !(cpu_of_arch (current_architecture) & m68020up))
7577 flags |= EF_M68K_M68000;
7578
7579 if (current_architecture & mcfisa_a)
7580 {
7581 static const unsigned isa_features[][2] =
7582 {
7583 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7584 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7585 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7586 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7587 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7588 {0,0},
7589 };
7590 static const unsigned mac_features[][2] =
7591 {
7592 {EF_M68K_CF_MAC, mcfmac},
7593 {EF_M68K_CF_EMAC, mcfemac},
7594 {0,0},
7595 };
7596 unsigned ix;
7597 unsigned pattern;
7598
7599 pattern = (current_architecture
7600 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7601 for (ix = 0; isa_features[ix][1]; ix++)
7602 {
7603 if (pattern == isa_features[ix][1])
7604 {
7605 flags |= isa_features[ix][0];
7606 break;
7607 }
7608 }
7609 if (!isa_features[ix][1])
7610 {
7611 cf_bad:
7612 as_warn (_("Not a defined coldfire architecture"));
7613 }
7614 else
7615 {
7616 if (current_architecture & cfloat)
7617 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7618
7619 pattern = current_architecture & (mcfmac|mcfemac);
7620 if (pattern)
7621 {
7622 for (ix = 0; mac_features[ix][1]; ix++)
7623 {
7624 if (pattern == mac_features[ix][1])
7625 {
7626 flags |= mac_features[ix][0];
7627 break;
7628 }
7629 }
7630 if (!mac_features[ix][1])
7631 goto cf_bad;
7632 }
7633 }
7634 }
7635 elf_elfheader (stdoutput)->e_flags |= flags;
7636 }
7637 #endif
7638
7639 int
7640 tc_m68k_regname_to_dw2regnum (char *regname)
7641 {
7642 unsigned int regnum;
7643 static const char *const regnames[] =
7644 {
7645 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7646 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7647 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7648 "pc"
7649 };
7650
7651 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7652 if (strcmp (regname, regnames[regnum]) == 0)
7653 return regnum;
7654
7655 return -1;
7656 }
7657
7658 void
7659 tc_m68k_frame_initial_instructions (void)
7660 {
7661 static int sp_regno = -1;
7662
7663 if (sp_regno < 0)
7664 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7665
7666 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7667 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7668 }
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