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Rearrange symbol_create parameters
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
30 #include "elf/m68k.h"
31
32 static void m68k_elf_cons (int);
33 static void m68k_elf_gnu_attribute (int);
34
35 /* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39 #if defined (TE_SVR4) || defined (TE_DELTA)
40 const char *m68k_comment_chars = "|#";
41 #else
42 const char *m68k_comment_chars = "|";
43 #endif
44
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars[] = "#*";
53
54 const char line_separator_chars[] = ";";
55
56 /* Chars that can be used to separate mant from exp in floating point nums. */
57 const char EXP_CHARS[] = "eE";
58
59 /* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
62 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
68 /* Are we trying to generate PIC code? If so, absolute references
69 ought to be made into linkage table references or pc-relative
70 references. Not implemented. For ELF there are other means
71 to denote pic relocations. */
72 int flag_want_pic;
73
74 static int flag_short_refs; /* -l option. */
75 static int flag_long_jumps; /* -S option. */
76 static int flag_keep_pcrel; /* --pcrel option. */
77
78 #ifdef REGISTER_PREFIX_OPTIONAL
79 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
80 #else
81 int flag_reg_prefix_optional;
82 #endif
83
84 /* Whether --register-prefix-optional was used on the command line. */
85 static int reg_prefix_optional_seen;
86
87 /* The floating point coprocessor to use by default. */
88 static enum m68k_register m68k_float_copnum = COP1;
89
90 /* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92 static int m68k_abspcadd;
93
94 /* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96 static int m68k_quick = 1;
97
98 /* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
100 be 32 bits. */
101 static int m68k_rel32 = 1;
102
103 /* This is non-zero if m68k_rel32 was set from the command line. */
104 static int m68k_rel32_from_cmdline;
105
106 /* The default width to use for an index register when using a base
107 displacement. */
108 static enum m68k_size m68k_index_width_default = SIZE_LONG;
109
110 /* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
112 label. */
113 struct label_line
114 {
115 struct label_line *next;
116 symbolS *label;
117 const char *file;
118 unsigned int line;
119 int text;
120 };
121
122 /* The list of labels. */
123
124 static struct label_line *labels;
125
126 /* The current label. */
127
128 static struct label_line *current_label;
129
130 /* Pointer to list holding the opcodes sorted by name. */
131 static struct m68k_opcode const ** m68k_sorted_opcodes;
132
133 /* It's an arbitrary name: This means I don't approve of it.
134 See flames below. */
135 static struct obstack robyn;
136
137 struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148 #define gettwo(x) (((x)->m_opcode)&0xffff)
149
150 static const enum m68k_register m68000_ctrl[] = { 0 };
151 static const enum m68k_register m68010_ctrl[] = {
152 SFC, DFC, USP, VBR,
153 0
154 };
155 static const enum m68k_register m68020_ctrl[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158 };
159 static const enum m68k_register m68040_ctrl[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163 };
164 static const enum m68k_register m68060_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168 };
169 static const enum m68k_register mcf_ctrl[] = {
170 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
171 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
172 0
173 };
174 static const enum m68k_register mcf51_ctrl[] = {
175 VBR, CPUCR,
176 0
177 };
178 static const enum m68k_register mcf5206_ctrl[] = {
179 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
180 0
181 };
182 static const enum m68k_register mcf5208_ctrl[] = {
183 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
184 0
185 };
186 static const enum m68k_register mcf5210a_ctrl[] = {
187 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
188 0
189 };
190 static const enum m68k_register mcf5213_ctrl[] = {
191 VBR, RAMBAR, RAMBAR1, FLASHBAR,
192 0
193 };
194 static const enum m68k_register mcf5216_ctrl[] = {
195 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
196 0
197 };
198 static const enum m68k_register mcf5221x_ctrl[] = {
199 VBR, FLASHBAR, RAMBAR, RAMBAR1,
200 0
201 };
202 static const enum m68k_register mcf52223_ctrl[] = {
203 VBR, FLASHBAR, RAMBAR, RAMBAR1,
204 0
205 };
206 static const enum m68k_register mcf52235_ctrl[] = {
207 VBR, FLASHBAR, RAMBAR, RAMBAR1,
208 0
209 };
210 static const enum m68k_register mcf5225_ctrl[] = {
211 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
212 0
213 };
214 static const enum m68k_register mcf52259_ctrl[] = {
215 VBR, FLASHBAR, RAMBAR, RAMBAR1,
216 0
217 };
218 static const enum m68k_register mcf52277_ctrl[] = {
219 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
220 0
221 };
222 static const enum m68k_register mcf5235_ctrl[] = {
223 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
224 0
225 };
226 static const enum m68k_register mcf5249_ctrl[] = {
227 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
228 0
229 };
230 static const enum m68k_register mcf5250_ctrl[] = {
231 VBR,
232 0
233 };
234 static const enum m68k_register mcf5253_ctrl[] = {
235 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
236 0
237 };
238 static const enum m68k_register mcf5271_ctrl[] = {
239 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
240 0
241 };
242 static const enum m68k_register mcf5272_ctrl[] = {
243 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
244 0
245 };
246 static const enum m68k_register mcf5275_ctrl[] = {
247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
248 0
249 };
250 static const enum m68k_register mcf5282_ctrl[] = {
251 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
252 0
253 };
254 static const enum m68k_register mcf53017_ctrl[] = {
255 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
256 0
257 };
258 static const enum m68k_register mcf5307_ctrl[] = {
259 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
260 0
261 };
262 static const enum m68k_register mcf5329_ctrl[] = {
263 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
264 0
265 };
266 static const enum m68k_register mcf5373_ctrl[] = {
267 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
268 0
269 };
270 static const enum m68k_register mcfv4e_ctrl[] = {
271 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
272 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
273 MBAR, SECMBAR,
274 MPCR /* Multiprocessor Control register */,
275 EDRAMBAR /* Embedded DRAM Base Address Register */,
276 /* Permutation control registers. */
277 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
278 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
279 /* Legacy names */
280 TC /* ASID */, BUSCR /* MMUBAR */,
281 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
282 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
283 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
284 0
285 };
286 static const enum m68k_register mcf5407_ctrl[] = {
287 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
288 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
289 /* Legacy names */
290 TC /* ASID */,
291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
292 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
293 0
294 };
295 static const enum m68k_register mcf54418_ctrl[] = {
296 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
297 VBR, PC, RAMBAR1,
298 /* Legacy names */
299 TC /* ASID */, BUSCR /* MMUBAR */,
300 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
301 RAMBAR /* RAMBAR1 */,
302 0
303 };
304 static const enum m68k_register mcf54455_ctrl[] = {
305 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
306 VBR, PC, RAMBAR1,
307 /* Legacy names */
308 TC /* ASID */, BUSCR /* MMUBAR */,
309 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
310 RAMBAR /* RAMBAR1 */,
311 0
312 };
313 static const enum m68k_register mcf5475_ctrl[] = {
314 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
315 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
316 /* Legacy names */
317 TC /* ASID */, BUSCR /* MMUBAR */,
318 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
319 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
320 0
321 };
322 static const enum m68k_register mcf5485_ctrl[] = {
323 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
324 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
325 /* Legacy names */
326 TC /* ASID */, BUSCR /* MMUBAR */,
327 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
328 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
329 0
330 };
331 static const enum m68k_register fido_ctrl[] = {
332 SFC, DFC, USP, VBR, CAC, MBO,
333 0
334 };
335 #define cpu32_ctrl m68010_ctrl
336
337 static const enum m68k_register *control_regs;
338
339 /* Internal form of a 68020 instruction. */
340 struct m68k_it
341 {
342 const char *error;
343 const char *args; /* List of opcode info. */
344 int numargs;
345
346 int numo; /* Number of shorts in opcode. */
347 short opcode[11];
348
349 struct m68k_op operands[6];
350
351 int nexp; /* Number of exprs in use. */
352 struct m68k_exp exprs[4];
353
354 int nfrag; /* Number of frags we have to produce. */
355 struct
356 {
357 int fragoff; /* Where in the current opcode the frag ends. */
358 symbolS *fadd;
359 offsetT foff;
360 int fragty;
361 }
362 fragb[4];
363
364 int nrel; /* Num of reloc structs in use. */
365 struct
366 {
367 int n;
368 expressionS exp;
369 char wid;
370 char pcrel;
371 /* In a pc relative address the difference between the address
372 of the offset and the address that the offset is relative
373 to. This depends on the addressing mode. Basically this
374 is the value to put in the offset field to address the
375 first byte of the offset, without regarding the special
376 significance of some values (in the branch instruction, for
377 example). */
378 int pcrel_fix;
379 /* Whether this expression needs special pic relocation, and if
380 so, which. */
381 enum pic_relocation pic_reloc;
382 }
383 reloc[5]; /* Five is enough??? */
384 };
385
386 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
387 #define float_of_arch(x) ((x) & mfloat)
388 #define mmu_of_arch(x) ((x) & mmmu)
389 #define arch_coldfire_p(x) ((x) & mcfisa_a)
390 #define arch_coldfire_fpu(x) ((x) & cfloat)
391
392 /* Macros for determining if cpu supports a specific addressing mode. */
393 #define HAVE_LONG_DISP(x) \
394 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
395 #define HAVE_LONG_CALL(x) \
396 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
397 #define HAVE_LONG_COND(x) \
398 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
399 #define HAVE_LONG_BRANCH(x) \
400 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
401 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
402
403 static struct m68k_it the_ins; /* The instruction being assembled. */
404
405 #define op(ex) ((ex)->exp.X_op)
406 #define adds(ex) ((ex)->exp.X_add_symbol)
407 #define subs(ex) ((ex)->exp.X_op_symbol)
408 #define offs(ex) ((ex)->exp.X_add_number)
409
410 /* Macros for adding things to the m68k_it struct. */
411 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
412
413 /* Like addword, but goes BEFORE general operands. */
414
415 static void
416 insop (int w, const struct m68k_incant *opcode)
417 {
418 int z;
419 for (z = the_ins.numo; z > opcode->m_codenum; --z)
420 the_ins.opcode[z] = the_ins.opcode[z - 1];
421 for (z = 0; z < the_ins.nrel; z++)
422 the_ins.reloc[z].n += 2;
423 for (z = 0; z < the_ins.nfrag; z++)
424 the_ins.fragb[z].fragoff++;
425 the_ins.opcode[opcode->m_codenum] = w;
426 the_ins.numo++;
427 }
428
429 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
430 Blecch. */
431 static void
432 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
433 {
434 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
435 ? the_ins.numo * 2 - 1
436 : (width == 'b'
437 ? the_ins.numo * 2 + 1
438 : the_ins.numo * 2));
439 the_ins.reloc[the_ins.nrel].exp = exp->exp;
440 the_ins.reloc[the_ins.nrel].wid = width;
441 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
442 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
443 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
444 }
445
446 /* Cause an extra frag to be generated here, inserting up to 10 bytes
447 (that value is chosen in the frag_var call in md_assemble). TYPE
448 is the subtype of the frag to be generated; its primary type is
449 rs_machine_dependent.
450
451 The TYPE parameter is also used by md_convert_frag_1 and
452 md_estimate_size_before_relax. The appropriate type of fixup will
453 be emitted by md_convert_frag_1.
454
455 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
456 static void
457 add_frag (symbolS *add, offsetT off, int type)
458 {
459 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
460 the_ins.fragb[the_ins.nfrag].fadd = add;
461 the_ins.fragb[the_ins.nfrag].foff = off;
462 the_ins.fragb[the_ins.nfrag++].fragty = type;
463 }
464
465 #define isvar(ex) \
466 (op (ex) != O_constant && op (ex) != O_big)
467
468 static char *crack_operand (char *str, struct m68k_op *opP);
469 static int get_num (struct m68k_exp *exp, int ok);
470 static int reverse_16_bits (int in);
471 static int reverse_8_bits (int in);
472 static void install_gen_operand (int mode, int val);
473 static void install_operand (int mode, int val);
474 static void s_bss (int);
475 static void s_data1 (int);
476 static void s_data2 (int);
477 static void s_even (int);
478 static void s_proc (int);
479 static void s_chip (int);
480 static void s_fopt (int);
481 static void s_opt (int);
482 static void s_reg (int);
483 static void s_restore (int);
484 static void s_save (int);
485 static void s_mri_if (int);
486 static void s_mri_else (int);
487 static void s_mri_endi (int);
488 static void s_mri_break (int);
489 static void s_mri_next (int);
490 static void s_mri_for (int);
491 static void s_mri_endf (int);
492 static void s_mri_repeat (int);
493 static void s_mri_until (int);
494 static void s_mri_while (int);
495 static void s_mri_endw (int);
496 static void s_m68k_cpu (int);
497 static void s_m68k_arch (int);
498
499 struct m68k_cpu
500 {
501 unsigned long arch; /* Architecture features. */
502 const enum m68k_register *control_regs; /* Control regs on chip */
503 const char *name; /* Name */
504 int alias; /* Alias for a canonical name. If 1, then
505 succeeds canonical name, if -1 then
506 succeeds canonical name, if <-1 ||>1 this is a
507 deprecated name, and the next/previous name
508 should be used. */
509 };
510
511 /* We hold flags for features explicitly enabled and explicitly
512 disabled. */
513 static int current_architecture;
514 static int not_current_architecture;
515 static const struct m68k_cpu *selected_arch;
516 static const struct m68k_cpu *selected_cpu;
517 static int initialized;
518
519 /* Architecture models. */
520 static const struct m68k_cpu m68k_archs[] =
521 {
522 {m68000, m68000_ctrl, "68000", 0},
523 {m68010, m68010_ctrl, "68010", 0},
524 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
525 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
526 {m68040, m68040_ctrl, "68040", 0},
527 {m68060, m68060_ctrl, "68060", 0},
528 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
529 {fido_a, fido_ctrl, "fidoa", 0},
530 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
531 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
532 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
533 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
534 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
535 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
536 {0,0,NULL, 0}
537 };
538
539 /* For -mno-mac we want to turn off all types of mac. */
540 static const unsigned no_mac = mcfmac | mcfemac;
541
542 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
543 for either. */
544 static const struct m68k_cpu m68k_extensions[] =
545 {
546 {m68851, NULL, "68851", -1},
547 {m68881, NULL, "68881", -1},
548 {m68881, NULL, "68882", -1},
549
550 {cfloat|m68881, NULL, "float", 0},
551
552 {mcfhwdiv, NULL, "div", 1},
553 {mcfusp, NULL, "usp", 1},
554 {mcfmac, (void *)&no_mac, "mac", 1},
555 {mcfemac, NULL, "emac", 1},
556
557 {0,NULL,NULL, 0}
558 };
559
560 /* Processor list */
561 static const struct m68k_cpu m68k_cpus[] =
562 {
563 {m68000, m68000_ctrl, "68000", 0},
564 {m68000, m68000_ctrl, "68ec000", 1},
565 {m68000, m68000_ctrl, "68hc000", 1},
566 {m68000, m68000_ctrl, "68hc001", 1},
567 {m68000, m68000_ctrl, "68008", 1},
568 {m68000, m68000_ctrl, "68302", 1},
569 {m68000, m68000_ctrl, "68306", 1},
570 {m68000, m68000_ctrl, "68307", 1},
571 {m68000, m68000_ctrl, "68322", 1},
572 {m68000, m68000_ctrl, "68356", 1},
573 {m68010, m68010_ctrl, "68010", 0},
574 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
575 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
576 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
577 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
578 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
579 {m68040, m68040_ctrl, "68040", 0},
580 {m68040, m68040_ctrl, "68ec040", 1},
581 {m68060, m68060_ctrl, "68060", 0},
582 {m68060, m68060_ctrl, "68ec060", 1},
583
584 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
585 {cpu32|m68881, cpu32_ctrl, "68330", 1},
586 {cpu32|m68881, cpu32_ctrl, "68331", 1},
587 {cpu32|m68881, cpu32_ctrl, "68332", 1},
588 {cpu32|m68881, cpu32_ctrl, "68333", 1},
589 {cpu32|m68881, cpu32_ctrl, "68334", 1},
590 {cpu32|m68881, cpu32_ctrl, "68336", 1},
591 {cpu32|m68881, cpu32_ctrl, "68340", 1},
592 {cpu32|m68881, cpu32_ctrl, "68341", 1},
593 {cpu32|m68881, cpu32_ctrl, "68349", 1},
594 {cpu32|m68881, cpu32_ctrl, "68360", 1},
595
596 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
597 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
598 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
599 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
600 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
601 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
602 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
603 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
604 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
605 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
606 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
607 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
608
609 {mcfisa_a, mcf_ctrl, "5200", 0},
610 {mcfisa_a, mcf_ctrl, "5202", 1},
611 {mcfisa_a, mcf_ctrl, "5204", 1},
612 {mcfisa_a, mcf5206_ctrl, "5206", 1},
613
614 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
615
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
618
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
621
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
625
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
629
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
631
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
634
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
639
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
642
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
645
646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
651
652 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
653 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
654 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
655
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
662
663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
665
666 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
667
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
670
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
674 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
675
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
682 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
683
684 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
685
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
690
691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
694
695 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
696
697 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
698 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
699 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
700 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
701 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
702
703 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
704 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
705 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
706 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
707 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
708 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
709
710 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
711 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
712 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
713 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
714 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
715 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
716 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
717
718 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
719 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
720 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
721 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
725
726 {fido_a, fido_ctrl, "fidoa", 0},
727 {fido_a, fido_ctrl, "fido", 1},
728
729 {0,NULL,NULL, 0}
730 };
731
732 static const struct m68k_cpu *m68k_lookup_cpu
733 (const char *, const struct m68k_cpu *, int, int *);
734 static int m68k_set_arch (const char *, int, int);
735 static int m68k_set_cpu (const char *, int, int);
736 static int m68k_set_extension (const char *, int, int);
737 static void m68k_init_arch (void);
738
739 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
740 architecture and we have a lot of relaxation modes. */
741
742 /* Macros used in the relaxation code. */
743 #define TAB(x,y) (((x) << 2) + (y))
744 #define TABTYPE(x) ((x) >> 2)
745
746 /* Relaxation states. */
747 #define BYTE 0
748 #define SHORT 1
749 #define LONG 2
750 #define SZ_UNDEF 3
751
752 /* Here are all the relaxation modes we support. First we can relax ordinary
753 branches. On 68020 and higher and on CPU32 all branch instructions take
754 three forms, so on these CPUs all branches always remain as such. When we
755 have to expand to the LONG form on a 68000, though, we substitute an
756 absolute jump instead. This is a direct replacement for unconditional
757 branches and a branch over a jump for conditional branches. However, if the
758 user requires PIC and disables this with --pcrel, we can only relax between
759 BYTE and SHORT forms, punting if that isn't enough. This gives us four
760 different relaxation modes for branches: */
761
762 #define BRANCHBWL 0 /* Branch byte, word, or long. */
763 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
764 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
765 #define BRANCHBW 3 /* Branch byte or word. */
766
767 /* We also relax coprocessor branches and DBcc's. All CPUs that support
768 coprocessor branches support them in word and long forms, so we have only
769 one relaxation mode for them. DBcc's are word only on all CPUs. We can
770 relax them to the LONG form with a branch-around sequence. This sequence
771 can use a long branch (if available) or an absolute jump (if acceptable).
772 This gives us two relaxation modes. If long branches are not available and
773 absolute jumps are not acceptable, we don't relax DBcc's. */
774
775 #define FBRANCH 4 /* Coprocessor branch. */
776 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
777 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
778
779 /* That's all for instruction relaxation. However, we also relax PC-relative
780 operands. Specifically, we have three operand relaxation modes. On the
781 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
782 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
783 two. Also PC+displacement+index operands in their simple form (with a non-
784 suppressed index without memory indirection) are supported on all CPUs, but
785 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
786 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
787 form of the PC+displacement+index operand. Finally, some absolute operands
788 can be relaxed down to 16-bit PC-relative. */
789
790 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
791 #define PCINDEX 8 /* PC + displacement + index. */
792 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
793
794 /* This relaxation is required for branches where there is no long
795 branch and we are in pcrel mode. We generate a bne/beq pair. */
796 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
797 */
798
799 /* Note that calls to frag_var need to specify the maximum expansion
800 needed; this is currently 12 bytes for bne/beq pair. */
801 #define FRAG_VAR_SIZE 12
802
803 /* The fields are:
804 How far Forward this mode will reach:
805 How far Backward this mode will reach:
806 How many bytes this mode will add to the size of the frag
807 Which mode to go to if the offset won't fit in this one
808
809 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
810 relax_typeS md_relax_table[] =
811 {
812 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
813 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
814 { 0, 0, 4, 0 },
815 { 1, 1, 0, 0 },
816
817 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
818 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
819 { 0, 0, 4, 0 },
820 { 1, 1, 0, 0 },
821
822 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
823 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
824 { 0, 0, 6, 0 },
825 { 1, 1, 0, 0 },
826
827 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
828 { 0, 0, 2, 0 },
829 { 1, 1, 0, 0 },
830 { 1, 1, 0, 0 },
831
832 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
833 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
834 { 0, 0, 4, 0 },
835 { 1, 1, 0, 0 },
836
837 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
838 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
839 { 0, 0, 10, 0 },
840 { 1, 1, 0, 0 },
841
842 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
843 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
844 { 0, 0, 10, 0 },
845 { 1, 1, 0, 0 },
846
847 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
848 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
849 { 0, 0, 6, 0 },
850 { 1, 1, 0, 0 },
851
852 { 125, -130, 0, TAB (PCINDEX, SHORT) },
853 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
854 { 0, 0, 4, 0 },
855 { 1, 1, 0, 0 },
856
857 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
858 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
859 { 0, 0, 4, 0 },
860 { 1, 1, 0, 0 },
861
862 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
863 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
864 { 0, 0, 10, 0 },
865 { 1, 1, 0, 0 },
866 };
867
868 /* These are the machine dependent pseudo-ops. These are included so
869 the assembler can work on the output from the SUN C compiler, which
870 generates these. */
871
872 /* This table describes all the machine specific pseudo-ops the assembler
873 has to support. The fields are:
874 pseudo-op name without dot
875 function to call to execute this pseudo-op
876 Integer arg to pass to the function. */
877 const pseudo_typeS md_pseudo_table[] =
878 {
879 {"data1", s_data1, 0},
880 {"data2", s_data2, 0},
881 {"bss", s_bss, 0},
882 {"even", s_even, 0},
883 {"skip", s_space, 0},
884 {"proc", s_proc, 0},
885 {"align", s_align_bytes, 0},
886 {"swbeg", s_ignore, 0},
887 {"long", m68k_elf_cons, 4},
888 {"extend", float_cons, 'x'},
889 {"ldouble", float_cons, 'x'},
890
891 {"arch", s_m68k_arch, 0},
892 {"cpu", s_m68k_cpu, 0},
893 {"gnu_attribute", m68k_elf_gnu_attribute, 0},
894
895 /* The following pseudo-ops are supported for MRI compatibility. */
896 {"chip", s_chip, 0},
897 {"comline", s_space, 1},
898 {"fopt", s_fopt, 0},
899 {"mask2", s_ignore, 0},
900 {"opt", s_opt, 0},
901 {"reg", s_reg, 0},
902 {"restore", s_restore, 0},
903 {"save", s_save, 0},
904
905 {"if", s_mri_if, 0},
906 {"if.b", s_mri_if, 'b'},
907 {"if.w", s_mri_if, 'w'},
908 {"if.l", s_mri_if, 'l'},
909 {"else", s_mri_else, 0},
910 {"else.s", s_mri_else, 's'},
911 {"else.l", s_mri_else, 'l'},
912 {"endi", s_mri_endi, 0},
913 {"break", s_mri_break, 0},
914 {"break.s", s_mri_break, 's'},
915 {"break.l", s_mri_break, 'l'},
916 {"next", s_mri_next, 0},
917 {"next.s", s_mri_next, 's'},
918 {"next.l", s_mri_next, 'l'},
919 {"for", s_mri_for, 0},
920 {"for.b", s_mri_for, 'b'},
921 {"for.w", s_mri_for, 'w'},
922 {"for.l", s_mri_for, 'l'},
923 {"endf", s_mri_endf, 0},
924 {"repeat", s_mri_repeat, 0},
925 {"until", s_mri_until, 0},
926 {"until.b", s_mri_until, 'b'},
927 {"until.w", s_mri_until, 'w'},
928 {"until.l", s_mri_until, 'l'},
929 {"while", s_mri_while, 0},
930 {"while.b", s_mri_while, 'b'},
931 {"while.w", s_mri_while, 'w'},
932 {"while.l", s_mri_while, 'l'},
933 {"endw", s_mri_endw, 0},
934
935 {0, 0, 0}
936 };
937
938 /* The mote pseudo ops are put into the opcode table, since they
939 don't start with a . they look like opcodes to gas. */
940
941 const pseudo_typeS mote_pseudo_table[] =
942 {
943
944 {"dcl", cons, 4},
945 {"dc", cons, 2},
946 {"dcw", cons, 2},
947 {"dcb", cons, 1},
948
949 {"dsl", s_space, 4},
950 {"ds", s_space, 2},
951 {"dsw", s_space, 2},
952 {"dsb", s_space, 1},
953
954 {"xdef", s_globl, 0},
955 {"align", s_align_bytes, 0},
956 {0, 0, 0}
957 };
958
959 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
960 gives identical results to a 32-bit host. */
961 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
962 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
963
964 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
965 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
966 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
967 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
968
969 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
970 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
971 #define islong(x) (1)
972
973 static char notend_table[256];
974 static char alt_notend_table[256];
975 #define notend(s) \
976 (! (notend_table[(unsigned char) *s] \
977 || (*s == ':' \
978 && alt_notend_table[(unsigned char) s[1]])))
979
980
981 /* Return zero if the reference to SYMBOL from within the same segment may
982 be relaxed. */
983
984 /* On an ELF system, we can't relax an externally visible symbol,
985 because it may be overridden by a shared library. However, if
986 TARGET_OS is "elf", then we presume that we are assembling for an
987 embedded system, in which case we don't have to worry about shared
988 libraries, and we can relax any external sym. */
989
990 #define relaxable_symbol(symbol) \
991 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
992 || S_IS_WEAK (symbol)))
993
994 /* Compute the relocation code for a fixup of SIZE bytes, using pc
995 relative relocation if PCREL is non-zero. PIC says whether a special
996 pic relocation was requested. */
997
998 static bfd_reloc_code_real_type
999 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
1000 {
1001 switch (pic)
1002 {
1003 case pic_got_pcrel:
1004 switch (size)
1005 {
1006 case 1:
1007 return BFD_RELOC_8_GOT_PCREL;
1008 case 2:
1009 return BFD_RELOC_16_GOT_PCREL;
1010 case 4:
1011 return BFD_RELOC_32_GOT_PCREL;
1012 }
1013 break;
1014
1015 case pic_got_off:
1016 switch (size)
1017 {
1018 case 1:
1019 return BFD_RELOC_8_GOTOFF;
1020 case 2:
1021 return BFD_RELOC_16_GOTOFF;
1022 case 4:
1023 return BFD_RELOC_32_GOTOFF;
1024 }
1025 break;
1026
1027 case pic_plt_pcrel:
1028 switch (size)
1029 {
1030 case 1:
1031 return BFD_RELOC_8_PLT_PCREL;
1032 case 2:
1033 return BFD_RELOC_16_PLT_PCREL;
1034 case 4:
1035 return BFD_RELOC_32_PLT_PCREL;
1036 }
1037 break;
1038
1039 case pic_plt_off:
1040 switch (size)
1041 {
1042 case 1:
1043 return BFD_RELOC_8_PLTOFF;
1044 case 2:
1045 return BFD_RELOC_16_PLTOFF;
1046 case 4:
1047 return BFD_RELOC_32_PLTOFF;
1048 }
1049 break;
1050
1051 case pic_tls_gd:
1052 switch (size)
1053 {
1054 case 1:
1055 return BFD_RELOC_68K_TLS_GD8;
1056 case 2:
1057 return BFD_RELOC_68K_TLS_GD16;
1058 case 4:
1059 return BFD_RELOC_68K_TLS_GD32;
1060 }
1061 break;
1062
1063 case pic_tls_ldm:
1064 switch (size)
1065 {
1066 case 1:
1067 return BFD_RELOC_68K_TLS_LDM8;
1068 case 2:
1069 return BFD_RELOC_68K_TLS_LDM16;
1070 case 4:
1071 return BFD_RELOC_68K_TLS_LDM32;
1072 }
1073 break;
1074
1075 case pic_tls_ldo:
1076 switch (size)
1077 {
1078 case 1:
1079 return BFD_RELOC_68K_TLS_LDO8;
1080 case 2:
1081 return BFD_RELOC_68K_TLS_LDO16;
1082 case 4:
1083 return BFD_RELOC_68K_TLS_LDO32;
1084 }
1085 break;
1086
1087 case pic_tls_ie:
1088 switch (size)
1089 {
1090 case 1:
1091 return BFD_RELOC_68K_TLS_IE8;
1092 case 2:
1093 return BFD_RELOC_68K_TLS_IE16;
1094 case 4:
1095 return BFD_RELOC_68K_TLS_IE32;
1096 }
1097 break;
1098
1099 case pic_tls_le:
1100 switch (size)
1101 {
1102 case 1:
1103 return BFD_RELOC_68K_TLS_LE8;
1104 case 2:
1105 return BFD_RELOC_68K_TLS_LE16;
1106 case 4:
1107 return BFD_RELOC_68K_TLS_LE32;
1108 }
1109 break;
1110
1111 case pic_none:
1112 if (pcrel)
1113 {
1114 switch (size)
1115 {
1116 case 1:
1117 return BFD_RELOC_8_PCREL;
1118 case 2:
1119 return BFD_RELOC_16_PCREL;
1120 case 4:
1121 return BFD_RELOC_32_PCREL;
1122 }
1123 }
1124 else
1125 {
1126 switch (size)
1127 {
1128 case 1:
1129 return BFD_RELOC_8;
1130 case 2:
1131 return BFD_RELOC_16;
1132 case 4:
1133 return BFD_RELOC_32;
1134 }
1135 }
1136 }
1137
1138 if (pcrel)
1139 {
1140 if (pic == pic_none)
1141 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1142 else
1143 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1144 }
1145 else
1146 {
1147 if (pic == pic_none)
1148 as_bad (_("Can not do %d byte relocation"), size);
1149 else
1150 as_bad (_("Can not do %d byte pic relocation"), size);
1151 }
1152
1153 return BFD_RELOC_NONE;
1154 }
1155
1156 /* Here we decide which fixups can be adjusted to make them relative
1157 to the beginning of the section instead of the symbol. Basically
1158 we need to make sure that the dynamic relocations are done
1159 correctly, so in some cases we force the original symbol to be
1160 used. */
1161 int
1162 tc_m68k_fix_adjustable (fixS *fixP)
1163 {
1164 /* Adjust_reloc_syms doesn't know about the GOT. */
1165 switch (fixP->fx_r_type)
1166 {
1167 case BFD_RELOC_8_GOT_PCREL:
1168 case BFD_RELOC_16_GOT_PCREL:
1169 case BFD_RELOC_32_GOT_PCREL:
1170 case BFD_RELOC_8_GOTOFF:
1171 case BFD_RELOC_16_GOTOFF:
1172 case BFD_RELOC_32_GOTOFF:
1173 case BFD_RELOC_8_PLT_PCREL:
1174 case BFD_RELOC_16_PLT_PCREL:
1175 case BFD_RELOC_32_PLT_PCREL:
1176 case BFD_RELOC_8_PLTOFF:
1177 case BFD_RELOC_16_PLTOFF:
1178 case BFD_RELOC_32_PLTOFF:
1179 case BFD_RELOC_68K_TLS_GD32:
1180 case BFD_RELOC_68K_TLS_GD16:
1181 case BFD_RELOC_68K_TLS_GD8:
1182 case BFD_RELOC_68K_TLS_LDM32:
1183 case BFD_RELOC_68K_TLS_LDM16:
1184 case BFD_RELOC_68K_TLS_LDM8:
1185 case BFD_RELOC_68K_TLS_LDO32:
1186 case BFD_RELOC_68K_TLS_LDO16:
1187 case BFD_RELOC_68K_TLS_LDO8:
1188 case BFD_RELOC_68K_TLS_IE32:
1189 case BFD_RELOC_68K_TLS_IE16:
1190 case BFD_RELOC_68K_TLS_IE8:
1191 case BFD_RELOC_68K_TLS_LE32:
1192 case BFD_RELOC_68K_TLS_LE16:
1193 case BFD_RELOC_68K_TLS_LE8:
1194 return 0;
1195
1196 case BFD_RELOC_VTABLE_INHERIT:
1197 case BFD_RELOC_VTABLE_ENTRY:
1198 return 0;
1199
1200 default:
1201 return 1;
1202 }
1203 }
1204
1205 arelent *
1206 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1207 {
1208 arelent *reloc;
1209 bfd_reloc_code_real_type code;
1210
1211 /* If the tcbit is set, then this was a fixup of a negative value
1212 that was never resolved. We do not have a reloc to handle this,
1213 so just return. We assume that other code will have detected this
1214 situation and produced a helpful error message, so we just tell the
1215 user that the reloc cannot be produced. */
1216 if (fixp->fx_tcbit)
1217 {
1218 if (fixp->fx_addsy)
1219 as_bad_where (fixp->fx_file, fixp->fx_line,
1220 _("Unable to produce reloc against symbol '%s'"),
1221 S_GET_NAME (fixp->fx_addsy));
1222 return NULL;
1223 }
1224
1225 if (fixp->fx_r_type != BFD_RELOC_NONE)
1226 {
1227 code = fixp->fx_r_type;
1228
1229 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1230 that fixup_segment converted a non-PC relative reloc into a
1231 PC relative reloc. In such a case, we need to convert the
1232 reloc code. */
1233 if (fixp->fx_pcrel)
1234 {
1235 switch (code)
1236 {
1237 case BFD_RELOC_8:
1238 code = BFD_RELOC_8_PCREL;
1239 break;
1240 case BFD_RELOC_16:
1241 code = BFD_RELOC_16_PCREL;
1242 break;
1243 case BFD_RELOC_32:
1244 code = BFD_RELOC_32_PCREL;
1245 break;
1246 case BFD_RELOC_8_PCREL:
1247 case BFD_RELOC_16_PCREL:
1248 case BFD_RELOC_32_PCREL:
1249 case BFD_RELOC_8_GOT_PCREL:
1250 case BFD_RELOC_16_GOT_PCREL:
1251 case BFD_RELOC_32_GOT_PCREL:
1252 case BFD_RELOC_8_GOTOFF:
1253 case BFD_RELOC_16_GOTOFF:
1254 case BFD_RELOC_32_GOTOFF:
1255 case BFD_RELOC_8_PLT_PCREL:
1256 case BFD_RELOC_16_PLT_PCREL:
1257 case BFD_RELOC_32_PLT_PCREL:
1258 case BFD_RELOC_8_PLTOFF:
1259 case BFD_RELOC_16_PLTOFF:
1260 case BFD_RELOC_32_PLTOFF:
1261 case BFD_RELOC_68K_TLS_GD32:
1262 case BFD_RELOC_68K_TLS_GD16:
1263 case BFD_RELOC_68K_TLS_GD8:
1264 case BFD_RELOC_68K_TLS_LDM32:
1265 case BFD_RELOC_68K_TLS_LDM16:
1266 case BFD_RELOC_68K_TLS_LDM8:
1267 case BFD_RELOC_68K_TLS_LDO32:
1268 case BFD_RELOC_68K_TLS_LDO16:
1269 case BFD_RELOC_68K_TLS_LDO8:
1270 case BFD_RELOC_68K_TLS_IE32:
1271 case BFD_RELOC_68K_TLS_IE16:
1272 case BFD_RELOC_68K_TLS_IE8:
1273 case BFD_RELOC_68K_TLS_LE32:
1274 case BFD_RELOC_68K_TLS_LE16:
1275 case BFD_RELOC_68K_TLS_LE8:
1276 break;
1277 default:
1278 as_bad_where (fixp->fx_file, fixp->fx_line,
1279 _("Cannot make %s relocation PC relative"),
1280 bfd_get_reloc_code_name (code));
1281 }
1282 }
1283 }
1284 else
1285 {
1286 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1287 switch (F (fixp->fx_size, fixp->fx_pcrel))
1288 {
1289 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1290 MAP (1, 0, BFD_RELOC_8);
1291 MAP (2, 0, BFD_RELOC_16);
1292 MAP (4, 0, BFD_RELOC_32);
1293 MAP (1, 1, BFD_RELOC_8_PCREL);
1294 MAP (2, 1, BFD_RELOC_16_PCREL);
1295 MAP (4, 1, BFD_RELOC_32_PCREL);
1296 default:
1297 abort ();
1298 }
1299 }
1300 #undef F
1301 #undef MAP
1302
1303 reloc = XNEW (arelent);
1304 reloc->sym_ptr_ptr = XNEW (asymbol *);
1305 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1306 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1307 if (!fixp->fx_pcrel)
1308 reloc->addend = fixp->fx_addnumber;
1309 else
1310 reloc->addend = (section->vma
1311 + fixp->fx_pcrel_adjust
1312 + fixp->fx_addnumber
1313 + md_pcrel_from (fixp));
1314
1315 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1316 gas_assert (reloc->howto != 0);
1317
1318 return reloc;
1319 }
1320
1321 /* Handle of the OPCODE hash table. NULL means any use before
1322 m68k_ip_begin() will crash. */
1323 static htab_t op_hash;
1324 \f
1325 /* Assemble an m68k instruction. */
1326
1327 static void
1328 m68k_ip (char *instring)
1329 {
1330 char *p;
1331 struct m68k_op *opP;
1332 const struct m68k_incant *opcode;
1333 const char *s;
1334 int tmpreg = 0, baseo = 0, outro = 0, nextword;
1335 char *pdot, *pdotmove;
1336 enum m68k_size siz1, siz2;
1337 char c;
1338 int losing;
1339 int opsfound;
1340 struct m68k_op operands_backup[6];
1341 LITTLENUM_TYPE words[6];
1342 LITTLENUM_TYPE *wordp;
1343 unsigned long ok_arch = 0;
1344
1345 if (*instring == ' ')
1346 instring++; /* Skip leading whitespace. */
1347
1348 /* Scan up to end of operation-code, which MUST end in end-of-string
1349 or exactly 1 space. */
1350 pdot = 0;
1351 for (p = instring; *p != '\0'; p++)
1352 {
1353 if (*p == ' ')
1354 break;
1355 if (*p == '.')
1356 pdot = p;
1357 }
1358
1359 if (p == instring)
1360 {
1361 the_ins.error = _("No operator");
1362 return;
1363 }
1364
1365 /* p now points to the end of the opcode name, probably whitespace.
1366 Make sure the name is null terminated by clobbering the
1367 whitespace, look it up in the hash table, then fix it back.
1368 Remove a dot, first, since the opcode tables have none. */
1369 if (pdot != NULL)
1370 {
1371 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1372 *pdotmove = pdotmove[1];
1373 p--;
1374 }
1375
1376 c = *p;
1377 *p = '\0';
1378 opcode = (const struct m68k_incant *) str_hash_find (op_hash, instring);
1379 *p = c;
1380
1381 if (pdot != NULL)
1382 {
1383 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1384 *pdotmove = pdotmove[-1];
1385 *pdot = '.';
1386 ++p;
1387 }
1388
1389 if (opcode == NULL)
1390 {
1391 the_ins.error = _("Unknown operator");
1392 return;
1393 }
1394
1395 /* Found a legitimate opcode, start matching operands. */
1396 while (*p == ' ')
1397 ++p;
1398
1399 if (opcode->m_operands == 0)
1400 {
1401 char *old = input_line_pointer;
1402 *old = '\n';
1403 input_line_pointer = p;
1404 /* Ahh - it's a motorola style pseudo op. */
1405 mote_pseudo_table[opcode->m_opnum].poc_handler
1406 (mote_pseudo_table[opcode->m_opnum].poc_val);
1407 input_line_pointer = old;
1408 *old = 0;
1409
1410 return;
1411 }
1412
1413 if (flag_mri && opcode->m_opnum == 0)
1414 {
1415 /* In MRI mode, random garbage is allowed after an instruction
1416 which accepts no operands. */
1417 the_ins.args = opcode->m_operands;
1418 the_ins.numargs = opcode->m_opnum;
1419 the_ins.numo = opcode->m_codenum;
1420 the_ins.opcode[0] = getone (opcode);
1421 the_ins.opcode[1] = gettwo (opcode);
1422 return;
1423 }
1424
1425 for (opP = &the_ins.operands[0]; *p; opP++)
1426 {
1427 p = crack_operand (p, opP);
1428
1429 if (opP->error)
1430 {
1431 the_ins.error = opP->error;
1432 return;
1433 }
1434 }
1435
1436 opsfound = opP - &the_ins.operands[0];
1437
1438 /* This ugly hack is to support the floating pt opcodes in their
1439 standard form. Essentially, we fake a first entry of type COP#1 */
1440 if (opcode->m_operands[0] == 'I')
1441 {
1442 int n;
1443
1444 for (n = opsfound; n > 0; --n)
1445 the_ins.operands[n] = the_ins.operands[n - 1];
1446
1447 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1448 the_ins.operands[0].mode = CONTROL;
1449 the_ins.operands[0].reg = m68k_float_copnum;
1450 opsfound++;
1451 }
1452
1453 /* We've got the operands. Find an opcode that'll accept them. */
1454 for (losing = 0;;)
1455 {
1456 /* If we didn't get the right number of ops, or we have no
1457 common model with this pattern then reject this pattern. */
1458
1459 ok_arch |= opcode->m_arch;
1460 if (opsfound != opcode->m_opnum
1461 || ((opcode->m_arch & current_architecture) == 0))
1462 ++losing;
1463 else
1464 {
1465 int i;
1466
1467 /* Make a copy of the operands of this insn so that
1468 we can modify them safely, should we want to. */
1469 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1470 for (i = 0; i < opsfound; i++)
1471 operands_backup[i] = the_ins.operands[i];
1472
1473 for (s = opcode->m_operands, opP = &operands_backup[0];
1474 *s && !losing;
1475 s += 2, opP++)
1476 {
1477 /* Warning: this switch is huge! */
1478 /* I've tried to organize the cases into this order:
1479 non-alpha first, then alpha by letter. Lower-case
1480 goes directly before uppercase counterpart. */
1481 /* Code with multiple case ...: gets sorted by the lowest
1482 case ... it belongs to. I hope this makes sense. */
1483 switch (*s)
1484 {
1485 case '!':
1486 switch (opP->mode)
1487 {
1488 case IMMED:
1489 case DREG:
1490 case AREG:
1491 case FPREG:
1492 case CONTROL:
1493 case AINC:
1494 case ADEC:
1495 case REGLST:
1496 losing++;
1497 break;
1498 default:
1499 break;
1500 }
1501 break;
1502
1503 case '<':
1504 switch (opP->mode)
1505 {
1506 case DREG:
1507 case AREG:
1508 case FPREG:
1509 case CONTROL:
1510 case IMMED:
1511 case ADEC:
1512 case REGLST:
1513 losing++;
1514 break;
1515 default:
1516 break;
1517 }
1518 break;
1519
1520 case '>':
1521 switch (opP->mode)
1522 {
1523 case DREG:
1524 case AREG:
1525 case FPREG:
1526 case CONTROL:
1527 case IMMED:
1528 case AINC:
1529 case REGLST:
1530 losing++;
1531 break;
1532 case ABSL:
1533 break;
1534 default:
1535 if (opP->reg == PC
1536 || opP->reg == ZPC)
1537 losing++;
1538 break;
1539 }
1540 break;
1541
1542 case 'm':
1543 switch (opP->mode)
1544 {
1545 case DREG:
1546 case AREG:
1547 case AINDR:
1548 case AINC:
1549 case ADEC:
1550 break;
1551 default:
1552 losing++;
1553 }
1554 break;
1555
1556 case 'n':
1557 switch (opP->mode)
1558 {
1559 case DISP:
1560 break;
1561 default:
1562 losing++;
1563 }
1564 break;
1565
1566 case 'o':
1567 switch (opP->mode)
1568 {
1569 case BASE:
1570 case ABSL:
1571 case IMMED:
1572 break;
1573 default:
1574 losing++;
1575 }
1576 break;
1577
1578 case 'p':
1579 switch (opP->mode)
1580 {
1581 case DREG:
1582 case AREG:
1583 case AINDR:
1584 case AINC:
1585 case ADEC:
1586 break;
1587 case DISP:
1588 if (opP->reg == PC || opP->reg == ZPC)
1589 losing++;
1590 break;
1591 default:
1592 losing++;
1593 }
1594 break;
1595
1596 case 'q':
1597 switch (opP->mode)
1598 {
1599 case DREG:
1600 case AINDR:
1601 case AINC:
1602 case ADEC:
1603 break;
1604 case DISP:
1605 if (opP->reg == PC || opP->reg == ZPC)
1606 losing++;
1607 break;
1608 default:
1609 losing++;
1610 break;
1611 }
1612 break;
1613
1614 case 'v':
1615 switch (opP->mode)
1616 {
1617 case DREG:
1618 case AINDR:
1619 case AINC:
1620 case ADEC:
1621 case ABSL:
1622 break;
1623 case DISP:
1624 if (opP->reg == PC || opP->reg == ZPC)
1625 losing++;
1626 break;
1627 default:
1628 losing++;
1629 break;
1630 }
1631 break;
1632
1633 case '#':
1634 if (opP->mode != IMMED)
1635 losing++;
1636 else if (s[1] == 'b'
1637 && ! isvar (&opP->disp)
1638 && (opP->disp.exp.X_op != O_constant
1639 || ! isbyte (opP->disp.exp.X_add_number)))
1640 losing++;
1641 else if (s[1] == 'B'
1642 && ! isvar (&opP->disp)
1643 && (opP->disp.exp.X_op != O_constant
1644 || ! issbyte (opP->disp.exp.X_add_number)))
1645 losing++;
1646 else if (s[1] == 'w'
1647 && ! isvar (&opP->disp)
1648 && (opP->disp.exp.X_op != O_constant
1649 || ! isword (opP->disp.exp.X_add_number)))
1650 losing++;
1651 else if (s[1] == 'W'
1652 && ! isvar (&opP->disp)
1653 && (opP->disp.exp.X_op != O_constant
1654 || ! issword (opP->disp.exp.X_add_number)))
1655 losing++;
1656 break;
1657
1658 case '^':
1659 case 'T':
1660 if (opP->mode != IMMED)
1661 losing++;
1662 break;
1663
1664 case '$':
1665 if (opP->mode == AREG
1666 || opP->mode == CONTROL
1667 || opP->mode == FPREG
1668 || opP->mode == IMMED
1669 || opP->mode == REGLST
1670 || (opP->mode != ABSL
1671 && (opP->reg == PC
1672 || opP->reg == ZPC)))
1673 losing++;
1674 break;
1675
1676 case '%':
1677 if (opP->mode == CONTROL
1678 || opP->mode == FPREG
1679 || opP->mode == REGLST
1680 || opP->mode == IMMED
1681 || (opP->mode != ABSL
1682 && (opP->reg == PC
1683 || opP->reg == ZPC)))
1684 losing++;
1685 break;
1686
1687 case '&':
1688 switch (opP->mode)
1689 {
1690 case DREG:
1691 case AREG:
1692 case FPREG:
1693 case CONTROL:
1694 case IMMED:
1695 case AINC:
1696 case ADEC:
1697 case REGLST:
1698 losing++;
1699 break;
1700 case ABSL:
1701 break;
1702 default:
1703 if (opP->reg == PC
1704 || opP->reg == ZPC)
1705 losing++;
1706 break;
1707 }
1708 break;
1709
1710 case '*':
1711 if (opP->mode == CONTROL
1712 || opP->mode == FPREG
1713 || opP->mode == REGLST)
1714 losing++;
1715 break;
1716
1717 case '+':
1718 if (opP->mode != AINC)
1719 losing++;
1720 break;
1721
1722 case '-':
1723 if (opP->mode != ADEC)
1724 losing++;
1725 break;
1726
1727 case '/':
1728 switch (opP->mode)
1729 {
1730 case AREG:
1731 case CONTROL:
1732 case FPREG:
1733 case AINC:
1734 case ADEC:
1735 case IMMED:
1736 case REGLST:
1737 losing++;
1738 break;
1739 default:
1740 break;
1741 }
1742 break;
1743
1744 case ';':
1745 switch (opP->mode)
1746 {
1747 case AREG:
1748 case CONTROL:
1749 case FPREG:
1750 case REGLST:
1751 losing++;
1752 break;
1753 default:
1754 break;
1755 }
1756 break;
1757
1758 case '?':
1759 switch (opP->mode)
1760 {
1761 case AREG:
1762 case CONTROL:
1763 case FPREG:
1764 case AINC:
1765 case ADEC:
1766 case IMMED:
1767 case REGLST:
1768 losing++;
1769 break;
1770 case ABSL:
1771 break;
1772 default:
1773 if (opP->reg == PC || opP->reg == ZPC)
1774 losing++;
1775 break;
1776 }
1777 break;
1778
1779 case '@':
1780 switch (opP->mode)
1781 {
1782 case AREG:
1783 case CONTROL:
1784 case FPREG:
1785 case IMMED:
1786 case REGLST:
1787 losing++;
1788 break;
1789 default:
1790 break;
1791 }
1792 break;
1793
1794 case '~': /* For now! (JF FOO is this right?) */
1795 switch (opP->mode)
1796 {
1797 case DREG:
1798 case AREG:
1799 case CONTROL:
1800 case FPREG:
1801 case IMMED:
1802 case REGLST:
1803 losing++;
1804 break;
1805 case ABSL:
1806 break;
1807 default:
1808 if (opP->reg == PC
1809 || opP->reg == ZPC)
1810 losing++;
1811 break;
1812 }
1813 break;
1814
1815 case '3':
1816 if (opP->mode != CONTROL
1817 || (opP->reg != TT0 && opP->reg != TT1))
1818 losing++;
1819 break;
1820
1821 case 'A':
1822 if (opP->mode != AREG)
1823 losing++;
1824 break;
1825
1826 case 'a':
1827 if (opP->mode != AINDR)
1828 ++losing;
1829 break;
1830
1831 case '4':
1832 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1833 && (opP->mode != DISP
1834 || opP->reg < ADDR0
1835 || opP->reg > ADDR7))
1836 ++losing;
1837 break;
1838
1839 case 'B': /* FOO */
1840 if (opP->mode != ABSL
1841 || (flag_long_jumps
1842 && strncmp (instring, "jbsr", 4) == 0))
1843 losing++;
1844 break;
1845
1846 case 'b':
1847 switch (opP->mode)
1848 {
1849 case IMMED:
1850 case ABSL:
1851 case AREG:
1852 case FPREG:
1853 case CONTROL:
1854 case POST:
1855 case PRE:
1856 case REGLST:
1857 losing++;
1858 break;
1859 default:
1860 break;
1861 }
1862 break;
1863
1864 case 'C':
1865 if (opP->mode != CONTROL || opP->reg != CCR)
1866 losing++;
1867 break;
1868
1869 case 'd':
1870 if (opP->mode != DISP
1871 || opP->reg < ADDR0
1872 || opP->reg > ADDR7)
1873 losing++;
1874 break;
1875
1876 case 'D':
1877 if (opP->mode != DREG)
1878 losing++;
1879 break;
1880
1881 case 'E':
1882 if (opP->reg != ACC)
1883 losing++;
1884 break;
1885
1886 case 'e':
1887 if (opP->reg != ACC && opP->reg != ACC1
1888 && opP->reg != ACC2 && opP->reg != ACC3)
1889 losing++;
1890 break;
1891
1892 case 'F':
1893 if (opP->mode != FPREG)
1894 losing++;
1895 break;
1896
1897 case 'G':
1898 if (opP->reg != MACSR)
1899 losing++;
1900 break;
1901
1902 case 'g':
1903 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1904 losing++;
1905 break;
1906
1907 case 'H':
1908 if (opP->reg != MASK)
1909 losing++;
1910 break;
1911
1912 case 'I':
1913 if (opP->mode != CONTROL
1914 || opP->reg < COP0
1915 || opP->reg > COP7)
1916 losing++;
1917 break;
1918
1919 case 'i':
1920 if (opP->mode != LSH && opP->mode != RSH)
1921 losing++;
1922 break;
1923
1924 case 'J':
1925 if (opP->mode != CONTROL
1926 || opP->reg < USP
1927 || opP->reg > last_movec_reg
1928 || !control_regs)
1929 losing++;
1930 else
1931 {
1932 const enum m68k_register *rp;
1933
1934 for (rp = control_regs; *rp; rp++)
1935 {
1936 if (*rp == opP->reg)
1937 break;
1938 /* In most CPUs RAMBAR refers to control reg
1939 c05 (RAMBAR1), but a few CPUs have it
1940 refer to c04 (RAMBAR0). */
1941 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1942 {
1943 opP->reg = RAMBAR_ALT;
1944 break;
1945 }
1946 }
1947 if (*rp == 0)
1948 losing++;
1949 }
1950 break;
1951
1952 case 'k':
1953 if (opP->mode != IMMED)
1954 losing++;
1955 break;
1956
1957 case 'l':
1958 case 'L':
1959 if (opP->mode == DREG
1960 || opP->mode == AREG
1961 || opP->mode == FPREG)
1962 {
1963 if (s[1] == '8')
1964 losing++;
1965 else
1966 {
1967 switch (opP->mode)
1968 {
1969 case DREG:
1970 opP->mask = 1 << (opP->reg - DATA0);
1971 break;
1972 case AREG:
1973 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1974 break;
1975 case FPREG:
1976 opP->mask = 1 << (opP->reg - FP0 + 16);
1977 break;
1978 default:
1979 abort ();
1980 }
1981 opP->mode = REGLST;
1982 }
1983 }
1984 else if (opP->mode == CONTROL)
1985 {
1986 if (s[1] != '8')
1987 losing++;
1988 else
1989 {
1990 switch (opP->reg)
1991 {
1992 case FPI:
1993 opP->mask = 1 << 24;
1994 break;
1995 case FPS:
1996 opP->mask = 1 << 25;
1997 break;
1998 case FPC:
1999 opP->mask = 1 << 26;
2000 break;
2001 default:
2002 losing++;
2003 break;
2004 }
2005 opP->mode = REGLST;
2006 }
2007 }
2008 else if (opP->mode != REGLST)
2009 losing++;
2010 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2011 losing++;
2012 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2013 losing++;
2014 break;
2015
2016 case 'M':
2017 if (opP->mode != IMMED)
2018 losing++;
2019 else if (opP->disp.exp.X_op != O_constant
2020 || ! issbyte (opP->disp.exp.X_add_number))
2021 losing++;
2022 else if (! m68k_quick
2023 && instring[3] != 'q'
2024 && instring[4] != 'q')
2025 losing++;
2026 break;
2027
2028 case 'O':
2029 if (opP->mode != DREG
2030 && opP->mode != IMMED
2031 && opP->mode != ABSL)
2032 losing++;
2033 break;
2034
2035 case 'Q':
2036 if (opP->mode != IMMED)
2037 losing++;
2038 else if (opP->disp.exp.X_op != O_constant
2039 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2040 losing++;
2041 else if (! m68k_quick
2042 && (strncmp (instring, "add", 3) == 0
2043 || strncmp (instring, "sub", 3) == 0)
2044 && instring[3] != 'q')
2045 losing++;
2046 break;
2047
2048 case 'R':
2049 if (opP->mode != DREG && opP->mode != AREG)
2050 losing++;
2051 break;
2052
2053 case 'r':
2054 if (opP->mode != AINDR
2055 && (opP->mode != BASE
2056 || (opP->reg != 0
2057 && opP->reg != ZADDR0)
2058 || opP->disp.exp.X_op != O_absent
2059 || ((opP->index.reg < DATA0
2060 || opP->index.reg > DATA7)
2061 && (opP->index.reg < ADDR0
2062 || opP->index.reg > ADDR7))
2063 || opP->index.size != SIZE_UNSPEC
2064 || opP->index.scale != 1))
2065 losing++;
2066 break;
2067
2068 case 's':
2069 if (opP->mode != CONTROL
2070 || ! (opP->reg == FPI
2071 || opP->reg == FPS
2072 || opP->reg == FPC))
2073 losing++;
2074 break;
2075
2076 case 'S':
2077 if (opP->mode != CONTROL || opP->reg != SR)
2078 losing++;
2079 break;
2080
2081 case 't':
2082 if (opP->mode != IMMED)
2083 losing++;
2084 else if (opP->disp.exp.X_op != O_constant
2085 || TRUNC (opP->disp.exp.X_add_number) > 7)
2086 losing++;
2087 break;
2088
2089 case 'U':
2090 if (opP->mode != CONTROL || opP->reg != USP)
2091 losing++;
2092 break;
2093
2094 case 'x':
2095 if (opP->mode != IMMED)
2096 losing++;
2097 else if (opP->disp.exp.X_op != O_constant
2098 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2099 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
2100 losing++;
2101 break;
2102
2103 case 'j':
2104 if (opP->mode != IMMED)
2105 losing++;
2106 else if (opP->disp.exp.X_op != O_constant
2107 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2108 losing++;
2109 break;
2110
2111 case 'K':
2112 if (opP->mode != IMMED)
2113 losing++;
2114 else if (opP->disp.exp.X_op != O_constant
2115 || TRUNC (opP->disp.exp.X_add_number) > 511)
2116 losing++;
2117 break;
2118
2119 /* JF these are out of order. We could put them
2120 in order if we were willing to put up with
2121 bunches of #ifdef m68851s in the code.
2122
2123 Don't forget that you need these operands
2124 to use 68030 MMU instructions. */
2125 #ifndef NO_68851
2126 /* Memory addressing mode used by pflushr. */
2127 case '|':
2128 if (opP->mode == CONTROL
2129 || opP->mode == FPREG
2130 || opP->mode == DREG
2131 || opP->mode == AREG
2132 || opP->mode == REGLST)
2133 losing++;
2134 /* We should accept immediate operands, but they
2135 supposedly have to be quad word, and we don't
2136 handle that. I would like to see what a Motorola
2137 assembler does before doing something here. */
2138 if (opP->mode == IMMED)
2139 losing++;
2140 break;
2141
2142 case 'f':
2143 if (opP->mode != CONTROL
2144 || (opP->reg != SFC && opP->reg != DFC))
2145 losing++;
2146 break;
2147
2148 case '0':
2149 if (opP->mode != CONTROL || opP->reg != TC)
2150 losing++;
2151 break;
2152
2153 case '1':
2154 if (opP->mode != CONTROL || opP->reg != AC)
2155 losing++;
2156 break;
2157
2158 case '2':
2159 if (opP->mode != CONTROL
2160 || (opP->reg != CAL
2161 && opP->reg != VAL
2162 && opP->reg != SCC))
2163 losing++;
2164 break;
2165
2166 case 'V':
2167 if (opP->mode != CONTROL
2168 || opP->reg != VAL)
2169 losing++;
2170 break;
2171
2172 case 'W':
2173 if (opP->mode != CONTROL
2174 || (opP->reg != DRP
2175 && opP->reg != SRP
2176 && opP->reg != CRP))
2177 losing++;
2178 break;
2179
2180 case 'w':
2181 switch (opP->mode)
2182 {
2183 case IMMED:
2184 case ABSL:
2185 case AREG:
2186 case DREG:
2187 case FPREG:
2188 case CONTROL:
2189 case POST:
2190 case PRE:
2191 case REGLST:
2192 losing++;
2193 break;
2194 default:
2195 break;
2196 }
2197 break;
2198
2199 case 'X':
2200 if (opP->mode != CONTROL
2201 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2202 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2203 losing++;
2204 break;
2205
2206 case 'Y':
2207 if (opP->mode != CONTROL || opP->reg != PSR)
2208 losing++;
2209 break;
2210
2211 case 'Z':
2212 if (opP->mode != CONTROL || opP->reg != PCSR)
2213 losing++;
2214 break;
2215 #endif
2216 case 'c':
2217 if (opP->mode != CONTROL
2218 || (opP->reg != NC
2219 && opP->reg != IC
2220 && opP->reg != DC
2221 && opP->reg != BC))
2222 losing++;
2223 break;
2224
2225 case '_':
2226 if (opP->mode != ABSL)
2227 ++losing;
2228 break;
2229
2230 case 'u':
2231 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2232 losing++;
2233 /* FIXME: kludge instead of fixing parser:
2234 upper/lower registers are *not* CONTROL
2235 registers, but ordinary ones. */
2236 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2237 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2238 opP->mode = DREG;
2239 else
2240 opP->mode = AREG;
2241 break;
2242
2243 case 'y':
2244 if (!(opP->mode == AINDR
2245 || (opP->mode == DISP
2246 && !(opP->reg == PC || opP->reg == ZPC))))
2247 losing++;
2248 break;
2249
2250 case 'z':
2251 if (!(opP->mode == AINDR || opP->mode == DISP))
2252 losing++;
2253 break;
2254
2255 default:
2256 abort ();
2257 }
2258
2259 if (losing)
2260 break;
2261 }
2262
2263 /* Since we have found the correct instruction, copy
2264 in the modifications that we may have made. */
2265 if (!losing)
2266 for (i = 0; i < opsfound; i++)
2267 the_ins.operands[i] = operands_backup[i];
2268 }
2269
2270 if (!losing)
2271 break;
2272
2273 opcode = opcode->m_next;
2274
2275 if (!opcode)
2276 {
2277 if (ok_arch
2278 && !(ok_arch & current_architecture))
2279 {
2280 const struct m68k_cpu *cpu;
2281 int any = 0;
2282 size_t space = 400;
2283 char *buf = XNEWVEC (char, space + 1);
2284 size_t len;
2285 int paren = 1;
2286
2287 the_ins.error = buf;
2288 /* Make sure there's a NUL at the end of the buffer -- strncpy
2289 won't write one when it runs out of buffer. */
2290 buf[space] = 0;
2291 #define APPEND(STRING) \
2292 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2293
2294 APPEND (_("invalid instruction for this architecture; needs "));
2295 switch (ok_arch)
2296 {
2297 case mcfisa_a:
2298 APPEND ("ColdFire ISA_A");
2299 break;
2300 case mcfhwdiv:
2301 APPEND ("ColdFire ");
2302 APPEND (_("hardware divide"));
2303 break;
2304 case mcfisa_aa:
2305 APPEND ("ColdFire ISA_A+");
2306 break;
2307 case mcfisa_b:
2308 APPEND ("ColdFire ISA_B");
2309 break;
2310 case mcfisa_c:
2311 APPEND ("ColdFire ISA_C");
2312 break;
2313 case cfloat:
2314 APPEND ("ColdFire fpu");
2315 break;
2316 case mfloat:
2317 APPEND ("M68K fpu");
2318 break;
2319 case mmmu:
2320 APPEND ("M68K mmu");
2321 break;
2322 case m68020up:
2323 APPEND ("68020 ");
2324 APPEND (_("or higher"));
2325 break;
2326 case m68000up:
2327 APPEND ("68000 ");
2328 APPEND (_("or higher"));
2329 break;
2330 case m68010up:
2331 APPEND ("68010 ");
2332 APPEND (_("or higher"));
2333 break;
2334 default:
2335 paren = 0;
2336 }
2337 if (paren)
2338 APPEND (" (");
2339
2340 for (cpu = m68k_cpus; cpu->name; cpu++)
2341 if (!cpu->alias && (cpu->arch & ok_arch))
2342 {
2343 const struct m68k_cpu *alias;
2344 int seen_master = 0;
2345
2346 if (any)
2347 APPEND (", ");
2348 any = 0;
2349 APPEND (cpu->name);
2350 for (alias = cpu; alias != m68k_cpus; alias--)
2351 if (alias[-1].alias >= 0)
2352 break;
2353 for (; !seen_master || alias->alias > 0; alias++)
2354 {
2355 if (!alias->alias)
2356 seen_master = 1;
2357 else
2358 {
2359 if (any)
2360 APPEND (", ");
2361 else
2362 APPEND (" [");
2363 APPEND (alias->name);
2364 any = 1;
2365 }
2366 }
2367 if (any)
2368 APPEND ("]");
2369 any = 1;
2370 }
2371 if (paren)
2372 APPEND (")");
2373 #undef APPEND
2374 if (!space)
2375 {
2376 /* We ran out of space, so replace the end of the list
2377 with ellipsis. */
2378 buf -= 4;
2379 while (*buf != ' ')
2380 buf--;
2381 strcpy (buf, " ...");
2382 }
2383 }
2384 else
2385 the_ins.error = _("operands mismatch");
2386 return;
2387 }
2388
2389 losing = 0;
2390 }
2391
2392 /* Now assemble it. */
2393 the_ins.args = opcode->m_operands;
2394 the_ins.numargs = opcode->m_opnum;
2395 the_ins.numo = opcode->m_codenum;
2396 the_ins.opcode[0] = getone (opcode);
2397 the_ins.opcode[1] = gettwo (opcode);
2398
2399 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2400 {
2401 int have_disp = 0;
2402 int use_pl = 0;
2403
2404 /* This switch is a doozy.
2405 Watch the first step; it's a big one! */
2406 switch (s[0])
2407 {
2408
2409 case '*':
2410 case '~':
2411 case '%':
2412 case ';':
2413 case '@':
2414 case '!':
2415 case '&':
2416 case '$':
2417 case '?':
2418 case '/':
2419 case '<':
2420 case '>':
2421 case 'b':
2422 case 'm':
2423 case 'n':
2424 case 'o':
2425 case 'p':
2426 case 'q':
2427 case 'v':
2428 case 'w':
2429 case 'y':
2430 case 'z':
2431 case '4':
2432 #ifndef NO_68851
2433 case '|':
2434 #endif
2435 switch (opP->mode)
2436 {
2437 case IMMED:
2438 tmpreg = 0x3c; /* 7.4 */
2439 if (strchr ("bwl", s[1]))
2440 nextword = get_num (&opP->disp, 90);
2441 else
2442 nextword = get_num (&opP->disp, 0);
2443 if (isvar (&opP->disp))
2444 add_fix (s[1], &opP->disp, 0, 0);
2445 switch (s[1])
2446 {
2447 case 'b':
2448 if (!isbyte (nextword))
2449 opP->error = _("operand out of range");
2450 addword (nextword);
2451 baseo = 0;
2452 break;
2453 case 'w':
2454 if (!isword (nextword))
2455 opP->error = _("operand out of range");
2456 addword (nextword);
2457 baseo = 0;
2458 break;
2459 case 'W':
2460 if (!issword (nextword))
2461 opP->error = _("operand out of range");
2462 addword (nextword);
2463 baseo = 0;
2464 break;
2465 case 'l':
2466 addword (nextword >> 16);
2467 addword (nextword);
2468 baseo = 0;
2469 break;
2470
2471 case 'f':
2472 baseo = 2;
2473 outro = 8;
2474 break;
2475 case 'F':
2476 baseo = 4;
2477 outro = 11;
2478 break;
2479 case 'x':
2480 baseo = 6;
2481 outro = 15;
2482 break;
2483 case 'p':
2484 baseo = 6;
2485 outro = -1;
2486 break;
2487 default:
2488 abort ();
2489 }
2490 if (!baseo)
2491 break;
2492
2493 /* We gotta put out some float. */
2494 if (op (&opP->disp) != O_big)
2495 {
2496 valueT val;
2497 int gencnt;
2498
2499 /* Can other cases happen here? */
2500 if (op (&opP->disp) != O_constant)
2501 abort ();
2502
2503 val = (valueT) offs (&opP->disp);
2504 gencnt = 0;
2505 do
2506 {
2507 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2508 val >>= LITTLENUM_NUMBER_OF_BITS;
2509 ++gencnt;
2510 }
2511 while (val != 0);
2512 offs (&opP->disp) = gencnt;
2513 }
2514 if (offs (&opP->disp) > 0)
2515 {
2516 if (offs (&opP->disp) > baseo)
2517 {
2518 as_warn (_("Bignum too big for %c format; truncated"),
2519 s[1]);
2520 offs (&opP->disp) = baseo;
2521 }
2522 baseo -= offs (&opP->disp);
2523 while (baseo--)
2524 addword (0);
2525 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2526 offs (&opP->disp)--;
2527 --wordp)
2528 addword (*wordp);
2529 break;
2530 }
2531 gen_to_words (words, baseo, (long) outro);
2532 for (wordp = words; baseo--; wordp++)
2533 addword (*wordp);
2534 break;
2535 case DREG:
2536 tmpreg = opP->reg - DATA; /* 0.dreg */
2537 break;
2538 case AREG:
2539 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2540 break;
2541 case AINDR:
2542 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2543 break;
2544 case ADEC:
2545 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2546 break;
2547 case AINC:
2548 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2549 break;
2550 case DISP:
2551
2552 nextword = get_num (&opP->disp, 90);
2553
2554 /* Convert mode 5 addressing with a zero offset into
2555 mode 2 addressing to reduce the instruction size by a
2556 word. */
2557 if (! isvar (&opP->disp)
2558 && (nextword == 0)
2559 && (opP->disp.size == SIZE_UNSPEC)
2560 && (opP->reg >= ADDR0)
2561 && (opP->reg <= ADDR7))
2562 {
2563 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2564 break;
2565 }
2566
2567 if (opP->reg == PC
2568 && ! isvar (&opP->disp)
2569 && m68k_abspcadd)
2570 {
2571 opP->disp.exp.X_op = O_symbol;
2572 opP->disp.exp.X_add_symbol =
2573 section_symbol (absolute_section);
2574 }
2575
2576 /* Force into index mode. Hope this works. */
2577
2578 /* We do the first bit for 32-bit displacements, and the
2579 second bit for 16 bit ones. It is possible that we
2580 should make the default be WORD instead of LONG, but
2581 I think that'd break GCC, so we put up with a little
2582 inefficiency for the sake of working output. */
2583
2584 if (!issword (nextword)
2585 || (isvar (&opP->disp)
2586 && ((opP->disp.size == SIZE_UNSPEC
2587 && flag_short_refs == 0
2588 && cpu_of_arch (current_architecture) >= m68020
2589 && ! arch_coldfire_p (current_architecture))
2590 || opP->disp.size == SIZE_LONG)))
2591 {
2592 if (cpu_of_arch (current_architecture) < m68020
2593 || arch_coldfire_p (current_architecture))
2594 opP->error =
2595 _("displacement too large for this architecture; needs 68020 or higher");
2596 if (opP->reg == PC)
2597 tmpreg = 0x3B; /* 7.3 */
2598 else
2599 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2600 if (isvar (&opP->disp))
2601 {
2602 if (opP->reg == PC)
2603 {
2604 if (opP->disp.size == SIZE_LONG
2605 /* If the displacement needs pic
2606 relocation it cannot be relaxed. */
2607 || opP->disp.pic_reloc != pic_none)
2608 {
2609 addword (0x0170);
2610 add_fix ('l', &opP->disp, 1, 2);
2611 }
2612 else
2613 {
2614 add_frag (adds (&opP->disp),
2615 SEXT (offs (&opP->disp)),
2616 TAB (PCREL1632, SZ_UNDEF));
2617 break;
2618 }
2619 }
2620 else
2621 {
2622 addword (0x0170);
2623 add_fix ('l', &opP->disp, 0, 0);
2624 }
2625 }
2626 else
2627 addword (0x0170);
2628 addword (nextword >> 16);
2629 }
2630 else
2631 {
2632 if (opP->reg == PC)
2633 tmpreg = 0x3A; /* 7.2 */
2634 else
2635 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2636
2637 if (isvar (&opP->disp))
2638 {
2639 if (opP->reg == PC)
2640 {
2641 add_fix ('w', &opP->disp, 1, 0);
2642 }
2643 else
2644 add_fix ('w', &opP->disp, 0, 0);
2645 }
2646 }
2647 addword (nextword);
2648 break;
2649
2650 case POST:
2651 case PRE:
2652 case BASE:
2653 nextword = 0;
2654 baseo = get_num (&opP->disp, 90);
2655 if (opP->mode == POST || opP->mode == PRE)
2656 outro = get_num (&opP->odisp, 90);
2657 /* Figure out the `addressing mode'.
2658 Also turn on the BASE_DISABLE bit, if needed. */
2659 if (opP->reg == PC || opP->reg == ZPC)
2660 {
2661 tmpreg = 0x3b; /* 7.3 */
2662 if (opP->reg == ZPC)
2663 nextword |= 0x80;
2664 }
2665 else if (opP->reg == 0)
2666 {
2667 nextword |= 0x80;
2668 tmpreg = 0x30; /* 6.garbage */
2669 }
2670 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2671 {
2672 nextword |= 0x80;
2673 tmpreg = 0x30 + opP->reg - ZADDR0;
2674 }
2675 else
2676 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2677
2678 siz1 = opP->disp.size;
2679 if (opP->mode == POST || opP->mode == PRE)
2680 siz2 = opP->odisp.size;
2681 else
2682 siz2 = SIZE_UNSPEC;
2683
2684 /* Index register stuff. */
2685 if (opP->index.reg != 0
2686 && opP->index.reg >= DATA
2687 && opP->index.reg <= ADDR7)
2688 {
2689 nextword |= (opP->index.reg - DATA) << 12;
2690
2691 if (opP->index.size == SIZE_LONG
2692 || (opP->index.size == SIZE_UNSPEC
2693 && m68k_index_width_default == SIZE_LONG))
2694 nextword |= 0x800;
2695
2696 if ((opP->index.scale != 1
2697 && cpu_of_arch (current_architecture) < m68020)
2698 || (opP->index.scale == 8
2699 && (arch_coldfire_p (current_architecture)
2700 && !arch_coldfire_fpu (current_architecture))))
2701 {
2702 opP->error =
2703 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2704 }
2705
2706 if (arch_coldfire_p (current_architecture)
2707 && opP->index.size == SIZE_WORD)
2708 opP->error = _("invalid index size for coldfire");
2709
2710 switch (opP->index.scale)
2711 {
2712 case 1:
2713 break;
2714 case 2:
2715 nextword |= 0x200;
2716 break;
2717 case 4:
2718 nextword |= 0x400;
2719 break;
2720 case 8:
2721 nextword |= 0x600;
2722 break;
2723 default:
2724 abort ();
2725 }
2726 /* IF it's simple,
2727 GET US OUT OF HERE! */
2728
2729 /* Must be INDEX, with an index register. Address
2730 register cannot be ZERO-PC, and either :b was
2731 forced, or we know it will fit. For a 68000 or
2732 68010, force this mode anyways, because the
2733 larger modes aren't supported. */
2734 if (opP->mode == BASE
2735 && ((opP->reg >= ADDR0
2736 && opP->reg <= ADDR7)
2737 || opP->reg == PC))
2738 {
2739 if (siz1 == SIZE_BYTE
2740 || cpu_of_arch (current_architecture) < m68020
2741 || arch_coldfire_p (current_architecture)
2742 || (siz1 == SIZE_UNSPEC
2743 && ! isvar (&opP->disp)
2744 && issbyte (baseo)))
2745 {
2746 nextword += baseo & 0xff;
2747 addword (nextword);
2748 if (isvar (&opP->disp))
2749 {
2750 /* Do a byte relocation. If it doesn't
2751 fit (possible on m68000) let the
2752 fixup processing complain later. */
2753 if (opP->reg == PC)
2754 add_fix ('B', &opP->disp, 1, 1);
2755 else
2756 add_fix ('B', &opP->disp, 0, 0);
2757 }
2758 else if (siz1 != SIZE_BYTE)
2759 {
2760 if (siz1 != SIZE_UNSPEC)
2761 as_warn (_("Forcing byte displacement"));
2762 if (! issbyte (baseo))
2763 opP->error = _("byte displacement out of range");
2764 }
2765
2766 break;
2767 }
2768 else if (siz1 == SIZE_UNSPEC
2769 && opP->reg == PC
2770 && isvar (&opP->disp)
2771 && subs (&opP->disp) == NULL
2772 /* If the displacement needs pic
2773 relocation it cannot be relaxed. */
2774 && opP->disp.pic_reloc == pic_none)
2775 {
2776 /* The code in md_convert_frag_1 needs to be
2777 able to adjust nextword. Call frag_grow
2778 to ensure that we have enough space in
2779 the frag obstack to make all the bytes
2780 contiguous. */
2781 frag_grow (14);
2782 nextword += baseo & 0xff;
2783 addword (nextword);
2784 add_frag (adds (&opP->disp),
2785 SEXT (offs (&opP->disp)),
2786 TAB (PCINDEX, SZ_UNDEF));
2787
2788 break;
2789 }
2790 }
2791 }
2792 else
2793 {
2794 nextword |= 0x40; /* No index reg. */
2795 if (opP->index.reg >= ZDATA0
2796 && opP->index.reg <= ZDATA7)
2797 nextword |= (opP->index.reg - ZDATA0) << 12;
2798 else if (opP->index.reg >= ZADDR0
2799 && opP->index.reg <= ZADDR7)
2800 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2801 }
2802
2803 /* It isn't simple. */
2804
2805 if (cpu_of_arch (current_architecture) < m68020
2806 || arch_coldfire_p (current_architecture))
2807 opP->error =
2808 _("invalid operand mode for this architecture; needs 68020 or higher");
2809
2810 nextword |= 0x100;
2811 /* If the guy specified a width, we assume that it is
2812 wide enough. Maybe it isn't. If so, we lose. */
2813 switch (siz1)
2814 {
2815 case SIZE_UNSPEC:
2816 if (isvar (&opP->disp)
2817 ? m68k_rel32
2818 : ! issword (baseo))
2819 {
2820 siz1 = SIZE_LONG;
2821 nextword |= 0x30;
2822 }
2823 else if (! isvar (&opP->disp) && baseo == 0)
2824 nextword |= 0x10;
2825 else
2826 {
2827 nextword |= 0x20;
2828 siz1 = SIZE_WORD;
2829 }
2830 break;
2831 case SIZE_BYTE:
2832 as_warn (_(":b not permitted; defaulting to :w"));
2833 /* Fall through. */
2834 case SIZE_WORD:
2835 nextword |= 0x20;
2836 break;
2837 case SIZE_LONG:
2838 nextword |= 0x30;
2839 break;
2840 }
2841
2842 /* Figure out inner displacement stuff. */
2843 if (opP->mode == POST || opP->mode == PRE)
2844 {
2845 if (cpu_of_arch (current_architecture) & cpu32)
2846 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2847 switch (siz2)
2848 {
2849 case SIZE_UNSPEC:
2850 if (isvar (&opP->odisp)
2851 ? m68k_rel32
2852 : ! issword (outro))
2853 {
2854 siz2 = SIZE_LONG;
2855 nextword |= 0x3;
2856 }
2857 else if (! isvar (&opP->odisp) && outro == 0)
2858 nextword |= 0x1;
2859 else
2860 {
2861 nextword |= 0x2;
2862 siz2 = SIZE_WORD;
2863 }
2864 break;
2865 case 1:
2866 as_warn (_(":b not permitted; defaulting to :w"));
2867 /* Fall through. */
2868 case 2:
2869 nextword |= 0x2;
2870 break;
2871 case 3:
2872 nextword |= 0x3;
2873 break;
2874 }
2875 if (opP->mode == POST
2876 && (nextword & 0x40) == 0)
2877 nextword |= 0x04;
2878 }
2879 addword (nextword);
2880
2881 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2882 {
2883 if (opP->reg == PC || opP->reg == ZPC)
2884 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2885 else
2886 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2887 }
2888 if (siz1 == SIZE_LONG)
2889 addword (baseo >> 16);
2890 if (siz1 != SIZE_UNSPEC)
2891 addword (baseo);
2892
2893 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2894 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2895 if (siz2 == SIZE_LONG)
2896 addword (outro >> 16);
2897 if (siz2 != SIZE_UNSPEC)
2898 addword (outro);
2899
2900 break;
2901
2902 case ABSL:
2903 nextword = get_num (&opP->disp, 90);
2904 switch (opP->disp.size)
2905 {
2906 default:
2907 abort ();
2908 case SIZE_UNSPEC:
2909 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2910 {
2911 tmpreg = 0x38; /* 7.0 */
2912 addword (nextword);
2913 break;
2914 }
2915 if (isvar (&opP->disp)
2916 && !subs (&opP->disp)
2917 && adds (&opP->disp)
2918 /* If the displacement needs pic relocation it
2919 cannot be relaxed. */
2920 && opP->disp.pic_reloc == pic_none
2921 && !flag_long_jumps
2922 && !strchr ("~%&$?", s[0]))
2923 {
2924 tmpreg = 0x3A; /* 7.2 */
2925 add_frag (adds (&opP->disp),
2926 SEXT (offs (&opP->disp)),
2927 TAB (ABSTOPCREL, SZ_UNDEF));
2928 break;
2929 }
2930 /* Fall through. */
2931 case SIZE_LONG:
2932 if (isvar (&opP->disp))
2933 add_fix ('l', &opP->disp, 0, 0);
2934
2935 tmpreg = 0x39;/* 7.1 mode */
2936 addword (nextword >> 16);
2937 addword (nextword);
2938 break;
2939
2940 case SIZE_BYTE:
2941 as_bad (_("unsupported byte value; use a different suffix"));
2942 /* Fall through. */
2943
2944 case SIZE_WORD:
2945 if (isvar (&opP->disp))
2946 add_fix ('w', &opP->disp, 0, 0);
2947
2948 tmpreg = 0x38;/* 7.0 mode */
2949 addword (nextword);
2950 break;
2951 }
2952 break;
2953 case CONTROL:
2954 case FPREG:
2955 default:
2956 as_bad (_("unknown/incorrect operand"));
2957 /* abort (); */
2958 }
2959
2960 /* If s[0] is '4', then this is for the mac instructions
2961 that can have a trailing_ampersand set. If so, set 0x100
2962 bit on tmpreg so install_gen_operand can check for it and
2963 set the appropriate bit (word2, bit 5). */
2964 if (s[0] == '4')
2965 {
2966 if (opP->trailing_ampersand)
2967 tmpreg |= 0x100;
2968 }
2969 install_gen_operand (s[1], tmpreg);
2970 break;
2971
2972 case '#':
2973 case '^':
2974 switch (s[1])
2975 { /* JF: I hate floating point! */
2976 case 'j':
2977 tmpreg = 70;
2978 break;
2979 case '8':
2980 tmpreg = 20;
2981 break;
2982 case 'C':
2983 tmpreg = 50;
2984 break;
2985 case '3':
2986 default:
2987 tmpreg = 90;
2988 break;
2989 }
2990 tmpreg = get_num (&opP->disp, tmpreg);
2991 if (isvar (&opP->disp))
2992 add_fix (s[1], &opP->disp, 0, 0);
2993 switch (s[1])
2994 {
2995 case 'b': /* Danger: These do no check for
2996 certain types of overflow.
2997 user beware! */
2998 if (!isbyte (tmpreg))
2999 opP->error = _("out of range");
3000 insop (tmpreg, opcode);
3001 if (isvar (&opP->disp))
3002 the_ins.reloc[the_ins.nrel - 1].n =
3003 (opcode->m_codenum) * 2 + 1;
3004 break;
3005 case 'B':
3006 if (!issbyte (tmpreg))
3007 opP->error = _("out of range");
3008 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3009 if (isvar (&opP->disp))
3010 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3011 break;
3012 case 'w':
3013 if (!isword (tmpreg))
3014 opP->error = _("out of range");
3015 insop (tmpreg, opcode);
3016 if (isvar (&opP->disp))
3017 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3018 break;
3019 case 'W':
3020 if (!issword (tmpreg))
3021 opP->error = _("out of range");
3022 insop (tmpreg, opcode);
3023 if (isvar (&opP->disp))
3024 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3025 break;
3026 case 'l':
3027 /* Because of the way insop works, we put these two out
3028 backwards. */
3029 insop (tmpreg, opcode);
3030 insop (tmpreg >> 16, opcode);
3031 if (isvar (&opP->disp))
3032 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3033 break;
3034 case '3':
3035 tmpreg &= 0xFF;
3036 /* Fall through. */
3037 case '8':
3038 case 'C':
3039 case 'j':
3040 install_operand (s[1], tmpreg);
3041 break;
3042 default:
3043 abort ();
3044 }
3045 break;
3046
3047 case '+':
3048 case '-':
3049 case 'A':
3050 case 'a':
3051 install_operand (s[1], opP->reg - ADDR);
3052 break;
3053
3054 case 'B':
3055 tmpreg = get_num (&opP->disp, 90);
3056
3057 switch (s[1])
3058 {
3059 case 'B':
3060 add_fix ('B', &opP->disp, 1, -1);
3061 break;
3062 case 'W':
3063 add_fix ('w', &opP->disp, 1, 0);
3064 addword (0);
3065 break;
3066 case 'L':
3067 long_branch:
3068 the_ins.opcode[0] |= 0xff;
3069 add_fix ('l', &opP->disp, 1, 0);
3070 addword (0);
3071 addword (0);
3072 break;
3073 case 'g': /* Conditional branch */
3074 have_disp = HAVE_LONG_CALL (current_architecture);
3075 goto var_branch;
3076
3077 case 'b': /* Unconditional branch */
3078 have_disp = HAVE_LONG_BRANCH (current_architecture);
3079 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
3080 goto var_branch;
3081
3082 case 's': /* Unconditional subroutine */
3083 have_disp = HAVE_LONG_CALL (current_architecture);
3084
3085 var_branch:
3086 if (subs (&opP->disp) /* We can't relax it. */
3087 /* If the displacement needs pic relocation it cannot be
3088 relaxed. */
3089 || opP->disp.pic_reloc != pic_none)
3090 {
3091 if (!have_disp)
3092 as_warn (_("Can't use long branches on this architecture"));
3093 goto long_branch;
3094 }
3095
3096 /* This could either be a symbol, or an absolute
3097 address. If it's an absolute address, turn it into
3098 an absolute jump right here and keep it out of the
3099 relaxer. */
3100 if (adds (&opP->disp) == 0)
3101 {
3102 if (the_ins.opcode[0] == 0x6000) /* jbra */
3103 the_ins.opcode[0] = 0x4EF9;
3104 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3105 the_ins.opcode[0] = 0x4EB9;
3106 else /* jCC */
3107 {
3108 the_ins.opcode[0] ^= 0x0100;
3109 the_ins.opcode[0] |= 0x0006;
3110 addword (0x4EF9);
3111 }
3112 add_fix ('l', &opP->disp, 0, 0);
3113 addword (0);
3114 addword (0);
3115 break;
3116 }
3117
3118 /* Now we know it's going into the relaxer. Now figure
3119 out which mode. We try in this order of preference:
3120 long branch, absolute jump, byte/word branches only. */
3121 if (have_disp)
3122 add_frag (adds (&opP->disp),
3123 SEXT (offs (&opP->disp)),
3124 TAB (BRANCHBWL, SZ_UNDEF));
3125 else if (! flag_keep_pcrel)
3126 {
3127 if ((the_ins.opcode[0] == 0x6000)
3128 || (the_ins.opcode[0] == 0x6100))
3129 add_frag (adds (&opP->disp),
3130 SEXT (offs (&opP->disp)),
3131 TAB (BRABSJUNC, SZ_UNDEF));
3132 else
3133 add_frag (adds (&opP->disp),
3134 SEXT (offs (&opP->disp)),
3135 TAB (BRABSJCOND, SZ_UNDEF));
3136 }
3137 else
3138 add_frag (adds (&opP->disp),
3139 SEXT (offs (&opP->disp)),
3140 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3141 : TAB (BRANCHBW, SZ_UNDEF)));
3142 break;
3143 case 'w':
3144 if (isvar (&opP->disp))
3145 {
3146 /* Check for DBcc instructions. We can relax them,
3147 but only if we have long branches and/or absolute
3148 jumps. */
3149 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3150 && (HAVE_LONG_BRANCH (current_architecture)
3151 || ! flag_keep_pcrel))
3152 {
3153 if (HAVE_LONG_BRANCH (current_architecture))
3154 add_frag (adds (&opP->disp),
3155 SEXT (offs (&opP->disp)),
3156 TAB (DBCCLBR, SZ_UNDEF));
3157 else
3158 add_frag (adds (&opP->disp),
3159 SEXT (offs (&opP->disp)),
3160 TAB (DBCCABSJ, SZ_UNDEF));
3161 break;
3162 }
3163 add_fix ('w', &opP->disp, 1, 0);
3164 }
3165 addword (0);
3166 break;
3167 case 'C': /* Fixed size LONG coproc branches. */
3168 add_fix ('l', &opP->disp, 1, 0);
3169 addword (0);
3170 addword (0);
3171 break;
3172 case 'c': /* Var size Coprocesssor branches. */
3173 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3174 {
3175 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3176 add_fix ('l', &opP->disp, 1, 0);
3177 addword (0);
3178 addword (0);
3179 }
3180 else
3181 add_frag (adds (&opP->disp),
3182 SEXT (offs (&opP->disp)),
3183 TAB (FBRANCH, SZ_UNDEF));
3184 break;
3185 default:
3186 abort ();
3187 }
3188 break;
3189
3190 case 'C': /* Ignore it. */
3191 break;
3192
3193 case 'd': /* JF this is a kludge. */
3194 install_operand ('s', opP->reg - ADDR);
3195 tmpreg = get_num (&opP->disp, 90);
3196 if (!issword (tmpreg))
3197 {
3198 as_warn (_("Expression out of range, using 0"));
3199 tmpreg = 0;
3200 }
3201 addword (tmpreg);
3202 break;
3203
3204 case 'D':
3205 install_operand (s[1], opP->reg - DATA);
3206 break;
3207
3208 case 'e': /* EMAC ACCx, reg/reg. */
3209 install_operand (s[1], opP->reg - ACC);
3210 break;
3211
3212 case 'E': /* Ignore it. */
3213 break;
3214
3215 case 'F':
3216 install_operand (s[1], opP->reg - FP0);
3217 break;
3218
3219 case 'g': /* EMAC ACCEXTx. */
3220 install_operand (s[1], opP->reg - ACCEXT01);
3221 break;
3222
3223 case 'G': /* Ignore it. */
3224 case 'H':
3225 break;
3226
3227 case 'I':
3228 tmpreg = opP->reg - COP0;
3229 install_operand (s[1], tmpreg);
3230 break;
3231
3232 case 'i': /* MAC/EMAC scale factor. */
3233 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3234 break;
3235
3236 case 'J': /* JF foo. */
3237 switch (opP->reg)
3238 {
3239 case SFC:
3240 tmpreg = 0x000;
3241 break;
3242 case DFC:
3243 tmpreg = 0x001;
3244 break;
3245 case CACR:
3246 tmpreg = 0x002;
3247 break;
3248 case TC:
3249 case ASID:
3250 tmpreg = 0x003;
3251 break;
3252 case ACR0:
3253 case ITT0:
3254 tmpreg = 0x004;
3255 break;
3256 case ACR1:
3257 case ITT1:
3258 tmpreg = 0x005;
3259 break;
3260 case ACR2:
3261 case DTT0:
3262 tmpreg = 0x006;
3263 break;
3264 case ACR3:
3265 case DTT1:
3266 tmpreg = 0x007;
3267 break;
3268 case BUSCR:
3269 case MMUBAR:
3270 tmpreg = 0x008;
3271 break;
3272 case RGPIOBAR:
3273 tmpreg = 0x009;
3274 break;
3275 case ACR4:
3276 case ACR5:
3277 case ACR6:
3278 case ACR7:
3279 tmpreg = 0x00c + (opP->reg - ACR4);
3280 break;
3281
3282 case USP:
3283 tmpreg = 0x800;
3284 break;
3285 case VBR:
3286 tmpreg = 0x801;
3287 break;
3288 case CAAR:
3289 case CPUCR:
3290 tmpreg = 0x802;
3291 break;
3292 case MSP:
3293 tmpreg = 0x803;
3294 break;
3295 case ISP:
3296 tmpreg = 0x804;
3297 break;
3298 case MMUSR:
3299 tmpreg = 0x805;
3300 break;
3301 case URP:
3302 tmpreg = 0x806;
3303 break;
3304 case SRP:
3305 tmpreg = 0x807;
3306 break;
3307 case PCR:
3308 tmpreg = 0x808;
3309 break;
3310 case ROMBAR:
3311 case ROMBAR0:
3312 tmpreg = 0xC00;
3313 break;
3314 case ROMBAR1:
3315 tmpreg = 0xC01;
3316 break;
3317 case FLASHBAR:
3318 case RAMBAR0:
3319 case RAMBAR_ALT:
3320 tmpreg = 0xC04;
3321 break;
3322 case RAMBAR:
3323 case RAMBAR1:
3324 tmpreg = 0xC05;
3325 break;
3326 case MPCR:
3327 tmpreg = 0xC0C;
3328 break;
3329 case EDRAMBAR:
3330 tmpreg = 0xC0D;
3331 break;
3332 case MBAR0:
3333 case MBAR2:
3334 case SECMBAR:
3335 tmpreg = 0xC0E;
3336 break;
3337 case MBAR1:
3338 case MBAR:
3339 tmpreg = 0xC0F;
3340 break;
3341 case PCR1U0:
3342 tmpreg = 0xD02;
3343 break;
3344 case PCR1L0:
3345 tmpreg = 0xD03;
3346 break;
3347 case PCR2U0:
3348 tmpreg = 0xD04;
3349 break;
3350 case PCR2L0:
3351 tmpreg = 0xD05;
3352 break;
3353 case PCR3U0:
3354 tmpreg = 0xD06;
3355 break;
3356 case PCR3L0:
3357 tmpreg = 0xD07;
3358 break;
3359 case PCR1L1:
3360 tmpreg = 0xD0A;
3361 break;
3362 case PCR1U1:
3363 tmpreg = 0xD0B;
3364 break;
3365 case PCR2L1:
3366 tmpreg = 0xD0C;
3367 break;
3368 case PCR2U1:
3369 tmpreg = 0xD0D;
3370 break;
3371 case PCR3L1:
3372 tmpreg = 0xD0E;
3373 break;
3374 case PCR3U1:
3375 tmpreg = 0xD0F;
3376 break;
3377 case CAC:
3378 tmpreg = 0xFFE;
3379 break;
3380 case MBO:
3381 tmpreg = 0xFFF;
3382 break;
3383 default:
3384 abort ();
3385 }
3386 install_operand (s[1], tmpreg);
3387 break;
3388
3389 case 'k':
3390 tmpreg = get_num (&opP->disp, 55);
3391 install_operand (s[1], tmpreg & 0x7f);
3392 break;
3393
3394 case 'l':
3395 tmpreg = opP->mask;
3396 if (s[1] == 'w')
3397 {
3398 if (tmpreg & 0x7FF0000)
3399 as_bad (_("Floating point register in register list"));
3400 insop (reverse_16_bits (tmpreg), opcode);
3401 }
3402 else
3403 {
3404 if (tmpreg & 0x700FFFF)
3405 as_bad (_("Wrong register in floating-point reglist"));
3406 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3407 }
3408 break;
3409
3410 case 'L':
3411 tmpreg = opP->mask;
3412 if (s[1] == 'w')
3413 {
3414 if (tmpreg & 0x7FF0000)
3415 as_bad (_("Floating point register in register list"));
3416 insop (tmpreg, opcode);
3417 }
3418 else if (s[1] == '8')
3419 {
3420 if (tmpreg & 0x0FFFFFF)
3421 as_bad (_("incorrect register in reglist"));
3422 install_operand (s[1], tmpreg >> 24);
3423 }
3424 else
3425 {
3426 if (tmpreg & 0x700FFFF)
3427 as_bad (_("wrong register in floating-point reglist"));
3428 else
3429 install_operand (s[1], tmpreg >> 16);
3430 }
3431 break;
3432
3433 case 'M':
3434 install_operand (s[1], get_num (&opP->disp, 60));
3435 break;
3436
3437 case 'O':
3438 tmpreg = ((opP->mode == DREG)
3439 ? 0x20 + (int) (opP->reg - DATA)
3440 : (get_num (&opP->disp, 40) & 0x1F));
3441 install_operand (s[1], tmpreg);
3442 break;
3443
3444 case 'Q':
3445 tmpreg = get_num (&opP->disp, 10);
3446 if (tmpreg == 8)
3447 tmpreg = 0;
3448 install_operand (s[1], tmpreg);
3449 break;
3450
3451 case 'R':
3452 /* This depends on the fact that ADDR registers are eight
3453 more than their corresponding DATA regs, so the result
3454 will have the ADDR_REG bit set. */
3455 install_operand (s[1], opP->reg - DATA);
3456 break;
3457
3458 case 'r':
3459 if (opP->mode == AINDR)
3460 install_operand (s[1], opP->reg - DATA);
3461 else
3462 install_operand (s[1], opP->index.reg - DATA);
3463 break;
3464
3465 case 's':
3466 if (opP->reg == FPI)
3467 tmpreg = 0x1;
3468 else if (opP->reg == FPS)
3469 tmpreg = 0x2;
3470 else if (opP->reg == FPC)
3471 tmpreg = 0x4;
3472 else
3473 abort ();
3474 install_operand (s[1], tmpreg);
3475 break;
3476
3477 case 'S': /* Ignore it. */
3478 break;
3479
3480 case 'T':
3481 install_operand (s[1], get_num (&opP->disp, 30));
3482 break;
3483
3484 case 'U': /* Ignore it. */
3485 break;
3486
3487 case 'c':
3488 switch (opP->reg)
3489 {
3490 case NC:
3491 tmpreg = 0;
3492 break;
3493 case DC:
3494 tmpreg = 1;
3495 break;
3496 case IC:
3497 tmpreg = 2;
3498 break;
3499 case BC:
3500 tmpreg = 3;
3501 break;
3502 default:
3503 as_fatal (_("failed sanity check"));
3504 } /* switch on cache token. */
3505 install_operand (s[1], tmpreg);
3506 break;
3507 #ifndef NO_68851
3508 /* JF: These are out of order, I fear. */
3509 case 'f':
3510 switch (opP->reg)
3511 {
3512 case SFC:
3513 tmpreg = 0;
3514 break;
3515 case DFC:
3516 tmpreg = 1;
3517 break;
3518 default:
3519 abort ();
3520 }
3521 install_operand (s[1], tmpreg);
3522 break;
3523
3524 case '0':
3525 case '1':
3526 case '2':
3527 switch (opP->reg)
3528 {
3529 case TC:
3530 tmpreg = 0;
3531 break;
3532 case CAL:
3533 tmpreg = 4;
3534 break;
3535 case VAL:
3536 tmpreg = 5;
3537 break;
3538 case SCC:
3539 tmpreg = 6;
3540 break;
3541 case AC:
3542 tmpreg = 7;
3543 break;
3544 default:
3545 abort ();
3546 }
3547 install_operand (s[1], tmpreg);
3548 break;
3549
3550 case 'V':
3551 if (opP->reg == VAL)
3552 break;
3553 abort ();
3554
3555 case 'W':
3556 switch (opP->reg)
3557 {
3558 case DRP:
3559 tmpreg = 1;
3560 break;
3561 case SRP:
3562 tmpreg = 2;
3563 break;
3564 case CRP:
3565 tmpreg = 3;
3566 break;
3567 default:
3568 abort ();
3569 }
3570 install_operand (s[1], tmpreg);
3571 break;
3572
3573 case 'X':
3574 switch (opP->reg)
3575 {
3576 case BAD:
3577 case BAD + 1:
3578 case BAD + 2:
3579 case BAD + 3:
3580 case BAD + 4:
3581 case BAD + 5:
3582 case BAD + 6:
3583 case BAD + 7:
3584 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3585 break;
3586
3587 case BAC:
3588 case BAC + 1:
3589 case BAC + 2:
3590 case BAC + 3:
3591 case BAC + 4:
3592 case BAC + 5:
3593 case BAC + 6:
3594 case BAC + 7:
3595 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3596 break;
3597
3598 default:
3599 abort ();
3600 }
3601 install_operand (s[1], tmpreg);
3602 break;
3603 case 'Y':
3604 know (opP->reg == PSR);
3605 break;
3606 case 'Z':
3607 know (opP->reg == PCSR);
3608 break;
3609 #endif /* m68851 */
3610 case '3':
3611 switch (opP->reg)
3612 {
3613 case TT0:
3614 tmpreg = 2;
3615 break;
3616 case TT1:
3617 tmpreg = 3;
3618 break;
3619 default:
3620 abort ();
3621 }
3622 install_operand (s[1], tmpreg);
3623 break;
3624 case 't':
3625 tmpreg = get_num (&opP->disp, 20);
3626 install_operand (s[1], tmpreg);
3627 break;
3628 case '_': /* used only for move16 absolute 32-bit address. */
3629 if (isvar (&opP->disp))
3630 add_fix ('l', &opP->disp, 0, 0);
3631 tmpreg = get_num (&opP->disp, 90);
3632 addword (tmpreg >> 16);
3633 addword (tmpreg & 0xFFFF);
3634 break;
3635 case 'u':
3636 install_operand (s[1], opP->reg - DATA0L);
3637 opP->reg -= (DATA0L);
3638 opP->reg &= 0x0F; /* remove upper/lower bit. */
3639 break;
3640 case 'x':
3641 tmpreg = get_num (&opP->disp, 80);
3642 if (tmpreg == -1)
3643 tmpreg = 0;
3644 install_operand (s[1], tmpreg);
3645 break;
3646 case 'j':
3647 tmpreg = get_num (&opP->disp, 10);
3648 install_operand (s[1], tmpreg - 1);
3649 break;
3650 case 'K':
3651 tmpreg = get_num (&opP->disp, 65);
3652 install_operand (s[1], tmpreg);
3653 break;
3654 default:
3655 abort ();
3656 }
3657 }
3658
3659 /* By the time when get here (FINALLY) the_ins contains the complete
3660 instruction, ready to be emitted. . . */
3661 }
3662
3663 static int
3664 reverse_16_bits (int in)
3665 {
3666 int out = 0;
3667 int n;
3668
3669 static int mask[16] =
3670 {
3671 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3672 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3673 };
3674 for (n = 0; n < 16; n++)
3675 {
3676 if (in & mask[n])
3677 out |= mask[15 - n];
3678 }
3679 return out;
3680 } /* reverse_16_bits() */
3681
3682 static int
3683 reverse_8_bits (int in)
3684 {
3685 int out = 0;
3686 int n;
3687
3688 static int mask[8] =
3689 {
3690 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3691 };
3692
3693 for (n = 0; n < 8; n++)
3694 {
3695 if (in & mask[n])
3696 out |= mask[7 - n];
3697 }
3698 return out;
3699 } /* reverse_8_bits() */
3700
3701 /* Cause an extra frag to be generated here, inserting up to
3702 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3703 generated; its primary type is rs_machine_dependent.
3704
3705 The TYPE parameter is also used by md_convert_frag_1 and
3706 md_estimate_size_before_relax. The appropriate type of fixup will
3707 be emitted by md_convert_frag_1.
3708
3709 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3710 static void
3711 install_operand (int mode, int val)
3712 {
3713 switch (mode)
3714 {
3715 case 's':
3716 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3717 break;
3718 case 'd':
3719 the_ins.opcode[0] |= val << 9;
3720 break;
3721 case 'E':
3722 the_ins.opcode[1] |= val << 9;
3723 break;
3724 case '1':
3725 the_ins.opcode[1] |= val << 12;
3726 break;
3727 case '2':
3728 the_ins.opcode[1] |= val << 6;
3729 break;
3730 case '3':
3731 the_ins.opcode[1] |= val;
3732 break;
3733 case '4':
3734 the_ins.opcode[2] |= val << 12;
3735 break;
3736 case '5':
3737 the_ins.opcode[2] |= val << 6;
3738 break;
3739 case '6':
3740 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3741 three words long! */
3742 the_ins.numo++;
3743 the_ins.opcode[2] |= val;
3744 break;
3745 case '7':
3746 the_ins.opcode[1] |= val << 7;
3747 break;
3748 case '8':
3749 the_ins.opcode[1] |= val << 10;
3750 break;
3751 #ifndef NO_68851
3752 case '9':
3753 the_ins.opcode[1] |= val << 5;
3754 break;
3755 #endif
3756
3757 case 't':
3758 the_ins.opcode[1] |= (val << 10) | (val << 7);
3759 break;
3760 case 'D':
3761 the_ins.opcode[1] |= (val << 12) | val;
3762 break;
3763 case 'g':
3764 the_ins.opcode[0] |= val = 0xff;
3765 break;
3766 case 'i':
3767 the_ins.opcode[0] |= val << 9;
3768 break;
3769 case 'C':
3770 the_ins.opcode[1] |= val;
3771 break;
3772 case 'j':
3773 the_ins.opcode[1] |= val;
3774 the_ins.numo++; /* What a hack. */
3775 break;
3776 case 'k':
3777 the_ins.opcode[1] |= val << 4;
3778 break;
3779 case 'b':
3780 case 'w':
3781 case 'W':
3782 case 'l':
3783 break;
3784 case 'e':
3785 the_ins.opcode[0] |= (val << 6);
3786 break;
3787 case 'L':
3788 the_ins.opcode[1] = (val >> 16);
3789 the_ins.opcode[2] = val & 0xffff;
3790 break;
3791 case 'm':
3792 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3793 the_ins.opcode[0] |= ((val & 0x7) << 9);
3794 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3795 break;
3796 case 'n': /* MAC/EMAC Rx on !load. */
3797 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3798 the_ins.opcode[0] |= ((val & 0x7) << 9);
3799 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3800 break;
3801 case 'o': /* MAC/EMAC Rx on load. */
3802 the_ins.opcode[1] |= val << 12;
3803 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3804 break;
3805 case 'M': /* MAC/EMAC Ry on !load. */
3806 the_ins.opcode[0] |= (val & 0xF);
3807 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3808 break;
3809 case 'N': /* MAC/EMAC Ry on load. */
3810 the_ins.opcode[1] |= (val & 0xF);
3811 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3812 break;
3813 case 'h':
3814 the_ins.opcode[1] |= ((val != 1) << 10);
3815 break;
3816 case 'F':
3817 the_ins.opcode[0] |= ((val & 0x3) << 9);
3818 break;
3819 case 'f':
3820 the_ins.opcode[0] |= ((val & 0x3) << 0);
3821 break;
3822 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3823 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3824 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3825 break;
3826 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3827 the_ins.opcode[0] |= ((val & 0x1) << 7);
3828 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3829 break;
3830 case 'I':
3831 the_ins.opcode[1] |= ((val & 0x3) << 9);
3832 break;
3833 case ']':
3834 the_ins.opcode[0] |= (val & 0x1) <<10;
3835 break;
3836 case 'c':
3837 default:
3838 as_fatal (_("failed sanity check."));
3839 }
3840 }
3841
3842 static void
3843 install_gen_operand (int mode, int val)
3844 {
3845 switch (mode)
3846 {
3847 case '/': /* Special for mask loads for mac/msac insns with
3848 possible mask; trailing_ampersand set in bit 8. */
3849 the_ins.opcode[0] |= (val & 0x3f);
3850 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3851 break;
3852 case 's':
3853 the_ins.opcode[0] |= val;
3854 break;
3855 case 'd':
3856 /* This is a kludge!!! */
3857 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3858 break;
3859 case 'b':
3860 case 'w':
3861 case 'l':
3862 case 'f':
3863 case 'F':
3864 case 'x':
3865 case 'p':
3866 the_ins.opcode[0] |= val;
3867 break;
3868 /* more stuff goes here. */
3869 default:
3870 as_fatal (_("failed sanity check."));
3871 }
3872 }
3873
3874 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3875 then deal with the bitfield hack. */
3876
3877 static char *
3878 crack_operand (char *str, struct m68k_op *opP)
3879 {
3880 int parens;
3881 int c;
3882 char *beg_str;
3883 int inquote = 0;
3884
3885 if (!str)
3886 {
3887 return str;
3888 }
3889 beg_str = str;
3890 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3891 {
3892 if (! inquote)
3893 {
3894 if (*str == '(')
3895 parens++;
3896 else if (*str == ')')
3897 {
3898 if (!parens)
3899 { /* ERROR. */
3900 opP->error = _("Extra )");
3901 return str;
3902 }
3903 --parens;
3904 }
3905 }
3906 if (flag_mri && *str == '\'')
3907 inquote = ! inquote;
3908 }
3909 if (!*str && parens)
3910 { /* ERROR. */
3911 opP->error = _("Missing )");
3912 return str;
3913 }
3914 c = *str;
3915 *str = '\0';
3916 if (m68k_ip_op (beg_str, opP) != 0)
3917 {
3918 *str = c;
3919 return str;
3920 }
3921 *str = c;
3922 if (c == '}')
3923 c = *++str; /* JF bitfield hack. */
3924 if (c)
3925 {
3926 c = *++str;
3927 if (!c)
3928 as_bad (_("Missing operand"));
3929 }
3930
3931 /* Detect MRI REG symbols and convert them to REGLSTs. */
3932 if (opP->mode == CONTROL && (int)opP->reg < 0)
3933 {
3934 opP->mode = REGLST;
3935 opP->mask = ~(int)opP->reg;
3936 opP->reg = 0;
3937 }
3938
3939 return str;
3940 }
3941
3942 /* This is the guts of the machine-dependent assembler. STR points to a
3943 machine dependent instruction. This function is supposed to emit
3944 the frags/bytes it assembles to.
3945 */
3946
3947 static void
3948 insert_reg (const char *regname, int regnum)
3949 {
3950 char buf[100];
3951 int i;
3952
3953 #ifdef REGISTER_PREFIX
3954 if (!flag_reg_prefix_optional)
3955 {
3956 buf[0] = REGISTER_PREFIX;
3957 strcpy (buf + 1, regname);
3958 regname = buf;
3959 }
3960 #endif
3961
3962 symbol_table_insert (symbol_new (regname, reg_section,
3963 &zero_address_frag, regnum));
3964
3965 for (i = 0; regname[i]; i++)
3966 buf[i] = TOUPPER (regname[i]);
3967 buf[i] = '\0';
3968
3969 symbol_table_insert (symbol_new (buf, reg_section,
3970 &zero_address_frag, regnum));
3971 }
3972
3973 struct init_entry
3974 {
3975 const char *name;
3976 int number;
3977 };
3978
3979 static const struct init_entry init_table[] =
3980 {
3981 { "d0", DATA0 },
3982 { "d1", DATA1 },
3983 { "d2", DATA2 },
3984 { "d3", DATA3 },
3985 { "d4", DATA4 },
3986 { "d5", DATA5 },
3987 { "d6", DATA6 },
3988 { "d7", DATA7 },
3989 { "a0", ADDR0 },
3990 { "a1", ADDR1 },
3991 { "a2", ADDR2 },
3992 { "a3", ADDR3 },
3993 { "a4", ADDR4 },
3994 { "a5", ADDR5 },
3995 { "a6", ADDR6 },
3996 { "fp", ADDR6 },
3997 { "a7", ADDR7 },
3998 { "sp", ADDR7 },
3999 { "ssp", ADDR7 },
4000 { "fp0", FP0 },
4001 { "fp1", FP1 },
4002 { "fp2", FP2 },
4003 { "fp3", FP3 },
4004 { "fp4", FP4 },
4005 { "fp5", FP5 },
4006 { "fp6", FP6 },
4007 { "fp7", FP7 },
4008 { "fpi", FPI },
4009 { "fpiar", FPI },
4010 { "fpc", FPI },
4011 { "fps", FPS },
4012 { "fpsr", FPS },
4013 { "fpc", FPC },
4014 { "fpcr", FPC },
4015 { "control", FPC },
4016 { "status", FPS },
4017 { "iaddr", FPI },
4018
4019 { "cop0", COP0 },
4020 { "cop1", COP1 },
4021 { "cop2", COP2 },
4022 { "cop3", COP3 },
4023 { "cop4", COP4 },
4024 { "cop5", COP5 },
4025 { "cop6", COP6 },
4026 { "cop7", COP7 },
4027 { "pc", PC },
4028 { "zpc", ZPC },
4029 { "sr", SR },
4030
4031 { "ccr", CCR },
4032 { "cc", CCR },
4033
4034 { "acc", ACC },
4035 { "acc0", ACC },
4036 { "acc1", ACC1 },
4037 { "acc2", ACC2 },
4038 { "acc3", ACC3 },
4039 { "accext01", ACCEXT01 },
4040 { "accext23", ACCEXT23 },
4041 { "macsr", MACSR },
4042 { "mask", MASK },
4043
4044 /* Control registers. */
4045 { "sfc", SFC }, /* Source Function Code. */
4046 { "sfcr", SFC },
4047 { "dfc", DFC }, /* Destination Function Code. */
4048 { "dfcr", DFC },
4049 { "cacr", CACR }, /* Cache Control Register. */
4050 { "caar", CAAR }, /* Cache Address Register. */
4051 { "cpucr", CPUCR }, /* CPU Control Register. */
4052
4053 { "usp", USP }, /* User Stack Pointer. */
4054 { "vbr", VBR }, /* Vector Base Register. */
4055 { "msp", MSP }, /* Master Stack Pointer. */
4056 { "isp", ISP }, /* Interrupt Stack Pointer. */
4057
4058 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4059 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4060 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4061 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
4062
4063 /* 68ec040 versions of same */
4064 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4065 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4066 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4067 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
4068
4069 /* Coldfire versions of same. The ColdFire programmer's reference
4070 manual indicated that the order is 2,3,0,1, but Ken Rose
4071 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4072 { "acr0", ACR0 }, /* Access Control Unit 0. */
4073 { "acr1", ACR1 }, /* Access Control Unit 1. */
4074 { "acr2", ACR2 }, /* Access Control Unit 2. */
4075 { "acr3", ACR3 }, /* Access Control Unit 3. */
4076 { "acr4", ACR4 }, /* Access Control Unit 4. */
4077 { "acr5", ACR5 }, /* Access Control Unit 5. */
4078 { "acr6", ACR6 }, /* Access Control Unit 6. */
4079 { "acr7", ACR7 }, /* Access Control Unit 7. */
4080
4081 { "tc", TC }, /* MMU Translation Control Register. */
4082 { "tcr", TC },
4083 { "asid", ASID },
4084
4085 { "mmusr", MMUSR }, /* MMU Status Register. */
4086 { "srp", SRP }, /* User Root Pointer. */
4087 { "urp", URP }, /* Supervisor Root Pointer. */
4088
4089 { "buscr", BUSCR },
4090 { "mmubar", MMUBAR },
4091 { "pcr", PCR },
4092
4093 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4094 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4095 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4096 { "mbar", MBAR }, /* Module Base Address Register. */
4097
4098 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4099 { "mbar1", MBAR1 }, /* mcfv4e registers. */
4100 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
4101 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4102 { "mpcr", MPCR }, /* mcfv4e registers. */
4103 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4104 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4105 { "asid", TC }, /* mcfv4e registers. */
4106 { "mmubar", BUSCR }, /* mcfv4e registers. */
4107 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4108 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4109 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4110 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4111 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4112 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4113 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4114 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4115 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4116 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4117 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4118 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4119
4120 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4121 { "rambar", RAMBAR }, /* mcf528x registers. */
4122
4123 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4124
4125 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4126
4127 { "cac", CAC }, /* fido registers. */
4128 { "mbb", MBO }, /* fido registers (obsolete). */
4129 { "mbo", MBO }, /* fido registers. */
4130 /* End of control registers. */
4131
4132 { "ac", AC },
4133 { "bc", BC },
4134 { "cal", CAL },
4135 { "crp", CRP },
4136 { "drp", DRP },
4137 { "pcsr", PCSR },
4138 { "psr", PSR },
4139 { "scc", SCC },
4140 { "val", VAL },
4141 { "bad0", BAD0 },
4142 { "bad1", BAD1 },
4143 { "bad2", BAD2 },
4144 { "bad3", BAD3 },
4145 { "bad4", BAD4 },
4146 { "bad5", BAD5 },
4147 { "bad6", BAD6 },
4148 { "bad7", BAD7 },
4149 { "bac0", BAC0 },
4150 { "bac1", BAC1 },
4151 { "bac2", BAC2 },
4152 { "bac3", BAC3 },
4153 { "bac4", BAC4 },
4154 { "bac5", BAC5 },
4155 { "bac6", BAC6 },
4156 { "bac7", BAC7 },
4157
4158 { "ic", IC },
4159 { "dc", DC },
4160 { "nc", NC },
4161
4162 { "tt0", TT0 },
4163 { "tt1", TT1 },
4164 /* 68ec030 versions of same. */
4165 { "ac0", TT0 },
4166 { "ac1", TT1 },
4167 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4168 { "acusr", PSR },
4169
4170 /* Suppressed data and address registers. */
4171 { "zd0", ZDATA0 },
4172 { "zd1", ZDATA1 },
4173 { "zd2", ZDATA2 },
4174 { "zd3", ZDATA3 },
4175 { "zd4", ZDATA4 },
4176 { "zd5", ZDATA5 },
4177 { "zd6", ZDATA6 },
4178 { "zd7", ZDATA7 },
4179 { "za0", ZADDR0 },
4180 { "za1", ZADDR1 },
4181 { "za2", ZADDR2 },
4182 { "za3", ZADDR3 },
4183 { "za4", ZADDR4 },
4184 { "za5", ZADDR5 },
4185 { "za6", ZADDR6 },
4186 { "za7", ZADDR7 },
4187
4188 /* Upper and lower data and address registers, used by macw and msacw. */
4189 { "d0l", DATA0L },
4190 { "d1l", DATA1L },
4191 { "d2l", DATA2L },
4192 { "d3l", DATA3L },
4193 { "d4l", DATA4L },
4194 { "d5l", DATA5L },
4195 { "d6l", DATA6L },
4196 { "d7l", DATA7L },
4197
4198 { "a0l", ADDR0L },
4199 { "a1l", ADDR1L },
4200 { "a2l", ADDR2L },
4201 { "a3l", ADDR3L },
4202 { "a4l", ADDR4L },
4203 { "a5l", ADDR5L },
4204 { "a6l", ADDR6L },
4205 { "a7l", ADDR7L },
4206
4207 { "d0u", DATA0U },
4208 { "d1u", DATA1U },
4209 { "d2u", DATA2U },
4210 { "d3u", DATA3U },
4211 { "d4u", DATA4U },
4212 { "d5u", DATA5U },
4213 { "d6u", DATA6U },
4214 { "d7u", DATA7U },
4215
4216 { "a0u", ADDR0U },
4217 { "a1u", ADDR1U },
4218 { "a2u", ADDR2U },
4219 { "a3u", ADDR3U },
4220 { "a4u", ADDR4U },
4221 { "a5u", ADDR5U },
4222 { "a6u", ADDR6U },
4223 { "a7u", ADDR7U },
4224
4225 { 0, 0 }
4226 };
4227
4228 static void
4229 init_regtable (void)
4230 {
4231 int i;
4232 for (i = 0; init_table[i].name; i++)
4233 insert_reg (init_table[i].name, init_table[i].number);
4234 }
4235
4236 void
4237 md_assemble (char *str)
4238 {
4239 const char *er;
4240 short *fromP;
4241 char *toP = NULL;
4242 int m, n = 0;
4243 char *to_beg_P;
4244 int shorts_this_frag;
4245 fixS *fixP;
4246
4247 if (!selected_cpu && !selected_arch)
4248 {
4249 /* We've not selected an architecture yet. Set the default
4250 now. We do this lazily so that an initial .cpu or .arch directive
4251 can specify. */
4252 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4253 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4254 }
4255 if (!initialized)
4256 m68k_init_arch ();
4257
4258 /* In MRI mode, the instruction and operands are separated by a
4259 space. Anything following the operands is a comment. The label
4260 has already been removed. */
4261 if (flag_mri)
4262 {
4263 char *s;
4264 int fields = 0;
4265 int infield = 0;
4266 int inquote = 0;
4267
4268 for (s = str; *s != '\0'; s++)
4269 {
4270 if ((*s == ' ' || *s == '\t') && ! inquote)
4271 {
4272 if (infield)
4273 {
4274 ++fields;
4275 if (fields >= 2)
4276 {
4277 *s = '\0';
4278 break;
4279 }
4280 infield = 0;
4281 }
4282 }
4283 else
4284 {
4285 if (! infield)
4286 infield = 1;
4287 if (*s == '\'')
4288 inquote = ! inquote;
4289 }
4290 }
4291 }
4292
4293 memset (&the_ins, '\0', sizeof (the_ins));
4294 m68k_ip (str);
4295 er = the_ins.error;
4296 if (!er)
4297 {
4298 for (n = 0; n < the_ins.numargs; n++)
4299 if (the_ins.operands[n].error)
4300 {
4301 er = the_ins.operands[n].error;
4302 break;
4303 }
4304 }
4305 if (er)
4306 {
4307 as_bad (_("%s -- statement `%s' ignored"), er, str);
4308 return;
4309 }
4310
4311 /* If there is a current label, record that it marks an instruction. */
4312 if (current_label != NULL)
4313 {
4314 current_label->text = 1;
4315 current_label = NULL;
4316 }
4317
4318 /* Tie dwarf2 debug info to the address at the start of the insn. */
4319 dwarf2_emit_insn (0);
4320
4321 if (the_ins.nfrag == 0)
4322 {
4323 /* No frag hacking involved; just put it out. */
4324 toP = frag_more (2 * the_ins.numo);
4325 fromP = &the_ins.opcode[0];
4326 for (m = the_ins.numo; m; --m)
4327 {
4328 md_number_to_chars (toP, (long) (*fromP), 2);
4329 toP += 2;
4330 fromP++;
4331 }
4332 /* Put out symbol-dependent info. */
4333 for (m = 0; m < the_ins.nrel; m++)
4334 {
4335 switch (the_ins.reloc[m].wid)
4336 {
4337 case 'B':
4338 n = 1;
4339 break;
4340 case 'b':
4341 n = 1;
4342 break;
4343 case '3':
4344 n = 1;
4345 break;
4346 case 'w':
4347 case 'W':
4348 n = 2;
4349 break;
4350 case 'l':
4351 n = 4;
4352 break;
4353 default:
4354 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
4355 the_ins.reloc[m].wid);
4356 }
4357
4358 fixP = fix_new_exp (frag_now,
4359 ((toP - frag_now->fr_literal)
4360 - the_ins.numo * 2 + the_ins.reloc[m].n),
4361 n,
4362 &the_ins.reloc[m].exp,
4363 the_ins.reloc[m].pcrel,
4364 get_reloc_code (n, the_ins.reloc[m].pcrel,
4365 the_ins.reloc[m].pic_reloc));
4366 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4367 if (the_ins.reloc[m].wid == 'B')
4368 fixP->fx_signed = 1;
4369 }
4370 return;
4371 }
4372
4373 /* There's some frag hacking. */
4374 {
4375 /* Calculate the max frag size. */
4376 int wid;
4377
4378 wid = 2 * the_ins.fragb[0].fragoff;
4379 for (n = 1; n < the_ins.nfrag; n++)
4380 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4381 /* frag_var part. */
4382 wid += FRAG_VAR_SIZE;
4383 /* Make sure the whole insn fits in one chunk, in particular that
4384 the var part is attached, as we access one byte before the
4385 variable frag for byte branches. */
4386 frag_grow (wid);
4387 }
4388
4389 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4390 {
4391 int wid;
4392
4393 if (n == 0)
4394 wid = 2 * the_ins.fragb[n].fragoff;
4395 else
4396 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4397 toP = frag_more (wid);
4398 to_beg_P = toP;
4399 shorts_this_frag = 0;
4400 for (m = wid / 2; m; --m)
4401 {
4402 md_number_to_chars (toP, (long) (*fromP), 2);
4403 toP += 2;
4404 fromP++;
4405 shorts_this_frag++;
4406 }
4407 for (m = 0; m < the_ins.nrel; m++)
4408 {
4409 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4410 {
4411 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4412 break;
4413 }
4414 wid = the_ins.reloc[m].wid;
4415 if (wid == 0)
4416 continue;
4417 the_ins.reloc[m].wid = 0;
4418 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4419
4420 fixP = fix_new_exp (frag_now,
4421 ((toP - frag_now->fr_literal)
4422 - the_ins.numo * 2 + the_ins.reloc[m].n),
4423 wid,
4424 &the_ins.reloc[m].exp,
4425 the_ins.reloc[m].pcrel,
4426 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4427 the_ins.reloc[m].pic_reloc));
4428 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4429 }
4430 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4431 (relax_substateT) (the_ins.fragb[n].fragty),
4432 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4433 }
4434 gas_assert (the_ins.nfrag >= 1);
4435 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff;
4436 shorts_this_frag = 0;
4437 if (n)
4438 {
4439 toP = frag_more (n * 2);
4440 while (n--)
4441 {
4442 md_number_to_chars (toP, (long) (*fromP), 2);
4443 toP += 2;
4444 fromP++;
4445 shorts_this_frag++;
4446 }
4447 }
4448 for (m = 0; m < the_ins.nrel; m++)
4449 {
4450 int wid;
4451
4452 wid = the_ins.reloc[m].wid;
4453 if (wid == 0)
4454 continue;
4455 the_ins.reloc[m].wid = 0;
4456 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4457
4458 fixP = fix_new_exp (frag_now,
4459 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4460 - shorts_this_frag * 2),
4461 wid,
4462 &the_ins.reloc[m].exp,
4463 the_ins.reloc[m].pcrel,
4464 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4465 the_ins.reloc[m].pic_reloc));
4466 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4467 }
4468 }
4469
4470 /* Comparison function used by qsort to rank the opcode entries by name. */
4471
4472 static int
4473 m68k_compare_opcode (const void * v1, const void * v2)
4474 {
4475 struct m68k_opcode * op1, * op2;
4476 int ret;
4477
4478 if (v1 == v2)
4479 return 0;
4480
4481 op1 = *(struct m68k_opcode **) v1;
4482 op2 = *(struct m68k_opcode **) v2;
4483
4484 /* Compare the two names. If different, return the comparison.
4485 If the same, return the order they are in the opcode table. */
4486 ret = strcmp (op1->name, op2->name);
4487 if (ret)
4488 return ret;
4489 if (op1 < op2)
4490 return -1;
4491 return 1;
4492 }
4493
4494 void
4495 md_begin (void)
4496 {
4497 const struct m68k_opcode *ins;
4498 struct m68k_incant *hack, *slak;
4499 int i;
4500
4501 /* Set up hash tables with 68000 instructions.
4502 similar to what the vax assembler does. */
4503 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4504 a copy of it at runtime, adding in the information we want but isn't
4505 there. I think it'd be better to have an awk script hack the table
4506 at compile time. Or even just xstr the table and use it as-is. But
4507 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4508 names. */
4509
4510 if (flag_mri)
4511 {
4512 flag_reg_prefix_optional = 1;
4513 m68k_abspcadd = 1;
4514 if (! m68k_rel32_from_cmdline)
4515 m68k_rel32 = 0;
4516 }
4517
4518 /* First sort the opcode table into alphabetical order to separate
4519 the order that the assembler wants to see the opcodes from the
4520 order that the disassembler wants to see them. */
4521 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes);
4522
4523 for (i = m68k_numopcodes; i--;)
4524 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4525
4526 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4527 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4528
4529 op_hash = str_htab_create ();
4530
4531 obstack_begin (&robyn, 4000);
4532 for (i = 0; i < m68k_numopcodes; i++)
4533 {
4534 hack = slak = XOBNEW (&robyn, struct m68k_incant);
4535 do
4536 {
4537 ins = m68k_sorted_opcodes[i];
4538
4539 /* We must enter all insns into the table, because .arch and
4540 .cpu directives can change things. */
4541 slak->m_operands = ins->args;
4542 slak->m_arch = ins->arch;
4543 slak->m_opcode = ins->opcode;
4544
4545 /* In most cases we can determine the number of opcode words
4546 by checking the second word of the mask. Unfortunately
4547 some instructions have 2 opcode words, but no fixed bits
4548 in the second word. A leading dot in the operands
4549 string also indicates 2 opcodes. */
4550 if (*slak->m_operands == '.')
4551 {
4552 slak->m_operands++;
4553 slak->m_codenum = 2;
4554 }
4555 else if (ins->match & 0xffffL)
4556 slak->m_codenum = 2;
4557 else
4558 slak->m_codenum = 1;
4559 slak->m_opnum = strlen (slak->m_operands) / 2;
4560
4561 if (i + 1 != m68k_numopcodes
4562 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4563 {
4564 slak->m_next = XOBNEW (&robyn, struct m68k_incant);
4565 i++;
4566 }
4567 else
4568 slak->m_next = 0;
4569 slak = slak->m_next;
4570 }
4571 while (slak);
4572
4573 str_hash_insert (op_hash, ins->name, (char *) hack);
4574 }
4575
4576 for (i = 0; i < m68k_numaliases; i++)
4577 {
4578 const char *name = m68k_opcode_aliases[i].primary;
4579 const char *alias = m68k_opcode_aliases[i].alias;
4580 void *val = (void *)str_hash_find (op_hash, name);
4581
4582 if (!val)
4583 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4584 str_hash_insert (op_hash, alias, val);
4585 }
4586
4587 /* In MRI mode, all unsized branches are variable sized. Normally,
4588 they are word sized. */
4589 if (flag_mri)
4590 {
4591 static struct m68k_opcode_alias mri_aliases[] =
4592 {
4593 { "bhi", "jhi", },
4594 { "bls", "jls", },
4595 { "bcc", "jcc", },
4596 { "bcs", "jcs", },
4597 { "bne", "jne", },
4598 { "beq", "jeq", },
4599 { "bvc", "jvc", },
4600 { "bvs", "jvs", },
4601 { "bpl", "jpl", },
4602 { "bmi", "jmi", },
4603 { "bge", "jge", },
4604 { "blt", "jlt", },
4605 { "bgt", "jgt", },
4606 { "ble", "jle", },
4607 { "bra", "jra", },
4608 { "bsr", "jbsr", },
4609 };
4610
4611 for (i = 0;
4612 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4613 i++)
4614 {
4615 const char *name = mri_aliases[i].primary;
4616 const char *alias = mri_aliases[i].alias;
4617 void *val = (void *)str_hash_find (op_hash, name);
4618
4619 if (!val)
4620 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4621 str_hash_insert (op_hash, alias, val);
4622 }
4623 }
4624
4625 for (i = 0; i < (int) sizeof (notend_table); i++)
4626 {
4627 notend_table[i] = 0;
4628 alt_notend_table[i] = 0;
4629 }
4630
4631 notend_table[','] = 1;
4632 notend_table['{'] = 1;
4633 notend_table['}'] = 1;
4634 alt_notend_table['a'] = 1;
4635 alt_notend_table['A'] = 1;
4636 alt_notend_table['d'] = 1;
4637 alt_notend_table['D'] = 1;
4638 alt_notend_table['#'] = 1;
4639 alt_notend_table['&'] = 1;
4640 alt_notend_table['f'] = 1;
4641 alt_notend_table['F'] = 1;
4642 #ifdef REGISTER_PREFIX
4643 alt_notend_table[REGISTER_PREFIX] = 1;
4644 #endif
4645
4646 /* We need to put '(' in alt_notend_table to handle
4647 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4648 alt_notend_table['('] = 1;
4649
4650 /* We need to put '@' in alt_notend_table to handle
4651 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4652 alt_notend_table['@'] = 1;
4653
4654 /* We need to put digits in alt_notend_table to handle
4655 bfextu %d0{24:1},%d0 */
4656 alt_notend_table['0'] = 1;
4657 alt_notend_table['1'] = 1;
4658 alt_notend_table['2'] = 1;
4659 alt_notend_table['3'] = 1;
4660 alt_notend_table['4'] = 1;
4661 alt_notend_table['5'] = 1;
4662 alt_notend_table['6'] = 1;
4663 alt_notend_table['7'] = 1;
4664 alt_notend_table['8'] = 1;
4665 alt_notend_table['9'] = 1;
4666
4667 #ifndef MIT_SYNTAX_ONLY
4668 /* Insert pseudo ops, these have to go into the opcode table since
4669 gas expects pseudo ops to start with a dot. */
4670 {
4671 int n = 0;
4672
4673 while (mote_pseudo_table[n].poc_name)
4674 {
4675 hack = XOBNEW (&robyn, struct m68k_incant);
4676 str_hash_insert (op_hash,
4677 mote_pseudo_table[n].poc_name, (char *) hack);
4678 hack->m_operands = 0;
4679 hack->m_opnum = n;
4680 n++;
4681 }
4682 }
4683 #endif
4684
4685 init_regtable ();
4686
4687 record_alignment (text_section, 2);
4688 record_alignment (data_section, 2);
4689 record_alignment (bss_section, 2);
4690 }
4691
4692 \f
4693 /* This is called when a label is defined. */
4694
4695 void
4696 m68k_frob_label (symbolS *sym)
4697 {
4698 struct label_line *n;
4699
4700 n = XNEW (struct label_line);
4701 n->next = labels;
4702 n->label = sym;
4703 n->file = as_where (&n->line);
4704 n->text = 0;
4705 labels = n;
4706 current_label = n;
4707
4708 dwarf2_emit_label (sym);
4709 }
4710
4711 /* This is called when a value that is not an instruction is emitted. */
4712
4713 void
4714 m68k_flush_pending_output (void)
4715 {
4716 current_label = NULL;
4717 }
4718
4719 /* This is called at the end of the assembly, when the final value of
4720 the label is known. We warn if this is a text symbol aligned at an
4721 odd location. */
4722
4723 void
4724 m68k_frob_symbol (symbolS *sym)
4725 {
4726 if (S_GET_SEGMENT (sym) == reg_section
4727 && (int) S_GET_VALUE (sym) < 0)
4728 {
4729 S_SET_SEGMENT (sym, absolute_section);
4730 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4731 }
4732 else if ((S_GET_VALUE (sym) & 1) != 0)
4733 {
4734 struct label_line *l;
4735
4736 for (l = labels; l != NULL; l = l->next)
4737 {
4738 if (l->label == sym)
4739 {
4740 if (l->text)
4741 as_warn_where (l->file, l->line,
4742 _("text label `%s' aligned to odd boundary"),
4743 S_GET_NAME (sym));
4744 break;
4745 }
4746 }
4747 }
4748 }
4749 \f
4750 /* This is called if we go in or out of MRI mode because of the .mri
4751 pseudo-op. */
4752
4753 void
4754 m68k_mri_mode_change (int on)
4755 {
4756 if (on)
4757 {
4758 if (! flag_reg_prefix_optional)
4759 {
4760 flag_reg_prefix_optional = 1;
4761 #ifdef REGISTER_PREFIX
4762 init_regtable ();
4763 #endif
4764 }
4765 m68k_abspcadd = 1;
4766 if (! m68k_rel32_from_cmdline)
4767 m68k_rel32 = 0;
4768 }
4769 else
4770 {
4771 if (! reg_prefix_optional_seen)
4772 {
4773 #ifdef REGISTER_PREFIX_OPTIONAL
4774 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4775 #else
4776 flag_reg_prefix_optional = 0;
4777 #endif
4778 #ifdef REGISTER_PREFIX
4779 init_regtable ();
4780 #endif
4781 }
4782 m68k_abspcadd = 0;
4783 if (! m68k_rel32_from_cmdline)
4784 m68k_rel32 = 1;
4785 }
4786 }
4787
4788 const char *
4789 md_atof (int type, char *litP, int *sizeP)
4790 {
4791 return ieee_md_atof (type, litP, sizeP, TRUE);
4792 }
4793
4794 void
4795 md_number_to_chars (char *buf, valueT val, int n)
4796 {
4797 number_to_chars_bigendian (buf, val, n);
4798 }
4799
4800 void
4801 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4802 {
4803 offsetT val = *valP;
4804 addressT upper_limit;
4805 offsetT lower_limit;
4806
4807 /* This is unnecessary but it convinces the native rs6000 compiler
4808 to generate the code we want. */
4809 char *buf = fixP->fx_frag->fr_literal;
4810 buf += fixP->fx_where;
4811 /* End ibm compiler workaround. */
4812
4813 val = SEXT (val);
4814
4815 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4816 fixP->fx_done = 1;
4817
4818 if (fixP->fx_addsy)
4819 {
4820 memset (buf, 0, fixP->fx_size);
4821 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4822
4823 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4824 && !S_IS_DEFINED (fixP->fx_addsy)
4825 && !S_IS_WEAK (fixP->fx_addsy))
4826 S_SET_WEAK (fixP->fx_addsy);
4827
4828 switch (fixP->fx_r_type)
4829 {
4830 case BFD_RELOC_68K_TLS_GD32:
4831 case BFD_RELOC_68K_TLS_GD16:
4832 case BFD_RELOC_68K_TLS_GD8:
4833 case BFD_RELOC_68K_TLS_LDM32:
4834 case BFD_RELOC_68K_TLS_LDM16:
4835 case BFD_RELOC_68K_TLS_LDM8:
4836 case BFD_RELOC_68K_TLS_LDO32:
4837 case BFD_RELOC_68K_TLS_LDO16:
4838 case BFD_RELOC_68K_TLS_LDO8:
4839 case BFD_RELOC_68K_TLS_IE32:
4840 case BFD_RELOC_68K_TLS_IE16:
4841 case BFD_RELOC_68K_TLS_IE8:
4842 case BFD_RELOC_68K_TLS_LE32:
4843 case BFD_RELOC_68K_TLS_LE16:
4844 case BFD_RELOC_68K_TLS_LE8:
4845 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4846 break;
4847
4848 default:
4849 break;
4850 }
4851
4852 return;
4853 }
4854
4855 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4856 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4857 return;
4858
4859 switch (fixP->fx_size)
4860 {
4861 /* The cast to offsetT below are necessary to make code
4862 correct for machines where ints are smaller than offsetT. */
4863 case 1:
4864 *buf++ = val;
4865 upper_limit = 0x7f;
4866 lower_limit = - (offsetT) 0x80;
4867 break;
4868 case 2:
4869 *buf++ = (val >> 8);
4870 *buf++ = val;
4871 upper_limit = 0x7fff;
4872 lower_limit = - (offsetT) 0x8000;
4873 break;
4874 case 4:
4875 *buf++ = (val >> 24);
4876 *buf++ = (val >> 16);
4877 *buf++ = (val >> 8);
4878 *buf++ = val;
4879 upper_limit = 0x7fffffff;
4880 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4881 break;
4882 default:
4883 BAD_CASE (fixP->fx_size);
4884 }
4885
4886 /* Fix up a negative reloc. */
4887 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4888 {
4889 fixP->fx_addsy = fixP->fx_subsy;
4890 fixP->fx_subsy = NULL;
4891 fixP->fx_tcbit = 1;
4892 }
4893
4894 /* For non-pc-relative values, it's conceivable we might get something
4895 like "0xff" for a byte field. So extend the upper part of the range
4896 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4897 so that we can do any range checking at all. */
4898 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4899 upper_limit = upper_limit * 2 + 1;
4900
4901 if ((addressT) val > upper_limit
4902 && (val > 0 || val < lower_limit))
4903 as_bad_where (fixP->fx_file, fixP->fx_line,
4904 _("value %ld out of range"), (long)val);
4905
4906 /* A one byte PC-relative reloc means a short branch. We can't use
4907 a short branch with a value of 0 or -1, because those indicate
4908 different opcodes (branches with longer offsets). fixup_segment
4909 in write.c may have clobbered fx_pcrel, so we need to examine the
4910 reloc type. */
4911 if ((fixP->fx_pcrel
4912 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4913 && fixP->fx_size == 1
4914 && (fixP->fx_addsy == NULL
4915 || S_IS_DEFINED (fixP->fx_addsy))
4916 && (val == 0 || val == -1))
4917 as_bad_where (fixP->fx_file, fixP->fx_line,
4918 _("invalid byte branch offset"));
4919 }
4920
4921 /* *fragP has been relaxed to its final size, and now needs to have
4922 the bytes inside it modified to conform to the new size There is UGLY
4923 MAGIC here. ..
4924 */
4925 static void
4926 md_convert_frag_1 (fragS *fragP)
4927 {
4928 long disp;
4929 fixS *fixP = NULL;
4930
4931 /* Address in object code of the displacement. */
4932 int object_address = fragP->fr_fix + fragP->fr_address;
4933
4934 /* Address in gas core of the place to store the displacement. */
4935 /* This convinces the native rs6000 compiler to generate the code we
4936 want. */
4937 char *buffer_address = fragP->fr_literal;
4938 buffer_address += fragP->fr_fix;
4939 /* End ibm compiler workaround. */
4940
4941 /* The displacement of the address, from current location. */
4942 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4943 disp = (disp + fragP->fr_offset) - object_address;
4944
4945 switch (fragP->fr_subtype)
4946 {
4947 case TAB (BRANCHBWL, BYTE):
4948 case TAB (BRABSJUNC, BYTE):
4949 case TAB (BRABSJCOND, BYTE):
4950 case TAB (BRANCHBW, BYTE):
4951 case TAB (BRANCHBWPL, BYTE):
4952 know (issbyte (disp));
4953 if (disp == 0)
4954 as_bad_where (fragP->fr_file, fragP->fr_line,
4955 _("short branch with zero offset: use :w"));
4956 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4957 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4958 fixP->fx_pcrel_adjust = -1;
4959 break;
4960 case TAB (BRANCHBWL, SHORT):
4961 case TAB (BRABSJUNC, SHORT):
4962 case TAB (BRABSJCOND, SHORT):
4963 case TAB (BRANCHBW, SHORT):
4964 case TAB (BRANCHBWPL, SHORT):
4965 fragP->fr_opcode[1] = 0x00;
4966 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4967 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4968 fragP->fr_fix += 2;
4969 break;
4970 case TAB (BRANCHBWL, LONG):
4971 fragP->fr_opcode[1] = (char) 0xFF;
4972 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4973 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4974 fragP->fr_fix += 4;
4975 break;
4976 case TAB (BRANCHBWPL, LONG):
4977 /* Here we are converting an unconditional branch into a pair of
4978 conditional branches, in order to get the range. */
4979 fragP->fr_opcode[0] = 0x66; /* bne */
4980 fragP->fr_opcode[1] = 0xFF;
4981 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4982 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4983 fixP->fx_file = fragP->fr_file;
4984 fixP->fx_line = fragP->fr_line;
4985 fragP->fr_fix += 4; /* Skip first offset */
4986 buffer_address += 4;
4987 *buffer_address++ = 0x67; /* beq */
4988 *buffer_address++ = 0xff;
4989 fragP->fr_fix += 2; /* Skip second branch opcode */
4990 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4991 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4992 fragP->fr_fix += 4;
4993 break;
4994 case TAB (BRABSJUNC, LONG):
4995 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4996 {
4997 if (flag_keep_pcrel)
4998 as_bad_where (fragP->fr_file, fragP->fr_line,
4999 _("Conversion of PC relative BSR to absolute JSR"));
5000 fragP->fr_opcode[0] = 0x4E;
5001 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
5002 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5003 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5004 fragP->fr_fix += 4;
5005 }
5006 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5007 {
5008 if (flag_keep_pcrel)
5009 as_bad_where (fragP->fr_file, fragP->fr_line,
5010 _("Conversion of PC relative branch to absolute jump"));
5011 fragP->fr_opcode[0] = 0x4E;
5012 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5013 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5014 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5015 fragP->fr_fix += 4;
5016 }
5017 else
5018 {
5019 /* This cannot happen, because jbsr and jbra are the only two
5020 unconditional branches. */
5021 abort ();
5022 }
5023 break;
5024 case TAB (BRABSJCOND, LONG):
5025 if (flag_keep_pcrel)
5026 as_bad_where (fragP->fr_file, fragP->fr_line,
5027 _("Conversion of PC relative conditional branch to absolute jump"));
5028
5029 /* Only Bcc 68000 instructions can come here
5030 Change bcc into b!cc/jmp absl long. */
5031 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5032 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
5033
5034 /* JF: these used to be fr_opcode[2,3], but they may be in a
5035 different frag, in which case referring to them is a no-no.
5036 Only fr_opcode[0,1] are guaranteed to work. */
5037 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5038 *buffer_address++ = (char) 0xf9;
5039 fragP->fr_fix += 2; /* Account for jmp instruction. */
5040 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5041 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5042 fragP->fr_fix += 4;
5043 break;
5044 case TAB (FBRANCH, SHORT):
5045 know ((fragP->fr_opcode[1] & 0x40) == 0);
5046 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5047 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5048 fragP->fr_fix += 2;
5049 break;
5050 case TAB (FBRANCH, LONG):
5051 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
5052 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5053 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5054 fragP->fr_fix += 4;
5055 break;
5056 case TAB (DBCCLBR, SHORT):
5057 case TAB (DBCCABSJ, SHORT):
5058 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5059 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5060 fragP->fr_fix += 2;
5061 break;
5062 case TAB (DBCCLBR, LONG):
5063 /* Only DBcc instructions can come here.
5064 Change dbcc into dbcc/bral.
5065 JF: these used to be fr_opcode[2-7], but that's wrong. */
5066 *buffer_address++ = 0x00; /* Branch offset = 4. */
5067 *buffer_address++ = 0x04;
5068 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5069 *buffer_address++ = 0x06;
5070 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5071 *buffer_address++ = (char) 0xff;
5072
5073 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5074 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5075 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5076 fragP->fr_fix += 4;
5077 break;
5078 case TAB (DBCCABSJ, LONG):
5079 /* Only DBcc instructions can come here.
5080 Change dbcc into dbcc/jmp.
5081 JF: these used to be fr_opcode[2-7], but that's wrong. */
5082 if (flag_keep_pcrel)
5083 as_bad_where (fragP->fr_file, fragP->fr_line,
5084 _("Conversion of PC relative conditional branch to absolute jump"));
5085
5086 *buffer_address++ = 0x00; /* Branch offset = 4. */
5087 *buffer_address++ = 0x04;
5088 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5089 *buffer_address++ = 0x06;
5090 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5091 *buffer_address++ = (char) 0xf9;
5092
5093 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5094 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5095 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5096 fragP->fr_fix += 4;
5097 break;
5098 case TAB (PCREL1632, SHORT):
5099 fragP->fr_opcode[1] &= ~0x3F;
5100 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5101 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5102 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5103 fragP->fr_fix += 2;
5104 break;
5105 case TAB (PCREL1632, LONG):
5106 /* Already set to mode 7.3; this indicates: PC indirect with
5107 suppressed index, 32-bit displacement. */
5108 *buffer_address++ = 0x01;
5109 *buffer_address++ = 0x70;
5110 fragP->fr_fix += 2;
5111 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5112 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5113 fixP->fx_pcrel_adjust = 2;
5114 fragP->fr_fix += 4;
5115 break;
5116 case TAB (PCINDEX, BYTE):
5117 gas_assert (fragP->fr_fix >= 2);
5118 buffer_address[-2] &= ~1;
5119 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5120 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5121 fixP->fx_pcrel_adjust = 1;
5122 break;
5123 case TAB (PCINDEX, SHORT):
5124 gas_assert (fragP->fr_fix >= 2);
5125 buffer_address[-2] |= 0x1;
5126 buffer_address[-1] = 0x20;
5127 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5128 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5129 fixP->fx_pcrel_adjust = 2;
5130 fragP->fr_fix += 2;
5131 break;
5132 case TAB (PCINDEX, LONG):
5133 gas_assert (fragP->fr_fix >= 2);
5134 buffer_address[-2] |= 0x1;
5135 buffer_address[-1] = 0x30;
5136 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5137 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5138 fixP->fx_pcrel_adjust = 2;
5139 fragP->fr_fix += 4;
5140 break;
5141 case TAB (ABSTOPCREL, SHORT):
5142 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5143 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5144 fragP->fr_fix += 2;
5145 break;
5146 case TAB (ABSTOPCREL, LONG):
5147 if (flag_keep_pcrel)
5148 as_bad_where (fragP->fr_file, fragP->fr_line,
5149 _("Conversion of PC relative displacement to absolute"));
5150 /* The thing to do here is force it to ABSOLUTE LONG, since
5151 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5152 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5153 abort ();
5154 fragP->fr_opcode[1] &= ~0x3F;
5155 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5156 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5157 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5158 fragP->fr_fix += 4;
5159 break;
5160 }
5161 if (fixP)
5162 {
5163 fixP->fx_file = fragP->fr_file;
5164 fixP->fx_line = fragP->fr_line;
5165 }
5166 }
5167
5168 void
5169 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5170 segT sec ATTRIBUTE_UNUSED,
5171 fragS *fragP)
5172 {
5173 md_convert_frag_1 (fragP);
5174 }
5175
5176 /* Force truly undefined symbols to their maximum size, and generally set up
5177 the frag list to be relaxed
5178 */
5179 int
5180 md_estimate_size_before_relax (fragS *fragP, segT segment)
5181 {
5182 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5183 switch (fragP->fr_subtype)
5184 {
5185 case TAB (BRANCHBWL, SZ_UNDEF):
5186 case TAB (BRANCHBWPL, SZ_UNDEF):
5187 case TAB (BRABSJUNC, SZ_UNDEF):
5188 case TAB (BRABSJCOND, SZ_UNDEF):
5189 {
5190 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5191 && relaxable_symbol (fragP->fr_symbol))
5192 {
5193 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5194 }
5195 else if (flag_short_refs)
5196 {
5197 /* Symbol is undefined and we want short ref. */
5198 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5199 }
5200 else
5201 {
5202 /* Symbol is still undefined. Make it LONG. */
5203 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5204 }
5205 break;
5206 }
5207
5208 case TAB (BRANCHBW, SZ_UNDEF):
5209 {
5210 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5211 && relaxable_symbol (fragP->fr_symbol))
5212 {
5213 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5214 }
5215 else
5216 {
5217 /* Symbol is undefined and we don't have long branches. */
5218 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5219 }
5220 break;
5221 }
5222
5223 case TAB (FBRANCH, SZ_UNDEF):
5224 case TAB (DBCCLBR, SZ_UNDEF):
5225 case TAB (DBCCABSJ, SZ_UNDEF):
5226 case TAB (PCREL1632, SZ_UNDEF):
5227 {
5228 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5229 && relaxable_symbol (fragP->fr_symbol))
5230 || flag_short_refs)
5231 {
5232 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5233 }
5234 else
5235 {
5236 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5237 }
5238 break;
5239 }
5240
5241 case TAB (PCINDEX, SZ_UNDEF):
5242 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5243 && relaxable_symbol (fragP->fr_symbol)))
5244 {
5245 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5246 }
5247 else
5248 {
5249 fragP->fr_subtype = TAB (PCINDEX, LONG);
5250 }
5251 break;
5252
5253 case TAB (ABSTOPCREL, SZ_UNDEF):
5254 {
5255 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5256 && relaxable_symbol (fragP->fr_symbol)))
5257 {
5258 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5259 }
5260 else
5261 {
5262 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5263 }
5264 break;
5265 }
5266
5267 default:
5268 break;
5269 }
5270
5271 /* Now that SZ_UNDEF are taken care of, check others. */
5272 switch (fragP->fr_subtype)
5273 {
5274 case TAB (BRANCHBWL, BYTE):
5275 case TAB (BRABSJUNC, BYTE):
5276 case TAB (BRABSJCOND, BYTE):
5277 case TAB (BRANCHBW, BYTE):
5278 /* We can't do a short jump to the next instruction, so in that
5279 case we force word mode. If the symbol is at the start of a
5280 frag, and it is the next frag with any data in it (usually
5281 this is just the next frag, but assembler listings may
5282 introduce empty frags), we must use word mode. */
5283 if (fragP->fr_symbol)
5284 {
5285 fragS *sym_frag;
5286
5287 sym_frag = symbol_get_frag (fragP->fr_symbol);
5288 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5289 {
5290 fragS *l;
5291
5292 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5293 if (l->fr_fix != 0)
5294 break;
5295 if (l == sym_frag)
5296 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5297 }
5298 }
5299 break;
5300 default:
5301 break;
5302 }
5303 return md_relax_table[fragP->fr_subtype].rlx_length;
5304 }
5305
5306 #ifndef WORKING_DOT_WORD
5307 int md_short_jump_size = 4;
5308 int md_long_jump_size = 6;
5309
5310 void
5311 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5312 fragS *frag ATTRIBUTE_UNUSED,
5313 symbolS *to_symbol ATTRIBUTE_UNUSED)
5314 {
5315 valueT offset;
5316
5317 offset = to_addr - (from_addr + 2);
5318
5319 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5320 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5321 }
5322
5323 void
5324 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5325 fragS *frag, symbolS *to_symbol)
5326 {
5327 valueT offset;
5328
5329 if (!HAVE_LONG_BRANCH (current_architecture))
5330 {
5331 if (flag_keep_pcrel)
5332 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5333 offset = to_addr - S_GET_VALUE (to_symbol);
5334 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5335 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5336 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5337 0, NO_RELOC);
5338 }
5339 else
5340 {
5341 offset = to_addr - (from_addr + 2);
5342 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5343 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5344 }
5345 }
5346
5347 #endif
5348
5349 /* Different values of OK tell what it's OK to return. Things that
5350 aren't OK are an error (what a shock, no?)
5351
5352 0: Everything is OK
5353 10: Absolute 1:8 only
5354 20: Absolute 0:7 only
5355 30: absolute 0:15 only
5356 40: Absolute 0:31 only
5357 50: absolute 0:127 only
5358 55: absolute -64:63 only
5359 60: absolute -128:127 only
5360 65: absolute 0:511 only
5361 70: absolute 0:4095 only
5362 80: absolute -1, 1:7 only
5363 90: No bignums. */
5364
5365 static int
5366 get_num (struct m68k_exp *exp, int ok)
5367 {
5368 if (exp->exp.X_op == O_absent)
5369 {
5370 /* Do the same thing the VAX asm does. */
5371 op (exp) = O_constant;
5372 adds (exp) = 0;
5373 subs (exp) = 0;
5374 offs (exp) = 0;
5375 if (ok == 10)
5376 {
5377 as_warn (_("expression out of range: defaulting to 1"));
5378 offs (exp) = 1;
5379 }
5380 }
5381 else if (exp->exp.X_op == O_constant)
5382 {
5383 switch (ok)
5384 {
5385 case 10:
5386 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5387 {
5388 as_warn (_("expression out of range: defaulting to 1"));
5389 offs (exp) = 1;
5390 }
5391 break;
5392 case 20:
5393 if ((valueT) TRUNC (offs (exp)) > 7)
5394 goto outrange;
5395 break;
5396 case 30:
5397 if ((valueT) TRUNC (offs (exp)) > 15)
5398 goto outrange;
5399 break;
5400 case 40:
5401 if ((valueT) TRUNC (offs (exp)) > 32)
5402 goto outrange;
5403 break;
5404 case 50:
5405 if ((valueT) TRUNC (offs (exp)) > 127)
5406 goto outrange;
5407 break;
5408 case 55:
5409 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5410 goto outrange;
5411 break;
5412 case 60:
5413 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5414 goto outrange;
5415 break;
5416 case 65:
5417 if ((valueT) TRUNC (offs (exp)) > 511)
5418 goto outrange;
5419 break;
5420 case 70:
5421 if ((valueT) TRUNC (offs (exp)) > 4095)
5422 {
5423 outrange:
5424 as_warn (_("expression out of range: defaulting to 0"));
5425 offs (exp) = 0;
5426 }
5427 break;
5428 case 80:
5429 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5430 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5431 {
5432 as_warn (_("expression out of range: defaulting to 1"));
5433 offs (exp) = 1;
5434 }
5435 break;
5436 default:
5437 break;
5438 }
5439 }
5440 else if (exp->exp.X_op == O_big)
5441 {
5442 if (offs (exp) <= 0 /* flonum. */
5443 && (ok == 90 /* no bignums */
5444 || (ok > 10 /* Small-int ranges including 0 ok. */
5445 /* If we have a flonum zero, a zero integer should
5446 do as well (e.g., in moveq). */
5447 && generic_floating_point_number.exponent == 0
5448 && generic_floating_point_number.low[0] == 0)))
5449 {
5450 /* HACK! Turn it into a long. */
5451 LITTLENUM_TYPE words[6];
5452
5453 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5454 op (exp) = O_constant;
5455 adds (exp) = 0;
5456 subs (exp) = 0;
5457 offs (exp) = words[1] | (words[0] << 16);
5458 }
5459 else if (ok != 0)
5460 {
5461 op (exp) = O_constant;
5462 adds (exp) = 0;
5463 subs (exp) = 0;
5464 offs (exp) = (ok == 10) ? 1 : 0;
5465 as_warn (_("Can't deal with expression; defaulting to %ld"),
5466 (long) offs (exp));
5467 }
5468 }
5469 else
5470 {
5471 if (ok >= 10 && ok <= 80)
5472 {
5473 op (exp) = O_constant;
5474 adds (exp) = 0;
5475 subs (exp) = 0;
5476 offs (exp) = (ok == 10) ? 1 : 0;
5477 as_warn (_("Can't deal with expression; defaulting to %ld"),
5478 (long) offs (exp));
5479 }
5480 }
5481
5482 if (exp->size != SIZE_UNSPEC)
5483 {
5484 switch (exp->size)
5485 {
5486 case SIZE_UNSPEC:
5487 case SIZE_LONG:
5488 break;
5489 case SIZE_BYTE:
5490 if (!isbyte (offs (exp)))
5491 as_warn (_("expression doesn't fit in BYTE"));
5492 break;
5493 case SIZE_WORD:
5494 if (!isword (offs (exp)))
5495 as_warn (_("expression doesn't fit in WORD"));
5496 break;
5497 }
5498 }
5499
5500 return offs (exp);
5501 }
5502
5503 /* These are the back-ends for the various machine dependent pseudo-ops. */
5504
5505 static void
5506 s_data1 (int ignore ATTRIBUTE_UNUSED)
5507 {
5508 subseg_set (data_section, 1);
5509 demand_empty_rest_of_line ();
5510 }
5511
5512 static void
5513 s_data2 (int ignore ATTRIBUTE_UNUSED)
5514 {
5515 subseg_set (data_section, 2);
5516 demand_empty_rest_of_line ();
5517 }
5518
5519 static void
5520 s_bss (int ignore ATTRIBUTE_UNUSED)
5521 {
5522 /* We don't support putting frags in the BSS segment, we fake it
5523 by marking in_bss, then looking at s_skip for clues. */
5524
5525 subseg_set (bss_section, 0);
5526 demand_empty_rest_of_line ();
5527 }
5528
5529 static void
5530 s_even (int ignore ATTRIBUTE_UNUSED)
5531 {
5532 int temp;
5533 long temp_fill;
5534
5535 temp = 1; /* JF should be 2? */
5536 temp_fill = get_absolute_expression ();
5537 if (!need_pass_2) /* Never make frag if expect extra pass. */
5538 frag_align (temp, (int) temp_fill, 0);
5539 demand_empty_rest_of_line ();
5540 record_alignment (now_seg, temp);
5541 }
5542
5543 static void
5544 s_proc (int ignore ATTRIBUTE_UNUSED)
5545 {
5546 demand_empty_rest_of_line ();
5547 }
5548 \f
5549 /* Pseudo-ops handled for MRI compatibility. */
5550
5551 /* This function returns non-zero if the argument is a conditional
5552 pseudo-op. This is called when checking whether a pending
5553 alignment is needed. */
5554
5555 int
5556 m68k_conditional_pseudoop (const pseudo_typeS *pop)
5557 {
5558 return (pop->poc_handler == s_mri_if
5559 || pop->poc_handler == s_mri_else);
5560 }
5561
5562 /* Handle an MRI style chip specification. */
5563
5564 static void
5565 mri_chip (void)
5566 {
5567 char *s;
5568 char c;
5569 int i;
5570
5571 s = input_line_pointer;
5572 /* We can't use get_symbol_name since the processor names are not proper
5573 symbols. */
5574 while (is_part_of_name (c = *input_line_pointer++))
5575 ;
5576 *--input_line_pointer = 0;
5577 for (i = 0; m68k_cpus[i].name; i++)
5578 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5579 break;
5580 if (!m68k_cpus[i].name)
5581 {
5582 as_bad (_("%s: unrecognized processor name"), s);
5583 *input_line_pointer = c;
5584 ignore_rest_of_line ();
5585 return;
5586 }
5587 *input_line_pointer = c;
5588
5589 if (*input_line_pointer == '/')
5590 current_architecture = 0;
5591 else
5592 current_architecture &= m68881 | m68851;
5593 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5594 control_regs = m68k_cpus[i].control_regs;
5595
5596 while (*input_line_pointer == '/')
5597 {
5598 ++input_line_pointer;
5599 s = input_line_pointer;
5600 /* We can't use get_symbol_name since the processor names are not
5601 proper symbols. */
5602 while (is_part_of_name (c = *input_line_pointer++))
5603 ;
5604 *--input_line_pointer = 0;
5605 if (strcmp (s, "68881") == 0)
5606 current_architecture |= m68881;
5607 else if (strcmp (s, "68851") == 0)
5608 current_architecture |= m68851;
5609 *input_line_pointer = c;
5610 }
5611 }
5612
5613 /* The MRI CHIP pseudo-op. */
5614
5615 static void
5616 s_chip (int ignore ATTRIBUTE_UNUSED)
5617 {
5618 char *stop = NULL;
5619 char stopc;
5620
5621 if (flag_mri)
5622 stop = mri_comment_field (&stopc);
5623 mri_chip ();
5624 if (flag_mri)
5625 mri_comment_end (stop, stopc);
5626 demand_empty_rest_of_line ();
5627 }
5628
5629 /* The MRI FOPT pseudo-op. */
5630
5631 static void
5632 s_fopt (int ignore ATTRIBUTE_UNUSED)
5633 {
5634 SKIP_WHITESPACE ();
5635
5636 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5637 {
5638 int temp;
5639
5640 input_line_pointer += 3;
5641 temp = get_absolute_expression ();
5642 if (temp < 0 || temp > 7)
5643 as_bad (_("bad coprocessor id"));
5644 else
5645 m68k_float_copnum = COP0 + temp;
5646 }
5647 else
5648 {
5649 as_bad (_("unrecognized fopt option"));
5650 ignore_rest_of_line ();
5651 return;
5652 }
5653
5654 demand_empty_rest_of_line ();
5655 }
5656
5657 /* The structure used to handle the MRI OPT pseudo-op. */
5658
5659 struct opt_action
5660 {
5661 /* The name of the option. */
5662 const char *name;
5663
5664 /* If this is not NULL, just call this function. The first argument
5665 is the ARG field of this structure, the second argument is
5666 whether the option was negated. */
5667 void (*pfn) (int arg, int on);
5668
5669 /* If this is not NULL, and the PFN field is NULL, set the variable
5670 this points to. Set it to the ARG field if the option was not
5671 negated, and the NOTARG field otherwise. */
5672 int *pvar;
5673
5674 /* The value to pass to PFN or to assign to *PVAR. */
5675 int arg;
5676
5677 /* The value to assign to *PVAR if the option is negated. If PFN is
5678 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5679 the option may not be negated. */
5680 int notarg;
5681 };
5682
5683 /* The table used to handle the MRI OPT pseudo-op. */
5684
5685 static void skip_to_comma (int, int);
5686 static void opt_nest (int, int);
5687 static void opt_chip (int, int);
5688 static void opt_list (int, int);
5689 static void opt_list_symbols (int, int);
5690
5691 static const struct opt_action opt_table[] =
5692 {
5693 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5694
5695 /* We do relaxing, so there is little use for these options. */
5696 { "b", 0, 0, 0, 0 },
5697 { "brs", 0, 0, 0, 0 },
5698 { "brb", 0, 0, 0, 0 },
5699 { "brl", 0, 0, 0, 0 },
5700 { "brw", 0, 0, 0, 0 },
5701
5702 { "c", 0, 0, 0, 0 },
5703 { "cex", 0, 0, 0, 0 },
5704 { "case", 0, &symbols_case_sensitive, 1, 0 },
5705 { "cl", 0, 0, 0, 0 },
5706 { "cre", 0, 0, 0, 0 },
5707 { "d", 0, &flag_keep_locals, 1, 0 },
5708 { "e", 0, 0, 0, 0 },
5709 { "f", 0, &flag_short_refs, 1, 0 },
5710 { "frs", 0, &flag_short_refs, 1, 0 },
5711 { "frl", 0, &flag_short_refs, 0, 1 },
5712 { "g", 0, 0, 0, 0 },
5713 { "i", 0, 0, 0, 0 },
5714 { "m", 0, 0, 0, 0 },
5715 { "mex", 0, 0, 0, 0 },
5716 { "mc", 0, 0, 0, 0 },
5717 { "md", 0, 0, 0, 0 },
5718 { "nest", opt_nest, 0, 0, 0 },
5719 { "next", skip_to_comma, 0, 0, 0 },
5720 { "o", 0, 0, 0, 0 },
5721 { "old", 0, 0, 0, 0 },
5722 { "op", skip_to_comma, 0, 0, 0 },
5723 { "pco", 0, 0, 0, 0 },
5724 { "p", opt_chip, 0, 0, 0 },
5725 { "pcr", 0, 0, 0, 0 },
5726 { "pcs", 0, 0, 0, 0 },
5727 { "r", 0, 0, 0, 0 },
5728 { "quick", 0, &m68k_quick, 1, 0 },
5729 { "rel32", 0, &m68k_rel32, 1, 0 },
5730 { "s", opt_list, 0, 0, 0 },
5731 { "t", opt_list_symbols, 0, 0, 0 },
5732 { "w", 0, &flag_no_warnings, 0, 1 },
5733 { "x", 0, 0, 0, 0 }
5734 };
5735
5736 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5737
5738 /* The MRI OPT pseudo-op. */
5739
5740 static void
5741 s_opt (int ignore ATTRIBUTE_UNUSED)
5742 {
5743 do
5744 {
5745 int t;
5746 char *s;
5747 char c;
5748 int i;
5749 const struct opt_action *o;
5750
5751 SKIP_WHITESPACE ();
5752
5753 t = 1;
5754 if (*input_line_pointer == '-')
5755 {
5756 ++input_line_pointer;
5757 t = 0;
5758 }
5759 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5760 {
5761 input_line_pointer += 2;
5762 t = 0;
5763 }
5764
5765 c = get_symbol_name (&s);
5766
5767 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5768 {
5769 if (strcasecmp (s, o->name) == 0)
5770 {
5771 if (o->pfn)
5772 {
5773 /* Restore input_line_pointer now in case the option
5774 takes arguments. */
5775 (void) restore_line_pointer (c);
5776 (*o->pfn) (o->arg, t);
5777 }
5778 else if (o->pvar != NULL)
5779 {
5780 if (! t && o->arg == o->notarg)
5781 as_bad (_("option `%s' may not be negated"), s);
5782 restore_line_pointer (c);
5783 *o->pvar = t ? o->arg : o->notarg;
5784 }
5785 else
5786 *input_line_pointer = c;
5787 break;
5788 }
5789 }
5790 if (i >= OPTCOUNT)
5791 {
5792 as_bad (_("option `%s' not recognized"), s);
5793 restore_line_pointer (c);
5794 }
5795 }
5796 while (*input_line_pointer++ == ',');
5797
5798 /* Move back to terminating character. */
5799 --input_line_pointer;
5800 demand_empty_rest_of_line ();
5801 }
5802
5803 /* Skip ahead to a comma. This is used for OPT options which we do
5804 not support and which take arguments. */
5805
5806 static void
5807 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5808 {
5809 while (*input_line_pointer != ','
5810 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5811 ++input_line_pointer;
5812 }
5813
5814 /* Handle the OPT NEST=depth option. */
5815
5816 static void
5817 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5818 {
5819 if (*input_line_pointer != '=')
5820 {
5821 as_bad (_("bad format of OPT NEST=depth"));
5822 return;
5823 }
5824
5825 ++input_line_pointer;
5826 max_macro_nest = get_absolute_expression ();
5827 }
5828
5829 /* Handle the OPT P=chip option. */
5830
5831 static void
5832 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5833 {
5834 if (*input_line_pointer != '=')
5835 {
5836 /* This is just OPT P, which we do not support. */
5837 return;
5838 }
5839
5840 ++input_line_pointer;
5841 mri_chip ();
5842 }
5843
5844 /* Handle the OPT S option. */
5845
5846 static void
5847 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5848 {
5849 listing_list (on);
5850 }
5851
5852 /* Handle the OPT T option. */
5853
5854 static void
5855 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5856 {
5857 if (on)
5858 listing |= LISTING_SYMBOLS;
5859 else
5860 listing &= ~LISTING_SYMBOLS;
5861 }
5862
5863 /* Handle the MRI REG pseudo-op. */
5864
5865 static void
5866 s_reg (int ignore ATTRIBUTE_UNUSED)
5867 {
5868 char *s;
5869 int c;
5870 struct m68k_op rop;
5871 int mask;
5872 char *stop = NULL;
5873 char stopc;
5874
5875 if (line_label == NULL)
5876 {
5877 as_bad (_("missing label"));
5878 ignore_rest_of_line ();
5879 return;
5880 }
5881
5882 if (flag_mri)
5883 stop = mri_comment_field (&stopc);
5884
5885 SKIP_WHITESPACE ();
5886
5887 s = input_line_pointer;
5888 while (ISALNUM (*input_line_pointer)
5889 #ifdef REGISTER_PREFIX
5890 || *input_line_pointer == REGISTER_PREFIX
5891 #endif
5892 || *input_line_pointer == '/'
5893 || *input_line_pointer == '-')
5894 ++input_line_pointer;
5895 c = *input_line_pointer;
5896 *input_line_pointer = '\0';
5897
5898 if (m68k_ip_op (s, &rop) != 0)
5899 {
5900 if (rop.error == NULL)
5901 as_bad (_("bad register list"));
5902 else
5903 as_bad (_("bad register list: %s"), rop.error);
5904 *input_line_pointer = c;
5905 ignore_rest_of_line ();
5906 return;
5907 }
5908
5909 *input_line_pointer = c;
5910
5911 if (rop.mode == REGLST)
5912 mask = rop.mask;
5913 else if (rop.mode == DREG)
5914 mask = 1 << (rop.reg - DATA0);
5915 else if (rop.mode == AREG)
5916 mask = 1 << (rop.reg - ADDR0 + 8);
5917 else if (rop.mode == FPREG)
5918 mask = 1 << (rop.reg - FP0 + 16);
5919 else if (rop.mode == CONTROL
5920 && rop.reg == FPI)
5921 mask = 1 << 24;
5922 else if (rop.mode == CONTROL
5923 && rop.reg == FPS)
5924 mask = 1 << 25;
5925 else if (rop.mode == CONTROL
5926 && rop.reg == FPC)
5927 mask = 1 << 26;
5928 else
5929 {
5930 as_bad (_("bad register list"));
5931 ignore_rest_of_line ();
5932 return;
5933 }
5934
5935 S_SET_SEGMENT (line_label, reg_section);
5936 S_SET_VALUE (line_label, ~mask);
5937 symbol_set_frag (line_label, &zero_address_frag);
5938
5939 if (flag_mri)
5940 mri_comment_end (stop, stopc);
5941
5942 demand_empty_rest_of_line ();
5943 }
5944
5945 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5946
5947 struct save_opts
5948 {
5949 struct save_opts *next;
5950 int abspcadd;
5951 int symbols_case_sensitive;
5952 int keep_locals;
5953 int short_refs;
5954 int architecture;
5955 const enum m68k_register *control_regs;
5956 int quick;
5957 int rel32;
5958 int listing;
5959 int no_warnings;
5960 /* FIXME: We don't save OPT S. */
5961 };
5962
5963 /* This variable holds the stack of saved options. */
5964
5965 static struct save_opts *save_stack;
5966
5967 /* The MRI SAVE pseudo-op. */
5968
5969 static void
5970 s_save (int ignore ATTRIBUTE_UNUSED)
5971 {
5972 struct save_opts *s;
5973
5974 s = XNEW (struct save_opts);
5975 s->abspcadd = m68k_abspcadd;
5976 s->symbols_case_sensitive = symbols_case_sensitive;
5977 s->keep_locals = flag_keep_locals;
5978 s->short_refs = flag_short_refs;
5979 s->architecture = current_architecture;
5980 s->control_regs = control_regs;
5981 s->quick = m68k_quick;
5982 s->rel32 = m68k_rel32;
5983 s->listing = listing;
5984 s->no_warnings = flag_no_warnings;
5985
5986 s->next = save_stack;
5987 save_stack = s;
5988
5989 demand_empty_rest_of_line ();
5990 }
5991
5992 /* The MRI RESTORE pseudo-op. */
5993
5994 static void
5995 s_restore (int ignore ATTRIBUTE_UNUSED)
5996 {
5997 struct save_opts *s;
5998
5999 if (save_stack == NULL)
6000 {
6001 as_bad (_("restore without save"));
6002 ignore_rest_of_line ();
6003 return;
6004 }
6005
6006 s = save_stack;
6007 save_stack = s->next;
6008
6009 m68k_abspcadd = s->abspcadd;
6010 symbols_case_sensitive = s->symbols_case_sensitive;
6011 flag_keep_locals = s->keep_locals;
6012 flag_short_refs = s->short_refs;
6013 current_architecture = s->architecture;
6014 control_regs = s->control_regs;
6015 m68k_quick = s->quick;
6016 m68k_rel32 = s->rel32;
6017 listing = s->listing;
6018 flag_no_warnings = s->no_warnings;
6019
6020 free (s);
6021
6022 demand_empty_rest_of_line ();
6023 }
6024
6025 /* Types of MRI structured control directives. */
6026
6027 enum mri_control_type
6028 {
6029 mri_for,
6030 mri_if,
6031 mri_repeat,
6032 mri_while
6033 };
6034
6035 /* This structure is used to stack the MRI structured control
6036 directives. */
6037
6038 struct mri_control_info
6039 {
6040 /* The directive within which this one is enclosed. */
6041 struct mri_control_info *outer;
6042
6043 /* The type of directive. */
6044 enum mri_control_type type;
6045
6046 /* Whether an ELSE has been in an IF. */
6047 int else_seen;
6048
6049 /* The add or sub statement at the end of a FOR. */
6050 char *incr;
6051
6052 /* The label of the top of a FOR or REPEAT loop. */
6053 char *top;
6054
6055 /* The label to jump to for the next iteration, or the else
6056 expression of a conditional. */
6057 char *next;
6058
6059 /* The label to jump to to break out of the loop, or the label past
6060 the end of a conditional. */
6061 char *bottom;
6062 };
6063
6064 /* The stack of MRI structured control directives. */
6065
6066 static struct mri_control_info *mri_control_stack;
6067
6068 /* The current MRI structured control directive index number, used to
6069 generate label names. */
6070
6071 static int mri_control_index;
6072
6073 /* Assemble an instruction for an MRI structured control directive. */
6074
6075 static void
6076 mri_assemble (char *str)
6077 {
6078 char *s;
6079
6080 /* md_assemble expects the opcode to be in lower case. */
6081 for (s = str; *s != ' ' && *s != '\0'; s++)
6082 *s = TOLOWER (*s);
6083
6084 md_assemble (str);
6085 }
6086
6087 /* Generate a new MRI label structured control directive label name. */
6088
6089 static char *
6090 mri_control_label (void)
6091 {
6092 char *n;
6093
6094 n = XNEWVEC (char, 20);
6095 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6096 ++mri_control_index;
6097 return n;
6098 }
6099
6100 /* Create a new MRI structured control directive. */
6101
6102 static struct mri_control_info *
6103 push_mri_control (enum mri_control_type type)
6104 {
6105 struct mri_control_info *n;
6106
6107 n = XNEW (struct mri_control_info);
6108
6109 n->type = type;
6110 n->else_seen = 0;
6111 if (type == mri_if || type == mri_while)
6112 n->top = NULL;
6113 else
6114 n->top = mri_control_label ();
6115 n->next = mri_control_label ();
6116 n->bottom = mri_control_label ();
6117
6118 n->outer = mri_control_stack;
6119 mri_control_stack = n;
6120
6121 return n;
6122 }
6123
6124 /* Pop off the stack of MRI structured control directives. */
6125
6126 static void
6127 pop_mri_control (void)
6128 {
6129 struct mri_control_info *n;
6130
6131 n = mri_control_stack;
6132 mri_control_stack = n->outer;
6133 free (n->top);
6134 free (n->next);
6135 free (n->bottom);
6136 free (n);
6137 }
6138
6139 /* Recognize a condition code in an MRI structured control expression. */
6140
6141 static int
6142 parse_mri_condition (int *pcc)
6143 {
6144 char c1, c2;
6145
6146 know (*input_line_pointer == '<');
6147
6148 ++input_line_pointer;
6149 c1 = *input_line_pointer++;
6150 c2 = *input_line_pointer++;
6151
6152 if (*input_line_pointer != '>')
6153 {
6154 as_bad (_("syntax error in structured control directive"));
6155 return 0;
6156 }
6157
6158 ++input_line_pointer;
6159 SKIP_WHITESPACE ();
6160
6161 c1 = TOLOWER (c1);
6162 c2 = TOLOWER (c2);
6163
6164 *pcc = (c1 << 8) | c2;
6165
6166 return 1;
6167 }
6168
6169 /* Parse a single operand in an MRI structured control expression. */
6170
6171 static int
6172 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6173 char **rightstart, char **rightstop)
6174 {
6175 char *s;
6176
6177 SKIP_WHITESPACE ();
6178
6179 *pcc = -1;
6180 *leftstart = NULL;
6181 *leftstop = NULL;
6182 *rightstart = NULL;
6183 *rightstop = NULL;
6184
6185 if (*input_line_pointer == '<')
6186 {
6187 /* It's just a condition code. */
6188 return parse_mri_condition (pcc);
6189 }
6190
6191 /* Look ahead for the condition code. */
6192 for (s = input_line_pointer; *s != '\0'; ++s)
6193 {
6194 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6195 break;
6196 }
6197 if (*s == '\0')
6198 {
6199 as_bad (_("missing condition code in structured control directive"));
6200 return 0;
6201 }
6202
6203 *leftstart = input_line_pointer;
6204 *leftstop = s;
6205 if (*leftstop > *leftstart
6206 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6207 --*leftstop;
6208
6209 input_line_pointer = s;
6210 if (! parse_mri_condition (pcc))
6211 return 0;
6212
6213 /* Look ahead for AND or OR or end of line. */
6214 for (s = input_line_pointer; *s != '\0'; ++s)
6215 {
6216 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6217 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6218 ^^^ ^^ */
6219 if ((s == input_line_pointer
6220 || *(s-1) == ' '
6221 || *(s-1) == '\t')
6222 && ((strncasecmp (s, "AND", 3) == 0
6223 && (s[3] == '.' || ! is_part_of_name (s[3])))
6224 || (strncasecmp (s, "OR", 2) == 0
6225 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6226 break;
6227 }
6228
6229 *rightstart = input_line_pointer;
6230 *rightstop = s;
6231 if (*rightstop > *rightstart
6232 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6233 --*rightstop;
6234
6235 input_line_pointer = s;
6236
6237 return 1;
6238 }
6239
6240 #define MCC(b1, b2) (((b1) << 8) | (b2))
6241
6242 /* Swap the sense of a condition. This changes the condition so that
6243 it generates the same result when the operands are swapped. */
6244
6245 static int
6246 swap_mri_condition (int cc)
6247 {
6248 switch (cc)
6249 {
6250 case MCC ('h', 'i'): return MCC ('c', 's');
6251 case MCC ('l', 's'): return MCC ('c', 'c');
6252 /* <HS> is an alias for <CC>. */
6253 case MCC ('h', 's'):
6254 case MCC ('c', 'c'): return MCC ('l', 's');
6255 /* <LO> is an alias for <CS>. */
6256 case MCC ('l', 'o'):
6257 case MCC ('c', 's'): return MCC ('h', 'i');
6258 case MCC ('p', 'l'): return MCC ('m', 'i');
6259 case MCC ('m', 'i'): return MCC ('p', 'l');
6260 case MCC ('g', 'e'): return MCC ('l', 'e');
6261 case MCC ('l', 't'): return MCC ('g', 't');
6262 case MCC ('g', 't'): return MCC ('l', 't');
6263 case MCC ('l', 'e'): return MCC ('g', 'e');
6264 /* Issue a warning for conditions we can not swap. */
6265 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6266 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6267 case MCC ('v', 'c'):
6268 case MCC ('v', 's'):
6269 default :
6270 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6271 (char) (cc >> 8), (char) (cc));
6272 break;
6273 }
6274 return cc;
6275 }
6276
6277 /* Reverse the sense of a condition. */
6278
6279 static int
6280 reverse_mri_condition (int cc)
6281 {
6282 switch (cc)
6283 {
6284 case MCC ('h', 'i'): return MCC ('l', 's');
6285 case MCC ('l', 's'): return MCC ('h', 'i');
6286 /* <HS> is an alias for <CC> */
6287 case MCC ('h', 's'): return MCC ('l', 'o');
6288 case MCC ('c', 'c'): return MCC ('c', 's');
6289 /* <LO> is an alias for <CS> */
6290 case MCC ('l', 'o'): return MCC ('h', 's');
6291 case MCC ('c', 's'): return MCC ('c', 'c');
6292 case MCC ('n', 'e'): return MCC ('e', 'q');
6293 case MCC ('e', 'q'): return MCC ('n', 'e');
6294 case MCC ('v', 'c'): return MCC ('v', 's');
6295 case MCC ('v', 's'): return MCC ('v', 'c');
6296 case MCC ('p', 'l'): return MCC ('m', 'i');
6297 case MCC ('m', 'i'): return MCC ('p', 'l');
6298 case MCC ('g', 'e'): return MCC ('l', 't');
6299 case MCC ('l', 't'): return MCC ('g', 'e');
6300 case MCC ('g', 't'): return MCC ('l', 'e');
6301 case MCC ('l', 'e'): return MCC ('g', 't');
6302 }
6303 return cc;
6304 }
6305
6306 /* Build an MRI structured control expression. This generates test
6307 and branch instructions. It goes to TRUELAB if the condition is
6308 true, and to FALSELAB if the condition is false. Exactly one of
6309 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6310 is the size qualifier for the expression. EXTENT is the size to
6311 use for the branch. */
6312
6313 static void
6314 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6315 char *rightstart, char *rightstop,
6316 const char *truelab, const char *falselab,
6317 int extent)
6318 {
6319 char *buf;
6320 char *s;
6321
6322 if (leftstart != NULL)
6323 {
6324 struct m68k_op leftop, rightop;
6325 char c;
6326
6327 /* Swap the compare operands, if necessary, to produce a legal
6328 m68k compare instruction. Comparing a register operand with
6329 a non-register operand requires the register to be on the
6330 right (cmp, cmpa). Comparing an immediate value with
6331 anything requires the immediate value to be on the left
6332 (cmpi). */
6333
6334 c = *leftstop;
6335 *leftstop = '\0';
6336 (void) m68k_ip_op (leftstart, &leftop);
6337 *leftstop = c;
6338
6339 c = *rightstop;
6340 *rightstop = '\0';
6341 (void) m68k_ip_op (rightstart, &rightop);
6342 *rightstop = c;
6343
6344 if (rightop.mode == IMMED
6345 || ((leftop.mode == DREG || leftop.mode == AREG)
6346 && (rightop.mode != DREG && rightop.mode != AREG)))
6347 {
6348 char *temp;
6349
6350 /* Correct conditional handling:
6351 if #1 <lt> d0 then ;means if (1 < d0)
6352 ...
6353 endi
6354
6355 should assemble to:
6356
6357 cmp #1,d0 if we do *not* swap the operands
6358 bgt true we need the swapped condition!
6359 ble false
6360 true:
6361 ...
6362 false:
6363 */
6364 temp = leftstart;
6365 leftstart = rightstart;
6366 rightstart = temp;
6367 temp = leftstop;
6368 leftstop = rightstop;
6369 rightstop = temp;
6370 }
6371 else
6372 {
6373 cc = swap_mri_condition (cc);
6374 }
6375 }
6376
6377 if (truelab == NULL)
6378 {
6379 cc = reverse_mri_condition (cc);
6380 truelab = falselab;
6381 }
6382
6383 if (leftstart != NULL)
6384 {
6385 buf = XNEWVEC (char, (20
6386 + (leftstop - leftstart)
6387 + (rightstop - rightstart)));
6388 s = buf;
6389 *s++ = 'c';
6390 *s++ = 'm';
6391 *s++ = 'p';
6392 if (qual != '\0')
6393 *s++ = TOLOWER (qual);
6394 *s++ = ' ';
6395 memcpy (s, leftstart, leftstop - leftstart);
6396 s += leftstop - leftstart;
6397 *s++ = ',';
6398 memcpy (s, rightstart, rightstop - rightstart);
6399 s += rightstop - rightstart;
6400 *s = '\0';
6401 mri_assemble (buf);
6402 free (buf);
6403 }
6404
6405 buf = XNEWVEC (char, 20 + strlen (truelab));
6406 s = buf;
6407 *s++ = 'b';
6408 *s++ = cc >> 8;
6409 *s++ = cc & 0xff;
6410 if (extent != '\0')
6411 *s++ = TOLOWER (extent);
6412 *s++ = ' ';
6413 strcpy (s, truelab);
6414 mri_assemble (buf);
6415 free (buf);
6416 }
6417
6418 /* Parse an MRI structured control expression. This generates test
6419 and branch instructions. STOP is where the expression ends. It
6420 goes to TRUELAB if the condition is true, and to FALSELAB if the
6421 condition is false. Exactly one of TRUELAB and FALSELAB will be
6422 NULL, meaning to fall through. QUAL is the size qualifier for the
6423 expression. EXTENT is the size to use for the branch. */
6424
6425 static void
6426 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6427 const char *falselab, int extent)
6428 {
6429 int c;
6430 int cc;
6431 char *leftstart;
6432 char *leftstop;
6433 char *rightstart;
6434 char *rightstop;
6435
6436 c = *stop;
6437 *stop = '\0';
6438
6439 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6440 &rightstart, &rightstop))
6441 {
6442 *stop = c;
6443 return;
6444 }
6445
6446 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6447 {
6448 const char *flab;
6449
6450 if (falselab != NULL)
6451 flab = falselab;
6452 else
6453 flab = mri_control_label ();
6454
6455 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6456 rightstop, (const char *) NULL, flab, extent);
6457
6458 input_line_pointer += 3;
6459 if (*input_line_pointer != '.'
6460 || input_line_pointer[1] == '\0')
6461 qual = '\0';
6462 else
6463 {
6464 qual = input_line_pointer[1];
6465 input_line_pointer += 2;
6466 }
6467
6468 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6469 &rightstart, &rightstop))
6470 {
6471 *stop = c;
6472 return;
6473 }
6474
6475 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6476 rightstop, truelab, falselab, extent);
6477
6478 if (falselab == NULL)
6479 colon (flab);
6480 }
6481 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6482 {
6483 const char *tlab;
6484
6485 if (truelab != NULL)
6486 tlab = truelab;
6487 else
6488 tlab = mri_control_label ();
6489
6490 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6491 rightstop, tlab, (const char *) NULL, extent);
6492
6493 input_line_pointer += 2;
6494 if (*input_line_pointer != '.'
6495 || input_line_pointer[1] == '\0')
6496 qual = '\0';
6497 else
6498 {
6499 qual = input_line_pointer[1];
6500 input_line_pointer += 2;
6501 }
6502
6503 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6504 &rightstart, &rightstop))
6505 {
6506 *stop = c;
6507 return;
6508 }
6509
6510 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6511 rightstop, truelab, falselab, extent);
6512
6513 if (truelab == NULL)
6514 colon (tlab);
6515 }
6516 else
6517 {
6518 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6519 rightstop, truelab, falselab, extent);
6520 }
6521
6522 *stop = c;
6523 if (input_line_pointer != stop)
6524 as_bad (_("syntax error in structured control directive"));
6525 }
6526
6527 /* Handle the MRI IF pseudo-op. This may be a structured control
6528 directive, or it may be a regular assembler conditional, depending
6529 on its operands. */
6530
6531 static void
6532 s_mri_if (int qual)
6533 {
6534 char *s;
6535 int c;
6536 struct mri_control_info *n;
6537
6538 /* A structured control directive must end with THEN with an
6539 optional qualifier. */
6540 s = input_line_pointer;
6541 /* We only accept '*' as introduction of comments if preceded by white space
6542 or at first column of a line (I think this can't actually happen here?)
6543 This is important when assembling:
6544 if d0 <ne> 12(a0,d0*2) then
6545 if d0 <ne> #CONST*20 then. */
6546 while (! (is_end_of_line[(unsigned char) *s]
6547 || (flag_mri
6548 && *s == '*'
6549 && (s == input_line_pointer
6550 || *(s-1) == ' '
6551 || *(s-1) == '\t'))))
6552 ++s;
6553 --s;
6554 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6555 --s;
6556
6557 if (s - input_line_pointer > 1
6558 && s[-1] == '.')
6559 s -= 2;
6560
6561 if (s - input_line_pointer < 3
6562 || strncasecmp (s - 3, "THEN", 4) != 0)
6563 {
6564 if (qual != '\0')
6565 {
6566 as_bad (_("missing then"));
6567 ignore_rest_of_line ();
6568 return;
6569 }
6570
6571 /* It's a conditional. */
6572 s_if (O_ne);
6573 return;
6574 }
6575
6576 /* Since this might be a conditional if, this pseudo-op will be
6577 called even if we are supported to be ignoring input. Double
6578 check now. Clobber *input_line_pointer so that ignore_input
6579 thinks that this is not a special pseudo-op. */
6580 c = *input_line_pointer;
6581 *input_line_pointer = 0;
6582 if (ignore_input ())
6583 {
6584 *input_line_pointer = c;
6585 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6586 ++input_line_pointer;
6587 demand_empty_rest_of_line ();
6588 return;
6589 }
6590 *input_line_pointer = c;
6591
6592 n = push_mri_control (mri_if);
6593
6594 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6595 n->next, s[1] == '.' ? s[2] : '\0');
6596
6597 if (s[1] == '.')
6598 input_line_pointer = s + 3;
6599 else
6600 input_line_pointer = s + 1;
6601
6602 if (flag_mri)
6603 {
6604 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6605 ++input_line_pointer;
6606 }
6607
6608 demand_empty_rest_of_line ();
6609 }
6610
6611 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6612 structured IF, associate the ELSE with the IF. Otherwise, assume
6613 it is a conditional else. */
6614
6615 static void
6616 s_mri_else (int qual)
6617 {
6618 int c;
6619 char *buf;
6620 char q[2];
6621
6622 if (qual == '\0'
6623 && (mri_control_stack == NULL
6624 || mri_control_stack->type != mri_if
6625 || mri_control_stack->else_seen))
6626 {
6627 s_else (0);
6628 return;
6629 }
6630
6631 c = *input_line_pointer;
6632 *input_line_pointer = 0;
6633 if (ignore_input ())
6634 {
6635 *input_line_pointer = c;
6636 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6637 ++input_line_pointer;
6638 demand_empty_rest_of_line ();
6639 return;
6640 }
6641 *input_line_pointer = c;
6642
6643 if (mri_control_stack == NULL
6644 || mri_control_stack->type != mri_if
6645 || mri_control_stack->else_seen)
6646 {
6647 as_bad (_("else without matching if"));
6648 ignore_rest_of_line ();
6649 return;
6650 }
6651
6652 mri_control_stack->else_seen = 1;
6653
6654 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom));
6655 q[0] = TOLOWER (qual);
6656 q[1] = '\0';
6657 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6658 mri_assemble (buf);
6659 free (buf);
6660
6661 colon (mri_control_stack->next);
6662
6663 if (flag_mri)
6664 {
6665 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6666 ++input_line_pointer;
6667 }
6668
6669 demand_empty_rest_of_line ();
6670 }
6671
6672 /* Handle the MRI ENDI pseudo-op. */
6673
6674 static void
6675 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6676 {
6677 if (mri_control_stack == NULL
6678 || mri_control_stack->type != mri_if)
6679 {
6680 as_bad (_("endi without matching if"));
6681 ignore_rest_of_line ();
6682 return;
6683 }
6684
6685 /* ignore_input will not return true for ENDI, so we don't need to
6686 worry about checking it again here. */
6687
6688 if (! mri_control_stack->else_seen)
6689 colon (mri_control_stack->next);
6690 colon (mri_control_stack->bottom);
6691
6692 pop_mri_control ();
6693
6694 if (flag_mri)
6695 {
6696 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6697 ++input_line_pointer;
6698 }
6699
6700 demand_empty_rest_of_line ();
6701 }
6702
6703 /* Handle the MRI BREAK pseudo-op. */
6704
6705 static void
6706 s_mri_break (int extent)
6707 {
6708 struct mri_control_info *n;
6709 char *buf;
6710 char ex[2];
6711
6712 n = mri_control_stack;
6713 while (n != NULL
6714 && n->type != mri_for
6715 && n->type != mri_repeat
6716 && n->type != mri_while)
6717 n = n->outer;
6718 if (n == NULL)
6719 {
6720 as_bad (_("break outside of structured loop"));
6721 ignore_rest_of_line ();
6722 return;
6723 }
6724
6725 buf = XNEWVEC (char, 20 + strlen (n->bottom));
6726 ex[0] = TOLOWER (extent);
6727 ex[1] = '\0';
6728 sprintf (buf, "bra%s %s", ex, n->bottom);
6729 mri_assemble (buf);
6730 free (buf);
6731
6732 if (flag_mri)
6733 {
6734 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6735 ++input_line_pointer;
6736 }
6737
6738 demand_empty_rest_of_line ();
6739 }
6740
6741 /* Handle the MRI NEXT pseudo-op. */
6742
6743 static void
6744 s_mri_next (int extent)
6745 {
6746 struct mri_control_info *n;
6747 char *buf;
6748 char ex[2];
6749
6750 n = mri_control_stack;
6751 while (n != NULL
6752 && n->type != mri_for
6753 && n->type != mri_repeat
6754 && n->type != mri_while)
6755 n = n->outer;
6756 if (n == NULL)
6757 {
6758 as_bad (_("next outside of structured loop"));
6759 ignore_rest_of_line ();
6760 return;
6761 }
6762
6763 buf = XNEWVEC (char, 20 + strlen (n->next));
6764 ex[0] = TOLOWER (extent);
6765 ex[1] = '\0';
6766 sprintf (buf, "bra%s %s", ex, n->next);
6767 mri_assemble (buf);
6768 free (buf);
6769
6770 if (flag_mri)
6771 {
6772 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6773 ++input_line_pointer;
6774 }
6775
6776 demand_empty_rest_of_line ();
6777 }
6778
6779 /* Handle the MRI FOR pseudo-op. */
6780
6781 static void
6782 s_mri_for (int qual)
6783 {
6784 const char *varstart, *varstop;
6785 const char *initstart, *initstop;
6786 const char *endstart, *endstop;
6787 const char *bystart, *bystop;
6788 int up;
6789 int by;
6790 int extent;
6791 struct mri_control_info *n;
6792 char *buf;
6793 char *s;
6794 char ex[2];
6795
6796 /* The syntax is
6797 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6798 */
6799
6800 SKIP_WHITESPACE ();
6801 varstart = input_line_pointer;
6802
6803 /* Look for the '='. */
6804 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6805 && *input_line_pointer != '=')
6806 ++input_line_pointer;
6807 if (*input_line_pointer != '=')
6808 {
6809 as_bad (_("missing ="));
6810 ignore_rest_of_line ();
6811 return;
6812 }
6813
6814 varstop = input_line_pointer;
6815 if (varstop > varstart
6816 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6817 --varstop;
6818
6819 ++input_line_pointer;
6820
6821 initstart = input_line_pointer;
6822
6823 /* Look for TO or DOWNTO. */
6824 up = 1;
6825 initstop = NULL;
6826 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6827 {
6828 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6829 && ! is_part_of_name (input_line_pointer[2]))
6830 {
6831 initstop = input_line_pointer;
6832 input_line_pointer += 2;
6833 break;
6834 }
6835 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6836 && ! is_part_of_name (input_line_pointer[6]))
6837 {
6838 initstop = input_line_pointer;
6839 up = 0;
6840 input_line_pointer += 6;
6841 break;
6842 }
6843 ++input_line_pointer;
6844 }
6845 if (initstop == NULL)
6846 {
6847 as_bad (_("missing to or downto"));
6848 ignore_rest_of_line ();
6849 return;
6850 }
6851 if (initstop > initstart
6852 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6853 --initstop;
6854
6855 SKIP_WHITESPACE ();
6856 endstart = input_line_pointer;
6857
6858 /* Look for BY or DO. */
6859 by = 0;
6860 endstop = NULL;
6861 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6862 {
6863 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6864 && ! is_part_of_name (input_line_pointer[2]))
6865 {
6866 endstop = input_line_pointer;
6867 by = 1;
6868 input_line_pointer += 2;
6869 break;
6870 }
6871 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6872 && (input_line_pointer[2] == '.'
6873 || ! is_part_of_name (input_line_pointer[2])))
6874 {
6875 endstop = input_line_pointer;
6876 input_line_pointer += 2;
6877 break;
6878 }
6879 ++input_line_pointer;
6880 }
6881 if (endstop == NULL)
6882 {
6883 as_bad (_("missing do"));
6884 ignore_rest_of_line ();
6885 return;
6886 }
6887 if (endstop > endstart
6888 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6889 --endstop;
6890
6891 if (! by)
6892 {
6893 bystart = "#1";
6894 bystop = bystart + 2;
6895 }
6896 else
6897 {
6898 SKIP_WHITESPACE ();
6899 bystart = input_line_pointer;
6900
6901 /* Look for DO. */
6902 bystop = NULL;
6903 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6904 {
6905 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6906 && (input_line_pointer[2] == '.'
6907 || ! is_part_of_name (input_line_pointer[2])))
6908 {
6909 bystop = input_line_pointer;
6910 input_line_pointer += 2;
6911 break;
6912 }
6913 ++input_line_pointer;
6914 }
6915 if (bystop == NULL)
6916 {
6917 as_bad (_("missing do"));
6918 ignore_rest_of_line ();
6919 return;
6920 }
6921 if (bystop > bystart
6922 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6923 --bystop;
6924 }
6925
6926 if (*input_line_pointer != '.')
6927 extent = '\0';
6928 else
6929 {
6930 extent = input_line_pointer[1];
6931 input_line_pointer += 2;
6932 }
6933
6934 /* We have fully parsed the FOR operands. Now build the loop. */
6935 n = push_mri_control (mri_for);
6936
6937 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart));
6938
6939 /* Move init,var. */
6940 s = buf;
6941 *s++ = 'm';
6942 *s++ = 'o';
6943 *s++ = 'v';
6944 *s++ = 'e';
6945 if (qual != '\0')
6946 *s++ = TOLOWER (qual);
6947 *s++ = ' ';
6948 memcpy (s, initstart, initstop - initstart);
6949 s += initstop - initstart;
6950 *s++ = ',';
6951 memcpy (s, varstart, varstop - varstart);
6952 s += varstop - varstart;
6953 *s = '\0';
6954 mri_assemble (buf);
6955
6956 colon (n->top);
6957
6958 /* cmp end,var. */
6959 s = buf;
6960 *s++ = 'c';
6961 *s++ = 'm';
6962 *s++ = 'p';
6963 if (qual != '\0')
6964 *s++ = TOLOWER (qual);
6965 *s++ = ' ';
6966 memcpy (s, endstart, endstop - endstart);
6967 s += endstop - endstart;
6968 *s++ = ',';
6969 memcpy (s, varstart, varstop - varstart);
6970 s += varstop - varstart;
6971 *s = '\0';
6972 mri_assemble (buf);
6973
6974 /* bcc bottom. */
6975 ex[0] = TOLOWER (extent);
6976 ex[1] = '\0';
6977 if (up)
6978 sprintf (buf, "blt%s %s", ex, n->bottom);
6979 else
6980 sprintf (buf, "bgt%s %s", ex, n->bottom);
6981 mri_assemble (buf);
6982
6983 /* Put together the add or sub instruction used by ENDF. */
6984 s = buf;
6985 if (up)
6986 strcpy (s, "add");
6987 else
6988 strcpy (s, "sub");
6989 s += 3;
6990 if (qual != '\0')
6991 *s++ = TOLOWER (qual);
6992 *s++ = ' ';
6993 memcpy (s, bystart, bystop - bystart);
6994 s += bystop - bystart;
6995 *s++ = ',';
6996 memcpy (s, varstart, varstop - varstart);
6997 s += varstop - varstart;
6998 *s = '\0';
6999 n->incr = buf;
7000
7001 if (flag_mri)
7002 {
7003 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7004 ++input_line_pointer;
7005 }
7006
7007 demand_empty_rest_of_line ();
7008 }
7009
7010 /* Handle the MRI ENDF pseudo-op. */
7011
7012 static void
7013 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
7014 {
7015 if (mri_control_stack == NULL
7016 || mri_control_stack->type != mri_for)
7017 {
7018 as_bad (_("endf without for"));
7019 ignore_rest_of_line ();
7020 return;
7021 }
7022
7023 colon (mri_control_stack->next);
7024
7025 mri_assemble (mri_control_stack->incr);
7026
7027 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7028 mri_assemble (mri_control_stack->incr);
7029
7030 free (mri_control_stack->incr);
7031
7032 colon (mri_control_stack->bottom);
7033
7034 pop_mri_control ();
7035
7036 if (flag_mri)
7037 {
7038 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7039 ++input_line_pointer;
7040 }
7041
7042 demand_empty_rest_of_line ();
7043 }
7044
7045 /* Handle the MRI REPEAT pseudo-op. */
7046
7047 static void
7048 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7049 {
7050 struct mri_control_info *n;
7051
7052 n = push_mri_control (mri_repeat);
7053 colon (n->top);
7054 if (flag_mri)
7055 {
7056 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7057 ++input_line_pointer;
7058 }
7059 demand_empty_rest_of_line ();
7060 }
7061
7062 /* Handle the MRI UNTIL pseudo-op. */
7063
7064 static void
7065 s_mri_until (int qual)
7066 {
7067 char *s;
7068
7069 if (mri_control_stack == NULL
7070 || mri_control_stack->type != mri_repeat)
7071 {
7072 as_bad (_("until without repeat"));
7073 ignore_rest_of_line ();
7074 return;
7075 }
7076
7077 colon (mri_control_stack->next);
7078
7079 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7080 ;
7081
7082 parse_mri_control_expression (s, qual, (const char *) NULL,
7083 mri_control_stack->top, '\0');
7084
7085 colon (mri_control_stack->bottom);
7086
7087 input_line_pointer = s;
7088
7089 pop_mri_control ();
7090
7091 if (flag_mri)
7092 {
7093 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7094 ++input_line_pointer;
7095 }
7096
7097 demand_empty_rest_of_line ();
7098 }
7099
7100 /* Handle the MRI WHILE pseudo-op. */
7101
7102 static void
7103 s_mri_while (int qual)
7104 {
7105 char *s;
7106
7107 struct mri_control_info *n;
7108
7109 s = input_line_pointer;
7110 /* We only accept '*' as introduction of comments if preceded by white space
7111 or at first column of a line (I think this can't actually happen here?)
7112 This is important when assembling:
7113 while d0 <ne> 12(a0,d0*2) do
7114 while d0 <ne> #CONST*20 do. */
7115 while (! (is_end_of_line[(unsigned char) *s]
7116 || (flag_mri
7117 && *s == '*'
7118 && (s == input_line_pointer
7119 || *(s-1) == ' '
7120 || *(s-1) == '\t'))))
7121 s++;
7122 --s;
7123 while (*s == ' ' || *s == '\t')
7124 --s;
7125 if (s - input_line_pointer > 1
7126 && s[-1] == '.')
7127 s -= 2;
7128 if (s - input_line_pointer < 2
7129 || strncasecmp (s - 1, "DO", 2) != 0)
7130 {
7131 as_bad (_("missing do"));
7132 ignore_rest_of_line ();
7133 return;
7134 }
7135
7136 n = push_mri_control (mri_while);
7137
7138 colon (n->next);
7139
7140 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7141 s[1] == '.' ? s[2] : '\0');
7142
7143 input_line_pointer = s + 1;
7144 if (*input_line_pointer == '.')
7145 input_line_pointer += 2;
7146
7147 if (flag_mri)
7148 {
7149 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7150 ++input_line_pointer;
7151 }
7152
7153 demand_empty_rest_of_line ();
7154 }
7155
7156 /* Handle the MRI ENDW pseudo-op. */
7157
7158 static void
7159 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7160 {
7161 char *buf;
7162
7163 if (mri_control_stack == NULL
7164 || mri_control_stack->type != mri_while)
7165 {
7166 as_bad (_("endw without while"));
7167 ignore_rest_of_line ();
7168 return;
7169 }
7170
7171 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next));
7172 sprintf (buf, "bra %s", mri_control_stack->next);
7173 mri_assemble (buf);
7174 free (buf);
7175
7176 colon (mri_control_stack->bottom);
7177
7178 pop_mri_control ();
7179
7180 if (flag_mri)
7181 {
7182 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7183 ++input_line_pointer;
7184 }
7185
7186 demand_empty_rest_of_line ();
7187 }
7188 \f
7189 /* Parse a .cpu directive. */
7190
7191 static void
7192 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7193 {
7194 char saved_char;
7195 char *name;
7196
7197 if (initialized)
7198 {
7199 as_bad (_("already assembled instructions"));
7200 ignore_rest_of_line ();
7201 return;
7202 }
7203
7204 name = input_line_pointer;
7205 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7206 input_line_pointer++;
7207 saved_char = *input_line_pointer;
7208 *input_line_pointer = 0;
7209
7210 m68k_set_cpu (name, 1, 0);
7211
7212 *input_line_pointer = saved_char;
7213 demand_empty_rest_of_line ();
7214 return;
7215 }
7216
7217 /* Parse a .arch directive. */
7218
7219 static void
7220 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7221 {
7222 char saved_char;
7223 char *name;
7224
7225 if (initialized)
7226 {
7227 as_bad (_("already assembled instructions"));
7228 ignore_rest_of_line ();
7229 return;
7230 }
7231
7232 name = input_line_pointer;
7233 while (*input_line_pointer && *input_line_pointer != ','
7234 && !ISSPACE (*input_line_pointer))
7235 input_line_pointer++;
7236 saved_char = *input_line_pointer;
7237 *input_line_pointer = 0;
7238
7239 if (m68k_set_arch (name, 1, 0))
7240 {
7241 /* Scan extensions. */
7242 do
7243 {
7244 *input_line_pointer++ = saved_char;
7245 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7246 break;
7247 name = input_line_pointer;
7248 while (*input_line_pointer && *input_line_pointer != ','
7249 && !ISSPACE (*input_line_pointer))
7250 input_line_pointer++;
7251 saved_char = *input_line_pointer;
7252 *input_line_pointer = 0;
7253 }
7254 while (m68k_set_extension (name, 1, 0));
7255 }
7256
7257 *input_line_pointer = saved_char;
7258 demand_empty_rest_of_line ();
7259 return;
7260 }
7261 \f
7262 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7263 if none is found, the caller is responsible for emitting an error
7264 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7265 cpu name, if it begins with a '6' (possibly skipping an intervening
7266 'c'. We also allow a 'c' in the same place. if NEGATED is
7267 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7268 the option is indeed negated. */
7269
7270 static const struct m68k_cpu *
7271 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7272 int allow_m, int *negated)
7273 {
7274 /* allow negated value? */
7275 if (negated)
7276 {
7277 *negated = 0;
7278
7279 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7280 {
7281 arg += 3;
7282 *negated = 1;
7283 }
7284 }
7285
7286 /* Remove 'm' or 'mc' prefix from 68k variants. */
7287 if (allow_m)
7288 {
7289 if (arg[0] == 'm')
7290 {
7291 if (arg[1] == '6')
7292 arg += 1;
7293 else if (arg[1] == 'c' && arg[2] == '6')
7294 arg += 2;
7295 }
7296 }
7297 else if (arg[0] == 'c' && arg[1] == '6')
7298 arg += 1;
7299
7300 for (; table->name; table++)
7301 if (!strcmp (arg, table->name))
7302 {
7303 if (table->alias < -1 || table->alias > 1)
7304 as_bad (_("`%s' is deprecated, use `%s'"),
7305 table->name, table[table->alias < 0 ? 1 : -1].name);
7306 return table;
7307 }
7308 return 0;
7309 }
7310
7311 /* Set the cpu, issuing errors if it is unrecognized. */
7312
7313 static int
7314 m68k_set_cpu (char const *name, int allow_m, int silent)
7315 {
7316 const struct m68k_cpu *cpu;
7317
7318 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7319
7320 if (!cpu)
7321 {
7322 if (!silent)
7323 as_bad (_("cpu `%s' unrecognized"), name);
7324 return 0;
7325 }
7326 selected_cpu = cpu;
7327 return 1;
7328 }
7329
7330 /* Set the architecture, issuing errors if it is unrecognized. */
7331
7332 static int
7333 m68k_set_arch (char const *name, int allow_m, int silent)
7334 {
7335 const struct m68k_cpu *arch;
7336
7337 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7338
7339 if (!arch)
7340 {
7341 if (!silent)
7342 as_bad (_("architecture `%s' unrecognized"), name);
7343 return 0;
7344 }
7345 selected_arch = arch;
7346 return 1;
7347 }
7348
7349 /* Set the architecture extension, issuing errors if it is
7350 unrecognized, or invalid */
7351
7352 static int
7353 m68k_set_extension (char const *name, int allow_m, int silent)
7354 {
7355 int negated;
7356 const struct m68k_cpu *ext;
7357
7358 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7359
7360 if (!ext)
7361 {
7362 if (!silent)
7363 as_bad (_("extension `%s' unrecognized"), name);
7364 return 0;
7365 }
7366
7367 if (negated)
7368 not_current_architecture |= (ext->control_regs
7369 ? *(unsigned *)ext->control_regs: ext->arch);
7370 else
7371 current_architecture |= ext->arch;
7372 return 1;
7373 }
7374
7375 /* md_parse_option
7376 Invocation line includes a switch not recognized by the base assembler.
7377 */
7378
7379 const char *md_shortopts = "lSA:m:kQ:V";
7380
7381 struct option md_longopts[] = {
7382 #define OPTION_PIC (OPTION_MD_BASE)
7383 {"pic", no_argument, NULL, OPTION_PIC},
7384 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7385 {"register-prefix-optional", no_argument, NULL,
7386 OPTION_REGISTER_PREFIX_OPTIONAL},
7387 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7388 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7389 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7390 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7391 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7392 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7393 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7394 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7395 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7396 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7397 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7398 {"pcrel", no_argument, NULL, OPTION_PCREL},
7399 {NULL, no_argument, NULL, 0}
7400 };
7401 size_t md_longopts_size = sizeof (md_longopts);
7402
7403 int
7404 md_parse_option (int c, const char *arg)
7405 {
7406 switch (c)
7407 {
7408 case 'l': /* -l means keep external to 2 bit offset
7409 rather than 16 bit one. */
7410 flag_short_refs = 1;
7411 break;
7412
7413 case 'S': /* -S means that jbsr's always turn into
7414 jsr's. */
7415 flag_long_jumps = 1;
7416 break;
7417
7418 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7419 branches into absolute jumps. */
7420 flag_keep_pcrel = 1;
7421 break;
7422
7423 case OPTION_PIC:
7424 case 'k':
7425 flag_want_pic = 1;
7426 break; /* -pic, Position Independent Code. */
7427
7428 case OPTION_REGISTER_PREFIX_OPTIONAL:
7429 flag_reg_prefix_optional = 1;
7430 reg_prefix_optional_seen = 1;
7431 break;
7432
7433 /* -V: SVR4 argument to print version ID. */
7434 case 'V':
7435 print_version_id ();
7436 break;
7437
7438 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7439 should be emitted or not. FIXME: Not implemented. */
7440 case 'Q':
7441 break;
7442
7443 case OPTION_BITWISE_OR:
7444 {
7445 char *n, *t;
7446 const char *s;
7447
7448 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1);
7449 t = n;
7450 for (s = m68k_comment_chars; *s != '\0'; s++)
7451 if (*s != '|')
7452 *t++ = *s;
7453 *t = '\0';
7454 m68k_comment_chars = n;
7455 }
7456 break;
7457
7458 case OPTION_BASE_SIZE_DEFAULT_16:
7459 m68k_index_width_default = SIZE_WORD;
7460 break;
7461
7462 case OPTION_BASE_SIZE_DEFAULT_32:
7463 m68k_index_width_default = SIZE_LONG;
7464 break;
7465
7466 case OPTION_DISP_SIZE_DEFAULT_16:
7467 m68k_rel32 = 0;
7468 m68k_rel32_from_cmdline = 1;
7469 break;
7470
7471 case OPTION_DISP_SIZE_DEFAULT_32:
7472 m68k_rel32 = 1;
7473 m68k_rel32_from_cmdline = 1;
7474 break;
7475
7476 case 'A':
7477 #if WARN_DEPRECATED
7478 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7479 arg, arg));
7480 #endif
7481 /* Intentional fall-through. */
7482 case 'm':
7483 if (!strncmp (arg, "arch=", 5))
7484 m68k_set_arch (arg + 5, 1, 0);
7485 else if (!strncmp (arg, "cpu=", 4))
7486 m68k_set_cpu (arg + 4, 1, 0);
7487 else if (m68k_set_extension (arg, 0, 1))
7488 ;
7489 else if (m68k_set_arch (arg, 0, 1))
7490 ;
7491 else if (m68k_set_cpu (arg, 0, 1))
7492 ;
7493 else
7494 return 0;
7495 break;
7496
7497 default:
7498 return 0;
7499 }
7500
7501 return 1;
7502 }
7503
7504 /* Setup tables from the selected arch and/or cpu */
7505
7506 static void
7507 m68k_init_arch (void)
7508 {
7509 if (not_current_architecture & current_architecture)
7510 {
7511 as_bad (_("architecture features both enabled and disabled"));
7512 not_current_architecture &= ~current_architecture;
7513 }
7514 if (selected_arch)
7515 {
7516 current_architecture |= selected_arch->arch;
7517 control_regs = selected_arch->control_regs;
7518 }
7519 else
7520 current_architecture |= selected_cpu->arch;
7521
7522 current_architecture &= ~not_current_architecture;
7523
7524 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7525 {
7526 /* Determine which float is really meant. */
7527 if (current_architecture & (m68k_mask & ~m68881))
7528 current_architecture ^= cfloat;
7529 else
7530 current_architecture ^= m68881;
7531 }
7532
7533 if (selected_cpu)
7534 {
7535 control_regs = selected_cpu->control_regs;
7536 if (current_architecture & ~selected_cpu->arch)
7537 {
7538 as_bad (_("selected processor does not have all features of selected architecture"));
7539 current_architecture
7540 = selected_cpu->arch & ~not_current_architecture;
7541 }
7542 }
7543
7544 if ((current_architecture & m68k_mask)
7545 && (current_architecture & ~m68k_mask))
7546 {
7547 as_bad (_ ("m68k and cf features both selected"));
7548 if (current_architecture & m68k_mask)
7549 current_architecture &= m68k_mask;
7550 else
7551 current_architecture &= ~m68k_mask;
7552 }
7553
7554 /* Permit m68881 specification with all cpus; those that can't work
7555 with a coprocessor could be doing emulation. */
7556 if (current_architecture & m68851)
7557 {
7558 if (current_architecture & m68040)
7559 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7560 }
7561 /* What other incompatibilities could we check for? */
7562
7563 if (cpu_of_arch (current_architecture) < m68020
7564 || arch_coldfire_p (current_architecture))
7565 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7566
7567 initialized = 1;
7568 }
7569
7570 void
7571 md_show_usage (FILE *stream)
7572 {
7573 const char *default_cpu = TARGET_CPU;
7574 int i;
7575
7576 /* Get the canonical name for the default target CPU. */
7577 if (*default_cpu == 'm')
7578 default_cpu++;
7579 for (i = 0; m68k_cpus[i].name; i++)
7580 {
7581 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7582 {
7583 while (m68k_cpus[i].alias > 0)
7584 i--;
7585 while (m68k_cpus[i].alias < 0)
7586 i++;
7587 default_cpu = m68k_cpus[i].name;
7588 }
7589 }
7590
7591 fprintf (stream, _("\
7592 -march=<arch> set architecture\n\
7593 -mcpu=<cpu> set cpu [default %s]\n\
7594 "), default_cpu);
7595 for (i = 0; m68k_extensions[i].name; i++)
7596 fprintf (stream, _("\
7597 -m[no-]%-16s enable/disable %s architecture extension\n\
7598 "), m68k_extensions[i].name,
7599 m68k_extensions[i].alias > 0 ? " ColdFire"
7600 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7601
7602 fprintf (stream, _("\
7603 -l use 1 word for refs to undefined symbols [default 2]\n\
7604 -pic, -k generate position independent code\n\
7605 -S turn jbsr into jsr\n\
7606 --pcrel never turn PC-relative branches into absolute jumps\n\
7607 --register-prefix-optional\n\
7608 recognize register names without prefix character\n\
7609 --bitwise-or do not treat `|' as a comment character\n\
7610 --base-size-default-16 base reg without size is 16 bits\n\
7611 --base-size-default-32 base reg without size is 32 bits (default)\n\
7612 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7613 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7614 "));
7615
7616 fprintf (stream, _("Architecture variants are: "));
7617 for (i = 0; m68k_archs[i].name; i++)
7618 {
7619 if (i)
7620 fprintf (stream, " | ");
7621 fprintf (stream, "%s", m68k_archs[i].name);
7622 }
7623 fprintf (stream, "\n");
7624
7625 fprintf (stream, _("Processor variants are: "));
7626 for (i = 0; m68k_cpus[i].name; i++)
7627 {
7628 if (i)
7629 fprintf (stream, " | ");
7630 fprintf (stream, "%s", m68k_cpus[i].name);
7631 }
7632 fprintf (stream, _("\n"));
7633 }
7634 \f
7635 #ifdef TEST2
7636
7637 /* TEST2: Test md_assemble() */
7638 /* Warning, this routine probably doesn't work anymore. */
7639 int
7640 main (void)
7641 {
7642 struct m68k_it the_ins;
7643 char buf[120];
7644 char *cp;
7645 int n;
7646
7647 m68k_ip_begin ();
7648 for (;;)
7649 {
7650 if (!gets (buf) || !*buf)
7651 break;
7652 if (buf[0] == '|' || buf[1] == '.')
7653 continue;
7654 for (cp = buf; *cp; cp++)
7655 if (*cp == '\t')
7656 *cp = ' ';
7657 if (is_label (buf))
7658 continue;
7659 memset (&the_ins, '\0', sizeof (the_ins));
7660 m68k_ip (&the_ins, buf);
7661 if (the_ins.error)
7662 {
7663 printf (_("Error %s in %s\n"), the_ins.error, buf);
7664 }
7665 else
7666 {
7667 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7668 for (n = 0; n < the_ins.numo; n++)
7669 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7670 printf (" ");
7671 print_the_insn (&the_ins.opcode[0], stdout);
7672 (void) putchar ('\n');
7673 }
7674 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7675 {
7676 if (the_ins.operands[n].error)
7677 {
7678 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7679 continue;
7680 }
7681 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7682 the_ins.operands[n].reg);
7683 if (the_ins.operands[n].b_const)
7684 printf ("Constant: '%.*s', ",
7685 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7686 the_ins.operands[n].b_const);
7687 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7688 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7689 if (the_ins.operands[n].b_iadd)
7690 printf ("Iadd: '%.*s',",
7691 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7692 the_ins.operands[n].b_iadd);
7693 putchar ('\n');
7694 }
7695 }
7696 m68k_ip_end ();
7697 return 0;
7698 }
7699
7700 int
7701 is_label (char *str)
7702 {
7703 while (*str == ' ')
7704 str++;
7705 while (*str && *str != ' ')
7706 str++;
7707 if (str[-1] == ':' || str[1] == '=')
7708 return 1;
7709 return 0;
7710 }
7711
7712 #endif
7713
7714 /* Possible states for relaxation:
7715
7716 0 0 branch offset byte (bra, etc)
7717 0 1 word
7718 0 2 long
7719
7720 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7721 1 1 word
7722 1 2 long
7723
7724 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7725 2 1 word-long
7726 2 2 long-word
7727 2 3 long-long
7728
7729 */
7730
7731 /* We have no need to default values of symbols. */
7732
7733 symbolS *
7734 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7735 {
7736 return 0;
7737 }
7738
7739 /* Round up a section size to the appropriate boundary. */
7740 valueT
7741 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7742 {
7743 return size;
7744 }
7745
7746 /* Exactly what point is a PC-relative offset relative TO?
7747 On the 68k, it is relative to the address of the first extension
7748 word. The difference between the addresses of the offset and the
7749 first extension word is stored in fx_pcrel_adjust. */
7750 long
7751 md_pcrel_from (fixS *fixP)
7752 {
7753 int adjust;
7754
7755 adjust = fixP->fx_pcrel_adjust;
7756 if (adjust == 64)
7757 adjust = -1;
7758 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7759 }
7760
7761 void
7762 m68k_elf_final_processing (void)
7763 {
7764 unsigned flags = 0;
7765
7766 if (arch_coldfire_fpu (current_architecture))
7767 flags |= EF_M68K_CFV4E;
7768 /* Set file-specific flags if this is a cpu32 processor. */
7769 if (cpu_of_arch (current_architecture) & cpu32)
7770 flags |= EF_M68K_CPU32;
7771 else if (cpu_of_arch (current_architecture) & fido_a)
7772 flags |= EF_M68K_FIDO;
7773 else if ((cpu_of_arch (current_architecture) & m68000up)
7774 && !(cpu_of_arch (current_architecture) & m68020up))
7775 flags |= EF_M68K_M68000;
7776
7777 if (current_architecture & mcfisa_a)
7778 {
7779 static const unsigned isa_features[][2] =
7780 {
7781 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7782 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7783 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7784 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7785 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7786 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7787 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7788 {0,0},
7789 };
7790 static const unsigned mac_features[][2] =
7791 {
7792 {EF_M68K_CF_MAC, mcfmac},
7793 {EF_M68K_CF_EMAC, mcfemac},
7794 {0,0},
7795 };
7796 unsigned ix;
7797 unsigned pattern;
7798
7799 pattern = (current_architecture
7800 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7801 for (ix = 0; isa_features[ix][1]; ix++)
7802 {
7803 if (pattern == isa_features[ix][1])
7804 {
7805 flags |= isa_features[ix][0];
7806 break;
7807 }
7808 }
7809 if (!isa_features[ix][1])
7810 {
7811 cf_bad:
7812 as_warn (_("Not a defined coldfire architecture"));
7813 }
7814 else
7815 {
7816 if (current_architecture & cfloat)
7817 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7818
7819 pattern = current_architecture & (mcfmac|mcfemac);
7820 if (pattern)
7821 {
7822 for (ix = 0; mac_features[ix][1]; ix++)
7823 {
7824 if (pattern == mac_features[ix][1])
7825 {
7826 flags |= mac_features[ix][0];
7827 break;
7828 }
7829 }
7830 if (!mac_features[ix][1])
7831 goto cf_bad;
7832 }
7833 }
7834 }
7835 elf_elfheader (stdoutput)->e_flags |= flags;
7836 }
7837
7838 /* Parse @TLSLDO and return the desired relocation. */
7839 static bfd_reloc_code_real_type
7840 m68k_elf_suffix (char **str_p, expressionS *exp_p)
7841 {
7842 char ident[20];
7843 char *str = *str_p;
7844 char *str2;
7845 int ch;
7846 int len;
7847
7848 if (*str++ != '@')
7849 return BFD_RELOC_UNUSED;
7850
7851 for (ch = *str, str2 = ident;
7852 (str2 < ident + sizeof (ident) - 1
7853 && (ISALNUM (ch) || ch == '@'));
7854 ch = *++str)
7855 {
7856 *str2++ = ch;
7857 }
7858
7859 *str2 = '\0';
7860 len = str2 - ident;
7861
7862 if (strncmp (ident, "TLSLDO", 6) == 0
7863 && len == 6)
7864 {
7865 /* Now check for identifier@suffix+constant. */
7866 if (*str == '-' || *str == '+')
7867 {
7868 char *orig_line = input_line_pointer;
7869 expressionS new_exp;
7870
7871 input_line_pointer = str;
7872 expression (&new_exp);
7873 if (new_exp.X_op == O_constant)
7874 {
7875 exp_p->X_add_number += new_exp.X_add_number;
7876 str = input_line_pointer;
7877 }
7878
7879 if (&input_line_pointer != str_p)
7880 input_line_pointer = orig_line;
7881 }
7882 *str_p = str;
7883
7884 return BFD_RELOC_68K_TLS_LDO32;
7885 }
7886
7887 return BFD_RELOC_UNUSED;
7888 }
7889
7890 /* Handles .long <tls_symbol>+0x8000 debug info.
7891 Clobbers input_line_pointer, checks end-of-line.
7892 Adapted from tc-ppc.c:ppc_elf_cons. */
7893 static void
7894 m68k_elf_cons (int nbytes /* 4=.long */)
7895 {
7896 if (is_it_end_of_statement ())
7897 {
7898 demand_empty_rest_of_line ();
7899 return;
7900 }
7901
7902 do
7903 {
7904 expressionS exp;
7905 bfd_reloc_code_real_type reloc;
7906
7907 expression (&exp);
7908 if (exp.X_op == O_symbol
7909 && *input_line_pointer == '@'
7910 && (reloc = m68k_elf_suffix (&input_line_pointer,
7911 &exp)) != BFD_RELOC_UNUSED)
7912 {
7913 reloc_howto_type *reloc_howto;
7914 int size;
7915
7916 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
7917 size = bfd_get_reloc_size (reloc_howto);
7918
7919 if (size > nbytes)
7920 {
7921 as_bad (ngettext ("%s relocations do not fit in %u byte",
7922 "%s relocations do not fit in %u bytes",
7923 nbytes),
7924 reloc_howto->name, nbytes);
7925 }
7926 else
7927 {
7928 char *p;
7929 int offset;
7930
7931 p = frag_more (nbytes);
7932 offset = 0;
7933 if (target_big_endian)
7934 offset = nbytes - size;
7935 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7936 &exp, 0, reloc);
7937 }
7938 }
7939 else
7940 emit_expr (&exp, (unsigned int) nbytes);
7941 }
7942 while (*input_line_pointer++ == ',');
7943
7944 /* Put terminator back into stream. */
7945 input_line_pointer--;
7946 demand_empty_rest_of_line ();
7947 }
7948
7949 /* Parse a .gnu_attribute directive. */
7950 static void
7951 m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
7952 {
7953 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU);
7954
7955 /* Check validity of defined m68k tags. */
7956 if (tag == Tag_GNU_M68K_ABI_FP)
7957 {
7958 unsigned int val;
7959
7960 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag);
7961
7962 if (tag == Tag_GNU_M68K_ABI_FP && val > 2)
7963 as_warn (_("unknown .gnu_attribute value"));
7964 }
7965 }
7966
7967 int
7968 tc_m68k_regname_to_dw2regnum (const char *regname)
7969 {
7970 unsigned int regnum;
7971 static const char *const regnames[] =
7972 {
7973 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7974 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7975 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7976 "pc"
7977 };
7978
7979 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7980 if (strcmp (regname, regnames[regnum]) == 0)
7981 return regnum;
7982
7983 return -1;
7984 }
7985
7986 void
7987 tc_m68k_frame_initial_instructions (void)
7988 {
7989 static int sp_regno = -1;
7990
7991 if (sp_regno < 0)
7992 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7993
7994 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7995 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7996 }
7997
7998 /* Check and emit error if broken-word handling has failed to fix up a
7999 case-table. This is called from write.c, after doing everything it
8000 knows about how to handle broken words. */
8001
8002 void
8003 tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
8004 {
8005 if (new_offset > 32767 || new_offset < -32768)
8006 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
8007 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
8008 (long) new_offset);
8009 }
8010
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