1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2022 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= false;
86 int mips_flag_pdr
= true;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
109 #define ILLEGAL_REG (32)
111 #define AT mips_opts.at
113 extern int target_big_endian
;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME ".rodata"
118 /* Ways in which an instruction can be "appended" to the output. */
120 /* Just add it normally. */
123 /* Add it normally and then add a nop. */
126 /* Turn an instruction with a delay slot into a "compact" version. */
129 /* Insert the instruction before the last one. */
133 /* Information about an instruction, including its format, operands
137 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
138 const struct mips_opcode
*insn_mo
;
140 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
141 a copy of INSN_MO->match with the operands filled in. If we have
142 decided to use an extended MIPS16 instruction, this includes the
144 unsigned long insn_opcode
;
146 /* The name if this is an label. */
149 /* The target label name if this is an branch. */
152 /* The frag that contains the instruction. */
155 /* The offset into FRAG of the first instruction byte. */
158 /* The relocs associated with the instruction, if any. */
161 /* True if this entry cannot be moved from its current position. */
162 unsigned int fixed_p
: 1;
164 /* True if this instruction occurred in a .set noreorder block. */
165 unsigned int noreorder_p
: 1;
167 /* True for mips16 instructions that jump to an absolute address. */
168 unsigned int mips16_absolute_jump_p
: 1;
170 /* True if this instruction is complete. */
171 unsigned int complete_p
: 1;
173 /* True if this instruction is cleared from history by unconditional
175 unsigned int cleared_p
: 1;
178 /* The ABI to use. */
189 /* MIPS ABI we are using for this output file. */
190 static enum mips_abi_level mips_abi
= NO_ABI
;
192 /* Whether or not we have code that can call pic code. */
193 int mips_abicalls
= false;
195 /* Whether or not we have code which can be put into a shared
197 static bool mips_in_shared
= true;
199 /* This is the set of options which may be modified by the .set
200 pseudo-op. We use a struct so that .set push and .set pop are more
203 struct mips_set_options
205 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
206 if it has not been initialized. Changed by `.set mipsN', and the
207 -mipsN command line option, and the default CPU. */
209 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
210 <asename>', by command line options, and based on the default
213 /* Whether we are assembling for the mips16 processor. 0 if we are
214 not, 1 if we are, and -1 if the value has not been initialized.
215 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
216 -nomips16 command line options, and the default CPU. */
218 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
219 1 if we are, and -1 if the value has not been initialized. Changed
220 by `.set micromips' and `.set nomicromips', and the -mmicromips
221 and -mno-micromips command line options, and the default CPU. */
223 /* Non-zero if we should not reorder instructions. Changed by `.set
224 reorder' and `.set noreorder'. */
226 /* Non-zero if we should not permit the register designated "assembler
227 temporary" to be used in instructions. The value is the register
228 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
229 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
231 /* Non-zero if we should warn when a macro instruction expands into
232 more than one machine instruction. Changed by `.set nomacro' and
234 int warn_about_macros
;
235 /* Non-zero if we should not move instructions. Changed by `.set
236 move', `.set volatile', `.set nomove', and `.set novolatile'. */
238 /* Non-zero if we should not optimize branches by moving the target
239 of the branch into the delay slot. Actually, we don't perform
240 this optimization anyhow. Changed by `.set bopt' and `.set
243 /* Non-zero if we should not autoextend mips16 instructions.
244 Changed by `.set autoextend' and `.set noautoextend'. */
246 /* True if we should only emit 32-bit microMIPS instructions.
247 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
248 and -mno-insn32 command line options. */
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
258 /* True if ".set sym32" is in effect. */
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
270 /* 1 if single-precision operations on odd-numbered registers are
274 /* The set of ASEs that should be enabled for the user specified
275 architecture. This cannot be inferred from 'arch' for all cores
276 as processors only have a unique 'arch' if they add architecture
277 specific instructions (UDI). */
281 /* Specifies whether module level options have been checked yet. */
282 static bool file_mips_opts_checked
= false;
284 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
285 value has not been initialized. Changed by `.nan legacy' and
286 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
287 options, and the default CPU. */
288 static int mips_nan2008
= -1;
290 /* This is the struct we use to hold the module level set of options.
291 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
292 fp fields to -1 to indicate that they have not been initialized. */
294 static struct mips_set_options file_mips_opts
=
296 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
297 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
298 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
299 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ false,
300 /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
304 /* This is similar to file_mips_opts, but for the current set of options. */
306 static struct mips_set_options mips_opts
=
308 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
309 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
310 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
311 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ false,
312 /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
316 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
317 static unsigned int file_ase_explicit
;
319 /* These variables are filled in with the masks of registers used.
320 The object format code reads them and puts them in the appropriate
322 unsigned long mips_gprmask
;
323 unsigned long mips_cprmask
[4];
325 /* True if any MIPS16 code was produced. */
326 static int file_ase_mips16
;
328 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
329 || mips_opts.isa == ISA_MIPS32R2 \
330 || mips_opts.isa == ISA_MIPS32R3 \
331 || mips_opts.isa == ISA_MIPS32R5 \
332 || mips_opts.isa == ISA_MIPS64 \
333 || mips_opts.isa == ISA_MIPS64R2 \
334 || mips_opts.isa == ISA_MIPS64R3 \
335 || mips_opts.isa == ISA_MIPS64R5)
337 /* True if any microMIPS code was produced. */
338 static int file_ase_micromips
;
340 /* True if we want to create R_MIPS_JALR for jalr $25. */
342 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
344 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
345 because there's no place for any addend, the only acceptable
346 expression is a bare symbol. */
347 #define MIPS_JALR_HINT_P(EXPR) \
348 (!HAVE_IN_PLACE_ADDENDS \
349 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
352 /* The argument of the -march= flag. The architecture we are assembling. */
353 static const char *mips_arch_string
;
355 /* The argument of the -mtune= flag. The architecture for which we
357 static int mips_tune
= CPU_UNKNOWN
;
358 static const char *mips_tune_string
;
360 /* True when generating 32-bit code for a 64-bit processor. */
361 static int mips_32bitmode
= 0;
363 /* True if the given ABI requires 32-bit registers. */
364 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
366 /* Likewise 64-bit registers. */
367 #define ABI_NEEDS_64BIT_REGS(ABI) \
369 || (ABI) == N64_ABI \
372 #define ISA_IS_R6(ISA) \
373 ((ISA) == ISA_MIPS32R6 \
374 || (ISA) == ISA_MIPS64R6)
376 /* Return true if ISA supports 64 bit wide gp registers. */
377 #define ISA_HAS_64BIT_REGS(ISA) \
378 ((ISA) == ISA_MIPS3 \
379 || (ISA) == ISA_MIPS4 \
380 || (ISA) == ISA_MIPS5 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2 \
383 || (ISA) == ISA_MIPS64R3 \
384 || (ISA) == ISA_MIPS64R5 \
385 || (ISA) == ISA_MIPS64R6)
387 /* Return true if ISA supports 64 bit wide float registers. */
388 #define ISA_HAS_64BIT_FPRS(ISA) \
389 ((ISA) == ISA_MIPS3 \
390 || (ISA) == ISA_MIPS4 \
391 || (ISA) == ISA_MIPS5 \
392 || (ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS32R3 \
394 || (ISA) == ISA_MIPS32R5 \
395 || (ISA) == ISA_MIPS32R6 \
396 || (ISA) == ISA_MIPS64 \
397 || (ISA) == ISA_MIPS64R2 \
398 || (ISA) == ISA_MIPS64R3 \
399 || (ISA) == ISA_MIPS64R5 \
400 || (ISA) == ISA_MIPS64R6)
402 /* Return true if ISA supports 64-bit right rotate (dror et al.)
404 #define ISA_HAS_DROR(ISA) \
405 ((ISA) == ISA_MIPS64R2 \
406 || (ISA) == ISA_MIPS64R3 \
407 || (ISA) == ISA_MIPS64R5 \
408 || (ISA) == ISA_MIPS64R6 \
409 || (mips_opts.micromips \
410 && ISA_HAS_64BIT_REGS (ISA)) \
413 /* Return true if ISA supports 32-bit right rotate (ror et al.)
415 #define ISA_HAS_ROR(ISA) \
416 ((ISA) == ISA_MIPS32R2 \
417 || (ISA) == ISA_MIPS32R3 \
418 || (ISA) == ISA_MIPS32R5 \
419 || (ISA) == ISA_MIPS32R6 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (mips_opts.ase & ASE_SMARTMIPS) \
425 || mips_opts.micromips \
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
430 (((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS32R3 \
433 || (ISA) == ISA_MIPS32R5 \
434 || (ISA) == ISA_MIPS32R6 \
435 || (ISA) == ISA_MIPS64 \
436 || (ISA) == ISA_MIPS64R2 \
437 || (ISA) == ISA_MIPS64R3 \
438 || (ISA) == ISA_MIPS64R5 \
439 || (ISA) == ISA_MIPS64R6 \
440 || (CPU) == CPU_R5900) \
441 && ((CPU) != CPU_GS464 \
442 || (CPU) != CPU_GS464E \
443 || (CPU) != CPU_GS264E))
445 /* Return true if ISA supports move to/from high part of a 64-bit
446 floating-point register. */
447 #define ISA_HAS_MXHC1(ISA) \
448 ((ISA) == ISA_MIPS32R2 \
449 || (ISA) == ISA_MIPS32R3 \
450 || (ISA) == ISA_MIPS32R5 \
451 || (ISA) == ISA_MIPS32R6 \
452 || (ISA) == ISA_MIPS64R2 \
453 || (ISA) == ISA_MIPS64R3 \
454 || (ISA) == ISA_MIPS64R5 \
455 || (ISA) == ISA_MIPS64R6)
457 /* Return true if ISA supports legacy NAN. */
458 #define ISA_HAS_LEGACY_NAN(ISA) \
459 ((ISA) == ISA_MIPS1 \
460 || (ISA) == ISA_MIPS2 \
461 || (ISA) == ISA_MIPS3 \
462 || (ISA) == ISA_MIPS4 \
463 || (ISA) == ISA_MIPS5 \
464 || (ISA) == ISA_MIPS32 \
465 || (ISA) == ISA_MIPS32R2 \
466 || (ISA) == ISA_MIPS32R3 \
467 || (ISA) == ISA_MIPS32R5 \
468 || (ISA) == ISA_MIPS64 \
469 || (ISA) == ISA_MIPS64R2 \
470 || (ISA) == ISA_MIPS64R3 \
471 || (ISA) == ISA_MIPS64R5)
474 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
479 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
483 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
485 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
487 /* True if relocations are stored in-place. */
488 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
490 /* The ABI-derived address size. */
491 #define HAVE_64BIT_ADDRESSES \
492 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
493 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
495 /* The size of symbolic constants (i.e., expressions of the form
496 "SYMBOL" or "SYMBOL + OFFSET"). */
497 #define HAVE_32BIT_SYMBOLS \
498 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
499 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
501 /* Addresses are loaded in different ways, depending on the address size
502 in use. The n32 ABI Documentation also mandates the use of additions
503 with overflow checking, but existing implementations don't follow it. */
504 #define ADDRESS_ADD_INSN \
505 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
507 #define ADDRESS_ADDI_INSN \
508 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
510 #define ADDRESS_LOAD_INSN \
511 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
513 #define ADDRESS_STORE_INSN \
514 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
516 /* Return true if the given CPU supports the MIPS16 ASE. */
517 #define CPU_HAS_MIPS16(cpu) \
518 (startswith (TARGET_CPU, "mips16") \
519 || startswith (TARGET_CANONICAL, "mips-lsi-elf"))
521 /* Return true if the given CPU supports the microMIPS ASE. */
522 #define CPU_HAS_MICROMIPS(cpu) 0
524 /* True if CPU has a dror instruction. */
525 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
527 /* True if CPU has a ror instruction. */
528 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
530 /* True if CPU is in the Octeon family. */
531 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
532 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
534 /* True if CPU has seq/sne and seqi/snei instructions. */
535 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
537 /* True, if CPU has support for ldc1 and sdc1. */
538 #define CPU_HAS_LDC1_SDC1(CPU) \
539 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
541 /* True if mflo and mfhi can be immediately followed by instructions
542 which write to the HI and LO registers.
544 According to MIPS specifications, MIPS ISAs I, II, and III need
545 (at least) two instructions between the reads of HI/LO and
546 instructions which write them, and later ISAs do not. Contradicting
547 the MIPS specifications, some MIPS IV processor user manuals (e.g.
548 the UM for the NEC Vr5000) document needing the instructions between
549 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
550 MIPS64 and later ISAs to have the interlocks, plus any specific
551 earlier-ISA CPUs for which CPU documentation declares that the
552 instructions are really interlocked. */
553 #define hilo_interlocks \
554 (mips_opts.isa == ISA_MIPS32 \
555 || mips_opts.isa == ISA_MIPS32R2 \
556 || mips_opts.isa == ISA_MIPS32R3 \
557 || mips_opts.isa == ISA_MIPS32R5 \
558 || mips_opts.isa == ISA_MIPS32R6 \
559 || mips_opts.isa == ISA_MIPS64 \
560 || mips_opts.isa == ISA_MIPS64R2 \
561 || mips_opts.isa == ISA_MIPS64R3 \
562 || mips_opts.isa == ISA_MIPS64R5 \
563 || mips_opts.isa == ISA_MIPS64R6 \
564 || mips_opts.arch == CPU_R4010 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.arch == CPU_R10000 \
567 || mips_opts.arch == CPU_R12000 \
568 || mips_opts.arch == CPU_R14000 \
569 || mips_opts.arch == CPU_R16000 \
570 || mips_opts.arch == CPU_RM7000 \
571 || mips_opts.arch == CPU_VR5500 \
572 || mips_opts.micromips \
575 /* Whether the processor uses hardware interlocks to protect reads
576 from the GPRs after they are loaded from memory, and thus does not
577 require nops to be inserted. This applies to instructions marked
578 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
579 level I and microMIPS mode instructions are always interlocked. */
580 #define gpr_interlocks \
581 (mips_opts.isa != ISA_MIPS1 \
582 || mips_opts.arch == CPU_R3900 \
583 || mips_opts.arch == CPU_R5900 \
584 || mips_opts.micromips \
587 /* Whether the processor uses hardware interlocks to avoid delays
588 required by coprocessor instructions, and thus does not require
589 nops to be inserted. This applies to instructions marked
590 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
591 instructions marked INSN_WRITE_COND_CODE and ones marked
592 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
593 levels I, II, and III and microMIPS mode instructions are always
595 /* Itbl support may require additional care here. */
596 #define cop_interlocks \
597 ((mips_opts.isa != ISA_MIPS1 \
598 && mips_opts.isa != ISA_MIPS2 \
599 && mips_opts.isa != ISA_MIPS3) \
600 || mips_opts.arch == CPU_R4300 \
601 || mips_opts.micromips \
604 /* Whether the processor uses hardware interlocks to protect reads
605 from coprocessor registers after they are loaded from memory, and
606 thus does not require nops to be inserted. This applies to
607 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
608 requires at MIPS ISA level I and microMIPS mode instructions are
609 always interlocked. */
610 #define cop_mem_interlocks \
611 (mips_opts.isa != ISA_MIPS1 \
612 || mips_opts.micromips \
615 /* Is this a mfhi or mflo instruction? */
616 #define MF_HILO_INSN(PINFO) \
617 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
619 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
620 has been selected. This implies, in particular, that addresses of text
621 labels have their LSB set. */
622 #define HAVE_CODE_COMPRESSION \
623 ((mips_opts.mips16 | mips_opts.micromips) != 0)
625 /* The minimum and maximum signed values that can be stored in a GPR. */
626 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
627 #define GPR_SMIN (-GPR_SMAX - 1)
629 /* MIPS PIC level. */
631 enum mips_pic_level mips_pic
;
633 /* 1 if we should generate 32 bit offsets from the $gp register in
634 SVR4_PIC mode. Currently has no meaning in other modes. */
635 static int mips_big_got
= 0;
637 /* 1 if trap instructions should used for overflow rather than break
639 static int mips_trap
= 0;
641 /* 1 if double width floating point constants should not be constructed
642 by assembling two single width halves into two single width floating
643 point registers which just happen to alias the double width destination
644 register. On some architectures this aliasing can be disabled by a bit
645 in the status register, and the setting of this bit cannot be determined
646 automatically at assemble time. */
647 static int mips_disable_float_construction
;
649 /* Non-zero if any .set noreorder directives were used. */
651 static int mips_any_noreorder
;
653 /* Non-zero if nops should be inserted when the register referenced in
654 an mfhi/mflo instruction is read in the next two instructions. */
655 static int mips_7000_hilo_fix
;
657 /* The size of objects in the small data section. */
658 static unsigned int g_switch_value
= 8;
659 /* Whether the -G option was used. */
660 static int g_switch_seen
= 0;
665 /* If we can determine in advance that GP optimization won't be
666 possible, we can skip the relaxation stuff that tries to produce
667 GP-relative references. This makes delay slot optimization work
670 This function can only provide a guess, but it seems to work for
671 gcc output. It needs to guess right for gcc, otherwise gcc
672 will put what it thinks is a GP-relative instruction in a branch
675 I don't know if a fix is needed for the SVR4_PIC mode. I've only
676 fixed it for the non-PIC mode. KR 95/04/07 */
677 static int nopic_need_relax (symbolS
*, int);
679 /* Handle of the OPCODE hash table. */
680 static htab_t op_hash
= NULL
;
682 /* The opcode hash table we use for the mips16. */
683 static htab_t mips16_op_hash
= NULL
;
685 /* The opcode hash table we use for the microMIPS ASE. */
686 static htab_t micromips_op_hash
= NULL
;
688 /* This array holds the chars that always start a comment. If the
689 pre-processor is disabled, these aren't very useful. */
690 const char comment_chars
[] = "#";
692 /* This array holds the chars that only start a comment at the beginning of
693 a line. If the line seems to have the form '# 123 filename'
694 .line and .file directives will appear in the pre-processed output. */
695 /* Note that input_file.c hand checks for '#' at the beginning of the
696 first line of the input file. This is because the compiler outputs
697 #NO_APP at the beginning of its output. */
698 /* Also note that C style comments are always supported. */
699 const char line_comment_chars
[] = "#";
701 /* This array holds machine specific line separator characters. */
702 const char line_separator_chars
[] = ";";
704 /* Chars that can be used to separate mant from exp in floating point nums. */
705 const char EXP_CHARS
[] = "eE";
707 /* Chars that mean this number is a floating point constant.
710 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
712 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
713 changed in read.c . Ideally it shouldn't have to know about it at all,
714 but nothing is ideal around here. */
716 /* Types of printf format used for instruction-related error messages.
717 "I" means int ("%d") and "S" means string ("%s"). */
718 enum mips_insn_error_format
725 /* Information about an error that was found while assembling the current
727 struct mips_insn_error
729 /* We sometimes need to match an instruction against more than one
730 opcode table entry. Errors found during this matching are reported
731 against a particular syntactic argument rather than against the
732 instruction as a whole. We grade these messages so that errors
733 against argument N have a greater priority than an error against
734 any argument < N, since the former implies that arguments up to N
735 were acceptable and that the opcode entry was therefore a closer match.
736 If several matches report an error against the same argument,
737 we only use that error if it is the same in all cases.
739 min_argnum is the minimum argument number for which an error message
740 should be accepted. It is 0 if MSG is against the instruction as
744 /* The printf()-style message, including its format and arguments. */
745 enum mips_insn_error_format format
;
754 /* The error that should be reported for the current instruction. */
755 static struct mips_insn_error insn_error
;
757 static int auto_align
= 1;
759 /* When outputting SVR4 PIC code, the assembler needs to know the
760 offset in the stack frame from which to restore the $gp register.
761 This is set by the .cprestore pseudo-op, and saved in this
763 static offsetT mips_cprestore_offset
= -1;
765 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
766 more optimizations, it can use a register value instead of a memory-saved
767 offset and even an other register than $gp as global pointer. */
768 static offsetT mips_cpreturn_offset
= -1;
769 static int mips_cpreturn_register
= -1;
770 static int mips_gp_register
= GP
;
771 static int mips_gprel_offset
= 0;
773 /* Whether mips_cprestore_offset has been set in the current function
774 (or whether it has already been warned about, if not). */
775 static int mips_cprestore_valid
= 0;
777 /* This is the register which holds the stack frame, as set by the
778 .frame pseudo-op. This is needed to implement .cprestore. */
779 static int mips_frame_reg
= SP
;
781 /* Whether mips_frame_reg has been set in the current function
782 (or whether it has already been warned about, if not). */
783 static int mips_frame_reg_valid
= 0;
785 /* To output NOP instructions correctly, we need to keep information
786 about the previous two instructions. */
788 /* Whether we are optimizing. The default value of 2 means to remove
789 unneeded NOPs and swap branch instructions when possible. A value
790 of 1 means to not swap branches. A value of 0 means to always
792 static int mips_optimize
= 2;
794 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
795 equivalent to seeing no -g option at all. */
796 static int mips_debug
= 0;
798 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
799 #define MAX_VR4130_NOPS 4
801 /* The maximum number of NOPs needed to fill delay slots. */
802 #define MAX_DELAY_NOPS 2
804 /* The maximum number of NOPs needed for any purpose. */
807 /* The maximum range of context length of ll/sc. */
808 #define MAX_LLSC_RANGE 20
810 /* A list of previous instructions, with index 0 being the most recent.
811 We need to look back MAX_NOPS instructions when filling delay slots
812 or working around processor errata. We need to look back one
813 instruction further if we're thinking about using history[0] to
814 fill a branch delay slot. */
815 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
817 /* The maximum number of LABELS detect for the same address. */
818 #define MAX_LABELS_SAME 10
820 /* Arrays of operands for each instruction. */
821 #define MAX_OPERANDS 6
822 struct mips_operand_array
824 const struct mips_operand
*operand
[MAX_OPERANDS
];
826 static struct mips_operand_array
*mips_operands
;
827 static struct mips_operand_array
*mips16_operands
;
828 static struct mips_operand_array
*micromips_operands
;
830 /* Nop instructions used by emit_nop. */
831 static struct mips_cl_insn nop_insn
;
832 static struct mips_cl_insn mips16_nop_insn
;
833 static struct mips_cl_insn micromips_nop16_insn
;
834 static struct mips_cl_insn micromips_nop32_insn
;
836 /* Sync instructions used by insert sync. */
837 static struct mips_cl_insn sync_insn
;
839 /* The appropriate nop for the current mode. */
840 #define NOP_INSN (mips_opts.mips16 \
842 : (mips_opts.micromips \
843 ? (mips_opts.insn32 \
844 ? µmips_nop32_insn \
845 : µmips_nop16_insn) \
848 /* The size of NOP_INSN in bytes. */
849 #define NOP_INSN_SIZE ((mips_opts.mips16 \
850 || (mips_opts.micromips && !mips_opts.insn32)) \
853 /* If this is set, it points to a frag holding nop instructions which
854 were inserted before the start of a noreorder section. If those
855 nops turn out to be unnecessary, the size of the frag can be
857 static fragS
*prev_nop_frag
;
859 /* The number of nop instructions we created in prev_nop_frag. */
860 static int prev_nop_frag_holds
;
862 /* The number of nop instructions that we know we need in
864 static int prev_nop_frag_required
;
866 /* The number of instructions we've seen since prev_nop_frag. */
867 static int prev_nop_frag_since
;
869 /* Relocations against symbols are sometimes done in two parts, with a HI
870 relocation and a LO relocation. Each relocation has only 16 bits of
871 space to store an addend. This means that in order for the linker to
872 handle carries correctly, it must be able to locate both the HI and
873 the LO relocation. This means that the relocations must appear in
874 order in the relocation table.
876 In order to implement this, we keep track of each unmatched HI
877 relocation. We then sort them so that they immediately precede the
878 corresponding LO relocation. */
883 struct mips_hi_fixup
*next
;
886 /* The section this fixup is in. */
890 /* The list of unmatched HI relocs. */
892 static struct mips_hi_fixup
*mips_hi_fixup_list
;
894 /* Map mips16 register numbers to normal MIPS register numbers. */
896 static const unsigned int mips16_to_32_reg_map
[] =
898 16, 17, 2, 3, 4, 5, 6, 7
901 /* Map microMIPS register numbers to normal MIPS register numbers. */
903 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
905 /* The microMIPS registers with type h. */
906 static const unsigned int micromips_to_32_reg_h_map1
[] =
908 5, 5, 6, 4, 4, 4, 4, 4
910 static const unsigned int micromips_to_32_reg_h_map2
[] =
912 6, 7, 7, 21, 22, 5, 6, 7
915 /* The microMIPS registers with type m. */
916 static const unsigned int micromips_to_32_reg_m_map
[] =
918 0, 17, 2, 3, 16, 18, 19, 20
921 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
923 /* Classifies the kind of instructions we're interested in when
924 implementing -mfix-vr4120. */
925 enum fix_vr4120_class
933 NUM_FIX_VR4120_CLASSES
936 /* ...likewise -mfix-loongson2f-jump. */
937 static bool mips_fix_loongson2f_jump
;
939 /* ...likewise -mfix-loongson2f-nop. */
940 static bool mips_fix_loongson2f_nop
;
942 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
943 static bool mips_fix_loongson2f
;
945 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
946 there must be at least one other instruction between an instruction
947 of type X and an instruction of type Y. */
948 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
950 /* True if -mfix-vr4120 is in force. */
951 static int mips_fix_vr4120
;
953 /* ...likewise -mfix-vr4130. */
954 static int mips_fix_vr4130
;
956 /* ...likewise -mfix-24k. */
957 static int mips_fix_24k
;
959 /* ...likewise -mfix-rm7000 */
960 static int mips_fix_rm7000
;
962 /* ...likewise -mfix-cn63xxp1 */
963 static bool mips_fix_cn63xxp1
;
965 /* ...likewise -mfix-r5900 */
966 static bool mips_fix_r5900
;
967 static bool mips_fix_r5900_explicit
;
969 /* ...likewise -mfix-loongson3-llsc. */
970 static bool mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
972 /* We don't relax branches by default, since this causes us to expand
973 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
974 fail to compute the offset before expanding the macro to the most
975 efficient expansion. */
977 static int mips_relax_branch
;
979 /* TRUE if checks are suppressed for invalid branches between ISA modes.
980 Needed for broken assembly produced by some GCC versions and some
981 sloppy code out there, where branches to data labels are present. */
982 static bool mips_ignore_branch_isa
;
984 /* The expansion of many macros depends on the type of symbol that
985 they refer to. For example, when generating position-dependent code,
986 a macro that refers to a symbol may have two different expansions,
987 one which uses GP-relative addresses and one which uses absolute
988 addresses. When generating SVR4-style PIC, a macro may have
989 different expansions for local and global symbols.
991 We handle these situations by generating both sequences and putting
992 them in variant frags. In position-dependent code, the first sequence
993 will be the GP-relative one and the second sequence will be the
994 absolute one. In SVR4 PIC, the first sequence will be for global
995 symbols and the second will be for local symbols.
997 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
998 SECOND are the lengths of the two sequences in bytes. These fields
999 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
1000 the subtype has the following flags:
1003 Set if generating PIC code.
1006 Set if it has been decided that we should use the second
1007 sequence instead of the first.
1010 Set in the first variant frag if the macro's second implementation
1011 is longer than its first. This refers to the macro as a whole,
1012 not an individual relaxation.
1015 Set in the first variant frag if the macro appeared in a .set nomacro
1016 block and if one alternative requires a warning but the other does not.
1019 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1022 RELAX_DELAY_SLOT_16BIT
1023 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1026 RELAX_DELAY_SLOT_SIZE_FIRST
1027 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1028 the macro is of the wrong size for the branch delay slot.
1030 RELAX_DELAY_SLOT_SIZE_SECOND
1031 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1032 the macro is of the wrong size for the branch delay slot.
1034 The frag's "opcode" points to the first fixup for relaxable code.
1036 Relaxable macros are generated using a sequence such as:
1038 relax_start (SYMBOL);
1039 ... generate first expansion ...
1041 ... generate second expansion ...
1044 The code and fixups for the unwanted alternative are discarded
1045 by md_convert_frag. */
1046 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1047 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1049 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1050 #define RELAX_SECOND(X) ((X) & 0xff)
1051 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1052 #define RELAX_USE_SECOND 0x20000
1053 #define RELAX_SECOND_LONGER 0x40000
1054 #define RELAX_NOMACRO 0x80000
1055 #define RELAX_DELAY_SLOT 0x100000
1056 #define RELAX_DELAY_SLOT_16BIT 0x200000
1057 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1058 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1060 /* Branch without likely bit. If label is out of range, we turn:
1062 beq reg1, reg2, label
1072 with the following opcode replacements:
1079 bltzal <-> bgezal (with jal label instead of j label)
1081 Even though keeping the delay slot instruction in the delay slot of
1082 the branch would be more efficient, it would be very tricky to do
1083 correctly, because we'd have to introduce a variable frag *after*
1084 the delay slot instruction, and expand that instead. Let's do it
1085 the easy way for now, even if the branch-not-taken case now costs
1086 one additional instruction. Out-of-range branches are not supposed
1087 to be common, anyway.
1089 Branch likely. If label is out of range, we turn:
1091 beql reg1, reg2, label
1092 delay slot (annulled if branch not taken)
1101 delay slot (executed only if branch taken)
1104 It would be possible to generate a shorter sequence by losing the
1105 likely bit, generating something like:
1110 delay slot (executed only if branch taken)
1122 bltzall -> bgezal (with jal label instead of j label)
1123 bgezall -> bltzal (ditto)
1126 but it's not clear that it would actually improve performance. */
1127 #define RELAX_BRANCH_ENCODE(at, pic, \
1128 uncond, likely, link, toofar) \
1129 ((relax_substateT) \
1132 | ((pic) ? 0x20 : 0) \
1133 | ((toofar) ? 0x40 : 0) \
1134 | ((link) ? 0x80 : 0) \
1135 | ((likely) ? 0x100 : 0) \
1136 | ((uncond) ? 0x200 : 0)))
1137 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1138 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1139 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1140 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1141 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1142 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1143 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1145 /* For mips16 code, we use an entirely different form of relaxation.
1146 mips16 supports two versions of most instructions which take
1147 immediate values: a small one which takes some small value, and a
1148 larger one which takes a 16 bit value. Since branches also follow
1149 this pattern, relaxing these values is required.
1151 We can assemble both mips16 and normal MIPS code in a single
1152 object. Therefore, we need to support this type of relaxation at
1153 the same time that we support the relaxation described above. We
1154 use the high bit of the subtype field to distinguish these cases.
1156 The information we store for this type of relaxation is the
1157 argument code found in the opcode file for this relocation, whether
1158 the user explicitly requested a small or extended form, and whether
1159 the relocation is in a jump or jal delay slot. That tells us the
1160 size of the value, and how it should be stored. We also store
1161 whether the fragment is considered to be extended or not. We also
1162 store whether this is known to be a branch to a different section,
1163 whether we have tried to relax this frag yet, and whether we have
1164 ever extended a PC relative fragment because of a shift count. */
1165 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1170 | ((e2) ? 0x100 : 0) \
1171 | ((pic) ? 0x200 : 0) \
1172 | ((sym32) ? 0x400 : 0) \
1173 | ((nomacro) ? 0x800 : 0) \
1174 | ((small) ? 0x1000 : 0) \
1175 | ((ext) ? 0x2000 : 0) \
1176 | ((dslot) ? 0x4000 : 0) \
1177 | ((jal_dslot) ? 0x8000 : 0))
1179 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1180 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1181 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1182 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1183 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1184 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1185 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1186 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1187 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1188 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1190 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1191 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1192 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1193 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1194 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1195 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1196 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1197 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1198 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1200 /* For microMIPS code, we use relaxation similar to one we use for
1201 MIPS16 code. Some instructions that take immediate values support
1202 two encodings: a small one which takes some small value, and a
1203 larger one which takes a 16 bit value. As some branches also follow
1204 this pattern, relaxing these values is required.
1206 We can assemble both microMIPS and normal MIPS code in a single
1207 object. Therefore, we need to support this type of relaxation at
1208 the same time that we support the relaxation described above. We
1209 use one of the high bits of the subtype field to distinguish these
1212 The information we store for this type of relaxation is the argument
1213 code found in the opcode file for this relocation, the register
1214 selected as the assembler temporary, whether in the 32-bit
1215 instruction mode, whether the branch is unconditional, whether it is
1216 compact, whether there is no delay-slot instruction available to fill
1217 in, whether it stores the link address implicitly in $ra, whether
1218 relaxation of out-of-range 32-bit branches to a sequence of
1219 instructions is enabled, and whether the displacement of a branch is
1220 too large to fit as an immediate argument of a 16-bit and a 32-bit
1221 branch, respectively. */
1222 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1223 uncond, compact, link, nods, \
1224 relax32, toofar16, toofar32) \
1227 | (((at) & 0x1f) << 8) \
1228 | ((insn32) ? 0x2000 : 0) \
1229 | ((pic) ? 0x4000 : 0) \
1230 | ((uncond) ? 0x8000 : 0) \
1231 | ((compact) ? 0x10000 : 0) \
1232 | ((link) ? 0x20000 : 0) \
1233 | ((nods) ? 0x40000 : 0) \
1234 | ((relax32) ? 0x80000 : 0) \
1235 | ((toofar16) ? 0x100000 : 0) \
1236 | ((toofar32) ? 0x200000 : 0))
1237 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1238 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1239 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1240 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1241 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1242 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1243 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1244 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1245 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1246 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1248 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1249 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1250 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1251 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1252 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1253 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1255 /* Sign-extend 16-bit value X. */
1256 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1258 /* Is the given value a sign-extended 32-bit value? */
1259 #define IS_SEXT_32BIT_NUM(x) \
1260 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1261 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1263 /* Is the given value a sign-extended 16-bit value? */
1264 #define IS_SEXT_16BIT_NUM(x) \
1265 (((x) &~ (offsetT) 0x7fff) == 0 \
1266 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1268 /* Is the given value a sign-extended 12-bit value? */
1269 #define IS_SEXT_12BIT_NUM(x) \
1270 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1272 /* Is the given value a sign-extended 9-bit value? */
1273 #define IS_SEXT_9BIT_NUM(x) \
1274 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1276 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1277 #define IS_ZEXT_32BIT_NUM(x) \
1278 (((x) &~ (offsetT) 0xffffffff) == 0 \
1279 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1281 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1283 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1284 (((STRUCT) >> (SHIFT)) & (MASK))
1286 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1287 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1289 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1290 : EXTRACT_BITS ((INSN).insn_opcode, \
1291 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1292 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1293 EXTRACT_BITS ((INSN).insn_opcode, \
1294 MIPS16OP_MASK_##FIELD, \
1295 MIPS16OP_SH_##FIELD)
1297 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1298 #define MIPS16_EXTEND (0xf000U << 16)
1300 /* Whether or not we are emitting a branch-likely macro. */
1301 static bool emit_branch_likely_macro
= false;
1303 /* Global variables used when generating relaxable macros. See the
1304 comment above RELAX_ENCODE for more details about how relaxation
1307 /* 0 if we're not emitting a relaxable macro.
1308 1 if we're emitting the first of the two relaxation alternatives.
1309 2 if we're emitting the second alternative. */
1312 /* The first relaxable fixup in the current frag. (In other words,
1313 the first fixup that refers to relaxable code.) */
1316 /* sizes[0] says how many bytes of the first alternative are stored in
1317 the current frag. Likewise sizes[1] for the second alternative. */
1318 unsigned int sizes
[2];
1320 /* The symbol on which the choice of sequence depends. */
1324 /* Global variables used to decide whether a macro needs a warning. */
1326 /* True if the macro is in a branch delay slot. */
1329 /* Set to the length in bytes required if the macro is in a delay slot
1330 that requires a specific length of instruction, otherwise zero. */
1331 unsigned int delay_slot_length
;
1333 /* For relaxable macros, sizes[0] is the length of the first alternative
1334 in bytes and sizes[1] is the length of the second alternative.
1335 For non-relaxable macros, both elements give the length of the
1337 unsigned int sizes
[2];
1339 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1340 instruction of the first alternative in bytes and first_insn_sizes[1]
1341 is the length of the first instruction of the second alternative.
1342 For non-relaxable macros, both elements give the length of the first
1343 instruction in bytes.
1345 Set to zero if we haven't yet seen the first instruction. */
1346 unsigned int first_insn_sizes
[2];
1348 /* For relaxable macros, insns[0] is the number of instructions for the
1349 first alternative and insns[1] is the number of instructions for the
1352 For non-relaxable macros, both elements give the number of
1353 instructions for the macro. */
1354 unsigned int insns
[2];
1356 /* The first variant frag for this macro. */
1358 } mips_macro_warning
;
1360 /* Prototypes for static functions. */
1362 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1364 static void append_insn
1365 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1367 static void mips_no_prev_insn (void);
1368 static void macro_build (expressionS
*, const char *, const char *, ...);
1369 static void mips16_macro_build
1370 (expressionS
*, const char *, const char *, va_list *);
1371 static void load_register (int, expressionS
*, int);
1372 static void macro_start (void);
1373 static void macro_end (void);
1374 static void macro (struct mips_cl_insn
*ip
, char *str
);
1375 static void mips16_macro (struct mips_cl_insn
* ip
);
1376 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1377 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1378 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1379 static void mips16_immed
1380 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1381 unsigned int, unsigned long *);
1382 static size_t my_getSmallExpression
1383 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1384 static void my_getExpression (expressionS
*, char *);
1385 static void s_align (int);
1386 static void s_change_sec (int);
1387 static void s_change_section (int);
1388 static void s_cons (int);
1389 static void s_float_cons (int);
1390 static void s_mips_globl (int);
1391 static void s_option (int);
1392 static void s_mipsset (int);
1393 static void s_abicalls (int);
1394 static void s_cpload (int);
1395 static void s_cpsetup (int);
1396 static void s_cplocal (int);
1397 static void s_cprestore (int);
1398 static void s_cpreturn (int);
1399 static void s_dtprelword (int);
1400 static void s_dtpreldword (int);
1401 static void s_tprelword (int);
1402 static void s_tpreldword (int);
1403 static void s_gpvalue (int);
1404 static void s_gpword (int);
1405 static void s_gpdword (int);
1406 static void s_ehword (int);
1407 static void s_cpadd (int);
1408 static void s_insn (int);
1409 static void s_nan (int);
1410 static void s_module (int);
1411 static void s_mips_ent (int);
1412 static void s_mips_end (int);
1413 static void s_mips_frame (int);
1414 static void s_mips_mask (int reg_type
);
1415 static void s_mips_stab (int);
1416 static void s_mips_weakext (int);
1417 static void s_mips_file (int);
1418 static void s_mips_loc (int);
1419 static bool pic_need_relax (symbolS
*);
1420 static int relaxed_branch_length (fragS
*, asection
*, int);
1421 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1422 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1423 static void file_mips_check_options (void);
1425 /* Table and functions used to map between CPU/ISA names, and
1426 ISA levels, and CPU numbers. */
1428 struct mips_cpu_info
1430 const char *name
; /* CPU or ISA name. */
1431 int flags
; /* MIPS_CPU_* flags. */
1432 int ase
; /* Set of ASEs implemented by the CPU. */
1433 int isa
; /* ISA level. */
1434 int cpu
; /* CPU number (default CPU if ISA). */
1437 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1439 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1440 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1441 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1443 /* Command-line options. */
1444 const char *md_shortopts
= "O::g::G:";
1448 OPTION_MARCH
= OPTION_MD_BASE
,
1480 OPTION_NO_SMARTMIPS
,
1490 OPTION_NO_MICROMIPS
,
1505 OPTION_M7000_HILO_FIX
,
1506 OPTION_MNO_7000_HILO_FIX
,
1510 OPTION_NO_FIX_RM7000
,
1511 OPTION_FIX_LOONGSON3_LLSC
,
1512 OPTION_NO_FIX_LOONGSON3_LLSC
,
1513 OPTION_FIX_LOONGSON2F_JUMP
,
1514 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1515 OPTION_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_LOONGSON2F_NOP
,
1518 OPTION_NO_FIX_VR4120
,
1520 OPTION_NO_FIX_VR4130
,
1521 OPTION_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_CN63XXP1
,
1524 OPTION_NO_FIX_R5900
,
1531 OPTION_CONSTRUCT_FLOATS
,
1532 OPTION_NO_CONSTRUCT_FLOATS
,
1536 OPTION_RELAX_BRANCH
,
1537 OPTION_NO_RELAX_BRANCH
,
1538 OPTION_IGNORE_BRANCH_ISA
,
1539 OPTION_NO_IGNORE_BRANCH_ISA
,
1548 OPTION_SINGLE_FLOAT
,
1549 OPTION_DOUBLE_FLOAT
,
1562 OPTION_MVXWORKS_PIC
,
1565 OPTION_NO_ODD_SPREG
,
1568 OPTION_LOONGSON_MMI
,
1569 OPTION_NO_LOONGSON_MMI
,
1570 OPTION_LOONGSON_CAM
,
1571 OPTION_NO_LOONGSON_CAM
,
1572 OPTION_LOONGSON_EXT
,
1573 OPTION_NO_LOONGSON_EXT
,
1574 OPTION_LOONGSON_EXT2
,
1575 OPTION_NO_LOONGSON_EXT2
,
1579 struct option md_longopts
[] =
1581 /* Options which specify architecture. */
1582 {"march", required_argument
, NULL
, OPTION_MARCH
},
1583 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1584 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1585 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1586 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1587 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1588 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1589 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1590 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1591 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1592 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1593 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1594 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1595 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1596 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1597 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1598 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1599 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1601 /* Options which specify Application Specific Extensions (ASEs). */
1602 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1603 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1604 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1605 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1606 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1607 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1608 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1609 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1610 {"mmt", no_argument
, NULL
, OPTION_MT
},
1611 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1612 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1613 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1614 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1615 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1616 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1617 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1618 {"meva", no_argument
, NULL
, OPTION_EVA
},
1619 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1620 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1621 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1622 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1623 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1624 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1625 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1626 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1627 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1628 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1629 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1630 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1631 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1632 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1633 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1634 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1635 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1636 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1637 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1638 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1639 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1640 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1641 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1642 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1643 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1645 /* Old-style architecture options. Don't add more of these. */
1646 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1647 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1648 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1649 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1650 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1651 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1652 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1653 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1655 /* Options which enable bug fixes. */
1656 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1657 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1658 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1659 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1660 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1661 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1662 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1663 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1664 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1665 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1666 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1667 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1668 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1669 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1670 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1671 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1672 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1673 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1674 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1675 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1676 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1678 /* Miscellaneous options. */
1679 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1680 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1681 {"break", no_argument
, NULL
, OPTION_BREAK
},
1682 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1683 {"EB", no_argument
, NULL
, OPTION_EB
},
1684 {"EL", no_argument
, NULL
, OPTION_EL
},
1685 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1686 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1687 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1688 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1689 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1690 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1691 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1692 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1693 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1694 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1695 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1696 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1697 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1698 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1699 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1700 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1701 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1702 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1703 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1704 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1705 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1706 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1707 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1709 /* Strictly speaking this next option is ELF specific,
1710 but we allow it for other ports as well in order to
1711 make testing easier. */
1712 {"32", no_argument
, NULL
, OPTION_32
},
1714 /* ELF-specific options. */
1715 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1716 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1717 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1718 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1719 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1720 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1721 {"n32", no_argument
, NULL
, OPTION_N32
},
1722 {"64", no_argument
, NULL
, OPTION_64
},
1723 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1724 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1725 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1726 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1727 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1728 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1730 {NULL
, no_argument
, NULL
, 0}
1732 size_t md_longopts_size
= sizeof (md_longopts
);
1734 /* Information about either an Application Specific Extension or an
1735 optional architecture feature that, for simplicity, we treat in the
1736 same way as an ASE. */
1739 /* The name of the ASE, used in both the command-line and .set options. */
1742 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1743 and 64-bit architectures, the flags here refer to the subset that
1744 is available on both. */
1747 /* The ASE_* flag used for instructions that are available on 64-bit
1748 architectures but that are not included in FLAGS. */
1749 unsigned int flags64
;
1751 /* The command-line options that turn the ASE on and off. */
1755 /* The minimum required architecture revisions for MIPS32, MIPS64,
1756 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1759 int micromips32_rev
;
1760 int micromips64_rev
;
1762 /* The architecture where the ASE was removed or -1 if the extension has not
1767 /* A table of all supported ASEs. */
1768 static const struct mips_ase mips_ases
[] = {
1769 { "dsp", ASE_DSP
, ASE_DSP64
,
1770 OPTION_DSP
, OPTION_NO_DSP
,
1774 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1775 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1779 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1780 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1784 { "eva", ASE_EVA
, 0,
1785 OPTION_EVA
, OPTION_NO_EVA
,
1789 { "mcu", ASE_MCU
, 0,
1790 OPTION_MCU
, OPTION_NO_MCU
,
1794 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1795 { "mdmx", ASE_MDMX
, 0,
1796 OPTION_MDMX
, OPTION_NO_MDMX
,
1800 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1801 { "mips3d", ASE_MIPS3D
, 0,
1802 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1807 OPTION_MT
, OPTION_NO_MT
,
1811 { "smartmips", ASE_SMARTMIPS
, 0,
1812 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1816 { "virt", ASE_VIRT
, ASE_VIRT64
,
1817 OPTION_VIRT
, OPTION_NO_VIRT
,
1821 { "msa", ASE_MSA
, ASE_MSA64
,
1822 OPTION_MSA
, OPTION_NO_MSA
,
1826 { "xpa", ASE_XPA
, 0,
1827 OPTION_XPA
, OPTION_NO_XPA
,
1831 { "mips16e2", ASE_MIPS16E2
, 0,
1832 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1836 { "crc", ASE_CRC
, ASE_CRC64
,
1837 OPTION_CRC
, OPTION_NO_CRC
,
1841 { "ginv", ASE_GINV
, 0,
1842 OPTION_GINV
, OPTION_NO_GINV
,
1846 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1847 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1851 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1852 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1856 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1857 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1861 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1862 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1867 /* The set of ASEs that require -mfp64. */
1868 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1870 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1871 static const unsigned int mips_ase_groups
[] = {
1872 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1873 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1878 The following pseudo-ops from the Kane and Heinrich MIPS book
1879 should be defined here, but are currently unsupported: .alias,
1880 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1882 The following pseudo-ops from the Kane and Heinrich MIPS book are
1883 specific to the type of debugging information being generated, and
1884 should be defined by the object format: .aent, .begin, .bend,
1885 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1888 The following pseudo-ops from the Kane and Heinrich MIPS book are
1889 not MIPS CPU specific, but are also not specific to the object file
1890 format. This file is probably the best place to define them, but
1891 they are not currently supported: .asm0, .endr, .lab, .struct. */
1893 static const pseudo_typeS mips_pseudo_table
[] =
1895 /* MIPS specific pseudo-ops. */
1896 {"option", s_option
, 0},
1897 {"set", s_mipsset
, 0},
1898 {"rdata", s_change_sec
, 'r'},
1899 {"sdata", s_change_sec
, 's'},
1900 {"livereg", s_ignore
, 0},
1901 {"abicalls", s_abicalls
, 0},
1902 {"cpload", s_cpload
, 0},
1903 {"cpsetup", s_cpsetup
, 0},
1904 {"cplocal", s_cplocal
, 0},
1905 {"cprestore", s_cprestore
, 0},
1906 {"cpreturn", s_cpreturn
, 0},
1907 {"dtprelword", s_dtprelword
, 0},
1908 {"dtpreldword", s_dtpreldword
, 0},
1909 {"tprelword", s_tprelword
, 0},
1910 {"tpreldword", s_tpreldword
, 0},
1911 {"gpvalue", s_gpvalue
, 0},
1912 {"gpword", s_gpword
, 0},
1913 {"gpdword", s_gpdword
, 0},
1914 {"ehword", s_ehword
, 0},
1915 {"cpadd", s_cpadd
, 0},
1916 {"insn", s_insn
, 0},
1918 {"module", s_module
, 0},
1920 /* Relatively generic pseudo-ops that happen to be used on MIPS
1922 {"asciiz", stringer
, 8 + 1},
1923 {"bss", s_change_sec
, 'b'},
1925 {"half", s_cons
, 1},
1926 {"dword", s_cons
, 3},
1927 {"weakext", s_mips_weakext
, 0},
1928 {"origin", s_org
, 0},
1929 {"repeat", s_rept
, 0},
1931 /* For MIPS this is non-standard, but we define it for consistency. */
1932 {"sbss", s_change_sec
, 'B'},
1934 /* These pseudo-ops are defined in read.c, but must be overridden
1935 here for one reason or another. */
1936 {"align", s_align
, 0},
1937 {"byte", s_cons
, 0},
1938 {"data", s_change_sec
, 'd'},
1939 {"double", s_float_cons
, 'd'},
1940 {"float", s_float_cons
, 'f'},
1941 {"globl", s_mips_globl
, 0},
1942 {"global", s_mips_globl
, 0},
1943 {"hword", s_cons
, 1},
1945 {"long", s_cons
, 2},
1946 {"octa", s_cons
, 4},
1947 {"quad", s_cons
, 3},
1948 {"section", s_change_section
, 0},
1949 {"short", s_cons
, 1},
1950 {"single", s_float_cons
, 'f'},
1951 {"stabd", s_mips_stab
, 'd'},
1952 {"stabn", s_mips_stab
, 'n'},
1953 {"stabs", s_mips_stab
, 's'},
1954 {"text", s_change_sec
, 't'},
1955 {"word", s_cons
, 2},
1957 { "extern", ecoff_directive_extern
, 0},
1962 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1964 /* These pseudo-ops should be defined by the object file format.
1965 However, a.out doesn't support them, so we have versions here. */
1966 {"aent", s_mips_ent
, 1},
1967 {"bgnb", s_ignore
, 0},
1968 {"end", s_mips_end
, 0},
1969 {"endb", s_ignore
, 0},
1970 {"ent", s_mips_ent
, 0},
1971 {"file", s_mips_file
, 0},
1972 {"fmask", s_mips_mask
, 'F'},
1973 {"frame", s_mips_frame
, 0},
1974 {"loc", s_mips_loc
, 0},
1975 {"mask", s_mips_mask
, 'R'},
1976 {"verstamp", s_ignore
, 0},
1980 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1981 purpose of the `.dc.a' internal pseudo-op. */
1984 mips_address_bytes (void)
1986 file_mips_check_options ();
1987 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1990 extern void pop_insert (const pseudo_typeS
*);
1993 mips_pop_insert (void)
1995 pop_insert (mips_pseudo_table
);
1996 if (! ECOFF_DEBUGGING
)
1997 pop_insert (mips_nonecoff_pseudo_table
);
2000 /* Symbols labelling the current insn. */
2002 struct insn_label_list
2004 struct insn_label_list
*next
;
2008 static struct insn_label_list
*free_insn_labels
;
2009 #define label_list tc_segment_info_data.labels
2011 static void mips_clear_insn_labels (void);
2012 static void mips_mark_labels (void);
2013 static void mips_compressed_mark_labels (void);
2016 mips_clear_insn_labels (void)
2018 struct insn_label_list
**pl
;
2019 segment_info_type
*si
;
2023 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2026 si
= seg_info (now_seg
);
2027 *pl
= si
->label_list
;
2028 si
->label_list
= NULL
;
2032 /* Mark instruction labels in MIPS16/microMIPS mode. */
2035 mips_mark_labels (void)
2037 if (HAVE_CODE_COMPRESSION
)
2038 mips_compressed_mark_labels ();
2041 static char *expr_end
;
2043 /* An expression in a macro instruction. This is set by mips_ip and
2044 mips16_ip and when populated is always an O_constant. */
2046 static expressionS imm_expr
;
2048 /* The relocatable field in an instruction and the relocs associated
2049 with it. These variables are used for instructions like LUI and
2050 JAL as well as true offsets. They are also used for address
2051 operands in macros. */
2053 static expressionS offset_expr
;
2054 static bfd_reloc_code_real_type offset_reloc
[3]
2055 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2057 /* This is set to the resulting size of the instruction to be produced
2058 by mips16_ip if an explicit extension is used or by mips_ip if an
2059 explicit size is supplied. */
2061 static unsigned int forced_insn_length
;
2063 /* True if we are assembling an instruction. All dot symbols defined during
2064 this time should be treated as code labels. */
2066 static bool mips_assembling_insn
;
2068 /* The pdr segment for per procedure frame/regmask info. Not used for
2071 static segT pdr_seg
;
2073 /* The default target format to use. */
2075 #if defined (TE_FreeBSD)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2077 #elif defined (TE_TMIPS)
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2080 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2084 mips_target_format (void)
2086 switch (OUTPUT_FLAVOR
)
2088 case bfd_target_elf_flavour
:
2090 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2091 return (target_big_endian
2092 ? "elf32-bigmips-vxworks"
2093 : "elf32-littlemips-vxworks");
2095 return (target_big_endian
2096 ? (HAVE_64BIT_OBJECTS
2097 ? ELF_TARGET ("elf64-", "big")
2099 ? ELF_TARGET ("elf32-n", "big")
2100 : ELF_TARGET ("elf32-", "big")))
2101 : (HAVE_64BIT_OBJECTS
2102 ? ELF_TARGET ("elf64-", "little")
2104 ? ELF_TARGET ("elf32-n", "little")
2105 : ELF_TARGET ("elf32-", "little"))));
2112 /* Return the ISA revision that is currently in use, or 0 if we are
2113 generating code for MIPS V or below. */
2118 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2121 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2124 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2127 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2130 /* microMIPS implies revision 2 or above. */
2131 if (mips_opts
.micromips
)
2134 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2140 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2143 mips_ase_mask (unsigned int flags
)
2147 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2148 if (flags
& mips_ase_groups
[i
])
2149 flags
|= mips_ase_groups
[i
];
2153 /* Check whether the current ISA supports ASE. Issue a warning if
2157 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2161 static unsigned int warned_isa
;
2162 static unsigned int warned_fp32
;
2164 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2165 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2167 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2168 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2169 && (warned_isa
& ase
->flags
) != ase
->flags
)
2171 warned_isa
|= ase
->flags
;
2172 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2173 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2175 as_warn (_("the %d-bit %s architecture does not support the"
2176 " `%s' extension"), size
, base
, ase
->name
);
2178 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2179 ase
->name
, base
, size
, min_rev
);
2181 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2182 && (warned_isa
& ase
->flags
) != ase
->flags
)
2184 warned_isa
|= ase
->flags
;
2185 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2186 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2187 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2188 ase
->name
, base
, size
, ase
->rem_rev
);
2191 if ((ase
->flags
& FP64_ASES
)
2192 && mips_opts
.fp
!= 64
2193 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2195 warned_fp32
|= ase
->flags
;
2196 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2200 /* Check all enabled ASEs to see whether they are supported by the
2201 chosen architecture. */
2204 mips_check_isa_supports_ases (void)
2206 unsigned int i
, mask
;
2208 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2210 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2211 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2212 mips_check_isa_supports_ase (&mips_ases
[i
]);
2216 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2217 that were affected. */
2220 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2225 mask
= mips_ase_mask (ase
->flags
);
2228 /* Clear combination ASE flags, which need to be recalculated based on
2229 updated regular ASE settings. */
2230 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
| ASE_EVA_R6
);
2233 opts
->ase
|= ase
->flags
;
2235 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2236 instructions which are only valid when both ASEs are enabled.
2237 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2238 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2240 opts
->ase
|= ASE_XPA_VIRT
;
2241 mask
|= ASE_XPA_VIRT
;
2243 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2245 opts
->ase
|= ASE_MIPS16E2_MT
;
2246 mask
|= ASE_MIPS16E2_MT
;
2249 /* The EVA Extension has instructions which are only valid when the R6 ISA
2250 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2252 if (((opts
->ase
& ASE_EVA
) != 0) && ISA_IS_R6 (opts
->isa
))
2254 opts
->ase
|= ASE_EVA_R6
;
2261 /* Return the ASE called NAME, or null if none. */
2263 static const struct mips_ase
*
2264 mips_lookup_ase (const char *name
)
2268 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2269 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2270 return &mips_ases
[i
];
2274 /* Return the length of a microMIPS instruction in bytes. If bits of
2275 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2276 otherwise it is a 32-bit instruction. */
2278 static inline unsigned int
2279 micromips_insn_length (const struct mips_opcode
*mo
)
2281 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2284 /* Return the length of MIPS16 instruction OPCODE. */
2286 static inline unsigned int
2287 mips16_opcode_length (unsigned long opcode
)
2289 return (opcode
>> 16) == 0 ? 2 : 4;
2292 /* Return the length of instruction INSN. */
2294 static inline unsigned int
2295 insn_length (const struct mips_cl_insn
*insn
)
2297 if (mips_opts
.micromips
)
2298 return micromips_insn_length (insn
->insn_mo
);
2299 else if (mips_opts
.mips16
)
2300 return mips16_opcode_length (insn
->insn_opcode
);
2305 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2308 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2313 insn
->insn_opcode
= mo
->match
;
2316 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2317 insn
->fixp
[i
] = NULL
;
2318 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2319 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2320 insn
->mips16_absolute_jump_p
= 0;
2321 insn
->complete_p
= 0;
2322 insn
->cleared_p
= 0;
2325 /* Get a list of all the operands in INSN. */
2327 static const struct mips_operand_array
*
2328 insn_operands (const struct mips_cl_insn
*insn
)
2330 if (insn
->insn_mo
>= &mips_opcodes
[0]
2331 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2332 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2334 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2335 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2336 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2338 if (insn
->insn_mo
>= µmips_opcodes
[0]
2339 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2340 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2345 /* Get a description of operand OPNO of INSN. */
2347 static const struct mips_operand
*
2348 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2350 const struct mips_operand_array
*operands
;
2352 operands
= insn_operands (insn
);
2353 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2355 return operands
->operand
[opno
];
2358 /* Install UVAL as the value of OPERAND in INSN. */
2361 insn_insert_operand (struct mips_cl_insn
*insn
,
2362 const struct mips_operand
*operand
, unsigned int uval
)
2364 if (mips_opts
.mips16
2365 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2366 && mips_opcode_32bit_p (insn
->insn_mo
))
2367 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2369 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2372 /* Extract the value of OPERAND from INSN. */
2374 static inline unsigned
2375 insn_extract_operand (const struct mips_cl_insn
*insn
,
2376 const struct mips_operand
*operand
)
2378 return mips_extract_operand (operand
, insn
->insn_opcode
);
2381 /* Record the current MIPS16/microMIPS mode in now_seg. */
2384 mips_record_compressed_mode (void)
2386 segment_info_type
*si
;
2388 si
= seg_info (now_seg
);
2389 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2390 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2391 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2392 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2395 /* Read a standard MIPS instruction from BUF. */
2397 static unsigned long
2398 read_insn (char *buf
)
2400 if (target_big_endian
)
2401 return bfd_getb32 ((bfd_byte
*) buf
);
2403 return bfd_getl32 ((bfd_byte
*) buf
);
2406 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2410 write_insn (char *buf
, unsigned int insn
)
2412 md_number_to_chars (buf
, insn
, 4);
2416 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2417 has length LENGTH. */
2419 static unsigned long
2420 read_compressed_insn (char *buf
, unsigned int length
)
2426 for (i
= 0; i
< length
; i
+= 2)
2429 if (target_big_endian
)
2430 insn
|= bfd_getb16 ((char *) buf
);
2432 insn
|= bfd_getl16 ((char *) buf
);
2438 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2439 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2442 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2446 for (i
= 0; i
< length
; i
+= 2)
2447 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2448 return buf
+ length
;
2451 /* Install INSN at the location specified by its "frag" and "where" fields. */
2454 install_insn (const struct mips_cl_insn
*insn
)
2456 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2457 if (HAVE_CODE_COMPRESSION
)
2458 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2460 write_insn (f
, insn
->insn_opcode
);
2461 mips_record_compressed_mode ();
2464 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2465 and install the opcode in the new location. */
2468 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2473 insn
->where
= where
;
2474 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2475 if (insn
->fixp
[i
] != NULL
)
2477 insn
->fixp
[i
]->fx_frag
= frag
;
2478 insn
->fixp
[i
]->fx_where
= where
;
2480 install_insn (insn
);
2483 /* Add INSN to the end of the output. */
2486 add_fixed_insn (struct mips_cl_insn
*insn
)
2488 char *f
= frag_more (insn_length (insn
));
2489 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2492 /* Start a variant frag and move INSN to the start of the variant part,
2493 marking it as fixed. The other arguments are as for frag_var. */
2496 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2497 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2499 frag_grow (max_chars
);
2500 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2502 frag_var (rs_machine_dependent
, max_chars
, var
,
2503 subtype
, symbol
, offset
, NULL
);
2506 /* Insert N copies of INSN into the history buffer, starting at
2507 position FIRST. Neither FIRST nor N need to be clipped. */
2510 insert_into_history (unsigned int first
, unsigned int n
,
2511 const struct mips_cl_insn
*insn
)
2513 if (mips_relax
.sequence
!= 2)
2517 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2519 history
[i
] = history
[i
- n
];
2525 /* Clear the error in insn_error. */
2528 clear_insn_error (void)
2530 memset (&insn_error
, 0, sizeof (insn_error
));
2533 /* Possibly record error message MSG for the current instruction.
2534 If the error is about a particular argument, ARGNUM is the 1-based
2535 number of that argument, otherwise it is 0. FORMAT is the format
2536 of MSG. Return true if MSG was used, false if the current message
2540 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2545 /* Give priority to errors against specific arguments, and to
2546 the first whole-instruction message. */
2552 /* Keep insn_error if it is against a later argument. */
2553 if (argnum
< insn_error
.min_argnum
)
2556 /* If both errors are against the same argument but are different,
2557 give up on reporting a specific error for this argument.
2558 See the comment about mips_insn_error for details. */
2559 if (argnum
== insn_error
.min_argnum
2561 && strcmp (insn_error
.msg
, msg
) != 0)
2564 insn_error
.min_argnum
+= 1;
2568 insn_error
.min_argnum
= argnum
;
2569 insn_error
.format
= format
;
2570 insn_error
.msg
= msg
;
2574 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2575 as for set_insn_error_format. */
2578 set_insn_error (int argnum
, const char *msg
)
2580 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2583 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2584 as for set_insn_error_format. */
2587 set_insn_error_i (int argnum
, const char *msg
, int i
)
2589 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2593 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2594 are as for set_insn_error_format. */
2597 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2599 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2601 insn_error
.u
.ss
[0] = s1
;
2602 insn_error
.u
.ss
[1] = s2
;
2606 /* Report the error in insn_error, which is against assembly code STR. */
2609 report_insn_error (const char *str
)
2611 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2613 switch (insn_error
.format
)
2620 as_bad (msg
, insn_error
.u
.i
, str
);
2624 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2628 free ((char *) msg
);
2631 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2632 the idea is to make it obvious at a glance that each errata is
2636 init_vr4120_conflicts (void)
2638 #define CONFLICT(FIRST, SECOND) \
2639 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2641 /* Errata 21 - [D]DIV[U] after [D]MACC */
2642 CONFLICT (MACC
, DIV
);
2643 CONFLICT (DMACC
, DIV
);
2645 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2646 CONFLICT (DMULT
, DMULT
);
2647 CONFLICT (DMULT
, DMACC
);
2648 CONFLICT (DMACC
, DMULT
);
2649 CONFLICT (DMACC
, DMACC
);
2651 /* Errata 24 - MT{LO,HI} after [D]MACC */
2652 CONFLICT (MACC
, MTHILO
);
2653 CONFLICT (DMACC
, MTHILO
);
2655 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2656 instruction is executed immediately after a MACC or DMACC
2657 instruction, the result of [either instruction] is incorrect." */
2658 CONFLICT (MACC
, MULT
);
2659 CONFLICT (MACC
, DMULT
);
2660 CONFLICT (DMACC
, MULT
);
2661 CONFLICT (DMACC
, DMULT
);
2663 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2664 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2665 DDIV or DDIVU instruction, the result of the MACC or
2666 DMACC instruction is incorrect.". */
2667 CONFLICT (DMULT
, MACC
);
2668 CONFLICT (DMULT
, DMACC
);
2669 CONFLICT (DIV
, MACC
);
2670 CONFLICT (DIV
, DMACC
);
2680 #define RNUM_MASK 0x00000ff
2681 #define RTYPE_MASK 0x0ffff00
2682 #define RTYPE_NUM 0x0000100
2683 #define RTYPE_FPU 0x0000200
2684 #define RTYPE_FCC 0x0000400
2685 #define RTYPE_VEC 0x0000800
2686 #define RTYPE_GP 0x0001000
2687 #define RTYPE_CP0 0x0002000
2688 #define RTYPE_PC 0x0004000
2689 #define RTYPE_ACC 0x0008000
2690 #define RTYPE_CCC 0x0010000
2691 #define RTYPE_VI 0x0020000
2692 #define RTYPE_VF 0x0040000
2693 #define RTYPE_R5900_I 0x0080000
2694 #define RTYPE_R5900_Q 0x0100000
2695 #define RTYPE_R5900_R 0x0200000
2696 #define RTYPE_R5900_ACC 0x0400000
2697 #define RTYPE_MSA 0x0800000
2698 #define RWARN 0x8000000
2700 #define GENERIC_REGISTER_NUMBERS \
2701 {"$0", RTYPE_NUM | 0}, \
2702 {"$1", RTYPE_NUM | 1}, \
2703 {"$2", RTYPE_NUM | 2}, \
2704 {"$3", RTYPE_NUM | 3}, \
2705 {"$4", RTYPE_NUM | 4}, \
2706 {"$5", RTYPE_NUM | 5}, \
2707 {"$6", RTYPE_NUM | 6}, \
2708 {"$7", RTYPE_NUM | 7}, \
2709 {"$8", RTYPE_NUM | 8}, \
2710 {"$9", RTYPE_NUM | 9}, \
2711 {"$10", RTYPE_NUM | 10}, \
2712 {"$11", RTYPE_NUM | 11}, \
2713 {"$12", RTYPE_NUM | 12}, \
2714 {"$13", RTYPE_NUM | 13}, \
2715 {"$14", RTYPE_NUM | 14}, \
2716 {"$15", RTYPE_NUM | 15}, \
2717 {"$16", RTYPE_NUM | 16}, \
2718 {"$17", RTYPE_NUM | 17}, \
2719 {"$18", RTYPE_NUM | 18}, \
2720 {"$19", RTYPE_NUM | 19}, \
2721 {"$20", RTYPE_NUM | 20}, \
2722 {"$21", RTYPE_NUM | 21}, \
2723 {"$22", RTYPE_NUM | 22}, \
2724 {"$23", RTYPE_NUM | 23}, \
2725 {"$24", RTYPE_NUM | 24}, \
2726 {"$25", RTYPE_NUM | 25}, \
2727 {"$26", RTYPE_NUM | 26}, \
2728 {"$27", RTYPE_NUM | 27}, \
2729 {"$28", RTYPE_NUM | 28}, \
2730 {"$29", RTYPE_NUM | 29}, \
2731 {"$30", RTYPE_NUM | 30}, \
2732 {"$31", RTYPE_NUM | 31}
2734 #define FPU_REGISTER_NAMES \
2735 {"$f0", RTYPE_FPU | 0}, \
2736 {"$f1", RTYPE_FPU | 1}, \
2737 {"$f2", RTYPE_FPU | 2}, \
2738 {"$f3", RTYPE_FPU | 3}, \
2739 {"$f4", RTYPE_FPU | 4}, \
2740 {"$f5", RTYPE_FPU | 5}, \
2741 {"$f6", RTYPE_FPU | 6}, \
2742 {"$f7", RTYPE_FPU | 7}, \
2743 {"$f8", RTYPE_FPU | 8}, \
2744 {"$f9", RTYPE_FPU | 9}, \
2745 {"$f10", RTYPE_FPU | 10}, \
2746 {"$f11", RTYPE_FPU | 11}, \
2747 {"$f12", RTYPE_FPU | 12}, \
2748 {"$f13", RTYPE_FPU | 13}, \
2749 {"$f14", RTYPE_FPU | 14}, \
2750 {"$f15", RTYPE_FPU | 15}, \
2751 {"$f16", RTYPE_FPU | 16}, \
2752 {"$f17", RTYPE_FPU | 17}, \
2753 {"$f18", RTYPE_FPU | 18}, \
2754 {"$f19", RTYPE_FPU | 19}, \
2755 {"$f20", RTYPE_FPU | 20}, \
2756 {"$f21", RTYPE_FPU | 21}, \
2757 {"$f22", RTYPE_FPU | 22}, \
2758 {"$f23", RTYPE_FPU | 23}, \
2759 {"$f24", RTYPE_FPU | 24}, \
2760 {"$f25", RTYPE_FPU | 25}, \
2761 {"$f26", RTYPE_FPU | 26}, \
2762 {"$f27", RTYPE_FPU | 27}, \
2763 {"$f28", RTYPE_FPU | 28}, \
2764 {"$f29", RTYPE_FPU | 29}, \
2765 {"$f30", RTYPE_FPU | 30}, \
2766 {"$f31", RTYPE_FPU | 31}
2768 #define FPU_CONDITION_CODE_NAMES \
2769 {"$fcc0", RTYPE_FCC | 0}, \
2770 {"$fcc1", RTYPE_FCC | 1}, \
2771 {"$fcc2", RTYPE_FCC | 2}, \
2772 {"$fcc3", RTYPE_FCC | 3}, \
2773 {"$fcc4", RTYPE_FCC | 4}, \
2774 {"$fcc5", RTYPE_FCC | 5}, \
2775 {"$fcc6", RTYPE_FCC | 6}, \
2776 {"$fcc7", RTYPE_FCC | 7}
2778 #define COPROC_CONDITION_CODE_NAMES \
2779 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2780 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2781 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2782 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2783 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2784 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2785 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2786 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2788 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2789 {"$a4", RTYPE_GP | 8}, \
2790 {"$a5", RTYPE_GP | 9}, \
2791 {"$a6", RTYPE_GP | 10}, \
2792 {"$a7", RTYPE_GP | 11}, \
2793 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2794 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2795 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2796 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2797 {"$t0", RTYPE_GP | 12}, \
2798 {"$t1", RTYPE_GP | 13}, \
2799 {"$t2", RTYPE_GP | 14}, \
2800 {"$t3", RTYPE_GP | 15}
2802 #define O32_SYMBOLIC_REGISTER_NAMES \
2803 {"$t0", RTYPE_GP | 8}, \
2804 {"$t1", RTYPE_GP | 9}, \
2805 {"$t2", RTYPE_GP | 10}, \
2806 {"$t3", RTYPE_GP | 11}, \
2807 {"$t4", RTYPE_GP | 12}, \
2808 {"$t5", RTYPE_GP | 13}, \
2809 {"$t6", RTYPE_GP | 14}, \
2810 {"$t7", RTYPE_GP | 15}, \
2811 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2812 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2813 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2814 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2816 /* Remaining symbolic register names. */
2817 #define SYMBOLIC_REGISTER_NAMES \
2818 {"$zero", RTYPE_GP | 0}, \
2819 {"$at", RTYPE_GP | 1}, \
2820 {"$AT", RTYPE_GP | 1}, \
2821 {"$v0", RTYPE_GP | 2}, \
2822 {"$v1", RTYPE_GP | 3}, \
2823 {"$a0", RTYPE_GP | 4}, \
2824 {"$a1", RTYPE_GP | 5}, \
2825 {"$a2", RTYPE_GP | 6}, \
2826 {"$a3", RTYPE_GP | 7}, \
2827 {"$s0", RTYPE_GP | 16}, \
2828 {"$s1", RTYPE_GP | 17}, \
2829 {"$s2", RTYPE_GP | 18}, \
2830 {"$s3", RTYPE_GP | 19}, \
2831 {"$s4", RTYPE_GP | 20}, \
2832 {"$s5", RTYPE_GP | 21}, \
2833 {"$s6", RTYPE_GP | 22}, \
2834 {"$s7", RTYPE_GP | 23}, \
2835 {"$t8", RTYPE_GP | 24}, \
2836 {"$t9", RTYPE_GP | 25}, \
2837 {"$k0", RTYPE_GP | 26}, \
2838 {"$kt0", RTYPE_GP | 26}, \
2839 {"$k1", RTYPE_GP | 27}, \
2840 {"$kt1", RTYPE_GP | 27}, \
2841 {"$gp", RTYPE_GP | 28}, \
2842 {"$sp", RTYPE_GP | 29}, \
2843 {"$s8", RTYPE_GP | 30}, \
2844 {"$fp", RTYPE_GP | 30}, \
2845 {"$ra", RTYPE_GP | 31}
2847 #define MIPS16_SPECIAL_REGISTER_NAMES \
2848 {"$pc", RTYPE_PC | 0}
2850 #define MDMX_VECTOR_REGISTER_NAMES \
2851 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2852 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2853 {"$v2", RTYPE_VEC | 2}, \
2854 {"$v3", RTYPE_VEC | 3}, \
2855 {"$v4", RTYPE_VEC | 4}, \
2856 {"$v5", RTYPE_VEC | 5}, \
2857 {"$v6", RTYPE_VEC | 6}, \
2858 {"$v7", RTYPE_VEC | 7}, \
2859 {"$v8", RTYPE_VEC | 8}, \
2860 {"$v9", RTYPE_VEC | 9}, \
2861 {"$v10", RTYPE_VEC | 10}, \
2862 {"$v11", RTYPE_VEC | 11}, \
2863 {"$v12", RTYPE_VEC | 12}, \
2864 {"$v13", RTYPE_VEC | 13}, \
2865 {"$v14", RTYPE_VEC | 14}, \
2866 {"$v15", RTYPE_VEC | 15}, \
2867 {"$v16", RTYPE_VEC | 16}, \
2868 {"$v17", RTYPE_VEC | 17}, \
2869 {"$v18", RTYPE_VEC | 18}, \
2870 {"$v19", RTYPE_VEC | 19}, \
2871 {"$v20", RTYPE_VEC | 20}, \
2872 {"$v21", RTYPE_VEC | 21}, \
2873 {"$v22", RTYPE_VEC | 22}, \
2874 {"$v23", RTYPE_VEC | 23}, \
2875 {"$v24", RTYPE_VEC | 24}, \
2876 {"$v25", RTYPE_VEC | 25}, \
2877 {"$v26", RTYPE_VEC | 26}, \
2878 {"$v27", RTYPE_VEC | 27}, \
2879 {"$v28", RTYPE_VEC | 28}, \
2880 {"$v29", RTYPE_VEC | 29}, \
2881 {"$v30", RTYPE_VEC | 30}, \
2882 {"$v31", RTYPE_VEC | 31}
2884 #define R5900_I_NAMES \
2885 {"$I", RTYPE_R5900_I | 0}
2887 #define R5900_Q_NAMES \
2888 {"$Q", RTYPE_R5900_Q | 0}
2890 #define R5900_R_NAMES \
2891 {"$R", RTYPE_R5900_R | 0}
2893 #define R5900_ACC_NAMES \
2894 {"$ACC", RTYPE_R5900_ACC | 0 }
2896 #define MIPS_DSP_ACCUMULATOR_NAMES \
2897 {"$ac0", RTYPE_ACC | 0}, \
2898 {"$ac1", RTYPE_ACC | 1}, \
2899 {"$ac2", RTYPE_ACC | 2}, \
2900 {"$ac3", RTYPE_ACC | 3}
2902 static const struct regname reg_names
[] = {
2903 GENERIC_REGISTER_NUMBERS
,
2905 FPU_CONDITION_CODE_NAMES
,
2906 COPROC_CONDITION_CODE_NAMES
,
2908 /* The $txx registers depends on the abi,
2909 these will be added later into the symbol table from
2910 one of the tables below once mips_abi is set after
2911 parsing of arguments from the command line. */
2912 SYMBOLIC_REGISTER_NAMES
,
2914 MIPS16_SPECIAL_REGISTER_NAMES
,
2915 MDMX_VECTOR_REGISTER_NAMES
,
2920 MIPS_DSP_ACCUMULATOR_NAMES
,
2924 static const struct regname reg_names_o32
[] = {
2925 O32_SYMBOLIC_REGISTER_NAMES
,
2929 static const struct regname reg_names_n32n64
[] = {
2930 N32N64_SYMBOLIC_REGISTER_NAMES
,
2934 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2935 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2936 of these register symbols, return the associated vector register,
2937 otherwise return SYMVAL itself. */
2940 mips_prefer_vec_regno (unsigned int symval
)
2942 if ((symval
& -2) == (RTYPE_GP
| 2))
2943 return RTYPE_VEC
| (symval
& 1);
2947 /* Return true if string [S, E) is a valid register name, storing its
2948 symbol value in *SYMVAL_PTR if so. */
2951 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2956 /* Terminate name. */
2960 /* Look up the name. */
2961 symbol
= symbol_find (s
);
2964 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2967 *symval_ptr
= S_GET_VALUE (symbol
);
2971 /* Return true if the string at *SPTR is a valid register name. Allow it
2972 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2975 When returning true, move *SPTR past the register, store the
2976 register's symbol value in *SYMVAL_PTR and the channel mask in
2977 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2978 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2979 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2982 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2983 unsigned int *channels_ptr
)
2987 unsigned int channels
, symval
, bit
;
2989 /* Find end of name. */
2991 if (is_name_beginner (*e
))
2993 while (is_part_of_name (*e
))
2997 if (!mips_parse_register_1 (s
, e
, &symval
))
3002 /* Eat characters from the end of the string that are valid
3003 channel suffixes. The preceding register must be $ACC or
3004 end with a digit, so there is no ambiguity. */
3007 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
3008 if (m
> s
&& m
[-1] == *q
)
3015 || !mips_parse_register_1 (s
, m
, &symval
)
3016 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3021 *symval_ptr
= symval
;
3023 *channels_ptr
= channels
;
3027 /* Check if SPTR points at a valid register specifier according to TYPES.
3028 If so, then return 1, advance S to consume the specifier and store
3029 the register's number in REGNOP, otherwise return 0. */
3032 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3036 if (mips_parse_register (s
, ®no
, NULL
))
3038 if (types
& RTYPE_VEC
)
3039 regno
= mips_prefer_vec_regno (regno
);
3048 as_warn (_("unrecognized register name `%s'"), *s
);
3053 return regno
<= RNUM_MASK
;
3056 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3057 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3060 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3065 for (i
= 0; i
< 4; i
++)
3066 if (*s
== "xyzw"[i
])
3068 *channels
|= 1 << (3 - i
);
3074 /* Token types for parsed operand lists. */
3075 enum mips_operand_token_type
{
3076 /* A plain register, e.g. $f2. */
3079 /* A 4-bit XYZW channel mask. */
3082 /* A constant vector index, e.g. [1]. */
3085 /* A register vector index, e.g. [$2]. */
3088 /* A continuous range of registers, e.g. $s0-$s4. */
3091 /* A (possibly relocated) expression. */
3094 /* A floating-point value. */
3097 /* A single character. This can be '(', ')' or ',', but '(' only appears
3101 /* A doubled character, either "--" or "++". */
3104 /* The end of the operand list. */
3108 /* A parsed operand token. */
3109 struct mips_operand_token
3111 /* The type of token. */
3112 enum mips_operand_token_type type
;
3115 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3118 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3119 unsigned int channels
;
3121 /* The integer value of an OT_INTEGER_INDEX. */
3124 /* The two register symbol values involved in an OT_REG_RANGE. */
3126 unsigned int regno1
;
3127 unsigned int regno2
;
3130 /* The value of an OT_INTEGER. The value is represented as an
3131 expression and the relocation operators that were applied to
3132 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3133 relocation operators were used. */
3136 bfd_reloc_code_real_type relocs
[3];
3139 /* The binary data for an OT_FLOAT constant, and the number of bytes
3142 unsigned char data
[8];
3146 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3151 /* An obstack used to construct lists of mips_operand_tokens. */
3152 static struct obstack mips_operand_tokens
;
3154 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3157 mips_add_token (struct mips_operand_token
*token
,
3158 enum mips_operand_token_type type
)
3161 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3164 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3165 and OT_REG tokens for them if so, and return a pointer to the first
3166 unconsumed character. Return null otherwise. */
3169 mips_parse_base_start (char *s
)
3171 struct mips_operand_token token
;
3172 unsigned int regno
, channels
;
3179 SKIP_SPACE_TABS (s
);
3181 /* Only match "--" as part of a base expression. In other contexts "--X"
3182 is a double negative. */
3183 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3187 SKIP_SPACE_TABS (s
);
3190 /* Allow a channel specifier because that leads to better error messages
3191 than treating something like "$vf0x++" as an expression. */
3192 if (!mips_parse_register (&s
, ®no
, &channels
))
3196 mips_add_token (&token
, OT_CHAR
);
3201 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3204 token
.u
.regno
= regno
;
3205 mips_add_token (&token
, OT_REG
);
3209 token
.u
.channels
= channels
;
3210 mips_add_token (&token
, OT_CHANNELS
);
3213 /* For consistency, only match "++" as part of base expressions too. */
3214 SKIP_SPACE_TABS (s
);
3215 if (s
[0] == '+' && s
[1] == '+')
3219 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3225 /* Parse one or more tokens from S. Return a pointer to the first
3226 unconsumed character on success. Return null if an error was found
3227 and store the error text in insn_error. FLOAT_FORMAT is as for
3228 mips_parse_arguments. */
3231 mips_parse_argument_token (char *s
, char float_format
)
3233 char *end
, *save_in
;
3235 unsigned int regno1
, regno2
, channels
;
3236 struct mips_operand_token token
;
3238 /* First look for "($reg", since we want to treat that as an
3239 OT_CHAR and OT_REG rather than an expression. */
3240 end
= mips_parse_base_start (s
);
3244 /* Handle other characters that end up as OT_CHARs. */
3245 if (*s
== ')' || *s
== ',')
3248 mips_add_token (&token
, OT_CHAR
);
3253 /* Handle tokens that start with a register. */
3254 if (mips_parse_register (&s
, ®no1
, &channels
))
3258 /* A register and a VU0 channel suffix. */
3259 token
.u
.regno
= regno1
;
3260 mips_add_token (&token
, OT_REG
);
3262 token
.u
.channels
= channels
;
3263 mips_add_token (&token
, OT_CHANNELS
);
3267 SKIP_SPACE_TABS (s
);
3270 /* A register range. */
3272 SKIP_SPACE_TABS (s
);
3273 if (!mips_parse_register (&s
, ®no2
, NULL
))
3275 set_insn_error (0, _("invalid register range"));
3279 token
.u
.reg_range
.regno1
= regno1
;
3280 token
.u
.reg_range
.regno2
= regno2
;
3281 mips_add_token (&token
, OT_REG_RANGE
);
3285 /* Add the register itself. */
3286 token
.u
.regno
= regno1
;
3287 mips_add_token (&token
, OT_REG
);
3289 /* Check for a vector index. */
3293 SKIP_SPACE_TABS (s
);
3294 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3295 mips_add_token (&token
, OT_REG_INDEX
);
3298 expressionS element
;
3300 my_getExpression (&element
, s
);
3301 if (element
.X_op
!= O_constant
)
3303 set_insn_error (0, _("vector element must be constant"));
3307 token
.u
.index
= element
.X_add_number
;
3308 mips_add_token (&token
, OT_INTEGER_INDEX
);
3310 SKIP_SPACE_TABS (s
);
3313 set_insn_error (0, _("missing `]'"));
3323 /* First try to treat expressions as floats. */
3324 save_in
= input_line_pointer
;
3325 input_line_pointer
= s
;
3326 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3327 &token
.u
.flt
.length
);
3328 end
= input_line_pointer
;
3329 input_line_pointer
= save_in
;
3332 set_insn_error (0, err
);
3337 mips_add_token (&token
, OT_FLOAT
);
3342 /* Treat everything else as an integer expression. */
3343 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3344 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3345 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3346 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3348 mips_add_token (&token
, OT_INTEGER
);
3352 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3353 if expressions should be treated as 32-bit floating-point constants,
3354 'd' if they should be treated as 64-bit floating-point constants,
3355 or 0 if they should be treated as integer expressions (the usual case).
3357 Return a list of tokens on success, otherwise return 0. The caller
3358 must obstack_free the list after use. */
3360 static struct mips_operand_token
*
3361 mips_parse_arguments (char *s
, char float_format
)
3363 struct mips_operand_token token
;
3365 SKIP_SPACE_TABS (s
);
3368 s
= mips_parse_argument_token (s
, float_format
);
3371 obstack_free (&mips_operand_tokens
,
3372 obstack_finish (&mips_operand_tokens
));
3375 SKIP_SPACE_TABS (s
);
3377 mips_add_token (&token
, OT_END
);
3378 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3381 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3382 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3385 is_opcode_valid (const struct mips_opcode
*mo
)
3387 int isa
= mips_opts
.isa
;
3388 int ase
= mips_opts
.ase
;
3392 if (ISA_HAS_64BIT_REGS (isa
))
3393 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3394 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3395 ase
|= mips_ases
[i
].flags64
;
3397 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3400 /* Check whether the instruction or macro requires single-precision or
3401 double-precision floating-point support. Note that this information is
3402 stored differently in the opcode table for insns and macros. */
3403 if (mo
->pinfo
== INSN_MACRO
)
3405 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3406 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3410 fp_s
= mo
->pinfo
& FP_S
;
3411 fp_d
= mo
->pinfo
& FP_D
;
3414 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3417 if (fp_s
&& mips_opts
.soft_float
)
3423 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3424 selected ISA and architecture. */
3427 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3429 int isa
= mips_opts
.isa
;
3430 int ase
= mips_opts
.ase
;
3433 if (ISA_HAS_64BIT_REGS (isa
))
3434 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3435 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3436 ase
|= mips_ases
[i
].flags64
;
3438 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3441 /* Return TRUE if the size of the microMIPS opcode MO matches one
3442 explicitly requested. Always TRUE in the standard MIPS mode.
3443 Use is_size_valid_16 for MIPS16 opcodes. */
3446 is_size_valid (const struct mips_opcode
*mo
)
3448 if (!mips_opts
.micromips
)
3451 if (mips_opts
.insn32
)
3453 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3455 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3458 if (!forced_insn_length
)
3460 if (mo
->pinfo
== INSN_MACRO
)
3462 return forced_insn_length
== micromips_insn_length (mo
);
3465 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3466 explicitly requested. */
3469 is_size_valid_16 (const struct mips_opcode
*mo
)
3471 if (!forced_insn_length
)
3473 if (mo
->pinfo
== INSN_MACRO
)
3475 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3477 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3482 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3483 of the preceding instruction. Always TRUE in the standard MIPS mode.
3485 We don't accept macros in 16-bit delay slots to avoid a case where
3486 a macro expansion fails because it relies on a preceding 32-bit real
3487 instruction to have matched and does not handle the operands correctly.
3488 The only macros that may expand to 16-bit instructions are JAL that
3489 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3490 and BGT (that likewise cannot be placed in a delay slot) that decay to
3491 a NOP. In all these cases the macros precede any corresponding real
3492 instruction definitions in the opcode table, so they will match in the
3493 second pass where the size of the delay slot is ignored and therefore
3494 produce correct code. */
3497 is_delay_slot_valid (const struct mips_opcode
*mo
)
3499 if (!mips_opts
.micromips
)
3502 if (mo
->pinfo
== INSN_MACRO
)
3503 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3504 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3505 && micromips_insn_length (mo
) != 4)
3507 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3508 && micromips_insn_length (mo
) != 2)
3514 /* For consistency checking, verify that all bits of OPCODE are specified
3515 either by the match/mask part of the instruction definition, or by the
3516 operand list. Also build up a list of operands in OPERANDS.
3518 INSN_BITS says which bits of the instruction are significant.
3519 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3520 provides the mips_operand description of each operand. DECODE_OPERAND
3521 is null for MIPS16 instructions. */
3524 validate_mips_insn (const struct mips_opcode
*opcode
,
3525 unsigned long insn_bits
,
3526 const struct mips_operand
*(*decode_operand
) (const char *),
3527 struct mips_operand_array
*operands
)
3530 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3531 const struct mips_operand
*operand
;
3533 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3534 if ((mask
& opcode
->match
) != opcode
->match
)
3536 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3537 opcode
->name
, opcode
->args
);
3542 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3543 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3544 for (s
= opcode
->args
; *s
; ++s
)
3557 if (!decode_operand
)
3558 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3560 operand
= decode_operand (s
);
3561 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3563 as_bad (_("internal: unknown operand type: %s %s"),
3564 opcode
->name
, opcode
->args
);
3567 gas_assert (opno
< MAX_OPERANDS
);
3568 operands
->operand
[opno
] = operand
;
3569 if (!decode_operand
&& operand
3570 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3571 && mips_opcode_32bit_p (opcode
))
3572 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3573 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3575 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3576 if (operand
->type
== OP_MDMX_IMM_REG
)
3577 /* Bit 5 is the format selector (OB vs QH). The opcode table
3578 has separate entries for each format. */
3579 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3580 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3581 used_bits
&= ~(mask
& 0x700);
3582 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3583 operand field that cannot be fully described with LSB/SIZE. */
3584 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3585 used_bits
&= ~0x6000;
3587 /* Skip prefix characters. */
3588 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3593 doubled
= used_bits
& mask
& insn_bits
;
3596 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3597 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3601 undefined
= ~used_bits
& insn_bits
;
3602 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3604 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3605 undefined
, opcode
->name
, opcode
->args
);
3608 used_bits
&= ~insn_bits
;
3611 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3612 used_bits
, opcode
->name
, opcode
->args
);
3618 /* The MIPS16 version of validate_mips_insn. */
3621 validate_mips16_insn (const struct mips_opcode
*opcode
,
3622 struct mips_operand_array
*operands
)
3624 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3626 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3629 /* The microMIPS version of validate_mips_insn. */
3632 validate_micromips_insn (const struct mips_opcode
*opc
,
3633 struct mips_operand_array
*operands
)
3635 unsigned long insn_bits
;
3636 unsigned long major
;
3637 unsigned int length
;
3639 if (opc
->pinfo
== INSN_MACRO
)
3640 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3643 length
= micromips_insn_length (opc
);
3644 if (length
!= 2 && length
!= 4)
3646 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3647 "%s %s"), length
, opc
->name
, opc
->args
);
3650 major
= opc
->match
>> (10 + 8 * (length
- 2));
3651 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3652 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3654 as_bad (_("internal error: bad microMIPS opcode "
3655 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3659 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3660 insn_bits
= 1 << 4 * length
;
3661 insn_bits
<<= 4 * length
;
3663 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3667 /* This function is called once, at assembler startup time. It should set up
3668 all the tables, etc. that the MD part of the assembler will need. */
3676 if (mips_pic
!= NO_PIC
)
3678 if (g_switch_seen
&& g_switch_value
!= 0)
3679 as_bad (_("-G may not be used in position-independent code"));
3682 else if (mips_abicalls
)
3684 if (g_switch_seen
&& g_switch_value
!= 0)
3685 as_bad (_("-G may not be used with abicalls"));
3689 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3690 as_warn (_("could not set architecture and machine"));
3692 op_hash
= str_htab_create ();
3694 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3695 for (i
= 0; i
< NUMOPCODES
;)
3697 const char *name
= mips_opcodes
[i
].name
;
3699 if (str_hash_insert (op_hash
, name
, &mips_opcodes
[i
], 0) != NULL
)
3700 as_fatal (_("duplicate %s"), name
);
3703 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3704 decode_mips_operand
, &mips_operands
[i
]))
3707 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3709 create_insn (&nop_insn
, mips_opcodes
+ i
);
3710 if (mips_fix_loongson2f_nop
)
3711 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3712 nop_insn
.fixed_p
= 1;
3715 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3716 create_insn (&sync_insn
, mips_opcodes
+ i
);
3720 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3723 mips16_op_hash
= str_htab_create ();
3724 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3725 bfd_mips16_num_opcodes
);
3728 while (i
< bfd_mips16_num_opcodes
)
3730 const char *name
= mips16_opcodes
[i
].name
;
3732 if (str_hash_insert (mips16_op_hash
, name
, &mips16_opcodes
[i
], 0))
3733 as_fatal (_("duplicate %s"), name
);
3736 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3738 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3740 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3741 mips16_nop_insn
.fixed_p
= 1;
3745 while (i
< bfd_mips16_num_opcodes
3746 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3749 micromips_op_hash
= str_htab_create ();
3750 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3751 bfd_micromips_num_opcodes
);
3754 while (i
< bfd_micromips_num_opcodes
)
3756 const char *name
= micromips_opcodes
[i
].name
;
3758 if (str_hash_insert (micromips_op_hash
, name
, µmips_opcodes
[i
], 0))
3759 as_fatal (_("duplicate %s"), name
);
3762 struct mips_cl_insn
*micromips_nop_insn
;
3764 if (!validate_micromips_insn (µmips_opcodes
[i
],
3765 µmips_operands
[i
]))
3768 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3770 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3771 micromips_nop_insn
= µmips_nop16_insn
;
3772 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3773 micromips_nop_insn
= µmips_nop32_insn
;
3777 if (micromips_nop_insn
->insn_mo
== NULL
3778 && strcmp (name
, "nop") == 0)
3780 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3781 micromips_nop_insn
->fixed_p
= 1;
3785 while (++i
< bfd_micromips_num_opcodes
3786 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3790 as_fatal (_("broken assembler, no assembly attempted"));
3792 /* We add all the general register names to the symbol table. This
3793 helps us detect invalid uses of them. */
3794 for (i
= 0; reg_names
[i
].name
; i
++)
3795 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3799 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3800 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3802 reg_names_n32n64
[i
].num
));
3804 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3805 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3807 reg_names_o32
[i
].num
));
3809 for (i
= 0; i
< 32; i
++)
3813 /* R5900 VU0 floating-point register. */
3814 sprintf (regname
, "$vf%d", i
);
3815 symbol_table_insert (symbol_new (regname
, reg_section
,
3816 &zero_address_frag
, RTYPE_VF
| i
));
3818 /* R5900 VU0 integer register. */
3819 sprintf (regname
, "$vi%d", i
);
3820 symbol_table_insert (symbol_new (regname
, reg_section
,
3821 &zero_address_frag
, RTYPE_VI
| i
));
3824 sprintf (regname
, "$w%d", i
);
3825 symbol_table_insert (symbol_new (regname
, reg_section
,
3826 &zero_address_frag
, RTYPE_MSA
| i
));
3829 obstack_init (&mips_operand_tokens
);
3831 mips_no_prev_insn ();
3834 mips_cprmask
[0] = 0;
3835 mips_cprmask
[1] = 0;
3836 mips_cprmask
[2] = 0;
3837 mips_cprmask
[3] = 0;
3839 /* set the default alignment for the text section (2**2) */
3840 record_alignment (text_section
, 2);
3842 bfd_set_gp_size (stdoutput
, g_switch_value
);
3844 /* On a native system other than VxWorks, sections must be aligned
3845 to 16 byte boundaries. When configured for an embedded ELF
3846 target, we don't bother. */
3847 if (!startswith (TARGET_OS
, "elf")
3848 && !startswith (TARGET_OS
, "vxworks"))
3850 bfd_set_section_alignment (text_section
, 4);
3851 bfd_set_section_alignment (data_section
, 4);
3852 bfd_set_section_alignment (bss_section
, 4);
3855 /* Create a .reginfo section for register masks and a .mdebug
3856 section for debugging information. */
3864 subseg
= now_subseg
;
3866 /* The ABI says this section should be loaded so that the
3867 running program can access it. However, we don't load it
3868 if we are configured for an embedded target. */
3869 flags
= SEC_READONLY
| SEC_DATA
;
3870 if (!startswith (TARGET_OS
, "elf"))
3871 flags
|= SEC_ALLOC
| SEC_LOAD
;
3873 if (mips_abi
!= N64_ABI
)
3875 sec
= subseg_new (".reginfo", (subsegT
) 0);
3877 bfd_set_section_flags (sec
, flags
);
3878 bfd_set_section_alignment (sec
, HAVE_NEWABI
? 3 : 2);
3880 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3884 /* The 64-bit ABI uses a .MIPS.options section rather than
3885 .reginfo section. */
3886 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3887 bfd_set_section_flags (sec
, flags
);
3888 bfd_set_section_alignment (sec
, 3);
3890 /* Set up the option header. */
3892 Elf_Internal_Options opthdr
;
3895 opthdr
.kind
= ODK_REGINFO
;
3896 opthdr
.size
= (sizeof (Elf_External_Options
)
3897 + sizeof (Elf64_External_RegInfo
));
3900 f
= frag_more (sizeof (Elf_External_Options
));
3901 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3902 (Elf_External_Options
*) f
);
3904 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3908 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3909 bfd_set_section_flags (sec
,
3910 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3911 bfd_set_section_alignment (sec
, 3);
3912 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3914 if (ECOFF_DEBUGGING
)
3916 sec
= subseg_new (".mdebug", (subsegT
) 0);
3917 bfd_set_section_flags (sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
3918 bfd_set_section_alignment (sec
, 2);
3920 else if (mips_flag_pdr
)
3922 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3923 bfd_set_section_flags (pdr_seg
,
3924 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
3925 bfd_set_section_alignment (pdr_seg
, 2);
3928 subseg_set (seg
, subseg
);
3931 if (mips_fix_vr4120
)
3932 init_vr4120_conflicts ();
3936 fpabi_incompatible_with (int fpabi
, const char *what
)
3938 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3939 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3943 fpabi_requires (int fpabi
, const char *what
)
3945 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3946 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3949 /* Check -mabi and register sizes against the specified FP ABI. */
3951 check_fpabi (int fpabi
)
3955 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3956 if (file_mips_opts
.soft_float
)
3957 fpabi_incompatible_with (fpabi
, "softfloat");
3958 else if (file_mips_opts
.single_float
)
3959 fpabi_incompatible_with (fpabi
, "singlefloat");
3960 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3961 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3962 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3963 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3966 case Val_GNU_MIPS_ABI_FP_XX
:
3967 if (mips_abi
!= O32_ABI
)
3968 fpabi_requires (fpabi
, "-mabi=32");
3969 else if (file_mips_opts
.soft_float
)
3970 fpabi_incompatible_with (fpabi
, "softfloat");
3971 else if (file_mips_opts
.single_float
)
3972 fpabi_incompatible_with (fpabi
, "singlefloat");
3973 else if (file_mips_opts
.fp
!= 0)
3974 fpabi_requires (fpabi
, "fp=xx");
3977 case Val_GNU_MIPS_ABI_FP_64A
:
3978 case Val_GNU_MIPS_ABI_FP_64
:
3979 if (mips_abi
!= O32_ABI
)
3980 fpabi_requires (fpabi
, "-mabi=32");
3981 else if (file_mips_opts
.soft_float
)
3982 fpabi_incompatible_with (fpabi
, "softfloat");
3983 else if (file_mips_opts
.single_float
)
3984 fpabi_incompatible_with (fpabi
, "singlefloat");
3985 else if (file_mips_opts
.fp
!= 64)
3986 fpabi_requires (fpabi
, "fp=64");
3987 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3988 fpabi_incompatible_with (fpabi
, "nooddspreg");
3989 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3990 fpabi_requires (fpabi
, "nooddspreg");
3993 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3994 if (file_mips_opts
.soft_float
)
3995 fpabi_incompatible_with (fpabi
, "softfloat");
3996 else if (!file_mips_opts
.single_float
)
3997 fpabi_requires (fpabi
, "singlefloat");
4000 case Val_GNU_MIPS_ABI_FP_SOFT
:
4001 if (!file_mips_opts
.soft_float
)
4002 fpabi_requires (fpabi
, "softfloat");
4005 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4006 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4007 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4010 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4011 /* Silently ignore compatibility value. */
4015 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4016 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4021 /* Perform consistency checks on the current options. */
4024 mips_check_options (struct mips_set_options
*opts
, bool abi_checks
)
4026 /* Check the size of integer registers agrees with the ABI and ISA. */
4027 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4028 as_bad (_("`gp=64' used with a 32-bit processor"));
4030 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4031 as_bad (_("`gp=32' used with a 64-bit ABI"));
4033 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4034 as_bad (_("`gp=64' used with a 32-bit ABI"));
4036 /* Check the size of the float registers agrees with the ABI and ISA. */
4040 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4041 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4042 else if (opts
->single_float
== 1)
4043 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4046 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4047 as_bad (_("`fp=64' used with a 32-bit fpu"));
4049 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4050 && !ISA_HAS_MXHC1 (opts
->isa
))
4051 as_warn (_("`fp=64' used with a 32-bit ABI"));
4055 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4056 as_warn (_("`fp=32' used with a 64-bit ABI"));
4057 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4058 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4061 as_bad (_("Unknown size of floating point registers"));
4065 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4066 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4068 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4069 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4070 else if (ISA_IS_R6 (opts
->isa
)
4071 && (opts
->micromips
== 1
4072 || opts
->mips16
== 1))
4073 as_fatal (_("`%s' cannot be used with `%s'"),
4074 opts
->micromips
? "micromips" : "mips16",
4075 mips_cpu_info_from_isa (opts
->isa
)->name
);
4077 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4078 as_fatal (_("branch relaxation is not supported in `%s'"),
4079 mips_cpu_info_from_isa (opts
->isa
)->name
);
4082 /* Perform consistency checks on the module level options exactly once.
4083 This is a deferred check that happens:
4084 at the first .set directive
4085 or, at the first pseudo op that generates code (inc .dc.a)
4086 or, at the first instruction
4090 file_mips_check_options (void)
4092 if (file_mips_opts_checked
)
4095 /* The following code determines the register size.
4096 Similar code was added to GCC 3.3 (see override_options() in
4097 config/mips/mips.c). The GAS and GCC code should be kept in sync
4098 as much as possible. */
4100 if (file_mips_opts
.gp
< 0)
4102 /* Infer the integer register size from the ABI and processor.
4103 Restrict ourselves to 32-bit registers if that's all the
4104 processor has, or if the ABI cannot handle 64-bit registers. */
4105 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4106 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4110 if (file_mips_opts
.fp
< 0)
4112 /* No user specified float register size.
4113 ??? GAS treats single-float processors as though they had 64-bit
4114 float registers (although it complains when double-precision
4115 instructions are used). As things stand, saying they have 32-bit
4116 registers would lead to spurious "register must be even" messages.
4117 So here we assume float registers are never smaller than the
4119 if (file_mips_opts
.gp
== 64)
4120 /* 64-bit integer registers implies 64-bit float registers. */
4121 file_mips_opts
.fp
= 64;
4122 else if ((file_mips_opts
.ase
& FP64_ASES
)
4123 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4124 /* Handle ASEs that require 64-bit float registers, if possible. */
4125 file_mips_opts
.fp
= 64;
4126 else if (ISA_IS_R6 (mips_opts
.isa
))
4127 /* R6 implies 64-bit float registers. */
4128 file_mips_opts
.fp
= 64;
4130 /* 32-bit float registers. */
4131 file_mips_opts
.fp
= 32;
4134 /* Disable operations on odd-numbered floating-point registers by default
4135 when using the FPXX ABI. */
4136 if (file_mips_opts
.oddspreg
< 0)
4138 if (file_mips_opts
.fp
== 0)
4139 file_mips_opts
.oddspreg
= 0;
4141 file_mips_opts
.oddspreg
= 1;
4144 /* End of GCC-shared inference code. */
4146 /* This flag is set when we have a 64-bit capable CPU but use only
4147 32-bit wide registers. Note that EABI does not use it. */
4148 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4149 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4150 || mips_abi
== O32_ABI
))
4153 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4154 as_bad (_("trap exception not supported at ISA 1"));
4156 /* If the selected architecture includes support for ASEs, enable
4157 generation of code for them. */
4158 if (file_mips_opts
.mips16
== -1)
4159 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4160 if (file_mips_opts
.micromips
== -1)
4161 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4164 if (mips_nan2008
== -1)
4165 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4166 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4167 as_fatal (_("`%s' does not support legacy NaN"),
4168 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4170 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4171 being selected implicitly. */
4172 if (file_mips_opts
.fp
!= 64)
4173 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4175 /* If the user didn't explicitly select or deselect a particular ASE,
4176 use the default setting for the CPU. */
4177 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4179 /* Set up the current options. These may change throughout assembly. */
4180 mips_opts
= file_mips_opts
;
4182 mips_check_isa_supports_ases ();
4183 mips_check_options (&file_mips_opts
, true);
4184 file_mips_opts_checked
= true;
4186 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4187 as_warn (_("could not set architecture and machine"));
4191 md_assemble (char *str
)
4193 struct mips_cl_insn insn
;
4194 bfd_reloc_code_real_type unused_reloc
[3]
4195 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4197 file_mips_check_options ();
4199 imm_expr
.X_op
= O_absent
;
4200 offset_expr
.X_op
= O_absent
;
4201 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4202 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4203 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4205 mips_mark_labels ();
4206 mips_assembling_insn
= true;
4207 clear_insn_error ();
4209 if (mips_opts
.mips16
)
4210 mips16_ip (str
, &insn
);
4213 mips_ip (str
, &insn
);
4214 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4215 str
, insn
.insn_opcode
));
4219 report_insn_error (str
);
4220 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4223 if (mips_opts
.mips16
)
4224 mips16_macro (&insn
);
4231 if (offset_expr
.X_op
!= O_absent
)
4232 append_insn (&insn
, &offset_expr
, offset_reloc
, false);
4234 append_insn (&insn
, NULL
, unused_reloc
, false);
4237 mips_assembling_insn
= false;
4240 /* Convenience functions for abstracting away the differences between
4241 MIPS16 and non-MIPS16 relocations. */
4244 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4248 case BFD_RELOC_MIPS16_JMP
:
4249 case BFD_RELOC_MIPS16_GPREL
:
4250 case BFD_RELOC_MIPS16_GOT16
:
4251 case BFD_RELOC_MIPS16_CALL16
:
4252 case BFD_RELOC_MIPS16_HI16_S
:
4253 case BFD_RELOC_MIPS16_HI16
:
4254 case BFD_RELOC_MIPS16_LO16
:
4255 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4264 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4268 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4269 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4270 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4271 case BFD_RELOC_MICROMIPS_GPREL16
:
4272 case BFD_RELOC_MICROMIPS_JMP
:
4273 case BFD_RELOC_MICROMIPS_HI16
:
4274 case BFD_RELOC_MICROMIPS_HI16_S
:
4275 case BFD_RELOC_MICROMIPS_LO16
:
4276 case BFD_RELOC_MICROMIPS_LITERAL
:
4277 case BFD_RELOC_MICROMIPS_GOT16
:
4278 case BFD_RELOC_MICROMIPS_CALL16
:
4279 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4280 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4281 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4282 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4283 case BFD_RELOC_MICROMIPS_SUB
:
4284 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4285 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4286 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4287 case BFD_RELOC_MICROMIPS_HIGHEST
:
4288 case BFD_RELOC_MICROMIPS_HIGHER
:
4289 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4290 case BFD_RELOC_MICROMIPS_JALR
:
4299 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4301 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4305 b_reloc_p (bfd_reloc_code_real_type reloc
)
4307 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4308 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4309 || reloc
== BFD_RELOC_16_PCREL_S2
4310 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4311 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4312 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4313 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4317 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4319 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4320 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4324 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4326 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4327 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4331 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4333 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4334 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4338 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4340 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4344 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4346 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4347 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4350 /* Return true if RELOC is a PC-relative relocation that does not have
4351 full address range. */
4354 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4358 case BFD_RELOC_16_PCREL_S2
:
4359 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4360 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4361 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4362 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4363 case BFD_RELOC_MIPS_21_PCREL_S2
:
4364 case BFD_RELOC_MIPS_26_PCREL_S2
:
4365 case BFD_RELOC_MIPS_18_PCREL_S3
:
4366 case BFD_RELOC_MIPS_19_PCREL_S2
:
4369 case BFD_RELOC_32_PCREL
:
4370 case BFD_RELOC_HI16_S_PCREL
:
4371 case BFD_RELOC_LO16_PCREL
:
4372 return HAVE_64BIT_ADDRESSES
;
4379 /* Return true if the given relocation might need a matching %lo().
4380 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4381 need a matching %lo() when applied to local symbols. */
4384 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4386 return (HAVE_IN_PLACE_ADDENDS
4387 && (hi16_reloc_p (reloc
)
4388 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4389 all GOT16 relocations evaluate to "G". */
4390 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4393 /* Return the type of %lo() reloc needed by RELOC, given that
4394 reloc_needs_lo_p. */
4396 static inline bfd_reloc_code_real_type
4397 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4399 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4400 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4404 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4408 fixup_has_matching_lo_p (fixS
*fixp
)
4410 return (fixp
->fx_next
!= NULL
4411 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4412 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4413 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4416 /* Move all labels in LABELS to the current insertion point. TEXT_P
4417 says whether the labels refer to text or data. */
4420 mips_move_labels (struct insn_label_list
*labels
, bool text_p
)
4422 struct insn_label_list
*l
;
4425 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4427 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4428 symbol_set_frag (l
->label
, frag_now
);
4429 val
= (valueT
) frag_now_fix ();
4430 /* MIPS16/microMIPS text labels are stored as odd.
4431 We just carry the ISA mode bit forward. */
4432 if (text_p
&& HAVE_CODE_COMPRESSION
)
4433 val
|= (S_GET_VALUE (l
->label
) & 0x1);
4434 S_SET_VALUE (l
->label
, val
);
4438 /* Move all labels in insn_labels to the current insertion point
4439 and treat them as text labels. */
4442 mips_move_text_labels (void)
4444 mips_move_labels (seg_info (now_seg
)->label_list
, true);
4447 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4450 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4452 bool linkonce
= false;
4453 segT symseg
= S_GET_SEGMENT (sym
);
4455 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4457 if ((bfd_section_flags (symseg
) & SEC_LINK_ONCE
))
4459 /* The GNU toolchain uses an extension for ELF: a section
4460 beginning with the magic string .gnu.linkonce is a
4461 linkonce section. */
4462 if (startswith (segment_name (symseg
), ".gnu.linkonce"))
4468 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4469 linker to handle them specially, such as generating jalx instructions
4470 when needed. We also make them odd for the duration of the assembly,
4471 in order to generate the right sort of code. We will make them even
4472 in the adjust_symtab routine, while leaving them marked. This is
4473 convenient for the debugger and the disassembler. The linker knows
4474 to make them odd again. */
4477 mips_compressed_mark_label (symbolS
*label
)
4479 gas_assert (HAVE_CODE_COMPRESSION
);
4481 if (mips_opts
.mips16
)
4482 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4484 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4485 if ((S_GET_VALUE (label
) & 1) == 0
4486 /* Don't adjust the address if the label is global or weak, or
4487 in a link-once section, since we'll be emitting symbol reloc
4488 references to it which will be patched up by the linker, and
4489 the final value of the symbol may or may not be MIPS16/microMIPS. */
4490 && !S_IS_WEAK (label
)
4491 && !S_IS_EXTERNAL (label
)
4492 && !s_is_linkonce (label
, now_seg
))
4493 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4496 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4499 mips_compressed_mark_labels (void)
4501 struct insn_label_list
*l
;
4503 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4504 mips_compressed_mark_label (l
->label
);
4507 /* End the current frag. Make it a variant frag and record the
4511 relax_close_frag (void)
4513 mips_macro_warning
.first_frag
= frag_now
;
4514 frag_var (rs_machine_dependent
, 0, 0,
4515 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4516 mips_pic
!= NO_PIC
),
4517 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4519 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4520 mips_relax
.first_fixup
= 0;
4523 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4524 See the comment above RELAX_ENCODE for more details. */
4527 relax_start (symbolS
*symbol
)
4529 gas_assert (mips_relax
.sequence
== 0);
4530 mips_relax
.sequence
= 1;
4531 mips_relax
.symbol
= symbol
;
4534 /* Start generating the second version of a relaxable sequence.
4535 See the comment above RELAX_ENCODE for more details. */
4540 gas_assert (mips_relax
.sequence
== 1);
4541 mips_relax
.sequence
= 2;
4544 /* End the current relaxable sequence. */
4549 gas_assert (mips_relax
.sequence
== 2);
4550 relax_close_frag ();
4551 mips_relax
.sequence
= 0;
4554 /* Return true if IP is a delayed branch or jump. */
4557 delayed_branch_p (const struct mips_cl_insn
*ip
)
4559 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4560 | INSN_COND_BRANCH_DELAY
4561 | INSN_COND_BRANCH_LIKELY
)) != 0;
4564 /* Return true if IP is a compact branch or jump. */
4567 compact_branch_p (const struct mips_cl_insn
*ip
)
4569 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4570 | INSN2_COND_BRANCH
)) != 0;
4573 /* Return true if IP is an unconditional branch or jump. */
4576 uncond_branch_p (const struct mips_cl_insn
*ip
)
4578 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4579 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4582 /* Return true if IP is a branch-likely instruction. */
4585 branch_likely_p (const struct mips_cl_insn
*ip
)
4587 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4590 /* Return the type of nop that should be used to fill the delay slot
4591 of delayed branch IP. */
4593 static struct mips_cl_insn
*
4594 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4596 if (mips_opts
.micromips
4597 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4598 return µmips_nop32_insn
;
4602 /* Return a mask that has bit N set if OPCODE reads the register(s)
4606 insn_read_mask (const struct mips_opcode
*opcode
)
4608 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4611 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4615 insn_write_mask (const struct mips_opcode
*opcode
)
4617 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4620 /* Return a mask of the registers specified by operand OPERAND of INSN.
4621 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4625 operand_reg_mask (const struct mips_cl_insn
*insn
,
4626 const struct mips_operand
*operand
,
4627 unsigned int type_mask
)
4629 unsigned int uval
, vsel
;
4631 switch (operand
->type
)
4638 case OP_ADDIUSP_INT
:
4639 case OP_ENTRY_EXIT_LIST
:
4640 case OP_REPEAT_DEST_REG
:
4641 case OP_REPEAT_PREV_REG
:
4644 case OP_VU0_MATCH_SUFFIX
:
4652 case OP_OPTIONAL_REG
:
4654 const struct mips_reg_operand
*reg_op
;
4656 reg_op
= (const struct mips_reg_operand
*) operand
;
4657 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4659 uval
= insn_extract_operand (insn
, operand
);
4660 return 1u << mips_decode_reg_operand (reg_op
, uval
);
4665 const struct mips_reg_pair_operand
*pair_op
;
4667 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4668 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4670 uval
= insn_extract_operand (insn
, operand
);
4671 return (1u << pair_op
->reg1_map
[uval
]) | (1u << pair_op
->reg2_map
[uval
]);
4674 case OP_CLO_CLZ_DEST
:
4675 if (!(type_mask
& (1 << OP_REG_GP
)))
4677 uval
= insn_extract_operand (insn
, operand
);
4678 return (1u << (uval
& 31)) | (1u << (uval
>> 5));
4681 if (!(type_mask
& (1 << OP_REG_GP
)))
4683 uval
= insn_extract_operand (insn
, operand
);
4684 gas_assert ((uval
& 31) == (uval
>> 5));
4685 return 1u << (uval
& 31);
4688 case OP_NON_ZERO_REG
:
4689 if (!(type_mask
& (1 << OP_REG_GP
)))
4691 uval
= insn_extract_operand (insn
, operand
);
4692 return 1u << (uval
& 31);
4694 case OP_LWM_SWM_LIST
:
4697 case OP_SAVE_RESTORE_LIST
:
4700 case OP_MDMX_IMM_REG
:
4701 if (!(type_mask
& (1 << OP_REG_VEC
)))
4703 uval
= insn_extract_operand (insn
, operand
);
4705 if ((vsel
& 0x18) == 0x18)
4707 return 1u << (uval
& 31);
4710 if (!(type_mask
& (1 << OP_REG_GP
)))
4712 return 1u << insn_extract_operand (insn
, operand
);
4717 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4718 where bit N of OPNO_MASK is set if operand N should be included.
4719 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4723 insn_reg_mask (const struct mips_cl_insn
*insn
,
4724 unsigned int type_mask
, unsigned int opno_mask
)
4726 unsigned int opno
, reg_mask
;
4730 while (opno_mask
!= 0)
4733 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4740 /* Return the mask of core registers that IP reads. */
4743 gpr_read_mask (const struct mips_cl_insn
*ip
)
4745 unsigned long pinfo
, pinfo2
;
4748 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4749 pinfo
= ip
->insn_mo
->pinfo
;
4750 pinfo2
= ip
->insn_mo
->pinfo2
;
4751 if (pinfo
& INSN_UDI
)
4753 /* UDI instructions have traditionally been assumed to read RS
4755 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4756 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4758 if (pinfo
& INSN_READ_GPR_24
)
4760 if (pinfo2
& INSN2_READ_GPR_16
)
4762 if (pinfo2
& INSN2_READ_SP
)
4764 if (pinfo2
& INSN2_READ_GPR_31
)
4766 /* Don't include register 0. */
4770 /* Return the mask of core registers that IP writes. */
4773 gpr_write_mask (const struct mips_cl_insn
*ip
)
4775 unsigned long pinfo
, pinfo2
;
4778 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4779 pinfo
= ip
->insn_mo
->pinfo
;
4780 pinfo2
= ip
->insn_mo
->pinfo2
;
4781 if (pinfo
& INSN_WRITE_GPR_24
)
4783 if (pinfo
& INSN_WRITE_GPR_31
)
4785 if (pinfo
& INSN_UDI
)
4786 /* UDI instructions have traditionally been assumed to write to RD. */
4787 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4788 if (pinfo2
& INSN2_WRITE_SP
)
4790 /* Don't include register 0. */
4794 /* Return the mask of floating-point registers that IP reads. */
4797 fpr_read_mask (const struct mips_cl_insn
*ip
)
4799 unsigned long pinfo
;
4802 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4803 | (1 << OP_REG_MSA
)),
4804 insn_read_mask (ip
->insn_mo
));
4805 pinfo
= ip
->insn_mo
->pinfo
;
4806 /* Conservatively treat all operands to an FP_D instruction are doubles.
4807 (This is overly pessimistic for things like cvt.d.s.) */
4808 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4813 /* Return the mask of floating-point registers that IP writes. */
4816 fpr_write_mask (const struct mips_cl_insn
*ip
)
4818 unsigned long pinfo
;
4821 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4822 | (1 << OP_REG_MSA
)),
4823 insn_write_mask (ip
->insn_mo
));
4824 pinfo
= ip
->insn_mo
->pinfo
;
4825 /* Conservatively treat all operands to an FP_D instruction are doubles.
4826 (This is overly pessimistic for things like cvt.s.d.) */
4827 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4832 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4833 Check whether that is allowed. */
4836 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4838 const char *s
= insn
->name
;
4839 bool oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4840 || FPR_SIZE
== 64) && mips_opts
.oddspreg
;
4842 if (insn
->pinfo
== INSN_MACRO
)
4843 /* Let a macro pass, we'll catch it later when it is expanded. */
4846 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4847 otherwise it depends on oddspreg. */
4848 if ((insn
->pinfo
& FP_S
)
4849 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4850 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4851 return FPR_SIZE
== 32 || oddspreg
;
4853 /* Allow odd registers for single-precision ops and double-precision if the
4854 floating-point registers are 64-bit wide. */
4855 switch (insn
->pinfo
& (FP_S
| FP_D
))
4861 return FPR_SIZE
== 64;
4866 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4867 s
= strchr (insn
->name
, '.');
4868 if (s
!= NULL
&& opnum
== 2)
4869 s
= strchr (s
+ 1, '.');
4870 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4873 return FPR_SIZE
== 64;
4876 /* Information about an instruction argument that we're trying to match. */
4877 struct mips_arg_info
4879 /* The instruction so far. */
4880 struct mips_cl_insn
*insn
;
4882 /* The first unconsumed operand token. */
4883 struct mips_operand_token
*token
;
4885 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4888 /* The 1-based argument number, for error reporting. This does not
4889 count elided optional registers, etc.. */
4892 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4893 unsigned int last_regno
;
4895 /* If the first operand was an OP_REG, this is the register that it
4896 specified, otherwise it is ILLEGAL_REG. */
4897 unsigned int dest_regno
;
4899 /* The value of the last OP_INT operand. Only used for OP_MSB,
4900 where it gives the lsb position. */
4901 unsigned int last_op_int
;
4903 /* If true, match routines should assume that no later instruction
4904 alternative matches and should therefore be as accommodating as
4905 possible. Match routines should not report errors if something
4906 is only invalid for !LAX_MATCH. */
4909 /* True if a reference to the current AT register was seen. */
4913 /* Record that the argument is out of range. */
4916 match_out_of_range (struct mips_arg_info
*arg
)
4918 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4921 /* Record that the argument isn't constant but needs to be. */
4924 match_not_constant (struct mips_arg_info
*arg
)
4926 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4930 /* Try to match an OT_CHAR token for character CH. Consume the token
4931 and return true on success, otherwise return false. */
4934 match_char (struct mips_arg_info
*arg
, char ch
)
4936 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4946 /* Try to get an expression from the next tokens in ARG. Consume the
4947 tokens and return true on success, storing the expression value in
4948 VALUE and relocation types in R. */
4951 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4952 bfd_reloc_code_real_type
*r
)
4954 /* If the next token is a '(' that was parsed as being part of a base
4955 expression, assume we have an elided offset. The later match will fail
4956 if this turns out to be wrong. */
4957 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4959 value
->X_op
= O_constant
;
4960 value
->X_add_number
= 0;
4961 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4965 /* Reject register-based expressions such as "0+$2" and "(($2))".
4966 For plain registers the default error seems more appropriate. */
4967 if (arg
->token
->type
== OT_INTEGER
4968 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4970 set_insn_error (arg
->argnum
, _("register value used as expression"));
4974 if (arg
->token
->type
== OT_INTEGER
)
4976 *value
= arg
->token
->u
.integer
.value
;
4977 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4983 (arg
->argnum
, _("operand %d must be an immediate expression"),
4988 /* Try to get a constant expression from the next tokens in ARG. Consume
4989 the tokens and return true on success, storing the constant value
4993 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4996 bfd_reloc_code_real_type r
[3];
4998 if (!match_expression (arg
, &ex
, r
))
5001 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5002 *value
= ex
.X_add_number
;
5005 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5006 match_out_of_range (arg
);
5008 match_not_constant (arg
);
5014 /* Return the RTYPE_* flags for a register operand of type TYPE that
5015 appears in instruction OPCODE. */
5018 convert_reg_type (const struct mips_opcode
*opcode
,
5019 enum mips_reg_operand_type type
)
5024 return RTYPE_NUM
| RTYPE_GP
;
5027 /* Allow vector register names for MDMX if the instruction is a 64-bit
5028 FPR load, store or move (including moves to and from GPRs). */
5029 if ((mips_opts
.ase
& ASE_MDMX
)
5030 && (opcode
->pinfo
& FP_D
)
5031 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5032 | INSN_COPROC_MEMORY_DELAY
5035 | INSN_STORE_MEMORY
)))
5036 return RTYPE_FPU
| RTYPE_VEC
;
5040 if (opcode
->pinfo
& (FP_D
| FP_S
))
5041 return RTYPE_CCC
| RTYPE_FCC
;
5045 if (opcode
->membership
& INSN_5400
)
5047 return RTYPE_FPU
| RTYPE_VEC
;
5053 case OP_REG_CONTROL
:
5054 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5055 return RTYPE_NUM
| RTYPE_CP0
;
5062 return RTYPE_NUM
| RTYPE_VI
;
5065 return RTYPE_NUM
| RTYPE_VF
;
5067 case OP_REG_R5900_I
:
5068 return RTYPE_R5900_I
;
5070 case OP_REG_R5900_Q
:
5071 return RTYPE_R5900_Q
;
5073 case OP_REG_R5900_R
:
5074 return RTYPE_R5900_R
;
5076 case OP_REG_R5900_ACC
:
5077 return RTYPE_R5900_ACC
;
5082 case OP_REG_MSA_CTRL
:
5088 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5091 check_regno (struct mips_arg_info
*arg
,
5092 enum mips_reg_operand_type type
, unsigned int regno
)
5094 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5095 arg
->seen_at
= true;
5097 if (type
== OP_REG_FP
5099 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5101 /* This was a warning prior to introducing O32 FPXX and FP64 support
5102 so maintain a warning for FP32 but raise an error for the new
5105 as_warn (_("float register should be even, was %d"), regno
);
5107 as_bad (_("float register should be even, was %d"), regno
);
5110 if (type
== OP_REG_CCC
)
5115 name
= arg
->insn
->insn_mo
->name
;
5116 length
= strlen (name
);
5117 if ((regno
& 1) != 0
5118 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5119 || (length
>= 5 && startswith (name
+ length
- 5, "any2"))))
5120 as_warn (_("condition code register should be even for %s, was %d"),
5123 if ((regno
& 3) != 0
5124 && (length
>= 5 && startswith (name
+ length
- 5, "any4")))
5125 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5130 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5131 a register of type TYPE. Return true on success, storing the register
5132 number in *REGNO and warning about any dubious uses. */
5135 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5136 unsigned int symval
, unsigned int *regno
)
5138 if (type
== OP_REG_VEC
)
5139 symval
= mips_prefer_vec_regno (symval
);
5140 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5143 *regno
= symval
& RNUM_MASK
;
5144 check_regno (arg
, type
, *regno
);
5148 /* Try to interpret the next token in ARG as a register of type TYPE.
5149 Consume the token and return true on success, storing the register
5150 number in *REGNO. Return false on failure. */
5153 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5154 unsigned int *regno
)
5156 if (arg
->token
->type
== OT_REG
5157 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5165 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5166 Consume the token and return true on success, storing the register numbers
5167 in *REGNO1 and *REGNO2. Return false on failure. */
5170 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5171 unsigned int *regno1
, unsigned int *regno2
)
5173 if (match_reg (arg
, type
, regno1
))
5178 if (arg
->token
->type
== OT_REG_RANGE
5179 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5180 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5181 && *regno1
<= *regno2
)
5189 /* OP_INT matcher. */
5192 match_int_operand (struct mips_arg_info
*arg
,
5193 const struct mips_operand
*operand_base
)
5195 const struct mips_int_operand
*operand
;
5197 int min_val
, max_val
, factor
;
5200 operand
= (const struct mips_int_operand
*) operand_base
;
5201 factor
= 1 << operand
->shift
;
5202 min_val
= mips_int_operand_min (operand
);
5203 max_val
= mips_int_operand_max (operand
);
5205 if (operand_base
->lsb
== 0
5206 && operand_base
->size
== 16
5207 && operand
->shift
== 0
5208 && operand
->bias
== 0
5209 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5211 /* The operand can be relocated. */
5212 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5215 if (offset_expr
.X_op
== O_big
)
5217 match_out_of_range (arg
);
5221 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5222 /* Relocation operators were used. Accept the argument and
5223 leave the relocation value in offset_expr and offset_relocs
5224 for the caller to process. */
5227 if (offset_expr
.X_op
!= O_constant
)
5229 /* Accept non-constant operands if no later alternative matches,
5230 leaving it for the caller to process. */
5231 if (!arg
->lax_match
)
5233 match_not_constant (arg
);
5236 offset_reloc
[0] = BFD_RELOC_LO16
;
5240 /* Clear the global state; we're going to install the operand
5242 sval
= offset_expr
.X_add_number
;
5243 offset_expr
.X_op
= O_absent
;
5245 /* For compatibility with older assemblers, we accept
5246 0x8000-0xffff as signed 16-bit numbers when only
5247 signed numbers are allowed. */
5250 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5251 if (!arg
->lax_match
&& sval
<= max_val
)
5253 match_out_of_range (arg
);
5260 if (!match_const_int (arg
, &sval
))
5264 arg
->last_op_int
= sval
;
5266 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5268 match_out_of_range (arg
);
5272 uval
= (unsigned int) sval
>> operand
->shift
;
5273 uval
-= operand
->bias
;
5275 /* Handle -mfix-cn63xxp1. */
5277 && mips_fix_cn63xxp1
5278 && !mips_opts
.micromips
5279 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5294 /* The rest must be changed to 28. */
5299 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5303 /* OP_MAPPED_INT matcher. */
5306 match_mapped_int_operand (struct mips_arg_info
*arg
,
5307 const struct mips_operand
*operand_base
)
5309 const struct mips_mapped_int_operand
*operand
;
5310 unsigned int uval
, num_vals
;
5313 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5314 if (!match_const_int (arg
, &sval
))
5317 num_vals
= 1 << operand_base
->size
;
5318 for (uval
= 0; uval
< num_vals
; uval
++)
5319 if (operand
->int_map
[uval
] == sval
)
5321 if (uval
== num_vals
)
5323 match_out_of_range (arg
);
5327 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5331 /* OP_MSB matcher. */
5334 match_msb_operand (struct mips_arg_info
*arg
,
5335 const struct mips_operand
*operand_base
)
5337 const struct mips_msb_operand
*operand
;
5338 int min_val
, max_val
, max_high
;
5339 offsetT size
, sval
, high
;
5341 operand
= (const struct mips_msb_operand
*) operand_base
;
5342 min_val
= operand
->bias
;
5343 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5344 max_high
= operand
->opsize
;
5346 if (!match_const_int (arg
, &size
))
5349 high
= size
+ arg
->last_op_int
;
5350 sval
= operand
->add_lsb
? high
: size
;
5352 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5354 match_out_of_range (arg
);
5357 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5361 /* OP_REG matcher. */
5364 match_reg_operand (struct mips_arg_info
*arg
,
5365 const struct mips_operand
*operand_base
)
5367 const struct mips_reg_operand
*operand
;
5368 unsigned int regno
, uval
, num_vals
;
5370 operand
= (const struct mips_reg_operand
*) operand_base
;
5371 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5374 if (operand
->reg_map
)
5376 num_vals
= 1 << operand
->root
.size
;
5377 for (uval
= 0; uval
< num_vals
; uval
++)
5378 if (operand
->reg_map
[uval
] == regno
)
5380 if (num_vals
== uval
)
5386 arg
->last_regno
= regno
;
5387 if (arg
->opnum
== 1)
5388 arg
->dest_regno
= regno
;
5389 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5393 /* OP_REG_PAIR matcher. */
5396 match_reg_pair_operand (struct mips_arg_info
*arg
,
5397 const struct mips_operand
*operand_base
)
5399 const struct mips_reg_pair_operand
*operand
;
5400 unsigned int regno1
, regno2
, uval
, num_vals
;
5402 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5403 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5404 || !match_char (arg
, ',')
5405 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5408 num_vals
= 1 << operand_base
->size
;
5409 for (uval
= 0; uval
< num_vals
; uval
++)
5410 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5412 if (uval
== num_vals
)
5415 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5419 /* OP_PCREL matcher. The caller chooses the relocation type. */
5422 match_pcrel_operand (struct mips_arg_info
*arg
)
5424 bfd_reloc_code_real_type r
[3];
5426 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5429 /* OP_PERF_REG matcher. */
5432 match_perf_reg_operand (struct mips_arg_info
*arg
,
5433 const struct mips_operand
*operand
)
5437 if (!match_const_int (arg
, &sval
))
5442 || (mips_opts
.arch
== CPU_R5900
5443 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5444 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5446 set_insn_error (arg
->argnum
, _("invalid performance register"));
5450 insn_insert_operand (arg
->insn
, operand
, sval
);
5454 /* OP_ADDIUSP matcher. */
5457 match_addiusp_operand (struct mips_arg_info
*arg
,
5458 const struct mips_operand
*operand
)
5463 if (!match_const_int (arg
, &sval
))
5468 match_out_of_range (arg
);
5473 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5475 match_out_of_range (arg
);
5479 uval
= (unsigned int) sval
;
5480 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5481 insn_insert_operand (arg
->insn
, operand
, uval
);
5485 /* OP_CLO_CLZ_DEST matcher. */
5488 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5489 const struct mips_operand
*operand
)
5493 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5496 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5500 /* OP_CHECK_PREV matcher. */
5503 match_check_prev_operand (struct mips_arg_info
*arg
,
5504 const struct mips_operand
*operand_base
)
5506 const struct mips_check_prev_operand
*operand
;
5509 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5511 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5514 if (!operand
->zero_ok
&& regno
== 0)
5517 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5518 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5519 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5521 arg
->last_regno
= regno
;
5522 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5529 /* OP_SAME_RS_RT matcher. */
5532 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5533 const struct mips_operand
*operand
)
5537 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5542 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5546 arg
->last_regno
= regno
;
5548 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5552 /* OP_LWM_SWM_LIST matcher. */
5555 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5556 const struct mips_operand
*operand
)
5558 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5559 struct mips_arg_info reset
;
5562 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5566 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5571 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5574 while (match_char (arg
, ',')
5575 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5578 if (operand
->size
== 2)
5580 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5586 and any permutations of these. */
5587 if ((reglist
& 0xfff1ffff) != 0x80010000)
5590 sregs
= (reglist
>> 17) & 7;
5595 /* The list must include at least one of ra and s0-sN,
5596 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5597 which are $23 and $30 respectively.) E.g.:
5605 and any permutations of these. */
5606 if ((reglist
& 0x3f00ffff) != 0)
5609 ra
= (reglist
>> 27) & 0x10;
5610 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5613 if ((sregs
& -sregs
) != sregs
)
5616 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5620 /* OP_ENTRY_EXIT_LIST matcher. */
5623 match_entry_exit_operand (struct mips_arg_info
*arg
,
5624 const struct mips_operand
*operand
)
5629 /* The format is the same for both ENTRY and EXIT, but the constraints
5631 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5632 mask
= (is_exit
? 7 << 3 : 0);
5635 unsigned int regno1
, regno2
;
5638 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5640 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5645 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5648 mask
|= (5 + regno2
) << 3;
5650 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5651 mask
|= (regno2
- 3) << 3;
5652 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5653 mask
|= (regno2
- 15) << 1;
5654 else if (regno1
== RA
&& regno2
== RA
)
5659 while (match_char (arg
, ','));
5661 insn_insert_operand (arg
->insn
, operand
, mask
);
5665 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5666 the argument register mask AMASK, the number of static registers
5667 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5668 respectively, and the frame size FRAME_SIZE. */
5671 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5672 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5673 unsigned int frame_size
)
5675 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5676 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5679 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5680 argument register mask AMASK, the number of static registers saved
5681 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5682 respectively, and the frame size FRAME_SIZE. */
5685 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5686 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5687 unsigned int frame_size
)
5691 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5692 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5693 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5694 | ((frame_size
& 0xf0) << 16));
5698 /* OP_SAVE_RESTORE_LIST matcher. */
5701 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5703 unsigned int opcode
, args
, statics
, sregs
;
5704 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5705 unsigned int arg_mask
, ra
, s0
, s1
;
5708 opcode
= arg
->insn
->insn_opcode
;
5710 num_frame_sizes
= 0;
5719 unsigned int regno1
, regno2
;
5721 if (arg
->token
->type
== OT_INTEGER
)
5723 /* Handle the frame size. */
5724 if (!match_const_int (arg
, &frame_size
))
5726 num_frame_sizes
+= 1;
5730 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5733 while (regno1
<= regno2
)
5735 if (regno1
>= 4 && regno1
<= 7)
5737 if (num_frame_sizes
== 0)
5739 args
|= 1 << (regno1
- 4);
5741 /* statics $a0-$a3 */
5742 statics
|= 1 << (regno1
- 4);
5744 else if (regno1
>= 16 && regno1
<= 23)
5746 sregs
|= 1 << (regno1
- 16);
5747 else if (regno1
== 30)
5750 else if (regno1
== 31)
5751 /* Add $ra to insn. */
5761 while (match_char (arg
, ','));
5763 /* Encode args/statics combination. */
5766 else if (args
== 0xf)
5767 /* All $a0-$a3 are args. */
5768 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5769 else if (statics
== 0xf)
5770 /* All $a0-$a3 are statics. */
5771 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5774 /* Count arg registers. */
5784 /* Count static registers. */
5786 while (statics
& 0x8)
5788 statics
= (statics
<< 1) & 0xf;
5794 /* Encode args/statics. */
5795 arg_mask
= (num_args
<< 2) | num_statics
;
5798 /* Encode $s0/$s1. */
5799 if (sregs
& (1 << 0)) /* $s0 */
5801 if (sregs
& (1 << 1)) /* $s1 */
5805 /* Encode $s2-$s8. */
5815 /* Encode frame size. */
5816 if (num_frame_sizes
== 0)
5818 set_insn_error (arg
->argnum
, _("missing frame size"));
5821 if (num_frame_sizes
> 1)
5823 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5826 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5828 set_insn_error (arg
->argnum
, _("invalid frame size"));
5833 /* Finally build the instruction. */
5834 if (mips_opts
.mips16
)
5835 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5837 else if (!mips_opts
.micromips
)
5838 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5843 arg
->insn
->insn_opcode
= opcode
;
5847 /* OP_MDMX_IMM_REG matcher. */
5850 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5851 const struct mips_operand
*operand
)
5853 unsigned int regno
, uval
;
5855 const struct mips_opcode
*opcode
;
5857 /* The mips_opcode records whether this is an octobyte or quadhalf
5858 instruction. Start out with that bit in place. */
5859 opcode
= arg
->insn
->insn_mo
;
5860 uval
= mips_extract_operand (operand
, opcode
->match
);
5861 is_qh
= (uval
!= 0);
5863 if (arg
->token
->type
== OT_REG
)
5865 if ((opcode
->membership
& INSN_5400
)
5866 && strcmp (opcode
->name
, "rzu.ob") == 0)
5868 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5873 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5877 /* Check whether this is a vector register or a broadcast of
5878 a single element. */
5879 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5881 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5883 set_insn_error (arg
->argnum
, _("invalid element selector"));
5886 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5891 /* A full vector. */
5892 if ((opcode
->membership
& INSN_5400
)
5893 && (strcmp (opcode
->name
, "sll.ob") == 0
5894 || strcmp (opcode
->name
, "srl.ob") == 0))
5896 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5902 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5904 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5912 if (!match_const_int (arg
, &sval
))
5914 if (sval
< 0 || sval
> 31)
5916 match_out_of_range (arg
);
5919 uval
|= (sval
& 31);
5921 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5923 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5925 insn_insert_operand (arg
->insn
, operand
, uval
);
5929 /* OP_IMM_INDEX matcher. */
5932 match_imm_index_operand (struct mips_arg_info
*arg
,
5933 const struct mips_operand
*operand
)
5935 unsigned int max_val
;
5937 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5940 max_val
= (1 << operand
->size
) - 1;
5941 if (arg
->token
->u
.index
> max_val
)
5943 match_out_of_range (arg
);
5946 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5951 /* OP_REG_INDEX matcher. */
5954 match_reg_index_operand (struct mips_arg_info
*arg
,
5955 const struct mips_operand
*operand
)
5959 if (arg
->token
->type
!= OT_REG_INDEX
)
5962 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5965 insn_insert_operand (arg
->insn
, operand
, regno
);
5970 /* OP_PC matcher. */
5973 match_pc_operand (struct mips_arg_info
*arg
)
5975 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5983 /* OP_REG28 matcher. */
5986 match_reg28_operand (struct mips_arg_info
*arg
)
5990 if (arg
->token
->type
== OT_REG
5991 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
6000 /* OP_NON_ZERO_REG matcher. */
6003 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6004 const struct mips_operand
*operand
)
6008 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6013 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6017 arg
->last_regno
= regno
;
6018 insn_insert_operand (arg
->insn
, operand
, regno
);
6022 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6023 register that we need to match. */
6026 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6030 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6033 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6034 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6035 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6037 Return the constant in IMM and OFFSET as follows:
6039 - If the constant should be loaded via memory, set IMM to O_absent and
6040 OFFSET to the memory address.
6042 - Otherwise, if the constant should be loaded into two 32-bit registers,
6043 set IMM to the O_constant to load into the high register and OFFSET
6044 to the corresponding value for the low register.
6046 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6048 These constants only appear as the last operand in an instruction,
6049 and every instruction that accepts them in any variant accepts them
6050 in all variants. This means we don't have to worry about backing out
6051 any changes if the instruction does not match. We just match
6052 unconditionally and report an error if the constant is invalid. */
6055 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6056 expressionS
*offset
, int length
, bool using_gprs
)
6061 const char *newname
;
6062 unsigned char *data
;
6064 /* Where the constant is placed is based on how the MIPS assembler
6067 length == 4 && using_gprs -- immediate value only
6068 length == 8 && using_gprs -- .rdata or immediate value
6069 length == 4 && !using_gprs -- .lit4 or immediate value
6070 length == 8 && !using_gprs -- .lit8 or immediate value
6072 The .lit4 and .lit8 sections are only used if permitted by the
6074 if (arg
->token
->type
!= OT_FLOAT
)
6076 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6080 gas_assert (arg
->token
->u
.flt
.length
== length
);
6081 data
= arg
->token
->u
.flt
.data
;
6084 /* Handle 32-bit constants for which an immediate value is best. */
6087 || g_switch_value
< 4
6088 || (data
[0] == 0 && data
[1] == 0)
6089 || (data
[2] == 0 && data
[3] == 0)))
6091 imm
->X_op
= O_constant
;
6092 if (!target_big_endian
)
6093 imm
->X_add_number
= bfd_getl32 (data
);
6095 imm
->X_add_number
= bfd_getb32 (data
);
6096 offset
->X_op
= O_absent
;
6100 /* Handle 64-bit constants for which an immediate value is best. */
6102 && !mips_disable_float_construction
6103 /* Constants can only be constructed in GPRs and copied to FPRs if the
6104 GPRs are at least as wide as the FPRs or MTHC1 is available.
6105 Unlike most tests for 32-bit floating-point registers this check
6106 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6107 permit 64-bit moves without MXHC1.
6108 Force the constant into memory otherwise. */
6111 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6113 && ((data
[0] == 0 && data
[1] == 0)
6114 || (data
[2] == 0 && data
[3] == 0))
6115 && ((data
[4] == 0 && data
[5] == 0)
6116 || (data
[6] == 0 && data
[7] == 0)))
6118 /* The value is simple enough to load with a couple of instructions.
6119 If using 32-bit registers, set IMM to the high order 32 bits and
6120 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6122 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6124 imm
->X_op
= O_constant
;
6125 offset
->X_op
= O_constant
;
6126 if (!target_big_endian
)
6128 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6129 offset
->X_add_number
= bfd_getl32 (data
);
6133 imm
->X_add_number
= bfd_getb32 (data
);
6134 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6136 if (offset
->X_add_number
== 0)
6137 offset
->X_op
= O_absent
;
6141 imm
->X_op
= O_constant
;
6142 if (!target_big_endian
)
6143 imm
->X_add_number
= bfd_getl64 (data
);
6145 imm
->X_add_number
= bfd_getb64 (data
);
6146 offset
->X_op
= O_absent
;
6151 /* Switch to the right section. */
6153 subseg
= now_subseg
;
6156 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6161 if (using_gprs
|| g_switch_value
< 8)
6162 newname
= RDATA_SECTION_NAME
;
6167 new_seg
= subseg_new (newname
, (subsegT
) 0);
6168 bfd_set_section_flags (new_seg
,
6169 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6170 frag_align (length
== 4 ? 2 : 3, 0, 0);
6171 if (!startswith (TARGET_OS
, "elf"))
6172 record_alignment (new_seg
, 4);
6174 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6176 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6178 /* Set the argument to the current address in the section. */
6179 imm
->X_op
= O_absent
;
6180 offset
->X_op
= O_symbol
;
6181 offset
->X_add_symbol
= symbol_temp_new_now ();
6182 offset
->X_add_number
= 0;
6184 /* Put the floating point number into the section. */
6185 p
= frag_more (length
);
6186 memcpy (p
, data
, length
);
6188 /* Switch back to the original section. */
6189 subseg_set (seg
, subseg
);
6193 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6197 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6198 const struct mips_operand
*operand
,
6203 /* The operand can be an XYZW mask or a single 2-bit channel index
6204 (with X being 0). */
6205 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6207 /* The suffix can be omitted when it is already part of the opcode. */
6208 if (arg
->token
->type
!= OT_CHANNELS
)
6211 uval
= arg
->token
->u
.channels
;
6212 if (operand
->size
== 2)
6214 /* Check that a single bit is set and convert it into a 2-bit index. */
6215 if ((uval
& -uval
) != uval
)
6217 uval
= 4 - ffs (uval
);
6220 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6225 insn_insert_operand (arg
->insn
, operand
, uval
);
6229 /* Try to match a token from ARG against OPERAND. Consume the token
6230 and return true on success, otherwise return false. */
6233 match_operand (struct mips_arg_info
*arg
,
6234 const struct mips_operand
*operand
)
6236 switch (operand
->type
)
6239 return match_int_operand (arg
, operand
);
6242 return match_mapped_int_operand (arg
, operand
);
6245 return match_msb_operand (arg
, operand
);
6248 case OP_OPTIONAL_REG
:
6249 return match_reg_operand (arg
, operand
);
6252 return match_reg_pair_operand (arg
, operand
);
6255 return match_pcrel_operand (arg
);
6258 return match_perf_reg_operand (arg
, operand
);
6260 case OP_ADDIUSP_INT
:
6261 return match_addiusp_operand (arg
, operand
);
6263 case OP_CLO_CLZ_DEST
:
6264 return match_clo_clz_dest_operand (arg
, operand
);
6266 case OP_LWM_SWM_LIST
:
6267 return match_lwm_swm_list_operand (arg
, operand
);
6269 case OP_ENTRY_EXIT_LIST
:
6270 return match_entry_exit_operand (arg
, operand
);
6272 case OP_SAVE_RESTORE_LIST
:
6273 return match_save_restore_list_operand (arg
);
6275 case OP_MDMX_IMM_REG
:
6276 return match_mdmx_imm_reg_operand (arg
, operand
);
6278 case OP_REPEAT_DEST_REG
:
6279 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6281 case OP_REPEAT_PREV_REG
:
6282 return match_tied_reg_operand (arg
, arg
->last_regno
);
6285 return match_pc_operand (arg
);
6288 return match_reg28_operand (arg
);
6291 return match_vu0_suffix_operand (arg
, operand
, false);
6293 case OP_VU0_MATCH_SUFFIX
:
6294 return match_vu0_suffix_operand (arg
, operand
, true);
6297 return match_imm_index_operand (arg
, operand
);
6300 return match_reg_index_operand (arg
, operand
);
6303 return match_same_rs_rt_operand (arg
, operand
);
6306 return match_check_prev_operand (arg
, operand
);
6308 case OP_NON_ZERO_REG
:
6309 return match_non_zero_reg_operand (arg
, operand
);
6314 /* ARG is the state after successfully matching an instruction.
6315 Issue any queued-up warnings. */
6318 check_completed_insn (struct mips_arg_info
*arg
)
6323 as_warn (_("used $at without \".set noat\""));
6325 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6329 /* Return true if modifying general-purpose register REG needs a delay. */
6332 reg_needs_delay (unsigned int reg
)
6334 unsigned long prev_pinfo
;
6336 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6337 if (!mips_opts
.noreorder
6338 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6339 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6340 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6346 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6347 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6348 by VR4120 errata. */
6351 classify_vr4120_insn (const char *name
)
6353 if (startswith (name
, "macc"))
6354 return FIX_VR4120_MACC
;
6355 if (startswith (name
, "dmacc"))
6356 return FIX_VR4120_DMACC
;
6357 if (startswith (name
, "mult"))
6358 return FIX_VR4120_MULT
;
6359 if (startswith (name
, "dmult"))
6360 return FIX_VR4120_DMULT
;
6361 if (strstr (name
, "div"))
6362 return FIX_VR4120_DIV
;
6363 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6364 return FIX_VR4120_MTHILO
;
6365 return NUM_FIX_VR4120_CLASSES
;
6368 #define INSN_ERET 0x42000018
6369 #define INSN_DERET 0x4200001f
6370 #define INSN_DMULT 0x1c
6371 #define INSN_DMULTU 0x1d
6373 /* Return the number of instructions that must separate INSN1 and INSN2,
6374 where INSN1 is the earlier instruction. Return the worst-case value
6375 for any INSN2 if INSN2 is null. */
6378 insns_between (const struct mips_cl_insn
*insn1
,
6379 const struct mips_cl_insn
*insn2
)
6381 unsigned long pinfo1
, pinfo2
;
6384 /* If INFO2 is null, pessimistically assume that all flags are set for
6385 the second instruction. */
6386 pinfo1
= insn1
->insn_mo
->pinfo
;
6387 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6389 /* For most targets, write-after-read dependencies on the HI and LO
6390 registers must be separated by at least two instructions. */
6391 if (!hilo_interlocks
)
6393 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6395 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6399 /* If we're working around r7000 errata, there must be two instructions
6400 between an mfhi or mflo and any instruction that uses the result. */
6401 if (mips_7000_hilo_fix
6402 && !mips_opts
.micromips
6403 && MF_HILO_INSN (pinfo1
)
6404 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6407 /* If we're working around 24K errata, one instruction is required
6408 if an ERET or DERET is followed by a branch instruction. */
6409 if (mips_fix_24k
&& !mips_opts
.micromips
)
6411 if (insn1
->insn_opcode
== INSN_ERET
6412 || insn1
->insn_opcode
== INSN_DERET
)
6415 || insn2
->insn_opcode
== INSN_ERET
6416 || insn2
->insn_opcode
== INSN_DERET
6417 || delayed_branch_p (insn2
))
6422 /* If we're working around PMC RM7000 errata, there must be three
6423 nops between a dmult and a load instruction. */
6424 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6426 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6427 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6429 if (pinfo2
& INSN_LOAD_MEMORY
)
6434 /* If working around VR4120 errata, check for combinations that need
6435 a single intervening instruction. */
6436 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6438 unsigned int class1
, class2
;
6440 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6441 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6445 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6446 if (vr4120_conflicts
[class1
] & (1 << class2
))
6451 if (!HAVE_CODE_COMPRESSION
)
6453 /* Check for GPR or coprocessor load delays. All such delays
6454 are on the RT register. */
6455 /* Itbl support may require additional care here. */
6456 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6457 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6459 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6463 /* Check for generic coprocessor hazards.
6465 This case is not handled very well. There is no special
6466 knowledge of CP0 handling, and the coprocessors other than
6467 the floating point unit are not distinguished at all. */
6468 /* Itbl support may require additional care here. FIXME!
6469 Need to modify this to include knowledge about
6470 user specified delays! */
6471 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6472 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6474 /* Handle cases where INSN1 writes to a known general coprocessor
6475 register. There must be a one instruction delay before INSN2
6476 if INSN2 reads that register, otherwise no delay is needed. */
6477 mask
= fpr_write_mask (insn1
);
6480 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6485 /* Read-after-write dependencies on the control registers
6486 require a two-instruction gap. */
6487 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6488 && (pinfo2
& INSN_READ_COND_CODE
))
6491 /* We don't know exactly what INSN1 does. If INSN2 is
6492 also a coprocessor instruction, assume there must be
6493 a one instruction gap. */
6494 if (pinfo2
& INSN_COP
)
6499 /* Check for read-after-write dependencies on the coprocessor
6500 control registers in cases where INSN1 does not need a general
6501 coprocessor delay. This means that INSN1 is a floating point
6502 comparison instruction. */
6503 /* Itbl support may require additional care here. */
6504 else if (!cop_interlocks
6505 && (pinfo1
& INSN_WRITE_COND_CODE
)
6506 && (pinfo2
& INSN_READ_COND_CODE
))
6510 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6511 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6513 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6514 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6515 || (insn2
&& delayed_branch_p (insn2
))))
6521 /* Return the number of nops that would be needed to work around the
6522 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6523 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6524 that are contained within the first IGNORE instructions of HIST. */
6527 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6528 const struct mips_cl_insn
*insn
)
6533 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6534 are not affected by the errata. */
6536 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6537 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6538 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6541 /* Search for the first MFLO or MFHI. */
6542 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6543 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6545 /* Extract the destination register. */
6546 mask
= gpr_write_mask (&hist
[i
]);
6548 /* No nops are needed if INSN reads that register. */
6549 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6552 /* ...or if any of the intervening instructions do. */
6553 for (j
= 0; j
< i
; j
++)
6554 if (gpr_read_mask (&hist
[j
]) & mask
)
6558 return MAX_VR4130_NOPS
- i
;
6563 #define BASE_REG_EQ(INSN1, INSN2) \
6564 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6565 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6567 /* Return the minimum alignment for this store instruction. */
6570 fix_24k_align_to (const struct mips_opcode
*mo
)
6572 if (strcmp (mo
->name
, "sh") == 0)
6575 if (strcmp (mo
->name
, "swc1") == 0
6576 || strcmp (mo
->name
, "swc2") == 0
6577 || strcmp (mo
->name
, "sw") == 0
6578 || strcmp (mo
->name
, "sc") == 0
6579 || strcmp (mo
->name
, "s.s") == 0)
6582 if (strcmp (mo
->name
, "sdc1") == 0
6583 || strcmp (mo
->name
, "sdc2") == 0
6584 || strcmp (mo
->name
, "s.d") == 0)
6591 struct fix_24k_store_info
6593 /* Immediate offset, if any, for this store instruction. */
6595 /* Alignment required by this store instruction. */
6597 /* True for register offsets. */
6598 int register_offset
;
6601 /* Comparison function used by qsort. */
6604 fix_24k_sort (const void *a
, const void *b
)
6606 const struct fix_24k_store_info
*pos1
= a
;
6607 const struct fix_24k_store_info
*pos2
= b
;
6609 return (pos1
->off
- pos2
->off
);
6612 /* INSN is a store instruction. Try to record the store information
6613 in STINFO. Return false if the information isn't known. */
6616 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6617 const struct mips_cl_insn
*insn
)
6619 /* The instruction must have a known offset. */
6620 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6623 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6624 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6628 /* Return the number of nops that would be needed to work around the 24k
6629 "lost data on stores during refill" errata if instruction INSN
6630 immediately followed the 2 instructions described by HIST.
6631 Ignore hazards that are contained within the first IGNORE
6632 instructions of HIST.
6634 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6635 for the data cache refills and store data. The following describes
6636 the scenario where the store data could be lost.
6638 * A data cache miss, due to either a load or a store, causing fill
6639 data to be supplied by the memory subsystem
6640 * The first three doublewords of fill data are returned and written
6642 * A sequence of four stores occurs in consecutive cycles around the
6643 final doubleword of the fill:
6647 * Zero, One or more instructions
6650 The four stores A-D must be to different doublewords of the line that
6651 is being filled. The fourth instruction in the sequence above permits
6652 the fill of the final doubleword to be transferred from the FSB into
6653 the cache. In the sequence above, the stores may be either integer
6654 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6655 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6656 different doublewords on the line. If the floating point unit is
6657 running in 1:2 mode, it is not possible to create the sequence above
6658 using only floating point store instructions.
6660 In this case, the cache line being filled is incorrectly marked
6661 invalid, thereby losing the data from any store to the line that
6662 occurs between the original miss and the completion of the five
6663 cycle sequence shown above.
6665 The workarounds are:
6667 * Run the data cache in write-through mode.
6668 * Insert a non-store instruction between
6669 Store A and Store B or Store B and Store C. */
6672 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6673 const struct mips_cl_insn
*insn
)
6675 struct fix_24k_store_info pos
[3];
6676 int align
, i
, base_offset
;
6681 /* If the previous instruction wasn't a store, there's nothing to
6683 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6686 /* If the instructions after the previous one are unknown, we have
6687 to assume the worst. */
6691 /* Check whether we are dealing with three consecutive stores. */
6692 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6693 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6696 /* If we don't know the relationship between the store addresses,
6697 assume the worst. */
6698 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6699 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6702 if (!fix_24k_record_store_info (&pos
[0], insn
)
6703 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6704 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6707 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6709 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6710 X bytes and such that the base register + X is known to be aligned
6713 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6717 align
= pos
[0].align_to
;
6718 base_offset
= pos
[0].off
;
6719 for (i
= 1; i
< 3; i
++)
6720 if (align
< pos
[i
].align_to
)
6722 align
= pos
[i
].align_to
;
6723 base_offset
= pos
[i
].off
;
6725 for (i
= 0; i
< 3; i
++)
6726 pos
[i
].off
-= base_offset
;
6729 pos
[0].off
&= ~align
+ 1;
6730 pos
[1].off
&= ~align
+ 1;
6731 pos
[2].off
&= ~align
+ 1;
6733 /* If any two stores write to the same chunk, they also write to the
6734 same doubleword. The offsets are still sorted at this point. */
6735 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6738 /* A range of at least 9 bytes is needed for the stores to be in
6739 non-overlapping doublewords. */
6740 if (pos
[2].off
- pos
[0].off
<= 8)
6743 if (pos
[2].off
- pos
[1].off
>= 24
6744 || pos
[1].off
- pos
[0].off
>= 24
6745 || pos
[2].off
- pos
[0].off
>= 32)
6751 /* Return the number of nops that would be needed if instruction INSN
6752 immediately followed the MAX_NOPS instructions given by HIST,
6753 where HIST[0] is the most recent instruction. Ignore hazards
6754 between INSN and the first IGNORE instructions in HIST.
6756 If INSN is null, return the worse-case number of nops for any
6760 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6761 const struct mips_cl_insn
*insn
)
6763 int i
, nops
, tmp_nops
;
6766 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6768 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6769 if (tmp_nops
> nops
)
6773 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6775 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6776 if (tmp_nops
> nops
)
6780 if (mips_fix_24k
&& !mips_opts
.micromips
)
6782 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6783 if (tmp_nops
> nops
)
6790 /* The variable arguments provide NUM_INSNS extra instructions that
6791 might be added to HIST. Return the largest number of nops that
6792 would be needed after the extended sequence, ignoring hazards
6793 in the first IGNORE instructions. */
6796 nops_for_sequence (int num_insns
, int ignore
,
6797 const struct mips_cl_insn
*hist
, ...)
6800 struct mips_cl_insn buffer
[MAX_NOPS
];
6801 struct mips_cl_insn
*cursor
;
6804 va_start (args
, hist
);
6805 cursor
= buffer
+ num_insns
;
6806 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6807 while (cursor
> buffer
)
6808 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6810 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6815 /* Like nops_for_insn, but if INSN is a branch, take into account the
6816 worst-case delay for the branch target. */
6819 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6820 const struct mips_cl_insn
*insn
)
6824 nops
= nops_for_insn (ignore
, hist
, insn
);
6825 if (delayed_branch_p (insn
))
6827 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6828 hist
, insn
, get_delay_slot_nop (insn
));
6829 if (tmp_nops
> nops
)
6832 else if (compact_branch_p (insn
))
6834 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6835 if (tmp_nops
> nops
)
6841 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6844 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6846 gas_assert (!HAVE_CODE_COMPRESSION
);
6847 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6848 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6851 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6852 jr target pc &= 'hffff_ffff_cfff_ffff. */
6855 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6857 gas_assert (!HAVE_CODE_COMPRESSION
);
6858 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6859 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6860 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6868 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6869 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6872 ep
.X_op
= O_constant
;
6873 ep
.X_add_number
= 0xcfff0000;
6874 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6875 ep
.X_add_number
= 0xffff;
6876 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6877 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6882 fix_loongson2f (struct mips_cl_insn
* ip
)
6884 if (mips_fix_loongson2f_nop
)
6885 fix_loongson2f_nop (ip
);
6887 if (mips_fix_loongson2f_jump
)
6888 fix_loongson2f_jump (ip
);
6892 has_label_name (const char *arr
[], size_t len
,const char *s
)
6895 for (i
= 0; i
< len
; i
++)
6899 if (streq (arr
[i
], s
))
6905 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6908 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6910 gas_assert (!HAVE_CODE_COMPRESSION
);
6912 /* If is an local label and the insn is not sync,
6913 look forward that whether an branch between ll/sc jump to here
6914 if so, insert a sync. */
6915 if (seg_info (now_seg
)->label_list
6916 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6917 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6921 const char *label_names
[MAX_LABELS_SAME
];
6922 const char *label_name
;
6924 label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6925 label_names
[0] = label_name
;
6926 struct insn_label_list
*llist
= seg_info (now_seg
)->label_list
;
6927 label_value
= S_GET_VALUE (llist
->label
);
6929 for (i
= 1; i
< MAX_LABELS_SAME
; i
++)
6931 llist
= llist
->next
;
6934 if (S_GET_VALUE (llist
->label
) == label_value
)
6935 label_names
[i
] = S_GET_NAME (llist
->label
);
6939 for (; i
< MAX_LABELS_SAME
; i
++)
6940 label_names
[i
] = NULL
;
6942 unsigned long lookback
= ARRAY_SIZE (history
);
6943 for (i
= 0; i
< lookback
; i
++)
6945 if (streq (history
[i
].insn_mo
->name
, "ll")
6946 || streq (history
[i
].insn_mo
->name
, "lld"))
6949 if (streq (history
[i
].insn_mo
->name
, "sc")
6950 || streq (history
[i
].insn_mo
->name
, "scd"))
6954 for (j
= i
+ 1; j
< lookback
; j
++)
6956 if (streq (history
[i
].insn_mo
->name
, "ll")
6957 || streq (history
[i
].insn_mo
->name
, "lld"))
6960 if (delayed_branch_p (&history
[j
]))
6962 if (has_label_name (label_names
,
6966 add_fixed_insn (&sync_insn
);
6967 insert_into_history (0, 1, &sync_insn
);
6976 /* If we find a sc, we look forward to look for an branch insn,
6977 and see whether it jump back and out of ll/sc. */
6978 else if (streq (ip
->insn_mo
->name
, "sc") || streq (ip
->insn_mo
->name
, "scd"))
6980 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6983 for (i
= 0; i
< lookback
; i
++)
6985 if (streq (history
[i
].insn_mo
->name
, "ll")
6986 || streq (history
[i
].insn_mo
->name
, "lld"))
6989 if (delayed_branch_p (&history
[i
]))
6993 for (j
= i
+ 1; j
< lookback
; j
++)
6995 if (streq (history
[j
].insn_mo
->name
, "ll")
6996 || streq (history
[i
].insn_mo
->name
, "lld"))
7000 for (; j
< lookback
; j
++)
7002 if (history
[j
].label
[0] != '\0'
7003 && streq (history
[j
].label
, history
[i
].target
)
7004 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
7006 add_fixed_insn (&sync_insn
);
7007 insert_into_history (++j
, 1, &sync_insn
);
7014 /* Skip if there is a sync before ll/lld. */
7015 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
7016 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
7017 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
7019 add_fixed_insn (&sync_insn
);
7020 insert_into_history (0, 1, &sync_insn
);
7024 /* IP is a branch that has a delay slot, and we need to fill it
7025 automatically. Return true if we can do that by swapping IP
7026 with the previous instruction.
7027 ADDRESS_EXPR is an operand of the instruction to be used with
7031 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7032 bfd_reloc_code_real_type
*reloc_type
)
7034 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7035 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7036 unsigned int fpr_read
, prev_fpr_write
;
7038 /* -O2 and above is required for this optimization. */
7039 if (mips_optimize
< 2)
7042 /* If we have seen .set volatile or .set nomove, don't optimize. */
7043 if (mips_opts
.nomove
)
7046 /* We can't swap if the previous instruction's position is fixed. */
7047 if (history
[0].fixed_p
)
7050 /* If the previous previous insn was in a .set noreorder, we can't
7051 swap. Actually, the MIPS assembler will swap in this situation.
7052 However, gcc configured -with-gnu-as will generate code like
7060 in which we can not swap the bne and INSN. If gcc is not configured
7061 -with-gnu-as, it does not output the .set pseudo-ops. */
7062 if (history
[1].noreorder_p
)
7065 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7066 This means that the previous instruction was a 4-byte one anyhow. */
7067 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7070 /* If the branch is itself the target of a branch, we can not swap.
7071 We cheat on this; all we check for is whether there is a label on
7072 this instruction. If there are any branches to anything other than
7073 a label, users must use .set noreorder. */
7074 if (seg_info (now_seg
)->label_list
)
7077 /* If the previous instruction is in a variant frag other than this
7078 branch's one, we cannot do the swap. This does not apply to
7079 MIPS16 code, which uses variant frags for different purposes. */
7080 if (!mips_opts
.mips16
7082 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7085 /* We do not swap with instructions that cannot architecturally
7086 be placed in a branch delay slot, such as SYNC or ERET. We
7087 also refrain from swapping with a trap instruction, since it
7088 complicates trap handlers to have the trap instruction be in
7090 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7091 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7094 /* Check for conflicts between the branch and the instructions
7095 before the candidate delay slot. */
7096 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7099 /* Check for conflicts between the swapped sequence and the
7100 target of the branch. */
7101 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7104 /* If the branch reads a register that the previous
7105 instruction sets, we can not swap. */
7106 gpr_read
= gpr_read_mask (ip
);
7107 prev_gpr_write
= gpr_write_mask (&history
[0]);
7108 if (gpr_read
& prev_gpr_write
)
7111 fpr_read
= fpr_read_mask (ip
);
7112 prev_fpr_write
= fpr_write_mask (&history
[0]);
7113 if (fpr_read
& prev_fpr_write
)
7116 /* If the branch writes a register that the previous
7117 instruction sets, we can not swap. */
7118 gpr_write
= gpr_write_mask (ip
);
7119 if (gpr_write
& prev_gpr_write
)
7122 /* If the branch writes a register that the previous
7123 instruction reads, we can not swap. */
7124 prev_gpr_read
= gpr_read_mask (&history
[0]);
7125 if (gpr_write
& prev_gpr_read
)
7128 /* If one instruction sets a condition code and the
7129 other one uses a condition code, we can not swap. */
7130 pinfo
= ip
->insn_mo
->pinfo
;
7131 if ((pinfo
& INSN_READ_COND_CODE
)
7132 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7134 if ((pinfo
& INSN_WRITE_COND_CODE
)
7135 && (prev_pinfo
& INSN_READ_COND_CODE
))
7138 /* If the previous instruction uses the PC, we can not swap. */
7139 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7140 if (prev_pinfo2
& INSN2_READ_PC
)
7143 /* If the previous instruction has an incorrect size for a fixed
7144 branch delay slot in microMIPS mode, we cannot swap. */
7145 pinfo2
= ip
->insn_mo
->pinfo2
;
7146 if (mips_opts
.micromips
7147 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7148 && insn_length (history
) != 2)
7150 if (mips_opts
.micromips
7151 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7152 && insn_length (history
) != 4)
7155 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7158 The short loop bug under certain conditions causes loops to execute
7159 only once or twice. We must ensure that the assembler never
7160 generates loops that satisfy all of the following conditions:
7162 - a loop consists of less than or equal to six instructions
7163 (including the branch delay slot);
7164 - a loop contains only one conditional branch instruction at the end
7166 - a loop does not contain any other branch or jump instructions;
7167 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7169 We need to do this because of a hardware bug in the R5900 chip. */
7171 /* Check if instruction has a parameter, ignore "j $31". */
7172 && (address_expr
!= NULL
)
7173 /* Parameter must be 16 bit. */
7174 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7175 /* Branch to same segment. */
7176 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7177 /* Branch to same code fragment. */
7178 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7179 /* Can only calculate branch offset if value is known. */
7180 && symbol_constant_p (address_expr
->X_add_symbol
)
7181 /* Check if branch is really conditional. */
7182 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7183 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7184 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7187 /* Check if loop is shorter than or equal to 6 instructions
7188 including branch and delay slot. */
7189 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7196 /* When the loop includes branches or jumps,
7197 it is not a short loop. */
7198 for (i
= 0; i
< (distance
/ 4); i
++)
7200 if ((history
[i
].cleared_p
)
7201 || delayed_branch_p (&history
[i
]))
7209 /* Insert nop after branch to fix short loop. */
7218 /* Decide how we should add IP to the instruction stream.
7219 ADDRESS_EXPR is an operand of the instruction to be used with
7222 static enum append_method
7223 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7224 bfd_reloc_code_real_type
*reloc_type
)
7226 /* The relaxed version of a macro sequence must be inherently
7228 if (mips_relax
.sequence
== 2)
7231 /* We must not dabble with instructions in a ".set noreorder" block. */
7232 if (mips_opts
.noreorder
)
7235 /* Otherwise, it's our responsibility to fill branch delay slots. */
7236 if (delayed_branch_p (ip
))
7238 if (!branch_likely_p (ip
)
7239 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7242 if (mips_opts
.mips16
7243 && ISA_SUPPORTS_MIPS16E
7244 && gpr_read_mask (ip
) != 0)
7245 return APPEND_ADD_COMPACT
;
7247 if (mips_opts
.micromips
7248 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7249 || (!forced_insn_length
7250 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7251 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7252 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7253 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7254 return APPEND_ADD_COMPACT
;
7256 return APPEND_ADD_WITH_NOP
;
7262 /* IP is an instruction whose opcode we have just changed, END points
7263 to the end of the opcode table processed. Point IP->insn_mo to the
7264 new opcode's definition. */
7267 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7269 const struct mips_opcode
*mo
;
7271 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7272 if (mo
->pinfo
!= INSN_MACRO
7273 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7281 /* IP is a MIPS16 instruction whose opcode we have just changed.
7282 Point IP->insn_mo to the new opcode's definition. */
7285 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7287 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7290 /* IP is a microMIPS instruction whose opcode we have just changed.
7291 Point IP->insn_mo to the new opcode's definition. */
7294 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7296 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7299 /* For microMIPS macros, we need to generate a local number label
7300 as the target of branches. */
7301 #define MICROMIPS_LABEL_CHAR '\037'
7302 static unsigned long micromips_target_label
;
7303 static char micromips_target_name
[32];
7306 micromips_label_name (void)
7308 char *p
= micromips_target_name
;
7309 char symbol_name_temporary
[24];
7317 l
= micromips_target_label
;
7318 #ifdef LOCAL_LABEL_PREFIX
7319 *p
++ = LOCAL_LABEL_PREFIX
;
7322 *p
++ = MICROMIPS_LABEL_CHAR
;
7325 symbol_name_temporary
[i
++] = l
% 10 + '0';
7330 *p
++ = symbol_name_temporary
[--i
];
7333 return micromips_target_name
;
7337 micromips_label_expr (expressionS
*label_expr
)
7339 label_expr
->X_op
= O_symbol
;
7340 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7341 label_expr
->X_add_number
= 0;
7345 micromips_label_inc (void)
7347 micromips_target_label
++;
7348 *micromips_target_name
= '\0';
7352 micromips_add_label (void)
7356 s
= colon (micromips_label_name ());
7357 micromips_label_inc ();
7358 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7361 /* If assembling microMIPS code, then return the microMIPS reloc
7362 corresponding to the requested one if any. Otherwise return
7363 the reloc unchanged. */
7365 static bfd_reloc_code_real_type
7366 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7368 static const bfd_reloc_code_real_type relocs
[][2] =
7370 /* Keep sorted incrementally by the left-hand key. */
7371 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7372 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7373 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7374 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7375 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7376 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7377 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7378 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7379 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7380 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7381 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7382 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7383 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7384 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7385 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7386 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7387 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7388 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7389 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7390 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7391 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7392 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7393 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7394 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7395 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7396 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7397 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7399 bfd_reloc_code_real_type r
;
7402 if (!mips_opts
.micromips
)
7404 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7410 return relocs
[i
][1];
7415 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7416 Return true on success, storing the resolved value in RESULT. */
7419 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7424 case BFD_RELOC_MIPS_HIGHEST
:
7425 case BFD_RELOC_MICROMIPS_HIGHEST
:
7426 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7429 case BFD_RELOC_MIPS_HIGHER
:
7430 case BFD_RELOC_MICROMIPS_HIGHER
:
7431 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7434 case BFD_RELOC_HI16_S
:
7435 case BFD_RELOC_HI16_S_PCREL
:
7436 case BFD_RELOC_MICROMIPS_HI16_S
:
7437 case BFD_RELOC_MIPS16_HI16_S
:
7438 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7441 case BFD_RELOC_HI16
:
7442 case BFD_RELOC_MICROMIPS_HI16
:
7443 case BFD_RELOC_MIPS16_HI16
:
7444 *result
= (operand
>> 16) & 0xffff;
7447 case BFD_RELOC_LO16
:
7448 case BFD_RELOC_LO16_PCREL
:
7449 case BFD_RELOC_MICROMIPS_LO16
:
7450 case BFD_RELOC_MIPS16_LO16
:
7451 *result
= operand
& 0xffff;
7454 case BFD_RELOC_UNUSED
:
7463 /* Output an instruction. IP is the instruction information.
7464 ADDRESS_EXPR is an operand of the instruction to be used with
7465 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7466 a macro expansion. */
7469 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7470 bfd_reloc_code_real_type
*reloc_type
, bool expansionp
)
7472 unsigned long prev_pinfo2
, pinfo
;
7473 bool relaxed_branch
= false;
7474 enum append_method method
;
7478 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7479 fix_loongson2f (ip
);
7481 ip
->target
[0] = '\0';
7482 if (offset_expr
.X_op
== O_symbol
)
7483 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7484 ip
->label
[0] = '\0';
7485 if (seg_info (now_seg
)->label_list
)
7486 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7487 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7488 fix_loongson3_llsc (ip
);
7490 file_ase_mips16
|= mips_opts
.mips16
;
7491 file_ase_micromips
|= mips_opts
.micromips
;
7493 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7494 pinfo
= ip
->insn_mo
->pinfo
;
7496 /* Don't raise alarm about `nods' frags as they'll fill in the right
7497 kind of nop in relaxation if required. */
7498 if (mips_opts
.micromips
7500 && !(history
[0].frag
7501 && history
[0].frag
->fr_type
== rs_machine_dependent
7502 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7503 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7504 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7505 && micromips_insn_length (ip
->insn_mo
) != 2)
7506 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7507 && micromips_insn_length (ip
->insn_mo
) != 4)))
7508 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7509 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7511 if (address_expr
== NULL
)
7513 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7514 && reloc_type
[1] == BFD_RELOC_UNUSED
7515 && reloc_type
[2] == BFD_RELOC_UNUSED
7516 && address_expr
->X_op
== O_constant
)
7518 switch (*reloc_type
)
7520 case BFD_RELOC_MIPS_JMP
:
7524 /* Shift is 2, unusually, for microMIPS JALX. */
7525 shift
= (mips_opts
.micromips
7526 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7527 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7528 as_bad (_("jump to misaligned address (0x%lx)"),
7529 (unsigned long) address_expr
->X_add_number
);
7530 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7536 case BFD_RELOC_MIPS16_JMP
:
7537 if ((address_expr
->X_add_number
& 3) != 0)
7538 as_bad (_("jump to misaligned address (0x%lx)"),
7539 (unsigned long) address_expr
->X_add_number
);
7541 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7542 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7543 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7547 case BFD_RELOC_16_PCREL_S2
:
7551 shift
= mips_opts
.micromips
? 1 : 2;
7552 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7553 as_bad (_("branch to misaligned address (0x%lx)"),
7554 (unsigned long) address_expr
->X_add_number
);
7555 if (!mips_relax_branch
)
7557 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7558 & ~((1 << (shift
+ 16)) - 1))
7559 as_bad (_("branch address range overflow (0x%lx)"),
7560 (unsigned long) address_expr
->X_add_number
);
7561 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7567 case BFD_RELOC_MIPS_21_PCREL_S2
:
7572 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7573 as_bad (_("branch to misaligned address (0x%lx)"),
7574 (unsigned long) address_expr
->X_add_number
);
7575 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7576 & ~((1 << (shift
+ 21)) - 1))
7577 as_bad (_("branch address range overflow (0x%lx)"),
7578 (unsigned long) address_expr
->X_add_number
);
7579 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7584 case BFD_RELOC_MIPS_26_PCREL_S2
:
7589 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7590 as_bad (_("branch to misaligned address (0x%lx)"),
7591 (unsigned long) address_expr
->X_add_number
);
7592 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7593 & ~((1 << (shift
+ 26)) - 1))
7594 as_bad (_("branch address range overflow (0x%lx)"),
7595 (unsigned long) address_expr
->X_add_number
);
7596 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7605 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7608 ip
->insn_opcode
|= value
& 0xffff;
7616 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7618 /* There are a lot of optimizations we could do that we don't.
7619 In particular, we do not, in general, reorder instructions.
7620 If you use gcc with optimization, it will reorder
7621 instructions and generally do much more optimization then we
7622 do here; repeating all that work in the assembler would only
7623 benefit hand written assembly code, and does not seem worth
7625 int nops
= (mips_optimize
== 0
7626 ? nops_for_insn (0, history
, NULL
)
7627 : nops_for_insn_or_target (0, history
, ip
));
7631 unsigned long old_frag_offset
;
7634 old_frag
= frag_now
;
7635 old_frag_offset
= frag_now_fix ();
7637 for (i
= 0; i
< nops
; i
++)
7638 add_fixed_insn (NOP_INSN
);
7639 insert_into_history (0, nops
, NOP_INSN
);
7643 listing_prev_line ();
7644 /* We may be at the start of a variant frag. In case we
7645 are, make sure there is enough space for the frag
7646 after the frags created by listing_prev_line. The
7647 argument to frag_grow here must be at least as large
7648 as the argument to all other calls to frag_grow in
7649 this file. We don't have to worry about being in the
7650 middle of a variant frag, because the variants insert
7651 all needed nop instructions themselves. */
7655 mips_move_text_labels ();
7657 #ifndef NO_ECOFF_DEBUGGING
7658 if (ECOFF_DEBUGGING
)
7659 ecoff_fix_loc (old_frag
, old_frag_offset
);
7663 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7667 /* Work out how many nops in prev_nop_frag are needed by IP,
7668 ignoring hazards generated by the first prev_nop_frag_since
7670 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7671 gas_assert (nops
<= prev_nop_frag_holds
);
7673 /* Enforce NOPS as a minimum. */
7674 if (nops
> prev_nop_frag_required
)
7675 prev_nop_frag_required
= nops
;
7677 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7679 /* Settle for the current number of nops. Update the history
7680 accordingly (for the benefit of any future .set reorder code). */
7681 prev_nop_frag
= NULL
;
7682 insert_into_history (prev_nop_frag_since
,
7683 prev_nop_frag_holds
, NOP_INSN
);
7687 /* Allow this instruction to replace one of the nops that was
7688 tentatively added to prev_nop_frag. */
7689 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7690 prev_nop_frag_holds
--;
7691 prev_nop_frag_since
++;
7695 method
= get_append_method (ip
, address_expr
, reloc_type
);
7696 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7698 dwarf2_emit_insn (0);
7699 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7700 so "move" the instruction address accordingly.
7702 Also, it doesn't seem appropriate for the assembler to reorder .loc
7703 entries. If this instruction is a branch that we are going to swap
7704 with the previous instruction, the two instructions should be
7705 treated as a unit, and the debug information for both instructions
7706 should refer to the start of the branch sequence. Using the
7707 current position is certainly wrong when swapping a 32-bit branch
7708 and a 16-bit delay slot, since the current position would then be
7709 in the middle of a branch. */
7710 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7712 relax32
= (mips_relax_branch
7713 /* Don't try branch relaxation within .set nomacro, or within
7714 .set noat if we use $at for PIC computations. If it turns
7715 out that the branch was out-of-range, we'll get an error. */
7716 && !mips_opts
.warn_about_macros
7717 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7718 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7719 as they have no complementing branches. */
7720 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7722 if (!HAVE_CODE_COMPRESSION
7725 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7726 && delayed_branch_p (ip
))
7728 relaxed_branch
= true;
7729 add_relaxed_insn (ip
, (relaxed_branch_length
7731 uncond_branch_p (ip
) ? -1
7732 : branch_likely_p (ip
) ? 1
7735 (AT
, mips_pic
!= NO_PIC
,
7736 uncond_branch_p (ip
),
7737 branch_likely_p (ip
),
7738 pinfo
& INSN_WRITE_GPR_31
,
7740 address_expr
->X_add_symbol
,
7741 address_expr
->X_add_number
);
7742 *reloc_type
= BFD_RELOC_UNUSED
;
7744 else if (mips_opts
.micromips
7746 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7747 || *reloc_type
> BFD_RELOC_UNUSED
)
7748 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7749 /* Don't try branch relaxation when users specify
7750 16-bit/32-bit instructions. */
7751 && !forced_insn_length
)
7753 bool relax16
= (method
!= APPEND_ADD_COMPACT
7754 && *reloc_type
> BFD_RELOC_UNUSED
);
7755 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7756 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7757 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7758 int nods
= method
== APPEND_ADD_WITH_NOP
;
7759 int al
= pinfo
& INSN_WRITE_GPR_31
;
7760 int length32
= nods
? 8 : 4;
7762 gas_assert (address_expr
!= NULL
);
7763 gas_assert (!mips_relax
.sequence
);
7765 relaxed_branch
= true;
7767 method
= APPEND_ADD
;
7769 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7770 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7771 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7773 uncond
, compact
, al
, nods
,
7775 address_expr
->X_add_symbol
,
7776 address_expr
->X_add_number
);
7777 *reloc_type
= BFD_RELOC_UNUSED
;
7779 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7781 bool require_unextended
;
7782 bool require_extended
;
7786 if (forced_insn_length
!= 0)
7788 require_unextended
= forced_insn_length
== 2;
7789 require_extended
= forced_insn_length
== 4;
7793 require_unextended
= (mips_opts
.noautoextend
7794 && !mips_opcode_32bit_p (ip
->insn_mo
));
7795 require_extended
= 0;
7798 /* We need to set up a variant frag. */
7799 gas_assert (address_expr
!= NULL
);
7800 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7801 symbol created by `make_expr_symbol' may not get a necessary
7802 external relocation produced. */
7803 if (address_expr
->X_op
== O_symbol
)
7805 symbol
= address_expr
->X_add_symbol
;
7806 offset
= address_expr
->X_add_number
;
7810 symbol
= make_expr_symbol (address_expr
);
7811 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7814 add_relaxed_insn (ip
, 12, 0,
7816 (*reloc_type
- BFD_RELOC_UNUSED
,
7817 mips_opts
.ase
& ASE_MIPS16E2
,
7820 mips_opts
.warn_about_macros
,
7821 require_unextended
, require_extended
,
7822 delayed_branch_p (&history
[0]),
7823 history
[0].mips16_absolute_jump_p
),
7826 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7828 if (!delayed_branch_p (ip
))
7829 /* Make sure there is enough room to swap this instruction with
7830 a following jump instruction. */
7832 add_fixed_insn (ip
);
7836 if (mips_opts
.mips16
7837 && mips_opts
.noreorder
7838 && delayed_branch_p (&history
[0]))
7839 as_warn (_("extended instruction in delay slot"));
7841 if (mips_relax
.sequence
)
7843 /* If we've reached the end of this frag, turn it into a variant
7844 frag and record the information for the instructions we've
7846 if (frag_room () < 4)
7847 relax_close_frag ();
7848 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7851 if (mips_relax
.sequence
!= 2)
7853 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7854 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7855 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7856 mips_macro_warning
.insns
[0]++;
7858 if (mips_relax
.sequence
!= 1)
7860 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7861 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7862 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7863 mips_macro_warning
.insns
[1]++;
7866 if (mips_opts
.mips16
)
7869 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7871 add_fixed_insn (ip
);
7874 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7876 bfd_reloc_code_real_type final_type
[3];
7877 reloc_howto_type
*howto0
;
7878 reloc_howto_type
*howto
;
7881 /* Perform any necessary conversion to microMIPS relocations
7882 and find out how many relocations there actually are. */
7883 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7884 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7886 /* In a compound relocation, it is the final (outermost)
7887 operator that determines the relocated field. */
7888 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7893 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7894 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7895 bfd_get_reloc_size (howto
),
7897 howto0
&& howto0
->pc_relative
,
7899 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7900 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7902 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7903 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7904 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7906 /* These relocations can have an addend that won't fit in
7907 4 octets for 64bit assembly. */
7909 && ! howto
->partial_inplace
7910 && (reloc_type
[0] == BFD_RELOC_16
7911 || reloc_type
[0] == BFD_RELOC_32
7912 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7913 || reloc_type
[0] == BFD_RELOC_GPREL16
7914 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7915 || reloc_type
[0] == BFD_RELOC_GPREL32
7916 || reloc_type
[0] == BFD_RELOC_64
7917 || reloc_type
[0] == BFD_RELOC_CTOR
7918 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7919 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7920 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7921 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7922 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7923 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7924 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7925 || hi16_reloc_p (reloc_type
[0])
7926 || lo16_reloc_p (reloc_type
[0])))
7927 ip
->fixp
[0]->fx_no_overflow
= 1;
7929 /* These relocations can have an addend that won't fit in 2 octets. */
7930 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7931 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7932 ip
->fixp
[0]->fx_no_overflow
= 1;
7934 if (mips_relax
.sequence
)
7936 if (mips_relax
.first_fixup
== 0)
7937 mips_relax
.first_fixup
= ip
->fixp
[0];
7939 else if (reloc_needs_lo_p (*reloc_type
))
7941 struct mips_hi_fixup
*hi_fixup
;
7943 /* Reuse the last entry if it already has a matching %lo. */
7944 hi_fixup
= mips_hi_fixup_list
;
7946 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7948 hi_fixup
= XNEW (struct mips_hi_fixup
);
7949 hi_fixup
->next
= mips_hi_fixup_list
;
7950 mips_hi_fixup_list
= hi_fixup
;
7952 hi_fixup
->fixp
= ip
->fixp
[0];
7953 hi_fixup
->seg
= now_seg
;
7956 /* Add fixups for the second and third relocations, if given.
7957 Note that the ABI allows the second relocation to be
7958 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7959 moment we only use RSS_UNDEF, but we could add support
7960 for the others if it ever becomes necessary. */
7961 for (i
= 1; i
< 3; i
++)
7962 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7964 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7965 ip
->fixp
[0]->fx_size
, NULL
, 0,
7966 false, final_type
[i
]);
7968 /* Use fx_tcbit to mark compound relocs. */
7969 ip
->fixp
[0]->fx_tcbit
= 1;
7970 ip
->fixp
[i
]->fx_tcbit
= 1;
7974 /* Update the register mask information. */
7975 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7976 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7981 insert_into_history (0, 1, ip
);
7984 case APPEND_ADD_WITH_NOP
:
7986 struct mips_cl_insn
*nop
;
7988 insert_into_history (0, 1, ip
);
7989 nop
= get_delay_slot_nop (ip
);
7990 add_fixed_insn (nop
);
7991 insert_into_history (0, 1, nop
);
7992 if (mips_relax
.sequence
)
7993 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7997 case APPEND_ADD_COMPACT
:
7998 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7999 if (mips_opts
.mips16
)
8001 ip
->insn_opcode
|= 0x0080;
8002 find_altered_mips16_opcode (ip
);
8004 /* Convert microMIPS instructions. */
8005 else if (mips_opts
.micromips
)
8008 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
8009 ip
->insn_opcode
|= 0x0020;
8011 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
8012 ip
->insn_opcode
= 0x40e00000;
8013 /* beqz16->beqzc, bnez16->bnezc */
8014 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
8016 unsigned long regno
;
8018 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
8019 regno
&= MICROMIPSOP_MASK_MD
;
8020 regno
= micromips_to_32_reg_d_map
[regno
];
8021 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
8022 | (regno
<< MICROMIPSOP_SH_RS
)
8023 | 0x40a00000) ^ 0x00400000;
8025 /* beqz->beqzc, bnez->bnezc */
8026 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
8027 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
8028 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8029 | 0x40a00000) ^ 0x00400000;
8030 /* beq $0->beqzc, bne $0->bnezc */
8031 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8032 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8033 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8034 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8035 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8036 | 0x40a00000) ^ 0x00400000;
8039 find_altered_micromips_opcode (ip
);
8044 insert_into_history (0, 1, ip
);
8049 struct mips_cl_insn delay
= history
[0];
8051 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8053 /* Add the delay slot instruction to the end of the
8054 current frag and shrink the fixed part of the
8055 original frag. If the branch occupies the tail of
8056 the latter, move it backwards to cover the gap. */
8057 delay
.frag
->fr_fix
-= branch_disp
;
8058 if (delay
.frag
== ip
->frag
)
8059 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8060 add_fixed_insn (&delay
);
8064 /* If this is not a relaxed branch and we are in the
8065 same frag, then just swap the instructions. */
8066 move_insn (ip
, delay
.frag
, delay
.where
);
8067 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8071 insert_into_history (0, 1, &delay
);
8076 /* If we have just completed an unconditional branch, clear the history. */
8077 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8078 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8082 mips_no_prev_insn ();
8084 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8085 history
[i
].cleared_p
= 1;
8088 /* We need to emit a label at the end of branch-likely macros. */
8089 if (emit_branch_likely_macro
)
8091 emit_branch_likely_macro
= false;
8092 micromips_add_label ();
8095 /* We just output an insn, so the next one doesn't have a label. */
8096 mips_clear_insn_labels ();
8099 /* Forget that there was any previous instruction or label.
8100 When BRANCH is true, the branch history is also flushed. */
8103 mips_no_prev_insn (void)
8105 prev_nop_frag
= NULL
;
8106 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8107 mips_clear_insn_labels ();
8110 /* This function must be called before we emit something other than
8111 instructions. It is like mips_no_prev_insn except that it inserts
8112 any NOPS that might be needed by previous instructions. */
8115 mips_emit_delays (void)
8117 if (! mips_opts
.noreorder
)
8119 int nops
= nops_for_insn (0, history
, NULL
);
8123 add_fixed_insn (NOP_INSN
);
8124 mips_move_text_labels ();
8127 mips_no_prev_insn ();
8130 /* Start a (possibly nested) noreorder block. */
8133 start_noreorder (void)
8135 if (mips_opts
.noreorder
== 0)
8140 /* None of the instructions before the .set noreorder can be moved. */
8141 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8142 history
[i
].fixed_p
= 1;
8144 /* Insert any nops that might be needed between the .set noreorder
8145 block and the previous instructions. We will later remove any
8146 nops that turn out not to be needed. */
8147 nops
= nops_for_insn (0, history
, NULL
);
8150 if (mips_optimize
!= 0)
8152 /* Record the frag which holds the nop instructions, so
8153 that we can remove them if we don't need them. */
8154 frag_grow (nops
* NOP_INSN_SIZE
);
8155 prev_nop_frag
= frag_now
;
8156 prev_nop_frag_holds
= nops
;
8157 prev_nop_frag_required
= 0;
8158 prev_nop_frag_since
= 0;
8161 for (; nops
> 0; --nops
)
8162 add_fixed_insn (NOP_INSN
);
8164 /* Move on to a new frag, so that it is safe to simply
8165 decrease the size of prev_nop_frag. */
8166 frag_wane (frag_now
);
8168 mips_move_text_labels ();
8170 mips_mark_labels ();
8171 mips_clear_insn_labels ();
8173 mips_opts
.noreorder
++;
8174 mips_any_noreorder
= 1;
8177 /* End a nested noreorder block. */
8180 end_noreorder (void)
8182 mips_opts
.noreorder
--;
8183 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8185 /* Commit to inserting prev_nop_frag_required nops and go back to
8186 handling nop insertion the .set reorder way. */
8187 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8189 insert_into_history (prev_nop_frag_since
,
8190 prev_nop_frag_required
, NOP_INSN
);
8191 prev_nop_frag
= NULL
;
8195 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8196 higher bits unset. */
8199 normalize_constant_expr (expressionS
*ex
)
8201 if (ex
->X_op
== O_constant
8202 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8203 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8207 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8208 all higher bits unset. */
8211 normalize_address_expr (expressionS
*ex
)
8213 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8214 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8215 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8216 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8220 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8221 Return true if the match was successful.
8223 OPCODE_EXTRA is a value that should be ORed into the opcode
8224 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8225 there are more alternatives after OPCODE and SOFT_MATCH is
8226 as for mips_arg_info. */
8229 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8230 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8231 bool lax_match
, bool complete_p
)
8234 struct mips_arg_info arg
;
8235 const struct mips_operand
*operand
;
8238 imm_expr
.X_op
= O_absent
;
8239 offset_expr
.X_op
= O_absent
;
8240 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8241 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8242 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8244 create_insn (insn
, opcode
);
8245 /* When no opcode suffix is specified, assume ".xyzw". */
8246 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8247 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8249 insn
->insn_opcode
|= opcode_extra
;
8250 memset (&arg
, 0, sizeof (arg
));
8254 arg
.last_regno
= ILLEGAL_REG
;
8255 arg
.dest_regno
= ILLEGAL_REG
;
8256 arg
.lax_match
= lax_match
;
8257 for (args
= opcode
->args
;; ++args
)
8259 if (arg
.token
->type
== OT_END
)
8261 /* Handle unary instructions in which only one operand is given.
8262 The source is then the same as the destination. */
8263 if (arg
.opnum
== 1 && *args
== ',')
8265 operand
= (mips_opts
.micromips
8266 ? decode_micromips_operand (args
+ 1)
8267 : decode_mips_operand (args
+ 1));
8268 if (operand
&& mips_optional_operand_p (operand
))
8276 /* Treat elided base registers as $0. */
8277 if (strcmp (args
, "(b)") == 0)
8285 /* The register suffix is optional. */
8290 /* Fail the match if there were too few operands. */
8294 /* Successful match. */
8297 clear_insn_error ();
8298 if (arg
.dest_regno
== arg
.last_regno
8299 && startswith (insn
->insn_mo
->name
, "jalr"))
8303 (0, _("source and destination must be different"));
8304 else if (arg
.last_regno
== 31)
8306 (0, _("a destination register must be supplied"));
8308 else if (arg
.last_regno
== 31
8309 && (startswith (insn
->insn_mo
->name
, "bltzal")
8310 || startswith (insn
->insn_mo
->name
, "bgezal")))
8311 set_insn_error (0, _("the source register must not be $31"));
8312 check_completed_insn (&arg
);
8316 /* Fail the match if the line has too many operands. */
8320 /* Handle characters that need to match exactly. */
8321 if (*args
== '(' || *args
== ')' || *args
== ',')
8323 if (match_char (&arg
, *args
))
8330 if (arg
.token
->type
== OT_DOUBLE_CHAR
8331 && arg
.token
->u
.ch
== *args
)
8339 /* Handle special macro operands. Work out the properties of
8348 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8352 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8361 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8365 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8369 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8375 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8377 imm_expr
.X_op
= O_constant
;
8379 normalize_constant_expr (&imm_expr
);
8383 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8385 /* Assume that the offset has been elided and that what
8386 we saw was a base register. The match will fail later
8387 if that assumption turns out to be wrong. */
8388 offset_expr
.X_op
= O_constant
;
8389 offset_expr
.X_add_number
= 0;
8393 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8395 normalize_address_expr (&offset_expr
);
8400 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8406 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8412 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8418 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8424 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8428 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8432 gas_assert (mips_opts
.micromips
);
8438 if (!forced_insn_length
)
8439 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8441 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8443 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8449 operand
= (mips_opts
.micromips
8450 ? decode_micromips_operand (args
)
8451 : decode_mips_operand (args
));
8455 /* Skip prefixes. */
8456 if (*args
== '+' || *args
== 'm' || *args
== '-')
8459 if (mips_optional_operand_p (operand
)
8461 && (arg
.token
[0].type
!= OT_REG
8462 || arg
.token
[1].type
== OT_END
))
8464 /* Assume that the register has been elided and is the
8465 same as the first operand. */
8470 if (!match_operand (&arg
, operand
))
8475 /* Like match_insn, but for MIPS16. */
8478 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8479 struct mips_operand_token
*tokens
)
8482 const struct mips_operand
*operand
;
8483 const struct mips_operand
*ext_operand
;
8485 int required_insn_length
;
8486 struct mips_arg_info arg
;
8489 if (forced_insn_length
)
8490 required_insn_length
= forced_insn_length
;
8491 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8492 required_insn_length
= 2;
8494 required_insn_length
= 0;
8496 create_insn (insn
, opcode
);
8497 imm_expr
.X_op
= O_absent
;
8498 offset_expr
.X_op
= O_absent
;
8499 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8500 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8501 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8504 memset (&arg
, 0, sizeof (arg
));
8508 arg
.last_regno
= ILLEGAL_REG
;
8509 arg
.dest_regno
= ILLEGAL_REG
;
8511 for (args
= opcode
->args
;; ++args
)
8515 if (arg
.token
->type
== OT_END
)
8519 /* Handle unary instructions in which only one operand is given.
8520 The source is then the same as the destination. */
8521 if (arg
.opnum
== 1 && *args
== ',')
8523 operand
= decode_mips16_operand (args
[1], false);
8524 if (operand
&& mips_optional_operand_p (operand
))
8532 /* Fail the match if there were too few operands. */
8536 /* Successful match. Stuff the immediate value in now, if
8538 clear_insn_error ();
8539 if (opcode
->pinfo
== INSN_MACRO
)
8541 gas_assert (relax_char
== 0 || relax_char
== 'p');
8542 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8545 && offset_expr
.X_op
== O_constant
8547 && calculate_reloc (*offset_reloc
,
8548 offset_expr
.X_add_number
,
8551 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8552 required_insn_length
, &insn
->insn_opcode
);
8553 offset_expr
.X_op
= O_absent
;
8554 *offset_reloc
= BFD_RELOC_UNUSED
;
8556 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8558 if (required_insn_length
== 2)
8559 set_insn_error (0, _("invalid unextended operand value"));
8560 else if (!mips_opcode_32bit_p (opcode
))
8562 forced_insn_length
= 4;
8563 insn
->insn_opcode
|= MIPS16_EXTEND
;
8566 else if (relax_char
)
8567 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8569 check_completed_insn (&arg
);
8573 /* Fail the match if the line has too many operands. */
8577 /* Handle characters that need to match exactly. */
8578 if (*args
== '(' || *args
== ')' || *args
== ',')
8580 if (match_char (&arg
, *args
))
8600 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8602 imm_expr
.X_op
= O_constant
;
8604 normalize_constant_expr (&imm_expr
);
8609 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8613 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8617 if (operand
->type
== OP_PCREL
)
8621 ext_operand
= decode_mips16_operand (c
, true);
8622 if (operand
!= ext_operand
)
8624 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8626 offset_expr
.X_op
= O_constant
;
8627 offset_expr
.X_add_number
= 0;
8632 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8635 /* '8' is used for SLTI(U) and has traditionally not
8636 been allowed to take relocation operators. */
8637 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8638 && (ext_operand
->size
!= 16 || c
== '8'))
8640 match_not_constant (&arg
);
8644 if (offset_expr
.X_op
== O_big
)
8646 match_out_of_range (&arg
);
8655 if (mips_optional_operand_p (operand
)
8657 && (arg
.token
[0].type
!= OT_REG
8658 || arg
.token
[1].type
== OT_END
))
8660 /* Assume that the register has been elided and is the
8661 same as the first operand. */
8666 if (!match_operand (&arg
, operand
))
8671 /* Record that the current instruction is invalid for the current ISA. */
8674 match_invalid_for_isa (void)
8677 (0, _("opcode not supported on this processor: %s (%s)"),
8678 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8679 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8682 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8683 Return true if a definite match or failure was found, storing any match
8684 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8685 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8686 tried and failed to match under normal conditions and now want to try a
8687 more relaxed match. */
8690 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8691 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8692 int opcode_extra
, bool lax_match
)
8694 const struct mips_opcode
*opcode
;
8695 const struct mips_opcode
*invalid_delay_slot
;
8696 bool seen_valid_for_isa
, seen_valid_for_size
;
8698 /* Search for a match, ignoring alternatives that don't satisfy the
8699 current ISA or forced_length. */
8700 invalid_delay_slot
= 0;
8701 seen_valid_for_isa
= false;
8702 seen_valid_for_size
= false;
8706 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8707 if (is_opcode_valid (opcode
))
8709 seen_valid_for_isa
= true;
8710 if (is_size_valid (opcode
))
8714 seen_valid_for_size
= true;
8715 delay_slot_ok
= is_delay_slot_valid (opcode
);
8716 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8717 lax_match
, delay_slot_ok
))
8721 if (!invalid_delay_slot
)
8722 invalid_delay_slot
= opcode
;
8731 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8733 /* If the only matches we found had the wrong length for the delay slot,
8734 pick the first such match. We'll issue an appropriate warning later. */
8735 if (invalid_delay_slot
)
8737 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8743 /* Handle the case where we didn't try to match an instruction because
8744 all the alternatives were incompatible with the current ISA. */
8745 if (!seen_valid_for_isa
)
8747 match_invalid_for_isa ();
8751 /* Handle the case where we didn't try to match an instruction because
8752 all the alternatives were of the wrong size. */
8753 if (!seen_valid_for_size
)
8755 if (mips_opts
.insn32
)
8756 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8759 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8760 8 * forced_insn_length
);
8767 /* Like match_insns, but for MIPS16. */
8770 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8771 struct mips_operand_token
*tokens
)
8773 const struct mips_opcode
*opcode
;
8774 bool seen_valid_for_isa
;
8775 bool seen_valid_for_size
;
8777 /* Search for a match, ignoring alternatives that don't satisfy the
8778 current ISA. There are no separate entries for extended forms so
8779 we deal with forced_length later. */
8780 seen_valid_for_isa
= false;
8781 seen_valid_for_size
= false;
8785 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8786 if (is_opcode_valid_16 (opcode
))
8788 seen_valid_for_isa
= true;
8789 if (is_size_valid_16 (opcode
))
8791 seen_valid_for_size
= true;
8792 if (match_mips16_insn (insn
, opcode
, tokens
))
8798 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8799 && strcmp (opcode
->name
, first
->name
) == 0);
8801 /* Handle the case where we didn't try to match an instruction because
8802 all the alternatives were incompatible with the current ISA. */
8803 if (!seen_valid_for_isa
)
8805 match_invalid_for_isa ();
8809 /* Handle the case where we didn't try to match an instruction because
8810 all the alternatives were of the wrong size. */
8811 if (!seen_valid_for_size
)
8813 if (forced_insn_length
== 2)
8815 (0, _("unrecognized unextended version of MIPS16 opcode"));
8818 (0, _("unrecognized extended version of MIPS16 opcode"));
8825 /* Set up global variables for the start of a new macro. */
8830 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8831 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8832 sizeof (mips_macro_warning
.first_insn_sizes
));
8833 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8834 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8835 && delayed_branch_p (&history
[0]));
8837 && history
[0].frag
->fr_type
== rs_machine_dependent
8838 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8839 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8840 mips_macro_warning
.delay_slot_length
= 0;
8842 switch (history
[0].insn_mo
->pinfo2
8843 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8845 case INSN2_BRANCH_DELAY_32BIT
:
8846 mips_macro_warning
.delay_slot_length
= 4;
8848 case INSN2_BRANCH_DELAY_16BIT
:
8849 mips_macro_warning
.delay_slot_length
= 2;
8852 mips_macro_warning
.delay_slot_length
= 0;
8855 mips_macro_warning
.first_frag
= NULL
;
8858 /* Given that a macro is longer than one instruction or of the wrong size,
8859 return the appropriate warning for it. Return null if no warning is
8860 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8861 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8862 and RELAX_NOMACRO. */
8865 macro_warning (relax_substateT subtype
)
8867 if (subtype
& RELAX_DELAY_SLOT
)
8868 return _("macro instruction expanded into multiple instructions"
8869 " in a branch delay slot");
8870 else if (subtype
& RELAX_NOMACRO
)
8871 return _("macro instruction expanded into multiple instructions");
8872 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8873 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8874 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8875 ? _("macro instruction expanded into a wrong size instruction"
8876 " in a 16-bit branch delay slot")
8877 : _("macro instruction expanded into a wrong size instruction"
8878 " in a 32-bit branch delay slot"));
8883 /* Finish up a macro. Emit warnings as appropriate. */
8888 /* Relaxation warning flags. */
8889 relax_substateT subtype
= 0;
8891 /* Check delay slot size requirements. */
8892 if (mips_macro_warning
.delay_slot_length
== 2)
8893 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8894 if (mips_macro_warning
.delay_slot_length
!= 0)
8896 if (mips_macro_warning
.delay_slot_length
8897 != mips_macro_warning
.first_insn_sizes
[0])
8898 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8899 if (mips_macro_warning
.delay_slot_length
8900 != mips_macro_warning
.first_insn_sizes
[1])
8901 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8904 /* Check instruction count requirements. */
8905 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8907 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8908 subtype
|= RELAX_SECOND_LONGER
;
8909 if (mips_opts
.warn_about_macros
)
8910 subtype
|= RELAX_NOMACRO
;
8911 if (mips_macro_warning
.delay_slot_p
)
8912 subtype
|= RELAX_DELAY_SLOT
;
8915 /* If both alternatives fail to fill a delay slot correctly,
8916 emit the warning now. */
8917 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8918 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8923 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8924 | RELAX_DELAY_SLOT_SIZE_FIRST
8925 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8926 msg
= macro_warning (s
);
8928 as_warn ("%s", msg
);
8932 /* If both implementations are longer than 1 instruction, then emit the
8934 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8939 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8940 msg
= macro_warning (s
);
8942 as_warn ("%s", msg
);
8946 /* If any flags still set, then one implementation might need a warning
8947 and the other either will need one of a different kind or none at all.
8948 Pass any remaining flags over to relaxation. */
8949 if (mips_macro_warning
.first_frag
!= NULL
)
8950 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8953 /* Instruction operand formats used in macros that vary between
8954 standard MIPS and microMIPS code. */
8956 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8957 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8958 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8959 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8960 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8961 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8962 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8963 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8965 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8966 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8967 : cop12_fmt[mips_opts.micromips])
8968 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8969 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8970 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8971 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8972 : mem12_fmt[mips_opts.micromips])
8973 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8974 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8975 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8977 /* Read a macro's relocation codes from *ARGS and store them in *R.
8978 The first argument in *ARGS will be either the code for a single
8979 relocation or -1 followed by the three codes that make up a
8980 composite relocation. */
8983 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8987 next
= va_arg (*args
, int);
8989 r
[0] = (bfd_reloc_code_real_type
) next
;
8992 for (i
= 0; i
< 3; i
++)
8993 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8994 /* This function is only used for 16-bit relocation fields.
8995 To make the macro code simpler, treat an unrelocated value
8996 in the same way as BFD_RELOC_LO16. */
8997 if (r
[0] == BFD_RELOC_UNUSED
)
8998 r
[0] = BFD_RELOC_LO16
;
9002 /* Build an instruction created by a macro expansion. This is passed
9003 a pointer to the count of instructions created so far, an
9004 expression, the name of the instruction to build, an operand format
9005 string, and corresponding arguments. */
9008 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
9010 const struct mips_opcode
*mo
= NULL
;
9011 bfd_reloc_code_real_type r
[3];
9012 const struct mips_opcode
*amo
;
9013 const struct mips_operand
*operand
;
9015 struct mips_cl_insn insn
;
9019 va_start (args
, fmt
);
9021 if (mips_opts
.mips16
)
9023 mips16_macro_build (ep
, name
, fmt
, &args
);
9028 r
[0] = BFD_RELOC_UNUSED
;
9029 r
[1] = BFD_RELOC_UNUSED
;
9030 r
[2] = BFD_RELOC_UNUSED
;
9031 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9032 amo
= (struct mips_opcode
*) str_hash_find (hash
, name
);
9034 gas_assert (strcmp (name
, amo
->name
) == 0);
9038 /* Search until we get a match for NAME. It is assumed here that
9039 macros will never generate MDMX, MIPS-3D, or MT instructions.
9040 We try to match an instruction that fulfills the branch delay
9041 slot instruction length requirement (if any) of the previous
9042 instruction. While doing this we record the first instruction
9043 seen that matches all the other conditions and use it anyway
9044 if the requirement cannot be met; we will issue an appropriate
9045 warning later on. */
9046 if (strcmp (fmt
, amo
->args
) == 0
9047 && amo
->pinfo
!= INSN_MACRO
9048 && is_opcode_valid (amo
)
9049 && is_size_valid (amo
))
9051 if (is_delay_slot_valid (amo
))
9061 gas_assert (amo
->name
);
9063 while (strcmp (name
, amo
->name
) == 0);
9066 create_insn (&insn
, mo
);
9079 macro_read_relocs (&args
, r
);
9080 gas_assert (*r
== BFD_RELOC_GPREL16
9081 || *r
== BFD_RELOC_MIPS_HIGHER
9082 || *r
== BFD_RELOC_HI16_S
9083 || *r
== BFD_RELOC_LO16
9084 || *r
== BFD_RELOC_MIPS_GOT_OFST
9085 || (mips_opts
.micromips
9086 && (*r
== BFD_RELOC_16
9087 || *r
== BFD_RELOC_MIPS_GOT16
9088 || *r
== BFD_RELOC_MIPS_CALL16
9089 || *r
== BFD_RELOC_MIPS_GOT_HI16
9090 || *r
== BFD_RELOC_MIPS_GOT_LO16
9091 || *r
== BFD_RELOC_MIPS_CALL_HI16
9092 || *r
== BFD_RELOC_MIPS_CALL_LO16
9093 || *r
== BFD_RELOC_MIPS_SUB
9094 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9095 || *r
== BFD_RELOC_MIPS_HIGHEST
9096 || *r
== BFD_RELOC_MIPS_GOT_DISP
9097 || *r
== BFD_RELOC_MIPS_TLS_GD
9098 || *r
== BFD_RELOC_MIPS_TLS_LDM
9099 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9100 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9101 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9102 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9103 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9107 macro_read_relocs (&args
, r
);
9111 macro_read_relocs (&args
, r
);
9112 gas_assert (ep
!= NULL
9113 && (ep
->X_op
== O_constant
9114 || (ep
->X_op
== O_symbol
9115 && (*r
== BFD_RELOC_MIPS_HIGHEST
9116 || *r
== BFD_RELOC_HI16_S
9117 || *r
== BFD_RELOC_HI16
9118 || *r
== BFD_RELOC_GPREL16
9119 || *r
== BFD_RELOC_MIPS_GOT_HI16
9120 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9124 gas_assert (ep
!= NULL
);
9127 * This allows macro() to pass an immediate expression for
9128 * creating short branches without creating a symbol.
9130 * We don't allow branch relaxation for these branches, as
9131 * they should only appear in ".set nomacro" anyway.
9133 if (ep
->X_op
== O_constant
)
9135 /* For microMIPS we always use relocations for branches.
9136 So we should not resolve immediate values. */
9137 gas_assert (!mips_opts
.micromips
);
9139 if ((ep
->X_add_number
& 3) != 0)
9140 as_bad (_("branch to misaligned address (0x%lx)"),
9141 (unsigned long) ep
->X_add_number
);
9142 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9143 as_bad (_("branch address range overflow (0x%lx)"),
9144 (unsigned long) ep
->X_add_number
);
9145 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9149 *r
= BFD_RELOC_16_PCREL_S2
;
9153 gas_assert (ep
!= NULL
);
9154 *r
= BFD_RELOC_MIPS_JMP
;
9158 operand
= (mips_opts
.micromips
9159 ? decode_micromips_operand (fmt
)
9160 : decode_mips_operand (fmt
));
9164 uval
= va_arg (args
, int);
9165 if (operand
->type
== OP_CLO_CLZ_DEST
)
9166 uval
|= (uval
<< 5);
9167 insn_insert_operand (&insn
, operand
, uval
);
9169 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9175 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9177 append_insn (&insn
, ep
, r
, true);
9181 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9184 struct mips_opcode
*mo
;
9185 struct mips_cl_insn insn
;
9186 const struct mips_operand
*operand
;
9187 bfd_reloc_code_real_type r
[3]
9188 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9190 mo
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, name
);
9192 gas_assert (strcmp (name
, mo
->name
) == 0);
9194 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9197 gas_assert (mo
->name
);
9198 gas_assert (strcmp (name
, mo
->name
) == 0);
9201 create_insn (&insn
, mo
);
9238 gas_assert (ep
!= NULL
);
9240 if (ep
->X_op
!= O_constant
)
9241 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9242 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9244 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9246 *r
= BFD_RELOC_UNUSED
;
9252 operand
= decode_mips16_operand (c
, false);
9256 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9261 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9263 append_insn (&insn
, ep
, r
, true);
9267 * Generate a "jalr" instruction with a relocation hint to the called
9268 * function. This occurs in NewABI PIC code.
9271 macro_build_jalr (expressionS
*ep
, int cprestore
)
9273 static const bfd_reloc_code_real_type jalr_relocs
[2]
9274 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9275 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9279 if (MIPS_JALR_HINT_P (ep
))
9284 if (mips_opts
.micromips
)
9286 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9287 ? "jalr" : "jalrs");
9288 if (MIPS_JALR_HINT_P (ep
)
9290 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9291 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9293 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9296 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9297 if (MIPS_JALR_HINT_P (ep
))
9298 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, false, jalr_reloc
);
9302 * Generate a "lui" instruction.
9305 macro_build_lui (expressionS
*ep
, int regnum
)
9307 gas_assert (! mips_opts
.mips16
);
9309 if (ep
->X_op
!= O_constant
)
9311 gas_assert (ep
->X_op
== O_symbol
);
9312 /* _gp_disp is a special case, used from s_cpload.
9313 __gnu_local_gp is used if mips_no_shared. */
9314 gas_assert (mips_pic
== NO_PIC
9316 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9317 || (! mips_in_shared
9318 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9319 "__gnu_local_gp") == 0));
9322 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9325 /* Generate a sequence of instructions to do a load or store from a constant
9326 offset off of a base register (breg) into/from a target register (treg),
9327 using AT if necessary. */
9329 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9330 int treg
, int breg
, int dbl
)
9332 gas_assert (ep
->X_op
== O_constant
);
9334 /* Sign-extending 32-bit constants makes their handling easier. */
9336 normalize_constant_expr (ep
);
9338 /* Right now, this routine can only handle signed 32-bit constants. */
9339 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9340 as_warn (_("operand overflow"));
9342 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9344 /* Signed 16-bit offset will fit in the op. Easy! */
9345 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9349 /* 32-bit offset, need multiple instructions and AT, like:
9350 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9351 addu $tempreg,$tempreg,$breg
9352 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9353 to handle the complete offset. */
9354 macro_build_lui (ep
, AT
);
9355 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9356 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9359 as_bad (_("macro used $at after \".set noat\""));
9364 * Generates code to set the $at register to true (one)
9365 * if reg is less than the immediate expression.
9368 set_at (int reg
, int unsignedp
)
9370 if (imm_expr
.X_add_number
>= -0x8000
9371 && imm_expr
.X_add_number
< 0x8000)
9372 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9373 AT
, reg
, BFD_RELOC_LO16
);
9376 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9377 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9381 /* Count the leading zeroes by performing a binary chop. This is a
9382 bulky bit of source, but performance is a LOT better for the
9383 majority of values than a simple loop to count the bits:
9384 for (lcnt = 0; (lcnt < 32); lcnt++)
9385 if ((v) & (1 << (31 - lcnt)))
9387 However it is not code size friendly, and the gain will drop a bit
9388 on certain cached systems.
9390 #define COUNT_TOP_ZEROES(v) \
9391 (((v) & ~0xffff) == 0 \
9392 ? ((v) & ~0xff) == 0 \
9393 ? ((v) & ~0xf) == 0 \
9394 ? ((v) & ~0x3) == 0 \
9395 ? ((v) & ~0x1) == 0 \
9400 : ((v) & ~0x7) == 0 \
9403 : ((v) & ~0x3f) == 0 \
9404 ? ((v) & ~0x1f) == 0 \
9407 : ((v) & ~0x7f) == 0 \
9410 : ((v) & ~0xfff) == 0 \
9411 ? ((v) & ~0x3ff) == 0 \
9412 ? ((v) & ~0x1ff) == 0 \
9415 : ((v) & ~0x7ff) == 0 \
9418 : ((v) & ~0x3fff) == 0 \
9419 ? ((v) & ~0x1fff) == 0 \
9422 : ((v) & ~0x7fff) == 0 \
9425 : ((v) & ~0xffffff) == 0 \
9426 ? ((v) & ~0xfffff) == 0 \
9427 ? ((v) & ~0x3ffff) == 0 \
9428 ? ((v) & ~0x1ffff) == 0 \
9431 : ((v) & ~0x7ffff) == 0 \
9434 : ((v) & ~0x3fffff) == 0 \
9435 ? ((v) & ~0x1fffff) == 0 \
9438 : ((v) & ~0x7fffff) == 0 \
9441 : ((v) & ~0xfffffff) == 0 \
9442 ? ((v) & ~0x3ffffff) == 0 \
9443 ? ((v) & ~0x1ffffff) == 0 \
9446 : ((v) & ~0x7ffffff) == 0 \
9449 : ((v) & ~0x3fffffff) == 0 \
9450 ? ((v) & ~0x1fffffff) == 0 \
9453 : ((v) & ~0x7fffffff) == 0 \
9458 * This routine generates the least number of instructions necessary to load
9459 * an absolute expression value into a register.
9462 load_register (int reg
, expressionS
*ep
, int dbl
)
9465 expressionS hi32
, lo32
;
9467 if (ep
->X_op
!= O_big
)
9469 gas_assert (ep
->X_op
== O_constant
);
9471 /* Sign-extending 32-bit constants makes their handling easier. */
9473 normalize_constant_expr (ep
);
9475 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9477 /* We can handle 16 bit signed values with an addiu to
9478 $zero. No need to ever use daddiu here, since $zero and
9479 the result are always correct in 32 bit mode. */
9480 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9483 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9485 /* We can handle 16 bit unsigned values with an ori to
9487 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9490 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9492 /* 32 bit values require an lui. */
9493 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9494 if ((ep
->X_add_number
& 0xffff) != 0)
9495 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9500 /* The value is larger than 32 bits. */
9502 if (!dbl
|| GPR_SIZE
== 32)
9506 sprintf_vma (value
, ep
->X_add_number
);
9507 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9508 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9512 if (ep
->X_op
!= O_big
)
9515 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9516 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9517 hi32
.X_add_number
&= 0xffffffff;
9519 lo32
.X_add_number
&= 0xffffffff;
9523 gas_assert (ep
->X_add_number
> 2);
9524 if (ep
->X_add_number
== 3)
9525 generic_bignum
[3] = 0;
9526 else if (ep
->X_add_number
> 4)
9527 as_bad (_("number larger than 64 bits"));
9528 lo32
.X_op
= O_constant
;
9529 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9530 hi32
.X_op
= O_constant
;
9531 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9534 if (hi32
.X_add_number
== 0)
9539 unsigned long hi
, lo
;
9541 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9543 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9545 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9548 if (lo32
.X_add_number
& 0x80000000)
9550 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9551 if (lo32
.X_add_number
& 0xffff)
9552 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9557 /* Check for 16bit shifted constant. We know that hi32 is
9558 non-zero, so start the mask on the first bit of the hi32
9563 unsigned long himask
, lomask
;
9567 himask
= 0xffff >> (32 - shift
);
9568 lomask
= (0xffffU
<< shift
) & 0xffffffff;
9572 himask
= 0xffffU
<< (shift
- 32);
9575 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9576 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9580 tmp
.X_op
= O_constant
;
9582 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9583 | (lo32
.X_add_number
>> shift
));
9585 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9586 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9587 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9588 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9593 while (shift
<= (64 - 16));
9595 /* Find the bit number of the lowest one bit, and store the
9596 shifted value in hi/lo. */
9597 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9598 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9602 while ((lo
& 1) == 0)
9609 lo
|= (hi
& ((2UL << (bit
- 1)) - 1)) << (32 - bit
);
9616 while ((hi
& 1) == 0)
9625 /* Optimize if the shifted value is a (power of 2) - 1. */
9626 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9627 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9629 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9634 /* This instruction will set the register to be all
9636 tmp
.X_op
= O_constant
;
9637 tmp
.X_add_number
= (offsetT
) -1;
9638 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9642 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9643 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9645 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9646 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9651 /* Sign extend hi32 before calling load_register, because we can
9652 generally get better code when we load a sign extended value. */
9653 if ((hi32
.X_add_number
& 0x80000000) != 0)
9654 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9655 load_register (reg
, &hi32
, 0);
9658 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9662 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9670 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9672 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9673 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9679 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9683 mid16
.X_add_number
>>= 16;
9684 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9685 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9688 if ((lo32
.X_add_number
& 0xffff) != 0)
9689 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9693 load_delay_nop (void)
9695 if (!gpr_interlocks
)
9696 macro_build (NULL
, "nop", "");
9699 /* Load an address into a register. */
9702 load_address (int reg
, expressionS
*ep
, int *used_at
)
9704 if (ep
->X_op
!= O_constant
9705 && ep
->X_op
!= O_symbol
)
9707 as_bad (_("expression too complex"));
9708 ep
->X_op
= O_constant
;
9711 if (ep
->X_op
== O_constant
)
9713 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9717 if (mips_pic
== NO_PIC
)
9719 /* If this is a reference to a GP relative symbol, we want
9720 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9722 lui $reg,<sym> (BFD_RELOC_HI16_S)
9723 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9724 If we have an addend, we always use the latter form.
9726 With 64bit address space and a usable $at we want
9727 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9728 lui $at,<sym> (BFD_RELOC_HI16_S)
9729 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9730 daddiu $at,<sym> (BFD_RELOC_LO16)
9734 If $at is already in use, we use a path which is suboptimal
9735 on superscalar processors.
9736 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9737 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9739 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9741 daddiu $reg,<sym> (BFD_RELOC_LO16)
9743 For GP relative symbols in 64bit address space we can use
9744 the same sequence as in 32bit address space. */
9745 if (HAVE_64BIT_SYMBOLS
)
9747 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9748 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9750 relax_start (ep
->X_add_symbol
);
9751 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9752 mips_gp_register
, BFD_RELOC_GPREL16
);
9756 if (*used_at
== 0 && mips_opts
.at
)
9758 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9759 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9760 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9761 BFD_RELOC_MIPS_HIGHER
);
9762 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9763 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9764 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9769 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9770 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9771 BFD_RELOC_MIPS_HIGHER
);
9772 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9773 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9774 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9775 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9778 if (mips_relax
.sequence
)
9783 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9784 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9786 relax_start (ep
->X_add_symbol
);
9787 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9788 mips_gp_register
, BFD_RELOC_GPREL16
);
9791 macro_build_lui (ep
, reg
);
9792 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9793 reg
, reg
, BFD_RELOC_LO16
);
9794 if (mips_relax
.sequence
)
9798 else if (!mips_big_got
)
9802 /* If this is a reference to an external symbol, we want
9803 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9805 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9807 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9808 If there is a constant, it must be added in after.
9810 If we have NewABI, we want
9811 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9812 unless we're referencing a global symbol with a non-zero
9813 offset, in which case cst must be added separately. */
9816 if (ep
->X_add_number
)
9818 ex
.X_add_number
= ep
->X_add_number
;
9819 ep
->X_add_number
= 0;
9820 relax_start (ep
->X_add_symbol
);
9821 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9822 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9823 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9824 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9825 ex
.X_op
= O_constant
;
9826 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9827 reg
, reg
, BFD_RELOC_LO16
);
9828 ep
->X_add_number
= ex
.X_add_number
;
9831 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9832 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9833 if (mips_relax
.sequence
)
9838 ex
.X_add_number
= ep
->X_add_number
;
9839 ep
->X_add_number
= 0;
9840 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9841 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9843 relax_start (ep
->X_add_symbol
);
9845 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9849 if (ex
.X_add_number
!= 0)
9851 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9852 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9853 ex
.X_op
= O_constant
;
9854 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9855 reg
, reg
, BFD_RELOC_LO16
);
9859 else if (mips_big_got
)
9863 /* This is the large GOT case. If this is a reference to an
9864 external symbol, we want
9865 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9867 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9869 Otherwise, for a reference to a local symbol in old ABI, we want
9870 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9872 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9873 If there is a constant, it must be added in after.
9875 In the NewABI, for local symbols, with or without offsets, we want:
9876 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9877 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9881 ex
.X_add_number
= ep
->X_add_number
;
9882 ep
->X_add_number
= 0;
9883 relax_start (ep
->X_add_symbol
);
9884 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9885 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9886 reg
, reg
, mips_gp_register
);
9887 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9888 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9889 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9890 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9891 else if (ex
.X_add_number
)
9893 ex
.X_op
= O_constant
;
9894 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9898 ep
->X_add_number
= ex
.X_add_number
;
9900 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9901 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9902 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9903 BFD_RELOC_MIPS_GOT_OFST
);
9908 ex
.X_add_number
= ep
->X_add_number
;
9909 ep
->X_add_number
= 0;
9910 relax_start (ep
->X_add_symbol
);
9911 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9912 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9913 reg
, reg
, mips_gp_register
);
9914 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9915 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9917 if (reg_needs_delay (mips_gp_register
))
9919 /* We need a nop before loading from $gp. This special
9920 check is required because the lui which starts the main
9921 instruction stream does not refer to $gp, and so will not
9922 insert the nop which may be required. */
9923 macro_build (NULL
, "nop", "");
9925 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9926 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9928 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9932 if (ex
.X_add_number
!= 0)
9934 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9935 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9936 ex
.X_op
= O_constant
;
9937 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9945 if (!mips_opts
.at
&& *used_at
== 1)
9946 as_bad (_("macro used $at after \".set noat\""));
9949 /* Move the contents of register SOURCE into register DEST. */
9952 move_register (int dest
, int source
)
9954 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9955 instruction specifically requires a 32-bit one. */
9956 if (mips_opts
.micromips
9957 && !mips_opts
.insn32
9958 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9959 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9961 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9964 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9965 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9966 The two alternatives are:
9968 Global symbol Local symbol
9969 ------------- ------------
9970 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9972 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9974 load_got_offset emits the first instruction and add_got_offset
9975 emits the second for a 16-bit offset or add_got_offset_hilo emits
9976 a sequence to add a 32-bit offset using a scratch register. */
9979 load_got_offset (int dest
, expressionS
*local
)
9984 global
.X_add_number
= 0;
9986 relax_start (local
->X_add_symbol
);
9987 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9988 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9990 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9991 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9996 add_got_offset (int dest
, expressionS
*local
)
10000 global
.X_op
= O_constant
;
10001 global
.X_op_symbol
= NULL
;
10002 global
.X_add_symbol
= NULL
;
10003 global
.X_add_number
= local
->X_add_number
;
10005 relax_start (local
->X_add_symbol
);
10006 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
10007 dest
, dest
, BFD_RELOC_LO16
);
10009 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
10014 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
10016 expressionS global
;
10017 int hold_mips_optimize
;
10019 global
.X_op
= O_constant
;
10020 global
.X_op_symbol
= NULL
;
10021 global
.X_add_symbol
= NULL
;
10022 global
.X_add_number
= local
->X_add_number
;
10024 relax_start (local
->X_add_symbol
);
10025 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
10027 /* Set mips_optimize around the lui instruction to avoid
10028 inserting an unnecessary nop after the lw. */
10029 hold_mips_optimize
= mips_optimize
;
10031 macro_build_lui (&global
, tmp
);
10032 mips_optimize
= hold_mips_optimize
;
10033 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10036 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10039 /* Emit a sequence of instructions to emulate a branch likely operation.
10040 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10041 is its complementing branch with the original condition negated.
10042 CALL is set if the original branch specified the link operation.
10043 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10045 Code like this is produced in the noreorder mode:
10050 delay slot (executed only if branch taken)
10053 or, if CALL is set:
10058 delay slot (executed only if branch taken)
10061 In the reorder mode the delay slot would be filled with a nop anyway,
10062 so code produced is simply:
10067 This function is used when producing code for the microMIPS ASE that
10068 does not implement branch likely instructions in hardware. */
10071 macro_build_branch_likely (const char *br
, const char *brneg
,
10072 int call
, expressionS
*ep
, const char *fmt
,
10073 unsigned int sreg
, unsigned int treg
)
10075 int noreorder
= mips_opts
.noreorder
;
10078 gas_assert (mips_opts
.micromips
);
10079 start_noreorder ();
10082 micromips_label_expr (&expr1
);
10083 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10084 macro_build (NULL
, "nop", "");
10085 macro_build (ep
, call
? "bal" : "b", "p");
10087 /* Set to true so that append_insn adds a label. */
10088 emit_branch_likely_macro
= true;
10092 macro_build (ep
, br
, fmt
, sreg
, treg
);
10093 macro_build (NULL
, "nop", "");
10098 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10099 the condition code tested. EP specifies the branch target. */
10102 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10104 const int call
= 0;
10129 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10132 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10133 the register tested. EP specifies the branch target. */
10136 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10138 const char *brneg
= NULL
;
10148 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10152 gas_assert (mips_opts
.micromips
);
10153 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10161 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10168 br
= mips_opts
.micromips
? "blez" : "blezl";
10175 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10179 gas_assert (mips_opts
.micromips
);
10180 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10187 if (mips_opts
.micromips
&& brneg
)
10188 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10190 macro_build (ep
, br
, "s,p", sreg
);
10193 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10194 TREG as the registers tested. EP specifies the branch target. */
10197 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10198 unsigned int sreg
, unsigned int treg
)
10200 const char *brneg
= NULL
;
10201 const int call
= 0;
10212 br
= mips_opts
.micromips
? "beq" : "beql";
10221 br
= mips_opts
.micromips
? "bne" : "bnel";
10227 if (mips_opts
.micromips
&& brneg
)
10228 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10230 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10233 /* Return the high part that should be loaded in order to make the low
10234 part of VALUE accessible using an offset of OFFBITS bits. */
10237 offset_high_part (offsetT value
, unsigned int offbits
)
10244 bias
= 1 << (offbits
- 1);
10245 low_mask
= bias
* 2 - 1;
10246 return (value
+ bias
) & ~low_mask
;
10249 /* Return true if the value stored in offset_expr and offset_reloc
10250 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10251 amount that the caller wants to add without inducing overflow
10252 and ALIGN is the known alignment of the value in bytes. */
10255 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10259 /* Accept any relocation operator if overflow isn't a concern. */
10260 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10263 /* These relocations are guaranteed not to overflow in correct links. */
10264 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10265 || gprel16_reloc_p (*offset_reloc
))
10268 if (offset_expr
.X_op
== O_constant
10269 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10270 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10277 * This routine implements the seemingly endless macro or synthesized
10278 * instructions and addressing modes in the mips assembly language. Many
10279 * of these macros are simple and are similar to each other. These could
10280 * probably be handled by some kind of table or grammar approach instead of
10281 * this verbose method. Others are not simple macros but are more like
10282 * optimizing code generation.
10283 * One interesting optimization is when several store macros appear
10284 * consecutively that would load AT with the upper half of the same address.
10285 * The ensuing load upper instructions are omitted. This implies some kind
10286 * of global optimization. We currently only optimize within a single macro.
10287 * For many of the load and store macros if the address is specified as a
10288 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10289 * first load register 'at' with zero and use it as the base register. The
10290 * mips assembler simply uses register $zero. Just one tiny optimization
10294 macro (struct mips_cl_insn
*ip
, char *str
)
10296 const struct mips_operand_array
*operands
;
10297 unsigned int breg
, i
;
10298 unsigned int tempreg
;
10301 expressionS label_expr
;
10316 int ll_sc_paired
= 0;
10319 int hold_mips_optimize
;
10320 unsigned int align
;
10321 unsigned int op
[MAX_OPERANDS
];
10323 gas_assert (! mips_opts
.mips16
);
10325 operands
= insn_operands (ip
);
10326 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10327 if (operands
->operand
[i
])
10328 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10332 mask
= ip
->insn_mo
->mask
;
10334 label_expr
.X_op
= O_constant
;
10335 label_expr
.X_op_symbol
= NULL
;
10336 label_expr
.X_add_symbol
= NULL
;
10337 label_expr
.X_add_number
= 0;
10339 expr1
.X_op
= O_constant
;
10340 expr1
.X_op_symbol
= NULL
;
10341 expr1
.X_add_symbol
= NULL
;
10342 expr1
.X_add_number
= 1;
10349 /* Fall through. */
10357 start_noreorder ();
10359 if (mips_opts
.micromips
)
10360 micromips_label_expr (&label_expr
);
10362 label_expr
.X_add_number
= 8;
10363 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10364 if (op
[0] == op
[1])
10365 macro_build (NULL
, "nop", "");
10367 move_register (op
[0], op
[1]);
10368 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10369 if (mips_opts
.micromips
)
10370 micromips_add_label ();
10378 if (ISA_IS_R6 (mips_opts
.isa
))
10390 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
10392 if (imm_expr
.X_add_number
>= -0x200
10393 && imm_expr
.X_add_number
< 0x200
10394 && !ISA_IS_R6 (mips_opts
.isa
))
10396 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10397 (int) imm_expr
.X_add_number
);
10406 if (imm_expr
.X_add_number
>= -0x8000
10407 && imm_expr
.X_add_number
< 0x8000)
10409 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10414 load_register (AT
, &imm_expr
, dbl
);
10415 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10434 if (imm_expr
.X_add_number
>= 0
10435 && imm_expr
.X_add_number
< 0x10000)
10437 if (mask
!= M_NOR_I
)
10438 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10441 macro_build (&imm_expr
, "ori", "t,r,i",
10442 op
[0], op
[1], BFD_RELOC_LO16
);
10443 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10449 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10450 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10454 switch (imm_expr
.X_add_number
)
10457 macro_build (NULL
, "nop", "");
10460 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10464 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10465 (int) imm_expr
.X_add_number
);
10468 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10469 (unsigned long) imm_expr
.X_add_number
);
10478 gas_assert (mips_opts
.micromips
);
10479 macro_build_branch_ccl (mask
, &offset_expr
,
10480 EXTRACT_OPERAND (1, BCC
, *ip
));
10487 if (imm_expr
.X_add_number
== 0)
10493 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10495 /* Fall through. */
10498 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10503 /* Fall through. */
10506 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10507 else if (op
[0] == 0)
10508 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10512 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10513 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10514 &offset_expr
, AT
, ZERO
);
10524 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10529 /* Fall through. */
10531 /* Check for > max integer. */
10532 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10535 /* Result is always false. */
10537 macro_build (NULL
, "nop", "");
10539 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10542 ++imm_expr
.X_add_number
;
10543 /* Fall through. */
10546 if (mask
== M_BGEL_I
)
10548 if (imm_expr
.X_add_number
== 0)
10550 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10551 &offset_expr
, op
[0]);
10554 if (imm_expr
.X_add_number
== 1)
10556 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10557 &offset_expr
, op
[0]);
10560 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10563 /* Result is always true. */
10564 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10565 macro_build (&offset_expr
, "b", "p");
10570 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10571 &offset_expr
, AT
, ZERO
);
10576 /* Fall through. */
10580 else if (op
[0] == 0)
10581 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10582 &offset_expr
, ZERO
, op
[1]);
10586 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10587 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10588 &offset_expr
, AT
, ZERO
);
10594 /* Fall through. */
10598 && imm_expr
.X_add_number
== -1))
10600 ++imm_expr
.X_add_number
;
10601 /* Fall through. */
10604 if (mask
== M_BGEUL_I
)
10606 if (imm_expr
.X_add_number
== 0)
10608 else if (imm_expr
.X_add_number
== 1)
10609 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10610 &offset_expr
, op
[0], ZERO
);
10615 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10616 &offset_expr
, AT
, ZERO
);
10622 /* Fall through. */
10625 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10626 else if (op
[0] == 0)
10627 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10631 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10632 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10633 &offset_expr
, AT
, ZERO
);
10639 /* Fall through. */
10642 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10643 &offset_expr
, op
[0], ZERO
);
10644 else if (op
[0] == 0)
10649 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10650 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10651 &offset_expr
, AT
, ZERO
);
10657 /* Fall through. */
10660 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10661 else if (op
[0] == 0)
10662 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10666 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10667 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10668 &offset_expr
, AT
, ZERO
);
10674 /* Fall through. */
10676 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10678 ++imm_expr
.X_add_number
;
10679 /* Fall through. */
10682 if (mask
== M_BLTL_I
)
10684 if (imm_expr
.X_add_number
== 0)
10685 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10686 else if (imm_expr
.X_add_number
== 1)
10687 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10692 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10693 &offset_expr
, AT
, ZERO
);
10699 /* Fall through. */
10702 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10703 &offset_expr
, op
[0], ZERO
);
10704 else if (op
[0] == 0)
10709 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10710 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10711 &offset_expr
, AT
, ZERO
);
10717 /* Fall through. */
10721 && imm_expr
.X_add_number
== -1))
10723 ++imm_expr
.X_add_number
;
10724 /* Fall through. */
10727 if (mask
== M_BLTUL_I
)
10729 if (imm_expr
.X_add_number
== 0)
10731 else if (imm_expr
.X_add_number
== 1)
10732 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10733 &offset_expr
, op
[0], ZERO
);
10738 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10739 &offset_expr
, AT
, ZERO
);
10745 /* Fall through. */
10748 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10749 else if (op
[0] == 0)
10750 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10754 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10755 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10756 &offset_expr
, AT
, ZERO
);
10762 /* Fall through. */
10766 else if (op
[0] == 0)
10767 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10768 &offset_expr
, ZERO
, op
[1]);
10772 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10773 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10774 &offset_expr
, AT
, ZERO
);
10780 /* Fall through. */
10786 /* Fall through. */
10792 as_warn (_("divide by zero"));
10794 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10796 macro_build (NULL
, "break", BRK_FMT
, 7);
10800 start_noreorder ();
10803 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10804 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10808 if (mips_opts
.micromips
)
10809 micromips_label_expr (&label_expr
);
10811 label_expr
.X_add_number
= 8;
10812 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10813 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10814 macro_build (NULL
, "break", BRK_FMT
, 7);
10815 if (mips_opts
.micromips
)
10816 micromips_add_label ();
10818 expr1
.X_add_number
= -1;
10820 load_register (AT
, &expr1
, dbl
);
10821 if (mips_opts
.micromips
)
10822 micromips_label_expr (&label_expr
);
10824 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10825 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10828 expr1
.X_add_number
= 1;
10829 load_register (AT
, &expr1
, dbl
);
10830 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10834 expr1
.X_add_number
= 0x80000000;
10835 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10839 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10840 /* We want to close the noreorder block as soon as possible, so
10841 that later insns are available for delay slot filling. */
10846 if (mips_opts
.micromips
)
10847 micromips_label_expr (&label_expr
);
10849 label_expr
.X_add_number
= 8;
10850 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10851 macro_build (NULL
, "nop", "");
10853 /* We want to close the noreorder block as soon as possible, so
10854 that later insns are available for delay slot filling. */
10857 macro_build (NULL
, "break", BRK_FMT
, 6);
10859 if (mips_opts
.micromips
)
10860 micromips_add_label ();
10861 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10900 if (imm_expr
.X_add_number
== 0)
10902 as_warn (_("divide by zero"));
10904 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10906 macro_build (NULL
, "break", BRK_FMT
, 7);
10909 if (imm_expr
.X_add_number
== 1)
10911 if (strcmp (s2
, "mflo") == 0)
10912 move_register (op
[0], op
[1]);
10914 move_register (op
[0], ZERO
);
10917 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10919 if (strcmp (s2
, "mflo") == 0)
10920 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10922 move_register (op
[0], ZERO
);
10927 load_register (AT
, &imm_expr
, dbl
);
10928 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10929 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10948 start_noreorder ();
10951 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10952 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10953 /* We want to close the noreorder block as soon as possible, so
10954 that later insns are available for delay slot filling. */
10959 if (mips_opts
.micromips
)
10960 micromips_label_expr (&label_expr
);
10962 label_expr
.X_add_number
= 8;
10963 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10964 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10966 /* We want to close the noreorder block as soon as possible, so
10967 that later insns are available for delay slot filling. */
10969 macro_build (NULL
, "break", BRK_FMT
, 7);
10970 if (mips_opts
.micromips
)
10971 micromips_add_label ();
10973 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10978 /* Fall through. */
10984 /* Fall through. */
10987 /* Load the address of a symbol into a register. If breg is not
10988 zero, we then add a base register to it. */
10991 if (dbl
&& GPR_SIZE
== 32)
10992 as_warn (_("dla used to load 32-bit register; recommend using la "
10995 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10996 as_warn (_("la used to load 64-bit address; recommend using dla "
10999 if (small_offset_p (0, align
, 16))
11001 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
11002 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11006 if (mips_opts
.at
&& (op
[0] == breg
))
11014 if (offset_expr
.X_op
!= O_symbol
11015 && offset_expr
.X_op
!= O_constant
)
11017 as_bad (_("expression too complex"));
11018 offset_expr
.X_op
= O_constant
;
11021 if (offset_expr
.X_op
== O_constant
)
11022 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
11023 else if (mips_pic
== NO_PIC
)
11025 /* If this is a reference to a GP relative symbol, we want
11026 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11028 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11029 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11030 If we have a constant, we need two instructions anyhow,
11031 so we may as well always use the latter form.
11033 With 64bit address space and a usable $at we want
11034 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11035 lui $at,<sym> (BFD_RELOC_HI16_S)
11036 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11037 daddiu $at,<sym> (BFD_RELOC_LO16)
11039 daddu $tempreg,$tempreg,$at
11041 If $at is already in use, we use a path which is suboptimal
11042 on superscalar processors.
11043 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11044 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11046 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11048 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11050 For GP relative symbols in 64bit address space we can use
11051 the same sequence as in 32bit address space. */
11052 if (HAVE_64BIT_SYMBOLS
)
11054 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11055 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11057 relax_start (offset_expr
.X_add_symbol
);
11058 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11059 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11063 if (used_at
== 0 && mips_opts
.at
)
11065 macro_build (&offset_expr
, "lui", LUI_FMT
,
11066 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11067 macro_build (&offset_expr
, "lui", LUI_FMT
,
11068 AT
, BFD_RELOC_HI16_S
);
11069 macro_build (&offset_expr
, "daddiu", "t,r,j",
11070 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11071 macro_build (&offset_expr
, "daddiu", "t,r,j",
11072 AT
, AT
, BFD_RELOC_LO16
);
11073 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11074 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11079 macro_build (&offset_expr
, "lui", LUI_FMT
,
11080 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11081 macro_build (&offset_expr
, "daddiu", "t,r,j",
11082 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11083 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11084 macro_build (&offset_expr
, "daddiu", "t,r,j",
11085 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11086 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11087 macro_build (&offset_expr
, "daddiu", "t,r,j",
11088 tempreg
, tempreg
, BFD_RELOC_LO16
);
11091 if (mips_relax
.sequence
)
11096 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11097 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11099 relax_start (offset_expr
.X_add_symbol
);
11100 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11101 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11104 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11105 as_bad (_("offset too large"));
11106 macro_build_lui (&offset_expr
, tempreg
);
11107 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11108 tempreg
, tempreg
, BFD_RELOC_LO16
);
11109 if (mips_relax
.sequence
)
11113 else if (!mips_big_got
&& !HAVE_NEWABI
)
11115 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11117 /* If this is a reference to an external symbol, and there
11118 is no constant, we want
11119 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11120 or for lca or if tempreg is PIC_CALL_REG
11121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11122 For a local symbol, we want
11123 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11125 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11127 If we have a small constant, and this is a reference to
11128 an external symbol, we want
11129 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11131 addiu $tempreg,$tempreg,<constant>
11132 For a local symbol, we want the same instruction
11133 sequence, but we output a BFD_RELOC_LO16 reloc on the
11136 If we have a large constant, and this is a reference to
11137 an external symbol, we want
11138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11139 lui $at,<hiconstant>
11140 addiu $at,$at,<loconstant>
11141 addu $tempreg,$tempreg,$at
11142 For a local symbol, we want the same instruction
11143 sequence, but we output a BFD_RELOC_LO16 reloc on the
11147 if (offset_expr
.X_add_number
== 0)
11149 if (mips_pic
== SVR4_PIC
11151 && (call
|| tempreg
== PIC_CALL_REG
))
11152 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11154 relax_start (offset_expr
.X_add_symbol
);
11155 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11156 lw_reloc_type
, mips_gp_register
);
11159 /* We're going to put in an addu instruction using
11160 tempreg, so we may as well insert the nop right
11165 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11166 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11168 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11169 tempreg
, tempreg
, BFD_RELOC_LO16
);
11171 /* FIXME: If breg == 0, and the next instruction uses
11172 $tempreg, then if this variant case is used an extra
11173 nop will be generated. */
11175 else if (offset_expr
.X_add_number
>= -0x8000
11176 && offset_expr
.X_add_number
< 0x8000)
11178 load_got_offset (tempreg
, &offset_expr
);
11180 add_got_offset (tempreg
, &offset_expr
);
11184 expr1
.X_add_number
= offset_expr
.X_add_number
;
11185 offset_expr
.X_add_number
=
11186 SEXT_16BIT (offset_expr
.X_add_number
);
11187 load_got_offset (tempreg
, &offset_expr
);
11188 offset_expr
.X_add_number
= expr1
.X_add_number
;
11189 /* If we are going to add in a base register, and the
11190 target register and the base register are the same,
11191 then we are using AT as a temporary register. Since
11192 we want to load the constant into AT, we add our
11193 current AT (from the global offset table) and the
11194 register into the register now, and pretend we were
11195 not using a base register. */
11199 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11204 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11208 else if (!mips_big_got
&& HAVE_NEWABI
)
11210 int add_breg_early
= 0;
11212 /* If this is a reference to an external, and there is no
11213 constant, or local symbol (*), with or without a
11215 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11216 or for lca or if tempreg is PIC_CALL_REG
11217 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11219 If we have a small constant, and this is a reference to
11220 an external symbol, we want
11221 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11222 addiu $tempreg,$tempreg,<constant>
11224 If we have a large constant, and this is a reference to
11225 an external symbol, we want
11226 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11227 lui $at,<hiconstant>
11228 addiu $at,$at,<loconstant>
11229 addu $tempreg,$tempreg,$at
11231 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11232 local symbols, even though it introduces an additional
11235 if (offset_expr
.X_add_number
)
11237 expr1
.X_add_number
= offset_expr
.X_add_number
;
11238 offset_expr
.X_add_number
= 0;
11240 relax_start (offset_expr
.X_add_symbol
);
11241 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11242 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11244 if (expr1
.X_add_number
>= -0x8000
11245 && expr1
.X_add_number
< 0x8000)
11247 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11248 tempreg
, tempreg
, BFD_RELOC_LO16
);
11250 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11254 /* If we are going to add in a base register, and the
11255 target register and the base register are the same,
11256 then we are using AT as a temporary register. Since
11257 we want to load the constant into AT, we add our
11258 current AT (from the global offset table) and the
11259 register into the register now, and pretend we were
11260 not using a base register. */
11265 gas_assert (tempreg
== AT
);
11266 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11269 add_breg_early
= 1;
11272 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11273 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11279 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11282 offset_expr
.X_add_number
= expr1
.X_add_number
;
11284 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11285 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11286 if (add_breg_early
)
11288 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11289 op
[0], tempreg
, breg
);
11295 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11297 relax_start (offset_expr
.X_add_symbol
);
11298 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11299 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11301 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11302 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11307 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11308 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11311 else if (mips_big_got
&& !HAVE_NEWABI
)
11314 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11315 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11316 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11318 /* This is the large GOT case. If this is a reference to an
11319 external symbol, and there is no constant, we want
11320 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11321 addu $tempreg,$tempreg,$gp
11322 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11323 or for lca or if tempreg is PIC_CALL_REG
11324 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11325 addu $tempreg,$tempreg,$gp
11326 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11327 For a local symbol, we want
11328 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11330 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11332 If we have a small constant, and this is a reference to
11333 an external symbol, we want
11334 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11335 addu $tempreg,$tempreg,$gp
11336 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11338 addiu $tempreg,$tempreg,<constant>
11339 For a local symbol, we want
11340 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11342 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11344 If we have a large constant, and this is a reference to
11345 an external symbol, we want
11346 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11347 addu $tempreg,$tempreg,$gp
11348 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11349 lui $at,<hiconstant>
11350 addiu $at,$at,<loconstant>
11351 addu $tempreg,$tempreg,$at
11352 For a local symbol, we want
11353 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11354 lui $at,<hiconstant>
11355 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11356 addu $tempreg,$tempreg,$at
11359 expr1
.X_add_number
= offset_expr
.X_add_number
;
11360 offset_expr
.X_add_number
= 0;
11361 relax_start (offset_expr
.X_add_symbol
);
11362 gpdelay
= reg_needs_delay (mips_gp_register
);
11363 if (expr1
.X_add_number
== 0 && breg
== 0
11364 && (call
|| tempreg
== PIC_CALL_REG
))
11366 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11367 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11369 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11370 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11371 tempreg
, tempreg
, mips_gp_register
);
11372 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11373 tempreg
, lw_reloc_type
, tempreg
);
11374 if (expr1
.X_add_number
== 0)
11378 /* We're going to put in an addu instruction using
11379 tempreg, so we may as well insert the nop right
11384 else if (expr1
.X_add_number
>= -0x8000
11385 && expr1
.X_add_number
< 0x8000)
11388 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11389 tempreg
, tempreg
, BFD_RELOC_LO16
);
11395 /* If we are going to add in a base register, and the
11396 target register and the base register are the same,
11397 then we are using AT as a temporary register. Since
11398 we want to load the constant into AT, we add our
11399 current AT (from the global offset table) and the
11400 register into the register now, and pretend we were
11401 not using a base register. */
11406 gas_assert (tempreg
== AT
);
11408 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11413 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11414 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11418 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11423 /* This is needed because this instruction uses $gp, but
11424 the first instruction on the main stream does not. */
11425 macro_build (NULL
, "nop", "");
11428 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11429 local_reloc_type
, mips_gp_register
);
11430 if (expr1
.X_add_number
>= -0x8000
11431 && expr1
.X_add_number
< 0x8000)
11434 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11435 tempreg
, tempreg
, BFD_RELOC_LO16
);
11436 /* FIXME: If add_number is 0, and there was no base
11437 register, the external symbol case ended with a load,
11438 so if the symbol turns out to not be external, and
11439 the next instruction uses tempreg, an unnecessary nop
11440 will be inserted. */
11446 /* We must add in the base register now, as in the
11447 external symbol case. */
11448 gas_assert (tempreg
== AT
);
11450 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11453 /* We set breg to 0 because we have arranged to add
11454 it in in both cases. */
11458 macro_build_lui (&expr1
, AT
);
11459 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11460 AT
, AT
, BFD_RELOC_LO16
);
11461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11462 tempreg
, tempreg
, AT
);
11467 else if (mips_big_got
&& HAVE_NEWABI
)
11469 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11470 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11471 int add_breg_early
= 0;
11473 /* This is the large GOT case. If this is a reference to an
11474 external symbol, and there is no constant, we want
11475 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11476 add $tempreg,$tempreg,$gp
11477 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11478 or for lca or if tempreg is PIC_CALL_REG
11479 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11480 add $tempreg,$tempreg,$gp
11481 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11483 If we have a small constant, and this is a reference to
11484 an external symbol, we want
11485 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11486 add $tempreg,$tempreg,$gp
11487 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11488 addi $tempreg,$tempreg,<constant>
11490 If we have a large constant, and this is a reference to
11491 an external symbol, we want
11492 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11493 addu $tempreg,$tempreg,$gp
11494 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11495 lui $at,<hiconstant>
11496 addi $at,$at,<loconstant>
11497 add $tempreg,$tempreg,$at
11499 If we have NewABI, and we know it's a local symbol, we want
11500 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11501 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11502 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11504 relax_start (offset_expr
.X_add_symbol
);
11506 expr1
.X_add_number
= offset_expr
.X_add_number
;
11507 offset_expr
.X_add_number
= 0;
11509 if (expr1
.X_add_number
== 0 && breg
== 0
11510 && (call
|| tempreg
== PIC_CALL_REG
))
11512 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11513 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11515 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11516 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11517 tempreg
, tempreg
, mips_gp_register
);
11518 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11519 tempreg
, lw_reloc_type
, tempreg
);
11521 if (expr1
.X_add_number
== 0)
11523 else if (expr1
.X_add_number
>= -0x8000
11524 && expr1
.X_add_number
< 0x8000)
11526 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11527 tempreg
, tempreg
, BFD_RELOC_LO16
);
11529 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11533 /* If we are going to add in a base register, and the
11534 target register and the base register are the same,
11535 then we are using AT as a temporary register. Since
11536 we want to load the constant into AT, we add our
11537 current AT (from the global offset table) and the
11538 register into the register now, and pretend we were
11539 not using a base register. */
11544 gas_assert (tempreg
== AT
);
11545 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11548 add_breg_early
= 1;
11551 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11552 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11557 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11560 offset_expr
.X_add_number
= expr1
.X_add_number
;
11561 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11562 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11563 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11564 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11565 if (add_breg_early
)
11567 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11568 op
[0], tempreg
, breg
);
11578 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11582 gas_assert (!mips_opts
.micromips
);
11583 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11587 gas_assert (!mips_opts
.micromips
);
11588 macro_build (NULL
, "c2", "C", 0x02);
11592 gas_assert (!mips_opts
.micromips
);
11593 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11597 gas_assert (!mips_opts
.micromips
);
11598 macro_build (NULL
, "c2", "C", 3);
11602 gas_assert (!mips_opts
.micromips
);
11603 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11607 /* The j instruction may not be used in PIC code, since it
11608 requires an absolute address. We convert it to a b
11610 if (mips_pic
== NO_PIC
)
11611 macro_build (&offset_expr
, "j", "a");
11613 macro_build (&offset_expr
, "b", "p");
11616 /* The jal instructions must be handled as macros because when
11617 generating PIC code they expand to multi-instruction
11618 sequences. Normally they are simple instructions. */
11622 /* Fall through. */
11624 gas_assert (mips_opts
.micromips
);
11625 if (mips_opts
.insn32
)
11627 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11635 /* Fall through. */
11638 if (mips_pic
== NO_PIC
)
11640 s
= jals
? "jalrs" : "jalr";
11641 if (mips_opts
.micromips
11642 && !mips_opts
.insn32
11644 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11645 macro_build (NULL
, s
, "mj", op
[1]);
11647 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11651 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11652 && mips_cprestore_offset
>= 0);
11654 if (op
[1] != PIC_CALL_REG
)
11655 as_warn (_("MIPS PIC call to register other than $25"));
11657 s
= ((mips_opts
.micromips
11658 && !mips_opts
.insn32
11659 && (!mips_opts
.noreorder
|| cprestore
))
11660 ? "jalrs" : "jalr");
11661 if (mips_opts
.micromips
11662 && !mips_opts
.insn32
11664 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11665 macro_build (NULL
, s
, "mj", op
[1]);
11667 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11668 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11670 if (mips_cprestore_offset
< 0)
11671 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11674 if (!mips_frame_reg_valid
)
11676 as_warn (_("no .frame pseudo-op used in PIC code"));
11677 /* Quiet this warning. */
11678 mips_frame_reg_valid
= 1;
11680 if (!mips_cprestore_valid
)
11682 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11683 /* Quiet this warning. */
11684 mips_cprestore_valid
= 1;
11686 if (mips_opts
.noreorder
)
11687 macro_build (NULL
, "nop", "");
11688 expr1
.X_add_number
= mips_cprestore_offset
;
11689 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11692 HAVE_64BIT_ADDRESSES
);
11700 gas_assert (mips_opts
.micromips
);
11701 if (mips_opts
.insn32
)
11703 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11707 /* Fall through. */
11709 if (mips_pic
== NO_PIC
)
11710 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11711 else if (mips_pic
== SVR4_PIC
)
11713 /* If this is a reference to an external symbol, and we are
11714 using a small GOT, we want
11715 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11719 lw $gp,cprestore($sp)
11720 The cprestore value is set using the .cprestore
11721 pseudo-op. If we are using a big GOT, we want
11722 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11724 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11728 lw $gp,cprestore($sp)
11729 If the symbol is not external, we want
11730 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11732 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11735 lw $gp,cprestore($sp)
11737 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11738 sequences above, minus nops, unless the symbol is local,
11739 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11745 relax_start (offset_expr
.X_add_symbol
);
11746 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11747 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11750 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11751 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11757 relax_start (offset_expr
.X_add_symbol
);
11758 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11759 BFD_RELOC_MIPS_CALL_HI16
);
11760 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11761 PIC_CALL_REG
, mips_gp_register
);
11762 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11763 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11766 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11767 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11769 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11770 PIC_CALL_REG
, PIC_CALL_REG
,
11771 BFD_RELOC_MIPS_GOT_OFST
);
11775 macro_build_jalr (&offset_expr
, 0);
11779 relax_start (offset_expr
.X_add_symbol
);
11782 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11783 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11792 gpdelay
= reg_needs_delay (mips_gp_register
);
11793 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11794 BFD_RELOC_MIPS_CALL_HI16
);
11795 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11796 PIC_CALL_REG
, mips_gp_register
);
11797 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11798 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11803 macro_build (NULL
, "nop", "");
11805 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11806 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11809 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11810 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11812 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11814 if (mips_cprestore_offset
< 0)
11815 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11818 if (!mips_frame_reg_valid
)
11820 as_warn (_("no .frame pseudo-op used in PIC code"));
11821 /* Quiet this warning. */
11822 mips_frame_reg_valid
= 1;
11824 if (!mips_cprestore_valid
)
11826 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11827 /* Quiet this warning. */
11828 mips_cprestore_valid
= 1;
11830 if (mips_opts
.noreorder
)
11831 macro_build (NULL
, "nop", "");
11832 expr1
.X_add_number
= mips_cprestore_offset
;
11833 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11836 HAVE_64BIT_ADDRESSES
);
11840 else if (mips_pic
== VXWORKS_PIC
)
11841 as_bad (_("non-PIC jump used in PIC library"));
11948 gas_assert (!mips_opts
.micromips
);
11951 /* Itbl support may require additional care here. */
11957 /* Itbl support may require additional care here. */
11963 offbits
= (mips_opts
.micromips
? 12
11964 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11966 /* Itbl support may require additional care here. */
11970 gas_assert (!mips_opts
.micromips
);
11973 /* Itbl support may require additional care here. */
11979 offbits
= (mips_opts
.micromips
? 12 : 16);
11984 offbits
= (mips_opts
.micromips
? 12 : 16);
11989 /* Itbl support may require additional care here. */
11995 offbits
= (mips_opts
.micromips
? 12
11996 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11998 /* Itbl support may require additional care here. */
12004 /* Itbl support may require additional care here. */
12010 /* Itbl support may require additional care here. */
12016 offbits
= (mips_opts
.micromips
? 12 : 16);
12021 offbits
= (mips_opts
.micromips
? 12 : 16);
12026 offbits
= (mips_opts
.micromips
? 12
12027 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12033 offbits
= (mips_opts
.micromips
? 12
12034 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12040 offbits
= (mips_opts
.micromips
? 12 : 16);
12043 gas_assert (mips_opts
.micromips
);
12050 gas_assert (mips_opts
.micromips
);
12059 s
= ip
->insn_mo
->name
;
12065 gas_assert (mips_opts
.micromips
);
12071 gas_assert (mips_opts
.micromips
);
12078 /* Try to use one the the load registers to compute the base address.
12079 We don't want to use $0 as tempreg. */
12082 if ((op
[0] == ZERO
&& op
[3] == op
[1])
12083 || (op
[1] == ZERO
&& op
[3] == op
[0])
12084 || (op
[0] == ZERO
&& op
[1] == ZERO
))
12086 else if (op
[0] != op
[3] && op
[0] != ZERO
)
12093 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12096 tempreg
= op
[0] + lp
;
12113 gas_assert (!mips_opts
.micromips
);
12116 /* Itbl support may require additional care here. */
12122 /* Itbl support may require additional care here. */
12128 offbits
= (mips_opts
.micromips
? 12
12129 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12131 /* Itbl support may require additional care here. */
12135 gas_assert (!mips_opts
.micromips
);
12138 /* Itbl support may require additional care here. */
12144 offbits
= (mips_opts
.micromips
? 12 : 16);
12149 offbits
= (mips_opts
.micromips
? 12 : 16);
12154 offbits
= (mips_opts
.micromips
? 12
12155 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12161 offbits
= (mips_opts
.micromips
? 12
12162 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12168 s
= ip
->insn_mo
->name
;
12175 fmt
= (mips_opts
.micromips
? "k,~(b)"
12176 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12178 offbits
= (mips_opts
.micromips
? 12
12179 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12189 fmt
= (mips_opts
.micromips
? "k,~(b)"
12190 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12192 offbits
= (mips_opts
.micromips
? 12
12193 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12205 /* Itbl support may require additional care here. */
12210 offbits
= (mips_opts
.micromips
? 12
12211 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12213 /* Itbl support may require additional care here. */
12219 /* Itbl support may require additional care here. */
12223 gas_assert (!mips_opts
.micromips
);
12226 /* Itbl support may require additional care here. */
12232 offbits
= (mips_opts
.micromips
? 12 : 16);
12237 offbits
= (mips_opts
.micromips
? 12 : 16);
12240 gas_assert (mips_opts
.micromips
);
12246 gas_assert (mips_opts
.micromips
);
12252 gas_assert (mips_opts
.micromips
);
12258 gas_assert (mips_opts
.micromips
);
12266 breg
= ll_sc_paired
? op
[3] : op
[2];
12267 if (small_offset_p (0, align
, 16))
12269 /* The first case exists for M_LD_AB and M_SD_AB, which are
12270 macros for o32 but which should act like normal instructions
12273 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12274 offset_reloc
[1], offset_reloc
[2], breg
);
12275 else if (small_offset_p (0, align
, offbits
))
12280 macro_build (NULL
, s
, fmt
, op
[0], op
[1], breg
);
12282 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12285 macro_build (NULL
, s
, fmt
, op
[0],
12286 (int) offset_expr
.X_add_number
, breg
);
12292 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12293 tempreg
, breg
, -1, offset_reloc
[0],
12294 offset_reloc
[1], offset_reloc
[2]);
12298 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12300 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12303 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12311 if (offset_expr
.X_op
!= O_constant
12312 && offset_expr
.X_op
!= O_symbol
)
12314 as_bad (_("expression too complex"));
12315 offset_expr
.X_op
= O_constant
;
12318 if (HAVE_32BIT_ADDRESSES
12319 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12323 sprintf_vma (value
, offset_expr
.X_add_number
);
12324 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12327 /* A constant expression in PIC code can be handled just as it
12328 is in non PIC code. */
12329 if (offset_expr
.X_op
== O_constant
)
12331 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12332 offbits
== 0 ? 16 : offbits
);
12333 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12335 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12337 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12338 tempreg
, tempreg
, breg
);
12341 if (offset_expr
.X_add_number
!= 0)
12342 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12343 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12345 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12347 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12349 else if (offbits
== 16)
12350 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12352 macro_build (NULL
, s
, fmt
, op
[0],
12353 (int) offset_expr
.X_add_number
, tempreg
);
12355 else if (offbits
!= 16)
12357 /* The offset field is too narrow to be used for a low-part
12358 relocation, so load the whole address into the auxiliary
12360 load_address (tempreg
, &offset_expr
, &used_at
);
12362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12363 tempreg
, tempreg
, breg
);
12367 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12369 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12372 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12374 else if (mips_pic
== NO_PIC
)
12376 /* If this is a reference to a GP relative symbol, and there
12377 is no base register, we want
12378 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12379 Otherwise, if there is no base register, we want
12380 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12381 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12382 If we have a constant, we need two instructions anyhow,
12383 so we always use the latter form.
12385 If we have a base register, and this is a reference to a
12386 GP relative symbol, we want
12387 addu $tempreg,$breg,$gp
12388 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12390 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12391 addu $tempreg,$tempreg,$breg
12392 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12393 With a constant we always use the latter case.
12395 With 64bit address space and no base register and $at usable,
12397 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12398 lui $at,<sym> (BFD_RELOC_HI16_S)
12399 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12402 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12403 If we have a base register, we want
12404 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12405 lui $at,<sym> (BFD_RELOC_HI16_S)
12406 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12410 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12412 Without $at we can't generate the optimal path for superscalar
12413 processors here since this would require two temporary registers.
12414 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12415 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12417 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12419 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12420 If we have a base register, we want
12421 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12422 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12424 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12426 daddu $tempreg,$tempreg,$breg
12427 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12429 For GP relative symbols in 64bit address space we can use
12430 the same sequence as in 32bit address space. */
12431 if (HAVE_64BIT_SYMBOLS
)
12433 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12434 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12436 relax_start (offset_expr
.X_add_symbol
);
12439 macro_build (&offset_expr
, s
, fmt
, op
[0],
12440 BFD_RELOC_GPREL16
, mips_gp_register
);
12444 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12445 tempreg
, breg
, mips_gp_register
);
12446 macro_build (&offset_expr
, s
, fmt
, op
[0],
12447 BFD_RELOC_GPREL16
, tempreg
);
12452 if (used_at
== 0 && mips_opts
.at
)
12454 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12455 BFD_RELOC_MIPS_HIGHEST
);
12456 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12458 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12459 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12461 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12462 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12463 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12464 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12470 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12471 BFD_RELOC_MIPS_HIGHEST
);
12472 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12473 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12474 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12475 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12476 tempreg
, BFD_RELOC_HI16_S
);
12477 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12479 macro_build (NULL
, "daddu", "d,v,t",
12480 tempreg
, tempreg
, breg
);
12481 macro_build (&offset_expr
, s
, fmt
, op
[0],
12482 BFD_RELOC_LO16
, tempreg
);
12485 if (mips_relax
.sequence
)
12492 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12493 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12495 relax_start (offset_expr
.X_add_symbol
);
12496 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12500 macro_build_lui (&offset_expr
, tempreg
);
12501 macro_build (&offset_expr
, s
, fmt
, op
[0],
12502 BFD_RELOC_LO16
, tempreg
);
12503 if (mips_relax
.sequence
)
12508 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12509 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12511 relax_start (offset_expr
.X_add_symbol
);
12512 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12513 tempreg
, breg
, mips_gp_register
);
12514 macro_build (&offset_expr
, s
, fmt
, op
[0],
12515 BFD_RELOC_GPREL16
, tempreg
);
12518 macro_build_lui (&offset_expr
, tempreg
);
12519 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12520 tempreg
, tempreg
, breg
);
12521 macro_build (&offset_expr
, s
, fmt
, op
[0],
12522 BFD_RELOC_LO16
, tempreg
);
12523 if (mips_relax
.sequence
)
12527 else if (!mips_big_got
)
12529 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12531 /* If this is a reference to an external symbol, we want
12532 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12534 <op> op[0],0($tempreg)
12536 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12538 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12539 <op> op[0],0($tempreg)
12541 For NewABI, we want
12542 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12543 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12545 If there is a base register, we add it to $tempreg before
12546 the <op>. If there is a constant, we stick it in the
12547 <op> instruction. We don't handle constants larger than
12548 16 bits, because we have no way to load the upper 16 bits
12549 (actually, we could handle them for the subset of cases
12550 in which we are not using $at). */
12551 gas_assert (offset_expr
.X_op
== O_symbol
);
12554 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12555 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12557 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12558 tempreg
, tempreg
, breg
);
12559 macro_build (&offset_expr
, s
, fmt
, op
[0],
12560 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12563 expr1
.X_add_number
= offset_expr
.X_add_number
;
12564 offset_expr
.X_add_number
= 0;
12565 if (expr1
.X_add_number
< -0x8000
12566 || expr1
.X_add_number
>= 0x8000)
12567 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12568 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12569 lw_reloc_type
, mips_gp_register
);
12571 relax_start (offset_expr
.X_add_symbol
);
12573 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12574 tempreg
, BFD_RELOC_LO16
);
12577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12578 tempreg
, tempreg
, breg
);
12579 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12581 else if (mips_big_got
&& !HAVE_NEWABI
)
12585 /* If this is a reference to an external symbol, we want
12586 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12587 addu $tempreg,$tempreg,$gp
12588 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12589 <op> op[0],0($tempreg)
12591 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12593 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12594 <op> op[0],0($tempreg)
12595 If there is a base register, we add it to $tempreg before
12596 the <op>. If there is a constant, we stick it in the
12597 <op> instruction. We don't handle constants larger than
12598 16 bits, because we have no way to load the upper 16 bits
12599 (actually, we could handle them for the subset of cases
12600 in which we are not using $at). */
12601 gas_assert (offset_expr
.X_op
== O_symbol
);
12602 expr1
.X_add_number
= offset_expr
.X_add_number
;
12603 offset_expr
.X_add_number
= 0;
12604 if (expr1
.X_add_number
< -0x8000
12605 || expr1
.X_add_number
>= 0x8000)
12606 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12607 gpdelay
= reg_needs_delay (mips_gp_register
);
12608 relax_start (offset_expr
.X_add_symbol
);
12609 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12610 BFD_RELOC_MIPS_GOT_HI16
);
12611 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12613 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12614 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12617 macro_build (NULL
, "nop", "");
12618 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12619 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12621 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12622 tempreg
, BFD_RELOC_LO16
);
12626 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12627 tempreg
, tempreg
, breg
);
12628 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12630 else if (mips_big_got
&& HAVE_NEWABI
)
12632 /* If this is a reference to an external symbol, we want
12633 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12634 add $tempreg,$tempreg,$gp
12635 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12636 <op> op[0],<ofst>($tempreg)
12637 Otherwise, for local symbols, we want:
12638 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12639 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12640 gas_assert (offset_expr
.X_op
== O_symbol
);
12641 expr1
.X_add_number
= offset_expr
.X_add_number
;
12642 offset_expr
.X_add_number
= 0;
12643 if (expr1
.X_add_number
< -0x8000
12644 || expr1
.X_add_number
>= 0x8000)
12645 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12646 relax_start (offset_expr
.X_add_symbol
);
12647 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12648 BFD_RELOC_MIPS_GOT_HI16
);
12649 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12651 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12652 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12654 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12655 tempreg
, tempreg
, breg
);
12656 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12659 offset_expr
.X_add_number
= expr1
.X_add_number
;
12660 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12661 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12663 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12664 tempreg
, tempreg
, breg
);
12665 macro_build (&offset_expr
, s
, fmt
, op
[0],
12666 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12675 gas_assert (mips_opts
.micromips
);
12676 gas_assert (mips_opts
.insn32
);
12677 start_noreorder ();
12678 macro_build (NULL
, "jr", "s", RA
);
12679 expr1
.X_add_number
= op
[0] << 2;
12680 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12685 gas_assert (mips_opts
.micromips
);
12686 gas_assert (mips_opts
.insn32
);
12687 macro_build (NULL
, "jr", "s", op
[0]);
12688 if (mips_opts
.noreorder
)
12689 macro_build (NULL
, "nop", "");
12694 load_register (op
[0], &imm_expr
, 0);
12698 load_register (op
[0], &imm_expr
, 1);
12702 if (imm_expr
.X_op
== O_constant
)
12705 load_register (AT
, &imm_expr
, 0);
12706 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12711 gas_assert (imm_expr
.X_op
== O_absent
12712 && offset_expr
.X_op
== O_symbol
12713 && strcmp (segment_name (S_GET_SEGMENT
12714 (offset_expr
.X_add_symbol
)),
12716 && offset_expr
.X_add_number
== 0);
12717 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12718 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12723 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12724 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12725 order 32 bits of the value and the low order 32 bits are either
12726 zero or in OFFSET_EXPR. */
12727 if (imm_expr
.X_op
== O_constant
)
12729 if (GPR_SIZE
== 64)
12730 load_register (op
[0], &imm_expr
, 1);
12735 if (target_big_endian
)
12747 load_register (hreg
, &imm_expr
, 0);
12750 if (offset_expr
.X_op
== O_absent
)
12751 move_register (lreg
, 0);
12754 gas_assert (offset_expr
.X_op
== O_constant
);
12755 load_register (lreg
, &offset_expr
, 0);
12761 gas_assert (imm_expr
.X_op
== O_absent
);
12763 /* We know that sym is in the .rdata section. First we get the
12764 upper 16 bits of the address. */
12765 if (mips_pic
== NO_PIC
)
12767 macro_build_lui (&offset_expr
, AT
);
12772 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12773 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12777 /* Now we load the register(s). */
12778 if (GPR_SIZE
== 64)
12781 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12782 BFD_RELOC_LO16
, AT
);
12787 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12788 BFD_RELOC_LO16
, AT
);
12791 /* FIXME: How in the world do we deal with the possible
12793 offset_expr
.X_add_number
+= 4;
12794 macro_build (&offset_expr
, "lw", "t,o(b)",
12795 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12801 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12802 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12803 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12804 the value and the low order 32 bits are either zero or in
12806 if (imm_expr
.X_op
== O_constant
)
12809 if (((FPR_SIZE
== 64 && GPR_SIZE
== 64)
12810 || !ISA_HAS_MXHC1 (mips_opts
.isa
))
12811 && imm_expr
.X_add_number
!= 0)
12815 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12817 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12818 macro_build (NULL
, "dmtc1", "t,S", tempreg
, op
[0]);
12821 if (!ISA_HAS_MXHC1 (mips_opts
.isa
))
12823 if (FPR_SIZE
!= 32)
12824 as_bad (_("Unable to generate `%s' compliant code "
12826 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12828 macro_build (NULL
, "mtc1", "t,G", tempreg
, op
[0] + 1);
12830 if (offset_expr
.X_op
== O_absent
)
12831 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12834 gas_assert (offset_expr
.X_op
== O_constant
);
12835 load_register (AT
, &offset_expr
, 0);
12836 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12838 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12840 if (imm_expr
.X_add_number
!= 0)
12844 load_register (AT
, &imm_expr
, 0);
12846 macro_build (NULL
, "mthc1", "t,G", tempreg
, op
[0]);
12852 gas_assert (imm_expr
.X_op
== O_absent
12853 && offset_expr
.X_op
== O_symbol
12854 && offset_expr
.X_add_number
== 0);
12855 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12856 if (strcmp (s
, ".lit8") == 0)
12858 op
[2] = mips_gp_register
;
12859 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12860 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12861 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12865 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12867 if (mips_pic
!= NO_PIC
)
12868 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12869 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12872 /* FIXME: This won't work for a 64 bit address. */
12873 macro_build_lui (&offset_expr
, AT
);
12877 offset_reloc
[0] = BFD_RELOC_LO16
;
12878 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12879 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12882 /* Fall through. */
12885 /* The MIPS assembler seems to check for X_add_number not
12886 being double aligned and generating:
12889 addiu at,at,%lo(foo+1)
12892 But, the resulting address is the same after relocation so why
12893 generate the extra instruction? */
12894 /* Itbl support may require additional care here. */
12897 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12906 gas_assert (!mips_opts
.micromips
);
12907 /* Itbl support may require additional care here. */
12910 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12930 if (GPR_SIZE
== 64)
12940 if (GPR_SIZE
== 64)
12948 /* Even on a big endian machine $fn comes before $fn+1. We have
12949 to adjust when loading from memory. We set coproc if we must
12950 load $fn+1 first. */
12951 /* Itbl support may require additional care here. */
12952 if (!target_big_endian
)
12956 if (small_offset_p (0, align
, 16))
12959 if (!small_offset_p (4, align
, 16))
12961 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12962 -1, offset_reloc
[0], offset_reloc
[1],
12964 expr1
.X_add_number
= 0;
12968 offset_reloc
[0] = BFD_RELOC_LO16
;
12969 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12970 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12972 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12974 ep
->X_add_number
+= 4;
12975 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12976 offset_reloc
[1], offset_reloc
[2], breg
);
12977 ep
->X_add_number
-= 4;
12978 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12979 offset_reloc
[1], offset_reloc
[2], breg
);
12983 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12984 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12986 ep
->X_add_number
+= 4;
12987 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12988 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12994 if (offset_expr
.X_op
!= O_symbol
12995 && offset_expr
.X_op
!= O_constant
)
12997 as_bad (_("expression too complex"));
12998 offset_expr
.X_op
= O_constant
;
13001 if (HAVE_32BIT_ADDRESSES
13002 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
13006 sprintf_vma (value
, offset_expr
.X_add_number
);
13007 as_bad (_("number (0x%s) larger than 32 bits"), value
);
13010 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
13012 /* If this is a reference to a GP relative symbol, we want
13013 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
13014 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
13015 If we have a base register, we use this
13017 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
13018 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
13019 If this is not a GP relative symbol, we want
13020 lui $at,<sym> (BFD_RELOC_HI16_S)
13021 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13022 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13023 If there is a base register, we add it to $at after the
13024 lui instruction. If there is a constant, we always use
13026 if (offset_expr
.X_op
== O_symbol
13027 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
13028 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
13030 relax_start (offset_expr
.X_add_symbol
);
13033 tempreg
= mips_gp_register
;
13037 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13038 AT
, breg
, mips_gp_register
);
13043 /* Itbl support may require additional care here. */
13044 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13045 BFD_RELOC_GPREL16
, tempreg
);
13046 offset_expr
.X_add_number
+= 4;
13048 /* Set mips_optimize to 2 to avoid inserting an
13050 hold_mips_optimize
= mips_optimize
;
13052 /* Itbl support may require additional care here. */
13053 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13054 BFD_RELOC_GPREL16
, tempreg
);
13055 mips_optimize
= hold_mips_optimize
;
13059 offset_expr
.X_add_number
-= 4;
13062 if (offset_high_part (offset_expr
.X_add_number
, 16)
13063 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
13065 load_address (AT
, &offset_expr
, &used_at
);
13066 offset_expr
.X_op
= O_constant
;
13067 offset_expr
.X_add_number
= 0;
13070 macro_build_lui (&offset_expr
, AT
);
13072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13073 /* Itbl support may require additional care here. */
13074 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13075 BFD_RELOC_LO16
, AT
);
13076 /* FIXME: How do we handle overflow here? */
13077 offset_expr
.X_add_number
+= 4;
13078 /* Itbl support may require additional care here. */
13079 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13080 BFD_RELOC_LO16
, AT
);
13081 if (mips_relax
.sequence
)
13084 else if (!mips_big_got
)
13086 /* If this is a reference to an external symbol, we want
13087 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13090 <op> op[0]+1,4($at)
13092 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13094 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13095 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13096 If there is a base register we add it to $at before the
13097 lwc1 instructions. If there is a constant we include it
13098 in the lwc1 instructions. */
13100 expr1
.X_add_number
= offset_expr
.X_add_number
;
13101 if (expr1
.X_add_number
< -0x8000
13102 || expr1
.X_add_number
>= 0x8000 - 4)
13103 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13104 load_got_offset (AT
, &offset_expr
);
13107 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13109 /* Set mips_optimize to 2 to avoid inserting an undesired
13111 hold_mips_optimize
= mips_optimize
;
13114 /* Itbl support may require additional care here. */
13115 relax_start (offset_expr
.X_add_symbol
);
13116 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13117 BFD_RELOC_LO16
, AT
);
13118 expr1
.X_add_number
+= 4;
13119 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13120 BFD_RELOC_LO16
, AT
);
13122 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13123 BFD_RELOC_LO16
, AT
);
13124 offset_expr
.X_add_number
+= 4;
13125 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13126 BFD_RELOC_LO16
, AT
);
13129 mips_optimize
= hold_mips_optimize
;
13131 else if (mips_big_got
)
13135 /* If this is a reference to an external symbol, we want
13136 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13138 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13141 <op> op[0]+1,4($at)
13143 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13145 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13146 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13147 If there is a base register we add it to $at before the
13148 lwc1 instructions. If there is a constant we include it
13149 in the lwc1 instructions. */
13151 expr1
.X_add_number
= offset_expr
.X_add_number
;
13152 offset_expr
.X_add_number
= 0;
13153 if (expr1
.X_add_number
< -0x8000
13154 || expr1
.X_add_number
>= 0x8000 - 4)
13155 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13156 gpdelay
= reg_needs_delay (mips_gp_register
);
13157 relax_start (offset_expr
.X_add_symbol
);
13158 macro_build (&offset_expr
, "lui", LUI_FMT
,
13159 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13160 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13161 AT
, AT
, mips_gp_register
);
13162 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13163 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13166 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13167 /* Itbl support may require additional care here. */
13168 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13169 BFD_RELOC_LO16
, AT
);
13170 expr1
.X_add_number
+= 4;
13172 /* Set mips_optimize to 2 to avoid inserting an undesired
13174 hold_mips_optimize
= mips_optimize
;
13176 /* Itbl support may require additional care here. */
13177 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13178 BFD_RELOC_LO16
, AT
);
13179 mips_optimize
= hold_mips_optimize
;
13180 expr1
.X_add_number
-= 4;
13183 offset_expr
.X_add_number
= expr1
.X_add_number
;
13185 macro_build (NULL
, "nop", "");
13186 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13187 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13190 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13191 /* Itbl support may require additional care here. */
13192 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13193 BFD_RELOC_LO16
, AT
);
13194 offset_expr
.X_add_number
+= 4;
13196 /* Set mips_optimize to 2 to avoid inserting an undesired
13198 hold_mips_optimize
= mips_optimize
;
13200 /* Itbl support may require additional care here. */
13201 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13202 BFD_RELOC_LO16
, AT
);
13203 mips_optimize
= hold_mips_optimize
;
13217 gas_assert (!mips_opts
.micromips
);
13222 /* New code added to support COPZ instructions.
13223 This code builds table entries out of the macros in mip_opcodes.
13224 R4000 uses interlocks to handle coproc delays.
13225 Other chips (like the R3000) require nops to be inserted for delays.
13227 FIXME: Currently, we require that the user handle delays.
13228 In order to fill delay slots for non-interlocked chips,
13229 we must have a way to specify delays based on the coprocessor.
13230 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13231 What are the side-effects of the cop instruction?
13232 What cache support might we have and what are its effects?
13233 Both coprocessor & memory require delays. how long???
13234 What registers are read/set/modified?
13236 If an itbl is provided to interpret cop instructions,
13237 this knowledge can be encoded in the itbl spec. */
13251 gas_assert (!mips_opts
.micromips
);
13252 /* For now we just do C (same as Cz). The parameter will be
13253 stored in insn_opcode by mips_ip. */
13254 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13258 move_register (op
[0], op
[1]);
13262 gas_assert (mips_opts
.micromips
);
13263 gas_assert (mips_opts
.insn32
);
13264 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13265 micromips_to_32_reg_m_map
[op
[1]]);
13266 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13267 micromips_to_32_reg_n_map
[op
[2]]);
13272 /* Fall through. */
13274 if (mips_opts
.arch
== CPU_R5900
)
13275 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13279 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13280 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13286 /* Fall through. */
13288 /* The MIPS assembler some times generates shifts and adds. I'm
13289 not trying to be that fancy. GCC should do this for us
13292 load_register (AT
, &imm_expr
, dbl
);
13293 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13294 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13299 /* Fall through. */
13306 /* Fall through. */
13309 start_noreorder ();
13312 load_register (AT
, &imm_expr
, dbl
);
13313 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13314 op
[1], imm
? AT
: op
[2]);
13315 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13316 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13317 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13319 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13322 if (mips_opts
.micromips
)
13323 micromips_label_expr (&label_expr
);
13325 label_expr
.X_add_number
= 8;
13326 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13327 macro_build (NULL
, "nop", "");
13328 macro_build (NULL
, "break", BRK_FMT
, 6);
13329 if (mips_opts
.micromips
)
13330 micromips_add_label ();
13333 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13338 /* Fall through. */
13345 /* Fall through. */
13348 start_noreorder ();
13351 load_register (AT
, &imm_expr
, dbl
);
13352 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13353 op
[1], imm
? AT
: op
[2]);
13354 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13355 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13357 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13360 if (mips_opts
.micromips
)
13361 micromips_label_expr (&label_expr
);
13363 label_expr
.X_add_number
= 8;
13364 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13365 macro_build (NULL
, "nop", "");
13366 macro_build (NULL
, "break", BRK_FMT
, 6);
13367 if (mips_opts
.micromips
)
13368 micromips_add_label ();
13374 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13376 if (op
[0] == op
[1])
13383 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13384 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13388 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13389 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13390 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13391 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13395 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13397 if (op
[0] == op
[1])
13404 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13405 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13409 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13410 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13411 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13412 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13421 rot
= imm_expr
.X_add_number
& 0x3f;
13422 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13424 rot
= (64 - rot
) & 0x3f;
13426 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13428 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13433 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13436 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13437 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13440 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13441 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13442 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13450 rot
= imm_expr
.X_add_number
& 0x1f;
13451 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13453 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13454 (32 - rot
) & 0x1f);
13459 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13463 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13464 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13465 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13470 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13472 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13476 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13477 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13478 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13479 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13483 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13485 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13489 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13490 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13491 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13492 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13501 rot
= imm_expr
.X_add_number
& 0x3f;
13502 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13505 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13507 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13512 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13515 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13516 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13519 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13520 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13521 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13529 rot
= imm_expr
.X_add_number
& 0x1f;
13530 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13532 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13537 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13541 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13542 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13543 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13549 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13550 else if (op
[2] == 0)
13551 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13554 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13555 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13560 if (imm_expr
.X_add_number
== 0)
13562 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13567 as_warn (_("instruction %s: result is always false"),
13568 ip
->insn_mo
->name
);
13569 move_register (op
[0], 0);
13572 if (CPU_HAS_SEQ (mips_opts
.arch
)
13573 && -512 <= imm_expr
.X_add_number
13574 && imm_expr
.X_add_number
< 512)
13576 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13577 (int) imm_expr
.X_add_number
);
13580 if (imm_expr
.X_add_number
>= 0
13581 && imm_expr
.X_add_number
< 0x10000)
13582 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13583 else if (imm_expr
.X_add_number
> -0x8000
13584 && imm_expr
.X_add_number
< 0)
13586 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13587 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13588 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13590 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13593 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13594 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13599 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13600 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13603 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13606 case M_SGE
: /* X >= Y <==> not (X < Y) */
13612 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13613 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13616 case M_SGE_I
: /* X >= I <==> not (X < I). */
13618 if (imm_expr
.X_add_number
>= -0x8000
13619 && imm_expr
.X_add_number
< 0x8000)
13620 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13621 op
[0], op
[1], BFD_RELOC_LO16
);
13624 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13625 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13629 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13632 case M_SGT
: /* X > Y <==> Y < X. */
13638 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13641 case M_SGT_I
: /* X > I <==> I < X. */
13648 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13649 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13652 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13658 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13659 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13662 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13669 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13670 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13671 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13675 if (imm_expr
.X_add_number
>= -0x8000
13676 && imm_expr
.X_add_number
< 0x8000)
13678 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13683 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13684 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13688 if (imm_expr
.X_add_number
>= -0x8000
13689 && imm_expr
.X_add_number
< 0x8000)
13691 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13696 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13697 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13702 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13703 else if (op
[2] == 0)
13704 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13707 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13708 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13713 if (imm_expr
.X_add_number
== 0)
13715 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13720 as_warn (_("instruction %s: result is always true"),
13721 ip
->insn_mo
->name
);
13722 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13723 op
[0], 0, BFD_RELOC_LO16
);
13726 if (CPU_HAS_SEQ (mips_opts
.arch
)
13727 && -512 <= imm_expr
.X_add_number
13728 && imm_expr
.X_add_number
< 512)
13730 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13731 (int) imm_expr
.X_add_number
);
13734 if (imm_expr
.X_add_number
>= 0
13735 && imm_expr
.X_add_number
< 0x10000)
13737 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13740 else if (imm_expr
.X_add_number
> -0x8000
13741 && imm_expr
.X_add_number
< 0)
13743 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13744 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13745 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13747 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13750 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13751 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13756 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13757 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13760 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13766 if (ISA_IS_R6 (mips_opts
.isa
))
13778 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
13780 if (imm_expr
.X_add_number
> -0x200
13781 && imm_expr
.X_add_number
<= 0x200
13782 && !ISA_IS_R6 (mips_opts
.isa
))
13784 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13785 (int) -imm_expr
.X_add_number
);
13794 if (imm_expr
.X_add_number
> -0x8000
13795 && imm_expr
.X_add_number
<= 0x8000)
13797 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13798 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13803 load_register (AT
, &imm_expr
, dbl
);
13804 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13826 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13827 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13832 gas_assert (!mips_opts
.micromips
);
13833 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13837 * Is the double cfc1 instruction a bug in the mips assembler;
13838 * or is there a reason for it?
13840 start_noreorder ();
13841 macro_build (NULL
, "cfc1", "t,g", op
[2], FCSR
);
13842 macro_build (NULL
, "cfc1", "t,g", op
[2], FCSR
);
13843 macro_build (NULL
, "nop", "");
13844 expr1
.X_add_number
= 3;
13845 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13846 expr1
.X_add_number
= 2;
13847 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13848 macro_build (NULL
, "ctc1", "t,g", AT
, FCSR
);
13849 macro_build (NULL
, "nop", "");
13850 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13852 macro_build (NULL
, "ctc1", "t,g", op
[2], FCSR
);
13853 macro_build (NULL
, "nop", "");
13870 offbits
= (mips_opts
.micromips
? 12 : 16);
13876 offbits
= (mips_opts
.micromips
? 12 : 16);
13888 offbits
= (mips_opts
.micromips
? 12 : 16);
13895 offbits
= (mips_opts
.micromips
? 12 : 16);
13901 large_offset
= !small_offset_p (off
, align
, offbits
);
13903 expr1
.X_add_number
= 0;
13908 if (small_offset_p (0, align
, 16))
13909 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13910 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13913 load_address (tempreg
, ep
, &used_at
);
13915 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13916 tempreg
, tempreg
, breg
);
13918 offset_reloc
[0] = BFD_RELOC_LO16
;
13919 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13920 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13925 else if (!ust
&& op
[0] == breg
)
13936 if (!target_big_endian
)
13937 ep
->X_add_number
+= off
;
13939 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13941 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13942 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13944 if (!target_big_endian
)
13945 ep
->X_add_number
-= off
;
13947 ep
->X_add_number
+= off
;
13949 macro_build (NULL
, s2
, "t,~(b)",
13950 tempreg
, (int) ep
->X_add_number
, breg
);
13952 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13953 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13955 /* If necessary, move the result in tempreg to the final destination. */
13956 if (!ust
&& op
[0] != tempreg
)
13958 /* Protect second load's delay slot. */
13960 move_register (op
[0], tempreg
);
13966 if (target_big_endian
== ust
)
13967 ep
->X_add_number
+= off
;
13968 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13969 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13970 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13972 /* For halfword transfers we need a temporary register to shuffle
13973 bytes. Unfortunately for M_USH_A we have none available before
13974 the next store as AT holds the base address. We deal with this
13975 case by clobbering TREG and then restoring it as with ULH. */
13976 tempreg
= ust
== large_offset
? op
[0] : AT
;
13978 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13980 if (target_big_endian
== ust
)
13981 ep
->X_add_number
-= off
;
13983 ep
->X_add_number
+= off
;
13984 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13985 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13987 /* For M_USH_A re-retrieve the LSB. */
13988 if (ust
&& large_offset
)
13990 if (target_big_endian
)
13991 ep
->X_add_number
+= off
;
13993 ep
->X_add_number
-= off
;
13994 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13995 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13997 /* For ULH and M_USH_A OR the LSB in. */
13998 if (!ust
|| large_offset
)
14000 tempreg
= !large_offset
? AT
: op
[0];
14001 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
14002 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
14007 /* FIXME: Check if this is one of the itbl macros, since they
14008 are added dynamically. */
14009 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
14012 if (!mips_opts
.at
&& used_at
)
14013 as_bad (_("macro used $at after \".set noat\""));
14016 /* Implement macros in mips16 mode. */
14019 mips16_macro (struct mips_cl_insn
*ip
)
14021 const struct mips_operand_array
*operands
;
14026 const char *s
, *s2
, *s3
;
14027 unsigned int op
[MAX_OPERANDS
];
14030 mask
= ip
->insn_mo
->mask
;
14032 operands
= insn_operands (ip
);
14033 for (i
= 0; i
< MAX_OPERANDS
; i
++)
14034 if (operands
->operand
[i
])
14035 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
14039 expr1
.X_op
= O_constant
;
14040 expr1
.X_op_symbol
= NULL
;
14041 expr1
.X_add_symbol
= NULL
;
14042 expr1
.X_add_number
= 1;
14053 /* Fall through. */
14059 /* Fall through. */
14063 start_noreorder ();
14064 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
14065 expr1
.X_add_number
= 2;
14066 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14067 macro_build (NULL
, "break", "6", 7);
14069 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14070 since that causes an overflow. We should do that as well,
14071 but I don't see how to do the comparisons without a temporary
14074 macro_build (NULL
, s
, "x", op
[0]);
14093 start_noreorder ();
14094 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
14095 expr1
.X_add_number
= 2;
14096 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14097 macro_build (NULL
, "break", "6", 7);
14099 macro_build (NULL
, s2
, "x", op
[0]);
14104 /* Fall through. */
14106 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
14107 macro_build (NULL
, "mflo", "x", op
[0]);
14115 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14116 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14120 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14121 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14125 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14126 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14148 goto do_reverse_branch
;
14152 goto do_reverse_branch
;
14164 goto do_reverse_branch
;
14175 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14176 macro_build (&offset_expr
, s2
, "p");
14203 goto do_addone_branch_i
;
14208 goto do_addone_branch_i
;
14223 goto do_addone_branch_i
;
14229 do_addone_branch_i
:
14230 ++imm_expr
.X_add_number
;
14233 macro_build (&imm_expr
, s
, s3
, op
[0]);
14234 macro_build (&offset_expr
, s2
, "p");
14238 expr1
.X_add_number
= 0;
14239 macro_build (&expr1
, "slti", "x,8", op
[1]);
14240 if (op
[0] != op
[1])
14241 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14242 expr1
.X_add_number
= 2;
14243 macro_build (&expr1
, "bteqz", "p");
14244 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14249 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14250 opcode bits in *OPCODE_EXTRA. */
14252 static struct mips_opcode
*
14253 mips_lookup_insn (htab_t hash
, const char *start
,
14254 ssize_t length
, unsigned int *opcode_extra
)
14256 char *name
, *dot
, *p
;
14257 unsigned int mask
, suffix
;
14259 struct mips_opcode
*insn
;
14261 /* Make a copy of the instruction so that we can fiddle with it. */
14262 name
= xstrndup (start
, length
);
14264 /* Look up the instruction as-is. */
14265 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14269 dot
= strchr (name
, '.');
14272 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14273 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14274 if (*p
== 0 && mask
!= 0)
14277 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14279 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14281 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14287 if (mips_opts
.micromips
)
14289 /* See if there's an instruction size override suffix,
14290 either `16' or `32', at the end of the mnemonic proper,
14291 that defines the operation, i.e. before the first `.'
14292 character if any. Strip it and retry. */
14293 opend
= dot
!= NULL
? dot
- name
: length
;
14294 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14296 else if (opend
>= 2 && name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14302 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14303 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14306 forced_insn_length
= suffix
;
14318 /* Assemble an instruction into its binary format. If the instruction
14319 is a macro, set imm_expr and offset_expr to the values associated
14320 with "I" and "A" operands respectively. Otherwise store the value
14321 of the relocatable field (if any) in offset_expr. In both cases
14322 set offset_reloc to the relocation operators applied to offset_expr. */
14325 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14327 const struct mips_opcode
*first
, *past
;
14331 struct mips_operand_token
*tokens
;
14332 unsigned int opcode_extra
;
14334 if (mips_opts
.micromips
)
14336 hash
= micromips_op_hash
;
14337 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14342 past
= &mips_opcodes
[NUMOPCODES
];
14344 forced_insn_length
= 0;
14347 /* We first try to match an instruction up to a space or to the end. */
14348 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14351 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14354 set_insn_error (0, _("unrecognized opcode"));
14358 if (strcmp (first
->name
, "li.s") == 0)
14360 else if (strcmp (first
->name
, "li.d") == 0)
14364 tokens
= mips_parse_arguments (str
+ end
, format
);
14368 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, false)
14369 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, true))
14370 set_insn_error (0, _("invalid operands"));
14372 obstack_free (&mips_operand_tokens
, tokens
);
14375 /* As for mips_ip, but used when assembling MIPS16 code.
14376 Also set forced_insn_length to the resulting instruction size in
14377 bytes if the user explicitly requested a small or extended instruction. */
14380 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14383 struct mips_opcode
*first
;
14384 struct mips_operand_token
*tokens
;
14387 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14409 else if (*s
== 'e')
14416 else if (*s
++ == ' ')
14418 set_insn_error (0, _("unrecognized opcode"));
14421 forced_insn_length
= l
;
14424 first
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, str
);
14429 set_insn_error (0, _("unrecognized opcode"));
14433 tokens
= mips_parse_arguments (s
, 0);
14437 if (!match_mips16_insns (insn
, first
, tokens
))
14438 set_insn_error (0, _("invalid operands"));
14440 obstack_free (&mips_operand_tokens
, tokens
);
14443 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14444 NBITS is the number of significant bits in VAL. */
14446 static unsigned long
14447 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14452 val
&= (1U << nbits
) - 1;
14453 if (nbits
== 16 || nbits
== 9)
14455 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14458 else if (nbits
== 15)
14460 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14463 else if (nbits
== 6)
14465 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14468 return (extval
<< 16) | val
;
14471 /* Like decode_mips16_operand, but require the operand to be defined and
14472 require it to be an integer. */
14474 static const struct mips_int_operand
*
14475 mips16_immed_operand (int type
, bool extended_p
)
14477 const struct mips_operand
*operand
;
14479 operand
= decode_mips16_operand (type
, extended_p
);
14480 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14482 return (const struct mips_int_operand
*) operand
;
14485 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14488 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14489 bfd_reloc_code_real_type reloc
, offsetT sval
)
14491 int min_val
, max_val
;
14493 min_val
= mips_int_operand_min (operand
);
14494 max_val
= mips_int_operand_max (operand
);
14495 if (reloc
!= BFD_RELOC_UNUSED
)
14498 sval
= SEXT_16BIT (sval
);
14503 return (sval
>= min_val
14505 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14508 /* Install immediate value VAL into MIPS16 instruction *INSN,
14509 extending it if necessary. The instruction in *INSN may
14510 already be extended.
14512 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14513 if none. In the former case, VAL is a 16-bit number with no
14514 defined signedness.
14516 TYPE is the type of the immediate field. USER_INSN_LENGTH
14517 is the length that the user requested, or 0 if none. */
14520 mips16_immed (const char *file
, unsigned int line
, int type
,
14521 bfd_reloc_code_real_type reloc
, offsetT val
,
14522 unsigned int user_insn_length
, unsigned long *insn
)
14524 const struct mips_int_operand
*operand
;
14525 unsigned int uval
, length
;
14527 operand
= mips16_immed_operand (type
, false);
14528 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14530 /* We need an extended instruction. */
14531 if (user_insn_length
== 2)
14532 as_bad_where (file
, line
, _("invalid unextended operand value"));
14534 *insn
|= MIPS16_EXTEND
;
14536 else if (user_insn_length
== 4)
14538 /* The operand doesn't force an unextended instruction to be extended.
14539 Warn if the user wanted an extended instruction anyway. */
14540 *insn
|= MIPS16_EXTEND
;
14541 as_warn_where (file
, line
,
14542 _("extended operand requested but not required"));
14545 length
= mips16_opcode_length (*insn
);
14548 operand
= mips16_immed_operand (type
, true);
14549 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14550 as_bad_where (file
, line
,
14551 _("operand value out of range for instruction"));
14553 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14554 if (length
== 2 || operand
->root
.lsb
!= 0)
14555 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14557 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14560 struct percent_op_match
14563 bfd_reloc_code_real_type reloc
;
14566 static const struct percent_op_match mips_percent_op
[] =
14568 {"%lo", BFD_RELOC_LO16
},
14569 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14570 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14571 {"%call16", BFD_RELOC_MIPS_CALL16
},
14572 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14573 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14574 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14575 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14576 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14577 {"%got", BFD_RELOC_MIPS_GOT16
},
14578 {"%gp_rel", BFD_RELOC_GPREL16
},
14579 {"%gprel", BFD_RELOC_GPREL16
},
14580 {"%half", BFD_RELOC_16
},
14581 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14582 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14583 {"%neg", BFD_RELOC_MIPS_SUB
},
14584 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14585 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14586 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14587 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14588 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14589 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14590 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14591 {"%hi", BFD_RELOC_HI16_S
},
14592 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14593 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14596 static const struct percent_op_match mips16_percent_op
[] =
14598 {"%lo", BFD_RELOC_MIPS16_LO16
},
14599 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14600 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14601 {"%got", BFD_RELOC_MIPS16_GOT16
},
14602 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14603 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14604 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14605 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14606 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14607 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14608 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14609 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14610 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14614 /* Return true if *STR points to a relocation operator. When returning true,
14615 move *STR over the operator and store its relocation code in *RELOC.
14616 Leave both *STR and *RELOC alone when returning false. */
14619 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14621 const struct percent_op_match
*percent_op
;
14624 if (mips_opts
.mips16
)
14626 percent_op
= mips16_percent_op
;
14627 limit
= ARRAY_SIZE (mips16_percent_op
);
14631 percent_op
= mips_percent_op
;
14632 limit
= ARRAY_SIZE (mips_percent_op
);
14635 for (i
= 0; i
< limit
; i
++)
14636 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14638 int len
= strlen (percent_op
[i
].str
);
14640 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14643 *str
+= strlen (percent_op
[i
].str
);
14644 *reloc
= percent_op
[i
].reloc
;
14646 /* Check whether the output BFD supports this relocation.
14647 If not, issue an error and fall back on something safe. */
14648 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14650 as_bad (_("relocation %s isn't supported by the current ABI"),
14651 percent_op
[i
].str
);
14652 *reloc
= BFD_RELOC_UNUSED
;
14660 /* Parse string STR as a 16-bit relocatable operand. Store the
14661 expression in *EP and the relocations in the array starting
14662 at RELOC. Return the number of relocation operators used.
14664 On exit, EXPR_END points to the first character after the expression. */
14667 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14670 bfd_reloc_code_real_type reversed_reloc
[3];
14671 size_t reloc_index
, i
;
14672 int crux_depth
, str_depth
;
14675 /* Search for the start of the main expression, recoding relocations
14676 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14677 of the main expression and with CRUX_DEPTH containing the number
14678 of open brackets at that point. */
14685 crux_depth
= str_depth
;
14687 /* Skip over whitespace and brackets, keeping count of the number
14689 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14694 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14695 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14697 my_getExpression (ep
, crux
);
14700 /* Match every open bracket. */
14701 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14705 if (crux_depth
> 0)
14706 as_bad (_("unclosed '('"));
14710 for (i
= 0; i
< reloc_index
; i
++)
14711 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14713 return reloc_index
;
14717 my_getExpression (expressionS
*ep
, char *str
)
14721 save_in
= input_line_pointer
;
14722 input_line_pointer
= str
;
14724 expr_end
= input_line_pointer
;
14725 input_line_pointer
= save_in
;
14729 md_atof (int type
, char *litP
, int *sizeP
)
14731 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14735 md_number_to_chars (char *buf
, valueT val
, int n
)
14737 if (target_big_endian
)
14738 number_to_chars_bigendian (buf
, val
, n
);
14740 number_to_chars_littleendian (buf
, val
, n
);
14743 static int support_64bit_objects(void)
14745 const char **list
, **l
;
14748 list
= bfd_target_list ();
14749 for (l
= list
; *l
!= NULL
; l
++)
14750 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14751 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14753 yes
= (*l
!= NULL
);
14758 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14759 NEW_VALUE. Warn if another value was already specified. Note:
14760 we have to defer parsing the -march and -mtune arguments in order
14761 to handle 'from-abi' correctly, since the ABI might be specified
14762 in a later argument. */
14765 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14767 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14768 as_warn (_("a different %s was already specified, is now %s"),
14769 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14772 *string_ptr
= new_value
;
14776 md_parse_option (int c
, const char *arg
)
14780 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14781 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14783 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14784 c
== mips_ases
[i
].option_on
);
14790 case OPTION_CONSTRUCT_FLOATS
:
14791 mips_disable_float_construction
= 0;
14794 case OPTION_NO_CONSTRUCT_FLOATS
:
14795 mips_disable_float_construction
= 1;
14807 target_big_endian
= 1;
14811 target_big_endian
= 0;
14817 else if (arg
[0] == '0')
14819 else if (arg
[0] == '1')
14829 mips_debug
= atoi (arg
);
14833 file_mips_opts
.isa
= ISA_MIPS1
;
14837 file_mips_opts
.isa
= ISA_MIPS2
;
14841 file_mips_opts
.isa
= ISA_MIPS3
;
14845 file_mips_opts
.isa
= ISA_MIPS4
;
14849 file_mips_opts
.isa
= ISA_MIPS5
;
14852 case OPTION_MIPS32
:
14853 file_mips_opts
.isa
= ISA_MIPS32
;
14856 case OPTION_MIPS32R2
:
14857 file_mips_opts
.isa
= ISA_MIPS32R2
;
14860 case OPTION_MIPS32R3
:
14861 file_mips_opts
.isa
= ISA_MIPS32R3
;
14864 case OPTION_MIPS32R5
:
14865 file_mips_opts
.isa
= ISA_MIPS32R5
;
14868 case OPTION_MIPS32R6
:
14869 file_mips_opts
.isa
= ISA_MIPS32R6
;
14872 case OPTION_MIPS64R2
:
14873 file_mips_opts
.isa
= ISA_MIPS64R2
;
14876 case OPTION_MIPS64R3
:
14877 file_mips_opts
.isa
= ISA_MIPS64R3
;
14880 case OPTION_MIPS64R5
:
14881 file_mips_opts
.isa
= ISA_MIPS64R5
;
14884 case OPTION_MIPS64R6
:
14885 file_mips_opts
.isa
= ISA_MIPS64R6
;
14888 case OPTION_MIPS64
:
14889 file_mips_opts
.isa
= ISA_MIPS64
;
14893 mips_set_option_string (&mips_tune_string
, arg
);
14897 mips_set_option_string (&mips_arch_string
, arg
);
14901 mips_set_option_string (&mips_arch_string
, "4650");
14902 mips_set_option_string (&mips_tune_string
, "4650");
14905 case OPTION_NO_M4650
:
14909 mips_set_option_string (&mips_arch_string
, "4010");
14910 mips_set_option_string (&mips_tune_string
, "4010");
14913 case OPTION_NO_M4010
:
14917 mips_set_option_string (&mips_arch_string
, "4100");
14918 mips_set_option_string (&mips_tune_string
, "4100");
14921 case OPTION_NO_M4100
:
14925 mips_set_option_string (&mips_arch_string
, "3900");
14926 mips_set_option_string (&mips_tune_string
, "3900");
14929 case OPTION_NO_M3900
:
14932 case OPTION_MICROMIPS
:
14933 if (file_mips_opts
.mips16
== 1)
14935 as_bad (_("-mmicromips cannot be used with -mips16"));
14938 file_mips_opts
.micromips
= 1;
14939 mips_no_prev_insn ();
14942 case OPTION_NO_MICROMIPS
:
14943 file_mips_opts
.micromips
= 0;
14944 mips_no_prev_insn ();
14947 case OPTION_MIPS16
:
14948 if (file_mips_opts
.micromips
== 1)
14950 as_bad (_("-mips16 cannot be used with -micromips"));
14953 file_mips_opts
.mips16
= 1;
14954 mips_no_prev_insn ();
14957 case OPTION_NO_MIPS16
:
14958 file_mips_opts
.mips16
= 0;
14959 mips_no_prev_insn ();
14962 case OPTION_FIX_24K
:
14966 case OPTION_NO_FIX_24K
:
14970 case OPTION_FIX_RM7000
:
14971 mips_fix_rm7000
= 1;
14974 case OPTION_NO_FIX_RM7000
:
14975 mips_fix_rm7000
= 0;
14978 case OPTION_FIX_LOONGSON3_LLSC
:
14979 mips_fix_loongson3_llsc
= true;
14982 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14983 mips_fix_loongson3_llsc
= false;
14986 case OPTION_FIX_LOONGSON2F_JUMP
:
14987 mips_fix_loongson2f_jump
= true;
14990 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14991 mips_fix_loongson2f_jump
= false;
14994 case OPTION_FIX_LOONGSON2F_NOP
:
14995 mips_fix_loongson2f_nop
= true;
14998 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14999 mips_fix_loongson2f_nop
= false;
15002 case OPTION_FIX_VR4120
:
15003 mips_fix_vr4120
= 1;
15006 case OPTION_NO_FIX_VR4120
:
15007 mips_fix_vr4120
= 0;
15010 case OPTION_FIX_VR4130
:
15011 mips_fix_vr4130
= 1;
15014 case OPTION_NO_FIX_VR4130
:
15015 mips_fix_vr4130
= 0;
15018 case OPTION_FIX_CN63XXP1
:
15019 mips_fix_cn63xxp1
= true;
15022 case OPTION_NO_FIX_CN63XXP1
:
15023 mips_fix_cn63xxp1
= false;
15026 case OPTION_FIX_R5900
:
15027 mips_fix_r5900
= true;
15028 mips_fix_r5900_explicit
= true;
15031 case OPTION_NO_FIX_R5900
:
15032 mips_fix_r5900
= false;
15033 mips_fix_r5900_explicit
= true;
15036 case OPTION_RELAX_BRANCH
:
15037 mips_relax_branch
= 1;
15040 case OPTION_NO_RELAX_BRANCH
:
15041 mips_relax_branch
= 0;
15044 case OPTION_IGNORE_BRANCH_ISA
:
15045 mips_ignore_branch_isa
= true;
15048 case OPTION_NO_IGNORE_BRANCH_ISA
:
15049 mips_ignore_branch_isa
= false;
15052 case OPTION_INSN32
:
15053 file_mips_opts
.insn32
= true;
15056 case OPTION_NO_INSN32
:
15057 file_mips_opts
.insn32
= false;
15060 case OPTION_MSHARED
:
15061 mips_in_shared
= true;
15064 case OPTION_MNO_SHARED
:
15065 mips_in_shared
= false;
15068 case OPTION_MSYM32
:
15069 file_mips_opts
.sym32
= true;
15072 case OPTION_MNO_SYM32
:
15073 file_mips_opts
.sym32
= false;
15076 /* When generating ELF code, we permit -KPIC and -call_shared to
15077 select SVR4_PIC, and -non_shared to select no PIC. This is
15078 intended to be compatible with Irix 5. */
15079 case OPTION_CALL_SHARED
:
15080 mips_pic
= SVR4_PIC
;
15081 mips_abicalls
= true;
15084 case OPTION_CALL_NONPIC
:
15086 mips_abicalls
= true;
15089 case OPTION_NON_SHARED
:
15091 mips_abicalls
= false;
15094 /* The -xgot option tells the assembler to use 32 bit offsets
15095 when accessing the got in SVR4_PIC mode. It is for Irix
15102 g_switch_value
= atoi (arg
);
15106 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15109 mips_abi
= O32_ABI
;
15113 mips_abi
= N32_ABI
;
15117 mips_abi
= N64_ABI
;
15118 if (!support_64bit_objects())
15119 as_fatal (_("no compiled in support for 64 bit object file format"));
15123 file_mips_opts
.gp
= 32;
15127 file_mips_opts
.gp
= 64;
15131 file_mips_opts
.fp
= 32;
15135 file_mips_opts
.fp
= 0;
15139 file_mips_opts
.fp
= 64;
15142 case OPTION_ODD_SPREG
:
15143 file_mips_opts
.oddspreg
= 1;
15146 case OPTION_NO_ODD_SPREG
:
15147 file_mips_opts
.oddspreg
= 0;
15150 case OPTION_SINGLE_FLOAT
:
15151 file_mips_opts
.single_float
= 1;
15154 case OPTION_DOUBLE_FLOAT
:
15155 file_mips_opts
.single_float
= 0;
15158 case OPTION_SOFT_FLOAT
:
15159 file_mips_opts
.soft_float
= 1;
15162 case OPTION_HARD_FLOAT
:
15163 file_mips_opts
.soft_float
= 0;
15167 if (strcmp (arg
, "32") == 0)
15168 mips_abi
= O32_ABI
;
15169 else if (strcmp (arg
, "o64") == 0)
15170 mips_abi
= O64_ABI
;
15171 else if (strcmp (arg
, "n32") == 0)
15172 mips_abi
= N32_ABI
;
15173 else if (strcmp (arg
, "64") == 0)
15175 mips_abi
= N64_ABI
;
15176 if (! support_64bit_objects())
15177 as_fatal (_("no compiled in support for 64 bit object file "
15180 else if (strcmp (arg
, "eabi") == 0)
15181 mips_abi
= EABI_ABI
;
15184 as_fatal (_("invalid abi -mabi=%s"), arg
);
15189 case OPTION_M7000_HILO_FIX
:
15190 mips_7000_hilo_fix
= true;
15193 case OPTION_MNO_7000_HILO_FIX
:
15194 mips_7000_hilo_fix
= false;
15197 case OPTION_MDEBUG
:
15198 mips_flag_mdebug
= true;
15201 case OPTION_NO_MDEBUG
:
15202 mips_flag_mdebug
= false;
15206 mips_flag_pdr
= true;
15209 case OPTION_NO_PDR
:
15210 mips_flag_pdr
= false;
15213 case OPTION_MVXWORKS_PIC
:
15214 mips_pic
= VXWORKS_PIC
;
15218 if (strcmp (arg
, "2008") == 0)
15220 else if (strcmp (arg
, "legacy") == 0)
15224 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15233 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15238 /* Set up globals to tune for the ISA or processor described by INFO. */
15241 mips_set_tune (const struct mips_cpu_info
*info
)
15244 mips_tune
= info
->cpu
;
15249 mips_after_parse_args (void)
15251 const struct mips_cpu_info
*arch_info
= 0;
15252 const struct mips_cpu_info
*tune_info
= 0;
15254 /* GP relative stuff not working for PE. */
15255 if (startswith (TARGET_OS
, "pe"))
15257 if (g_switch_seen
&& g_switch_value
!= 0)
15258 as_bad (_("-G not supported in this configuration"));
15259 g_switch_value
= 0;
15262 if (mips_abi
== NO_ABI
)
15263 mips_abi
= MIPS_DEFAULT_ABI
;
15265 /* The following code determines the architecture.
15266 Similar code was added to GCC 3.3 (see override_options() in
15267 config/mips/mips.c). The GAS and GCC code should be kept in sync
15268 as much as possible. */
15270 if (mips_arch_string
!= 0)
15271 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15273 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15275 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15276 ISA level specified by -mipsN, while arch_info->isa contains
15277 the -march selection (if any). */
15278 if (arch_info
!= 0)
15280 /* -march takes precedence over -mipsN, since it is more descriptive.
15281 There's no harm in specifying both as long as the ISA levels
15283 if (file_mips_opts
.isa
!= arch_info
->isa
)
15284 as_bad (_("-%s conflicts with the other architecture options,"
15285 " which imply -%s"),
15286 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15287 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15290 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15293 if (arch_info
== 0)
15295 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15296 gas_assert (arch_info
);
15299 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15300 as_bad (_("-march=%s is not compatible with the selected ABI"),
15303 file_mips_opts
.arch
= arch_info
->cpu
;
15304 file_mips_opts
.isa
= arch_info
->isa
;
15305 file_mips_opts
.init_ase
= arch_info
->ase
;
15307 /* The EVA Extension has instructions which are only valid when the R6 ISA
15308 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15310 if (((file_mips_opts
.ase
& ASE_EVA
) != 0) && ISA_IS_R6 (file_mips_opts
.isa
))
15311 file_mips_opts
.ase
|= ASE_EVA_R6
;
15313 /* Set up initial mips_opts state. */
15314 mips_opts
= file_mips_opts
;
15316 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15317 if (!mips_fix_r5900_explicit
)
15318 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15320 /* The register size inference code is now placed in
15321 file_mips_check_options. */
15323 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15325 if (mips_tune_string
!= 0)
15326 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15328 if (tune_info
== 0)
15329 mips_set_tune (arch_info
);
15331 mips_set_tune (tune_info
);
15333 if (mips_flag_mdebug
< 0)
15334 mips_flag_mdebug
= 0;
15338 mips_init_after_args (void)
15340 /* Initialize opcodes. */
15341 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15342 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15346 md_pcrel_from (fixS
*fixP
)
15348 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15350 switch (fixP
->fx_r_type
)
15352 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15353 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15354 /* Return the address of the delay slot. */
15357 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15358 case BFD_RELOC_MICROMIPS_JMP
:
15359 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15360 case BFD_RELOC_16_PCREL_S2
:
15361 case BFD_RELOC_MIPS_21_PCREL_S2
:
15362 case BFD_RELOC_MIPS_26_PCREL_S2
:
15363 case BFD_RELOC_MIPS_JMP
:
15364 /* Return the address of the delay slot. */
15367 case BFD_RELOC_MIPS_18_PCREL_S3
:
15368 /* Return the aligned address of the doubleword containing
15369 the instruction. */
15377 /* This is called before the symbol table is processed. In order to
15378 work with gcc when using mips-tfile, we must keep all local labels.
15379 However, in other cases, we want to discard them. If we were
15380 called with -g, but we didn't see any debugging information, it may
15381 mean that gcc is smuggling debugging information through to
15382 mips-tfile, in which case we must generate all local labels. */
15385 mips_frob_file_before_adjust (void)
15387 #ifndef NO_ECOFF_DEBUGGING
15388 if (ECOFF_DEBUGGING
15390 && ! ecoff_debugging_seen
)
15391 flag_keep_locals
= 1;
15395 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15396 the corresponding LO16 reloc. This is called before md_apply_fix and
15397 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15398 relocation operators.
15400 For our purposes, a %lo() expression matches a %got() or %hi()
15403 (a) it refers to the same symbol; and
15404 (b) the offset applied in the %lo() expression is no lower than
15405 the offset applied in the %got() or %hi().
15407 (b) allows us to cope with code like:
15410 lh $4,%lo(foo+2)($4)
15412 ...which is legal on RELA targets, and has a well-defined behaviour
15413 if the user knows that adding 2 to "foo" will not induce a carry to
15416 When several %lo()s match a particular %got() or %hi(), we use the
15417 following rules to distinguish them:
15419 (1) %lo()s with smaller offsets are a better match than %lo()s with
15422 (2) %lo()s with no matching %got() or %hi() are better than those
15423 that already have a matching %got() or %hi().
15425 (3) later %lo()s are better than earlier %lo()s.
15427 These rules are applied in order.
15429 (1) means, among other things, that %lo()s with identical offsets are
15430 chosen if they exist.
15432 (2) means that we won't associate several high-part relocations with
15433 the same low-part relocation unless there's no alternative. Having
15434 several high parts for the same low part is a GNU extension; this rule
15435 allows careful users to avoid it.
15437 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15438 with the last high-part relocation being at the front of the list.
15439 It therefore makes sense to choose the last matching low-part
15440 relocation, all other things being equal. It's also easier
15441 to code that way. */
15444 mips_frob_file (void)
15446 struct mips_hi_fixup
*l
;
15447 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15449 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15451 segment_info_type
*seginfo
;
15453 fixS
**hi_pos
, **lo_pos
, **pos
;
15455 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15457 /* If a GOT16 relocation turns out to be against a global symbol,
15458 there isn't supposed to be a matching LO. Ignore %gots against
15459 constants; we'll report an error for those later. */
15460 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15461 && !(l
->fixp
->fx_addsy
15462 && pic_need_relax (l
->fixp
->fx_addsy
)))
15465 /* Check quickly whether the next fixup happens to be a matching %lo. */
15466 if (fixup_has_matching_lo_p (l
->fixp
))
15469 seginfo
= seg_info (l
->seg
);
15471 /* Set HI_POS to the position of this relocation in the chain.
15472 Set LO_POS to the position of the chosen low-part relocation.
15473 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15474 relocation that matches an immediately-preceding high-part
15478 matched_lo_p
= false;
15479 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15481 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15483 if (*pos
== l
->fixp
)
15486 if ((*pos
)->fx_r_type
== looking_for_rtype
15487 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15488 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15490 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15492 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15495 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15496 && fixup_has_matching_lo_p (*pos
));
15499 /* If we found a match, remove the high-part relocation from its
15500 current position and insert it before the low-part relocation.
15501 Make the offsets match so that fixup_has_matching_lo_p()
15504 We don't warn about unmatched high-part relocations since some
15505 versions of gcc have been known to emit dead "lui ...%hi(...)"
15507 if (lo_pos
!= NULL
)
15509 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15510 if (l
->fixp
->fx_next
!= *lo_pos
)
15512 *hi_pos
= l
->fixp
->fx_next
;
15513 l
->fixp
->fx_next
= *lo_pos
;
15521 mips_force_relocation (fixS
*fixp
)
15523 if (generic_force_reloc (fixp
))
15526 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15527 so that the linker relaxation can update targets. */
15528 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15529 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15530 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15533 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15534 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15535 microMIPS symbols so that we can do cross-mode branch diagnostics
15536 and BAL to JALX conversion by the linker. */
15537 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15538 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15539 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15541 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15544 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15545 if (ISA_IS_R6 (file_mips_opts
.isa
)
15546 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15547 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15548 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15549 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15550 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15551 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15552 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15558 /* Implement TC_FORCE_RELOCATION_ABS. */
15561 mips_force_relocation_abs (fixS
*fixp
)
15563 if (generic_force_reloc (fixp
))
15566 /* These relocations do not have enough bits in the in-place addend
15567 to hold an arbitrary absolute section's offset. */
15568 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15574 /* Read the instruction associated with RELOC from BUF. */
15576 static unsigned int
15577 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15579 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15580 return read_compressed_insn (buf
, 4);
15582 return read_insn (buf
);
15585 /* Write instruction INSN to BUF, given that it has been relocated
15589 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15590 unsigned long insn
)
15592 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15593 write_compressed_insn (buf
, insn
, 4);
15595 write_insn (buf
, insn
);
15598 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15599 to a symbol in another ISA mode, which cannot be converted to JALX. */
15602 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15604 unsigned long opcode
;
15608 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15611 other
= S_GET_OTHER (fixP
->fx_addsy
);
15612 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15613 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15614 switch (fixP
->fx_r_type
)
15616 case BFD_RELOC_MIPS_JMP
:
15617 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15618 case BFD_RELOC_MICROMIPS_JMP
:
15619 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15625 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15626 jump to a symbol in the same ISA mode. */
15629 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15631 unsigned long opcode
;
15635 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15638 other
= S_GET_OTHER (fixP
->fx_addsy
);
15639 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15640 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15641 switch (fixP
->fx_r_type
)
15643 case BFD_RELOC_MIPS_JMP
:
15644 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15645 case BFD_RELOC_MIPS16_JMP
:
15646 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15647 case BFD_RELOC_MICROMIPS_JMP
:
15648 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15654 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15655 to a symbol whose value plus addend is not aligned according to the
15656 ultimate (after linker relaxation) jump instruction's immediate field
15657 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15658 regular MIPS code, to (1 << 2). */
15661 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15663 bool micro_to_mips_p
;
15667 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15670 other
= S_GET_OTHER (fixP
->fx_addsy
);
15671 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15672 val
+= fixP
->fx_offset
;
15673 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15674 && !ELF_ST_IS_MICROMIPS (other
));
15675 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15676 != ELF_ST_IS_COMPRESSED (other
));
15679 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15680 to a symbol whose annotation indicates another ISA mode. For absolute
15681 symbols check the ISA bit instead.
15683 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15684 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15685 MIPS symbols and associated with BAL instructions as these instructions
15686 may be converted to JALX by the linker. */
15689 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15692 unsigned long opcode
;
15698 if (mips_ignore_branch_isa
)
15701 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15704 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15705 absolute_p
= bfd_is_abs_section (symsec
);
15707 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15708 other
= S_GET_OTHER (fixP
->fx_addsy
);
15710 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15711 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15712 switch (fixP
->fx_r_type
)
15714 case BFD_RELOC_16_PCREL_S2
:
15715 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15716 && opcode
!= 0x0411);
15717 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15718 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15719 && opcode
!= 0x4060);
15720 case BFD_RELOC_MIPS_21_PCREL_S2
:
15721 case BFD_RELOC_MIPS_26_PCREL_S2
:
15722 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15723 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15724 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15725 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15726 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15727 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15733 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15734 branch instruction pointed to by FIXP is not aligned according to the
15735 branch instruction's immediate field requirement. We need the addend
15736 to preserve the ISA bit and also the sum must not have bit 2 set. We
15737 must explicitly OR in the ISA bit from symbol annotation as the bit
15738 won't be set in the symbol's value then. */
15741 fix_bad_misaligned_branch_p (fixS
*fixP
)
15750 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15753 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15754 absolute_p
= bfd_is_abs_section (symsec
);
15756 val
= S_GET_VALUE (fixP
->fx_addsy
);
15757 other
= S_GET_OTHER (fixP
->fx_addsy
);
15758 off
= fixP
->fx_offset
;
15760 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15761 val
|= ELF_ST_IS_COMPRESSED (other
);
15763 return (val
& 0x3) != isa_bit
;
15766 /* Calculate the relocation target by masking off ISA mode bit before
15767 combining symbol and addend. */
15770 fix_bad_misaligned_address (fixS
*fixP
)
15775 gas_assert (fixP
!= NULL
&& fixP
->fx_addsy
!= NULL
);
15776 val
= S_GET_VALUE (fixP
->fx_addsy
);
15777 off
= fixP
->fx_offset
;
15778 isa_mode
= (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP
->fx_addsy
))
15781 return ((val
& ~isa_mode
) + off
);
15784 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15785 and its calculated value VAL. */
15788 fix_validate_branch (fixS
*fixP
, valueT val
)
15790 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15792 _("branch to misaligned address (0x%lx)"),
15793 (long) (val
+ md_pcrel_from (fixP
)));
15794 else if (fix_bad_cross_mode_branch_p (fixP
))
15795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15796 _("branch to a symbol in another ISA mode"));
15797 else if (fix_bad_misaligned_branch_p (fixP
))
15798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15799 _("branch to misaligned address (0x%lx)"),
15800 (long) fix_bad_misaligned_address (fixP
));
15801 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15803 _("cannot encode misaligned addend "
15804 "in the relocatable field (0x%lx)"),
15805 (long) fixP
->fx_offset
);
15808 /* Apply a fixup to the object file. */
15811 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15814 unsigned long insn
;
15815 reloc_howto_type
*howto
;
15817 if (fixP
->fx_pcrel
)
15818 switch (fixP
->fx_r_type
)
15820 case BFD_RELOC_16_PCREL_S2
:
15821 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15822 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15823 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15824 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15825 case BFD_RELOC_32_PCREL
:
15826 case BFD_RELOC_MIPS_21_PCREL_S2
:
15827 case BFD_RELOC_MIPS_26_PCREL_S2
:
15828 case BFD_RELOC_MIPS_18_PCREL_S3
:
15829 case BFD_RELOC_MIPS_19_PCREL_S2
:
15830 case BFD_RELOC_HI16_S_PCREL
:
15831 case BFD_RELOC_LO16_PCREL
:
15835 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15840 _("PC-relative reference to a different section"));
15844 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15845 that have no MIPS ELF equivalent. */
15846 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15848 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15853 gas_assert (fixP
->fx_size
== 2
15854 || fixP
->fx_size
== 4
15855 || fixP
->fx_r_type
== BFD_RELOC_8
15856 || fixP
->fx_r_type
== BFD_RELOC_16
15857 || fixP
->fx_r_type
== BFD_RELOC_64
15858 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15859 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15860 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15861 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15862 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15863 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15864 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15866 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15868 /* Don't treat parts of a composite relocation as done. There are two
15871 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15872 should nevertheless be emitted if the first part is.
15874 (2) In normal usage, composite relocations are never assembly-time
15875 constants. The easiest way of dealing with the pathological
15876 exceptions is to generate a relocation against STN_UNDEF and
15877 leave everything up to the linker. */
15878 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15881 switch (fixP
->fx_r_type
)
15883 case BFD_RELOC_MIPS_TLS_GD
:
15884 case BFD_RELOC_MIPS_TLS_LDM
:
15885 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15886 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15887 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15888 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15889 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15890 case BFD_RELOC_MIPS_TLS_TPREL32
:
15891 case BFD_RELOC_MIPS_TLS_TPREL64
:
15892 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15893 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15894 case BFD_RELOC_MICROMIPS_TLS_GD
:
15895 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15896 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15897 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15898 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15899 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15900 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15901 case BFD_RELOC_MIPS16_TLS_GD
:
15902 case BFD_RELOC_MIPS16_TLS_LDM
:
15903 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15904 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15905 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15906 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15907 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15908 if (fixP
->fx_addsy
)
15909 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15912 _("TLS relocation against a constant"));
15915 case BFD_RELOC_MIPS_JMP
:
15916 case BFD_RELOC_MIPS16_JMP
:
15917 case BFD_RELOC_MICROMIPS_JMP
:
15921 gas_assert (!fixP
->fx_done
);
15923 /* Shift is 2, unusually, for microMIPS JALX. */
15924 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15925 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15930 if (fix_bad_cross_mode_jump_p (fixP
))
15931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15932 _("jump to a symbol in another ISA mode"));
15933 else if (fix_bad_same_mode_jalx_p (fixP
))
15934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15935 _("JALX to a symbol in the same ISA mode"));
15936 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15938 _("jump to misaligned address (0x%lx)"),
15939 (long) fix_bad_misaligned_address (fixP
));
15940 else if (HAVE_IN_PLACE_ADDENDS
15941 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15943 _("cannot encode misaligned addend "
15944 "in the relocatable field (0x%lx)"),
15945 (long) fixP
->fx_offset
);
15947 /* Fall through. */
15949 case BFD_RELOC_MIPS_SHIFT5
:
15950 case BFD_RELOC_MIPS_SHIFT6
:
15951 case BFD_RELOC_MIPS_GOT_DISP
:
15952 case BFD_RELOC_MIPS_GOT_PAGE
:
15953 case BFD_RELOC_MIPS_GOT_OFST
:
15954 case BFD_RELOC_MIPS_SUB
:
15955 case BFD_RELOC_MIPS_INSERT_A
:
15956 case BFD_RELOC_MIPS_INSERT_B
:
15957 case BFD_RELOC_MIPS_DELETE
:
15958 case BFD_RELOC_MIPS_HIGHEST
:
15959 case BFD_RELOC_MIPS_HIGHER
:
15960 case BFD_RELOC_MIPS_SCN_DISP
:
15961 case BFD_RELOC_MIPS_REL16
:
15962 case BFD_RELOC_MIPS_RELGOT
:
15963 case BFD_RELOC_MIPS_JALR
:
15964 case BFD_RELOC_HI16
:
15965 case BFD_RELOC_HI16_S
:
15966 case BFD_RELOC_LO16
:
15967 case BFD_RELOC_GPREL16
:
15968 case BFD_RELOC_MIPS_LITERAL
:
15969 case BFD_RELOC_MIPS_CALL16
:
15970 case BFD_RELOC_MIPS_GOT16
:
15971 case BFD_RELOC_GPREL32
:
15972 case BFD_RELOC_MIPS_GOT_HI16
:
15973 case BFD_RELOC_MIPS_GOT_LO16
:
15974 case BFD_RELOC_MIPS_CALL_HI16
:
15975 case BFD_RELOC_MIPS_CALL_LO16
:
15976 case BFD_RELOC_HI16_S_PCREL
:
15977 case BFD_RELOC_LO16_PCREL
:
15978 case BFD_RELOC_MIPS16_GPREL
:
15979 case BFD_RELOC_MIPS16_GOT16
:
15980 case BFD_RELOC_MIPS16_CALL16
:
15981 case BFD_RELOC_MIPS16_HI16
:
15982 case BFD_RELOC_MIPS16_HI16_S
:
15983 case BFD_RELOC_MIPS16_LO16
:
15984 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15985 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15986 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15987 case BFD_RELOC_MICROMIPS_SUB
:
15988 case BFD_RELOC_MICROMIPS_HIGHEST
:
15989 case BFD_RELOC_MICROMIPS_HIGHER
:
15990 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15991 case BFD_RELOC_MICROMIPS_JALR
:
15992 case BFD_RELOC_MICROMIPS_HI16
:
15993 case BFD_RELOC_MICROMIPS_HI16_S
:
15994 case BFD_RELOC_MICROMIPS_LO16
:
15995 case BFD_RELOC_MICROMIPS_GPREL16
:
15996 case BFD_RELOC_MICROMIPS_LITERAL
:
15997 case BFD_RELOC_MICROMIPS_CALL16
:
15998 case BFD_RELOC_MICROMIPS_GOT16
:
15999 case BFD_RELOC_MICROMIPS_GOT_HI16
:
16000 case BFD_RELOC_MICROMIPS_GOT_LO16
:
16001 case BFD_RELOC_MICROMIPS_CALL_HI16
:
16002 case BFD_RELOC_MICROMIPS_CALL_LO16
:
16003 case BFD_RELOC_MIPS_EH
:
16008 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
16010 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
16011 if (mips16_reloc_p (fixP
->fx_r_type
))
16012 insn
|= mips16_immed_extend (value
, 16);
16014 insn
|= (value
& 0xffff);
16015 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
16018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16019 _("unsupported constant in relocation"));
16024 /* This is handled like BFD_RELOC_32, but we output a sign
16025 extended value if we are only 32 bits. */
16028 if (8 <= sizeof (valueT
))
16029 md_number_to_chars (buf
, *valP
, 8);
16034 if ((*valP
& 0x80000000) != 0)
16038 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16039 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16044 case BFD_RELOC_RVA
:
16046 case BFD_RELOC_32_PCREL
:
16049 /* If we are deleting this reloc entry, we must fill in the
16050 value now. This can happen if we have a .word which is not
16051 resolved when it appears but is later defined. */
16053 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16056 case BFD_RELOC_MIPS_21_PCREL_S2
:
16057 fix_validate_branch (fixP
, *valP
);
16058 if (!fixP
->fx_done
)
16061 if (*valP
+ 0x400000 <= 0x7fffff)
16063 insn
= read_insn (buf
);
16064 insn
|= (*valP
>> 2) & 0x1fffff;
16065 write_insn (buf
, insn
);
16068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16069 _("branch out of range"));
16072 case BFD_RELOC_MIPS_26_PCREL_S2
:
16073 fix_validate_branch (fixP
, *valP
);
16074 if (!fixP
->fx_done
)
16077 if (*valP
+ 0x8000000 <= 0xfffffff)
16079 insn
= read_insn (buf
);
16080 insn
|= (*valP
>> 2) & 0x3ffffff;
16081 write_insn (buf
, insn
);
16084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16085 _("branch out of range"));
16088 case BFD_RELOC_MIPS_18_PCREL_S3
:
16089 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
16090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16091 _("PC-relative access using misaligned symbol (%lx)"),
16092 (long) S_GET_VALUE (fixP
->fx_addsy
));
16093 if ((fixP
->fx_offset
& 0x7) != 0)
16094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16095 _("PC-relative access using misaligned offset (%lx)"),
16096 (long) fixP
->fx_offset
);
16097 if (!fixP
->fx_done
)
16100 if (*valP
+ 0x100000 <= 0x1fffff)
16102 insn
= read_insn (buf
);
16103 insn
|= (*valP
>> 3) & 0x3ffff;
16104 write_insn (buf
, insn
);
16107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16108 _("PC-relative access out of range"));
16111 case BFD_RELOC_MIPS_19_PCREL_S2
:
16112 if ((*valP
& 0x3) != 0)
16113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16114 _("PC-relative access to misaligned address (%lx)"),
16116 if (!fixP
->fx_done
)
16119 if (*valP
+ 0x100000 <= 0x1fffff)
16121 insn
= read_insn (buf
);
16122 insn
|= (*valP
>> 2) & 0x7ffff;
16123 write_insn (buf
, insn
);
16126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16127 _("PC-relative access out of range"));
16130 case BFD_RELOC_16_PCREL_S2
:
16131 fix_validate_branch (fixP
, *valP
);
16133 /* We need to save the bits in the instruction since fixup_segment()
16134 might be deleting the relocation entry (i.e., a branch within
16135 the current segment). */
16136 if (! fixP
->fx_done
)
16139 /* Update old instruction data. */
16140 insn
= read_insn (buf
);
16142 if (*valP
+ 0x20000 <= 0x3ffff)
16144 insn
|= (*valP
>> 2) & 0xffff;
16145 write_insn (buf
, insn
);
16147 else if (fixP
->fx_tcbit2
16149 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16150 && (fixP
->fx_frag
->fr_address
16151 < text_section
->vma
+ bfd_section_size (text_section
))
16152 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16153 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16154 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16156 /* The branch offset is too large. If this is an
16157 unconditional branch, and we are not generating PIC code,
16158 we can convert it to an absolute jump instruction. */
16159 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16160 insn
= 0x0c000000; /* jal */
16162 insn
= 0x08000000; /* j */
16163 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16165 fixP
->fx_addsy
= section_symbol (text_section
);
16166 *valP
+= md_pcrel_from (fixP
);
16167 write_insn (buf
, insn
);
16171 /* If we got here, we have branch-relaxation disabled,
16172 and there's nothing we can do to fix this instruction
16173 without turning it into a longer sequence. */
16174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16175 _("branch out of range"));
16179 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16180 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16181 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16182 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16183 gas_assert (!fixP
->fx_done
);
16184 if (fix_bad_cross_mode_branch_p (fixP
))
16185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16186 _("branch to a symbol in another ISA mode"));
16187 else if (fixP
->fx_addsy
16188 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
16189 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16190 && (fixP
->fx_offset
& 0x1) != 0)
16191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16192 _("branch to misaligned address (0x%lx)"),
16193 (long) fix_bad_misaligned_address (fixP
));
16194 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16195 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16196 _("cannot encode misaligned addend "
16197 "in the relocatable field (0x%lx)"),
16198 (long) fixP
->fx_offset
);
16201 case BFD_RELOC_VTABLE_INHERIT
:
16204 && !S_IS_DEFINED (fixP
->fx_addsy
)
16205 && !S_IS_WEAK (fixP
->fx_addsy
))
16206 S_SET_WEAK (fixP
->fx_addsy
);
16209 case BFD_RELOC_NONE
:
16210 case BFD_RELOC_VTABLE_ENTRY
:
16218 /* Remember value for tc_gen_reloc. */
16219 fixP
->fx_addnumber
= *valP
;
16229 c
= get_symbol_name (&name
);
16230 p
= (symbolS
*) symbol_find_or_make (name
);
16231 (void) restore_line_pointer (c
);
16235 /* Align the current frag to a given power of two. If a particular
16236 fill byte should be used, FILL points to an integer that contains
16237 that byte, otherwise FILL is null.
16239 This function used to have the comment:
16241 The MIPS assembler also automatically adjusts any preceding label.
16243 The implementation therefore applied the adjustment to a maximum of
16244 one label. However, other label adjustments are applied to batches
16245 of labels, and adjusting just one caused problems when new labels
16246 were added for the sake of debugging or unwind information.
16247 We therefore adjust all preceding labels (given as LABELS) instead. */
16250 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16252 mips_emit_delays ();
16253 mips_record_compressed_mode ();
16254 if (fill
== NULL
&& subseg_text_p (now_seg
))
16255 frag_align_code (to
, 0);
16257 frag_align (to
, fill
? *fill
: 0, 0);
16258 record_alignment (now_seg
, to
);
16259 mips_move_labels (labels
, subseg_text_p (now_seg
));
16262 /* Align to a given power of two. .align 0 turns off the automatic
16263 alignment used by the data creating pseudo-ops. */
16266 s_align (int x ATTRIBUTE_UNUSED
)
16268 int temp
, fill_value
, *fill_ptr
;
16269 long max_alignment
= 28;
16271 /* o Note that the assembler pulls down any immediately preceding label
16272 to the aligned address.
16273 o It's not documented but auto alignment is reinstated by
16274 a .align pseudo instruction.
16275 o Note also that after auto alignment is turned off the mips assembler
16276 issues an error on attempt to assemble an improperly aligned data item.
16279 temp
= get_absolute_expression ();
16280 if (temp
> max_alignment
)
16281 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16284 as_warn (_("alignment negative, 0 assumed"));
16287 if (*input_line_pointer
== ',')
16289 ++input_line_pointer
;
16290 fill_value
= get_absolute_expression ();
16291 fill_ptr
= &fill_value
;
16297 segment_info_type
*si
= seg_info (now_seg
);
16298 struct insn_label_list
*l
= si
->label_list
;
16299 /* Auto alignment should be switched on by next section change. */
16301 mips_align (temp
, fill_ptr
, l
);
16308 demand_empty_rest_of_line ();
16312 s_change_sec (int sec
)
16316 /* The ELF backend needs to know that we are changing sections, so
16317 that .previous works correctly. We could do something like check
16318 for an obj_section_change_hook macro, but that might be confusing
16319 as it would not be appropriate to use it in the section changing
16320 functions in read.c, since obj-elf.c intercepts those. FIXME:
16321 This should be cleaner, somehow. */
16322 obj_elf_section_change_hook ();
16324 mips_emit_delays ();
16335 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16336 demand_empty_rest_of_line ();
16340 seg
= subseg_new (RDATA_SECTION_NAME
,
16341 (subsegT
) get_absolute_expression ());
16342 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
16343 | SEC_RELOC
| SEC_DATA
));
16344 if (!startswith (TARGET_OS
, "elf"))
16345 record_alignment (seg
, 4);
16346 demand_empty_rest_of_line ();
16350 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16351 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
16352 | SEC_DATA
| SEC_SMALL_DATA
));
16353 if (!startswith (TARGET_OS
, "elf"))
16354 record_alignment (seg
, 4);
16355 demand_empty_rest_of_line ();
16359 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16360 bfd_set_section_flags (seg
, SEC_ALLOC
| SEC_SMALL_DATA
);
16361 if (!startswith (TARGET_OS
, "elf"))
16362 record_alignment (seg
, 4);
16363 demand_empty_rest_of_line ();
16371 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16374 const char *section_name
;
16375 char c
, next_c
= 0;
16378 int section_entry_size
;
16379 int section_alignment
;
16381 saved_ilp
= input_line_pointer
;
16382 section_name
= obj_elf_section_name ();
16383 if (section_name
== NULL
)
16385 c
= input_line_pointer
[0];
16387 next_c
= input_line_pointer
[1];
16389 /* Do we have .section Name<,"flags">? */
16390 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16392 input_line_pointer
= saved_ilp
;
16393 obj_elf_section (ignore
);
16397 input_line_pointer
++;
16399 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16401 section_type
= get_absolute_expression ();
16405 if (*input_line_pointer
++ == ',')
16406 section_flag
= get_absolute_expression ();
16410 if (*input_line_pointer
++ == ',')
16411 section_entry_size
= get_absolute_expression ();
16413 section_entry_size
= 0;
16415 if (*input_line_pointer
++ == ',')
16416 section_alignment
= get_absolute_expression ();
16418 section_alignment
= 0;
16420 /* FIXME: really ignore? */
16421 (void) section_alignment
;
16423 /* When using the generic form of .section (as implemented by obj-elf.c),
16424 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16425 traditionally had to fall back on the more common @progbits instead.
16427 There's nothing really harmful in this, since bfd will correct
16428 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16429 means that, for backwards compatibility, the special_section entries
16430 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16432 Even so, we shouldn't force users of the MIPS .section syntax to
16433 incorrectly label the sections as SHT_PROGBITS. The best compromise
16434 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16435 generic type-checking code. */
16436 if (section_type
== SHT_MIPS_DWARF
)
16437 section_type
= SHT_PROGBITS
;
16439 obj_elf_change_section (section_name
, section_type
, section_flag
,
16440 section_entry_size
, 0, 0, 0);
16444 mips_enable_auto_align (void)
16450 s_cons (int log_size
)
16452 segment_info_type
*si
= seg_info (now_seg
);
16453 struct insn_label_list
*l
= si
->label_list
;
16455 mips_emit_delays ();
16456 if (log_size
> 0 && auto_align
)
16457 mips_align (log_size
, 0, l
);
16458 cons (1 << log_size
);
16459 mips_clear_insn_labels ();
16463 s_float_cons (int type
)
16465 segment_info_type
*si
= seg_info (now_seg
);
16466 struct insn_label_list
*l
= si
->label_list
;
16468 mips_emit_delays ();
16473 mips_align (3, 0, l
);
16475 mips_align (2, 0, l
);
16479 mips_clear_insn_labels ();
16482 /* Handle .globl. We need to override it because on Irix 5 you are
16485 where foo is an undefined symbol, to mean that foo should be
16486 considered to be the address of a function. */
16489 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16497 c
= get_symbol_name (&name
);
16498 symbolP
= symbol_find_or_make (name
);
16499 S_SET_EXTERNAL (symbolP
);
16501 *input_line_pointer
= c
;
16502 SKIP_WHITESPACE_AFTER_NAME ();
16504 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16505 && (*input_line_pointer
!= ','))
16510 c
= get_symbol_name (&secname
);
16511 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16513 as_bad (_("%s: no such section"), secname
);
16514 (void) restore_line_pointer (c
);
16516 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16517 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
16520 c
= *input_line_pointer
;
16523 input_line_pointer
++;
16524 SKIP_WHITESPACE ();
16525 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16531 demand_empty_rest_of_line ();
16535 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16536 any undefined non-function symbol to STT_OBJECT. We try to be
16537 compatible, since newer Irix 5 and 6 linkers care. */
16540 mips_frob_symbol (symbolS
*symp ATTRIBUTE_UNUSED
)
16542 /* This late in assembly we can set BSF_OBJECT indiscriminately
16543 and let elf.c:swap_out_syms sort out the symbol type. */
16544 flagword
*flags
= &symbol_get_bfdsym (symp
)->flags
;
16545 if ((*flags
& (BSF_GLOBAL
| BSF_WEAK
)) != 0
16546 || !S_IS_DEFINED (symp
))
16547 *flags
|= BSF_OBJECT
;
16552 s_option (int x ATTRIBUTE_UNUSED
)
16557 c
= get_symbol_name (&opt
);
16561 /* FIXME: What does this mean? */
16563 else if (startswith (opt
, "pic") && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16567 i
= atoi (opt
+ 3);
16568 if (i
!= 0 && i
!= 2)
16569 as_bad (_(".option pic%d not supported"), i
);
16570 else if (mips_pic
== VXWORKS_PIC
)
16571 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16576 mips_pic
= SVR4_PIC
;
16577 mips_abicalls
= true;
16580 if (mips_pic
== SVR4_PIC
)
16582 if (g_switch_seen
&& g_switch_value
!= 0)
16583 as_warn (_("-G may not be used with SVR4 PIC code"));
16584 g_switch_value
= 0;
16585 bfd_set_gp_size (stdoutput
, 0);
16589 as_warn (_("unrecognized option \"%s\""), opt
);
16591 (void) restore_line_pointer (c
);
16592 demand_empty_rest_of_line ();
16595 /* This structure is used to hold a stack of .set values. */
16597 struct mips_option_stack
16599 struct mips_option_stack
*next
;
16600 struct mips_set_options options
;
16603 static struct mips_option_stack
*mips_opts_stack
;
16605 /* Return status for .set/.module option handling. */
16607 enum code_option_type
16609 /* Unrecognized option. */
16610 OPTION_TYPE_BAD
= -1,
16612 /* Ordinary option. */
16613 OPTION_TYPE_NORMAL
,
16615 /* ISA changing option. */
16619 /* Handle common .set/.module options. Return status indicating option
16622 static enum code_option_type
16623 parse_code_option (char * name
)
16625 bool isa_set
= false;
16626 const struct mips_ase
*ase
;
16628 if (startswith (name
, "at="))
16630 char *s
= name
+ 3;
16632 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16633 as_bad (_("unrecognized register name `%s'"), s
);
16635 else if (strcmp (name
, "at") == 0)
16636 mips_opts
.at
= ATREG
;
16637 else if (strcmp (name
, "noat") == 0)
16638 mips_opts
.at
= ZERO
;
16639 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16640 mips_opts
.nomove
= 0;
16641 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16642 mips_opts
.nomove
= 1;
16643 else if (strcmp (name
, "bopt") == 0)
16644 mips_opts
.nobopt
= 0;
16645 else if (strcmp (name
, "nobopt") == 0)
16646 mips_opts
.nobopt
= 1;
16647 else if (strcmp (name
, "gp=32") == 0)
16649 else if (strcmp (name
, "gp=64") == 0)
16651 else if (strcmp (name
, "fp=32") == 0)
16653 else if (strcmp (name
, "fp=xx") == 0)
16655 else if (strcmp (name
, "fp=64") == 0)
16657 else if (strcmp (name
, "softfloat") == 0)
16658 mips_opts
.soft_float
= 1;
16659 else if (strcmp (name
, "hardfloat") == 0)
16660 mips_opts
.soft_float
= 0;
16661 else if (strcmp (name
, "singlefloat") == 0)
16662 mips_opts
.single_float
= 1;
16663 else if (strcmp (name
, "doublefloat") == 0)
16664 mips_opts
.single_float
= 0;
16665 else if (strcmp (name
, "nooddspreg") == 0)
16666 mips_opts
.oddspreg
= 0;
16667 else if (strcmp (name
, "oddspreg") == 0)
16668 mips_opts
.oddspreg
= 1;
16669 else if (strcmp (name
, "mips16") == 0
16670 || strcmp (name
, "MIPS-16") == 0)
16671 mips_opts
.mips16
= 1;
16672 else if (strcmp (name
, "nomips16") == 0
16673 || strcmp (name
, "noMIPS-16") == 0)
16674 mips_opts
.mips16
= 0;
16675 else if (strcmp (name
, "micromips") == 0)
16676 mips_opts
.micromips
= 1;
16677 else if (strcmp (name
, "nomicromips") == 0)
16678 mips_opts
.micromips
= 0;
16679 else if (name
[0] == 'n'
16681 && (ase
= mips_lookup_ase (name
+ 2)))
16682 mips_set_ase (ase
, &mips_opts
, false);
16683 else if ((ase
= mips_lookup_ase (name
)))
16684 mips_set_ase (ase
, &mips_opts
, true);
16685 else if (startswith (name
, "mips") || startswith (name
, "arch="))
16687 /* Permit the user to change the ISA and architecture on the fly.
16688 Needless to say, misuse can cause serious problems. */
16689 if (startswith (name
, "arch="))
16691 const struct mips_cpu_info
*p
;
16693 p
= mips_parse_cpu ("internal use", name
+ 5);
16695 as_bad (_("unknown architecture %s"), name
+ 5);
16698 mips_opts
.arch
= p
->cpu
;
16699 mips_opts
.isa
= p
->isa
;
16701 mips_opts
.init_ase
= p
->ase
;
16704 else if (startswith (name
, "mips"))
16706 const struct mips_cpu_info
*p
;
16708 p
= mips_parse_cpu ("internal use", name
);
16710 as_bad (_("unknown ISA level %s"), name
+ 4);
16713 mips_opts
.arch
= p
->cpu
;
16714 mips_opts
.isa
= p
->isa
;
16716 mips_opts
.init_ase
= p
->ase
;
16720 as_bad (_("unknown ISA or architecture %s"), name
);
16722 else if (strcmp (name
, "autoextend") == 0)
16723 mips_opts
.noautoextend
= 0;
16724 else if (strcmp (name
, "noautoextend") == 0)
16725 mips_opts
.noautoextend
= 1;
16726 else if (strcmp (name
, "insn32") == 0)
16727 mips_opts
.insn32
= true;
16728 else if (strcmp (name
, "noinsn32") == 0)
16729 mips_opts
.insn32
= false;
16730 else if (strcmp (name
, "sym32") == 0)
16731 mips_opts
.sym32
= true;
16732 else if (strcmp (name
, "nosym32") == 0)
16733 mips_opts
.sym32
= false;
16735 return OPTION_TYPE_BAD
;
16737 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16740 /* Handle the .set pseudo-op. */
16743 s_mipsset (int x ATTRIBUTE_UNUSED
)
16745 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16746 char *name
= input_line_pointer
, ch
;
16748 file_mips_check_options ();
16750 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16751 ++input_line_pointer
;
16752 ch
= *input_line_pointer
;
16753 *input_line_pointer
= '\0';
16755 if (strchr (name
, ','))
16757 /* Generic ".set" directive; use the generic handler. */
16758 *input_line_pointer
= ch
;
16759 input_line_pointer
= name
;
16764 if (strcmp (name
, "reorder") == 0)
16766 if (mips_opts
.noreorder
)
16769 else if (strcmp (name
, "noreorder") == 0)
16771 if (!mips_opts
.noreorder
)
16772 start_noreorder ();
16774 else if (strcmp (name
, "macro") == 0)
16775 mips_opts
.warn_about_macros
= 0;
16776 else if (strcmp (name
, "nomacro") == 0)
16778 if (mips_opts
.noreorder
== 0)
16779 as_bad (_("`noreorder' must be set before `nomacro'"));
16780 mips_opts
.warn_about_macros
= 1;
16782 else if (strcmp (name
, "gp=default") == 0)
16783 mips_opts
.gp
= file_mips_opts
.gp
;
16784 else if (strcmp (name
, "fp=default") == 0)
16785 mips_opts
.fp
= file_mips_opts
.fp
;
16786 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16788 mips_opts
.isa
= file_mips_opts
.isa
;
16789 mips_opts
.arch
= file_mips_opts
.arch
;
16790 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16791 mips_opts
.gp
= file_mips_opts
.gp
;
16792 mips_opts
.fp
= file_mips_opts
.fp
;
16794 else if (strcmp (name
, "push") == 0)
16796 struct mips_option_stack
*s
;
16798 s
= XNEW (struct mips_option_stack
);
16799 s
->next
= mips_opts_stack
;
16800 s
->options
= mips_opts
;
16801 mips_opts_stack
= s
;
16803 else if (strcmp (name
, "pop") == 0)
16805 struct mips_option_stack
*s
;
16807 s
= mips_opts_stack
;
16809 as_bad (_(".set pop with no .set push"));
16812 /* If we're changing the reorder mode we need to handle
16813 delay slots correctly. */
16814 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16815 start_noreorder ();
16816 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16819 mips_opts
= s
->options
;
16820 mips_opts_stack
= s
->next
;
16826 type
= parse_code_option (name
);
16827 if (type
== OPTION_TYPE_BAD
)
16828 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16831 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16832 registers based on what is supported by the arch/cpu. */
16833 if (type
== OPTION_TYPE_ISA
)
16835 switch (mips_opts
.isa
)
16840 /* MIPS I cannot support FPXX. */
16842 /* fall-through. */
16849 if (mips_opts
.fp
!= 0)
16865 if (mips_opts
.fp
!= 0)
16867 if (mips_opts
.arch
== CPU_R5900
)
16874 as_bad (_("unknown ISA level %s"), name
+ 4);
16879 mips_check_options (&mips_opts
, false);
16881 mips_check_isa_supports_ases ();
16882 *input_line_pointer
= ch
;
16883 demand_empty_rest_of_line ();
16886 /* Handle the .module pseudo-op. */
16889 s_module (int ignore ATTRIBUTE_UNUSED
)
16891 char *name
= input_line_pointer
, ch
;
16893 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16894 ++input_line_pointer
;
16895 ch
= *input_line_pointer
;
16896 *input_line_pointer
= '\0';
16898 if (!file_mips_opts_checked
)
16900 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16901 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16903 /* Update module level settings from mips_opts. */
16904 file_mips_opts
= mips_opts
;
16907 as_bad (_(".module is not permitted after generating code"));
16909 *input_line_pointer
= ch
;
16910 demand_empty_rest_of_line ();
16913 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16914 .option pic2. It means to generate SVR4 PIC calls. */
16917 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16919 mips_pic
= SVR4_PIC
;
16920 mips_abicalls
= true;
16922 if (g_switch_seen
&& g_switch_value
!= 0)
16923 as_warn (_("-G may not be used with SVR4 PIC code"));
16924 g_switch_value
= 0;
16926 bfd_set_gp_size (stdoutput
, 0);
16927 demand_empty_rest_of_line ();
16930 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16931 PIC code. It sets the $gp register for the function based on the
16932 function address, which is in the register named in the argument.
16933 This uses a relocation against _gp_disp, which is handled specially
16934 by the linker. The result is:
16935 lui $gp,%hi(_gp_disp)
16936 addiu $gp,$gp,%lo(_gp_disp)
16937 addu $gp,$gp,.cpload argument
16938 The .cpload argument is normally $25 == $t9.
16940 The -mno-shared option changes this to:
16941 lui $gp,%hi(__gnu_local_gp)
16942 addiu $gp,$gp,%lo(__gnu_local_gp)
16943 and the argument is ignored. This saves an instruction, but the
16944 resulting code is not position independent; it uses an absolute
16945 address for __gnu_local_gp. Thus code assembled with -mno-shared
16946 can go into an ordinary executable, but not into a shared library. */
16949 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16955 file_mips_check_options ();
16957 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16958 .cpload is ignored. */
16959 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16965 if (mips_opts
.mips16
)
16967 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16968 ignore_rest_of_line ();
16972 /* .cpload should be in a .set noreorder section. */
16973 if (mips_opts
.noreorder
== 0)
16974 as_warn (_(".cpload not in noreorder section"));
16976 reg
= tc_get_register (0);
16978 /* If we need to produce a 64-bit address, we are better off using
16979 the default instruction sequence. */
16980 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16982 ex
.X_op
= O_symbol
;
16983 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16985 ex
.X_op_symbol
= NULL
;
16986 ex
.X_add_number
= 0;
16988 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16989 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16991 mips_mark_labels ();
16992 mips_assembling_insn
= true;
16995 macro_build_lui (&ex
, mips_gp_register
);
16996 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16997 mips_gp_register
, BFD_RELOC_LO16
);
16999 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
17000 mips_gp_register
, reg
);
17003 mips_assembling_insn
= false;
17004 demand_empty_rest_of_line ();
17007 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
17008 .cpsetup $reg1, offset|$reg2, label
17010 If offset is given, this results in:
17011 sd $gp, offset($sp)
17012 lui $gp, %hi(%neg(%gp_rel(label)))
17013 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17014 daddu $gp, $gp, $reg1
17016 If $reg2 is given, this results in:
17018 lui $gp, %hi(%neg(%gp_rel(label)))
17019 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17020 daddu $gp, $gp, $reg1
17021 $reg1 is normally $25 == $t9.
17023 The -mno-shared option replaces the last three instructions with
17025 addiu $gp,$gp,%lo(_gp) */
17028 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17030 expressionS ex_off
;
17031 expressionS ex_sym
;
17034 file_mips_check_options ();
17036 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17037 We also need NewABI support. */
17038 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17044 if (mips_opts
.mips16
)
17046 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17047 ignore_rest_of_line ();
17051 reg1
= tc_get_register (0);
17052 SKIP_WHITESPACE ();
17053 if (*input_line_pointer
!= ',')
17055 as_bad (_("missing argument separator ',' for .cpsetup"));
17059 ++input_line_pointer
;
17060 SKIP_WHITESPACE ();
17061 if (*input_line_pointer
== '$')
17063 mips_cpreturn_register
= tc_get_register (0);
17064 mips_cpreturn_offset
= -1;
17068 mips_cpreturn_offset
= get_absolute_expression ();
17069 mips_cpreturn_register
= -1;
17071 SKIP_WHITESPACE ();
17072 if (*input_line_pointer
!= ',')
17074 as_bad (_("missing argument separator ',' for .cpsetup"));
17078 ++input_line_pointer
;
17079 SKIP_WHITESPACE ();
17080 expression (&ex_sym
);
17082 mips_mark_labels ();
17083 mips_assembling_insn
= true;
17086 if (mips_cpreturn_register
== -1)
17088 ex_off
.X_op
= O_constant
;
17089 ex_off
.X_add_symbol
= NULL
;
17090 ex_off
.X_op_symbol
= NULL
;
17091 ex_off
.X_add_number
= mips_cpreturn_offset
;
17093 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17094 BFD_RELOC_LO16
, SP
);
17097 move_register (mips_cpreturn_register
, mips_gp_register
);
17099 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17101 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17102 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17105 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17106 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17107 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17109 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17110 mips_gp_register
, reg1
);
17116 ex
.X_op
= O_symbol
;
17117 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17118 ex
.X_op_symbol
= NULL
;
17119 ex
.X_add_number
= 0;
17121 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17122 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17124 macro_build_lui (&ex
, mips_gp_register
);
17125 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17126 mips_gp_register
, BFD_RELOC_LO16
);
17131 mips_assembling_insn
= false;
17132 demand_empty_rest_of_line ();
17136 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17138 file_mips_check_options ();
17140 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17141 .cplocal is ignored. */
17142 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17148 if (mips_opts
.mips16
)
17150 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17151 ignore_rest_of_line ();
17155 mips_gp_register
= tc_get_register (0);
17156 demand_empty_rest_of_line ();
17159 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17160 offset from $sp. The offset is remembered, and after making a PIC
17161 call $gp is restored from that location. */
17164 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17168 file_mips_check_options ();
17170 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17171 .cprestore is ignored. */
17172 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17178 if (mips_opts
.mips16
)
17180 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17181 ignore_rest_of_line ();
17185 mips_cprestore_offset
= get_absolute_expression ();
17186 mips_cprestore_valid
= 1;
17188 ex
.X_op
= O_constant
;
17189 ex
.X_add_symbol
= NULL
;
17190 ex
.X_op_symbol
= NULL
;
17191 ex
.X_add_number
= mips_cprestore_offset
;
17193 mips_mark_labels ();
17194 mips_assembling_insn
= true;
17197 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17198 SP
, HAVE_64BIT_ADDRESSES
);
17201 mips_assembling_insn
= false;
17202 demand_empty_rest_of_line ();
17205 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17206 was given in the preceding .cpsetup, it results in:
17207 ld $gp, offset($sp)
17209 If a register $reg2 was given there, it results in:
17210 or $gp, $reg2, $0 */
17213 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17217 file_mips_check_options ();
17219 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17220 We also need NewABI support. */
17221 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17227 if (mips_opts
.mips16
)
17229 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17230 ignore_rest_of_line ();
17234 mips_mark_labels ();
17235 mips_assembling_insn
= true;
17238 if (mips_cpreturn_register
== -1)
17240 ex
.X_op
= O_constant
;
17241 ex
.X_add_symbol
= NULL
;
17242 ex
.X_op_symbol
= NULL
;
17243 ex
.X_add_number
= mips_cpreturn_offset
;
17245 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17248 move_register (mips_gp_register
, mips_cpreturn_register
);
17252 mips_assembling_insn
= false;
17253 demand_empty_rest_of_line ();
17256 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17257 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17258 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17259 debug information or MIPS16 TLS. */
17262 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17263 bfd_reloc_code_real_type rtype
)
17270 if (ex
.X_op
!= O_symbol
)
17272 as_bad (_("unsupported use of %s"), dirstr
);
17273 ignore_rest_of_line ();
17276 p
= frag_more (bytes
);
17277 md_number_to_chars (p
, 0, bytes
);
17278 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false, rtype
);
17279 demand_empty_rest_of_line ();
17280 mips_clear_insn_labels ();
17283 /* Handle .dtprelword. */
17286 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17288 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17291 /* Handle .dtpreldword. */
17294 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17296 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17299 /* Handle .tprelword. */
17302 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17304 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17307 /* Handle .tpreldword. */
17310 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17312 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17315 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17316 code. It sets the offset to use in gp_rel relocations. */
17319 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17321 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17322 We also need NewABI support. */
17323 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17329 mips_gprel_offset
= get_absolute_expression ();
17331 demand_empty_rest_of_line ();
17334 /* Handle the .gpword pseudo-op. This is used when generating PIC
17335 code. It generates a 32 bit GP relative reloc. */
17338 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17340 segment_info_type
*si
;
17341 struct insn_label_list
*l
;
17345 /* When not generating PIC code, this is treated as .word. */
17346 if (mips_pic
!= SVR4_PIC
)
17352 si
= seg_info (now_seg
);
17353 l
= si
->label_list
;
17354 mips_emit_delays ();
17356 mips_align (2, 0, l
);
17359 mips_clear_insn_labels ();
17361 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17363 as_bad (_("unsupported use of .gpword"));
17364 ignore_rest_of_line ();
17368 md_number_to_chars (p
, 0, 4);
17369 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
17370 BFD_RELOC_GPREL32
);
17372 demand_empty_rest_of_line ();
17376 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17378 segment_info_type
*si
;
17379 struct insn_label_list
*l
;
17383 /* When not generating PIC code, this is treated as .dword. */
17384 if (mips_pic
!= SVR4_PIC
)
17390 si
= seg_info (now_seg
);
17391 l
= si
->label_list
;
17392 mips_emit_delays ();
17394 mips_align (3, 0, l
);
17397 mips_clear_insn_labels ();
17399 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17401 as_bad (_("unsupported use of .gpdword"));
17402 ignore_rest_of_line ();
17406 md_number_to_chars (p
, 0, 8);
17407 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
17408 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17410 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17411 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17412 false, BFD_RELOC_64
)->fx_tcbit
= 1;
17414 demand_empty_rest_of_line ();
17417 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17418 tables. It generates a R_MIPS_EH reloc. */
17421 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17426 mips_emit_delays ();
17429 mips_clear_insn_labels ();
17431 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17433 as_bad (_("unsupported use of .ehword"));
17434 ignore_rest_of_line ();
17438 md_number_to_chars (p
, 0, 4);
17439 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
17440 BFD_RELOC_32_PCREL
);
17442 demand_empty_rest_of_line ();
17445 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17446 tables in SVR4 PIC code. */
17449 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17453 file_mips_check_options ();
17455 /* This is ignored when not generating SVR4 PIC code. */
17456 if (mips_pic
!= SVR4_PIC
)
17462 mips_mark_labels ();
17463 mips_assembling_insn
= true;
17465 /* Add $gp to the register named as an argument. */
17467 reg
= tc_get_register (0);
17468 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17471 mips_assembling_insn
= false;
17472 demand_empty_rest_of_line ();
17475 /* Handle the .insn pseudo-op. This marks instruction labels in
17476 mips16/micromips mode. This permits the linker to handle them specially,
17477 such as generating jalx instructions when needed. We also make
17478 them odd for the duration of the assembly, in order to generate the
17479 right sort of code. We will make them even in the adjust_symtab
17480 routine, while leaving them marked. This is convenient for the
17481 debugger and the disassembler. The linker knows to make them odd
17485 s_insn (int ignore ATTRIBUTE_UNUSED
)
17487 file_mips_check_options ();
17488 file_ase_mips16
|= mips_opts
.mips16
;
17489 file_ase_micromips
|= mips_opts
.micromips
;
17491 mips_mark_labels ();
17493 demand_empty_rest_of_line ();
17496 /* Handle the .nan pseudo-op. */
17499 s_nan (int ignore ATTRIBUTE_UNUSED
)
17501 static const char str_legacy
[] = "legacy";
17502 static const char str_2008
[] = "2008";
17505 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17507 if (i
== sizeof (str_2008
) - 1
17508 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17510 else if (i
== sizeof (str_legacy
) - 1
17511 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17513 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17516 as_bad (_("`%s' does not support legacy NaN"),
17517 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17520 as_bad (_("bad .nan directive"));
17522 input_line_pointer
+= i
;
17523 demand_empty_rest_of_line ();
17526 /* Handle a .stab[snd] directive. Ideally these directives would be
17527 implemented in a transparent way, so that removing them would not
17528 have any effect on the generated instructions. However, s_stab
17529 internally changes the section, so in practice we need to decide
17530 now whether the preceding label marks compressed code. We do not
17531 support changing the compression mode of a label after a .stab*
17532 directive, such as in:
17538 so the current mode wins. */
17541 s_mips_stab (int type
)
17543 file_mips_check_options ();
17544 mips_mark_labels ();
17548 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17551 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17558 c
= get_symbol_name (&name
);
17559 symbolP
= symbol_find_or_make (name
);
17560 S_SET_WEAK (symbolP
);
17561 *input_line_pointer
= c
;
17563 SKIP_WHITESPACE_AFTER_NAME ();
17565 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17567 if (S_IS_DEFINED (symbolP
))
17569 as_bad (_("ignoring attempt to redefine symbol %s"),
17570 S_GET_NAME (symbolP
));
17571 ignore_rest_of_line ();
17575 if (*input_line_pointer
== ',')
17577 ++input_line_pointer
;
17578 SKIP_WHITESPACE ();
17582 if (exp
.X_op
!= O_symbol
)
17584 as_bad (_("bad .weakext directive"));
17585 ignore_rest_of_line ();
17588 symbol_set_value_expression (symbolP
, &exp
);
17591 demand_empty_rest_of_line ();
17594 /* Parse a register string into a number. Called from the ECOFF code
17595 to parse .frame. The argument is non-zero if this is the frame
17596 register, so that we can record it in mips_frame_reg. */
17599 tc_get_register (int frame
)
17603 SKIP_WHITESPACE ();
17604 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17608 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17609 mips_frame_reg_valid
= 1;
17610 mips_cprestore_valid
= 0;
17616 md_section_align (asection
*seg
, valueT addr
)
17618 int align
= bfd_section_alignment (seg
);
17620 /* We don't need to align ELF sections to the full alignment.
17621 However, Irix 5 may prefer that we align them at least to a 16
17622 byte boundary. We don't bother to align the sections if we
17623 are targeted for an embedded system. */
17624 if (startswith (TARGET_OS
, "elf"))
17629 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17632 /* Utility routine, called from above as well. If called while the
17633 input file is still being read, it's only an approximation. (For
17634 example, a symbol may later become defined which appeared to be
17635 undefined earlier.) */
17638 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17643 if (g_switch_value
> 0)
17645 const char *symname
;
17648 /* Find out whether this symbol can be referenced off the $gp
17649 register. It can be if it is smaller than the -G size or if
17650 it is in the .sdata or .sbss section. Certain symbols can
17651 not be referenced off the $gp, although it appears as though
17653 symname
= S_GET_NAME (sym
);
17654 if (symname
!= (const char *) NULL
17655 && (strcmp (symname
, "eprol") == 0
17656 || strcmp (symname
, "etext") == 0
17657 || strcmp (symname
, "_gp") == 0
17658 || strcmp (symname
, "edata") == 0
17659 || strcmp (symname
, "_fbss") == 0
17660 || strcmp (symname
, "_fdata") == 0
17661 || strcmp (symname
, "_ftext") == 0
17662 || strcmp (symname
, "end") == 0
17663 || strcmp (symname
, "_gp_disp") == 0))
17665 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17667 #ifndef NO_ECOFF_DEBUGGING
17668 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17669 && (symbol_get_obj (sym
)->ecoff_extern_size
17670 <= g_switch_value
))
17672 /* We must defer this decision until after the whole
17673 file has been read, since there might be a .extern
17674 after the first use of this symbol. */
17675 || (before_relaxing
17676 #ifndef NO_ECOFF_DEBUGGING
17677 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17679 && S_GET_VALUE (sym
) == 0)
17680 || (S_GET_VALUE (sym
) != 0
17681 && S_GET_VALUE (sym
) <= g_switch_value
)))
17685 const char *segname
;
17687 segname
= segment_name (S_GET_SEGMENT (sym
));
17688 gas_assert (strcmp (segname
, ".lit8") != 0
17689 && strcmp (segname
, ".lit4") != 0);
17690 change
= (strcmp (segname
, ".sdata") != 0
17691 && strcmp (segname
, ".sbss") != 0
17692 && !startswith (segname
, ".sdata.")
17693 && !startswith (segname
, ".sbss.")
17694 && !startswith (segname
, ".gnu.linkonce.sb.")
17695 && !startswith (segname
, ".gnu.linkonce.s."));
17700 /* We are not optimizing for the $gp register. */
17705 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17708 pic_need_relax (symbolS
*sym
)
17712 /* Handle the case of a symbol equated to another symbol. */
17713 while (symbol_equated_reloc_p (sym
))
17717 /* It's possible to get a loop here in a badly written program. */
17718 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17724 if (symbol_section_p (sym
))
17727 symsec
= S_GET_SEGMENT (sym
);
17729 /* This must duplicate the test in adjust_reloc_syms. */
17730 return (!bfd_is_und_section (symsec
)
17731 && !bfd_is_abs_section (symsec
)
17732 && !bfd_is_com_section (symsec
)
17733 /* A global or weak symbol is treated as external. */
17734 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17737 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17738 convert a section-relative value VAL to the equivalent PC-relative
17742 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17743 offsetT val
, long stretch
)
17748 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17750 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17752 /* If the relax_marker of the symbol fragment differs from the
17753 relax_marker of this fragment, we have not yet adjusted the
17754 symbol fragment fr_address. We want to add in STRETCH in
17755 order to get a better estimate of the address. This
17756 particularly matters because of the shift bits. */
17757 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17761 /* Adjust stretch for any alignment frag. Note that if have
17762 been expanding the earlier code, the symbol may be
17763 defined in what appears to be an earlier frag. FIXME:
17764 This doesn't handle the fr_subtype field, which specifies
17765 a maximum number of bytes to skip when doing an
17767 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17769 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17772 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17774 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17783 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17785 /* The base address rules are complicated. The base address of
17786 a branch is the following instruction. The base address of a
17787 PC relative load or add is the instruction itself, but if it
17788 is in a delay slot (in which case it can not be extended) use
17789 the address of the instruction whose delay slot it is in. */
17790 if (pcrel_op
->include_isa_bit
)
17794 /* If we are currently assuming that this frag should be
17795 extended, then the current address is two bytes higher. */
17796 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17799 /* Ignore the low bit in the target, since it will be set
17800 for a text label. */
17803 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17805 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17808 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17813 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17814 extended opcode. SEC is the section the frag is in. */
17817 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17819 const struct mips_int_operand
*operand
;
17824 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17826 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17829 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17830 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17831 operand
= mips16_immed_operand (type
, false);
17832 if (S_FORCE_RELOC (fragp
->fr_symbol
, true)
17833 || (operand
->root
.type
== OP_PCREL
17835 : !bfd_is_abs_section (symsec
)))
17838 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17840 if (operand
->root
.type
== OP_PCREL
)
17842 const struct mips_pcrel_operand
*pcrel_op
;
17845 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17848 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17849 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17851 /* If any of the shifted bits are set, we must use an extended
17852 opcode. If the address depends on the size of this
17853 instruction, this can lead to a loop, so we arrange to always
17854 use an extended opcode. */
17855 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17857 fragp
->fr_subtype
=
17858 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17862 /* If we are about to mark a frag as extended because the value
17863 is precisely the next value above maxtiny, then there is a
17864 chance of an infinite loop as in the following code:
17869 In this case when the la is extended, foo is 0x3fc bytes
17870 away, so the la can be shrunk, but then foo is 0x400 away, so
17871 the la must be extended. To avoid this loop, we mark the
17872 frag as extended if it was small, and is about to become
17873 extended with the next value above maxtiny. */
17874 maxtiny
= mips_int_operand_max (operand
);
17875 if (val
== maxtiny
+ (1 << operand
->shift
)
17876 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17878 fragp
->fr_subtype
=
17879 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17884 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17887 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17888 macro expansion. SEC is the section the frag is in. We only
17889 support PC-relative instructions (LA, DLA, LW, LD) here, in
17890 non-PIC code using 32-bit addressing. */
17893 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17895 const struct mips_pcrel_operand
*pcrel_op
;
17896 const struct mips_int_operand
*operand
;
17901 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17903 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17905 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17908 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17914 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17915 if (bfd_is_abs_section (symsec
))
17917 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17919 if (S_FORCE_RELOC (fragp
->fr_symbol
, true) || sec
!= symsec
)
17922 operand
= mips16_immed_operand (type
, true);
17923 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17924 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17925 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17927 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17934 /* Compute the length of a branch sequence, and adjust the
17935 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17936 worst-case length is computed, with UPDATE being used to indicate
17937 whether an unconditional (-1), branch-likely (+1) or regular (0)
17938 branch is to be computed. */
17940 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17946 && S_IS_DEFINED (fragp
->fr_symbol
)
17947 && !S_IS_WEAK (fragp
->fr_symbol
)
17948 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17953 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17955 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17959 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17962 /* If the symbol is not defined or it's in a different segment,
17963 we emit the long sequence. */
17966 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17968 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17969 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17970 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17971 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17972 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17978 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17981 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17983 /* Additional space for PIC loading of target address. */
17985 if (mips_opts
.isa
== ISA_MIPS1
)
17986 /* Additional space for $at-stabilizing nop. */
17990 /* If branch is conditional. */
17991 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17998 /* Get a FRAG's branch instruction delay slot size, either from the
17999 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
18000 or SHORT_INSN_SIZE otherwise. */
18003 frag_branch_delay_slot_size (fragS
*fragp
, bool al
, int short_insn_size
)
18005 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18008 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
18010 return short_insn_size
;
18013 /* Compute the length of a branch sequence, and adjust the
18014 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18015 worst-case length is computed, with UPDATE being used to indicate
18016 whether an unconditional (-1), or regular (0) branch is to be
18020 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18022 bool insn32
= true;
18026 int short_insn_size
;
18032 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18033 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18034 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18035 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18037 short_insn_size
= insn32
? 4 : 2;
18040 && S_IS_DEFINED (fragp
->fr_symbol
)
18041 && !S_IS_WEAK (fragp
->fr_symbol
)
18042 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18047 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18048 /* Ignore the low bit in the target, since it will be set
18049 for a text label. */
18050 if ((val
& 1) != 0)
18053 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18057 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18060 /* If the symbol is not defined or it's in a different segment,
18061 we emit the long sequence. */
18064 if (fragp
&& update
18065 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18066 fragp
->fr_subtype
= (toofar
18067 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18068 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18073 bool compact_known
= fragp
!= NULL
;
18074 bool compact
= false;
18079 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18080 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18083 uncond
= update
< 0;
18085 /* If label is out of range, we turn branch <br>:
18087 <br> label # 4 bytes
18094 # compact && (!PIC || insn32)
18097 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
18098 length
+= short_insn_size
;
18100 /* If assembling PIC code, we further turn:
18106 lw/ld at, %got(label)(gp) # 4 bytes
18107 d/addiu at, %lo(label) # 4 bytes
18108 jr/c at # 2/4 bytes
18111 length
+= 4 + short_insn_size
;
18113 /* Add an extra nop if the jump has no compact form and we need
18114 to fill the delay slot. */
18115 if ((!pic
|| al
) && nods
)
18117 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
18118 : short_insn_size
);
18120 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18122 <brneg> 0f # 4 bytes
18123 nop # 2/4 bytes if !compact
18126 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
18130 /* Add an extra nop to fill the delay slot. */
18131 gas_assert (fragp
);
18132 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18138 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18139 bit accordingly. */
18142 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18147 && S_IS_DEFINED (fragp
->fr_symbol
)
18148 && !S_IS_WEAK (fragp
->fr_symbol
)
18149 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18155 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18156 /* Ignore the low bit in the target, since it will be set
18157 for a text label. */
18158 if ((val
& 1) != 0)
18161 /* Assume this is a 2-byte branch. */
18162 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18164 /* We try to avoid the infinite loop by not adding 2 more bytes for
18169 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18171 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18172 else if (type
== 'E')
18173 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18178 /* If the symbol is not defined or it's in a different segment,
18179 we emit a normal 32-bit branch. */
18182 if (fragp
&& update
18183 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18185 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18186 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18194 /* Estimate the size of a frag before relaxing. Unless this is the
18195 mips16, we are not really relaxing here, and the final size is
18196 encoded in the subtype information. For the mips16, we have to
18197 decide whether we are using an extended opcode or not. */
18200 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18204 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18207 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false);
18209 return fragp
->fr_var
;
18212 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18214 /* We don't want to modify the EXTENDED bit here; it might get us
18215 into infinite loops. We change it only in mips_relax_frag(). */
18216 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18217 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18219 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18222 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18226 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18227 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, false);
18228 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18229 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, false);
18230 fragp
->fr_var
= length
;
18235 if (mips_pic
== VXWORKS_PIC
)
18236 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18238 else if (RELAX_PIC (fragp
->fr_subtype
))
18239 change
= pic_need_relax (fragp
->fr_symbol
);
18241 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18245 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18246 return -RELAX_FIRST (fragp
->fr_subtype
);
18249 return -RELAX_SECOND (fragp
->fr_subtype
);
18252 /* This is called to see whether a reloc against a defined symbol
18253 should be converted into a reloc against a section. */
18256 mips_fix_adjustable (fixS
*fixp
)
18258 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18259 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18262 if (fixp
->fx_addsy
== NULL
)
18265 /* Allow relocs used for EH tables. */
18266 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18269 /* If symbol SYM is in a mergeable section, relocations of the form
18270 SYM + 0 can usually be made section-relative. The mergeable data
18271 is then identified by the section offset rather than by the symbol.
18273 However, if we're generating REL LO16 relocations, the offset is split
18274 between the LO16 and partnering high part relocation. The linker will
18275 need to recalculate the complete offset in order to correctly identify
18278 The linker has traditionally not looked for the partnering high part
18279 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18280 placed anywhere. Rather than break backwards compatibility by changing
18281 this, it seems better not to force the issue, and instead keep the
18282 original symbol. This will work with either linker behavior. */
18283 if ((lo16_reloc_p (fixp
->fx_r_type
)
18284 || reloc_needs_lo_p (fixp
->fx_r_type
))
18285 && HAVE_IN_PLACE_ADDENDS
18286 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18289 /* There is no place to store an in-place offset for JALR relocations. */
18290 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18293 /* Likewise an in-range offset of limited PC-relative relocations may
18294 overflow the in-place relocatable field if recalculated against the
18295 start address of the symbol's containing section.
18297 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18298 section relative to allow linker relaxations to be performed later on. */
18299 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18300 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18303 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18304 to a floating-point stub. The same is true for non-R_MIPS16_26
18305 relocations against MIPS16 functions; in this case, the stub becomes
18306 the function's canonical address.
18308 Floating-point stubs are stored in unique .mips16.call.* or
18309 .mips16.fn.* sections. If a stub T for function F is in section S,
18310 the first relocation in section S must be against F; this is how the
18311 linker determines the target function. All relocations that might
18312 resolve to T must also be against F. We therefore have the following
18313 restrictions, which are given in an intentionally-redundant way:
18315 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18318 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18319 if that stub might be used.
18321 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18324 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18325 that stub might be used.
18327 There is a further restriction:
18329 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18330 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18331 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18332 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18333 against MIPS16 or microMIPS symbols because we need to keep the
18334 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18335 detection and JAL or BAL to JALX instruction conversion in the
18338 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18339 against a MIPS16 symbol. We deal with (5) by additionally leaving
18340 alone any jump and branch relocations against a microMIPS symbol.
18342 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18343 relocation against some symbol R, no relocation against R may be
18344 reduced. (Note that this deals with (2) as well as (1) because
18345 relocations against global symbols will never be reduced on ELF
18346 targets.) This approach is a little simpler than trying to detect
18347 stub sections, and gives the "all or nothing" per-symbol consistency
18348 that we have for MIPS16 symbols. */
18349 if (fixp
->fx_subsy
== NULL
18350 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18351 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18352 && (jmp_reloc_p (fixp
->fx_r_type
)
18353 || b_reloc_p (fixp
->fx_r_type
)))
18354 || *symbol_get_tc (fixp
->fx_addsy
)))
18360 /* Translate internal representation of relocation info to BFD target
18364 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18366 static arelent
*retval
[4];
18368 bfd_reloc_code_real_type code
;
18370 memset (retval
, 0, sizeof(retval
));
18371 reloc
= retval
[0] = XCNEW (arelent
);
18372 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18373 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18374 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18376 if (fixp
->fx_pcrel
)
18378 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18379 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18380 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18381 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18382 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18383 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18384 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18385 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18386 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18387 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18388 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18389 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18391 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18392 Relocations want only the symbol offset. */
18393 switch (fixp
->fx_r_type
)
18395 case BFD_RELOC_MIPS_18_PCREL_S3
:
18396 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18399 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18403 else if (HAVE_IN_PLACE_ADDENDS
18404 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18405 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18406 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18408 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18409 addend accordingly. */
18410 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18413 reloc
->addend
= fixp
->fx_addnumber
;
18415 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18416 entry to be used in the relocation's section offset. */
18417 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18419 reloc
->address
= reloc
->addend
;
18423 code
= fixp
->fx_r_type
;
18425 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18426 if (reloc
->howto
== NULL
)
18428 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18429 _("cannot represent %s relocation in this object file"
18431 bfd_get_reloc_code_name (code
));
18438 /* Relax a machine dependent frag. This returns the amount by which
18439 the current size of the frag should change. */
18442 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18444 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18446 offsetT old_var
= fragp
->fr_var
;
18448 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
18450 return fragp
->fr_var
- old_var
;
18453 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18455 offsetT old_var
= fragp
->fr_var
;
18456 offsetT new_var
= 4;
18458 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18459 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, true);
18460 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18461 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, true);
18462 fragp
->fr_var
= new_var
;
18464 return new_var
- old_var
;
18467 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18470 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18472 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18474 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18475 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18477 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18479 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18485 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18487 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18489 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18490 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18491 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18493 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18495 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18503 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18505 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18507 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18508 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18509 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18513 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18514 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18521 /* Convert a machine dependent frag. */
18524 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18526 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18529 unsigned long insn
;
18532 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18533 insn
= read_insn (buf
);
18535 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18537 /* We generate a fixup instead of applying it right now
18538 because, if there are linker relaxations, we're going to
18539 need the relocations. */
18540 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18541 fragp
->fr_symbol
, fragp
->fr_offset
,
18542 true, BFD_RELOC_16_PCREL_S2
);
18543 fixp
->fx_file
= fragp
->fr_file
;
18544 fixp
->fx_line
= fragp
->fr_line
;
18546 buf
= write_insn (buf
, insn
);
18552 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18553 _("relaxed out-of-range branch into a jump"));
18555 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18558 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18560 /* Reverse the branch. */
18561 switch ((insn
>> 28) & 0xf)
18564 if ((insn
& 0xff000000) == 0x47000000
18565 || (insn
& 0xff600000) == 0x45600000)
18567 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18568 reversed by tweaking bit 23. */
18569 insn
^= 0x00800000;
18573 /* bc[0-3][tf]l? instructions can have the condition
18574 reversed by tweaking a single TF bit, and their
18575 opcodes all have 0x4???????. */
18576 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18577 insn
^= 0x00010000;
18582 /* bltz 0x04000000 bgez 0x04010000
18583 bltzal 0x04100000 bgezal 0x04110000 */
18584 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18585 insn
^= 0x00010000;
18589 /* beq 0x10000000 bne 0x14000000
18590 blez 0x18000000 bgtz 0x1c000000 */
18591 insn
^= 0x04000000;
18599 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18601 /* Clear the and-link bit. */
18602 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18604 /* bltzal 0x04100000 bgezal 0x04110000
18605 bltzall 0x04120000 bgezall 0x04130000 */
18606 insn
&= ~0x00100000;
18609 /* Branch over the branch (if the branch was likely) or the
18610 full jump (not likely case). Compute the offset from the
18611 current instruction to branch to. */
18612 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18616 /* How many bytes in instructions we've already emitted? */
18617 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18618 /* How many bytes in instructions from here to the end? */
18619 i
= fragp
->fr_var
- i
;
18621 /* Convert to instruction count. */
18623 /* Branch counts from the next instruction. */
18626 /* Branch over the jump. */
18627 buf
= write_insn (buf
, insn
);
18630 buf
= write_insn (buf
, 0);
18632 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18634 /* beql $0, $0, 2f */
18636 /* Compute the PC offset from the current instruction to
18637 the end of the variable frag. */
18638 /* How many bytes in instructions we've already emitted? */
18639 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18640 /* How many bytes in instructions from here to the end? */
18641 i
= fragp
->fr_var
- i
;
18642 /* Convert to instruction count. */
18644 /* Don't decrement i, because we want to branch over the
18648 buf
= write_insn (buf
, insn
);
18649 buf
= write_insn (buf
, 0);
18653 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18656 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18657 ? 0x0c000000 : 0x08000000);
18659 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18660 fragp
->fr_symbol
, fragp
->fr_offset
,
18661 false, BFD_RELOC_MIPS_JMP
);
18662 fixp
->fx_file
= fragp
->fr_file
;
18663 fixp
->fx_line
= fragp
->fr_line
;
18665 buf
= write_insn (buf
, insn
);
18669 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18671 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18672 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18673 insn
|= at
<< OP_SH_RT
;
18675 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18676 fragp
->fr_symbol
, fragp
->fr_offset
,
18677 false, BFD_RELOC_MIPS_GOT16
);
18678 fixp
->fx_file
= fragp
->fr_file
;
18679 fixp
->fx_line
= fragp
->fr_line
;
18681 buf
= write_insn (buf
, insn
);
18683 if (mips_opts
.isa
== ISA_MIPS1
)
18685 buf
= write_insn (buf
, 0);
18687 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18688 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18689 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18691 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18692 fragp
->fr_symbol
, fragp
->fr_offset
,
18693 false, BFD_RELOC_LO16
);
18694 fixp
->fx_file
= fragp
->fr_file
;
18695 fixp
->fx_line
= fragp
->fr_line
;
18697 buf
= write_insn (buf
, insn
);
18700 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18704 insn
|= at
<< OP_SH_RS
;
18706 buf
= write_insn (buf
, insn
);
18710 fragp
->fr_fix
+= fragp
->fr_var
;
18711 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18715 /* Relax microMIPS branches. */
18716 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18718 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18719 bool compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18720 bool insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18721 bool nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18722 bool pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18723 bool al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18724 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18726 unsigned long insn
;
18729 fragp
->fr_fix
+= fragp
->fr_var
;
18731 /* Handle 16-bit branches that fit or are forced to fit. */
18732 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18734 /* We generate a fixup instead of applying it right now,
18735 because if there is linker relaxation, we're going to
18736 need the relocations. */
18740 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18741 fragp
->fr_symbol
, fragp
->fr_offset
,
18742 true, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18745 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18746 fragp
->fr_symbol
, fragp
->fr_offset
,
18747 true, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18753 fixp
->fx_file
= fragp
->fr_file
;
18754 fixp
->fx_line
= fragp
->fr_line
;
18756 /* These relocations can have an addend that won't fit in
18758 fixp
->fx_no_overflow
= 1;
18763 /* Handle 32-bit branches that fit or are forced to fit. */
18764 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18765 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18767 /* We generate a fixup instead of applying it right now,
18768 because if there is linker relaxation, we're going to
18769 need the relocations. */
18770 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18771 fragp
->fr_symbol
, fragp
->fr_offset
,
18772 true, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18773 fixp
->fx_file
= fragp
->fr_file
;
18774 fixp
->fx_line
= fragp
->fr_line
;
18778 insn
= read_compressed_insn (buf
, 4);
18783 /* Check the short-delay-slot bit. */
18784 if (!al
|| (insn
& 0x02000000) != 0)
18785 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18787 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18790 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18795 /* Relax 16-bit branches to 32-bit branches. */
18798 insn
= read_compressed_insn (buf
, 2);
18800 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18801 insn
= 0x94000000; /* beq */
18802 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18804 unsigned long regno
;
18806 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18807 regno
= micromips_to_32_reg_d_map
[regno
];
18808 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18809 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18814 /* Nothing else to do, just write it out. */
18815 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18816 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18818 buf
= write_compressed_insn (buf
, insn
, 4);
18820 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18821 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18826 insn
= read_compressed_insn (buf
, 4);
18828 /* Relax 32-bit branches to a sequence of instructions. */
18829 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18830 _("relaxed out-of-range branch into a jump"));
18832 /* Set the short-delay-slot bit. */
18833 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18835 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18839 /* Reverse the branch. */
18840 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18841 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18842 insn
^= 0x20000000;
18843 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18844 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18845 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18846 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18847 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18848 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18849 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18850 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18851 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18852 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18853 insn
^= 0x00400000;
18854 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18855 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18856 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18857 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18858 insn
^= 0x00200000;
18859 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18861 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18863 insn
^= 0x00800000;
18869 /* Clear the and-link and short-delay-slot bits. */
18870 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18872 /* bltzal 0x40200000 bgezal 0x40600000 */
18873 /* bltzals 0x42200000 bgezals 0x42600000 */
18874 insn
&= ~0x02200000;
18877 /* Make a label at the end for use with the branch. */
18878 l
= symbol_new (micromips_label_name (), asec
, fragp
, fragp
->fr_fix
);
18879 micromips_label_inc ();
18880 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18883 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, true,
18884 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18885 fixp
->fx_file
= fragp
->fr_file
;
18886 fixp
->fx_line
= fragp
->fr_line
;
18888 /* Branch over the jump. */
18889 buf
= write_compressed_insn (buf
, insn
, 4);
18895 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18897 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18903 unsigned long jal
= (short_ds
|| nods
18904 ? 0x74000000 : 0xf4000000); /* jal/s */
18906 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18907 insn
= al
? jal
: 0xd4000000;
18909 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18910 fragp
->fr_symbol
, fragp
->fr_offset
,
18911 false, BFD_RELOC_MICROMIPS_JMP
);
18912 fixp
->fx_file
= fragp
->fr_file
;
18913 fixp
->fx_line
= fragp
->fr_line
;
18915 buf
= write_compressed_insn (buf
, insn
, 4);
18917 if (compact
|| nods
)
18921 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18923 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18928 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18930 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18931 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18932 insn
|= at
<< MICROMIPSOP_SH_RT
;
18934 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18935 fragp
->fr_symbol
, fragp
->fr_offset
,
18936 false, BFD_RELOC_MICROMIPS_GOT16
);
18937 fixp
->fx_file
= fragp
->fr_file
;
18938 fixp
->fx_line
= fragp
->fr_line
;
18940 buf
= write_compressed_insn (buf
, insn
, 4);
18942 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18943 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18944 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18946 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18947 fragp
->fr_symbol
, fragp
->fr_offset
,
18948 false, BFD_RELOC_MICROMIPS_LO16
);
18949 fixp
->fx_file
= fragp
->fr_file
;
18950 fixp
->fx_line
= fragp
->fr_line
;
18952 buf
= write_compressed_insn (buf
, insn
, 4);
18957 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18958 insn
|= at
<< MICROMIPSOP_SH_RS
;
18960 buf
= write_compressed_insn (buf
, insn
, 4);
18962 if (compact
|| nods
)
18964 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18968 /* jr/jrc/jalr/jalrs $at */
18969 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18970 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18972 insn
= al
? jalr
: jr
;
18973 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18975 buf
= write_compressed_insn (buf
, insn
, 2);
18980 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18982 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18987 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18991 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18994 const struct mips_int_operand
*operand
;
18997 unsigned int user_length
;
18999 unsigned long insn
;
19004 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
19005 operand
= mips16_immed_operand (type
, false);
19007 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
19008 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
19009 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
19011 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
19012 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, true)
19013 || (operand
->root
.type
== OP_PCREL
&& !mac
19015 : !bfd_is_abs_section (symsec
)));
19017 if (operand
->root
.type
== OP_PCREL
&& !mac
)
19019 const struct mips_pcrel_operand
*pcrel_op
;
19021 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
19023 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
19025 if (!mips_ignore_branch_isa
19026 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
19027 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19028 _("branch to a symbol in another ISA mode"));
19029 else if ((fragp
->fr_offset
& 0x1) != 0)
19030 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19031 _("branch to misaligned address (0x%lx)"),
19032 (long) (resolve_symbol_value (fragp
->fr_symbol
)
19033 + (fragp
->fr_offset
& ~1)));
19036 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
19038 /* Make sure the section winds up with the alignment we have
19040 if (operand
->shift
> 0)
19041 record_alignment (asec
, operand
->shift
);
19044 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
19045 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
19048 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19049 _("macro instruction expanded into multiple "
19050 "instructions in a branch delay slot"));
19052 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19053 _("extended instruction in a branch delay slot"));
19055 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
19056 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19057 _("macro instruction expanded into multiple "
19060 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19062 insn
= read_compressed_insn (buf
, 2);
19064 insn
|= MIPS16_EXTEND
;
19066 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
19068 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
19080 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
19081 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
19083 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
19089 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
19091 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19092 fragp
->fr_symbol
, fragp
->fr_offset
,
19093 false, BFD_RELOC_MIPS16_HI16_S
);
19094 fixp
->fx_file
= fragp
->fr_file
;
19095 fixp
->fx_line
= fragp
->fr_line
;
19097 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
19098 fragp
->fr_symbol
, fragp
->fr_offset
,
19099 false, BFD_RELOC_MIPS16_LO16
);
19100 fixp
->fx_file
= fragp
->fr_file
;
19101 fixp
->fx_line
= fragp
->fr_line
;
19106 switch (insn
& 0xf800)
19108 case 0x0800: /* ADDIU */
19109 reg
= (insn
>> 8) & 0x7;
19110 op
= 0xf0004800 | (reg
<< 8);
19112 case 0xb000: /* LW */
19113 reg
= (insn
>> 8) & 0x7;
19114 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
19116 case 0xf800: /* I64 */
19117 reg
= (insn
>> 5) & 0x7;
19118 switch (insn
& 0x0700)
19120 case 0x0400: /* LD */
19121 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
19123 case 0x0600: /* DADDIU */
19124 op
= 0xf000fd00 | (reg
<< 5);
19134 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19135 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19136 buf
= write_compressed_insn (buf
, new, 4);
19139 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19140 buf
= write_compressed_insn (buf
, new, 4);
19142 op
|= mips16_immed_extend (val
, 16);
19143 buf
= write_compressed_insn (buf
, op
, 4);
19145 fragp
->fr_fix
+= e2
? 8 : 12;
19149 unsigned int length
= ext
? 4 : 2;
19153 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19160 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19165 if (mac
|| reloc
== BFD_RELOC_NONE
)
19166 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19167 _("unsupported relocation"));
19170 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19171 fragp
->fr_symbol
, fragp
->fr_offset
,
19173 fixp
->fx_file
= fragp
->fr_file
;
19174 fixp
->fx_line
= fragp
->fr_line
;
19177 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19178 _("invalid unextended operand value"));
19181 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19182 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19184 gas_assert (mips16_opcode_length (insn
) == length
);
19185 write_compressed_insn (buf
, insn
, length
);
19186 fragp
->fr_fix
+= length
;
19191 relax_substateT subtype
= fragp
->fr_subtype
;
19192 bool second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19193 bool use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19194 unsigned int first
, second
;
19197 first
= RELAX_FIRST (subtype
);
19198 second
= RELAX_SECOND (subtype
);
19199 fixp
= (fixS
*) fragp
->fr_opcode
;
19201 /* If the delay slot chosen does not match the size of the instruction,
19202 then emit a warning. */
19203 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19204 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19209 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19210 | RELAX_DELAY_SLOT_SIZE_FIRST
19211 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19212 msg
= macro_warning (s
);
19214 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19218 /* Possibly emit a warning if we've chosen the longer option. */
19219 if (use_second
== second_longer
)
19225 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19226 msg
= macro_warning (s
);
19228 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19232 /* Go through all the fixups for the first sequence. Disable them
19233 (by marking them as done) if we're going to use the second
19234 sequence instead. */
19236 && fixp
->fx_frag
== fragp
19237 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19239 if (subtype
& RELAX_USE_SECOND
)
19241 fixp
= fixp
->fx_next
;
19244 /* Go through the fixups for the second sequence. Disable them if
19245 we're going to use the first sequence, otherwise adjust their
19246 addresses to account for the relaxation. */
19247 while (fixp
&& fixp
->fx_frag
== fragp
)
19249 if (subtype
& RELAX_USE_SECOND
)
19250 fixp
->fx_where
-= first
;
19253 fixp
= fixp
->fx_next
;
19256 /* Now modify the frag contents. */
19257 if (subtype
& RELAX_USE_SECOND
)
19261 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19262 memmove (start
, start
+ first
, second
);
19263 fragp
->fr_fix
-= first
;
19266 fragp
->fr_fix
-= second
;
19270 /* This function is called after the relocs have been generated.
19271 We've been storing mips16 text labels as odd. Here we convert them
19272 back to even for the convenience of the debugger. */
19275 mips_frob_file_after_relocs (void)
19278 unsigned int count
, i
;
19280 syms
= bfd_get_outsymbols (stdoutput
);
19281 count
= bfd_get_symcount (stdoutput
);
19282 for (i
= 0; i
< count
; i
++, syms
++)
19283 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19284 && ((*syms
)->value
& 1) != 0)
19286 (*syms
)->value
&= ~1;
19287 /* If the symbol has an odd size, it was probably computed
19288 incorrectly, so adjust that as well. */
19289 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19290 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19294 /* This function is called whenever a label is defined, including fake
19295 labels instantiated off the dot special symbol. It is used when
19296 handling branch delays; if a branch has a label, we assume we cannot
19297 move it. This also bumps the value of the symbol by 1 in compressed
19301 mips_record_label (symbolS
*sym
)
19303 segment_info_type
*si
= seg_info (now_seg
);
19304 struct insn_label_list
*l
;
19306 if (free_insn_labels
== NULL
)
19307 l
= XNEW (struct insn_label_list
);
19310 l
= free_insn_labels
;
19311 free_insn_labels
= l
->next
;
19315 l
->next
= si
->label_list
;
19316 si
->label_list
= l
;
19319 /* This function is called as tc_frob_label() whenever a label is defined
19320 and adds a DWARF-2 record we only want for true labels. */
19323 mips_define_label (symbolS
*sym
)
19325 mips_record_label (sym
);
19326 dwarf2_emit_label (sym
);
19329 /* This function is called by tc_new_dot_label whenever a new dot symbol
19333 mips_add_dot_label (symbolS
*sym
)
19335 mips_record_label (sym
);
19336 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19337 mips_compressed_mark_label (sym
);
19340 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19341 static unsigned int
19342 mips_convert_ase_flags (int ase
)
19344 unsigned int ext_ases
= 0;
19347 ext_ases
|= AFL_ASE_DSP
;
19348 if (ase
& ASE_DSPR2
)
19349 ext_ases
|= AFL_ASE_DSPR2
;
19350 if (ase
& ASE_DSPR3
)
19351 ext_ases
|= AFL_ASE_DSPR3
;
19353 ext_ases
|= AFL_ASE_EVA
;
19355 ext_ases
|= AFL_ASE_MCU
;
19356 if (ase
& ASE_MDMX
)
19357 ext_ases
|= AFL_ASE_MDMX
;
19358 if (ase
& ASE_MIPS3D
)
19359 ext_ases
|= AFL_ASE_MIPS3D
;
19361 ext_ases
|= AFL_ASE_MT
;
19362 if (ase
& ASE_SMARTMIPS
)
19363 ext_ases
|= AFL_ASE_SMARTMIPS
;
19364 if (ase
& ASE_VIRT
)
19365 ext_ases
|= AFL_ASE_VIRT
;
19367 ext_ases
|= AFL_ASE_MSA
;
19369 ext_ases
|= AFL_ASE_XPA
;
19370 if (ase
& ASE_MIPS16E2
)
19371 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19373 ext_ases
|= AFL_ASE_CRC
;
19374 if (ase
& ASE_GINV
)
19375 ext_ases
|= AFL_ASE_GINV
;
19376 if (ase
& ASE_LOONGSON_MMI
)
19377 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19378 if (ase
& ASE_LOONGSON_CAM
)
19379 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19380 if (ase
& ASE_LOONGSON_EXT
)
19381 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19382 if (ase
& ASE_LOONGSON_EXT2
)
19383 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19387 /* Some special processing for a MIPS ELF file. */
19390 mips_elf_final_processing (void)
19393 Elf_Internal_ABIFlags_v0 flags
;
19397 switch (file_mips_opts
.isa
)
19400 flags
.isa_level
= 1;
19403 flags
.isa_level
= 2;
19406 flags
.isa_level
= 3;
19409 flags
.isa_level
= 4;
19412 flags
.isa_level
= 5;
19415 flags
.isa_level
= 32;
19419 flags
.isa_level
= 32;
19423 flags
.isa_level
= 32;
19427 flags
.isa_level
= 32;
19431 flags
.isa_level
= 32;
19435 flags
.isa_level
= 64;
19439 flags
.isa_level
= 64;
19443 flags
.isa_level
= 64;
19447 flags
.isa_level
= 64;
19451 flags
.isa_level
= 64;
19456 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19457 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19458 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19459 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19461 flags
.cpr2_size
= AFL_REG_NONE
;
19462 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19463 Tag_GNU_MIPS_ABI_FP
);
19464 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19465 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19466 if (file_ase_mips16
)
19467 flags
.ases
|= AFL_ASE_MIPS16
;
19468 if (file_ase_micromips
)
19469 flags
.ases
|= AFL_ASE_MICROMIPS
;
19471 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19472 || file_mips_opts
.fp
== 64)
19473 && file_mips_opts
.oddspreg
)
19474 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19477 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19478 ((Elf_External_ABIFlags_v0
*)
19481 /* Write out the register information. */
19482 if (mips_abi
!= N64_ABI
)
19486 s
.ri_gprmask
= mips_gprmask
;
19487 s
.ri_cprmask
[0] = mips_cprmask
[0];
19488 s
.ri_cprmask
[1] = mips_cprmask
[1];
19489 s
.ri_cprmask
[2] = mips_cprmask
[2];
19490 s
.ri_cprmask
[3] = mips_cprmask
[3];
19491 /* The gp_value field is set by the MIPS ELF backend. */
19493 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19494 ((Elf32_External_RegInfo
*)
19495 mips_regmask_frag
));
19499 Elf64_Internal_RegInfo s
;
19501 s
.ri_gprmask
= mips_gprmask
;
19503 s
.ri_cprmask
[0] = mips_cprmask
[0];
19504 s
.ri_cprmask
[1] = mips_cprmask
[1];
19505 s
.ri_cprmask
[2] = mips_cprmask
[2];
19506 s
.ri_cprmask
[3] = mips_cprmask
[3];
19507 /* The gp_value field is set by the MIPS ELF backend. */
19509 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19510 ((Elf64_External_RegInfo
*)
19511 mips_regmask_frag
));
19514 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19515 sort of BFD interface for this. */
19516 if (mips_any_noreorder
)
19517 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19518 if (mips_pic
!= NO_PIC
)
19520 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19521 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19524 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19526 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19527 defined at present; this might need to change in future. */
19528 if (file_ase_mips16
)
19529 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19530 if (file_ase_micromips
)
19531 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19532 if (file_mips_opts
.ase
& ASE_MDMX
)
19533 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19535 /* Set the MIPS ELF ABI flags. */
19536 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19537 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19538 else if (mips_abi
== O64_ABI
)
19539 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19540 else if (mips_abi
== EABI_ABI
)
19542 if (file_mips_opts
.gp
== 64)
19543 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19545 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19548 /* Nothing to do for N32_ABI or N64_ABI. */
19550 if (mips_32bitmode
)
19551 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19553 if (mips_nan2008
== 1)
19554 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19556 /* 32 bit code with 64 bit FP registers. */
19557 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19558 Tag_GNU_MIPS_ABI_FP
);
19559 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19560 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19563 typedef struct proc
{
19565 symbolS
*func_end_sym
;
19566 unsigned long reg_mask
;
19567 unsigned long reg_offset
;
19568 unsigned long fpreg_mask
;
19569 unsigned long fpreg_offset
;
19570 unsigned long frame_offset
;
19571 unsigned long frame_reg
;
19572 unsigned long pc_reg
;
19575 static procS cur_proc
;
19576 static procS
*cur_proc_ptr
;
19577 static int numprocs
;
19579 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19580 as "2", and a normal nop as "0". */
19582 #define NOP_OPCODE_MIPS 0
19583 #define NOP_OPCODE_MIPS16 1
19584 #define NOP_OPCODE_MICROMIPS 2
19587 mips_nop_opcode (void)
19589 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19590 return NOP_OPCODE_MICROMIPS
;
19591 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19592 return NOP_OPCODE_MIPS16
;
19594 return NOP_OPCODE_MIPS
;
19597 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19598 32-bit microMIPS NOPs here (if applicable). */
19601 mips_handle_align (fragS
*fragp
)
19605 int bytes
, size
, excess
;
19608 if (fragp
->fr_type
!= rs_align_code
)
19611 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19613 switch (nop_opcode
)
19615 case NOP_OPCODE_MICROMIPS
:
19616 opcode
= micromips_nop32_insn
.insn_opcode
;
19619 case NOP_OPCODE_MIPS16
:
19620 opcode
= mips16_nop_insn
.insn_opcode
;
19623 case NOP_OPCODE_MIPS
:
19625 opcode
= nop_insn
.insn_opcode
;
19630 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19631 excess
= bytes
% size
;
19633 /* Handle the leading part if we're not inserting a whole number of
19634 instructions, and make it the end of the fixed part of the frag.
19635 Try to fit in a short microMIPS NOP if applicable and possible,
19636 and use zeroes otherwise. */
19637 gas_assert (excess
< 4);
19638 fragp
->fr_fix
+= excess
;
19643 /* Fall through. */
19645 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19647 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19651 /* Fall through. */
19654 /* Fall through. */
19659 md_number_to_chars (p
, opcode
, size
);
19660 fragp
->fr_var
= size
;
19669 if (*input_line_pointer
== '-')
19671 ++input_line_pointer
;
19674 if (!ISDIGIT (*input_line_pointer
))
19675 as_bad (_("expected simple number"));
19676 if (input_line_pointer
[0] == '0')
19678 if (input_line_pointer
[1] == 'x')
19680 input_line_pointer
+= 2;
19681 while (ISXDIGIT (*input_line_pointer
))
19684 val
|= hex_value (*input_line_pointer
++);
19686 return negative
? -val
: val
;
19690 ++input_line_pointer
;
19691 while (ISDIGIT (*input_line_pointer
))
19694 val
|= *input_line_pointer
++ - '0';
19696 return negative
? -val
: val
;
19699 if (!ISDIGIT (*input_line_pointer
))
19701 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19702 *input_line_pointer
, *input_line_pointer
);
19703 as_warn (_("invalid number"));
19706 while (ISDIGIT (*input_line_pointer
))
19709 val
+= *input_line_pointer
++ - '0';
19711 return negative
? -val
: val
;
19714 /* The .file directive; just like the usual .file directive, but there
19715 is an initial number which is the ECOFF file index. In the non-ECOFF
19716 case .file implies DWARF-2. */
19719 s_mips_file (int x ATTRIBUTE_UNUSED
)
19721 static int first_file_directive
= 0;
19723 if (ECOFF_DEBUGGING
)
19732 filename
= dwarf2_directive_filename ();
19734 /* Versions of GCC up to 3.1 start files with a ".file"
19735 directive even for stabs output. Make sure that this
19736 ".file" is handled. Note that you need a version of GCC
19737 after 3.1 in order to support DWARF-2 on MIPS. */
19738 if (filename
!= NULL
&& ! first_file_directive
)
19740 (void) new_logical_line (filename
, -1);
19741 s_app_file_string (filename
, 0);
19743 first_file_directive
= 1;
19747 /* The .loc directive, implying DWARF-2. */
19750 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19752 if (!ECOFF_DEBUGGING
)
19753 dwarf2_directive_loc (0);
19756 /* The .end directive. */
19759 s_mips_end (int x ATTRIBUTE_UNUSED
)
19763 /* Following functions need their own .frame and .cprestore directives. */
19764 mips_frame_reg_valid
= 0;
19765 mips_cprestore_valid
= 0;
19767 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19770 demand_empty_rest_of_line ();
19775 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19776 as_warn (_(".end not in text section"));
19780 as_warn (_(".end directive without a preceding .ent directive"));
19781 demand_empty_rest_of_line ();
19787 gas_assert (S_GET_NAME (p
));
19788 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19789 as_warn (_(".end symbol does not match .ent symbol"));
19791 if (debug_type
== DEBUG_STABS
)
19792 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19796 as_warn (_(".end directive missing or unknown symbol"));
19798 /* Create an expression to calculate the size of the function. */
19799 if (p
&& cur_proc_ptr
)
19801 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19802 expressionS
*exp
= XNEW (expressionS
);
19805 exp
->X_op
= O_subtract
;
19806 exp
->X_add_symbol
= symbol_temp_new_now ();
19807 exp
->X_op_symbol
= p
;
19808 exp
->X_add_number
= 0;
19810 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19813 #ifdef md_flush_pending_output
19814 md_flush_pending_output ();
19817 /* Generate a .pdr section. */
19818 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19820 segT saved_seg
= now_seg
;
19821 subsegT saved_subseg
= now_subseg
;
19825 gas_assert (pdr_seg
);
19826 subseg_set (pdr_seg
, 0);
19828 /* Write the symbol. */
19829 exp
.X_op
= O_symbol
;
19830 exp
.X_add_symbol
= p
;
19831 exp
.X_add_number
= 0;
19832 emit_expr (&exp
, 4);
19834 fragp
= frag_more (7 * 4);
19836 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19837 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19838 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19839 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19840 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19841 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19842 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19844 subseg_set (saved_seg
, saved_subseg
);
19847 cur_proc_ptr
= NULL
;
19850 /* The .aent and .ent directives. */
19853 s_mips_ent (int aent
)
19857 symbolP
= get_symbol ();
19858 if (*input_line_pointer
== ',')
19859 ++input_line_pointer
;
19860 SKIP_WHITESPACE ();
19861 if (ISDIGIT (*input_line_pointer
)
19862 || *input_line_pointer
== '-')
19865 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19866 as_warn (_(".ent or .aent not in text section"));
19868 if (!aent
&& cur_proc_ptr
)
19869 as_warn (_("missing .end"));
19873 /* This function needs its own .frame and .cprestore directives. */
19874 mips_frame_reg_valid
= 0;
19875 mips_cprestore_valid
= 0;
19877 cur_proc_ptr
= &cur_proc
;
19878 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19880 cur_proc_ptr
->func_sym
= symbolP
;
19884 if (debug_type
== DEBUG_STABS
)
19885 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19886 S_GET_NAME (symbolP
));
19889 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19891 demand_empty_rest_of_line ();
19894 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19895 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19896 s_mips_frame is used so that we can set the PDR information correctly.
19897 We can't use the ecoff routines because they make reference to the ecoff
19898 symbol table (in the mdebug section). */
19901 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19903 if (ECOFF_DEBUGGING
)
19909 if (cur_proc_ptr
== (procS
*) NULL
)
19911 as_warn (_(".frame outside of .ent"));
19912 demand_empty_rest_of_line ();
19916 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19918 SKIP_WHITESPACE ();
19919 if (*input_line_pointer
++ != ','
19920 || get_absolute_expression_and_terminator (&val
) != ',')
19922 as_warn (_("bad .frame directive"));
19923 --input_line_pointer
;
19924 demand_empty_rest_of_line ();
19928 cur_proc_ptr
->frame_offset
= val
;
19929 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19931 demand_empty_rest_of_line ();
19935 /* The .fmask and .mask directives. If the mdebug section is present
19936 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19937 embedded targets, s_mips_mask is used so that we can set the PDR
19938 information correctly. We can't use the ecoff routines because they
19939 make reference to the ecoff symbol table (in the mdebug section). */
19942 s_mips_mask (int reg_type
)
19944 if (ECOFF_DEBUGGING
)
19945 s_ignore (reg_type
);
19950 if (cur_proc_ptr
== (procS
*) NULL
)
19952 as_warn (_(".mask/.fmask outside of .ent"));
19953 demand_empty_rest_of_line ();
19957 if (get_absolute_expression_and_terminator (&mask
) != ',')
19959 as_warn (_("bad .mask/.fmask directive"));
19960 --input_line_pointer
;
19961 demand_empty_rest_of_line ();
19965 off
= get_absolute_expression ();
19967 if (reg_type
== 'F')
19969 cur_proc_ptr
->fpreg_mask
= mask
;
19970 cur_proc_ptr
->fpreg_offset
= off
;
19974 cur_proc_ptr
->reg_mask
= mask
;
19975 cur_proc_ptr
->reg_offset
= off
;
19978 demand_empty_rest_of_line ();
19982 /* A table describing all the processors gas knows about. Names are
19983 matched in the order listed.
19985 To ease comparison, please keep this table in the same order as
19986 gcc's mips_cpu_info_table[]. */
19987 static const struct mips_cpu_info mips_cpu_info_table
[] =
19989 /* Entries for generic ISAs. */
19990 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19991 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19992 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19993 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19994 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19995 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19996 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19997 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19998 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19999 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
20000 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
20001 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
20002 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
20003 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
20004 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
20007 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20008 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20009 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
20012 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
20015 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
20016 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
20017 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
20018 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
20019 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20020 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20021 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
20022 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
20023 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
20024 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
20025 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
20026 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
20027 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
20028 /* ST Microelectronics Loongson 2E and 2F cores. */
20029 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
20030 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
20033 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
20034 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
20035 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
20036 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
20037 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
20038 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
20039 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
20040 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
20041 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
20042 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
20043 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
20044 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
20045 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
20046 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
20047 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
20050 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20051 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20052 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20053 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
20055 /* MIPS 32 Release 2 */
20056 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20057 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20058 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20059 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20060 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20061 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20062 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20063 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20064 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20065 ISA_MIPS32R2
, CPU_MIPS32R2
},
20066 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20067 ISA_MIPS32R2
, CPU_MIPS32R2
},
20068 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20069 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20070 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20071 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20072 /* Deprecated forms of the above. */
20073 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20074 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20075 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20076 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20077 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20078 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20079 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20080 /* Deprecated forms of the above. */
20081 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20082 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20083 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20084 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20085 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20086 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20087 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20088 /* Deprecated forms of the above. */
20089 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20090 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20091 /* 34Kn is a 34kc without DSP. */
20092 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20093 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20094 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20095 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20096 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20097 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20098 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20099 /* Deprecated forms of the above. */
20100 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20101 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20102 /* 1004K cores are multiprocessor versions of the 34K. */
20103 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20104 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20105 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20106 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20107 /* interaptiv is the new name for 1004kf. */
20108 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20109 { "interaptiv-mr2", 0,
20110 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
20111 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
20112 /* M5100 family. */
20113 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20114 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20115 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20116 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20119 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20120 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20121 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20122 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20124 /* Broadcom SB-1 CPU core. */
20125 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20126 /* Broadcom SB-1A CPU core. */
20127 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20129 /* MIPS 64 Release 2. */
20130 /* Loongson CPU core. */
20131 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20132 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20133 ISA_MIPS64R2
, CPU_GS464
},
20134 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20135 ISA_MIPS64R2
, CPU_GS464
},
20136 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20137 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20138 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20139 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20141 /* Cavium Networks Octeon CPU core. */
20142 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20143 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20144 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20145 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20148 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20151 XLP is mostly like XLR, with the prominent exception that it is
20152 MIPS64R2 rather than MIPS64. */
20153 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20155 /* MIPS 64 Release 6. */
20156 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20157 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20158 ISA_MIPS64R6
, CPU_MIPS64R6
},
20159 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20162 { NULL
, 0, 0, 0, 0 }
20166 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20167 with a final "000" replaced by "k". Ignore case.
20169 Note: this function is shared between GCC and GAS. */
20172 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20174 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20175 given
++, canonical
++;
20177 return ((*given
== 0 && *canonical
== 0)
20178 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20182 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20183 CPU name. We've traditionally allowed a lot of variation here.
20185 Note: this function is shared between GCC and GAS. */
20188 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20190 /* First see if the name matches exactly, or with a final "000"
20191 turned into "k". */
20192 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20195 /* If not, try comparing based on numerical designation alone.
20196 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20197 if (TOLOWER (*given
) == 'r')
20199 if (!ISDIGIT (*given
))
20202 /* Skip over some well-known prefixes in the canonical name,
20203 hoping to find a number there too. */
20204 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20206 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20208 else if (TOLOWER (canonical
[0]) == 'r')
20211 return mips_strict_matching_cpu_name_p (canonical
, given
);
20215 /* Parse an option that takes the name of a processor as its argument.
20216 OPTION is the name of the option and CPU_STRING is the argument.
20217 Return the corresponding processor enumeration if the CPU_STRING is
20218 recognized, otherwise report an error and return null.
20220 A similar function exists in GCC. */
20222 static const struct mips_cpu_info
*
20223 mips_parse_cpu (const char *option
, const char *cpu_string
)
20225 const struct mips_cpu_info
*p
;
20227 /* 'from-abi' selects the most compatible architecture for the given
20228 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20229 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20230 version. Look first at the -mgp options, if given, otherwise base
20231 the choice on MIPS_DEFAULT_64BIT.
20233 Treat NO_ABI like the EABIs. One reason to do this is that the
20234 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20235 architecture. This code picks MIPS I for 'mips' and MIPS III for
20236 'mips64', just as we did in the days before 'from-abi'. */
20237 if (strcasecmp (cpu_string
, "from-abi") == 0)
20239 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20240 return mips_cpu_info_from_isa (ISA_MIPS1
);
20242 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20243 return mips_cpu_info_from_isa (ISA_MIPS3
);
20245 if (file_mips_opts
.gp
>= 0)
20246 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20247 ? ISA_MIPS1
: ISA_MIPS3
);
20249 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20254 /* 'default' has traditionally been a no-op. Probably not very useful. */
20255 if (strcasecmp (cpu_string
, "default") == 0)
20258 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20259 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20262 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20266 /* Return the canonical processor information for ISA (a member of the
20267 ISA_MIPS* enumeration). */
20269 static const struct mips_cpu_info
*
20270 mips_cpu_info_from_isa (int isa
)
20274 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20275 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20276 && isa
== mips_cpu_info_table
[i
].isa
)
20277 return (&mips_cpu_info_table
[i
]);
20282 static const struct mips_cpu_info
*
20283 mips_cpu_info_from_arch (int arch
)
20287 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20288 if (arch
== mips_cpu_info_table
[i
].cpu
)
20289 return (&mips_cpu_info_table
[i
]);
20295 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20299 fprintf (stream
, "%24s", "");
20304 fprintf (stream
, ", ");
20308 if (*col_p
+ strlen (string
) > 72)
20310 fprintf (stream
, "\n%24s", "");
20314 fprintf (stream
, "%s", string
);
20315 *col_p
+= strlen (string
);
20321 md_show_usage (FILE *stream
)
20326 fprintf (stream
, _("\
20328 -EB generate big endian output\n\
20329 -EL generate little endian output\n\
20330 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20331 -G NUM allow referencing objects up to NUM bytes\n\
20332 implicitly with the gp register [default 8]\n"));
20333 fprintf (stream
, _("\
20334 -mips1 generate MIPS ISA I instructions\n\
20335 -mips2 generate MIPS ISA II instructions\n\
20336 -mips3 generate MIPS ISA III instructions\n\
20337 -mips4 generate MIPS ISA IV instructions\n\
20338 -mips5 generate MIPS ISA V instructions\n\
20339 -mips32 generate MIPS32 ISA instructions\n\
20340 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20341 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20342 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20343 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20344 -mips64 generate MIPS64 ISA instructions\n\
20345 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20346 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20347 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20348 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20349 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20353 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20354 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20355 show (stream
, "from-abi", &column
, &first
);
20356 fputc ('\n', stream
);
20358 fprintf (stream
, _("\
20359 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20360 -no-mCPU don't generate code specific to CPU.\n\
20361 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20365 show (stream
, "3900", &column
, &first
);
20366 show (stream
, "4010", &column
, &first
);
20367 show (stream
, "4100", &column
, &first
);
20368 show (stream
, "4650", &column
, &first
);
20369 fputc ('\n', stream
);
20371 fprintf (stream
, _("\
20372 -mips16 generate mips16 instructions\n\
20373 -no-mips16 do not generate mips16 instructions\n"));
20374 fprintf (stream
, _("\
20375 -mmips16e2 generate MIPS16e2 instructions\n\
20376 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20377 fprintf (stream
, _("\
20378 -mmicromips generate microMIPS instructions\n\
20379 -mno-micromips do not generate microMIPS instructions\n"));
20380 fprintf (stream
, _("\
20381 -msmartmips generate smartmips instructions\n\
20382 -mno-smartmips do not generate smartmips instructions\n"));
20383 fprintf (stream
, _("\
20384 -mdsp generate DSP instructions\n\
20385 -mno-dsp do not generate DSP instructions\n"));
20386 fprintf (stream
, _("\
20387 -mdspr2 generate DSP R2 instructions\n\
20388 -mno-dspr2 do not generate DSP R2 instructions\n"));
20389 fprintf (stream
, _("\
20390 -mdspr3 generate DSP R3 instructions\n\
20391 -mno-dspr3 do not generate DSP R3 instructions\n"));
20392 fprintf (stream
, _("\
20393 -mmt generate MT instructions\n\
20394 -mno-mt do not generate MT instructions\n"));
20395 fprintf (stream
, _("\
20396 -mmcu generate MCU instructions\n\
20397 -mno-mcu do not generate MCU instructions\n"));
20398 fprintf (stream
, _("\
20399 -mmsa generate MSA instructions\n\
20400 -mno-msa do not generate MSA instructions\n"));
20401 fprintf (stream
, _("\
20402 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20403 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20404 fprintf (stream
, _("\
20405 -mvirt generate Virtualization instructions\n\
20406 -mno-virt do not generate Virtualization instructions\n"));
20407 fprintf (stream
, _("\
20408 -mcrc generate CRC instructions\n\
20409 -mno-crc do not generate CRC instructions\n"));
20410 fprintf (stream
, _("\
20411 -mginv generate Global INValidate (GINV) instructions\n\
20412 -mno-ginv do not generate Global INValidate instructions\n"));
20413 fprintf (stream
, _("\
20414 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20415 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20416 fprintf (stream
, _("\
20417 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20418 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20419 fprintf (stream
, _("\
20420 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20421 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20422 fprintf (stream
, _("\
20423 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20424 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20425 fprintf (stream
, _("\
20426 -minsn32 only generate 32-bit microMIPS instructions\n\
20427 -mno-insn32 generate all microMIPS instructions\n"));
20428 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20429 fprintf (stream
, _("\
20430 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20431 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20433 fprintf (stream
, _("\
20434 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20435 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20437 fprintf (stream
, _("\
20438 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20439 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20440 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20441 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20442 -mfix-vr4120 work around certain VR4120 errata\n\
20443 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20444 -mfix-24k insert a nop after ERET and DERET instructions\n\
20445 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20446 -mfix-r5900 work around R5900 short loop errata\n\
20447 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20448 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20449 -msym32 assume all symbols have 32-bit values\n\
20450 -O0 do not remove unneeded NOPs, do not swap branches\n\
20451 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20452 -O2 remove unneeded NOPs and swap branches\n\
20453 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20454 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20455 fprintf (stream
, _("\
20456 -mhard-float allow floating-point instructions\n\
20457 -msoft-float do not allow floating-point instructions\n\
20458 -msingle-float only allow 32-bit floating-point operations\n\
20459 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20460 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20461 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20462 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20463 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20464 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20468 show (stream
, "legacy", &column
, &first
);
20469 show (stream
, "2008", &column
, &first
);
20471 fputc ('\n', stream
);
20473 fprintf (stream
, _("\
20474 -KPIC, -call_shared generate SVR4 position independent code\n\
20475 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20476 -mvxworks-pic generate VxWorks position independent code\n\
20477 -non_shared do not generate code that can operate with DSOs\n\
20478 -xgot assume a 32 bit GOT\n\
20479 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20480 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20481 position dependent (non shared) code\n\
20482 -mabi=ABI create ABI conformant object file for:\n"));
20486 show (stream
, "32", &column
, &first
);
20487 show (stream
, "o64", &column
, &first
);
20488 show (stream
, "n32", &column
, &first
);
20489 show (stream
, "64", &column
, &first
);
20490 show (stream
, "eabi", &column
, &first
);
20492 fputc ('\n', stream
);
20494 fprintf (stream
, _("\
20495 -32 create o32 ABI object file%s\n"),
20496 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20497 fprintf (stream
, _("\
20498 -n32 create n32 ABI object file%s\n"),
20499 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20500 fprintf (stream
, _("\
20501 -64 create 64 ABI object file%s\n"),
20502 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20507 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20509 if (HAVE_64BIT_SYMBOLS
)
20510 return dwarf2_format_64bit_irix
;
20512 return dwarf2_format_32bit
;
20517 mips_dwarf2_addr_size (void)
20519 if (HAVE_64BIT_OBJECTS
)
20525 /* Standard calling conventions leave the CFA at SP on entry. */
20527 mips_cfi_frame_initial_instructions (void)
20529 cfi_add_CFA_def_cfa_register (SP
);
20533 tc_mips_regname_to_dw2regnum (char *regname
)
20535 unsigned int regnum
= -1;
20538 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20544 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20545 Given a symbolic attribute NAME, return the proper integer value.
20546 Returns -1 if the attribute is not known. */
20549 mips_convert_symbolic_attribute (const char *name
)
20551 static const struct
20556 attribute_table
[] =
20558 #define T(tag) {#tag, tag}
20559 T (Tag_GNU_MIPS_ABI_FP
),
20560 T (Tag_GNU_MIPS_ABI_MSA
),
20568 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20569 if (streq (name
, attribute_table
[i
].name
))
20570 return attribute_table
[i
].tag
;
20578 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20580 mips_emit_delays ();
20582 as_warn (_("missing .end at end of assembly"));
20584 /* Just in case no code was emitted, do the consistency check. */
20585 file_mips_check_options ();
20587 /* Set a floating-point ABI if the user did not. */
20588 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20590 /* Perform consistency checks on the floating-point ABI. */
20591 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20592 Tag_GNU_MIPS_ABI_FP
);
20593 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20594 check_fpabi (fpabi
);
20598 /* Soft-float gets precedence over single-float, the two options should
20599 not be used together so this should not matter. */
20600 if (file_mips_opts
.soft_float
== 1)
20601 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20602 /* Single-float gets precedence over all double_float cases. */
20603 else if (file_mips_opts
.single_float
== 1)
20604 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20607 switch (file_mips_opts
.fp
)
20610 if (file_mips_opts
.gp
== 32)
20611 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20614 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20617 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20618 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20619 else if (file_mips_opts
.gp
== 32)
20620 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20622 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20627 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20628 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20632 /* Returns the relocation type required for a particular CFI encoding. */
20634 bfd_reloc_code_real_type
20635 mips_cfi_reloc_for_encoding (int encoding
)
20637 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20638 return BFD_RELOC_32_PCREL
;
20639 else return BFD_RELOC_NONE
;