1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1138 | ((e2) ? 0x100 : 0) \
1139 | ((pic) ? 0x200 : 0) \
1140 | ((sym32) ? 0x400 : 0) \
1141 | ((nomacro) ? 0x800 : 0) \
1142 | ((small) ? 0x1000 : 0) \
1143 | ((ext) ? 0x2000 : 0) \
1144 | ((dslot) ? 0x4000 : 0) \
1145 | ((jal_dslot) ? 0x8000 : 0))
1147 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1148 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1149 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1150 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1151 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1152 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1153 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1154 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1155 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1158 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1159 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1160 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1161 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1162 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1163 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1164 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1165 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1166 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1168 /* For microMIPS code, we use relaxation similar to one we use for
1169 MIPS16 code. Some instructions that take immediate values support
1170 two encodings: a small one which takes some small value, and a
1171 larger one which takes a 16 bit value. As some branches also follow
1172 this pattern, relaxing these values is required.
1174 We can assemble both microMIPS and normal MIPS code in a single
1175 object. Therefore, we need to support this type of relaxation at
1176 the same time that we support the relaxation described above. We
1177 use one of the high bits of the subtype field to distinguish these
1180 The information we store for this type of relaxation is the argument
1181 code found in the opcode file for this relocation, the register
1182 selected as the assembler temporary, whether in the 32-bit
1183 instruction mode, whether the branch is unconditional, whether it is
1184 compact, whether there is no delay-slot instruction available to fill
1185 in, whether it stores the link address implicitly in $ra, whether
1186 relaxation of out-of-range 32-bit branches to a sequence of
1187 instructions is enabled, and whether the displacement of a branch is
1188 too large to fit as an immediate argument of a 16-bit and a 32-bit
1189 branch, respectively. */
1190 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1191 uncond, compact, link, nods, \
1192 relax32, toofar16, toofar32) \
1195 | (((at) & 0x1f) << 8) \
1196 | ((insn32) ? 0x2000 : 0) \
1197 | ((pic) ? 0x4000 : 0) \
1198 | ((uncond) ? 0x8000 : 0) \
1199 | ((compact) ? 0x10000 : 0) \
1200 | ((link) ? 0x20000 : 0) \
1201 | ((nods) ? 0x40000 : 0) \
1202 | ((relax32) ? 0x80000 : 0) \
1203 | ((toofar16) ? 0x100000 : 0) \
1204 | ((toofar32) ? 0x200000 : 0))
1205 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1206 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1207 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1208 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1209 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1210 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1211 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1212 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1213 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1214 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1216 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1217 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1218 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1219 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1220 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1221 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1223 /* Sign-extend 16-bit value X. */
1224 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1226 /* Is the given value a sign-extended 32-bit value? */
1227 #define IS_SEXT_32BIT_NUM(x) \
1228 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1229 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1231 /* Is the given value a sign-extended 16-bit value? */
1232 #define IS_SEXT_16BIT_NUM(x) \
1233 (((x) &~ (offsetT) 0x7fff) == 0 \
1234 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1236 /* Is the given value a sign-extended 12-bit value? */
1237 #define IS_SEXT_12BIT_NUM(x) \
1238 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1240 /* Is the given value a sign-extended 9-bit value? */
1241 #define IS_SEXT_9BIT_NUM(x) \
1242 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1244 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1245 #define IS_ZEXT_32BIT_NUM(x) \
1246 (((x) &~ (offsetT) 0xffffffff) == 0 \
1247 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1249 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1251 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1252 (((STRUCT) >> (SHIFT)) & (MASK))
1254 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1255 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1257 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1258 : EXTRACT_BITS ((INSN).insn_opcode, \
1259 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1260 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1261 EXTRACT_BITS ((INSN).insn_opcode, \
1262 MIPS16OP_MASK_##FIELD, \
1263 MIPS16OP_SH_##FIELD)
1265 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1266 #define MIPS16_EXTEND (0xf000U << 16)
1268 /* Whether or not we are emitting a branch-likely macro. */
1269 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1271 /* Global variables used when generating relaxable macros. See the
1272 comment above RELAX_ENCODE for more details about how relaxation
1275 /* 0 if we're not emitting a relaxable macro.
1276 1 if we're emitting the first of the two relaxation alternatives.
1277 2 if we're emitting the second alternative. */
1280 /* The first relaxable fixup in the current frag. (In other words,
1281 the first fixup that refers to relaxable code.) */
1284 /* sizes[0] says how many bytes of the first alternative are stored in
1285 the current frag. Likewise sizes[1] for the second alternative. */
1286 unsigned int sizes
[2];
1288 /* The symbol on which the choice of sequence depends. */
1292 /* Global variables used to decide whether a macro needs a warning. */
1294 /* True if the macro is in a branch delay slot. */
1295 bfd_boolean delay_slot_p
;
1297 /* Set to the length in bytes required if the macro is in a delay slot
1298 that requires a specific length of instruction, otherwise zero. */
1299 unsigned int delay_slot_length
;
1301 /* For relaxable macros, sizes[0] is the length of the first alternative
1302 in bytes and sizes[1] is the length of the second alternative.
1303 For non-relaxable macros, both elements give the length of the
1305 unsigned int sizes
[2];
1307 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1308 instruction of the first alternative in bytes and first_insn_sizes[1]
1309 is the length of the first instruction of the second alternative.
1310 For non-relaxable macros, both elements give the length of the first
1311 instruction in bytes.
1313 Set to zero if we haven't yet seen the first instruction. */
1314 unsigned int first_insn_sizes
[2];
1316 /* For relaxable macros, insns[0] is the number of instructions for the
1317 first alternative and insns[1] is the number of instructions for the
1320 For non-relaxable macros, both elements give the number of
1321 instructions for the macro. */
1322 unsigned int insns
[2];
1324 /* The first variant frag for this macro. */
1326 } mips_macro_warning
;
1328 /* Prototypes for static functions. */
1330 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1332 static void append_insn
1333 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1334 bfd_boolean expansionp
);
1335 static void mips_no_prev_insn (void);
1336 static void macro_build (expressionS
*, const char *, const char *, ...);
1337 static void mips16_macro_build
1338 (expressionS
*, const char *, const char *, va_list *);
1339 static void load_register (int, expressionS
*, int);
1340 static void macro_start (void);
1341 static void macro_end (void);
1342 static void macro (struct mips_cl_insn
*ip
, char *str
);
1343 static void mips16_macro (struct mips_cl_insn
* ip
);
1344 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1345 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1346 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1347 static void mips16_immed
1348 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1352 static void my_getExpression (expressionS
*, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void s_nan (int);
1378 static void s_module (int);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type
);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean
pic_need_relax (symbolS
*);
1388 static int relaxed_branch_length (fragS
*, asection
*, int);
1389 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1390 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1391 static void file_mips_check_options (void);
1393 /* Table and functions used to map between CPU/ISA names, and
1394 ISA levels, and CPU numbers. */
1396 struct mips_cpu_info
1398 const char *name
; /* CPU or ISA name. */
1399 int flags
; /* MIPS_CPU_* flags. */
1400 int ase
; /* Set of ASEs implemented by the CPU. */
1401 int isa
; /* ISA level. */
1402 int cpu
; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1407 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1408 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1409 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1411 /* Command-line options. */
1412 const char *md_shortopts
= "O::g::G:";
1416 OPTION_MARCH
= OPTION_MD_BASE
,
1448 OPTION_NO_SMARTMIPS
,
1458 OPTION_NO_MICROMIPS
,
1463 OPTION_COMPAT_ARCH_BASE
,
1472 OPTION_M7000_HILO_FIX
,
1473 OPTION_MNO_7000_HILO_FIX
,
1477 OPTION_NO_FIX_RM7000
,
1478 OPTION_FIX_LOONGSON2F_JUMP
,
1479 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1480 OPTION_FIX_LOONGSON2F_NOP
,
1481 OPTION_NO_FIX_LOONGSON2F_NOP
,
1483 OPTION_NO_FIX_VR4120
,
1485 OPTION_NO_FIX_VR4130
,
1486 OPTION_FIX_CN63XXP1
,
1487 OPTION_NO_FIX_CN63XXP1
,
1494 OPTION_CONSTRUCT_FLOATS
,
1495 OPTION_NO_CONSTRUCT_FLOATS
,
1499 OPTION_RELAX_BRANCH
,
1500 OPTION_NO_RELAX_BRANCH
,
1501 OPTION_IGNORE_BRANCH_ISA
,
1502 OPTION_NO_IGNORE_BRANCH_ISA
,
1511 OPTION_SINGLE_FLOAT
,
1512 OPTION_DOUBLE_FLOAT
,
1525 OPTION_MVXWORKS_PIC
,
1528 OPTION_NO_ODD_SPREG
,
1532 struct option md_longopts
[] =
1534 /* Options which specify architecture. */
1535 {"march", required_argument
, NULL
, OPTION_MARCH
},
1536 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1537 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1538 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1539 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1540 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1541 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1542 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1543 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1544 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1545 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1546 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1547 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1548 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1549 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1550 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1551 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1552 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1554 /* Options which specify Application Specific Extensions (ASEs). */
1555 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1556 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1557 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1558 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1559 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1560 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1561 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1562 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1563 {"mmt", no_argument
, NULL
, OPTION_MT
},
1564 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1565 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1566 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1567 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1568 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1569 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1570 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1571 {"meva", no_argument
, NULL
, OPTION_EVA
},
1572 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1573 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1574 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1575 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1576 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1577 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1578 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1579 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1580 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1581 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1582 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1583 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1584 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1586 /* Old-style architecture options. Don't add more of these. */
1587 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1588 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1589 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1590 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1591 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1592 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1593 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1594 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1596 /* Options which enable bug fixes. */
1597 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1598 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1599 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1600 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1601 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1602 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1603 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1604 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1605 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1606 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1607 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1608 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1609 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1610 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1611 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1612 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1613 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1615 /* Miscellaneous options. */
1616 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1617 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1618 {"break", no_argument
, NULL
, OPTION_BREAK
},
1619 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1620 {"EB", no_argument
, NULL
, OPTION_EB
},
1621 {"EL", no_argument
, NULL
, OPTION_EL
},
1622 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1623 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1624 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1625 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1626 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1627 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1628 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1629 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1630 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1631 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1632 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1633 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1634 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1635 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1636 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1637 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1638 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1639 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1640 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1641 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1642 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1643 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1644 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1646 /* Strictly speaking this next option is ELF specific,
1647 but we allow it for other ports as well in order to
1648 make testing easier. */
1649 {"32", no_argument
, NULL
, OPTION_32
},
1651 /* ELF-specific options. */
1652 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1653 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1654 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1655 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1656 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1657 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1658 {"n32", no_argument
, NULL
, OPTION_N32
},
1659 {"64", no_argument
, NULL
, OPTION_64
},
1660 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1661 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1662 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1663 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1664 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1665 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1667 {NULL
, no_argument
, NULL
, 0}
1669 size_t md_longopts_size
= sizeof (md_longopts
);
1671 /* Information about either an Application Specific Extension or an
1672 optional architecture feature that, for simplicity, we treat in the
1673 same way as an ASE. */
1676 /* The name of the ASE, used in both the command-line and .set options. */
1679 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1680 and 64-bit architectures, the flags here refer to the subset that
1681 is available on both. */
1684 /* The ASE_* flag used for instructions that are available on 64-bit
1685 architectures but that are not included in FLAGS. */
1686 unsigned int flags64
;
1688 /* The command-line options that turn the ASE on and off. */
1692 /* The minimum required architecture revisions for MIPS32, MIPS64,
1693 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1696 int micromips32_rev
;
1697 int micromips64_rev
;
1699 /* The architecture where the ASE was removed or -1 if the extension has not
1704 /* A table of all supported ASEs. */
1705 static const struct mips_ase mips_ases
[] = {
1706 { "dsp", ASE_DSP
, ASE_DSP64
,
1707 OPTION_DSP
, OPTION_NO_DSP
,
1711 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1712 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1716 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1717 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1721 { "eva", ASE_EVA
, 0,
1722 OPTION_EVA
, OPTION_NO_EVA
,
1726 { "mcu", ASE_MCU
, 0,
1727 OPTION_MCU
, OPTION_NO_MCU
,
1731 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1732 { "mdmx", ASE_MDMX
, 0,
1733 OPTION_MDMX
, OPTION_NO_MDMX
,
1737 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1738 { "mips3d", ASE_MIPS3D
, 0,
1739 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1744 OPTION_MT
, OPTION_NO_MT
,
1748 { "smartmips", ASE_SMARTMIPS
, 0,
1749 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1753 { "virt", ASE_VIRT
, ASE_VIRT64
,
1754 OPTION_VIRT
, OPTION_NO_VIRT
,
1758 { "msa", ASE_MSA
, ASE_MSA64
,
1759 OPTION_MSA
, OPTION_NO_MSA
,
1763 { "xpa", ASE_XPA
, 0,
1764 OPTION_XPA
, OPTION_NO_XPA
,
1768 { "mips16e2", ASE_MIPS16E2
, 0,
1769 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1774 /* The set of ASEs that require -mfp64. */
1775 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1777 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1778 static const unsigned int mips_ase_groups
[] = {
1779 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1784 The following pseudo-ops from the Kane and Heinrich MIPS book
1785 should be defined here, but are currently unsupported: .alias,
1786 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1788 The following pseudo-ops from the Kane and Heinrich MIPS book are
1789 specific to the type of debugging information being generated, and
1790 should be defined by the object format: .aent, .begin, .bend,
1791 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1794 The following pseudo-ops from the Kane and Heinrich MIPS book are
1795 not MIPS CPU specific, but are also not specific to the object file
1796 format. This file is probably the best place to define them, but
1797 they are not currently supported: .asm0, .endr, .lab, .struct. */
1799 static const pseudo_typeS mips_pseudo_table
[] =
1801 /* MIPS specific pseudo-ops. */
1802 {"option", s_option
, 0},
1803 {"set", s_mipsset
, 0},
1804 {"rdata", s_change_sec
, 'r'},
1805 {"sdata", s_change_sec
, 's'},
1806 {"livereg", s_ignore
, 0},
1807 {"abicalls", s_abicalls
, 0},
1808 {"cpload", s_cpload
, 0},
1809 {"cpsetup", s_cpsetup
, 0},
1810 {"cplocal", s_cplocal
, 0},
1811 {"cprestore", s_cprestore
, 0},
1812 {"cpreturn", s_cpreturn
, 0},
1813 {"dtprelword", s_dtprelword
, 0},
1814 {"dtpreldword", s_dtpreldword
, 0},
1815 {"tprelword", s_tprelword
, 0},
1816 {"tpreldword", s_tpreldword
, 0},
1817 {"gpvalue", s_gpvalue
, 0},
1818 {"gpword", s_gpword
, 0},
1819 {"gpdword", s_gpdword
, 0},
1820 {"ehword", s_ehword
, 0},
1821 {"cpadd", s_cpadd
, 0},
1822 {"insn", s_insn
, 0},
1824 {"module", s_module
, 0},
1826 /* Relatively generic pseudo-ops that happen to be used on MIPS
1828 {"asciiz", stringer
, 8 + 1},
1829 {"bss", s_change_sec
, 'b'},
1831 {"half", s_cons
, 1},
1832 {"dword", s_cons
, 3},
1833 {"weakext", s_mips_weakext
, 0},
1834 {"origin", s_org
, 0},
1835 {"repeat", s_rept
, 0},
1837 /* For MIPS this is non-standard, but we define it for consistency. */
1838 {"sbss", s_change_sec
, 'B'},
1840 /* These pseudo-ops are defined in read.c, but must be overridden
1841 here for one reason or another. */
1842 {"align", s_align
, 0},
1843 {"byte", s_cons
, 0},
1844 {"data", s_change_sec
, 'd'},
1845 {"double", s_float_cons
, 'd'},
1846 {"float", s_float_cons
, 'f'},
1847 {"globl", s_mips_globl
, 0},
1848 {"global", s_mips_globl
, 0},
1849 {"hword", s_cons
, 1},
1851 {"long", s_cons
, 2},
1852 {"octa", s_cons
, 4},
1853 {"quad", s_cons
, 3},
1854 {"section", s_change_section
, 0},
1855 {"short", s_cons
, 1},
1856 {"single", s_float_cons
, 'f'},
1857 {"stabd", s_mips_stab
, 'd'},
1858 {"stabn", s_mips_stab
, 'n'},
1859 {"stabs", s_mips_stab
, 's'},
1860 {"text", s_change_sec
, 't'},
1861 {"word", s_cons
, 2},
1863 { "extern", ecoff_directive_extern
, 0},
1868 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1870 /* These pseudo-ops should be defined by the object file format.
1871 However, a.out doesn't support them, so we have versions here. */
1872 {"aent", s_mips_ent
, 1},
1873 {"bgnb", s_ignore
, 0},
1874 {"end", s_mips_end
, 0},
1875 {"endb", s_ignore
, 0},
1876 {"ent", s_mips_ent
, 0},
1877 {"file", s_mips_file
, 0},
1878 {"fmask", s_mips_mask
, 'F'},
1879 {"frame", s_mips_frame
, 0},
1880 {"loc", s_mips_loc
, 0},
1881 {"mask", s_mips_mask
, 'R'},
1882 {"verstamp", s_ignore
, 0},
1886 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1887 purpose of the `.dc.a' internal pseudo-op. */
1890 mips_address_bytes (void)
1892 file_mips_check_options ();
1893 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1896 extern void pop_insert (const pseudo_typeS
*);
1899 mips_pop_insert (void)
1901 pop_insert (mips_pseudo_table
);
1902 if (! ECOFF_DEBUGGING
)
1903 pop_insert (mips_nonecoff_pseudo_table
);
1906 /* Symbols labelling the current insn. */
1908 struct insn_label_list
1910 struct insn_label_list
*next
;
1914 static struct insn_label_list
*free_insn_labels
;
1915 #define label_list tc_segment_info_data.labels
1917 static void mips_clear_insn_labels (void);
1918 static void mips_mark_labels (void);
1919 static void mips_compressed_mark_labels (void);
1922 mips_clear_insn_labels (void)
1924 struct insn_label_list
**pl
;
1925 segment_info_type
*si
;
1929 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1932 si
= seg_info (now_seg
);
1933 *pl
= si
->label_list
;
1934 si
->label_list
= NULL
;
1938 /* Mark instruction labels in MIPS16/microMIPS mode. */
1941 mips_mark_labels (void)
1943 if (HAVE_CODE_COMPRESSION
)
1944 mips_compressed_mark_labels ();
1947 static char *expr_end
;
1949 /* An expression in a macro instruction. This is set by mips_ip and
1950 mips16_ip and when populated is always an O_constant. */
1952 static expressionS imm_expr
;
1954 /* The relocatable field in an instruction and the relocs associated
1955 with it. These variables are used for instructions like LUI and
1956 JAL as well as true offsets. They are also used for address
1957 operands in macros. */
1959 static expressionS offset_expr
;
1960 static bfd_reloc_code_real_type offset_reloc
[3]
1961 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1963 /* This is set to the resulting size of the instruction to be produced
1964 by mips16_ip if an explicit extension is used or by mips_ip if an
1965 explicit size is supplied. */
1967 static unsigned int forced_insn_length
;
1969 /* True if we are assembling an instruction. All dot symbols defined during
1970 this time should be treated as code labels. */
1972 static bfd_boolean mips_assembling_insn
;
1974 /* The pdr segment for per procedure frame/regmask info. Not used for
1977 static segT pdr_seg
;
1979 /* The default target format to use. */
1981 #if defined (TE_FreeBSD)
1982 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1983 #elif defined (TE_TMIPS)
1984 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1986 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1990 mips_target_format (void)
1992 switch (OUTPUT_FLAVOR
)
1994 case bfd_target_elf_flavour
:
1996 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1997 return (target_big_endian
1998 ? "elf32-bigmips-vxworks"
1999 : "elf32-littlemips-vxworks");
2001 return (target_big_endian
2002 ? (HAVE_64BIT_OBJECTS
2003 ? ELF_TARGET ("elf64-", "big")
2005 ? ELF_TARGET ("elf32-n", "big")
2006 : ELF_TARGET ("elf32-", "big")))
2007 : (HAVE_64BIT_OBJECTS
2008 ? ELF_TARGET ("elf64-", "little")
2010 ? ELF_TARGET ("elf32-n", "little")
2011 : ELF_TARGET ("elf32-", "little"))));
2018 /* Return the ISA revision that is currently in use, or 0 if we are
2019 generating code for MIPS V or below. */
2024 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2027 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2030 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2033 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2036 /* microMIPS implies revision 2 or above. */
2037 if (mips_opts
.micromips
)
2040 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2046 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2049 mips_ase_mask (unsigned int flags
)
2053 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2054 if (flags
& mips_ase_groups
[i
])
2055 flags
|= mips_ase_groups
[i
];
2059 /* Check whether the current ISA supports ASE. Issue a warning if
2063 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2067 static unsigned int warned_isa
;
2068 static unsigned int warned_fp32
;
2070 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2071 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2073 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2074 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2075 && (warned_isa
& ase
->flags
) != ase
->flags
)
2077 warned_isa
|= ase
->flags
;
2078 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2079 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2081 as_warn (_("the %d-bit %s architecture does not support the"
2082 " `%s' extension"), size
, base
, ase
->name
);
2084 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2085 ase
->name
, base
, size
, min_rev
);
2087 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2088 && (warned_isa
& ase
->flags
) != ase
->flags
)
2090 warned_isa
|= ase
->flags
;
2091 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2092 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2093 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2094 ase
->name
, base
, size
, ase
->rem_rev
);
2097 if ((ase
->flags
& FP64_ASES
)
2098 && mips_opts
.fp
!= 64
2099 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2101 warned_fp32
|= ase
->flags
;
2102 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2106 /* Check all enabled ASEs to see whether they are supported by the
2107 chosen architecture. */
2110 mips_check_isa_supports_ases (void)
2112 unsigned int i
, mask
;
2114 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2116 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2117 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2118 mips_check_isa_supports_ase (&mips_ases
[i
]);
2122 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2123 that were affected. */
2126 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2127 bfd_boolean enabled_p
)
2131 mask
= mips_ase_mask (ase
->flags
);
2134 opts
->ase
|= ase
->flags
;
2136 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2138 opts
->ase
|= ASE_MIPS16E2_MT
;
2139 mask
|= ASE_MIPS16E2_MT
;
2145 /* Return the ASE called NAME, or null if none. */
2147 static const struct mips_ase
*
2148 mips_lookup_ase (const char *name
)
2152 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2153 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2154 return &mips_ases
[i
];
2158 /* Return the length of a microMIPS instruction in bytes. If bits of
2159 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2160 otherwise it is a 32-bit instruction. */
2162 static inline unsigned int
2163 micromips_insn_length (const struct mips_opcode
*mo
)
2165 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2168 /* Return the length of MIPS16 instruction OPCODE. */
2170 static inline unsigned int
2171 mips16_opcode_length (unsigned long opcode
)
2173 return (opcode
>> 16) == 0 ? 2 : 4;
2176 /* Return the length of instruction INSN. */
2178 static inline unsigned int
2179 insn_length (const struct mips_cl_insn
*insn
)
2181 if (mips_opts
.micromips
)
2182 return micromips_insn_length (insn
->insn_mo
);
2183 else if (mips_opts
.mips16
)
2184 return mips16_opcode_length (insn
->insn_opcode
);
2189 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2192 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2197 insn
->insn_opcode
= mo
->match
;
2200 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2201 insn
->fixp
[i
] = NULL
;
2202 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2203 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2204 insn
->mips16_absolute_jump_p
= 0;
2205 insn
->complete_p
= 0;
2206 insn
->cleared_p
= 0;
2209 /* Get a list of all the operands in INSN. */
2211 static const struct mips_operand_array
*
2212 insn_operands (const struct mips_cl_insn
*insn
)
2214 if (insn
->insn_mo
>= &mips_opcodes
[0]
2215 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2216 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2218 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2219 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2220 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2222 if (insn
->insn_mo
>= µmips_opcodes
[0]
2223 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2224 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2229 /* Get a description of operand OPNO of INSN. */
2231 static const struct mips_operand
*
2232 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2234 const struct mips_operand_array
*operands
;
2236 operands
= insn_operands (insn
);
2237 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2239 return operands
->operand
[opno
];
2242 /* Install UVAL as the value of OPERAND in INSN. */
2245 insn_insert_operand (struct mips_cl_insn
*insn
,
2246 const struct mips_operand
*operand
, unsigned int uval
)
2248 if (mips_opts
.mips16
2249 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2250 && mips_opcode_32bit_p (insn
->insn_mo
))
2251 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2253 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2256 /* Extract the value of OPERAND from INSN. */
2258 static inline unsigned
2259 insn_extract_operand (const struct mips_cl_insn
*insn
,
2260 const struct mips_operand
*operand
)
2262 return mips_extract_operand (operand
, insn
->insn_opcode
);
2265 /* Record the current MIPS16/microMIPS mode in now_seg. */
2268 mips_record_compressed_mode (void)
2270 segment_info_type
*si
;
2272 si
= seg_info (now_seg
);
2273 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2274 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2275 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2276 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2279 /* Read a standard MIPS instruction from BUF. */
2281 static unsigned long
2282 read_insn (char *buf
)
2284 if (target_big_endian
)
2285 return bfd_getb32 ((bfd_byte
*) buf
);
2287 return bfd_getl32 ((bfd_byte
*) buf
);
2290 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2294 write_insn (char *buf
, unsigned int insn
)
2296 md_number_to_chars (buf
, insn
, 4);
2300 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2301 has length LENGTH. */
2303 static unsigned long
2304 read_compressed_insn (char *buf
, unsigned int length
)
2310 for (i
= 0; i
< length
; i
+= 2)
2313 if (target_big_endian
)
2314 insn
|= bfd_getb16 ((char *) buf
);
2316 insn
|= bfd_getl16 ((char *) buf
);
2322 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2323 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2326 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2330 for (i
= 0; i
< length
; i
+= 2)
2331 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2332 return buf
+ length
;
2335 /* Install INSN at the location specified by its "frag" and "where" fields. */
2338 install_insn (const struct mips_cl_insn
*insn
)
2340 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2341 if (HAVE_CODE_COMPRESSION
)
2342 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2344 write_insn (f
, insn
->insn_opcode
);
2345 mips_record_compressed_mode ();
2348 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2349 and install the opcode in the new location. */
2352 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2357 insn
->where
= where
;
2358 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2359 if (insn
->fixp
[i
] != NULL
)
2361 insn
->fixp
[i
]->fx_frag
= frag
;
2362 insn
->fixp
[i
]->fx_where
= where
;
2364 install_insn (insn
);
2367 /* Add INSN to the end of the output. */
2370 add_fixed_insn (struct mips_cl_insn
*insn
)
2372 char *f
= frag_more (insn_length (insn
));
2373 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2376 /* Start a variant frag and move INSN to the start of the variant part,
2377 marking it as fixed. The other arguments are as for frag_var. */
2380 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2381 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2383 frag_grow (max_chars
);
2384 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2386 frag_var (rs_machine_dependent
, max_chars
, var
,
2387 subtype
, symbol
, offset
, NULL
);
2390 /* Insert N copies of INSN into the history buffer, starting at
2391 position FIRST. Neither FIRST nor N need to be clipped. */
2394 insert_into_history (unsigned int first
, unsigned int n
,
2395 const struct mips_cl_insn
*insn
)
2397 if (mips_relax
.sequence
!= 2)
2401 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2403 history
[i
] = history
[i
- n
];
2409 /* Clear the error in insn_error. */
2412 clear_insn_error (void)
2414 memset (&insn_error
, 0, sizeof (insn_error
));
2417 /* Possibly record error message MSG for the current instruction.
2418 If the error is about a particular argument, ARGNUM is the 1-based
2419 number of that argument, otherwise it is 0. FORMAT is the format
2420 of MSG. Return true if MSG was used, false if the current message
2424 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2429 /* Give priority to errors against specific arguments, and to
2430 the first whole-instruction message. */
2436 /* Keep insn_error if it is against a later argument. */
2437 if (argnum
< insn_error
.min_argnum
)
2440 /* If both errors are against the same argument but are different,
2441 give up on reporting a specific error for this argument.
2442 See the comment about mips_insn_error for details. */
2443 if (argnum
== insn_error
.min_argnum
2445 && strcmp (insn_error
.msg
, msg
) != 0)
2448 insn_error
.min_argnum
+= 1;
2452 insn_error
.min_argnum
= argnum
;
2453 insn_error
.format
= format
;
2454 insn_error
.msg
= msg
;
2458 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2459 as for set_insn_error_format. */
2462 set_insn_error (int argnum
, const char *msg
)
2464 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2467 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2468 as for set_insn_error_format. */
2471 set_insn_error_i (int argnum
, const char *msg
, int i
)
2473 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2477 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2478 are as for set_insn_error_format. */
2481 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2483 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2485 insn_error
.u
.ss
[0] = s1
;
2486 insn_error
.u
.ss
[1] = s2
;
2490 /* Report the error in insn_error, which is against assembly code STR. */
2493 report_insn_error (const char *str
)
2495 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2497 switch (insn_error
.format
)
2504 as_bad (msg
, insn_error
.u
.i
, str
);
2508 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2512 free ((char *) msg
);
2515 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2516 the idea is to make it obvious at a glance that each errata is
2520 init_vr4120_conflicts (void)
2522 #define CONFLICT(FIRST, SECOND) \
2523 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2525 /* Errata 21 - [D]DIV[U] after [D]MACC */
2526 CONFLICT (MACC
, DIV
);
2527 CONFLICT (DMACC
, DIV
);
2529 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2530 CONFLICT (DMULT
, DMULT
);
2531 CONFLICT (DMULT
, DMACC
);
2532 CONFLICT (DMACC
, DMULT
);
2533 CONFLICT (DMACC
, DMACC
);
2535 /* Errata 24 - MT{LO,HI} after [D]MACC */
2536 CONFLICT (MACC
, MTHILO
);
2537 CONFLICT (DMACC
, MTHILO
);
2539 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2540 instruction is executed immediately after a MACC or DMACC
2541 instruction, the result of [either instruction] is incorrect." */
2542 CONFLICT (MACC
, MULT
);
2543 CONFLICT (MACC
, DMULT
);
2544 CONFLICT (DMACC
, MULT
);
2545 CONFLICT (DMACC
, DMULT
);
2547 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2548 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2549 DDIV or DDIVU instruction, the result of the MACC or
2550 DMACC instruction is incorrect.". */
2551 CONFLICT (DMULT
, MACC
);
2552 CONFLICT (DMULT
, DMACC
);
2553 CONFLICT (DIV
, MACC
);
2554 CONFLICT (DIV
, DMACC
);
2564 #define RNUM_MASK 0x00000ff
2565 #define RTYPE_MASK 0x0ffff00
2566 #define RTYPE_NUM 0x0000100
2567 #define RTYPE_FPU 0x0000200
2568 #define RTYPE_FCC 0x0000400
2569 #define RTYPE_VEC 0x0000800
2570 #define RTYPE_GP 0x0001000
2571 #define RTYPE_CP0 0x0002000
2572 #define RTYPE_PC 0x0004000
2573 #define RTYPE_ACC 0x0008000
2574 #define RTYPE_CCC 0x0010000
2575 #define RTYPE_VI 0x0020000
2576 #define RTYPE_VF 0x0040000
2577 #define RTYPE_R5900_I 0x0080000
2578 #define RTYPE_R5900_Q 0x0100000
2579 #define RTYPE_R5900_R 0x0200000
2580 #define RTYPE_R5900_ACC 0x0400000
2581 #define RTYPE_MSA 0x0800000
2582 #define RWARN 0x8000000
2584 #define GENERIC_REGISTER_NUMBERS \
2585 {"$0", RTYPE_NUM | 0}, \
2586 {"$1", RTYPE_NUM | 1}, \
2587 {"$2", RTYPE_NUM | 2}, \
2588 {"$3", RTYPE_NUM | 3}, \
2589 {"$4", RTYPE_NUM | 4}, \
2590 {"$5", RTYPE_NUM | 5}, \
2591 {"$6", RTYPE_NUM | 6}, \
2592 {"$7", RTYPE_NUM | 7}, \
2593 {"$8", RTYPE_NUM | 8}, \
2594 {"$9", RTYPE_NUM | 9}, \
2595 {"$10", RTYPE_NUM | 10}, \
2596 {"$11", RTYPE_NUM | 11}, \
2597 {"$12", RTYPE_NUM | 12}, \
2598 {"$13", RTYPE_NUM | 13}, \
2599 {"$14", RTYPE_NUM | 14}, \
2600 {"$15", RTYPE_NUM | 15}, \
2601 {"$16", RTYPE_NUM | 16}, \
2602 {"$17", RTYPE_NUM | 17}, \
2603 {"$18", RTYPE_NUM | 18}, \
2604 {"$19", RTYPE_NUM | 19}, \
2605 {"$20", RTYPE_NUM | 20}, \
2606 {"$21", RTYPE_NUM | 21}, \
2607 {"$22", RTYPE_NUM | 22}, \
2608 {"$23", RTYPE_NUM | 23}, \
2609 {"$24", RTYPE_NUM | 24}, \
2610 {"$25", RTYPE_NUM | 25}, \
2611 {"$26", RTYPE_NUM | 26}, \
2612 {"$27", RTYPE_NUM | 27}, \
2613 {"$28", RTYPE_NUM | 28}, \
2614 {"$29", RTYPE_NUM | 29}, \
2615 {"$30", RTYPE_NUM | 30}, \
2616 {"$31", RTYPE_NUM | 31}
2618 #define FPU_REGISTER_NAMES \
2619 {"$f0", RTYPE_FPU | 0}, \
2620 {"$f1", RTYPE_FPU | 1}, \
2621 {"$f2", RTYPE_FPU | 2}, \
2622 {"$f3", RTYPE_FPU | 3}, \
2623 {"$f4", RTYPE_FPU | 4}, \
2624 {"$f5", RTYPE_FPU | 5}, \
2625 {"$f6", RTYPE_FPU | 6}, \
2626 {"$f7", RTYPE_FPU | 7}, \
2627 {"$f8", RTYPE_FPU | 8}, \
2628 {"$f9", RTYPE_FPU | 9}, \
2629 {"$f10", RTYPE_FPU | 10}, \
2630 {"$f11", RTYPE_FPU | 11}, \
2631 {"$f12", RTYPE_FPU | 12}, \
2632 {"$f13", RTYPE_FPU | 13}, \
2633 {"$f14", RTYPE_FPU | 14}, \
2634 {"$f15", RTYPE_FPU | 15}, \
2635 {"$f16", RTYPE_FPU | 16}, \
2636 {"$f17", RTYPE_FPU | 17}, \
2637 {"$f18", RTYPE_FPU | 18}, \
2638 {"$f19", RTYPE_FPU | 19}, \
2639 {"$f20", RTYPE_FPU | 20}, \
2640 {"$f21", RTYPE_FPU | 21}, \
2641 {"$f22", RTYPE_FPU | 22}, \
2642 {"$f23", RTYPE_FPU | 23}, \
2643 {"$f24", RTYPE_FPU | 24}, \
2644 {"$f25", RTYPE_FPU | 25}, \
2645 {"$f26", RTYPE_FPU | 26}, \
2646 {"$f27", RTYPE_FPU | 27}, \
2647 {"$f28", RTYPE_FPU | 28}, \
2648 {"$f29", RTYPE_FPU | 29}, \
2649 {"$f30", RTYPE_FPU | 30}, \
2650 {"$f31", RTYPE_FPU | 31}
2652 #define FPU_CONDITION_CODE_NAMES \
2653 {"$fcc0", RTYPE_FCC | 0}, \
2654 {"$fcc1", RTYPE_FCC | 1}, \
2655 {"$fcc2", RTYPE_FCC | 2}, \
2656 {"$fcc3", RTYPE_FCC | 3}, \
2657 {"$fcc4", RTYPE_FCC | 4}, \
2658 {"$fcc5", RTYPE_FCC | 5}, \
2659 {"$fcc6", RTYPE_FCC | 6}, \
2660 {"$fcc7", RTYPE_FCC | 7}
2662 #define COPROC_CONDITION_CODE_NAMES \
2663 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2664 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2665 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2666 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2667 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2668 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2669 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2670 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2672 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2673 {"$a4", RTYPE_GP | 8}, \
2674 {"$a5", RTYPE_GP | 9}, \
2675 {"$a6", RTYPE_GP | 10}, \
2676 {"$a7", RTYPE_GP | 11}, \
2677 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2678 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2679 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2680 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2681 {"$t0", RTYPE_GP | 12}, \
2682 {"$t1", RTYPE_GP | 13}, \
2683 {"$t2", RTYPE_GP | 14}, \
2684 {"$t3", RTYPE_GP | 15}
2686 #define O32_SYMBOLIC_REGISTER_NAMES \
2687 {"$t0", RTYPE_GP | 8}, \
2688 {"$t1", RTYPE_GP | 9}, \
2689 {"$t2", RTYPE_GP | 10}, \
2690 {"$t3", RTYPE_GP | 11}, \
2691 {"$t4", RTYPE_GP | 12}, \
2692 {"$t5", RTYPE_GP | 13}, \
2693 {"$t6", RTYPE_GP | 14}, \
2694 {"$t7", RTYPE_GP | 15}, \
2695 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2696 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2697 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2698 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2700 /* Remaining symbolic register names */
2701 #define SYMBOLIC_REGISTER_NAMES \
2702 {"$zero", RTYPE_GP | 0}, \
2703 {"$at", RTYPE_GP | 1}, \
2704 {"$AT", RTYPE_GP | 1}, \
2705 {"$v0", RTYPE_GP | 2}, \
2706 {"$v1", RTYPE_GP | 3}, \
2707 {"$a0", RTYPE_GP | 4}, \
2708 {"$a1", RTYPE_GP | 5}, \
2709 {"$a2", RTYPE_GP | 6}, \
2710 {"$a3", RTYPE_GP | 7}, \
2711 {"$s0", RTYPE_GP | 16}, \
2712 {"$s1", RTYPE_GP | 17}, \
2713 {"$s2", RTYPE_GP | 18}, \
2714 {"$s3", RTYPE_GP | 19}, \
2715 {"$s4", RTYPE_GP | 20}, \
2716 {"$s5", RTYPE_GP | 21}, \
2717 {"$s6", RTYPE_GP | 22}, \
2718 {"$s7", RTYPE_GP | 23}, \
2719 {"$t8", RTYPE_GP | 24}, \
2720 {"$t9", RTYPE_GP | 25}, \
2721 {"$k0", RTYPE_GP | 26}, \
2722 {"$kt0", RTYPE_GP | 26}, \
2723 {"$k1", RTYPE_GP | 27}, \
2724 {"$kt1", RTYPE_GP | 27}, \
2725 {"$gp", RTYPE_GP | 28}, \
2726 {"$sp", RTYPE_GP | 29}, \
2727 {"$s8", RTYPE_GP | 30}, \
2728 {"$fp", RTYPE_GP | 30}, \
2729 {"$ra", RTYPE_GP | 31}
2731 #define MIPS16_SPECIAL_REGISTER_NAMES \
2732 {"$pc", RTYPE_PC | 0}
2734 #define MDMX_VECTOR_REGISTER_NAMES \
2735 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2736 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2737 {"$v2", RTYPE_VEC | 2}, \
2738 {"$v3", RTYPE_VEC | 3}, \
2739 {"$v4", RTYPE_VEC | 4}, \
2740 {"$v5", RTYPE_VEC | 5}, \
2741 {"$v6", RTYPE_VEC | 6}, \
2742 {"$v7", RTYPE_VEC | 7}, \
2743 {"$v8", RTYPE_VEC | 8}, \
2744 {"$v9", RTYPE_VEC | 9}, \
2745 {"$v10", RTYPE_VEC | 10}, \
2746 {"$v11", RTYPE_VEC | 11}, \
2747 {"$v12", RTYPE_VEC | 12}, \
2748 {"$v13", RTYPE_VEC | 13}, \
2749 {"$v14", RTYPE_VEC | 14}, \
2750 {"$v15", RTYPE_VEC | 15}, \
2751 {"$v16", RTYPE_VEC | 16}, \
2752 {"$v17", RTYPE_VEC | 17}, \
2753 {"$v18", RTYPE_VEC | 18}, \
2754 {"$v19", RTYPE_VEC | 19}, \
2755 {"$v20", RTYPE_VEC | 20}, \
2756 {"$v21", RTYPE_VEC | 21}, \
2757 {"$v22", RTYPE_VEC | 22}, \
2758 {"$v23", RTYPE_VEC | 23}, \
2759 {"$v24", RTYPE_VEC | 24}, \
2760 {"$v25", RTYPE_VEC | 25}, \
2761 {"$v26", RTYPE_VEC | 26}, \
2762 {"$v27", RTYPE_VEC | 27}, \
2763 {"$v28", RTYPE_VEC | 28}, \
2764 {"$v29", RTYPE_VEC | 29}, \
2765 {"$v30", RTYPE_VEC | 30}, \
2766 {"$v31", RTYPE_VEC | 31}
2768 #define R5900_I_NAMES \
2769 {"$I", RTYPE_R5900_I | 0}
2771 #define R5900_Q_NAMES \
2772 {"$Q", RTYPE_R5900_Q | 0}
2774 #define R5900_R_NAMES \
2775 {"$R", RTYPE_R5900_R | 0}
2777 #define R5900_ACC_NAMES \
2778 {"$ACC", RTYPE_R5900_ACC | 0 }
2780 #define MIPS_DSP_ACCUMULATOR_NAMES \
2781 {"$ac0", RTYPE_ACC | 0}, \
2782 {"$ac1", RTYPE_ACC | 1}, \
2783 {"$ac2", RTYPE_ACC | 2}, \
2784 {"$ac3", RTYPE_ACC | 3}
2786 static const struct regname reg_names
[] = {
2787 GENERIC_REGISTER_NUMBERS
,
2789 FPU_CONDITION_CODE_NAMES
,
2790 COPROC_CONDITION_CODE_NAMES
,
2792 /* The $txx registers depends on the abi,
2793 these will be added later into the symbol table from
2794 one of the tables below once mips_abi is set after
2795 parsing of arguments from the command line. */
2796 SYMBOLIC_REGISTER_NAMES
,
2798 MIPS16_SPECIAL_REGISTER_NAMES
,
2799 MDMX_VECTOR_REGISTER_NAMES
,
2804 MIPS_DSP_ACCUMULATOR_NAMES
,
2808 static const struct regname reg_names_o32
[] = {
2809 O32_SYMBOLIC_REGISTER_NAMES
,
2813 static const struct regname reg_names_n32n64
[] = {
2814 N32N64_SYMBOLIC_REGISTER_NAMES
,
2818 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2819 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2820 of these register symbols, return the associated vector register,
2821 otherwise return SYMVAL itself. */
2824 mips_prefer_vec_regno (unsigned int symval
)
2826 if ((symval
& -2) == (RTYPE_GP
| 2))
2827 return RTYPE_VEC
| (symval
& 1);
2831 /* Return true if string [S, E) is a valid register name, storing its
2832 symbol value in *SYMVAL_PTR if so. */
2835 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2840 /* Terminate name. */
2844 /* Look up the name. */
2845 symbol
= symbol_find (s
);
2848 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2851 *symval_ptr
= S_GET_VALUE (symbol
);
2855 /* Return true if the string at *SPTR is a valid register name. Allow it
2856 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2859 When returning true, move *SPTR past the register, store the
2860 register's symbol value in *SYMVAL_PTR and the channel mask in
2861 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2862 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2863 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2866 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2867 unsigned int *channels_ptr
)
2871 unsigned int channels
, symval
, bit
;
2873 /* Find end of name. */
2875 if (is_name_beginner (*e
))
2877 while (is_part_of_name (*e
))
2881 if (!mips_parse_register_1 (s
, e
, &symval
))
2886 /* Eat characters from the end of the string that are valid
2887 channel suffixes. The preceding register must be $ACC or
2888 end with a digit, so there is no ambiguity. */
2891 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2892 if (m
> s
&& m
[-1] == *q
)
2899 || !mips_parse_register_1 (s
, m
, &symval
)
2900 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2905 *symval_ptr
= symval
;
2907 *channels_ptr
= channels
;
2911 /* Check if SPTR points at a valid register specifier according to TYPES.
2912 If so, then return 1, advance S to consume the specifier and store
2913 the register's number in REGNOP, otherwise return 0. */
2916 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2920 if (mips_parse_register (s
, ®no
, NULL
))
2922 if (types
& RTYPE_VEC
)
2923 regno
= mips_prefer_vec_regno (regno
);
2932 as_warn (_("unrecognized register name `%s'"), *s
);
2937 return regno
<= RNUM_MASK
;
2940 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2941 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2944 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2949 for (i
= 0; i
< 4; i
++)
2950 if (*s
== "xyzw"[i
])
2952 *channels
|= 1 << (3 - i
);
2958 /* Token types for parsed operand lists. */
2959 enum mips_operand_token_type
{
2960 /* A plain register, e.g. $f2. */
2963 /* A 4-bit XYZW channel mask. */
2966 /* A constant vector index, e.g. [1]. */
2969 /* A register vector index, e.g. [$2]. */
2972 /* A continuous range of registers, e.g. $s0-$s4. */
2975 /* A (possibly relocated) expression. */
2978 /* A floating-point value. */
2981 /* A single character. This can be '(', ')' or ',', but '(' only appears
2985 /* A doubled character, either "--" or "++". */
2988 /* The end of the operand list. */
2992 /* A parsed operand token. */
2993 struct mips_operand_token
2995 /* The type of token. */
2996 enum mips_operand_token_type type
;
2999 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3002 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3003 unsigned int channels
;
3005 /* The integer value of an OT_INTEGER_INDEX. */
3008 /* The two register symbol values involved in an OT_REG_RANGE. */
3010 unsigned int regno1
;
3011 unsigned int regno2
;
3014 /* The value of an OT_INTEGER. The value is represented as an
3015 expression and the relocation operators that were applied to
3016 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3017 relocation operators were used. */
3020 bfd_reloc_code_real_type relocs
[3];
3023 /* The binary data for an OT_FLOAT constant, and the number of bytes
3026 unsigned char data
[8];
3030 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3035 /* An obstack used to construct lists of mips_operand_tokens. */
3036 static struct obstack mips_operand_tokens
;
3038 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3041 mips_add_token (struct mips_operand_token
*token
,
3042 enum mips_operand_token_type type
)
3045 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3048 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3049 and OT_REG tokens for them if so, and return a pointer to the first
3050 unconsumed character. Return null otherwise. */
3053 mips_parse_base_start (char *s
)
3055 struct mips_operand_token token
;
3056 unsigned int regno
, channels
;
3057 bfd_boolean decrement_p
;
3063 SKIP_SPACE_TABS (s
);
3065 /* Only match "--" as part of a base expression. In other contexts "--X"
3066 is a double negative. */
3067 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3071 SKIP_SPACE_TABS (s
);
3074 /* Allow a channel specifier because that leads to better error messages
3075 than treating something like "$vf0x++" as an expression. */
3076 if (!mips_parse_register (&s
, ®no
, &channels
))
3080 mips_add_token (&token
, OT_CHAR
);
3085 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3088 token
.u
.regno
= regno
;
3089 mips_add_token (&token
, OT_REG
);
3093 token
.u
.channels
= channels
;
3094 mips_add_token (&token
, OT_CHANNELS
);
3097 /* For consistency, only match "++" as part of base expressions too. */
3098 SKIP_SPACE_TABS (s
);
3099 if (s
[0] == '+' && s
[1] == '+')
3103 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3109 /* Parse one or more tokens from S. Return a pointer to the first
3110 unconsumed character on success. Return null if an error was found
3111 and store the error text in insn_error. FLOAT_FORMAT is as for
3112 mips_parse_arguments. */
3115 mips_parse_argument_token (char *s
, char float_format
)
3117 char *end
, *save_in
;
3119 unsigned int regno1
, regno2
, channels
;
3120 struct mips_operand_token token
;
3122 /* First look for "($reg", since we want to treat that as an
3123 OT_CHAR and OT_REG rather than an expression. */
3124 end
= mips_parse_base_start (s
);
3128 /* Handle other characters that end up as OT_CHARs. */
3129 if (*s
== ')' || *s
== ',')
3132 mips_add_token (&token
, OT_CHAR
);
3137 /* Handle tokens that start with a register. */
3138 if (mips_parse_register (&s
, ®no1
, &channels
))
3142 /* A register and a VU0 channel suffix. */
3143 token
.u
.regno
= regno1
;
3144 mips_add_token (&token
, OT_REG
);
3146 token
.u
.channels
= channels
;
3147 mips_add_token (&token
, OT_CHANNELS
);
3151 SKIP_SPACE_TABS (s
);
3154 /* A register range. */
3156 SKIP_SPACE_TABS (s
);
3157 if (!mips_parse_register (&s
, ®no2
, NULL
))
3159 set_insn_error (0, _("invalid register range"));
3163 token
.u
.reg_range
.regno1
= regno1
;
3164 token
.u
.reg_range
.regno2
= regno2
;
3165 mips_add_token (&token
, OT_REG_RANGE
);
3169 /* Add the register itself. */
3170 token
.u
.regno
= regno1
;
3171 mips_add_token (&token
, OT_REG
);
3173 /* Check for a vector index. */
3177 SKIP_SPACE_TABS (s
);
3178 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3179 mips_add_token (&token
, OT_REG_INDEX
);
3182 expressionS element
;
3184 my_getExpression (&element
, s
);
3185 if (element
.X_op
!= O_constant
)
3187 set_insn_error (0, _("vector element must be constant"));
3191 token
.u
.index
= element
.X_add_number
;
3192 mips_add_token (&token
, OT_INTEGER_INDEX
);
3194 SKIP_SPACE_TABS (s
);
3197 set_insn_error (0, _("missing `]'"));
3207 /* First try to treat expressions as floats. */
3208 save_in
= input_line_pointer
;
3209 input_line_pointer
= s
;
3210 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3211 &token
.u
.flt
.length
);
3212 end
= input_line_pointer
;
3213 input_line_pointer
= save_in
;
3216 set_insn_error (0, err
);
3221 mips_add_token (&token
, OT_FLOAT
);
3226 /* Treat everything else as an integer expression. */
3227 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3228 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3229 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3230 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3232 mips_add_token (&token
, OT_INTEGER
);
3236 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3237 if expressions should be treated as 32-bit floating-point constants,
3238 'd' if they should be treated as 64-bit floating-point constants,
3239 or 0 if they should be treated as integer expressions (the usual case).
3241 Return a list of tokens on success, otherwise return 0. The caller
3242 must obstack_free the list after use. */
3244 static struct mips_operand_token
*
3245 mips_parse_arguments (char *s
, char float_format
)
3247 struct mips_operand_token token
;
3249 SKIP_SPACE_TABS (s
);
3252 s
= mips_parse_argument_token (s
, float_format
);
3255 obstack_free (&mips_operand_tokens
,
3256 obstack_finish (&mips_operand_tokens
));
3259 SKIP_SPACE_TABS (s
);
3261 mips_add_token (&token
, OT_END
);
3262 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3265 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3266 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3269 is_opcode_valid (const struct mips_opcode
*mo
)
3271 int isa
= mips_opts
.isa
;
3272 int ase
= mips_opts
.ase
;
3276 if (ISA_HAS_64BIT_REGS (isa
))
3277 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3278 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3279 ase
|= mips_ases
[i
].flags64
;
3281 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3284 /* Check whether the instruction or macro requires single-precision or
3285 double-precision floating-point support. Note that this information is
3286 stored differently in the opcode table for insns and macros. */
3287 if (mo
->pinfo
== INSN_MACRO
)
3289 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3290 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3294 fp_s
= mo
->pinfo
& FP_S
;
3295 fp_d
= mo
->pinfo
& FP_D
;
3298 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3301 if (fp_s
&& mips_opts
.soft_float
)
3307 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3308 selected ISA and architecture. */
3311 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3313 int isa
= mips_opts
.isa
;
3314 int ase
= mips_opts
.ase
;
3317 if (ISA_HAS_64BIT_REGS (isa
))
3318 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3319 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3320 ase
|= mips_ases
[i
].flags64
;
3322 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3325 /* Return TRUE if the size of the microMIPS opcode MO matches one
3326 explicitly requested. Always TRUE in the standard MIPS mode.
3327 Use is_size_valid_16 for MIPS16 opcodes. */
3330 is_size_valid (const struct mips_opcode
*mo
)
3332 if (!mips_opts
.micromips
)
3335 if (mips_opts
.insn32
)
3337 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3339 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3342 if (!forced_insn_length
)
3344 if (mo
->pinfo
== INSN_MACRO
)
3346 return forced_insn_length
== micromips_insn_length (mo
);
3349 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3350 explicitly requested. */
3353 is_size_valid_16 (const struct mips_opcode
*mo
)
3355 if (!forced_insn_length
)
3357 if (mo
->pinfo
== INSN_MACRO
)
3359 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3361 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3366 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3367 of the preceding instruction. Always TRUE in the standard MIPS mode.
3369 We don't accept macros in 16-bit delay slots to avoid a case where
3370 a macro expansion fails because it relies on a preceding 32-bit real
3371 instruction to have matched and does not handle the operands correctly.
3372 The only macros that may expand to 16-bit instructions are JAL that
3373 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3374 and BGT (that likewise cannot be placed in a delay slot) that decay to
3375 a NOP. In all these cases the macros precede any corresponding real
3376 instruction definitions in the opcode table, so they will match in the
3377 second pass where the size of the delay slot is ignored and therefore
3378 produce correct code. */
3381 is_delay_slot_valid (const struct mips_opcode
*mo
)
3383 if (!mips_opts
.micromips
)
3386 if (mo
->pinfo
== INSN_MACRO
)
3387 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3388 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3389 && micromips_insn_length (mo
) != 4)
3391 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3392 && micromips_insn_length (mo
) != 2)
3398 /* For consistency checking, verify that all bits of OPCODE are specified
3399 either by the match/mask part of the instruction definition, or by the
3400 operand list. Also build up a list of operands in OPERANDS.
3402 INSN_BITS says which bits of the instruction are significant.
3403 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3404 provides the mips_operand description of each operand. DECODE_OPERAND
3405 is null for MIPS16 instructions. */
3408 validate_mips_insn (const struct mips_opcode
*opcode
,
3409 unsigned long insn_bits
,
3410 const struct mips_operand
*(*decode_operand
) (const char *),
3411 struct mips_operand_array
*operands
)
3414 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3415 const struct mips_operand
*operand
;
3417 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3418 if ((mask
& opcode
->match
) != opcode
->match
)
3420 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3421 opcode
->name
, opcode
->args
);
3426 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3427 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3428 for (s
= opcode
->args
; *s
; ++s
)
3441 if (!decode_operand
)
3442 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3444 operand
= decode_operand (s
);
3445 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3447 as_bad (_("internal: unknown operand type: %s %s"),
3448 opcode
->name
, opcode
->args
);
3451 gas_assert (opno
< MAX_OPERANDS
);
3452 operands
->operand
[opno
] = operand
;
3453 if (!decode_operand
&& operand
3454 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3455 && mips_opcode_32bit_p (opcode
))
3456 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3457 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3459 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3460 if (operand
->type
== OP_MDMX_IMM_REG
)
3461 /* Bit 5 is the format selector (OB vs QH). The opcode table
3462 has separate entries for each format. */
3463 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3464 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3465 used_bits
&= ~(mask
& 0x700);
3466 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3467 operand field that cannot be fully described with LSB/SIZE. */
3468 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3469 used_bits
&= ~0x6000;
3471 /* Skip prefix characters. */
3472 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3477 doubled
= used_bits
& mask
& insn_bits
;
3480 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3481 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3485 undefined
= ~used_bits
& insn_bits
;
3486 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3488 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3489 undefined
, opcode
->name
, opcode
->args
);
3492 used_bits
&= ~insn_bits
;
3495 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3496 used_bits
, opcode
->name
, opcode
->args
);
3502 /* The MIPS16 version of validate_mips_insn. */
3505 validate_mips16_insn (const struct mips_opcode
*opcode
,
3506 struct mips_operand_array
*operands
)
3508 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3510 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3513 /* The microMIPS version of validate_mips_insn. */
3516 validate_micromips_insn (const struct mips_opcode
*opc
,
3517 struct mips_operand_array
*operands
)
3519 unsigned long insn_bits
;
3520 unsigned long major
;
3521 unsigned int length
;
3523 if (opc
->pinfo
== INSN_MACRO
)
3524 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3527 length
= micromips_insn_length (opc
);
3528 if (length
!= 2 && length
!= 4)
3530 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3531 "%s %s"), length
, opc
->name
, opc
->args
);
3534 major
= opc
->match
>> (10 + 8 * (length
- 2));
3535 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3536 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3538 as_bad (_("internal error: bad microMIPS opcode "
3539 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3543 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3544 insn_bits
= 1 << 4 * length
;
3545 insn_bits
<<= 4 * length
;
3547 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3551 /* This function is called once, at assembler startup time. It should set up
3552 all the tables, etc. that the MD part of the assembler will need. */
3557 const char *retval
= NULL
;
3561 if (mips_pic
!= NO_PIC
)
3563 if (g_switch_seen
&& g_switch_value
!= 0)
3564 as_bad (_("-G may not be used in position-independent code"));
3567 else if (mips_abicalls
)
3569 if (g_switch_seen
&& g_switch_value
!= 0)
3570 as_bad (_("-G may not be used with abicalls"));
3574 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3575 as_warn (_("could not set architecture and machine"));
3577 op_hash
= hash_new ();
3579 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3580 for (i
= 0; i
< NUMOPCODES
;)
3582 const char *name
= mips_opcodes
[i
].name
;
3584 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3587 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3588 mips_opcodes
[i
].name
, retval
);
3589 /* Probably a memory allocation problem? Give up now. */
3590 as_fatal (_("broken assembler, no assembly attempted"));
3594 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3595 decode_mips_operand
, &mips_operands
[i
]))
3597 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3599 create_insn (&nop_insn
, mips_opcodes
+ i
);
3600 if (mips_fix_loongson2f_nop
)
3601 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3602 nop_insn
.fixed_p
= 1;
3606 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3609 mips16_op_hash
= hash_new ();
3610 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3611 bfd_mips16_num_opcodes
);
3614 while (i
< bfd_mips16_num_opcodes
)
3616 const char *name
= mips16_opcodes
[i
].name
;
3618 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3620 as_fatal (_("internal: can't hash `%s': %s"),
3621 mips16_opcodes
[i
].name
, retval
);
3624 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3626 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3628 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3629 mips16_nop_insn
.fixed_p
= 1;
3633 while (i
< bfd_mips16_num_opcodes
3634 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3637 micromips_op_hash
= hash_new ();
3638 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3639 bfd_micromips_num_opcodes
);
3642 while (i
< bfd_micromips_num_opcodes
)
3644 const char *name
= micromips_opcodes
[i
].name
;
3646 retval
= hash_insert (micromips_op_hash
, name
,
3647 (void *) µmips_opcodes
[i
]);
3649 as_fatal (_("internal: can't hash `%s': %s"),
3650 micromips_opcodes
[i
].name
, retval
);
3653 struct mips_cl_insn
*micromips_nop_insn
;
3655 if (!validate_micromips_insn (µmips_opcodes
[i
],
3656 µmips_operands
[i
]))
3659 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3661 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3662 micromips_nop_insn
= µmips_nop16_insn
;
3663 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3664 micromips_nop_insn
= µmips_nop32_insn
;
3668 if (micromips_nop_insn
->insn_mo
== NULL
3669 && strcmp (name
, "nop") == 0)
3671 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3672 micromips_nop_insn
->fixed_p
= 1;
3676 while (++i
< bfd_micromips_num_opcodes
3677 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3681 as_fatal (_("broken assembler, no assembly attempted"));
3683 /* We add all the general register names to the symbol table. This
3684 helps us detect invalid uses of them. */
3685 for (i
= 0; reg_names
[i
].name
; i
++)
3686 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3687 reg_names
[i
].num
, /* & RNUM_MASK, */
3688 &zero_address_frag
));
3690 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3691 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3692 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3693 &zero_address_frag
));
3695 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3696 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3697 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3698 &zero_address_frag
));
3700 for (i
= 0; i
< 32; i
++)
3704 /* R5900 VU0 floating-point register. */
3705 sprintf (regname
, "$vf%d", i
);
3706 symbol_table_insert (symbol_new (regname
, reg_section
,
3707 RTYPE_VF
| i
, &zero_address_frag
));
3709 /* R5900 VU0 integer register. */
3710 sprintf (regname
, "$vi%d", i
);
3711 symbol_table_insert (symbol_new (regname
, reg_section
,
3712 RTYPE_VI
| i
, &zero_address_frag
));
3715 sprintf (regname
, "$w%d", i
);
3716 symbol_table_insert (symbol_new (regname
, reg_section
,
3717 RTYPE_MSA
| i
, &zero_address_frag
));
3720 obstack_init (&mips_operand_tokens
);
3722 mips_no_prev_insn ();
3725 mips_cprmask
[0] = 0;
3726 mips_cprmask
[1] = 0;
3727 mips_cprmask
[2] = 0;
3728 mips_cprmask
[3] = 0;
3730 /* set the default alignment for the text section (2**2) */
3731 record_alignment (text_section
, 2);
3733 bfd_set_gp_size (stdoutput
, g_switch_value
);
3735 /* On a native system other than VxWorks, sections must be aligned
3736 to 16 byte boundaries. When configured for an embedded ELF
3737 target, we don't bother. */
3738 if (strncmp (TARGET_OS
, "elf", 3) != 0
3739 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3741 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3742 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3743 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3746 /* Create a .reginfo section for register masks and a .mdebug
3747 section for debugging information. */
3755 subseg
= now_subseg
;
3757 /* The ABI says this section should be loaded so that the
3758 running program can access it. However, we don't load it
3759 if we are configured for an embedded target */
3760 flags
= SEC_READONLY
| SEC_DATA
;
3761 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3762 flags
|= SEC_ALLOC
| SEC_LOAD
;
3764 if (mips_abi
!= N64_ABI
)
3766 sec
= subseg_new (".reginfo", (subsegT
) 0);
3768 bfd_set_section_flags (stdoutput
, sec
, flags
);
3769 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3771 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3775 /* The 64-bit ABI uses a .MIPS.options section rather than
3776 .reginfo section. */
3777 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3778 bfd_set_section_flags (stdoutput
, sec
, flags
);
3779 bfd_set_section_alignment (stdoutput
, sec
, 3);
3781 /* Set up the option header. */
3783 Elf_Internal_Options opthdr
;
3786 opthdr
.kind
= ODK_REGINFO
;
3787 opthdr
.size
= (sizeof (Elf_External_Options
)
3788 + sizeof (Elf64_External_RegInfo
));
3791 f
= frag_more (sizeof (Elf_External_Options
));
3792 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3793 (Elf_External_Options
*) f
);
3795 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3799 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3800 bfd_set_section_flags (stdoutput
, sec
,
3801 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3802 bfd_set_section_alignment (stdoutput
, sec
, 3);
3803 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3805 if (ECOFF_DEBUGGING
)
3807 sec
= subseg_new (".mdebug", (subsegT
) 0);
3808 (void) bfd_set_section_flags (stdoutput
, sec
,
3809 SEC_HAS_CONTENTS
| SEC_READONLY
);
3810 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3812 else if (mips_flag_pdr
)
3814 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3815 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3816 SEC_READONLY
| SEC_RELOC
3818 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3821 subseg_set (seg
, subseg
);
3824 if (mips_fix_vr4120
)
3825 init_vr4120_conflicts ();
3829 fpabi_incompatible_with (int fpabi
, const char *what
)
3831 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3832 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3836 fpabi_requires (int fpabi
, const char *what
)
3838 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3839 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3842 /* Check -mabi and register sizes against the specified FP ABI. */
3844 check_fpabi (int fpabi
)
3848 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3849 if (file_mips_opts
.soft_float
)
3850 fpabi_incompatible_with (fpabi
, "softfloat");
3851 else if (file_mips_opts
.single_float
)
3852 fpabi_incompatible_with (fpabi
, "singlefloat");
3853 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3854 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3855 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3856 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3859 case Val_GNU_MIPS_ABI_FP_XX
:
3860 if (mips_abi
!= O32_ABI
)
3861 fpabi_requires (fpabi
, "-mabi=32");
3862 else if (file_mips_opts
.soft_float
)
3863 fpabi_incompatible_with (fpabi
, "softfloat");
3864 else if (file_mips_opts
.single_float
)
3865 fpabi_incompatible_with (fpabi
, "singlefloat");
3866 else if (file_mips_opts
.fp
!= 0)
3867 fpabi_requires (fpabi
, "fp=xx");
3870 case Val_GNU_MIPS_ABI_FP_64A
:
3871 case Val_GNU_MIPS_ABI_FP_64
:
3872 if (mips_abi
!= O32_ABI
)
3873 fpabi_requires (fpabi
, "-mabi=32");
3874 else if (file_mips_opts
.soft_float
)
3875 fpabi_incompatible_with (fpabi
, "softfloat");
3876 else if (file_mips_opts
.single_float
)
3877 fpabi_incompatible_with (fpabi
, "singlefloat");
3878 else if (file_mips_opts
.fp
!= 64)
3879 fpabi_requires (fpabi
, "fp=64");
3880 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3881 fpabi_incompatible_with (fpabi
, "nooddspreg");
3882 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3883 fpabi_requires (fpabi
, "nooddspreg");
3886 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3887 if (file_mips_opts
.soft_float
)
3888 fpabi_incompatible_with (fpabi
, "softfloat");
3889 else if (!file_mips_opts
.single_float
)
3890 fpabi_requires (fpabi
, "singlefloat");
3893 case Val_GNU_MIPS_ABI_FP_SOFT
:
3894 if (!file_mips_opts
.soft_float
)
3895 fpabi_requires (fpabi
, "softfloat");
3898 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3899 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3900 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3903 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3904 /* Silently ignore compatibility value. */
3908 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3909 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3914 /* Perform consistency checks on the current options. */
3917 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3919 /* Check the size of integer registers agrees with the ABI and ISA. */
3920 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3921 as_bad (_("`gp=64' used with a 32-bit processor"));
3923 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3924 as_bad (_("`gp=32' used with a 64-bit ABI"));
3926 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3927 as_bad (_("`gp=64' used with a 32-bit ABI"));
3929 /* Check the size of the float registers agrees with the ABI and ISA. */
3933 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3934 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3935 else if (opts
->single_float
== 1)
3936 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3939 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3940 as_bad (_("`fp=64' used with a 32-bit fpu"));
3942 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3943 && !ISA_HAS_MXHC1 (opts
->isa
))
3944 as_warn (_("`fp=64' used with a 32-bit ABI"));
3948 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3949 as_warn (_("`fp=32' used with a 64-bit ABI"));
3950 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3951 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3954 as_bad (_("Unknown size of floating point registers"));
3958 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3959 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3961 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3962 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3963 else if (ISA_IS_R6 (opts
->isa
)
3964 && (opts
->micromips
== 1
3965 || opts
->mips16
== 1))
3966 as_fatal (_("`%s' cannot be used with `%s'"),
3967 opts
->micromips
? "micromips" : "mips16",
3968 mips_cpu_info_from_isa (opts
->isa
)->name
);
3970 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3971 as_fatal (_("branch relaxation is not supported in `%s'"),
3972 mips_cpu_info_from_isa (opts
->isa
)->name
);
3975 /* Perform consistency checks on the module level options exactly once.
3976 This is a deferred check that happens:
3977 at the first .set directive
3978 or, at the first pseudo op that generates code (inc .dc.a)
3979 or, at the first instruction
3983 file_mips_check_options (void)
3985 const struct mips_cpu_info
*arch_info
= 0;
3987 if (file_mips_opts_checked
)
3990 /* The following code determines the register size.
3991 Similar code was added to GCC 3.3 (see override_options() in
3992 config/mips/mips.c). The GAS and GCC code should be kept in sync
3993 as much as possible. */
3995 if (file_mips_opts
.gp
< 0)
3997 /* Infer the integer register size from the ABI and processor.
3998 Restrict ourselves to 32-bit registers if that's all the
3999 processor has, or if the ABI cannot handle 64-bit registers. */
4000 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4001 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4005 if (file_mips_opts
.fp
< 0)
4007 /* No user specified float register size.
4008 ??? GAS treats single-float processors as though they had 64-bit
4009 float registers (although it complains when double-precision
4010 instructions are used). As things stand, saying they have 32-bit
4011 registers would lead to spurious "register must be even" messages.
4012 So here we assume float registers are never smaller than the
4014 if (file_mips_opts
.gp
== 64)
4015 /* 64-bit integer registers implies 64-bit float registers. */
4016 file_mips_opts
.fp
= 64;
4017 else if ((file_mips_opts
.ase
& FP64_ASES
)
4018 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4019 /* Handle ASEs that require 64-bit float registers, if possible. */
4020 file_mips_opts
.fp
= 64;
4021 else if (ISA_IS_R6 (mips_opts
.isa
))
4022 /* R6 implies 64-bit float registers. */
4023 file_mips_opts
.fp
= 64;
4025 /* 32-bit float registers. */
4026 file_mips_opts
.fp
= 32;
4029 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
4031 /* Disable operations on odd-numbered floating-point registers by default
4032 when using the FPXX ABI. */
4033 if (file_mips_opts
.oddspreg
< 0)
4035 if (file_mips_opts
.fp
== 0)
4036 file_mips_opts
.oddspreg
= 0;
4038 file_mips_opts
.oddspreg
= 1;
4041 /* End of GCC-shared inference code. */
4043 /* This flag is set when we have a 64-bit capable CPU but use only
4044 32-bit wide registers. Note that EABI does not use it. */
4045 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4046 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4047 || mips_abi
== O32_ABI
))
4050 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4051 as_bad (_("trap exception not supported at ISA 1"));
4053 /* If the selected architecture includes support for ASEs, enable
4054 generation of code for them. */
4055 if (file_mips_opts
.mips16
== -1)
4056 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4057 if (file_mips_opts
.micromips
== -1)
4058 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4061 if (mips_nan2008
== -1)
4062 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4063 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4064 as_fatal (_("`%s' does not support legacy NaN"),
4065 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4067 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4068 being selected implicitly. */
4069 if (file_mips_opts
.fp
!= 64)
4070 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4072 /* If the user didn't explicitly select or deselect a particular ASE,
4073 use the default setting for the CPU. */
4074 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4076 /* Set up the current options. These may change throughout assembly. */
4077 mips_opts
= file_mips_opts
;
4079 mips_check_isa_supports_ases ();
4080 mips_check_options (&file_mips_opts
, TRUE
);
4081 file_mips_opts_checked
= TRUE
;
4083 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4084 as_warn (_("could not set architecture and machine"));
4088 md_assemble (char *str
)
4090 struct mips_cl_insn insn
;
4091 bfd_reloc_code_real_type unused_reloc
[3]
4092 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4094 file_mips_check_options ();
4096 imm_expr
.X_op
= O_absent
;
4097 offset_expr
.X_op
= O_absent
;
4098 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4099 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4100 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4102 mips_mark_labels ();
4103 mips_assembling_insn
= TRUE
;
4104 clear_insn_error ();
4106 if (mips_opts
.mips16
)
4107 mips16_ip (str
, &insn
);
4110 mips_ip (str
, &insn
);
4111 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4112 str
, insn
.insn_opcode
));
4116 report_insn_error (str
);
4117 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4120 if (mips_opts
.mips16
)
4121 mips16_macro (&insn
);
4128 if (offset_expr
.X_op
!= O_absent
)
4129 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4131 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4134 mips_assembling_insn
= FALSE
;
4137 /* Convenience functions for abstracting away the differences between
4138 MIPS16 and non-MIPS16 relocations. */
4140 static inline bfd_boolean
4141 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4145 case BFD_RELOC_MIPS16_JMP
:
4146 case BFD_RELOC_MIPS16_GPREL
:
4147 case BFD_RELOC_MIPS16_GOT16
:
4148 case BFD_RELOC_MIPS16_CALL16
:
4149 case BFD_RELOC_MIPS16_HI16_S
:
4150 case BFD_RELOC_MIPS16_HI16
:
4151 case BFD_RELOC_MIPS16_LO16
:
4152 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4160 static inline bfd_boolean
4161 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4165 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4166 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4167 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4168 case BFD_RELOC_MICROMIPS_GPREL16
:
4169 case BFD_RELOC_MICROMIPS_JMP
:
4170 case BFD_RELOC_MICROMIPS_HI16
:
4171 case BFD_RELOC_MICROMIPS_HI16_S
:
4172 case BFD_RELOC_MICROMIPS_LO16
:
4173 case BFD_RELOC_MICROMIPS_LITERAL
:
4174 case BFD_RELOC_MICROMIPS_GOT16
:
4175 case BFD_RELOC_MICROMIPS_CALL16
:
4176 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4177 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4178 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4179 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4180 case BFD_RELOC_MICROMIPS_SUB
:
4181 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4182 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4183 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4184 case BFD_RELOC_MICROMIPS_HIGHEST
:
4185 case BFD_RELOC_MICROMIPS_HIGHER
:
4186 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4187 case BFD_RELOC_MICROMIPS_JALR
:
4195 static inline bfd_boolean
4196 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4198 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4201 static inline bfd_boolean
4202 b_reloc_p (bfd_reloc_code_real_type reloc
)
4204 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4205 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4206 || reloc
== BFD_RELOC_16_PCREL_S2
4207 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4208 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4209 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4210 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4213 static inline bfd_boolean
4214 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4216 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4217 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4220 static inline bfd_boolean
4221 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4223 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4224 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4227 static inline bfd_boolean
4228 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4230 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4231 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4234 static inline bfd_boolean
4235 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4237 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4240 static inline bfd_boolean
4241 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4243 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4244 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4247 /* Return true if RELOC is a PC-relative relocation that does not have
4248 full address range. */
4250 static inline bfd_boolean
4251 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4255 case BFD_RELOC_16_PCREL_S2
:
4256 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4257 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4258 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4259 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4260 case BFD_RELOC_MIPS_21_PCREL_S2
:
4261 case BFD_RELOC_MIPS_26_PCREL_S2
:
4262 case BFD_RELOC_MIPS_18_PCREL_S3
:
4263 case BFD_RELOC_MIPS_19_PCREL_S2
:
4266 case BFD_RELOC_32_PCREL
:
4267 case BFD_RELOC_HI16_S_PCREL
:
4268 case BFD_RELOC_LO16_PCREL
:
4269 return HAVE_64BIT_ADDRESSES
;
4276 /* Return true if the given relocation might need a matching %lo().
4277 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4278 need a matching %lo() when applied to local symbols. */
4280 static inline bfd_boolean
4281 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4283 return (HAVE_IN_PLACE_ADDENDS
4284 && (hi16_reloc_p (reloc
)
4285 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4286 all GOT16 relocations evaluate to "G". */
4287 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4290 /* Return the type of %lo() reloc needed by RELOC, given that
4291 reloc_needs_lo_p. */
4293 static inline bfd_reloc_code_real_type
4294 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4296 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4297 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4301 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4304 static inline bfd_boolean
4305 fixup_has_matching_lo_p (fixS
*fixp
)
4307 return (fixp
->fx_next
!= NULL
4308 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4309 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4310 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4313 /* Move all labels in LABELS to the current insertion point. TEXT_P
4314 says whether the labels refer to text or data. */
4317 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4319 struct insn_label_list
*l
;
4322 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4324 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4325 symbol_set_frag (l
->label
, frag_now
);
4326 val
= (valueT
) frag_now_fix ();
4327 /* MIPS16/microMIPS text labels are stored as odd. */
4328 if (text_p
&& HAVE_CODE_COMPRESSION
)
4330 S_SET_VALUE (l
->label
, val
);
4334 /* Move all labels in insn_labels to the current insertion point
4335 and treat them as text labels. */
4338 mips_move_text_labels (void)
4340 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4343 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4346 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4348 bfd_boolean linkonce
= FALSE
;
4349 segT symseg
= S_GET_SEGMENT (sym
);
4351 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4353 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4355 /* The GNU toolchain uses an extension for ELF: a section
4356 beginning with the magic string .gnu.linkonce is a
4357 linkonce section. */
4358 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4359 sizeof ".gnu.linkonce" - 1) == 0)
4365 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4366 linker to handle them specially, such as generating jalx instructions
4367 when needed. We also make them odd for the duration of the assembly,
4368 in order to generate the right sort of code. We will make them even
4369 in the adjust_symtab routine, while leaving them marked. This is
4370 convenient for the debugger and the disassembler. The linker knows
4371 to make them odd again. */
4374 mips_compressed_mark_label (symbolS
*label
)
4376 gas_assert (HAVE_CODE_COMPRESSION
);
4378 if (mips_opts
.mips16
)
4379 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4381 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4382 if ((S_GET_VALUE (label
) & 1) == 0
4383 /* Don't adjust the address if the label is global or weak, or
4384 in a link-once section, since we'll be emitting symbol reloc
4385 references to it which will be patched up by the linker, and
4386 the final value of the symbol may or may not be MIPS16/microMIPS. */
4387 && !S_IS_WEAK (label
)
4388 && !S_IS_EXTERNAL (label
)
4389 && !s_is_linkonce (label
, now_seg
))
4390 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4393 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4396 mips_compressed_mark_labels (void)
4398 struct insn_label_list
*l
;
4400 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4401 mips_compressed_mark_label (l
->label
);
4404 /* End the current frag. Make it a variant frag and record the
4408 relax_close_frag (void)
4410 mips_macro_warning
.first_frag
= frag_now
;
4411 frag_var (rs_machine_dependent
, 0, 0,
4412 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4413 mips_pic
!= NO_PIC
),
4414 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4416 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4417 mips_relax
.first_fixup
= 0;
4420 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4421 See the comment above RELAX_ENCODE for more details. */
4424 relax_start (symbolS
*symbol
)
4426 gas_assert (mips_relax
.sequence
== 0);
4427 mips_relax
.sequence
= 1;
4428 mips_relax
.symbol
= symbol
;
4431 /* Start generating the second version of a relaxable sequence.
4432 See the comment above RELAX_ENCODE for more details. */
4437 gas_assert (mips_relax
.sequence
== 1);
4438 mips_relax
.sequence
= 2;
4441 /* End the current relaxable sequence. */
4446 gas_assert (mips_relax
.sequence
== 2);
4447 relax_close_frag ();
4448 mips_relax
.sequence
= 0;
4451 /* Return true if IP is a delayed branch or jump. */
4453 static inline bfd_boolean
4454 delayed_branch_p (const struct mips_cl_insn
*ip
)
4456 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4457 | INSN_COND_BRANCH_DELAY
4458 | INSN_COND_BRANCH_LIKELY
)) != 0;
4461 /* Return true if IP is a compact branch or jump. */
4463 static inline bfd_boolean
4464 compact_branch_p (const struct mips_cl_insn
*ip
)
4466 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4467 | INSN2_COND_BRANCH
)) != 0;
4470 /* Return true if IP is an unconditional branch or jump. */
4472 static inline bfd_boolean
4473 uncond_branch_p (const struct mips_cl_insn
*ip
)
4475 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4476 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4479 /* Return true if IP is a branch-likely instruction. */
4481 static inline bfd_boolean
4482 branch_likely_p (const struct mips_cl_insn
*ip
)
4484 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4487 /* Return the type of nop that should be used to fill the delay slot
4488 of delayed branch IP. */
4490 static struct mips_cl_insn
*
4491 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4493 if (mips_opts
.micromips
4494 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4495 return µmips_nop32_insn
;
4499 /* Return a mask that has bit N set if OPCODE reads the register(s)
4503 insn_read_mask (const struct mips_opcode
*opcode
)
4505 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4508 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4512 insn_write_mask (const struct mips_opcode
*opcode
)
4514 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4517 /* Return a mask of the registers specified by operand OPERAND of INSN.
4518 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4522 operand_reg_mask (const struct mips_cl_insn
*insn
,
4523 const struct mips_operand
*operand
,
4524 unsigned int type_mask
)
4526 unsigned int uval
, vsel
;
4528 switch (operand
->type
)
4535 case OP_ADDIUSP_INT
:
4536 case OP_ENTRY_EXIT_LIST
:
4537 case OP_REPEAT_DEST_REG
:
4538 case OP_REPEAT_PREV_REG
:
4541 case OP_VU0_MATCH_SUFFIX
:
4549 case OP_OPTIONAL_REG
:
4551 const struct mips_reg_operand
*reg_op
;
4553 reg_op
= (const struct mips_reg_operand
*) operand
;
4554 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4556 uval
= insn_extract_operand (insn
, operand
);
4557 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4562 const struct mips_reg_pair_operand
*pair_op
;
4564 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4565 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4567 uval
= insn_extract_operand (insn
, operand
);
4568 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4571 case OP_CLO_CLZ_DEST
:
4572 if (!(type_mask
& (1 << OP_REG_GP
)))
4574 uval
= insn_extract_operand (insn
, operand
);
4575 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4578 if (!(type_mask
& (1 << OP_REG_GP
)))
4580 uval
= insn_extract_operand (insn
, operand
);
4581 gas_assert ((uval
& 31) == (uval
>> 5));
4582 return 1 << (uval
& 31);
4585 case OP_NON_ZERO_REG
:
4586 if (!(type_mask
& (1 << OP_REG_GP
)))
4588 uval
= insn_extract_operand (insn
, operand
);
4589 return 1 << (uval
& 31);
4591 case OP_LWM_SWM_LIST
:
4594 case OP_SAVE_RESTORE_LIST
:
4597 case OP_MDMX_IMM_REG
:
4598 if (!(type_mask
& (1 << OP_REG_VEC
)))
4600 uval
= insn_extract_operand (insn
, operand
);
4602 if ((vsel
& 0x18) == 0x18)
4604 return 1 << (uval
& 31);
4607 if (!(type_mask
& (1 << OP_REG_GP
)))
4609 return 1 << insn_extract_operand (insn
, operand
);
4614 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4615 where bit N of OPNO_MASK is set if operand N should be included.
4616 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4620 insn_reg_mask (const struct mips_cl_insn
*insn
,
4621 unsigned int type_mask
, unsigned int opno_mask
)
4623 unsigned int opno
, reg_mask
;
4627 while (opno_mask
!= 0)
4630 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4637 /* Return the mask of core registers that IP reads. */
4640 gpr_read_mask (const struct mips_cl_insn
*ip
)
4642 unsigned long pinfo
, pinfo2
;
4645 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4646 pinfo
= ip
->insn_mo
->pinfo
;
4647 pinfo2
= ip
->insn_mo
->pinfo2
;
4648 if (pinfo
& INSN_UDI
)
4650 /* UDI instructions have traditionally been assumed to read RS
4652 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4653 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4655 if (pinfo
& INSN_READ_GPR_24
)
4657 if (pinfo2
& INSN2_READ_GPR_16
)
4659 if (pinfo2
& INSN2_READ_SP
)
4661 if (pinfo2
& INSN2_READ_GPR_31
)
4663 /* Don't include register 0. */
4667 /* Return the mask of core registers that IP writes. */
4670 gpr_write_mask (const struct mips_cl_insn
*ip
)
4672 unsigned long pinfo
, pinfo2
;
4675 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4676 pinfo
= ip
->insn_mo
->pinfo
;
4677 pinfo2
= ip
->insn_mo
->pinfo2
;
4678 if (pinfo
& INSN_WRITE_GPR_24
)
4680 if (pinfo
& INSN_WRITE_GPR_31
)
4682 if (pinfo
& INSN_UDI
)
4683 /* UDI instructions have traditionally been assumed to write to RD. */
4684 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4685 if (pinfo2
& INSN2_WRITE_SP
)
4687 /* Don't include register 0. */
4691 /* Return the mask of floating-point registers that IP reads. */
4694 fpr_read_mask (const struct mips_cl_insn
*ip
)
4696 unsigned long pinfo
;
4699 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4700 | (1 << OP_REG_MSA
)),
4701 insn_read_mask (ip
->insn_mo
));
4702 pinfo
= ip
->insn_mo
->pinfo
;
4703 /* Conservatively treat all operands to an FP_D instruction are doubles.
4704 (This is overly pessimistic for things like cvt.d.s.) */
4705 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4710 /* Return the mask of floating-point registers that IP writes. */
4713 fpr_write_mask (const struct mips_cl_insn
*ip
)
4715 unsigned long pinfo
;
4718 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4719 | (1 << OP_REG_MSA
)),
4720 insn_write_mask (ip
->insn_mo
));
4721 pinfo
= ip
->insn_mo
->pinfo
;
4722 /* Conservatively treat all operands to an FP_D instruction are doubles.
4723 (This is overly pessimistic for things like cvt.s.d.) */
4724 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4729 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4730 Check whether that is allowed. */
4733 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4735 const char *s
= insn
->name
;
4736 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4738 && mips_opts
.oddspreg
;
4740 if (insn
->pinfo
== INSN_MACRO
)
4741 /* Let a macro pass, we'll catch it later when it is expanded. */
4744 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4745 otherwise it depends on oddspreg. */
4746 if ((insn
->pinfo
& FP_S
)
4747 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4748 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4749 return FPR_SIZE
== 32 || oddspreg
;
4751 /* Allow odd registers for single-precision ops and double-precision if the
4752 floating-point registers are 64-bit wide. */
4753 switch (insn
->pinfo
& (FP_S
| FP_D
))
4759 return FPR_SIZE
== 64;
4764 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4765 s
= strchr (insn
->name
, '.');
4766 if (s
!= NULL
&& opnum
== 2)
4767 s
= strchr (s
+ 1, '.');
4768 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4771 return FPR_SIZE
== 64;
4774 /* Information about an instruction argument that we're trying to match. */
4775 struct mips_arg_info
4777 /* The instruction so far. */
4778 struct mips_cl_insn
*insn
;
4780 /* The first unconsumed operand token. */
4781 struct mips_operand_token
*token
;
4783 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4786 /* The 1-based argument number, for error reporting. This does not
4787 count elided optional registers, etc.. */
4790 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4791 unsigned int last_regno
;
4793 /* If the first operand was an OP_REG, this is the register that it
4794 specified, otherwise it is ILLEGAL_REG. */
4795 unsigned int dest_regno
;
4797 /* The value of the last OP_INT operand. Only used for OP_MSB,
4798 where it gives the lsb position. */
4799 unsigned int last_op_int
;
4801 /* If true, match routines should assume that no later instruction
4802 alternative matches and should therefore be as accommodating as
4803 possible. Match routines should not report errors if something
4804 is only invalid for !LAX_MATCH. */
4805 bfd_boolean lax_match
;
4807 /* True if a reference to the current AT register was seen. */
4808 bfd_boolean seen_at
;
4811 /* Record that the argument is out of range. */
4814 match_out_of_range (struct mips_arg_info
*arg
)
4816 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4819 /* Record that the argument isn't constant but needs to be. */
4822 match_not_constant (struct mips_arg_info
*arg
)
4824 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4828 /* Try to match an OT_CHAR token for character CH. Consume the token
4829 and return true on success, otherwise return false. */
4832 match_char (struct mips_arg_info
*arg
, char ch
)
4834 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4844 /* Try to get an expression from the next tokens in ARG. Consume the
4845 tokens and return true on success, storing the expression value in
4846 VALUE and relocation types in R. */
4849 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4850 bfd_reloc_code_real_type
*r
)
4852 /* If the next token is a '(' that was parsed as being part of a base
4853 expression, assume we have an elided offset. The later match will fail
4854 if this turns out to be wrong. */
4855 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4857 value
->X_op
= O_constant
;
4858 value
->X_add_number
= 0;
4859 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4863 /* Reject register-based expressions such as "0+$2" and "(($2))".
4864 For plain registers the default error seems more appropriate. */
4865 if (arg
->token
->type
== OT_INTEGER
4866 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4868 set_insn_error (arg
->argnum
, _("register value used as expression"));
4872 if (arg
->token
->type
== OT_INTEGER
)
4874 *value
= arg
->token
->u
.integer
.value
;
4875 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4881 (arg
->argnum
, _("operand %d must be an immediate expression"),
4886 /* Try to get a constant expression from the next tokens in ARG. Consume
4887 the tokens and return return true on success, storing the constant value
4891 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4894 bfd_reloc_code_real_type r
[3];
4896 if (!match_expression (arg
, &ex
, r
))
4899 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4900 *value
= ex
.X_add_number
;
4903 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4904 match_out_of_range (arg
);
4906 match_not_constant (arg
);
4912 /* Return the RTYPE_* flags for a register operand of type TYPE that
4913 appears in instruction OPCODE. */
4916 convert_reg_type (const struct mips_opcode
*opcode
,
4917 enum mips_reg_operand_type type
)
4922 return RTYPE_NUM
| RTYPE_GP
;
4925 /* Allow vector register names for MDMX if the instruction is a 64-bit
4926 FPR load, store or move (including moves to and from GPRs). */
4927 if ((mips_opts
.ase
& ASE_MDMX
)
4928 && (opcode
->pinfo
& FP_D
)
4929 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4930 | INSN_COPROC_MEMORY_DELAY
4933 | INSN_STORE_MEMORY
)))
4934 return RTYPE_FPU
| RTYPE_VEC
;
4938 if (opcode
->pinfo
& (FP_D
| FP_S
))
4939 return RTYPE_CCC
| RTYPE_FCC
;
4943 if (opcode
->membership
& INSN_5400
)
4945 return RTYPE_FPU
| RTYPE_VEC
;
4951 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4952 return RTYPE_NUM
| RTYPE_CP0
;
4959 return RTYPE_NUM
| RTYPE_VI
;
4962 return RTYPE_NUM
| RTYPE_VF
;
4964 case OP_REG_R5900_I
:
4965 return RTYPE_R5900_I
;
4967 case OP_REG_R5900_Q
:
4968 return RTYPE_R5900_Q
;
4970 case OP_REG_R5900_R
:
4971 return RTYPE_R5900_R
;
4973 case OP_REG_R5900_ACC
:
4974 return RTYPE_R5900_ACC
;
4979 case OP_REG_MSA_CTRL
:
4985 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4988 check_regno (struct mips_arg_info
*arg
,
4989 enum mips_reg_operand_type type
, unsigned int regno
)
4991 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4992 arg
->seen_at
= TRUE
;
4994 if (type
== OP_REG_FP
4996 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4998 /* This was a warning prior to introducing O32 FPXX and FP64 support
4999 so maintain a warning for FP32 but raise an error for the new
5002 as_warn (_("float register should be even, was %d"), regno
);
5004 as_bad (_("float register should be even, was %d"), regno
);
5007 if (type
== OP_REG_CCC
)
5012 name
= arg
->insn
->insn_mo
->name
;
5013 length
= strlen (name
);
5014 if ((regno
& 1) != 0
5015 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5016 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5017 as_warn (_("condition code register should be even for %s, was %d"),
5020 if ((regno
& 3) != 0
5021 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5022 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5027 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5028 a register of type TYPE. Return true on success, storing the register
5029 number in *REGNO and warning about any dubious uses. */
5032 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5033 unsigned int symval
, unsigned int *regno
)
5035 if (type
== OP_REG_VEC
)
5036 symval
= mips_prefer_vec_regno (symval
);
5037 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5040 *regno
= symval
& RNUM_MASK
;
5041 check_regno (arg
, type
, *regno
);
5045 /* Try to interpret the next token in ARG as a register of type TYPE.
5046 Consume the token and return true on success, storing the register
5047 number in *REGNO. Return false on failure. */
5050 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5051 unsigned int *regno
)
5053 if (arg
->token
->type
== OT_REG
5054 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5062 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5063 Consume the token and return true on success, storing the register numbers
5064 in *REGNO1 and *REGNO2. Return false on failure. */
5067 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5068 unsigned int *regno1
, unsigned int *regno2
)
5070 if (match_reg (arg
, type
, regno1
))
5075 if (arg
->token
->type
== OT_REG_RANGE
5076 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5077 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5078 && *regno1
<= *regno2
)
5086 /* OP_INT matcher. */
5089 match_int_operand (struct mips_arg_info
*arg
,
5090 const struct mips_operand
*operand_base
)
5092 const struct mips_int_operand
*operand
;
5094 int min_val
, max_val
, factor
;
5097 operand
= (const struct mips_int_operand
*) operand_base
;
5098 factor
= 1 << operand
->shift
;
5099 min_val
= mips_int_operand_min (operand
);
5100 max_val
= mips_int_operand_max (operand
);
5102 if (operand_base
->lsb
== 0
5103 && operand_base
->size
== 16
5104 && operand
->shift
== 0
5105 && operand
->bias
== 0
5106 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5108 /* The operand can be relocated. */
5109 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5112 if (offset_expr
.X_op
== O_big
)
5114 match_out_of_range (arg
);
5118 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5119 /* Relocation operators were used. Accept the argument and
5120 leave the relocation value in offset_expr and offset_relocs
5121 for the caller to process. */
5124 if (offset_expr
.X_op
!= O_constant
)
5126 /* Accept non-constant operands if no later alternative matches,
5127 leaving it for the caller to process. */
5128 if (!arg
->lax_match
)
5130 match_not_constant (arg
);
5133 offset_reloc
[0] = BFD_RELOC_LO16
;
5137 /* Clear the global state; we're going to install the operand
5139 sval
= offset_expr
.X_add_number
;
5140 offset_expr
.X_op
= O_absent
;
5142 /* For compatibility with older assemblers, we accept
5143 0x8000-0xffff as signed 16-bit numbers when only
5144 signed numbers are allowed. */
5147 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5148 if (!arg
->lax_match
&& sval
<= max_val
)
5150 match_out_of_range (arg
);
5157 if (!match_const_int (arg
, &sval
))
5161 arg
->last_op_int
= sval
;
5163 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5165 match_out_of_range (arg
);
5169 uval
= (unsigned int) sval
>> operand
->shift
;
5170 uval
-= operand
->bias
;
5172 /* Handle -mfix-cn63xxp1. */
5174 && mips_fix_cn63xxp1
5175 && !mips_opts
.micromips
5176 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5191 /* The rest must be changed to 28. */
5196 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5200 /* OP_MAPPED_INT matcher. */
5203 match_mapped_int_operand (struct mips_arg_info
*arg
,
5204 const struct mips_operand
*operand_base
)
5206 const struct mips_mapped_int_operand
*operand
;
5207 unsigned int uval
, num_vals
;
5210 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5211 if (!match_const_int (arg
, &sval
))
5214 num_vals
= 1 << operand_base
->size
;
5215 for (uval
= 0; uval
< num_vals
; uval
++)
5216 if (operand
->int_map
[uval
] == sval
)
5218 if (uval
== num_vals
)
5220 match_out_of_range (arg
);
5224 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5228 /* OP_MSB matcher. */
5231 match_msb_operand (struct mips_arg_info
*arg
,
5232 const struct mips_operand
*operand_base
)
5234 const struct mips_msb_operand
*operand
;
5235 int min_val
, max_val
, max_high
;
5236 offsetT size
, sval
, high
;
5238 operand
= (const struct mips_msb_operand
*) operand_base
;
5239 min_val
= operand
->bias
;
5240 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5241 max_high
= operand
->opsize
;
5243 if (!match_const_int (arg
, &size
))
5246 high
= size
+ arg
->last_op_int
;
5247 sval
= operand
->add_lsb
? high
: size
;
5249 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5251 match_out_of_range (arg
);
5254 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5258 /* OP_REG matcher. */
5261 match_reg_operand (struct mips_arg_info
*arg
,
5262 const struct mips_operand
*operand_base
)
5264 const struct mips_reg_operand
*operand
;
5265 unsigned int regno
, uval
, num_vals
;
5267 operand
= (const struct mips_reg_operand
*) operand_base
;
5268 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5271 if (operand
->reg_map
)
5273 num_vals
= 1 << operand
->root
.size
;
5274 for (uval
= 0; uval
< num_vals
; uval
++)
5275 if (operand
->reg_map
[uval
] == regno
)
5277 if (num_vals
== uval
)
5283 arg
->last_regno
= regno
;
5284 if (arg
->opnum
== 1)
5285 arg
->dest_regno
= regno
;
5286 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5290 /* OP_REG_PAIR matcher. */
5293 match_reg_pair_operand (struct mips_arg_info
*arg
,
5294 const struct mips_operand
*operand_base
)
5296 const struct mips_reg_pair_operand
*operand
;
5297 unsigned int regno1
, regno2
, uval
, num_vals
;
5299 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5300 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5301 || !match_char (arg
, ',')
5302 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5305 num_vals
= 1 << operand_base
->size
;
5306 for (uval
= 0; uval
< num_vals
; uval
++)
5307 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5309 if (uval
== num_vals
)
5312 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5316 /* OP_PCREL matcher. The caller chooses the relocation type. */
5319 match_pcrel_operand (struct mips_arg_info
*arg
)
5321 bfd_reloc_code_real_type r
[3];
5323 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5326 /* OP_PERF_REG matcher. */
5329 match_perf_reg_operand (struct mips_arg_info
*arg
,
5330 const struct mips_operand
*operand
)
5334 if (!match_const_int (arg
, &sval
))
5339 || (mips_opts
.arch
== CPU_R5900
5340 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5341 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5343 set_insn_error (arg
->argnum
, _("invalid performance register"));
5347 insn_insert_operand (arg
->insn
, operand
, sval
);
5351 /* OP_ADDIUSP matcher. */
5354 match_addiusp_operand (struct mips_arg_info
*arg
,
5355 const struct mips_operand
*operand
)
5360 if (!match_const_int (arg
, &sval
))
5365 match_out_of_range (arg
);
5370 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5372 match_out_of_range (arg
);
5376 uval
= (unsigned int) sval
;
5377 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5378 insn_insert_operand (arg
->insn
, operand
, uval
);
5382 /* OP_CLO_CLZ_DEST matcher. */
5385 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5386 const struct mips_operand
*operand
)
5390 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5393 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5397 /* OP_CHECK_PREV matcher. */
5400 match_check_prev_operand (struct mips_arg_info
*arg
,
5401 const struct mips_operand
*operand_base
)
5403 const struct mips_check_prev_operand
*operand
;
5406 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5408 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5411 if (!operand
->zero_ok
&& regno
== 0)
5414 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5415 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5416 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5418 arg
->last_regno
= regno
;
5419 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5426 /* OP_SAME_RS_RT matcher. */
5429 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5430 const struct mips_operand
*operand
)
5434 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5439 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5443 arg
->last_regno
= regno
;
5445 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5449 /* OP_LWM_SWM_LIST matcher. */
5452 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5453 const struct mips_operand
*operand
)
5455 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5456 struct mips_arg_info reset
;
5459 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5463 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5468 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5471 while (match_char (arg
, ',')
5472 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5475 if (operand
->size
== 2)
5477 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5483 and any permutations of these. */
5484 if ((reglist
& 0xfff1ffff) != 0x80010000)
5487 sregs
= (reglist
>> 17) & 7;
5492 /* The list must include at least one of ra and s0-sN,
5493 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5494 which are $23 and $30 respectively.) E.g.:
5502 and any permutations of these. */
5503 if ((reglist
& 0x3f00ffff) != 0)
5506 ra
= (reglist
>> 27) & 0x10;
5507 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5510 if ((sregs
& -sregs
) != sregs
)
5513 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5517 /* OP_ENTRY_EXIT_LIST matcher. */
5520 match_entry_exit_operand (struct mips_arg_info
*arg
,
5521 const struct mips_operand
*operand
)
5524 bfd_boolean is_exit
;
5526 /* The format is the same for both ENTRY and EXIT, but the constraints
5528 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5529 mask
= (is_exit
? 7 << 3 : 0);
5532 unsigned int regno1
, regno2
;
5533 bfd_boolean is_freg
;
5535 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5537 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5542 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5545 mask
|= (5 + regno2
) << 3;
5547 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5548 mask
|= (regno2
- 3) << 3;
5549 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5550 mask
|= (regno2
- 15) << 1;
5551 else if (regno1
== RA
&& regno2
== RA
)
5556 while (match_char (arg
, ','));
5558 insn_insert_operand (arg
->insn
, operand
, mask
);
5562 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5563 the argument register mask AMASK, the number of static registers
5564 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5565 respectively, and the frame size FRAME_SIZE. */
5568 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5569 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5570 unsigned int frame_size
)
5572 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5573 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5576 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5577 argument register mask AMASK, the number of static registers saved
5578 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5579 respectively, and the frame size FRAME_SIZE. */
5582 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5583 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5584 unsigned int frame_size
)
5588 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5589 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5590 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5591 | ((frame_size
& 0xf0) << 16));
5595 /* OP_SAVE_RESTORE_LIST matcher. */
5598 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5600 unsigned int opcode
, args
, statics
, sregs
;
5601 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5602 unsigned int arg_mask
, ra
, s0
, s1
;
5605 opcode
= arg
->insn
->insn_opcode
;
5607 num_frame_sizes
= 0;
5616 unsigned int regno1
, regno2
;
5618 if (arg
->token
->type
== OT_INTEGER
)
5620 /* Handle the frame size. */
5621 if (!match_const_int (arg
, &frame_size
))
5623 num_frame_sizes
+= 1;
5627 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5630 while (regno1
<= regno2
)
5632 if (regno1
>= 4 && regno1
<= 7)
5634 if (num_frame_sizes
== 0)
5636 args
|= 1 << (regno1
- 4);
5638 /* statics $a0-$a3 */
5639 statics
|= 1 << (regno1
- 4);
5641 else if (regno1
>= 16 && regno1
<= 23)
5643 sregs
|= 1 << (regno1
- 16);
5644 else if (regno1
== 30)
5647 else if (regno1
== 31)
5648 /* Add $ra to insn. */
5658 while (match_char (arg
, ','));
5660 /* Encode args/statics combination. */
5663 else if (args
== 0xf)
5664 /* All $a0-$a3 are args. */
5665 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5666 else if (statics
== 0xf)
5667 /* All $a0-$a3 are statics. */
5668 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5671 /* Count arg registers. */
5681 /* Count static registers. */
5683 while (statics
& 0x8)
5685 statics
= (statics
<< 1) & 0xf;
5691 /* Encode args/statics. */
5692 arg_mask
= (num_args
<< 2) | num_statics
;
5695 /* Encode $s0/$s1. */
5696 if (sregs
& (1 << 0)) /* $s0 */
5698 if (sregs
& (1 << 1)) /* $s1 */
5702 /* Encode $s2-$s8. */
5712 /* Encode frame size. */
5713 if (num_frame_sizes
== 0)
5715 set_insn_error (arg
->argnum
, _("missing frame size"));
5718 if (num_frame_sizes
> 1)
5720 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5723 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5725 set_insn_error (arg
->argnum
, _("invalid frame size"));
5730 /* Finally build the instruction. */
5731 if (mips_opts
.mips16
)
5732 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5734 else if (!mips_opts
.micromips
)
5735 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5740 arg
->insn
->insn_opcode
= opcode
;
5744 /* OP_MDMX_IMM_REG matcher. */
5747 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5748 const struct mips_operand
*operand
)
5750 unsigned int regno
, uval
;
5752 const struct mips_opcode
*opcode
;
5754 /* The mips_opcode records whether this is an octobyte or quadhalf
5755 instruction. Start out with that bit in place. */
5756 opcode
= arg
->insn
->insn_mo
;
5757 uval
= mips_extract_operand (operand
, opcode
->match
);
5758 is_qh
= (uval
!= 0);
5760 if (arg
->token
->type
== OT_REG
)
5762 if ((opcode
->membership
& INSN_5400
)
5763 && strcmp (opcode
->name
, "rzu.ob") == 0)
5765 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5770 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5774 /* Check whether this is a vector register or a broadcast of
5775 a single element. */
5776 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5778 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5780 set_insn_error (arg
->argnum
, _("invalid element selector"));
5783 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5788 /* A full vector. */
5789 if ((opcode
->membership
& INSN_5400
)
5790 && (strcmp (opcode
->name
, "sll.ob") == 0
5791 || strcmp (opcode
->name
, "srl.ob") == 0))
5793 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5799 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5801 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5809 if (!match_const_int (arg
, &sval
))
5811 if (sval
< 0 || sval
> 31)
5813 match_out_of_range (arg
);
5816 uval
|= (sval
& 31);
5818 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5820 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5822 insn_insert_operand (arg
->insn
, operand
, uval
);
5826 /* OP_IMM_INDEX matcher. */
5829 match_imm_index_operand (struct mips_arg_info
*arg
,
5830 const struct mips_operand
*operand
)
5832 unsigned int max_val
;
5834 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5837 max_val
= (1 << operand
->size
) - 1;
5838 if (arg
->token
->u
.index
> max_val
)
5840 match_out_of_range (arg
);
5843 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5848 /* OP_REG_INDEX matcher. */
5851 match_reg_index_operand (struct mips_arg_info
*arg
,
5852 const struct mips_operand
*operand
)
5856 if (arg
->token
->type
!= OT_REG_INDEX
)
5859 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5862 insn_insert_operand (arg
->insn
, operand
, regno
);
5867 /* OP_PC matcher. */
5870 match_pc_operand (struct mips_arg_info
*arg
)
5872 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5880 /* OP_REG28 matcher. */
5883 match_reg28_operand (struct mips_arg_info
*arg
)
5887 if (arg
->token
->type
== OT_REG
5888 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5897 /* OP_NON_ZERO_REG matcher. */
5900 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5901 const struct mips_operand
*operand
)
5905 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5911 arg
->last_regno
= regno
;
5912 insn_insert_operand (arg
->insn
, operand
, regno
);
5916 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5917 register that we need to match. */
5920 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5924 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5927 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5928 the length of the value in bytes (4 for float, 8 for double) and
5929 USING_GPRS says whether the destination is a GPR rather than an FPR.
5931 Return the constant in IMM and OFFSET as follows:
5933 - If the constant should be loaded via memory, set IMM to O_absent and
5934 OFFSET to the memory address.
5936 - Otherwise, if the constant should be loaded into two 32-bit registers,
5937 set IMM to the O_constant to load into the high register and OFFSET
5938 to the corresponding value for the low register.
5940 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5942 These constants only appear as the last operand in an instruction,
5943 and every instruction that accepts them in any variant accepts them
5944 in all variants. This means we don't have to worry about backing out
5945 any changes if the instruction does not match. We just match
5946 unconditionally and report an error if the constant is invalid. */
5949 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5950 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5955 const char *newname
;
5956 unsigned char *data
;
5958 /* Where the constant is placed is based on how the MIPS assembler
5961 length == 4 && using_gprs -- immediate value only
5962 length == 8 && using_gprs -- .rdata or immediate value
5963 length == 4 && !using_gprs -- .lit4 or immediate value
5964 length == 8 && !using_gprs -- .lit8 or immediate value
5966 The .lit4 and .lit8 sections are only used if permitted by the
5968 if (arg
->token
->type
!= OT_FLOAT
)
5970 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5974 gas_assert (arg
->token
->u
.flt
.length
== length
);
5975 data
= arg
->token
->u
.flt
.data
;
5978 /* Handle 32-bit constants for which an immediate value is best. */
5981 || g_switch_value
< 4
5982 || (data
[0] == 0 && data
[1] == 0)
5983 || (data
[2] == 0 && data
[3] == 0)))
5985 imm
->X_op
= O_constant
;
5986 if (!target_big_endian
)
5987 imm
->X_add_number
= bfd_getl32 (data
);
5989 imm
->X_add_number
= bfd_getb32 (data
);
5990 offset
->X_op
= O_absent
;
5994 /* Handle 64-bit constants for which an immediate value is best. */
5996 && !mips_disable_float_construction
5997 /* Constants can only be constructed in GPRs and copied to FPRs if the
5998 GPRs are at least as wide as the FPRs or MTHC1 is available.
5999 Unlike most tests for 32-bit floating-point registers this check
6000 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6001 permit 64-bit moves without MXHC1.
6002 Force the constant into memory otherwise. */
6005 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6007 && ((data
[0] == 0 && data
[1] == 0)
6008 || (data
[2] == 0 && data
[3] == 0))
6009 && ((data
[4] == 0 && data
[5] == 0)
6010 || (data
[6] == 0 && data
[7] == 0)))
6012 /* The value is simple enough to load with a couple of instructions.
6013 If using 32-bit registers, set IMM to the high order 32 bits and
6014 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6016 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6018 imm
->X_op
= O_constant
;
6019 offset
->X_op
= O_constant
;
6020 if (!target_big_endian
)
6022 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6023 offset
->X_add_number
= bfd_getl32 (data
);
6027 imm
->X_add_number
= bfd_getb32 (data
);
6028 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6030 if (offset
->X_add_number
== 0)
6031 offset
->X_op
= O_absent
;
6035 imm
->X_op
= O_constant
;
6036 if (!target_big_endian
)
6037 imm
->X_add_number
= bfd_getl64 (data
);
6039 imm
->X_add_number
= bfd_getb64 (data
);
6040 offset
->X_op
= O_absent
;
6045 /* Switch to the right section. */
6047 subseg
= now_subseg
;
6050 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6055 if (using_gprs
|| g_switch_value
< 8)
6056 newname
= RDATA_SECTION_NAME
;
6061 new_seg
= subseg_new (newname
, (subsegT
) 0);
6062 bfd_set_section_flags (stdoutput
, new_seg
,
6063 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6064 frag_align (length
== 4 ? 2 : 3, 0, 0);
6065 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6066 record_alignment (new_seg
, 4);
6068 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6070 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6072 /* Set the argument to the current address in the section. */
6073 imm
->X_op
= O_absent
;
6074 offset
->X_op
= O_symbol
;
6075 offset
->X_add_symbol
= symbol_temp_new_now ();
6076 offset
->X_add_number
= 0;
6078 /* Put the floating point number into the section. */
6079 p
= frag_more (length
);
6080 memcpy (p
, data
, length
);
6082 /* Switch back to the original section. */
6083 subseg_set (seg
, subseg
);
6087 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6091 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6092 const struct mips_operand
*operand
,
6093 bfd_boolean match_p
)
6097 /* The operand can be an XYZW mask or a single 2-bit channel index
6098 (with X being 0). */
6099 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6101 /* The suffix can be omitted when it is already part of the opcode. */
6102 if (arg
->token
->type
!= OT_CHANNELS
)
6105 uval
= arg
->token
->u
.channels
;
6106 if (operand
->size
== 2)
6108 /* Check that a single bit is set and convert it into a 2-bit index. */
6109 if ((uval
& -uval
) != uval
)
6111 uval
= 4 - ffs (uval
);
6114 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6119 insn_insert_operand (arg
->insn
, operand
, uval
);
6123 /* S is the text seen for ARG. Match it against OPERAND. Return the end
6124 of the argument text if the match is successful, otherwise return null. */
6127 match_operand (struct mips_arg_info
*arg
,
6128 const struct mips_operand
*operand
)
6130 switch (operand
->type
)
6133 return match_int_operand (arg
, operand
);
6136 return match_mapped_int_operand (arg
, operand
);
6139 return match_msb_operand (arg
, operand
);
6142 case OP_OPTIONAL_REG
:
6143 return match_reg_operand (arg
, operand
);
6146 return match_reg_pair_operand (arg
, operand
);
6149 return match_pcrel_operand (arg
);
6152 return match_perf_reg_operand (arg
, operand
);
6154 case OP_ADDIUSP_INT
:
6155 return match_addiusp_operand (arg
, operand
);
6157 case OP_CLO_CLZ_DEST
:
6158 return match_clo_clz_dest_operand (arg
, operand
);
6160 case OP_LWM_SWM_LIST
:
6161 return match_lwm_swm_list_operand (arg
, operand
);
6163 case OP_ENTRY_EXIT_LIST
:
6164 return match_entry_exit_operand (arg
, operand
);
6166 case OP_SAVE_RESTORE_LIST
:
6167 return match_save_restore_list_operand (arg
);
6169 case OP_MDMX_IMM_REG
:
6170 return match_mdmx_imm_reg_operand (arg
, operand
);
6172 case OP_REPEAT_DEST_REG
:
6173 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6175 case OP_REPEAT_PREV_REG
:
6176 return match_tied_reg_operand (arg
, arg
->last_regno
);
6179 return match_pc_operand (arg
);
6182 return match_reg28_operand (arg
);
6185 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6187 case OP_VU0_MATCH_SUFFIX
:
6188 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6191 return match_imm_index_operand (arg
, operand
);
6194 return match_reg_index_operand (arg
, operand
);
6197 return match_same_rs_rt_operand (arg
, operand
);
6200 return match_check_prev_operand (arg
, operand
);
6202 case OP_NON_ZERO_REG
:
6203 return match_non_zero_reg_operand (arg
, operand
);
6208 /* ARG is the state after successfully matching an instruction.
6209 Issue any queued-up warnings. */
6212 check_completed_insn (struct mips_arg_info
*arg
)
6217 as_warn (_("used $at without \".set noat\""));
6219 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6223 /* Return true if modifying general-purpose register REG needs a delay. */
6226 reg_needs_delay (unsigned int reg
)
6228 unsigned long prev_pinfo
;
6230 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6231 if (!mips_opts
.noreorder
6232 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6233 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6234 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6240 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6241 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6242 by VR4120 errata. */
6245 classify_vr4120_insn (const char *name
)
6247 if (strncmp (name
, "macc", 4) == 0)
6248 return FIX_VR4120_MACC
;
6249 if (strncmp (name
, "dmacc", 5) == 0)
6250 return FIX_VR4120_DMACC
;
6251 if (strncmp (name
, "mult", 4) == 0)
6252 return FIX_VR4120_MULT
;
6253 if (strncmp (name
, "dmult", 5) == 0)
6254 return FIX_VR4120_DMULT
;
6255 if (strstr (name
, "div"))
6256 return FIX_VR4120_DIV
;
6257 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6258 return FIX_VR4120_MTHILO
;
6259 return NUM_FIX_VR4120_CLASSES
;
6262 #define INSN_ERET 0x42000018
6263 #define INSN_DERET 0x4200001f
6264 #define INSN_DMULT 0x1c
6265 #define INSN_DMULTU 0x1d
6267 /* Return the number of instructions that must separate INSN1 and INSN2,
6268 where INSN1 is the earlier instruction. Return the worst-case value
6269 for any INSN2 if INSN2 is null. */
6272 insns_between (const struct mips_cl_insn
*insn1
,
6273 const struct mips_cl_insn
*insn2
)
6275 unsigned long pinfo1
, pinfo2
;
6278 /* If INFO2 is null, pessimistically assume that all flags are set for
6279 the second instruction. */
6280 pinfo1
= insn1
->insn_mo
->pinfo
;
6281 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6283 /* For most targets, write-after-read dependencies on the HI and LO
6284 registers must be separated by at least two instructions. */
6285 if (!hilo_interlocks
)
6287 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6289 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6293 /* If we're working around r7000 errata, there must be two instructions
6294 between an mfhi or mflo and any instruction that uses the result. */
6295 if (mips_7000_hilo_fix
6296 && !mips_opts
.micromips
6297 && MF_HILO_INSN (pinfo1
)
6298 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6301 /* If we're working around 24K errata, one instruction is required
6302 if an ERET or DERET is followed by a branch instruction. */
6303 if (mips_fix_24k
&& !mips_opts
.micromips
)
6305 if (insn1
->insn_opcode
== INSN_ERET
6306 || insn1
->insn_opcode
== INSN_DERET
)
6309 || insn2
->insn_opcode
== INSN_ERET
6310 || insn2
->insn_opcode
== INSN_DERET
6311 || delayed_branch_p (insn2
))
6316 /* If we're working around PMC RM7000 errata, there must be three
6317 nops between a dmult and a load instruction. */
6318 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6320 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6321 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6323 if (pinfo2
& INSN_LOAD_MEMORY
)
6328 /* If working around VR4120 errata, check for combinations that need
6329 a single intervening instruction. */
6330 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6332 unsigned int class1
, class2
;
6334 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6335 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6339 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6340 if (vr4120_conflicts
[class1
] & (1 << class2
))
6345 if (!HAVE_CODE_COMPRESSION
)
6347 /* Check for GPR or coprocessor load delays. All such delays
6348 are on the RT register. */
6349 /* Itbl support may require additional care here. */
6350 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6351 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6353 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6357 /* Check for generic coprocessor hazards.
6359 This case is not handled very well. There is no special
6360 knowledge of CP0 handling, and the coprocessors other than
6361 the floating point unit are not distinguished at all. */
6362 /* Itbl support may require additional care here. FIXME!
6363 Need to modify this to include knowledge about
6364 user specified delays! */
6365 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6366 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6368 /* Handle cases where INSN1 writes to a known general coprocessor
6369 register. There must be a one instruction delay before INSN2
6370 if INSN2 reads that register, otherwise no delay is needed. */
6371 mask
= fpr_write_mask (insn1
);
6374 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6379 /* Read-after-write dependencies on the control registers
6380 require a two-instruction gap. */
6381 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6382 && (pinfo2
& INSN_READ_COND_CODE
))
6385 /* We don't know exactly what INSN1 does. If INSN2 is
6386 also a coprocessor instruction, assume there must be
6387 a one instruction gap. */
6388 if (pinfo2
& INSN_COP
)
6393 /* Check for read-after-write dependencies on the coprocessor
6394 control registers in cases where INSN1 does not need a general
6395 coprocessor delay. This means that INSN1 is a floating point
6396 comparison instruction. */
6397 /* Itbl support may require additional care here. */
6398 else if (!cop_interlocks
6399 && (pinfo1
& INSN_WRITE_COND_CODE
)
6400 && (pinfo2
& INSN_READ_COND_CODE
))
6404 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6405 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6407 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6408 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6409 || (insn2
&& delayed_branch_p (insn2
))))
6415 /* Return the number of nops that would be needed to work around the
6416 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6417 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6418 that are contained within the first IGNORE instructions of HIST. */
6421 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6422 const struct mips_cl_insn
*insn
)
6427 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6428 are not affected by the errata. */
6430 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6431 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6432 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6435 /* Search for the first MFLO or MFHI. */
6436 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6437 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6439 /* Extract the destination register. */
6440 mask
= gpr_write_mask (&hist
[i
]);
6442 /* No nops are needed if INSN reads that register. */
6443 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6446 /* ...or if any of the intervening instructions do. */
6447 for (j
= 0; j
< i
; j
++)
6448 if (gpr_read_mask (&hist
[j
]) & mask
)
6452 return MAX_VR4130_NOPS
- i
;
6457 #define BASE_REG_EQ(INSN1, INSN2) \
6458 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6459 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6461 /* Return the minimum alignment for this store instruction. */
6464 fix_24k_align_to (const struct mips_opcode
*mo
)
6466 if (strcmp (mo
->name
, "sh") == 0)
6469 if (strcmp (mo
->name
, "swc1") == 0
6470 || strcmp (mo
->name
, "swc2") == 0
6471 || strcmp (mo
->name
, "sw") == 0
6472 || strcmp (mo
->name
, "sc") == 0
6473 || strcmp (mo
->name
, "s.s") == 0)
6476 if (strcmp (mo
->name
, "sdc1") == 0
6477 || strcmp (mo
->name
, "sdc2") == 0
6478 || strcmp (mo
->name
, "s.d") == 0)
6485 struct fix_24k_store_info
6487 /* Immediate offset, if any, for this store instruction. */
6489 /* Alignment required by this store instruction. */
6491 /* True for register offsets. */
6492 int register_offset
;
6495 /* Comparison function used by qsort. */
6498 fix_24k_sort (const void *a
, const void *b
)
6500 const struct fix_24k_store_info
*pos1
= a
;
6501 const struct fix_24k_store_info
*pos2
= b
;
6503 return (pos1
->off
- pos2
->off
);
6506 /* INSN is a store instruction. Try to record the store information
6507 in STINFO. Return false if the information isn't known. */
6510 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6511 const struct mips_cl_insn
*insn
)
6513 /* The instruction must have a known offset. */
6514 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6517 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6518 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6522 /* Return the number of nops that would be needed to work around the 24k
6523 "lost data on stores during refill" errata if instruction INSN
6524 immediately followed the 2 instructions described by HIST.
6525 Ignore hazards that are contained within the first IGNORE
6526 instructions of HIST.
6528 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6529 for the data cache refills and store data. The following describes
6530 the scenario where the store data could be lost.
6532 * A data cache miss, due to either a load or a store, causing fill
6533 data to be supplied by the memory subsystem
6534 * The first three doublewords of fill data are returned and written
6536 * A sequence of four stores occurs in consecutive cycles around the
6537 final doubleword of the fill:
6541 * Zero, One or more instructions
6544 The four stores A-D must be to different doublewords of the line that
6545 is being filled. The fourth instruction in the sequence above permits
6546 the fill of the final doubleword to be transferred from the FSB into
6547 the cache. In the sequence above, the stores may be either integer
6548 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6549 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6550 different doublewords on the line. If the floating point unit is
6551 running in 1:2 mode, it is not possible to create the sequence above
6552 using only floating point store instructions.
6554 In this case, the cache line being filled is incorrectly marked
6555 invalid, thereby losing the data from any store to the line that
6556 occurs between the original miss and the completion of the five
6557 cycle sequence shown above.
6559 The workarounds are:
6561 * Run the data cache in write-through mode.
6562 * Insert a non-store instruction between
6563 Store A and Store B or Store B and Store C. */
6566 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6567 const struct mips_cl_insn
*insn
)
6569 struct fix_24k_store_info pos
[3];
6570 int align
, i
, base_offset
;
6575 /* If the previous instruction wasn't a store, there's nothing to
6577 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6580 /* If the instructions after the previous one are unknown, we have
6581 to assume the worst. */
6585 /* Check whether we are dealing with three consecutive stores. */
6586 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6587 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6590 /* If we don't know the relationship between the store addresses,
6591 assume the worst. */
6592 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6593 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6596 if (!fix_24k_record_store_info (&pos
[0], insn
)
6597 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6598 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6601 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6603 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6604 X bytes and such that the base register + X is known to be aligned
6607 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6611 align
= pos
[0].align_to
;
6612 base_offset
= pos
[0].off
;
6613 for (i
= 1; i
< 3; i
++)
6614 if (align
< pos
[i
].align_to
)
6616 align
= pos
[i
].align_to
;
6617 base_offset
= pos
[i
].off
;
6619 for (i
= 0; i
< 3; i
++)
6620 pos
[i
].off
-= base_offset
;
6623 pos
[0].off
&= ~align
+ 1;
6624 pos
[1].off
&= ~align
+ 1;
6625 pos
[2].off
&= ~align
+ 1;
6627 /* If any two stores write to the same chunk, they also write to the
6628 same doubleword. The offsets are still sorted at this point. */
6629 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6632 /* A range of at least 9 bytes is needed for the stores to be in
6633 non-overlapping doublewords. */
6634 if (pos
[2].off
- pos
[0].off
<= 8)
6637 if (pos
[2].off
- pos
[1].off
>= 24
6638 || pos
[1].off
- pos
[0].off
>= 24
6639 || pos
[2].off
- pos
[0].off
>= 32)
6645 /* Return the number of nops that would be needed if instruction INSN
6646 immediately followed the MAX_NOPS instructions given by HIST,
6647 where HIST[0] is the most recent instruction. Ignore hazards
6648 between INSN and the first IGNORE instructions in HIST.
6650 If INSN is null, return the worse-case number of nops for any
6654 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6655 const struct mips_cl_insn
*insn
)
6657 int i
, nops
, tmp_nops
;
6660 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6662 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6663 if (tmp_nops
> nops
)
6667 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6669 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6670 if (tmp_nops
> nops
)
6674 if (mips_fix_24k
&& !mips_opts
.micromips
)
6676 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6677 if (tmp_nops
> nops
)
6684 /* The variable arguments provide NUM_INSNS extra instructions that
6685 might be added to HIST. Return the largest number of nops that
6686 would be needed after the extended sequence, ignoring hazards
6687 in the first IGNORE instructions. */
6690 nops_for_sequence (int num_insns
, int ignore
,
6691 const struct mips_cl_insn
*hist
, ...)
6694 struct mips_cl_insn buffer
[MAX_NOPS
];
6695 struct mips_cl_insn
*cursor
;
6698 va_start (args
, hist
);
6699 cursor
= buffer
+ num_insns
;
6700 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6701 while (cursor
> buffer
)
6702 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6704 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6709 /* Like nops_for_insn, but if INSN is a branch, take into account the
6710 worst-case delay for the branch target. */
6713 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6714 const struct mips_cl_insn
*insn
)
6718 nops
= nops_for_insn (ignore
, hist
, insn
);
6719 if (delayed_branch_p (insn
))
6721 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6722 hist
, insn
, get_delay_slot_nop (insn
));
6723 if (tmp_nops
> nops
)
6726 else if (compact_branch_p (insn
))
6728 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6729 if (tmp_nops
> nops
)
6735 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6738 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6740 gas_assert (!HAVE_CODE_COMPRESSION
);
6741 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6742 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6745 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6746 jr target pc &= 'hffff_ffff_cfff_ffff. */
6749 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6751 gas_assert (!HAVE_CODE_COMPRESSION
);
6752 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6753 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6754 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6762 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6763 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6766 ep
.X_op
= O_constant
;
6767 ep
.X_add_number
= 0xcfff0000;
6768 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6769 ep
.X_add_number
= 0xffff;
6770 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6771 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6776 fix_loongson2f (struct mips_cl_insn
* ip
)
6778 if (mips_fix_loongson2f_nop
)
6779 fix_loongson2f_nop (ip
);
6781 if (mips_fix_loongson2f_jump
)
6782 fix_loongson2f_jump (ip
);
6785 /* IP is a branch that has a delay slot, and we need to fill it
6786 automatically. Return true if we can do that by swapping IP
6787 with the previous instruction.
6788 ADDRESS_EXPR is an operand of the instruction to be used with
6792 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6793 bfd_reloc_code_real_type
*reloc_type
)
6795 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6796 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6797 unsigned int fpr_read
, prev_fpr_write
;
6799 /* -O2 and above is required for this optimization. */
6800 if (mips_optimize
< 2)
6803 /* If we have seen .set volatile or .set nomove, don't optimize. */
6804 if (mips_opts
.nomove
)
6807 /* We can't swap if the previous instruction's position is fixed. */
6808 if (history
[0].fixed_p
)
6811 /* If the previous previous insn was in a .set noreorder, we can't
6812 swap. Actually, the MIPS assembler will swap in this situation.
6813 However, gcc configured -with-gnu-as will generate code like
6821 in which we can not swap the bne and INSN. If gcc is not configured
6822 -with-gnu-as, it does not output the .set pseudo-ops. */
6823 if (history
[1].noreorder_p
)
6826 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6827 This means that the previous instruction was a 4-byte one anyhow. */
6828 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6831 /* If the branch is itself the target of a branch, we can not swap.
6832 We cheat on this; all we check for is whether there is a label on
6833 this instruction. If there are any branches to anything other than
6834 a label, users must use .set noreorder. */
6835 if (seg_info (now_seg
)->label_list
)
6838 /* If the previous instruction is in a variant frag other than this
6839 branch's one, we cannot do the swap. This does not apply to
6840 MIPS16 code, which uses variant frags for different purposes. */
6841 if (!mips_opts
.mips16
6843 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6846 /* We do not swap with instructions that cannot architecturally
6847 be placed in a branch delay slot, such as SYNC or ERET. We
6848 also refrain from swapping with a trap instruction, since it
6849 complicates trap handlers to have the trap instruction be in
6851 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6852 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6855 /* Check for conflicts between the branch and the instructions
6856 before the candidate delay slot. */
6857 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6860 /* Check for conflicts between the swapped sequence and the
6861 target of the branch. */
6862 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6865 /* If the branch reads a register that the previous
6866 instruction sets, we can not swap. */
6867 gpr_read
= gpr_read_mask (ip
);
6868 prev_gpr_write
= gpr_write_mask (&history
[0]);
6869 if (gpr_read
& prev_gpr_write
)
6872 fpr_read
= fpr_read_mask (ip
);
6873 prev_fpr_write
= fpr_write_mask (&history
[0]);
6874 if (fpr_read
& prev_fpr_write
)
6877 /* If the branch writes a register that the previous
6878 instruction sets, we can not swap. */
6879 gpr_write
= gpr_write_mask (ip
);
6880 if (gpr_write
& prev_gpr_write
)
6883 /* If the branch writes a register that the previous
6884 instruction reads, we can not swap. */
6885 prev_gpr_read
= gpr_read_mask (&history
[0]);
6886 if (gpr_write
& prev_gpr_read
)
6889 /* If one instruction sets a condition code and the
6890 other one uses a condition code, we can not swap. */
6891 pinfo
= ip
->insn_mo
->pinfo
;
6892 if ((pinfo
& INSN_READ_COND_CODE
)
6893 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6895 if ((pinfo
& INSN_WRITE_COND_CODE
)
6896 && (prev_pinfo
& INSN_READ_COND_CODE
))
6899 /* If the previous instruction uses the PC, we can not swap. */
6900 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6901 if (prev_pinfo2
& INSN2_READ_PC
)
6904 /* If the previous instruction has an incorrect size for a fixed
6905 branch delay slot in microMIPS mode, we cannot swap. */
6906 pinfo2
= ip
->insn_mo
->pinfo2
;
6907 if (mips_opts
.micromips
6908 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6909 && insn_length (history
) != 2)
6911 if (mips_opts
.micromips
6912 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6913 && insn_length (history
) != 4)
6916 /* On R5900 short loops need to be fixed by inserting a nop in
6917 the branch delay slots.
6918 A short loop can be terminated too early. */
6919 if (mips_opts
.arch
== CPU_R5900
6920 /* Check if instruction has a parameter, ignore "j $31". */
6921 && (address_expr
!= NULL
)
6922 /* Parameter must be 16 bit. */
6923 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6924 /* Branch to same segment. */
6925 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6926 /* Branch to same code fragment. */
6927 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6928 /* Can only calculate branch offset if value is known. */
6929 && symbol_constant_p (address_expr
->X_add_symbol
)
6930 /* Check if branch is really conditional. */
6931 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6932 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6933 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6936 /* Check if loop is shorter than 6 instructions including
6937 branch and delay slot. */
6938 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6945 /* When the loop includes branches or jumps,
6946 it is not a short loop. */
6947 for (i
= 0; i
< (distance
/ 4); i
++)
6949 if ((history
[i
].cleared_p
)
6950 || delayed_branch_p (&history
[i
]))
6958 /* Insert nop after branch to fix short loop. */
6967 /* Decide how we should add IP to the instruction stream.
6968 ADDRESS_EXPR is an operand of the instruction to be used with
6971 static enum append_method
6972 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6973 bfd_reloc_code_real_type
*reloc_type
)
6975 /* The relaxed version of a macro sequence must be inherently
6977 if (mips_relax
.sequence
== 2)
6980 /* We must not dabble with instructions in a ".set noreorder" block. */
6981 if (mips_opts
.noreorder
)
6984 /* Otherwise, it's our responsibility to fill branch delay slots. */
6985 if (delayed_branch_p (ip
))
6987 if (!branch_likely_p (ip
)
6988 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6991 if (mips_opts
.mips16
6992 && ISA_SUPPORTS_MIPS16E
6993 && gpr_read_mask (ip
) != 0)
6994 return APPEND_ADD_COMPACT
;
6996 if (mips_opts
.micromips
6997 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
6998 || (!forced_insn_length
6999 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7000 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7001 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7002 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7003 return APPEND_ADD_COMPACT
;
7005 return APPEND_ADD_WITH_NOP
;
7011 /* IP is an instruction whose opcode we have just changed, END points
7012 to the end of the opcode table processed. Point IP->insn_mo to the
7013 new opcode's definition. */
7016 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7018 const struct mips_opcode
*mo
;
7020 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7021 if (mo
->pinfo
!= INSN_MACRO
7022 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7030 /* IP is a MIPS16 instruction whose opcode we have just changed.
7031 Point IP->insn_mo to the new opcode's definition. */
7034 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7036 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7039 /* IP is a microMIPS instruction whose opcode we have just changed.
7040 Point IP->insn_mo to the new opcode's definition. */
7043 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7045 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7048 /* For microMIPS macros, we need to generate a local number label
7049 as the target of branches. */
7050 #define MICROMIPS_LABEL_CHAR '\037'
7051 static unsigned long micromips_target_label
;
7052 static char micromips_target_name
[32];
7055 micromips_label_name (void)
7057 char *p
= micromips_target_name
;
7058 char symbol_name_temporary
[24];
7066 l
= micromips_target_label
;
7067 #ifdef LOCAL_LABEL_PREFIX
7068 *p
++ = LOCAL_LABEL_PREFIX
;
7071 *p
++ = MICROMIPS_LABEL_CHAR
;
7074 symbol_name_temporary
[i
++] = l
% 10 + '0';
7079 *p
++ = symbol_name_temporary
[--i
];
7082 return micromips_target_name
;
7086 micromips_label_expr (expressionS
*label_expr
)
7088 label_expr
->X_op
= O_symbol
;
7089 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7090 label_expr
->X_add_number
= 0;
7094 micromips_label_inc (void)
7096 micromips_target_label
++;
7097 *micromips_target_name
= '\0';
7101 micromips_add_label (void)
7105 s
= colon (micromips_label_name ());
7106 micromips_label_inc ();
7107 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7110 /* If assembling microMIPS code, then return the microMIPS reloc
7111 corresponding to the requested one if any. Otherwise return
7112 the reloc unchanged. */
7114 static bfd_reloc_code_real_type
7115 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7117 static const bfd_reloc_code_real_type relocs
[][2] =
7119 /* Keep sorted incrementally by the left-hand key. */
7120 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7121 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7122 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7123 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7124 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7125 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7126 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7127 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7128 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7129 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7130 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7131 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7132 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7133 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7134 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7135 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7136 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7137 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7138 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7139 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7140 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7141 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7142 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7143 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7144 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7145 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7146 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7148 bfd_reloc_code_real_type r
;
7151 if (!mips_opts
.micromips
)
7153 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7159 return relocs
[i
][1];
7164 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7165 Return true on success, storing the resolved value in RESULT. */
7168 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7173 case BFD_RELOC_MIPS_HIGHEST
:
7174 case BFD_RELOC_MICROMIPS_HIGHEST
:
7175 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7178 case BFD_RELOC_MIPS_HIGHER
:
7179 case BFD_RELOC_MICROMIPS_HIGHER
:
7180 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7183 case BFD_RELOC_HI16_S
:
7184 case BFD_RELOC_HI16_S_PCREL
:
7185 case BFD_RELOC_MICROMIPS_HI16_S
:
7186 case BFD_RELOC_MIPS16_HI16_S
:
7187 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7190 case BFD_RELOC_HI16
:
7191 case BFD_RELOC_MICROMIPS_HI16
:
7192 case BFD_RELOC_MIPS16_HI16
:
7193 *result
= (operand
>> 16) & 0xffff;
7196 case BFD_RELOC_LO16
:
7197 case BFD_RELOC_LO16_PCREL
:
7198 case BFD_RELOC_MICROMIPS_LO16
:
7199 case BFD_RELOC_MIPS16_LO16
:
7200 *result
= operand
& 0xffff;
7203 case BFD_RELOC_UNUSED
:
7212 /* Output an instruction. IP is the instruction information.
7213 ADDRESS_EXPR is an operand of the instruction to be used with
7214 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7215 a macro expansion. */
7218 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7219 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7221 unsigned long prev_pinfo2
, pinfo
;
7222 bfd_boolean relaxed_branch
= FALSE
;
7223 enum append_method method
;
7224 bfd_boolean relax32
;
7227 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7228 fix_loongson2f (ip
);
7230 file_ase_mips16
|= mips_opts
.mips16
;
7231 file_ase_micromips
|= mips_opts
.micromips
;
7233 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7234 pinfo
= ip
->insn_mo
->pinfo
;
7236 /* Don't raise alarm about `nods' frags as they'll fill in the right
7237 kind of nop in relaxation if required. */
7238 if (mips_opts
.micromips
7240 && !(history
[0].frag
7241 && history
[0].frag
->fr_type
== rs_machine_dependent
7242 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7243 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7244 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7245 && micromips_insn_length (ip
->insn_mo
) != 2)
7246 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7247 && micromips_insn_length (ip
->insn_mo
) != 4)))
7248 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7249 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7251 if (address_expr
== NULL
)
7253 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7254 && reloc_type
[1] == BFD_RELOC_UNUSED
7255 && reloc_type
[2] == BFD_RELOC_UNUSED
7256 && address_expr
->X_op
== O_constant
)
7258 switch (*reloc_type
)
7260 case BFD_RELOC_MIPS_JMP
:
7264 /* Shift is 2, unusually, for microMIPS JALX. */
7265 shift
= (mips_opts
.micromips
7266 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7267 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7268 as_bad (_("jump to misaligned address (0x%lx)"),
7269 (unsigned long) address_expr
->X_add_number
);
7270 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7276 case BFD_RELOC_MIPS16_JMP
:
7277 if ((address_expr
->X_add_number
& 3) != 0)
7278 as_bad (_("jump to misaligned address (0x%lx)"),
7279 (unsigned long) address_expr
->X_add_number
);
7281 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7282 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7283 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7287 case BFD_RELOC_16_PCREL_S2
:
7291 shift
= mips_opts
.micromips
? 1 : 2;
7292 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7293 as_bad (_("branch to misaligned address (0x%lx)"),
7294 (unsigned long) address_expr
->X_add_number
);
7295 if (!mips_relax_branch
)
7297 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7298 & ~((1 << (shift
+ 16)) - 1))
7299 as_bad (_("branch address range overflow (0x%lx)"),
7300 (unsigned long) address_expr
->X_add_number
);
7301 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7307 case BFD_RELOC_MIPS_21_PCREL_S2
:
7312 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7313 as_bad (_("branch to misaligned address (0x%lx)"),
7314 (unsigned long) address_expr
->X_add_number
);
7315 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7316 & ~((1 << (shift
+ 21)) - 1))
7317 as_bad (_("branch address range overflow (0x%lx)"),
7318 (unsigned long) address_expr
->X_add_number
);
7319 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7324 case BFD_RELOC_MIPS_26_PCREL_S2
:
7329 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7330 as_bad (_("branch to misaligned address (0x%lx)"),
7331 (unsigned long) address_expr
->X_add_number
);
7332 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7333 & ~((1 << (shift
+ 26)) - 1))
7334 as_bad (_("branch address range overflow (0x%lx)"),
7335 (unsigned long) address_expr
->X_add_number
);
7336 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7345 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7348 ip
->insn_opcode
|= value
& 0xffff;
7356 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7358 /* There are a lot of optimizations we could do that we don't.
7359 In particular, we do not, in general, reorder instructions.
7360 If you use gcc with optimization, it will reorder
7361 instructions and generally do much more optimization then we
7362 do here; repeating all that work in the assembler would only
7363 benefit hand written assembly code, and does not seem worth
7365 int nops
= (mips_optimize
== 0
7366 ? nops_for_insn (0, history
, NULL
)
7367 : nops_for_insn_or_target (0, history
, ip
));
7371 unsigned long old_frag_offset
;
7374 old_frag
= frag_now
;
7375 old_frag_offset
= frag_now_fix ();
7377 for (i
= 0; i
< nops
; i
++)
7378 add_fixed_insn (NOP_INSN
);
7379 insert_into_history (0, nops
, NOP_INSN
);
7383 listing_prev_line ();
7384 /* We may be at the start of a variant frag. In case we
7385 are, make sure there is enough space for the frag
7386 after the frags created by listing_prev_line. The
7387 argument to frag_grow here must be at least as large
7388 as the argument to all other calls to frag_grow in
7389 this file. We don't have to worry about being in the
7390 middle of a variant frag, because the variants insert
7391 all needed nop instructions themselves. */
7395 mips_move_text_labels ();
7397 #ifndef NO_ECOFF_DEBUGGING
7398 if (ECOFF_DEBUGGING
)
7399 ecoff_fix_loc (old_frag
, old_frag_offset
);
7403 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7407 /* Work out how many nops in prev_nop_frag are needed by IP,
7408 ignoring hazards generated by the first prev_nop_frag_since
7410 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7411 gas_assert (nops
<= prev_nop_frag_holds
);
7413 /* Enforce NOPS as a minimum. */
7414 if (nops
> prev_nop_frag_required
)
7415 prev_nop_frag_required
= nops
;
7417 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7419 /* Settle for the current number of nops. Update the history
7420 accordingly (for the benefit of any future .set reorder code). */
7421 prev_nop_frag
= NULL
;
7422 insert_into_history (prev_nop_frag_since
,
7423 prev_nop_frag_holds
, NOP_INSN
);
7427 /* Allow this instruction to replace one of the nops that was
7428 tentatively added to prev_nop_frag. */
7429 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7430 prev_nop_frag_holds
--;
7431 prev_nop_frag_since
++;
7435 method
= get_append_method (ip
, address_expr
, reloc_type
);
7436 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7438 dwarf2_emit_insn (0);
7439 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7440 so "move" the instruction address accordingly.
7442 Also, it doesn't seem appropriate for the assembler to reorder .loc
7443 entries. If this instruction is a branch that we are going to swap
7444 with the previous instruction, the two instructions should be
7445 treated as a unit, and the debug information for both instructions
7446 should refer to the start of the branch sequence. Using the
7447 current position is certainly wrong when swapping a 32-bit branch
7448 and a 16-bit delay slot, since the current position would then be
7449 in the middle of a branch. */
7450 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7452 relax32
= (mips_relax_branch
7453 /* Don't try branch relaxation within .set nomacro, or within
7454 .set noat if we use $at for PIC computations. If it turns
7455 out that the branch was out-of-range, we'll get an error. */
7456 && !mips_opts
.warn_about_macros
7457 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7458 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7459 as they have no complementing branches. */
7460 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7462 if (!HAVE_CODE_COMPRESSION
7465 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7466 && delayed_branch_p (ip
))
7468 relaxed_branch
= TRUE
;
7469 add_relaxed_insn (ip
, (relaxed_branch_length
7471 uncond_branch_p (ip
) ? -1
7472 : branch_likely_p (ip
) ? 1
7475 (AT
, mips_pic
!= NO_PIC
,
7476 uncond_branch_p (ip
),
7477 branch_likely_p (ip
),
7478 pinfo
& INSN_WRITE_GPR_31
,
7480 address_expr
->X_add_symbol
,
7481 address_expr
->X_add_number
);
7482 *reloc_type
= BFD_RELOC_UNUSED
;
7484 else if (mips_opts
.micromips
7486 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7487 || *reloc_type
> BFD_RELOC_UNUSED
)
7488 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7489 /* Don't try branch relaxation when users specify
7490 16-bit/32-bit instructions. */
7491 && !forced_insn_length
)
7493 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7494 && *reloc_type
> BFD_RELOC_UNUSED
);
7495 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7496 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7497 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7498 int nods
= method
== APPEND_ADD_WITH_NOP
;
7499 int al
= pinfo
& INSN_WRITE_GPR_31
;
7500 int length32
= nods
? 8 : 4;
7502 gas_assert (address_expr
!= NULL
);
7503 gas_assert (!mips_relax
.sequence
);
7505 relaxed_branch
= TRUE
;
7507 method
= APPEND_ADD
;
7509 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7510 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7511 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7513 uncond
, compact
, al
, nods
,
7515 address_expr
->X_add_symbol
,
7516 address_expr
->X_add_number
);
7517 *reloc_type
= BFD_RELOC_UNUSED
;
7519 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7521 bfd_boolean require_unextended
;
7522 bfd_boolean require_extended
;
7526 if (forced_insn_length
!= 0)
7528 require_unextended
= forced_insn_length
== 2;
7529 require_extended
= forced_insn_length
== 4;
7533 require_unextended
= (mips_opts
.noautoextend
7534 && !mips_opcode_32bit_p (ip
->insn_mo
));
7535 require_extended
= 0;
7538 /* We need to set up a variant frag. */
7539 gas_assert (address_expr
!= NULL
);
7540 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7541 symbol created by `make_expr_symbol' may not get a necessary
7542 external relocation produced. */
7543 if (address_expr
->X_op
== O_symbol
)
7545 symbol
= address_expr
->X_add_symbol
;
7546 offset
= address_expr
->X_add_number
;
7550 symbol
= make_expr_symbol (address_expr
);
7551 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7554 add_relaxed_insn (ip
, 12, 0,
7556 (*reloc_type
- BFD_RELOC_UNUSED
,
7557 mips_opts
.ase
& ASE_MIPS16E2
,
7560 mips_opts
.warn_about_macros
,
7561 require_unextended
, require_extended
,
7562 delayed_branch_p (&history
[0]),
7563 history
[0].mips16_absolute_jump_p
),
7566 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7568 if (!delayed_branch_p (ip
))
7569 /* Make sure there is enough room to swap this instruction with
7570 a following jump instruction. */
7572 add_fixed_insn (ip
);
7576 if (mips_opts
.mips16
7577 && mips_opts
.noreorder
7578 && delayed_branch_p (&history
[0]))
7579 as_warn (_("extended instruction in delay slot"));
7581 if (mips_relax
.sequence
)
7583 /* If we've reached the end of this frag, turn it into a variant
7584 frag and record the information for the instructions we've
7586 if (frag_room () < 4)
7587 relax_close_frag ();
7588 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7591 if (mips_relax
.sequence
!= 2)
7593 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7594 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7595 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7596 mips_macro_warning
.insns
[0]++;
7598 if (mips_relax
.sequence
!= 1)
7600 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7601 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7602 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7603 mips_macro_warning
.insns
[1]++;
7606 if (mips_opts
.mips16
)
7609 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7611 add_fixed_insn (ip
);
7614 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7616 bfd_reloc_code_real_type final_type
[3];
7617 reloc_howto_type
*howto0
;
7618 reloc_howto_type
*howto
;
7621 /* Perform any necessary conversion to microMIPS relocations
7622 and find out how many relocations there actually are. */
7623 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7624 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7626 /* In a compound relocation, it is the final (outermost)
7627 operator that determines the relocated field. */
7628 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7633 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7634 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7635 bfd_get_reloc_size (howto
),
7637 howto0
&& howto0
->pc_relative
,
7639 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7640 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7642 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7643 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7644 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7646 /* These relocations can have an addend that won't fit in
7647 4 octets for 64bit assembly. */
7649 && ! howto
->partial_inplace
7650 && (reloc_type
[0] == BFD_RELOC_16
7651 || reloc_type
[0] == BFD_RELOC_32
7652 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7653 || reloc_type
[0] == BFD_RELOC_GPREL16
7654 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7655 || reloc_type
[0] == BFD_RELOC_GPREL32
7656 || reloc_type
[0] == BFD_RELOC_64
7657 || reloc_type
[0] == BFD_RELOC_CTOR
7658 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7659 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7660 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7661 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7662 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7663 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7664 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7665 || hi16_reloc_p (reloc_type
[0])
7666 || lo16_reloc_p (reloc_type
[0])))
7667 ip
->fixp
[0]->fx_no_overflow
= 1;
7669 /* These relocations can have an addend that won't fit in 2 octets. */
7670 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7671 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7672 ip
->fixp
[0]->fx_no_overflow
= 1;
7674 if (mips_relax
.sequence
)
7676 if (mips_relax
.first_fixup
== 0)
7677 mips_relax
.first_fixup
= ip
->fixp
[0];
7679 else if (reloc_needs_lo_p (*reloc_type
))
7681 struct mips_hi_fixup
*hi_fixup
;
7683 /* Reuse the last entry if it already has a matching %lo. */
7684 hi_fixup
= mips_hi_fixup_list
;
7686 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7688 hi_fixup
= XNEW (struct mips_hi_fixup
);
7689 hi_fixup
->next
= mips_hi_fixup_list
;
7690 mips_hi_fixup_list
= hi_fixup
;
7692 hi_fixup
->fixp
= ip
->fixp
[0];
7693 hi_fixup
->seg
= now_seg
;
7696 /* Add fixups for the second and third relocations, if given.
7697 Note that the ABI allows the second relocation to be
7698 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7699 moment we only use RSS_UNDEF, but we could add support
7700 for the others if it ever becomes necessary. */
7701 for (i
= 1; i
< 3; i
++)
7702 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7704 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7705 ip
->fixp
[0]->fx_size
, NULL
, 0,
7706 FALSE
, final_type
[i
]);
7708 /* Use fx_tcbit to mark compound relocs. */
7709 ip
->fixp
[0]->fx_tcbit
= 1;
7710 ip
->fixp
[i
]->fx_tcbit
= 1;
7714 /* Update the register mask information. */
7715 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7716 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7721 insert_into_history (0, 1, ip
);
7724 case APPEND_ADD_WITH_NOP
:
7726 struct mips_cl_insn
*nop
;
7728 insert_into_history (0, 1, ip
);
7729 nop
= get_delay_slot_nop (ip
);
7730 add_fixed_insn (nop
);
7731 insert_into_history (0, 1, nop
);
7732 if (mips_relax
.sequence
)
7733 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7737 case APPEND_ADD_COMPACT
:
7738 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7739 if (mips_opts
.mips16
)
7741 ip
->insn_opcode
|= 0x0080;
7742 find_altered_mips16_opcode (ip
);
7744 /* Convert microMIPS instructions. */
7745 else if (mips_opts
.micromips
)
7748 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7749 ip
->insn_opcode
|= 0x0020;
7751 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7752 ip
->insn_opcode
= 0x40e00000;
7753 /* beqz16->beqzc, bnez16->bnezc */
7754 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7756 unsigned long regno
;
7758 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7759 regno
&= MICROMIPSOP_MASK_MD
;
7760 regno
= micromips_to_32_reg_d_map
[regno
];
7761 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7762 | (regno
<< MICROMIPSOP_SH_RS
)
7763 | 0x40a00000) ^ 0x00400000;
7765 /* beqz->beqzc, bnez->bnezc */
7766 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7767 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7768 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7769 | 0x40a00000) ^ 0x00400000;
7770 /* beq $0->beqzc, bne $0->bnezc */
7771 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7772 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7773 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7774 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7775 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7776 | 0x40a00000) ^ 0x00400000;
7779 find_altered_micromips_opcode (ip
);
7784 insert_into_history (0, 1, ip
);
7789 struct mips_cl_insn delay
= history
[0];
7791 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7793 /* Add the delay slot instruction to the end of the
7794 current frag and shrink the fixed part of the
7795 original frag. If the branch occupies the tail of
7796 the latter, move it backwards to cover the gap. */
7797 delay
.frag
->fr_fix
-= branch_disp
;
7798 if (delay
.frag
== ip
->frag
)
7799 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7800 add_fixed_insn (&delay
);
7804 /* If this is not a relaxed branch and we are in the
7805 same frag, then just swap the instructions. */
7806 move_insn (ip
, delay
.frag
, delay
.where
);
7807 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7811 insert_into_history (0, 1, &delay
);
7816 /* If we have just completed an unconditional branch, clear the history. */
7817 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7818 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7822 mips_no_prev_insn ();
7824 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7825 history
[i
].cleared_p
= 1;
7828 /* We need to emit a label at the end of branch-likely macros. */
7829 if (emit_branch_likely_macro
)
7831 emit_branch_likely_macro
= FALSE
;
7832 micromips_add_label ();
7835 /* We just output an insn, so the next one doesn't have a label. */
7836 mips_clear_insn_labels ();
7839 /* Forget that there was any previous instruction or label.
7840 When BRANCH is true, the branch history is also flushed. */
7843 mips_no_prev_insn (void)
7845 prev_nop_frag
= NULL
;
7846 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7847 mips_clear_insn_labels ();
7850 /* This function must be called before we emit something other than
7851 instructions. It is like mips_no_prev_insn except that it inserts
7852 any NOPS that might be needed by previous instructions. */
7855 mips_emit_delays (void)
7857 if (! mips_opts
.noreorder
)
7859 int nops
= nops_for_insn (0, history
, NULL
);
7863 add_fixed_insn (NOP_INSN
);
7864 mips_move_text_labels ();
7867 mips_no_prev_insn ();
7870 /* Start a (possibly nested) noreorder block. */
7873 start_noreorder (void)
7875 if (mips_opts
.noreorder
== 0)
7880 /* None of the instructions before the .set noreorder can be moved. */
7881 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7882 history
[i
].fixed_p
= 1;
7884 /* Insert any nops that might be needed between the .set noreorder
7885 block and the previous instructions. We will later remove any
7886 nops that turn out not to be needed. */
7887 nops
= nops_for_insn (0, history
, NULL
);
7890 if (mips_optimize
!= 0)
7892 /* Record the frag which holds the nop instructions, so
7893 that we can remove them if we don't need them. */
7894 frag_grow (nops
* NOP_INSN_SIZE
);
7895 prev_nop_frag
= frag_now
;
7896 prev_nop_frag_holds
= nops
;
7897 prev_nop_frag_required
= 0;
7898 prev_nop_frag_since
= 0;
7901 for (; nops
> 0; --nops
)
7902 add_fixed_insn (NOP_INSN
);
7904 /* Move on to a new frag, so that it is safe to simply
7905 decrease the size of prev_nop_frag. */
7906 frag_wane (frag_now
);
7908 mips_move_text_labels ();
7910 mips_mark_labels ();
7911 mips_clear_insn_labels ();
7913 mips_opts
.noreorder
++;
7914 mips_any_noreorder
= 1;
7917 /* End a nested noreorder block. */
7920 end_noreorder (void)
7922 mips_opts
.noreorder
--;
7923 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7925 /* Commit to inserting prev_nop_frag_required nops and go back to
7926 handling nop insertion the .set reorder way. */
7927 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7929 insert_into_history (prev_nop_frag_since
,
7930 prev_nop_frag_required
, NOP_INSN
);
7931 prev_nop_frag
= NULL
;
7935 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7936 higher bits unset. */
7939 normalize_constant_expr (expressionS
*ex
)
7941 if (ex
->X_op
== O_constant
7942 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7943 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7947 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7948 all higher bits unset. */
7951 normalize_address_expr (expressionS
*ex
)
7953 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7954 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7955 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7956 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7960 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7961 Return true if the match was successful.
7963 OPCODE_EXTRA is a value that should be ORed into the opcode
7964 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7965 there are more alternatives after OPCODE and SOFT_MATCH is
7966 as for mips_arg_info. */
7969 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7970 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7971 bfd_boolean lax_match
, bfd_boolean complete_p
)
7974 struct mips_arg_info arg
;
7975 const struct mips_operand
*operand
;
7978 imm_expr
.X_op
= O_absent
;
7979 offset_expr
.X_op
= O_absent
;
7980 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7981 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7982 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7984 create_insn (insn
, opcode
);
7985 /* When no opcode suffix is specified, assume ".xyzw". */
7986 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7987 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7989 insn
->insn_opcode
|= opcode_extra
;
7990 memset (&arg
, 0, sizeof (arg
));
7994 arg
.last_regno
= ILLEGAL_REG
;
7995 arg
.dest_regno
= ILLEGAL_REG
;
7996 arg
.lax_match
= lax_match
;
7997 for (args
= opcode
->args
;; ++args
)
7999 if (arg
.token
->type
== OT_END
)
8001 /* Handle unary instructions in which only one operand is given.
8002 The source is then the same as the destination. */
8003 if (arg
.opnum
== 1 && *args
== ',')
8005 operand
= (mips_opts
.micromips
8006 ? decode_micromips_operand (args
+ 1)
8007 : decode_mips_operand (args
+ 1));
8008 if (operand
&& mips_optional_operand_p (operand
))
8016 /* Treat elided base registers as $0. */
8017 if (strcmp (args
, "(b)") == 0)
8025 /* The register suffix is optional. */
8030 /* Fail the match if there were too few operands. */
8034 /* Successful match. */
8037 clear_insn_error ();
8038 if (arg
.dest_regno
== arg
.last_regno
8039 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8043 (0, _("source and destination must be different"));
8044 else if (arg
.last_regno
== 31)
8046 (0, _("a destination register must be supplied"));
8048 else if (arg
.last_regno
== 31
8049 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8050 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8051 set_insn_error (0, _("the source register must not be $31"));
8052 check_completed_insn (&arg
);
8056 /* Fail the match if the line has too many operands. */
8060 /* Handle characters that need to match exactly. */
8061 if (*args
== '(' || *args
== ')' || *args
== ',')
8063 if (match_char (&arg
, *args
))
8070 if (arg
.token
->type
== OT_DOUBLE_CHAR
8071 && arg
.token
->u
.ch
== *args
)
8079 /* Handle special macro operands. Work out the properties of
8088 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8092 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8101 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8105 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8109 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8115 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8117 imm_expr
.X_op
= O_constant
;
8119 normalize_constant_expr (&imm_expr
);
8123 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8125 /* Assume that the offset has been elided and that what
8126 we saw was a base register. The match will fail later
8127 if that assumption turns out to be wrong. */
8128 offset_expr
.X_op
= O_constant
;
8129 offset_expr
.X_add_number
= 0;
8133 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8135 normalize_address_expr (&offset_expr
);
8140 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8146 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8152 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8158 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8164 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8168 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8172 gas_assert (mips_opts
.micromips
);
8178 if (!forced_insn_length
)
8179 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8181 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8183 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8189 operand
= (mips_opts
.micromips
8190 ? decode_micromips_operand (args
)
8191 : decode_mips_operand (args
));
8195 /* Skip prefixes. */
8196 if (*args
== '+' || *args
== 'm' || *args
== '-')
8199 if (mips_optional_operand_p (operand
)
8201 && (arg
.token
[0].type
!= OT_REG
8202 || arg
.token
[1].type
== OT_END
))
8204 /* Assume that the register has been elided and is the
8205 same as the first operand. */
8210 if (!match_operand (&arg
, operand
))
8215 /* Like match_insn, but for MIPS16. */
8218 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8219 struct mips_operand_token
*tokens
)
8222 const struct mips_operand
*operand
;
8223 const struct mips_operand
*ext_operand
;
8224 bfd_boolean pcrel
= FALSE
;
8225 int required_insn_length
;
8226 struct mips_arg_info arg
;
8229 if (forced_insn_length
)
8230 required_insn_length
= forced_insn_length
;
8231 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8232 required_insn_length
= 2;
8234 required_insn_length
= 0;
8236 create_insn (insn
, opcode
);
8237 imm_expr
.X_op
= O_absent
;
8238 offset_expr
.X_op
= O_absent
;
8239 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8240 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8241 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8244 memset (&arg
, 0, sizeof (arg
));
8248 arg
.last_regno
= ILLEGAL_REG
;
8249 arg
.dest_regno
= ILLEGAL_REG
;
8251 for (args
= opcode
->args
;; ++args
)
8255 if (arg
.token
->type
== OT_END
)
8259 /* Handle unary instructions in which only one operand is given.
8260 The source is then the same as the destination. */
8261 if (arg
.opnum
== 1 && *args
== ',')
8263 operand
= decode_mips16_operand (args
[1], FALSE
);
8264 if (operand
&& mips_optional_operand_p (operand
))
8272 /* Fail the match if there were too few operands. */
8276 /* Successful match. Stuff the immediate value in now, if
8278 clear_insn_error ();
8279 if (opcode
->pinfo
== INSN_MACRO
)
8281 gas_assert (relax_char
== 0 || relax_char
== 'p');
8282 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8285 && offset_expr
.X_op
== O_constant
8287 && calculate_reloc (*offset_reloc
,
8288 offset_expr
.X_add_number
,
8291 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8292 required_insn_length
, &insn
->insn_opcode
);
8293 offset_expr
.X_op
= O_absent
;
8294 *offset_reloc
= BFD_RELOC_UNUSED
;
8296 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8298 if (required_insn_length
== 2)
8299 set_insn_error (0, _("invalid unextended operand value"));
8300 else if (!mips_opcode_32bit_p (opcode
))
8302 forced_insn_length
= 4;
8303 insn
->insn_opcode
|= MIPS16_EXTEND
;
8306 else if (relax_char
)
8307 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8309 check_completed_insn (&arg
);
8313 /* Fail the match if the line has too many operands. */
8317 /* Handle characters that need to match exactly. */
8318 if (*args
== '(' || *args
== ')' || *args
== ',')
8320 if (match_char (&arg
, *args
))
8340 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8342 imm_expr
.X_op
= O_constant
;
8344 normalize_constant_expr (&imm_expr
);
8349 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8353 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8357 if (operand
->type
== OP_PCREL
)
8361 ext_operand
= decode_mips16_operand (c
, TRUE
);
8362 if (operand
!= ext_operand
)
8364 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8366 offset_expr
.X_op
= O_constant
;
8367 offset_expr
.X_add_number
= 0;
8372 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8375 /* '8' is used for SLTI(U) and has traditionally not
8376 been allowed to take relocation operators. */
8377 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8378 && (ext_operand
->size
!= 16 || c
== '8'))
8380 match_not_constant (&arg
);
8384 if (offset_expr
.X_op
== O_big
)
8386 match_out_of_range (&arg
);
8395 if (mips_optional_operand_p (operand
)
8397 && (arg
.token
[0].type
!= OT_REG
8398 || arg
.token
[1].type
== OT_END
))
8400 /* Assume that the register has been elided and is the
8401 same as the first operand. */
8406 if (!match_operand (&arg
, operand
))
8411 /* Record that the current instruction is invalid for the current ISA. */
8414 match_invalid_for_isa (void)
8417 (0, _("opcode not supported on this processor: %s (%s)"),
8418 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8419 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8422 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8423 Return true if a definite match or failure was found, storing any match
8424 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8425 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8426 tried and failed to match under normal conditions and now want to try a
8427 more relaxed match. */
8430 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8431 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8432 int opcode_extra
, bfd_boolean lax_match
)
8434 const struct mips_opcode
*opcode
;
8435 const struct mips_opcode
*invalid_delay_slot
;
8436 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8438 /* Search for a match, ignoring alternatives that don't satisfy the
8439 current ISA or forced_length. */
8440 invalid_delay_slot
= 0;
8441 seen_valid_for_isa
= FALSE
;
8442 seen_valid_for_size
= FALSE
;
8446 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8447 if (is_opcode_valid (opcode
))
8449 seen_valid_for_isa
= TRUE
;
8450 if (is_size_valid (opcode
))
8452 bfd_boolean delay_slot_ok
;
8454 seen_valid_for_size
= TRUE
;
8455 delay_slot_ok
= is_delay_slot_valid (opcode
);
8456 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8457 lax_match
, delay_slot_ok
))
8461 if (!invalid_delay_slot
)
8462 invalid_delay_slot
= opcode
;
8471 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8473 /* If the only matches we found had the wrong length for the delay slot,
8474 pick the first such match. We'll issue an appropriate warning later. */
8475 if (invalid_delay_slot
)
8477 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8483 /* Handle the case where we didn't try to match an instruction because
8484 all the alternatives were incompatible with the current ISA. */
8485 if (!seen_valid_for_isa
)
8487 match_invalid_for_isa ();
8491 /* Handle the case where we didn't try to match an instruction because
8492 all the alternatives were of the wrong size. */
8493 if (!seen_valid_for_size
)
8495 if (mips_opts
.insn32
)
8496 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8499 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8500 8 * forced_insn_length
);
8507 /* Like match_insns, but for MIPS16. */
8510 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8511 struct mips_operand_token
*tokens
)
8513 const struct mips_opcode
*opcode
;
8514 bfd_boolean seen_valid_for_isa
;
8515 bfd_boolean seen_valid_for_size
;
8517 /* Search for a match, ignoring alternatives that don't satisfy the
8518 current ISA. There are no separate entries for extended forms so
8519 we deal with forced_length later. */
8520 seen_valid_for_isa
= FALSE
;
8521 seen_valid_for_size
= FALSE
;
8525 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8526 if (is_opcode_valid_16 (opcode
))
8528 seen_valid_for_isa
= TRUE
;
8529 if (is_size_valid_16 (opcode
))
8531 seen_valid_for_size
= TRUE
;
8532 if (match_mips16_insn (insn
, opcode
, tokens
))
8538 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8539 && strcmp (opcode
->name
, first
->name
) == 0);
8541 /* Handle the case where we didn't try to match an instruction because
8542 all the alternatives were incompatible with the current ISA. */
8543 if (!seen_valid_for_isa
)
8545 match_invalid_for_isa ();
8549 /* Handle the case where we didn't try to match an instruction because
8550 all the alternatives were of the wrong size. */
8551 if (!seen_valid_for_size
)
8553 if (forced_insn_length
== 2)
8555 (0, _("unrecognized unextended version of MIPS16 opcode"));
8558 (0, _("unrecognized extended version of MIPS16 opcode"));
8565 /* Set up global variables for the start of a new macro. */
8570 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8571 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8572 sizeof (mips_macro_warning
.first_insn_sizes
));
8573 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8574 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8575 && delayed_branch_p (&history
[0]));
8577 && history
[0].frag
->fr_type
== rs_machine_dependent
8578 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8579 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8580 mips_macro_warning
.delay_slot_length
= 0;
8582 switch (history
[0].insn_mo
->pinfo2
8583 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8585 case INSN2_BRANCH_DELAY_32BIT
:
8586 mips_macro_warning
.delay_slot_length
= 4;
8588 case INSN2_BRANCH_DELAY_16BIT
:
8589 mips_macro_warning
.delay_slot_length
= 2;
8592 mips_macro_warning
.delay_slot_length
= 0;
8595 mips_macro_warning
.first_frag
= NULL
;
8598 /* Given that a macro is longer than one instruction or of the wrong size,
8599 return the appropriate warning for it. Return null if no warning is
8600 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8601 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8602 and RELAX_NOMACRO. */
8605 macro_warning (relax_substateT subtype
)
8607 if (subtype
& RELAX_DELAY_SLOT
)
8608 return _("macro instruction expanded into multiple instructions"
8609 " in a branch delay slot");
8610 else if (subtype
& RELAX_NOMACRO
)
8611 return _("macro instruction expanded into multiple instructions");
8612 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8613 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8614 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8615 ? _("macro instruction expanded into a wrong size instruction"
8616 " in a 16-bit branch delay slot")
8617 : _("macro instruction expanded into a wrong size instruction"
8618 " in a 32-bit branch delay slot"));
8623 /* Finish up a macro. Emit warnings as appropriate. */
8628 /* Relaxation warning flags. */
8629 relax_substateT subtype
= 0;
8631 /* Check delay slot size requirements. */
8632 if (mips_macro_warning
.delay_slot_length
== 2)
8633 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8634 if (mips_macro_warning
.delay_slot_length
!= 0)
8636 if (mips_macro_warning
.delay_slot_length
8637 != mips_macro_warning
.first_insn_sizes
[0])
8638 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8639 if (mips_macro_warning
.delay_slot_length
8640 != mips_macro_warning
.first_insn_sizes
[1])
8641 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8644 /* Check instruction count requirements. */
8645 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8647 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8648 subtype
|= RELAX_SECOND_LONGER
;
8649 if (mips_opts
.warn_about_macros
)
8650 subtype
|= RELAX_NOMACRO
;
8651 if (mips_macro_warning
.delay_slot_p
)
8652 subtype
|= RELAX_DELAY_SLOT
;
8655 /* If both alternatives fail to fill a delay slot correctly,
8656 emit the warning now. */
8657 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8658 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8663 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8664 | RELAX_DELAY_SLOT_SIZE_FIRST
8665 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8666 msg
= macro_warning (s
);
8668 as_warn ("%s", msg
);
8672 /* If both implementations are longer than 1 instruction, then emit the
8674 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8679 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8680 msg
= macro_warning (s
);
8682 as_warn ("%s", msg
);
8686 /* If any flags still set, then one implementation might need a warning
8687 and the other either will need one of a different kind or none at all.
8688 Pass any remaining flags over to relaxation. */
8689 if (mips_macro_warning
.first_frag
!= NULL
)
8690 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8693 /* Instruction operand formats used in macros that vary between
8694 standard MIPS and microMIPS code. */
8696 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8697 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8698 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8699 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8700 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8701 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8702 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8703 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8705 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8706 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8707 : cop12_fmt[mips_opts.micromips])
8708 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8709 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8710 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8711 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8712 : mem12_fmt[mips_opts.micromips])
8713 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8714 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8715 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8717 /* Read a macro's relocation codes from *ARGS and store them in *R.
8718 The first argument in *ARGS will be either the code for a single
8719 relocation or -1 followed by the three codes that make up a
8720 composite relocation. */
8723 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8727 next
= va_arg (*args
, int);
8729 r
[0] = (bfd_reloc_code_real_type
) next
;
8732 for (i
= 0; i
< 3; i
++)
8733 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8734 /* This function is only used for 16-bit relocation fields.
8735 To make the macro code simpler, treat an unrelocated value
8736 in the same way as BFD_RELOC_LO16. */
8737 if (r
[0] == BFD_RELOC_UNUSED
)
8738 r
[0] = BFD_RELOC_LO16
;
8742 /* Build an instruction created by a macro expansion. This is passed
8743 a pointer to the count of instructions created so far, an
8744 expression, the name of the instruction to build, an operand format
8745 string, and corresponding arguments. */
8748 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8750 const struct mips_opcode
*mo
= NULL
;
8751 bfd_reloc_code_real_type r
[3];
8752 const struct mips_opcode
*amo
;
8753 const struct mips_operand
*operand
;
8754 struct hash_control
*hash
;
8755 struct mips_cl_insn insn
;
8759 va_start (args
, fmt
);
8761 if (mips_opts
.mips16
)
8763 mips16_macro_build (ep
, name
, fmt
, &args
);
8768 r
[0] = BFD_RELOC_UNUSED
;
8769 r
[1] = BFD_RELOC_UNUSED
;
8770 r
[2] = BFD_RELOC_UNUSED
;
8771 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8772 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8774 gas_assert (strcmp (name
, amo
->name
) == 0);
8778 /* Search until we get a match for NAME. It is assumed here that
8779 macros will never generate MDMX, MIPS-3D, or MT instructions.
8780 We try to match an instruction that fulfills the branch delay
8781 slot instruction length requirement (if any) of the previous
8782 instruction. While doing this we record the first instruction
8783 seen that matches all the other conditions and use it anyway
8784 if the requirement cannot be met; we will issue an appropriate
8785 warning later on. */
8786 if (strcmp (fmt
, amo
->args
) == 0
8787 && amo
->pinfo
!= INSN_MACRO
8788 && is_opcode_valid (amo
)
8789 && is_size_valid (amo
))
8791 if (is_delay_slot_valid (amo
))
8801 gas_assert (amo
->name
);
8803 while (strcmp (name
, amo
->name
) == 0);
8806 create_insn (&insn
, mo
);
8819 macro_read_relocs (&args
, r
);
8820 gas_assert (*r
== BFD_RELOC_GPREL16
8821 || *r
== BFD_RELOC_MIPS_HIGHER
8822 || *r
== BFD_RELOC_HI16_S
8823 || *r
== BFD_RELOC_LO16
8824 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8828 macro_read_relocs (&args
, r
);
8832 macro_read_relocs (&args
, r
);
8833 gas_assert (ep
!= NULL
8834 && (ep
->X_op
== O_constant
8835 || (ep
->X_op
== O_symbol
8836 && (*r
== BFD_RELOC_MIPS_HIGHEST
8837 || *r
== BFD_RELOC_HI16_S
8838 || *r
== BFD_RELOC_HI16
8839 || *r
== BFD_RELOC_GPREL16
8840 || *r
== BFD_RELOC_MIPS_GOT_HI16
8841 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8845 gas_assert (ep
!= NULL
);
8848 * This allows macro() to pass an immediate expression for
8849 * creating short branches without creating a symbol.
8851 * We don't allow branch relaxation for these branches, as
8852 * they should only appear in ".set nomacro" anyway.
8854 if (ep
->X_op
== O_constant
)
8856 /* For microMIPS we always use relocations for branches.
8857 So we should not resolve immediate values. */
8858 gas_assert (!mips_opts
.micromips
);
8860 if ((ep
->X_add_number
& 3) != 0)
8861 as_bad (_("branch to misaligned address (0x%lx)"),
8862 (unsigned long) ep
->X_add_number
);
8863 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8864 as_bad (_("branch address range overflow (0x%lx)"),
8865 (unsigned long) ep
->X_add_number
);
8866 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8870 *r
= BFD_RELOC_16_PCREL_S2
;
8874 gas_assert (ep
!= NULL
);
8875 *r
= BFD_RELOC_MIPS_JMP
;
8879 operand
= (mips_opts
.micromips
8880 ? decode_micromips_operand (fmt
)
8881 : decode_mips_operand (fmt
));
8885 uval
= va_arg (args
, int);
8886 if (operand
->type
== OP_CLO_CLZ_DEST
)
8887 uval
|= (uval
<< 5);
8888 insn_insert_operand (&insn
, operand
, uval
);
8890 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8896 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8898 append_insn (&insn
, ep
, r
, TRUE
);
8902 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8905 struct mips_opcode
*mo
;
8906 struct mips_cl_insn insn
;
8907 const struct mips_operand
*operand
;
8908 bfd_reloc_code_real_type r
[3]
8909 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8911 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8913 gas_assert (strcmp (name
, mo
->name
) == 0);
8915 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8918 gas_assert (mo
->name
);
8919 gas_assert (strcmp (name
, mo
->name
) == 0);
8922 create_insn (&insn
, mo
);
8959 gas_assert (ep
!= NULL
);
8961 if (ep
->X_op
!= O_constant
)
8962 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8963 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8965 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8967 *r
= BFD_RELOC_UNUSED
;
8973 operand
= decode_mips16_operand (c
, FALSE
);
8977 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8982 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8984 append_insn (&insn
, ep
, r
, TRUE
);
8988 * Generate a "jalr" instruction with a relocation hint to the called
8989 * function. This occurs in NewABI PIC code.
8992 macro_build_jalr (expressionS
*ep
, int cprestore
)
8994 static const bfd_reloc_code_real_type jalr_relocs
[2]
8995 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8996 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9000 if (MIPS_JALR_HINT_P (ep
))
9005 if (mips_opts
.micromips
)
9007 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9008 ? "jalr" : "jalrs");
9009 if (MIPS_JALR_HINT_P (ep
)
9011 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9012 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9014 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9017 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9018 if (MIPS_JALR_HINT_P (ep
))
9019 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9023 * Generate a "lui" instruction.
9026 macro_build_lui (expressionS
*ep
, int regnum
)
9028 gas_assert (! mips_opts
.mips16
);
9030 if (ep
->X_op
!= O_constant
)
9032 gas_assert (ep
->X_op
== O_symbol
);
9033 /* _gp_disp is a special case, used from s_cpload.
9034 __gnu_local_gp is used if mips_no_shared. */
9035 gas_assert (mips_pic
== NO_PIC
9037 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9038 || (! mips_in_shared
9039 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9040 "__gnu_local_gp") == 0));
9043 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9046 /* Generate a sequence of instructions to do a load or store from a constant
9047 offset off of a base register (breg) into/from a target register (treg),
9048 using AT if necessary. */
9050 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9051 int treg
, int breg
, int dbl
)
9053 gas_assert (ep
->X_op
== O_constant
);
9055 /* Sign-extending 32-bit constants makes their handling easier. */
9057 normalize_constant_expr (ep
);
9059 /* Right now, this routine can only handle signed 32-bit constants. */
9060 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9061 as_warn (_("operand overflow"));
9063 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9065 /* Signed 16-bit offset will fit in the op. Easy! */
9066 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9070 /* 32-bit offset, need multiple instructions and AT, like:
9071 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9072 addu $tempreg,$tempreg,$breg
9073 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9074 to handle the complete offset. */
9075 macro_build_lui (ep
, AT
);
9076 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9077 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9080 as_bad (_("macro used $at after \".set noat\""));
9085 * Generates code to set the $at register to true (one)
9086 * if reg is less than the immediate expression.
9089 set_at (int reg
, int unsignedp
)
9091 if (imm_expr
.X_add_number
>= -0x8000
9092 && imm_expr
.X_add_number
< 0x8000)
9093 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9094 AT
, reg
, BFD_RELOC_LO16
);
9097 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9098 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9102 /* Count the leading zeroes by performing a binary chop. This is a
9103 bulky bit of source, but performance is a LOT better for the
9104 majority of values than a simple loop to count the bits:
9105 for (lcnt = 0; (lcnt < 32); lcnt++)
9106 if ((v) & (1 << (31 - lcnt)))
9108 However it is not code size friendly, and the gain will drop a bit
9109 on certain cached systems.
9111 #define COUNT_TOP_ZEROES(v) \
9112 (((v) & ~0xffff) == 0 \
9113 ? ((v) & ~0xff) == 0 \
9114 ? ((v) & ~0xf) == 0 \
9115 ? ((v) & ~0x3) == 0 \
9116 ? ((v) & ~0x1) == 0 \
9121 : ((v) & ~0x7) == 0 \
9124 : ((v) & ~0x3f) == 0 \
9125 ? ((v) & ~0x1f) == 0 \
9128 : ((v) & ~0x7f) == 0 \
9131 : ((v) & ~0xfff) == 0 \
9132 ? ((v) & ~0x3ff) == 0 \
9133 ? ((v) & ~0x1ff) == 0 \
9136 : ((v) & ~0x7ff) == 0 \
9139 : ((v) & ~0x3fff) == 0 \
9140 ? ((v) & ~0x1fff) == 0 \
9143 : ((v) & ~0x7fff) == 0 \
9146 : ((v) & ~0xffffff) == 0 \
9147 ? ((v) & ~0xfffff) == 0 \
9148 ? ((v) & ~0x3ffff) == 0 \
9149 ? ((v) & ~0x1ffff) == 0 \
9152 : ((v) & ~0x7ffff) == 0 \
9155 : ((v) & ~0x3fffff) == 0 \
9156 ? ((v) & ~0x1fffff) == 0 \
9159 : ((v) & ~0x7fffff) == 0 \
9162 : ((v) & ~0xfffffff) == 0 \
9163 ? ((v) & ~0x3ffffff) == 0 \
9164 ? ((v) & ~0x1ffffff) == 0 \
9167 : ((v) & ~0x7ffffff) == 0 \
9170 : ((v) & ~0x3fffffff) == 0 \
9171 ? ((v) & ~0x1fffffff) == 0 \
9174 : ((v) & ~0x7fffffff) == 0 \
9179 * This routine generates the least number of instructions necessary to load
9180 * an absolute expression value into a register.
9183 load_register (int reg
, expressionS
*ep
, int dbl
)
9186 expressionS hi32
, lo32
;
9188 if (ep
->X_op
!= O_big
)
9190 gas_assert (ep
->X_op
== O_constant
);
9192 /* Sign-extending 32-bit constants makes their handling easier. */
9194 normalize_constant_expr (ep
);
9196 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9198 /* We can handle 16 bit signed values with an addiu to
9199 $zero. No need to ever use daddiu here, since $zero and
9200 the result are always correct in 32 bit mode. */
9201 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9204 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9206 /* We can handle 16 bit unsigned values with an ori to
9208 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9211 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9213 /* 32 bit values require an lui. */
9214 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9215 if ((ep
->X_add_number
& 0xffff) != 0)
9216 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9221 /* The value is larger than 32 bits. */
9223 if (!dbl
|| GPR_SIZE
== 32)
9227 sprintf_vma (value
, ep
->X_add_number
);
9228 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9229 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9233 if (ep
->X_op
!= O_big
)
9236 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9237 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9238 hi32
.X_add_number
&= 0xffffffff;
9240 lo32
.X_add_number
&= 0xffffffff;
9244 gas_assert (ep
->X_add_number
> 2);
9245 if (ep
->X_add_number
== 3)
9246 generic_bignum
[3] = 0;
9247 else if (ep
->X_add_number
> 4)
9248 as_bad (_("number larger than 64 bits"));
9249 lo32
.X_op
= O_constant
;
9250 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9251 hi32
.X_op
= O_constant
;
9252 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9255 if (hi32
.X_add_number
== 0)
9260 unsigned long hi
, lo
;
9262 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9264 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9266 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9269 if (lo32
.X_add_number
& 0x80000000)
9271 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9272 if (lo32
.X_add_number
& 0xffff)
9273 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9278 /* Check for 16bit shifted constant. We know that hi32 is
9279 non-zero, so start the mask on the first bit of the hi32
9284 unsigned long himask
, lomask
;
9288 himask
= 0xffff >> (32 - shift
);
9289 lomask
= (0xffff << shift
) & 0xffffffff;
9293 himask
= 0xffff << (shift
- 32);
9296 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9297 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9301 tmp
.X_op
= O_constant
;
9303 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9304 | (lo32
.X_add_number
>> shift
));
9306 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9307 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9308 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9309 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9314 while (shift
<= (64 - 16));
9316 /* Find the bit number of the lowest one bit, and store the
9317 shifted value in hi/lo. */
9318 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9319 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9323 while ((lo
& 1) == 0)
9328 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9334 while ((hi
& 1) == 0)
9343 /* Optimize if the shifted value is a (power of 2) - 1. */
9344 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9345 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9347 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9352 /* This instruction will set the register to be all
9354 tmp
.X_op
= O_constant
;
9355 tmp
.X_add_number
= (offsetT
) -1;
9356 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9360 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9361 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9363 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9364 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9369 /* Sign extend hi32 before calling load_register, because we can
9370 generally get better code when we load a sign extended value. */
9371 if ((hi32
.X_add_number
& 0x80000000) != 0)
9372 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9373 load_register (reg
, &hi32
, 0);
9376 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9380 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9388 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9390 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9391 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9397 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9401 mid16
.X_add_number
>>= 16;
9402 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9403 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9406 if ((lo32
.X_add_number
& 0xffff) != 0)
9407 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9411 load_delay_nop (void)
9413 if (!gpr_interlocks
)
9414 macro_build (NULL
, "nop", "");
9417 /* Load an address into a register. */
9420 load_address (int reg
, expressionS
*ep
, int *used_at
)
9422 if (ep
->X_op
!= O_constant
9423 && ep
->X_op
!= O_symbol
)
9425 as_bad (_("expression too complex"));
9426 ep
->X_op
= O_constant
;
9429 if (ep
->X_op
== O_constant
)
9431 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9435 if (mips_pic
== NO_PIC
)
9437 /* If this is a reference to a GP relative symbol, we want
9438 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9440 lui $reg,<sym> (BFD_RELOC_HI16_S)
9441 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9442 If we have an addend, we always use the latter form.
9444 With 64bit address space and a usable $at we want
9445 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9446 lui $at,<sym> (BFD_RELOC_HI16_S)
9447 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9448 daddiu $at,<sym> (BFD_RELOC_LO16)
9452 If $at is already in use, we use a path which is suboptimal
9453 on superscalar processors.
9454 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9455 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9457 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9459 daddiu $reg,<sym> (BFD_RELOC_LO16)
9461 For GP relative symbols in 64bit address space we can use
9462 the same sequence as in 32bit address space. */
9463 if (HAVE_64BIT_SYMBOLS
)
9465 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9466 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9468 relax_start (ep
->X_add_symbol
);
9469 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9470 mips_gp_register
, BFD_RELOC_GPREL16
);
9474 if (*used_at
== 0 && mips_opts
.at
)
9476 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9477 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9478 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9479 BFD_RELOC_MIPS_HIGHER
);
9480 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9481 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9482 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9487 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9488 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9489 BFD_RELOC_MIPS_HIGHER
);
9490 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9491 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9492 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9493 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9496 if (mips_relax
.sequence
)
9501 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9502 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9504 relax_start (ep
->X_add_symbol
);
9505 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9506 mips_gp_register
, BFD_RELOC_GPREL16
);
9509 macro_build_lui (ep
, reg
);
9510 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9511 reg
, reg
, BFD_RELOC_LO16
);
9512 if (mips_relax
.sequence
)
9516 else if (!mips_big_got
)
9520 /* If this is a reference to an external symbol, we want
9521 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9523 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9525 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9526 If there is a constant, it must be added in after.
9528 If we have NewABI, we want
9529 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9530 unless we're referencing a global symbol with a non-zero
9531 offset, in which case cst must be added separately. */
9534 if (ep
->X_add_number
)
9536 ex
.X_add_number
= ep
->X_add_number
;
9537 ep
->X_add_number
= 0;
9538 relax_start (ep
->X_add_symbol
);
9539 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9540 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9541 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9542 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9543 ex
.X_op
= O_constant
;
9544 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9545 reg
, reg
, BFD_RELOC_LO16
);
9546 ep
->X_add_number
= ex
.X_add_number
;
9549 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9550 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9551 if (mips_relax
.sequence
)
9556 ex
.X_add_number
= ep
->X_add_number
;
9557 ep
->X_add_number
= 0;
9558 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9559 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9561 relax_start (ep
->X_add_symbol
);
9563 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9567 if (ex
.X_add_number
!= 0)
9569 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9570 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9571 ex
.X_op
= O_constant
;
9572 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9573 reg
, reg
, BFD_RELOC_LO16
);
9577 else if (mips_big_got
)
9581 /* This is the large GOT case. If this is a reference to an
9582 external symbol, we want
9583 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9585 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9587 Otherwise, for a reference to a local symbol in old ABI, we want
9588 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9590 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9591 If there is a constant, it must be added in after.
9593 In the NewABI, for local symbols, with or without offsets, we want:
9594 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9595 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9599 ex
.X_add_number
= ep
->X_add_number
;
9600 ep
->X_add_number
= 0;
9601 relax_start (ep
->X_add_symbol
);
9602 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9603 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9604 reg
, reg
, mips_gp_register
);
9605 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9606 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9607 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9609 else if (ex
.X_add_number
)
9611 ex
.X_op
= O_constant
;
9612 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9616 ep
->X_add_number
= ex
.X_add_number
;
9618 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9619 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9620 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9621 BFD_RELOC_MIPS_GOT_OFST
);
9626 ex
.X_add_number
= ep
->X_add_number
;
9627 ep
->X_add_number
= 0;
9628 relax_start (ep
->X_add_symbol
);
9629 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9630 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9631 reg
, reg
, mips_gp_register
);
9632 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9633 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9635 if (reg_needs_delay (mips_gp_register
))
9637 /* We need a nop before loading from $gp. This special
9638 check is required because the lui which starts the main
9639 instruction stream does not refer to $gp, and so will not
9640 insert the nop which may be required. */
9641 macro_build (NULL
, "nop", "");
9643 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9644 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9646 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9650 if (ex
.X_add_number
!= 0)
9652 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9653 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9654 ex
.X_op
= O_constant
;
9655 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9663 if (!mips_opts
.at
&& *used_at
== 1)
9664 as_bad (_("macro used $at after \".set noat\""));
9667 /* Move the contents of register SOURCE into register DEST. */
9670 move_register (int dest
, int source
)
9672 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9673 instruction specifically requires a 32-bit one. */
9674 if (mips_opts
.micromips
9675 && !mips_opts
.insn32
9676 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9677 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9679 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9682 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9683 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9684 The two alternatives are:
9686 Global symbol Local symbol
9687 ------------- ------------
9688 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9690 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9692 load_got_offset emits the first instruction and add_got_offset
9693 emits the second for a 16-bit offset or add_got_offset_hilo emits
9694 a sequence to add a 32-bit offset using a scratch register. */
9697 load_got_offset (int dest
, expressionS
*local
)
9702 global
.X_add_number
= 0;
9704 relax_start (local
->X_add_symbol
);
9705 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9706 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9708 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9709 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9714 add_got_offset (int dest
, expressionS
*local
)
9718 global
.X_op
= O_constant
;
9719 global
.X_op_symbol
= NULL
;
9720 global
.X_add_symbol
= NULL
;
9721 global
.X_add_number
= local
->X_add_number
;
9723 relax_start (local
->X_add_symbol
);
9724 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9725 dest
, dest
, BFD_RELOC_LO16
);
9727 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9732 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9735 int hold_mips_optimize
;
9737 global
.X_op
= O_constant
;
9738 global
.X_op_symbol
= NULL
;
9739 global
.X_add_symbol
= NULL
;
9740 global
.X_add_number
= local
->X_add_number
;
9742 relax_start (local
->X_add_symbol
);
9743 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9745 /* Set mips_optimize around the lui instruction to avoid
9746 inserting an unnecessary nop after the lw. */
9747 hold_mips_optimize
= mips_optimize
;
9749 macro_build_lui (&global
, tmp
);
9750 mips_optimize
= hold_mips_optimize
;
9751 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9754 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9757 /* Emit a sequence of instructions to emulate a branch likely operation.
9758 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9759 is its complementing branch with the original condition negated.
9760 CALL is set if the original branch specified the link operation.
9761 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9763 Code like this is produced in the noreorder mode:
9768 delay slot (executed only if branch taken)
9776 delay slot (executed only if branch taken)
9779 In the reorder mode the delay slot would be filled with a nop anyway,
9780 so code produced is simply:
9785 This function is used when producing code for the microMIPS ASE that
9786 does not implement branch likely instructions in hardware. */
9789 macro_build_branch_likely (const char *br
, const char *brneg
,
9790 int call
, expressionS
*ep
, const char *fmt
,
9791 unsigned int sreg
, unsigned int treg
)
9793 int noreorder
= mips_opts
.noreorder
;
9796 gas_assert (mips_opts
.micromips
);
9800 micromips_label_expr (&expr1
);
9801 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9802 macro_build (NULL
, "nop", "");
9803 macro_build (ep
, call
? "bal" : "b", "p");
9805 /* Set to true so that append_insn adds a label. */
9806 emit_branch_likely_macro
= TRUE
;
9810 macro_build (ep
, br
, fmt
, sreg
, treg
);
9811 macro_build (NULL
, "nop", "");
9816 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9817 the condition code tested. EP specifies the branch target. */
9820 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9847 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9850 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9851 the register tested. EP specifies the branch target. */
9854 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9856 const char *brneg
= NULL
;
9866 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9870 gas_assert (mips_opts
.micromips
);
9871 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9879 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9886 br
= mips_opts
.micromips
? "blez" : "blezl";
9893 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9897 gas_assert (mips_opts
.micromips
);
9898 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9905 if (mips_opts
.micromips
&& brneg
)
9906 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9908 macro_build (ep
, br
, "s,p", sreg
);
9911 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9912 TREG as the registers tested. EP specifies the branch target. */
9915 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9916 unsigned int sreg
, unsigned int treg
)
9918 const char *brneg
= NULL
;
9930 br
= mips_opts
.micromips
? "beq" : "beql";
9939 br
= mips_opts
.micromips
? "bne" : "bnel";
9945 if (mips_opts
.micromips
&& brneg
)
9946 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9948 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9951 /* Return the high part that should be loaded in order to make the low
9952 part of VALUE accessible using an offset of OFFBITS bits. */
9955 offset_high_part (offsetT value
, unsigned int offbits
)
9962 bias
= 1 << (offbits
- 1);
9963 low_mask
= bias
* 2 - 1;
9964 return (value
+ bias
) & ~low_mask
;
9967 /* Return true if the value stored in offset_expr and offset_reloc
9968 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9969 amount that the caller wants to add without inducing overflow
9970 and ALIGN is the known alignment of the value in bytes. */
9973 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9977 /* Accept any relocation operator if overflow isn't a concern. */
9978 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9981 /* These relocations are guaranteed not to overflow in correct links. */
9982 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9983 || gprel16_reloc_p (*offset_reloc
))
9986 if (offset_expr
.X_op
== O_constant
9987 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9988 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9995 * This routine implements the seemingly endless macro or synthesized
9996 * instructions and addressing modes in the mips assembly language. Many
9997 * of these macros are simple and are similar to each other. These could
9998 * probably be handled by some kind of table or grammar approach instead of
9999 * this verbose method. Others are not simple macros but are more like
10000 * optimizing code generation.
10001 * One interesting optimization is when several store macros appear
10002 * consecutively that would load AT with the upper half of the same address.
10003 * The ensuing load upper instructions are omitted. This implies some kind
10004 * of global optimization. We currently only optimize within a single macro.
10005 * For many of the load and store macros if the address is specified as a
10006 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10007 * first load register 'at' with zero and use it as the base register. The
10008 * mips assembler simply uses register $zero. Just one tiny optimization
10012 macro (struct mips_cl_insn
*ip
, char *str
)
10014 const struct mips_operand_array
*operands
;
10015 unsigned int breg
, i
;
10016 unsigned int tempreg
;
10019 expressionS label_expr
;
10034 bfd_boolean large_offset
;
10036 int hold_mips_optimize
;
10037 unsigned int align
;
10038 unsigned int op
[MAX_OPERANDS
];
10040 gas_assert (! mips_opts
.mips16
);
10042 operands
= insn_operands (ip
);
10043 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10044 if (operands
->operand
[i
])
10045 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10049 mask
= ip
->insn_mo
->mask
;
10051 label_expr
.X_op
= O_constant
;
10052 label_expr
.X_op_symbol
= NULL
;
10053 label_expr
.X_add_symbol
= NULL
;
10054 label_expr
.X_add_number
= 0;
10056 expr1
.X_op
= O_constant
;
10057 expr1
.X_op_symbol
= NULL
;
10058 expr1
.X_add_symbol
= NULL
;
10059 expr1
.X_add_number
= 1;
10066 /* Fall through. */
10074 start_noreorder ();
10076 if (mips_opts
.micromips
)
10077 micromips_label_expr (&label_expr
);
10079 label_expr
.X_add_number
= 8;
10080 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10081 if (op
[0] == op
[1])
10082 macro_build (NULL
, "nop", "");
10084 move_register (op
[0], op
[1]);
10085 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10086 if (mips_opts
.micromips
)
10087 micromips_add_label ();
10104 if (!mips_opts
.micromips
)
10106 if (imm_expr
.X_add_number
>= -0x200
10107 && imm_expr
.X_add_number
< 0x200)
10109 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10110 (int) imm_expr
.X_add_number
);
10119 if (imm_expr
.X_add_number
>= -0x8000
10120 && imm_expr
.X_add_number
< 0x8000)
10122 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10127 load_register (AT
, &imm_expr
, dbl
);
10128 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10147 if (imm_expr
.X_add_number
>= 0
10148 && imm_expr
.X_add_number
< 0x10000)
10150 if (mask
!= M_NOR_I
)
10151 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10154 macro_build (&imm_expr
, "ori", "t,r,i",
10155 op
[0], op
[1], BFD_RELOC_LO16
);
10156 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10162 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10163 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10167 switch (imm_expr
.X_add_number
)
10170 macro_build (NULL
, "nop", "");
10173 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10177 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10178 (int) imm_expr
.X_add_number
);
10181 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10182 (unsigned long) imm_expr
.X_add_number
);
10191 gas_assert (mips_opts
.micromips
);
10192 macro_build_branch_ccl (mask
, &offset_expr
,
10193 EXTRACT_OPERAND (1, BCC
, *ip
));
10200 if (imm_expr
.X_add_number
== 0)
10206 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10208 /* Fall through. */
10211 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10216 /* Fall through. */
10219 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10220 else if (op
[0] == 0)
10221 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10225 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10226 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10227 &offset_expr
, AT
, ZERO
);
10237 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10242 /* Fall through. */
10244 /* Check for > max integer. */
10245 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10248 /* Result is always false. */
10250 macro_build (NULL
, "nop", "");
10252 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10255 ++imm_expr
.X_add_number
;
10259 if (mask
== M_BGEL_I
)
10261 if (imm_expr
.X_add_number
== 0)
10263 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10264 &offset_expr
, op
[0]);
10267 if (imm_expr
.X_add_number
== 1)
10269 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10270 &offset_expr
, op
[0]);
10273 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10276 /* result is always true */
10277 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10278 macro_build (&offset_expr
, "b", "p");
10283 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10284 &offset_expr
, AT
, ZERO
);
10289 /* Fall through. */
10293 else if (op
[0] == 0)
10294 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10295 &offset_expr
, ZERO
, op
[1]);
10299 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10300 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10301 &offset_expr
, AT
, ZERO
);
10307 /* Fall through. */
10311 && imm_expr
.X_add_number
== -1))
10313 ++imm_expr
.X_add_number
;
10317 if (mask
== M_BGEUL_I
)
10319 if (imm_expr
.X_add_number
== 0)
10321 else if (imm_expr
.X_add_number
== 1)
10322 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10323 &offset_expr
, op
[0], ZERO
);
10328 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10329 &offset_expr
, AT
, ZERO
);
10335 /* Fall through. */
10338 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10339 else if (op
[0] == 0)
10340 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10344 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10345 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10346 &offset_expr
, AT
, ZERO
);
10352 /* Fall through. */
10355 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10356 &offset_expr
, op
[0], ZERO
);
10357 else if (op
[0] == 0)
10362 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10363 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10364 &offset_expr
, AT
, ZERO
);
10370 /* Fall through. */
10373 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10374 else if (op
[0] == 0)
10375 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10379 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10380 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10381 &offset_expr
, AT
, ZERO
);
10387 /* Fall through. */
10389 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10391 ++imm_expr
.X_add_number
;
10395 if (mask
== M_BLTL_I
)
10397 if (imm_expr
.X_add_number
== 0)
10398 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10399 else if (imm_expr
.X_add_number
== 1)
10400 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10405 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10406 &offset_expr
, AT
, ZERO
);
10412 /* Fall through. */
10415 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10416 &offset_expr
, op
[0], ZERO
);
10417 else if (op
[0] == 0)
10422 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10423 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10424 &offset_expr
, AT
, ZERO
);
10430 /* Fall through. */
10434 && imm_expr
.X_add_number
== -1))
10436 ++imm_expr
.X_add_number
;
10440 if (mask
== M_BLTUL_I
)
10442 if (imm_expr
.X_add_number
== 0)
10444 else if (imm_expr
.X_add_number
== 1)
10445 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10446 &offset_expr
, op
[0], ZERO
);
10451 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10452 &offset_expr
, AT
, ZERO
);
10458 /* Fall through. */
10461 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10462 else if (op
[0] == 0)
10463 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10467 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10468 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10469 &offset_expr
, AT
, ZERO
);
10475 /* Fall through. */
10479 else if (op
[0] == 0)
10480 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10481 &offset_expr
, ZERO
, op
[1]);
10485 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10486 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10487 &offset_expr
, AT
, ZERO
);
10493 /* Fall through. */
10499 /* Fall through. */
10505 as_warn (_("divide by zero"));
10507 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10509 macro_build (NULL
, "break", BRK_FMT
, 7);
10513 start_noreorder ();
10516 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10517 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10521 if (mips_opts
.micromips
)
10522 micromips_label_expr (&label_expr
);
10524 label_expr
.X_add_number
= 8;
10525 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10526 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10527 macro_build (NULL
, "break", BRK_FMT
, 7);
10528 if (mips_opts
.micromips
)
10529 micromips_add_label ();
10531 expr1
.X_add_number
= -1;
10533 load_register (AT
, &expr1
, dbl
);
10534 if (mips_opts
.micromips
)
10535 micromips_label_expr (&label_expr
);
10537 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10538 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10541 expr1
.X_add_number
= 1;
10542 load_register (AT
, &expr1
, dbl
);
10543 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10547 expr1
.X_add_number
= 0x80000000;
10548 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10552 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10553 /* We want to close the noreorder block as soon as possible, so
10554 that later insns are available for delay slot filling. */
10559 if (mips_opts
.micromips
)
10560 micromips_label_expr (&label_expr
);
10562 label_expr
.X_add_number
= 8;
10563 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10564 macro_build (NULL
, "nop", "");
10566 /* We want to close the noreorder block as soon as possible, so
10567 that later insns are available for delay slot filling. */
10570 macro_build (NULL
, "break", BRK_FMT
, 6);
10572 if (mips_opts
.micromips
)
10573 micromips_add_label ();
10574 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10613 if (imm_expr
.X_add_number
== 0)
10615 as_warn (_("divide by zero"));
10617 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10619 macro_build (NULL
, "break", BRK_FMT
, 7);
10622 if (imm_expr
.X_add_number
== 1)
10624 if (strcmp (s2
, "mflo") == 0)
10625 move_register (op
[0], op
[1]);
10627 move_register (op
[0], ZERO
);
10630 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10632 if (strcmp (s2
, "mflo") == 0)
10633 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10635 move_register (op
[0], ZERO
);
10640 load_register (AT
, &imm_expr
, dbl
);
10641 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10642 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10661 start_noreorder ();
10664 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10665 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10666 /* We want to close the noreorder block as soon as possible, so
10667 that later insns are available for delay slot filling. */
10672 if (mips_opts
.micromips
)
10673 micromips_label_expr (&label_expr
);
10675 label_expr
.X_add_number
= 8;
10676 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10677 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10679 /* We want to close the noreorder block as soon as possible, so
10680 that later insns are available for delay slot filling. */
10682 macro_build (NULL
, "break", BRK_FMT
, 7);
10683 if (mips_opts
.micromips
)
10684 micromips_add_label ();
10686 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10691 /* Fall through. */
10697 /* Fall through. */
10700 /* Load the address of a symbol into a register. If breg is not
10701 zero, we then add a base register to it. */
10704 if (dbl
&& GPR_SIZE
== 32)
10705 as_warn (_("dla used to load 32-bit register; recommend using la "
10708 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10709 as_warn (_("la used to load 64-bit address; recommend using dla "
10712 if (small_offset_p (0, align
, 16))
10714 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10715 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10719 if (mips_opts
.at
&& (op
[0] == breg
))
10727 if (offset_expr
.X_op
!= O_symbol
10728 && offset_expr
.X_op
!= O_constant
)
10730 as_bad (_("expression too complex"));
10731 offset_expr
.X_op
= O_constant
;
10734 if (offset_expr
.X_op
== O_constant
)
10735 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10736 else if (mips_pic
== NO_PIC
)
10738 /* If this is a reference to a GP relative symbol, we want
10739 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10741 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10742 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10743 If we have a constant, we need two instructions anyhow,
10744 so we may as well always use the latter form.
10746 With 64bit address space and a usable $at we want
10747 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10748 lui $at,<sym> (BFD_RELOC_HI16_S)
10749 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10750 daddiu $at,<sym> (BFD_RELOC_LO16)
10752 daddu $tempreg,$tempreg,$at
10754 If $at is already in use, we use a path which is suboptimal
10755 on superscalar processors.
10756 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10757 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10759 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10761 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10763 For GP relative symbols in 64bit address space we can use
10764 the same sequence as in 32bit address space. */
10765 if (HAVE_64BIT_SYMBOLS
)
10767 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10768 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10770 relax_start (offset_expr
.X_add_symbol
);
10771 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10772 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10776 if (used_at
== 0 && mips_opts
.at
)
10778 macro_build (&offset_expr
, "lui", LUI_FMT
,
10779 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10780 macro_build (&offset_expr
, "lui", LUI_FMT
,
10781 AT
, BFD_RELOC_HI16_S
);
10782 macro_build (&offset_expr
, "daddiu", "t,r,j",
10783 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10784 macro_build (&offset_expr
, "daddiu", "t,r,j",
10785 AT
, AT
, BFD_RELOC_LO16
);
10786 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10787 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10792 macro_build (&offset_expr
, "lui", LUI_FMT
,
10793 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10794 macro_build (&offset_expr
, "daddiu", "t,r,j",
10795 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10796 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10797 macro_build (&offset_expr
, "daddiu", "t,r,j",
10798 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10799 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10800 macro_build (&offset_expr
, "daddiu", "t,r,j",
10801 tempreg
, tempreg
, BFD_RELOC_LO16
);
10804 if (mips_relax
.sequence
)
10809 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10810 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10812 relax_start (offset_expr
.X_add_symbol
);
10813 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10814 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10817 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10818 as_bad (_("offset too large"));
10819 macro_build_lui (&offset_expr
, tempreg
);
10820 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10821 tempreg
, tempreg
, BFD_RELOC_LO16
);
10822 if (mips_relax
.sequence
)
10826 else if (!mips_big_got
&& !HAVE_NEWABI
)
10828 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10830 /* If this is a reference to an external symbol, and there
10831 is no constant, we want
10832 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10833 or for lca or if tempreg is PIC_CALL_REG
10834 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10835 For a local symbol, we want
10836 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10838 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10840 If we have a small constant, and this is a reference to
10841 an external symbol, we want
10842 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10844 addiu $tempreg,$tempreg,<constant>
10845 For a local symbol, we want the same instruction
10846 sequence, but we output a BFD_RELOC_LO16 reloc on the
10849 If we have a large constant, and this is a reference to
10850 an external symbol, we want
10851 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10852 lui $at,<hiconstant>
10853 addiu $at,$at,<loconstant>
10854 addu $tempreg,$tempreg,$at
10855 For a local symbol, we want the same instruction
10856 sequence, but we output a BFD_RELOC_LO16 reloc on the
10860 if (offset_expr
.X_add_number
== 0)
10862 if (mips_pic
== SVR4_PIC
10864 && (call
|| tempreg
== PIC_CALL_REG
))
10865 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10867 relax_start (offset_expr
.X_add_symbol
);
10868 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10869 lw_reloc_type
, mips_gp_register
);
10872 /* We're going to put in an addu instruction using
10873 tempreg, so we may as well insert the nop right
10878 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10879 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10881 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10882 tempreg
, tempreg
, BFD_RELOC_LO16
);
10884 /* FIXME: If breg == 0, and the next instruction uses
10885 $tempreg, then if this variant case is used an extra
10886 nop will be generated. */
10888 else if (offset_expr
.X_add_number
>= -0x8000
10889 && offset_expr
.X_add_number
< 0x8000)
10891 load_got_offset (tempreg
, &offset_expr
);
10893 add_got_offset (tempreg
, &offset_expr
);
10897 expr1
.X_add_number
= offset_expr
.X_add_number
;
10898 offset_expr
.X_add_number
=
10899 SEXT_16BIT (offset_expr
.X_add_number
);
10900 load_got_offset (tempreg
, &offset_expr
);
10901 offset_expr
.X_add_number
= expr1
.X_add_number
;
10902 /* If we are going to add in a base register, and the
10903 target register and the base register are the same,
10904 then we are using AT as a temporary register. Since
10905 we want to load the constant into AT, we add our
10906 current AT (from the global offset table) and the
10907 register into the register now, and pretend we were
10908 not using a base register. */
10912 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10917 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10921 else if (!mips_big_got
&& HAVE_NEWABI
)
10923 int add_breg_early
= 0;
10925 /* If this is a reference to an external, and there is no
10926 constant, or local symbol (*), with or without a
10928 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10929 or for lca or if tempreg is PIC_CALL_REG
10930 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10932 If we have a small constant, and this is a reference to
10933 an external symbol, we want
10934 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10935 addiu $tempreg,$tempreg,<constant>
10937 If we have a large constant, and this is a reference to
10938 an external symbol, we want
10939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10940 lui $at,<hiconstant>
10941 addiu $at,$at,<loconstant>
10942 addu $tempreg,$tempreg,$at
10944 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10945 local symbols, even though it introduces an additional
10948 if (offset_expr
.X_add_number
)
10950 expr1
.X_add_number
= offset_expr
.X_add_number
;
10951 offset_expr
.X_add_number
= 0;
10953 relax_start (offset_expr
.X_add_symbol
);
10954 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10955 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10957 if (expr1
.X_add_number
>= -0x8000
10958 && expr1
.X_add_number
< 0x8000)
10960 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10961 tempreg
, tempreg
, BFD_RELOC_LO16
);
10963 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10967 /* If we are going to add in a base register, and the
10968 target register and the base register are the same,
10969 then we are using AT as a temporary register. Since
10970 we want to load the constant into AT, we add our
10971 current AT (from the global offset table) and the
10972 register into the register now, and pretend we were
10973 not using a base register. */
10978 gas_assert (tempreg
== AT
);
10979 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10982 add_breg_early
= 1;
10985 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10986 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10992 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10995 offset_expr
.X_add_number
= expr1
.X_add_number
;
10997 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10998 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10999 if (add_breg_early
)
11001 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11002 op
[0], tempreg
, breg
);
11008 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11010 relax_start (offset_expr
.X_add_symbol
);
11011 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11012 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11014 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11015 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11020 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11021 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11024 else if (mips_big_got
&& !HAVE_NEWABI
)
11027 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11028 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11029 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11031 /* This is the large GOT case. If this is a reference to an
11032 external symbol, and there is no constant, we want
11033 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11034 addu $tempreg,$tempreg,$gp
11035 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11036 or for lca or if tempreg is PIC_CALL_REG
11037 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11038 addu $tempreg,$tempreg,$gp
11039 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11040 For a local symbol, we want
11041 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11043 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11045 If we have a small constant, and this is a reference to
11046 an external symbol, we want
11047 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11048 addu $tempreg,$tempreg,$gp
11049 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11051 addiu $tempreg,$tempreg,<constant>
11052 For a local symbol, we want
11053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11055 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11057 If we have a large constant, and this is a reference to
11058 an external symbol, we want
11059 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11060 addu $tempreg,$tempreg,$gp
11061 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11062 lui $at,<hiconstant>
11063 addiu $at,$at,<loconstant>
11064 addu $tempreg,$tempreg,$at
11065 For a local symbol, we want
11066 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11067 lui $at,<hiconstant>
11068 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11069 addu $tempreg,$tempreg,$at
11072 expr1
.X_add_number
= offset_expr
.X_add_number
;
11073 offset_expr
.X_add_number
= 0;
11074 relax_start (offset_expr
.X_add_symbol
);
11075 gpdelay
= reg_needs_delay (mips_gp_register
);
11076 if (expr1
.X_add_number
== 0 && breg
== 0
11077 && (call
|| tempreg
== PIC_CALL_REG
))
11079 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11080 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11082 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11083 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11084 tempreg
, tempreg
, mips_gp_register
);
11085 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11086 tempreg
, lw_reloc_type
, tempreg
);
11087 if (expr1
.X_add_number
== 0)
11091 /* We're going to put in an addu instruction using
11092 tempreg, so we may as well insert the nop right
11097 else if (expr1
.X_add_number
>= -0x8000
11098 && expr1
.X_add_number
< 0x8000)
11101 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11102 tempreg
, tempreg
, BFD_RELOC_LO16
);
11108 /* If we are going to add in a base register, and the
11109 target register and the base register are the same,
11110 then we are using AT as a temporary register. Since
11111 we want to load the constant into AT, we add our
11112 current AT (from the global offset table) and the
11113 register into the register now, and pretend we were
11114 not using a base register. */
11119 gas_assert (tempreg
== AT
);
11121 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11126 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11127 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11131 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11136 /* This is needed because this instruction uses $gp, but
11137 the first instruction on the main stream does not. */
11138 macro_build (NULL
, "nop", "");
11141 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11142 local_reloc_type
, mips_gp_register
);
11143 if (expr1
.X_add_number
>= -0x8000
11144 && expr1
.X_add_number
< 0x8000)
11147 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11148 tempreg
, tempreg
, BFD_RELOC_LO16
);
11149 /* FIXME: If add_number is 0, and there was no base
11150 register, the external symbol case ended with a load,
11151 so if the symbol turns out to not be external, and
11152 the next instruction uses tempreg, an unnecessary nop
11153 will be inserted. */
11159 /* We must add in the base register now, as in the
11160 external symbol case. */
11161 gas_assert (tempreg
== AT
);
11163 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11166 /* We set breg to 0 because we have arranged to add
11167 it in in both cases. */
11171 macro_build_lui (&expr1
, AT
);
11172 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11173 AT
, AT
, BFD_RELOC_LO16
);
11174 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11175 tempreg
, tempreg
, AT
);
11180 else if (mips_big_got
&& HAVE_NEWABI
)
11182 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11183 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11184 int add_breg_early
= 0;
11186 /* This is the large GOT case. If this is a reference to an
11187 external symbol, and there is no constant, we want
11188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11189 add $tempreg,$tempreg,$gp
11190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11191 or for lca or if tempreg is PIC_CALL_REG
11192 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11193 add $tempreg,$tempreg,$gp
11194 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11196 If we have a small constant, and this is a reference to
11197 an external symbol, we want
11198 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11199 add $tempreg,$tempreg,$gp
11200 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11201 addi $tempreg,$tempreg,<constant>
11203 If we have a large constant, and this is a reference to
11204 an external symbol, we want
11205 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11206 addu $tempreg,$tempreg,$gp
11207 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11208 lui $at,<hiconstant>
11209 addi $at,$at,<loconstant>
11210 add $tempreg,$tempreg,$at
11212 If we have NewABI, and we know it's a local symbol, we want
11213 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11214 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11215 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11217 relax_start (offset_expr
.X_add_symbol
);
11219 expr1
.X_add_number
= offset_expr
.X_add_number
;
11220 offset_expr
.X_add_number
= 0;
11222 if (expr1
.X_add_number
== 0 && breg
== 0
11223 && (call
|| tempreg
== PIC_CALL_REG
))
11225 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11226 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11228 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11229 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11230 tempreg
, tempreg
, mips_gp_register
);
11231 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11232 tempreg
, lw_reloc_type
, tempreg
);
11234 if (expr1
.X_add_number
== 0)
11236 else if (expr1
.X_add_number
>= -0x8000
11237 && expr1
.X_add_number
< 0x8000)
11239 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11240 tempreg
, tempreg
, BFD_RELOC_LO16
);
11242 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11246 /* If we are going to add in a base register, and the
11247 target register and the base register are the same,
11248 then we are using AT as a temporary register. Since
11249 we want to load the constant into AT, we add our
11250 current AT (from the global offset table) and the
11251 register into the register now, and pretend we were
11252 not using a base register. */
11257 gas_assert (tempreg
== AT
);
11258 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11261 add_breg_early
= 1;
11264 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11265 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11270 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11273 offset_expr
.X_add_number
= expr1
.X_add_number
;
11274 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11275 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11276 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11277 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11278 if (add_breg_early
)
11280 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11281 op
[0], tempreg
, breg
);
11291 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11295 gas_assert (!mips_opts
.micromips
);
11296 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11300 gas_assert (!mips_opts
.micromips
);
11301 macro_build (NULL
, "c2", "C", 0x02);
11305 gas_assert (!mips_opts
.micromips
);
11306 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11310 gas_assert (!mips_opts
.micromips
);
11311 macro_build (NULL
, "c2", "C", 3);
11315 gas_assert (!mips_opts
.micromips
);
11316 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11320 /* The j instruction may not be used in PIC code, since it
11321 requires an absolute address. We convert it to a b
11323 if (mips_pic
== NO_PIC
)
11324 macro_build (&offset_expr
, "j", "a");
11326 macro_build (&offset_expr
, "b", "p");
11329 /* The jal instructions must be handled as macros because when
11330 generating PIC code they expand to multi-instruction
11331 sequences. Normally they are simple instructions. */
11335 /* Fall through. */
11337 gas_assert (mips_opts
.micromips
);
11338 if (mips_opts
.insn32
)
11340 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11348 /* Fall through. */
11351 if (mips_pic
== NO_PIC
)
11353 s
= jals
? "jalrs" : "jalr";
11354 if (mips_opts
.micromips
11355 && !mips_opts
.insn32
11357 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11358 macro_build (NULL
, s
, "mj", op
[1]);
11360 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11364 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11365 && mips_cprestore_offset
>= 0);
11367 if (op
[1] != PIC_CALL_REG
)
11368 as_warn (_("MIPS PIC call to register other than $25"));
11370 s
= ((mips_opts
.micromips
11371 && !mips_opts
.insn32
11372 && (!mips_opts
.noreorder
|| cprestore
))
11373 ? "jalrs" : "jalr");
11374 if (mips_opts
.micromips
11375 && !mips_opts
.insn32
11377 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11378 macro_build (NULL
, s
, "mj", op
[1]);
11380 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11381 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11383 if (mips_cprestore_offset
< 0)
11384 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11387 if (!mips_frame_reg_valid
)
11389 as_warn (_("no .frame pseudo-op used in PIC code"));
11390 /* Quiet this warning. */
11391 mips_frame_reg_valid
= 1;
11393 if (!mips_cprestore_valid
)
11395 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11396 /* Quiet this warning. */
11397 mips_cprestore_valid
= 1;
11399 if (mips_opts
.noreorder
)
11400 macro_build (NULL
, "nop", "");
11401 expr1
.X_add_number
= mips_cprestore_offset
;
11402 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11405 HAVE_64BIT_ADDRESSES
);
11413 gas_assert (mips_opts
.micromips
);
11414 if (mips_opts
.insn32
)
11416 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11420 /* Fall through. */
11422 if (mips_pic
== NO_PIC
)
11423 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11424 else if (mips_pic
== SVR4_PIC
)
11426 /* If this is a reference to an external symbol, and we are
11427 using a small GOT, we want
11428 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11432 lw $gp,cprestore($sp)
11433 The cprestore value is set using the .cprestore
11434 pseudo-op. If we are using a big GOT, we want
11435 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11437 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11441 lw $gp,cprestore($sp)
11442 If the symbol is not external, we want
11443 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11445 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11448 lw $gp,cprestore($sp)
11450 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11451 sequences above, minus nops, unless the symbol is local,
11452 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11458 relax_start (offset_expr
.X_add_symbol
);
11459 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11460 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11463 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11464 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11470 relax_start (offset_expr
.X_add_symbol
);
11471 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11472 BFD_RELOC_MIPS_CALL_HI16
);
11473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11474 PIC_CALL_REG
, mips_gp_register
);
11475 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11476 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11479 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11480 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11482 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11483 PIC_CALL_REG
, PIC_CALL_REG
,
11484 BFD_RELOC_MIPS_GOT_OFST
);
11488 macro_build_jalr (&offset_expr
, 0);
11492 relax_start (offset_expr
.X_add_symbol
);
11495 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11496 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11505 gpdelay
= reg_needs_delay (mips_gp_register
);
11506 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11507 BFD_RELOC_MIPS_CALL_HI16
);
11508 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11509 PIC_CALL_REG
, mips_gp_register
);
11510 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11511 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11516 macro_build (NULL
, "nop", "");
11518 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11519 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11522 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11523 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11525 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11527 if (mips_cprestore_offset
< 0)
11528 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11531 if (!mips_frame_reg_valid
)
11533 as_warn (_("no .frame pseudo-op used in PIC code"));
11534 /* Quiet this warning. */
11535 mips_frame_reg_valid
= 1;
11537 if (!mips_cprestore_valid
)
11539 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11540 /* Quiet this warning. */
11541 mips_cprestore_valid
= 1;
11543 if (mips_opts
.noreorder
)
11544 macro_build (NULL
, "nop", "");
11545 expr1
.X_add_number
= mips_cprestore_offset
;
11546 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11549 HAVE_64BIT_ADDRESSES
);
11553 else if (mips_pic
== VXWORKS_PIC
)
11554 as_bad (_("non-PIC jump used in PIC library"));
11661 gas_assert (!mips_opts
.micromips
);
11664 /* Itbl support may require additional care here. */
11670 /* Itbl support may require additional care here. */
11676 offbits
= (mips_opts
.micromips
? 12
11677 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11679 /* Itbl support may require additional care here. */
11683 gas_assert (!mips_opts
.micromips
);
11686 /* Itbl support may require additional care here. */
11692 offbits
= (mips_opts
.micromips
? 12 : 16);
11697 offbits
= (mips_opts
.micromips
? 12 : 16);
11702 /* Itbl support may require additional care here. */
11708 offbits
= (mips_opts
.micromips
? 12
11709 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11711 /* Itbl support may require additional care here. */
11717 /* Itbl support may require additional care here. */
11723 /* Itbl support may require additional care here. */
11729 offbits
= (mips_opts
.micromips
? 12 : 16);
11734 offbits
= (mips_opts
.micromips
? 12 : 16);
11739 offbits
= (mips_opts
.micromips
? 12
11740 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11746 offbits
= (mips_opts
.micromips
? 12
11747 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11753 offbits
= (mips_opts
.micromips
? 12 : 16);
11756 gas_assert (mips_opts
.micromips
);
11763 gas_assert (mips_opts
.micromips
);
11770 gas_assert (mips_opts
.micromips
);
11776 gas_assert (mips_opts
.micromips
);
11783 /* We don't want to use $0 as tempreg. */
11784 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11787 tempreg
= op
[0] + lp
;
11803 gas_assert (!mips_opts
.micromips
);
11806 /* Itbl support may require additional care here. */
11812 /* Itbl support may require additional care here. */
11818 offbits
= (mips_opts
.micromips
? 12
11819 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11821 /* Itbl support may require additional care here. */
11825 gas_assert (!mips_opts
.micromips
);
11828 /* Itbl support may require additional care here. */
11834 offbits
= (mips_opts
.micromips
? 12 : 16);
11839 offbits
= (mips_opts
.micromips
? 12 : 16);
11844 offbits
= (mips_opts
.micromips
? 12
11845 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11851 offbits
= (mips_opts
.micromips
? 12
11852 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11857 fmt
= (mips_opts
.micromips
? "k,~(b)"
11858 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11860 offbits
= (mips_opts
.micromips
? 12
11861 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11871 fmt
= (mips_opts
.micromips
? "k,~(b)"
11872 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11874 offbits
= (mips_opts
.micromips
? 12
11875 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11887 /* Itbl support may require additional care here. */
11892 offbits
= (mips_opts
.micromips
? 12
11893 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11895 /* Itbl support may require additional care here. */
11901 /* Itbl support may require additional care here. */
11905 gas_assert (!mips_opts
.micromips
);
11908 /* Itbl support may require additional care here. */
11914 offbits
= (mips_opts
.micromips
? 12 : 16);
11919 offbits
= (mips_opts
.micromips
? 12 : 16);
11922 gas_assert (mips_opts
.micromips
);
11928 gas_assert (mips_opts
.micromips
);
11934 gas_assert (mips_opts
.micromips
);
11940 gas_assert (mips_opts
.micromips
);
11949 if (small_offset_p (0, align
, 16))
11951 /* The first case exists for M_LD_AB and M_SD_AB, which are
11952 macros for o32 but which should act like normal instructions
11955 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11956 offset_reloc
[1], offset_reloc
[2], breg
);
11957 else if (small_offset_p (0, align
, offbits
))
11960 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11962 macro_build (NULL
, s
, fmt
, op
[0],
11963 (int) offset_expr
.X_add_number
, breg
);
11969 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11970 tempreg
, breg
, -1, offset_reloc
[0],
11971 offset_reloc
[1], offset_reloc
[2]);
11973 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11975 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11983 if (offset_expr
.X_op
!= O_constant
11984 && offset_expr
.X_op
!= O_symbol
)
11986 as_bad (_("expression too complex"));
11987 offset_expr
.X_op
= O_constant
;
11990 if (HAVE_32BIT_ADDRESSES
11991 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11995 sprintf_vma (value
, offset_expr
.X_add_number
);
11996 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11999 /* A constant expression in PIC code can be handled just as it
12000 is in non PIC code. */
12001 if (offset_expr
.X_op
== O_constant
)
12003 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12004 offbits
== 0 ? 16 : offbits
);
12005 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12007 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12009 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12010 tempreg
, tempreg
, breg
);
12013 if (offset_expr
.X_add_number
!= 0)
12014 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12015 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12016 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12018 else if (offbits
== 16)
12019 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12021 macro_build (NULL
, s
, fmt
, op
[0],
12022 (int) offset_expr
.X_add_number
, tempreg
);
12024 else if (offbits
!= 16)
12026 /* The offset field is too narrow to be used for a low-part
12027 relocation, so load the whole address into the auxiliary
12029 load_address (tempreg
, &offset_expr
, &used_at
);
12031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12032 tempreg
, tempreg
, breg
);
12034 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12036 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12038 else if (mips_pic
== NO_PIC
)
12040 /* If this is a reference to a GP relative symbol, and there
12041 is no base register, we want
12042 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12043 Otherwise, if there is no base register, we want
12044 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12045 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12046 If we have a constant, we need two instructions anyhow,
12047 so we always use the latter form.
12049 If we have a base register, and this is a reference to a
12050 GP relative symbol, we want
12051 addu $tempreg,$breg,$gp
12052 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12054 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12055 addu $tempreg,$tempreg,$breg
12056 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12057 With a constant we always use the latter case.
12059 With 64bit address space and no base register and $at usable,
12061 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12062 lui $at,<sym> (BFD_RELOC_HI16_S)
12063 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12066 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12067 If we have a base register, we want
12068 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12069 lui $at,<sym> (BFD_RELOC_HI16_S)
12070 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12074 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12076 Without $at we can't generate the optimal path for superscalar
12077 processors here since this would require two temporary registers.
12078 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12079 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12081 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12083 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12084 If we have a base register, we want
12085 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12086 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12088 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12090 daddu $tempreg,$tempreg,$breg
12091 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12093 For GP relative symbols in 64bit address space we can use
12094 the same sequence as in 32bit address space. */
12095 if (HAVE_64BIT_SYMBOLS
)
12097 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12098 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12100 relax_start (offset_expr
.X_add_symbol
);
12103 macro_build (&offset_expr
, s
, fmt
, op
[0],
12104 BFD_RELOC_GPREL16
, mips_gp_register
);
12108 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12109 tempreg
, breg
, mips_gp_register
);
12110 macro_build (&offset_expr
, s
, fmt
, op
[0],
12111 BFD_RELOC_GPREL16
, tempreg
);
12116 if (used_at
== 0 && mips_opts
.at
)
12118 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12119 BFD_RELOC_MIPS_HIGHEST
);
12120 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12122 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12123 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12125 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12126 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12127 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12128 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12134 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12135 BFD_RELOC_MIPS_HIGHEST
);
12136 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12137 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12138 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12139 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12140 tempreg
, BFD_RELOC_HI16_S
);
12141 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12143 macro_build (NULL
, "daddu", "d,v,t",
12144 tempreg
, tempreg
, breg
);
12145 macro_build (&offset_expr
, s
, fmt
, op
[0],
12146 BFD_RELOC_LO16
, tempreg
);
12149 if (mips_relax
.sequence
)
12156 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12157 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12159 relax_start (offset_expr
.X_add_symbol
);
12160 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12164 macro_build_lui (&offset_expr
, tempreg
);
12165 macro_build (&offset_expr
, s
, fmt
, op
[0],
12166 BFD_RELOC_LO16
, tempreg
);
12167 if (mips_relax
.sequence
)
12172 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12173 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12175 relax_start (offset_expr
.X_add_symbol
);
12176 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12177 tempreg
, breg
, mips_gp_register
);
12178 macro_build (&offset_expr
, s
, fmt
, op
[0],
12179 BFD_RELOC_GPREL16
, tempreg
);
12182 macro_build_lui (&offset_expr
, tempreg
);
12183 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12184 tempreg
, tempreg
, breg
);
12185 macro_build (&offset_expr
, s
, fmt
, op
[0],
12186 BFD_RELOC_LO16
, tempreg
);
12187 if (mips_relax
.sequence
)
12191 else if (!mips_big_got
)
12193 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12195 /* If this is a reference to an external symbol, we want
12196 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12198 <op> op[0],0($tempreg)
12200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12202 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12203 <op> op[0],0($tempreg)
12205 For NewABI, we want
12206 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12207 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12209 If there is a base register, we add it to $tempreg before
12210 the <op>. If there is a constant, we stick it in the
12211 <op> instruction. We don't handle constants larger than
12212 16 bits, because we have no way to load the upper 16 bits
12213 (actually, we could handle them for the subset of cases
12214 in which we are not using $at). */
12215 gas_assert (offset_expr
.X_op
== O_symbol
);
12218 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12219 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12221 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12222 tempreg
, tempreg
, breg
);
12223 macro_build (&offset_expr
, s
, fmt
, op
[0],
12224 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12227 expr1
.X_add_number
= offset_expr
.X_add_number
;
12228 offset_expr
.X_add_number
= 0;
12229 if (expr1
.X_add_number
< -0x8000
12230 || expr1
.X_add_number
>= 0x8000)
12231 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12232 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12233 lw_reloc_type
, mips_gp_register
);
12235 relax_start (offset_expr
.X_add_symbol
);
12237 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12238 tempreg
, BFD_RELOC_LO16
);
12241 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12242 tempreg
, tempreg
, breg
);
12243 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12245 else if (mips_big_got
&& !HAVE_NEWABI
)
12249 /* If this is a reference to an external symbol, we want
12250 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12251 addu $tempreg,$tempreg,$gp
12252 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12253 <op> op[0],0($tempreg)
12255 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12257 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12258 <op> op[0],0($tempreg)
12259 If there is a base register, we add it to $tempreg before
12260 the <op>. If there is a constant, we stick it in the
12261 <op> instruction. We don't handle constants larger than
12262 16 bits, because we have no way to load the upper 16 bits
12263 (actually, we could handle them for the subset of cases
12264 in which we are not using $at). */
12265 gas_assert (offset_expr
.X_op
== O_symbol
);
12266 expr1
.X_add_number
= offset_expr
.X_add_number
;
12267 offset_expr
.X_add_number
= 0;
12268 if (expr1
.X_add_number
< -0x8000
12269 || expr1
.X_add_number
>= 0x8000)
12270 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12271 gpdelay
= reg_needs_delay (mips_gp_register
);
12272 relax_start (offset_expr
.X_add_symbol
);
12273 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12274 BFD_RELOC_MIPS_GOT_HI16
);
12275 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12277 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12278 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12281 macro_build (NULL
, "nop", "");
12282 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12283 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12285 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12286 tempreg
, BFD_RELOC_LO16
);
12290 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12291 tempreg
, tempreg
, breg
);
12292 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12294 else if (mips_big_got
&& HAVE_NEWABI
)
12296 /* If this is a reference to an external symbol, we want
12297 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12298 add $tempreg,$tempreg,$gp
12299 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12300 <op> op[0],<ofst>($tempreg)
12301 Otherwise, for local symbols, we want:
12302 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12303 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12304 gas_assert (offset_expr
.X_op
== O_symbol
);
12305 expr1
.X_add_number
= offset_expr
.X_add_number
;
12306 offset_expr
.X_add_number
= 0;
12307 if (expr1
.X_add_number
< -0x8000
12308 || expr1
.X_add_number
>= 0x8000)
12309 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12310 relax_start (offset_expr
.X_add_symbol
);
12311 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12312 BFD_RELOC_MIPS_GOT_HI16
);
12313 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12315 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12316 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12318 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12319 tempreg
, tempreg
, breg
);
12320 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12323 offset_expr
.X_add_number
= expr1
.X_add_number
;
12324 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12325 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12327 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12328 tempreg
, tempreg
, breg
);
12329 macro_build (&offset_expr
, s
, fmt
, op
[0],
12330 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12339 gas_assert (mips_opts
.micromips
);
12340 gas_assert (mips_opts
.insn32
);
12341 start_noreorder ();
12342 macro_build (NULL
, "jr", "s", RA
);
12343 expr1
.X_add_number
= op
[0] << 2;
12344 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12349 gas_assert (mips_opts
.micromips
);
12350 gas_assert (mips_opts
.insn32
);
12351 macro_build (NULL
, "jr", "s", op
[0]);
12352 if (mips_opts
.noreorder
)
12353 macro_build (NULL
, "nop", "");
12358 load_register (op
[0], &imm_expr
, 0);
12362 load_register (op
[0], &imm_expr
, 1);
12366 if (imm_expr
.X_op
== O_constant
)
12369 load_register (AT
, &imm_expr
, 0);
12370 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12375 gas_assert (imm_expr
.X_op
== O_absent
12376 && offset_expr
.X_op
== O_symbol
12377 && strcmp (segment_name (S_GET_SEGMENT
12378 (offset_expr
.X_add_symbol
)),
12380 && offset_expr
.X_add_number
== 0);
12381 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12382 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12387 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12388 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12389 order 32 bits of the value and the low order 32 bits are either
12390 zero or in OFFSET_EXPR. */
12391 if (imm_expr
.X_op
== O_constant
)
12393 if (GPR_SIZE
== 64)
12394 load_register (op
[0], &imm_expr
, 1);
12399 if (target_big_endian
)
12411 load_register (hreg
, &imm_expr
, 0);
12414 if (offset_expr
.X_op
== O_absent
)
12415 move_register (lreg
, 0);
12418 gas_assert (offset_expr
.X_op
== O_constant
);
12419 load_register (lreg
, &offset_expr
, 0);
12425 gas_assert (imm_expr
.X_op
== O_absent
);
12427 /* We know that sym is in the .rdata section. First we get the
12428 upper 16 bits of the address. */
12429 if (mips_pic
== NO_PIC
)
12431 macro_build_lui (&offset_expr
, AT
);
12436 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12437 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12441 /* Now we load the register(s). */
12442 if (GPR_SIZE
== 64)
12445 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12446 BFD_RELOC_LO16
, AT
);
12451 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12452 BFD_RELOC_LO16
, AT
);
12455 /* FIXME: How in the world do we deal with the possible
12457 offset_expr
.X_add_number
+= 4;
12458 macro_build (&offset_expr
, "lw", "t,o(b)",
12459 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12465 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12466 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12467 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12468 the value and the low order 32 bits are either zero or in
12470 if (imm_expr
.X_op
== O_constant
)
12473 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12474 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12475 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12478 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12479 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12480 else if (FPR_SIZE
!= 32)
12481 as_bad (_("Unable to generate `%s' compliant code "
12483 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12485 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12486 if (offset_expr
.X_op
== O_absent
)
12487 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12490 gas_assert (offset_expr
.X_op
== O_constant
);
12491 load_register (AT
, &offset_expr
, 0);
12492 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12498 gas_assert (imm_expr
.X_op
== O_absent
12499 && offset_expr
.X_op
== O_symbol
12500 && offset_expr
.X_add_number
== 0);
12501 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12502 if (strcmp (s
, ".lit8") == 0)
12504 op
[2] = mips_gp_register
;
12505 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12506 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12507 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12511 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12513 if (mips_pic
!= NO_PIC
)
12514 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12515 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12518 /* FIXME: This won't work for a 64 bit address. */
12519 macro_build_lui (&offset_expr
, AT
);
12523 offset_reloc
[0] = BFD_RELOC_LO16
;
12524 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12525 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12532 * The MIPS assembler seems to check for X_add_number not
12533 * being double aligned and generating:
12534 * lui at,%hi(foo+1)
12536 * addiu at,at,%lo(foo+1)
12539 * But, the resulting address is the same after relocation so why
12540 * generate the extra instruction?
12542 /* Itbl support may require additional care here. */
12545 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12554 gas_assert (!mips_opts
.micromips
);
12555 /* Itbl support may require additional care here. */
12558 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12578 if (GPR_SIZE
== 64)
12588 if (GPR_SIZE
== 64)
12596 /* Even on a big endian machine $fn comes before $fn+1. We have
12597 to adjust when loading from memory. We set coproc if we must
12598 load $fn+1 first. */
12599 /* Itbl support may require additional care here. */
12600 if (!target_big_endian
)
12604 if (small_offset_p (0, align
, 16))
12607 if (!small_offset_p (4, align
, 16))
12609 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12610 -1, offset_reloc
[0], offset_reloc
[1],
12612 expr1
.X_add_number
= 0;
12616 offset_reloc
[0] = BFD_RELOC_LO16
;
12617 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12618 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12620 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12622 ep
->X_add_number
+= 4;
12623 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12624 offset_reloc
[1], offset_reloc
[2], breg
);
12625 ep
->X_add_number
-= 4;
12626 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12627 offset_reloc
[1], offset_reloc
[2], breg
);
12631 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12632 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12634 ep
->X_add_number
+= 4;
12635 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12636 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12642 if (offset_expr
.X_op
!= O_symbol
12643 && offset_expr
.X_op
!= O_constant
)
12645 as_bad (_("expression too complex"));
12646 offset_expr
.X_op
= O_constant
;
12649 if (HAVE_32BIT_ADDRESSES
12650 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12654 sprintf_vma (value
, offset_expr
.X_add_number
);
12655 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12658 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12660 /* If this is a reference to a GP relative symbol, we want
12661 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12662 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12663 If we have a base register, we use this
12665 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12666 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12667 If this is not a GP relative symbol, we want
12668 lui $at,<sym> (BFD_RELOC_HI16_S)
12669 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12670 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12671 If there is a base register, we add it to $at after the
12672 lui instruction. If there is a constant, we always use
12674 if (offset_expr
.X_op
== O_symbol
12675 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12676 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12678 relax_start (offset_expr
.X_add_symbol
);
12681 tempreg
= mips_gp_register
;
12685 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12686 AT
, breg
, mips_gp_register
);
12691 /* Itbl support may require additional care here. */
12692 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12693 BFD_RELOC_GPREL16
, tempreg
);
12694 offset_expr
.X_add_number
+= 4;
12696 /* Set mips_optimize to 2 to avoid inserting an
12698 hold_mips_optimize
= mips_optimize
;
12700 /* Itbl support may require additional care here. */
12701 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12702 BFD_RELOC_GPREL16
, tempreg
);
12703 mips_optimize
= hold_mips_optimize
;
12707 offset_expr
.X_add_number
-= 4;
12710 if (offset_high_part (offset_expr
.X_add_number
, 16)
12711 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12713 load_address (AT
, &offset_expr
, &used_at
);
12714 offset_expr
.X_op
= O_constant
;
12715 offset_expr
.X_add_number
= 0;
12718 macro_build_lui (&offset_expr
, AT
);
12720 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12721 /* Itbl support may require additional care here. */
12722 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12723 BFD_RELOC_LO16
, AT
);
12724 /* FIXME: How do we handle overflow here? */
12725 offset_expr
.X_add_number
+= 4;
12726 /* Itbl support may require additional care here. */
12727 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12728 BFD_RELOC_LO16
, AT
);
12729 if (mips_relax
.sequence
)
12732 else if (!mips_big_got
)
12734 /* If this is a reference to an external symbol, we want
12735 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12738 <op> op[0]+1,4($at)
12740 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12742 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12743 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12744 If there is a base register we add it to $at before the
12745 lwc1 instructions. If there is a constant we include it
12746 in the lwc1 instructions. */
12748 expr1
.X_add_number
= offset_expr
.X_add_number
;
12749 if (expr1
.X_add_number
< -0x8000
12750 || expr1
.X_add_number
>= 0x8000 - 4)
12751 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12752 load_got_offset (AT
, &offset_expr
);
12755 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12757 /* Set mips_optimize to 2 to avoid inserting an undesired
12759 hold_mips_optimize
= mips_optimize
;
12762 /* Itbl support may require additional care here. */
12763 relax_start (offset_expr
.X_add_symbol
);
12764 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12765 BFD_RELOC_LO16
, AT
);
12766 expr1
.X_add_number
+= 4;
12767 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12768 BFD_RELOC_LO16
, AT
);
12770 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12771 BFD_RELOC_LO16
, AT
);
12772 offset_expr
.X_add_number
+= 4;
12773 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12774 BFD_RELOC_LO16
, AT
);
12777 mips_optimize
= hold_mips_optimize
;
12779 else if (mips_big_got
)
12783 /* If this is a reference to an external symbol, we want
12784 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12786 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12789 <op> op[0]+1,4($at)
12791 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12793 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12794 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12795 If there is a base register we add it to $at before the
12796 lwc1 instructions. If there is a constant we include it
12797 in the lwc1 instructions. */
12799 expr1
.X_add_number
= offset_expr
.X_add_number
;
12800 offset_expr
.X_add_number
= 0;
12801 if (expr1
.X_add_number
< -0x8000
12802 || expr1
.X_add_number
>= 0x8000 - 4)
12803 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12804 gpdelay
= reg_needs_delay (mips_gp_register
);
12805 relax_start (offset_expr
.X_add_symbol
);
12806 macro_build (&offset_expr
, "lui", LUI_FMT
,
12807 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12808 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12809 AT
, AT
, mips_gp_register
);
12810 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12811 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12814 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12815 /* Itbl support may require additional care here. */
12816 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12817 BFD_RELOC_LO16
, AT
);
12818 expr1
.X_add_number
+= 4;
12820 /* Set mips_optimize to 2 to avoid inserting an undesired
12822 hold_mips_optimize
= mips_optimize
;
12824 /* Itbl support may require additional care here. */
12825 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12826 BFD_RELOC_LO16
, AT
);
12827 mips_optimize
= hold_mips_optimize
;
12828 expr1
.X_add_number
-= 4;
12831 offset_expr
.X_add_number
= expr1
.X_add_number
;
12833 macro_build (NULL
, "nop", "");
12834 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12835 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12838 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12839 /* Itbl support may require additional care here. */
12840 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12841 BFD_RELOC_LO16
, AT
);
12842 offset_expr
.X_add_number
+= 4;
12844 /* Set mips_optimize to 2 to avoid inserting an undesired
12846 hold_mips_optimize
= mips_optimize
;
12848 /* Itbl support may require additional care here. */
12849 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12850 BFD_RELOC_LO16
, AT
);
12851 mips_optimize
= hold_mips_optimize
;
12865 gas_assert (!mips_opts
.micromips
);
12870 /* New code added to support COPZ instructions.
12871 This code builds table entries out of the macros in mip_opcodes.
12872 R4000 uses interlocks to handle coproc delays.
12873 Other chips (like the R3000) require nops to be inserted for delays.
12875 FIXME: Currently, we require that the user handle delays.
12876 In order to fill delay slots for non-interlocked chips,
12877 we must have a way to specify delays based on the coprocessor.
12878 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12879 What are the side-effects of the cop instruction?
12880 What cache support might we have and what are its effects?
12881 Both coprocessor & memory require delays. how long???
12882 What registers are read/set/modified?
12884 If an itbl is provided to interpret cop instructions,
12885 this knowledge can be encoded in the itbl spec. */
12899 gas_assert (!mips_opts
.micromips
);
12900 /* For now we just do C (same as Cz). The parameter will be
12901 stored in insn_opcode by mips_ip. */
12902 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12906 move_register (op
[0], op
[1]);
12910 gas_assert (mips_opts
.micromips
);
12911 gas_assert (mips_opts
.insn32
);
12912 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12913 micromips_to_32_reg_m_map
[op
[1]]);
12914 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12915 micromips_to_32_reg_n_map
[op
[2]]);
12920 /* Fall through. */
12922 if (mips_opts
.arch
== CPU_R5900
)
12923 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12927 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12928 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12934 /* Fall through. */
12936 /* The MIPS assembler some times generates shifts and adds. I'm
12937 not trying to be that fancy. GCC should do this for us
12940 load_register (AT
, &imm_expr
, dbl
);
12941 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12942 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12947 /* Fall through. */
12954 /* Fall through. */
12957 start_noreorder ();
12960 load_register (AT
, &imm_expr
, dbl
);
12961 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12962 op
[1], imm
? AT
: op
[2]);
12963 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12964 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12965 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12967 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12970 if (mips_opts
.micromips
)
12971 micromips_label_expr (&label_expr
);
12973 label_expr
.X_add_number
= 8;
12974 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12975 macro_build (NULL
, "nop", "");
12976 macro_build (NULL
, "break", BRK_FMT
, 6);
12977 if (mips_opts
.micromips
)
12978 micromips_add_label ();
12981 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12986 /* Fall through. */
12993 /* Fall through. */
12996 start_noreorder ();
12999 load_register (AT
, &imm_expr
, dbl
);
13000 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13001 op
[1], imm
? AT
: op
[2]);
13002 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13003 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13005 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13008 if (mips_opts
.micromips
)
13009 micromips_label_expr (&label_expr
);
13011 label_expr
.X_add_number
= 8;
13012 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13013 macro_build (NULL
, "nop", "");
13014 macro_build (NULL
, "break", BRK_FMT
, 6);
13015 if (mips_opts
.micromips
)
13016 micromips_add_label ();
13022 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13024 if (op
[0] == op
[1])
13031 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13032 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13036 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13037 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13038 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13039 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13043 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13045 if (op
[0] == op
[1])
13052 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13053 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13057 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13058 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13059 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13060 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13069 rot
= imm_expr
.X_add_number
& 0x3f;
13070 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13072 rot
= (64 - rot
) & 0x3f;
13074 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13076 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13081 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13084 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13085 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13088 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13089 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13090 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13098 rot
= imm_expr
.X_add_number
& 0x1f;
13099 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13101 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13102 (32 - rot
) & 0x1f);
13107 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13111 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13112 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13113 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13118 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13120 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13124 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13125 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13126 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13127 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13131 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13133 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13137 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13138 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13139 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13140 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13149 rot
= imm_expr
.X_add_number
& 0x3f;
13150 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13153 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13155 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13160 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13163 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13164 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13167 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13168 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13169 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13177 rot
= imm_expr
.X_add_number
& 0x1f;
13178 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13180 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13185 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13189 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13190 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13191 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13197 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13198 else if (op
[2] == 0)
13199 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13202 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13203 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13208 if (imm_expr
.X_add_number
== 0)
13210 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13215 as_warn (_("instruction %s: result is always false"),
13216 ip
->insn_mo
->name
);
13217 move_register (op
[0], 0);
13220 if (CPU_HAS_SEQ (mips_opts
.arch
)
13221 && -512 <= imm_expr
.X_add_number
13222 && imm_expr
.X_add_number
< 512)
13224 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13225 (int) imm_expr
.X_add_number
);
13228 if (imm_expr
.X_add_number
>= 0
13229 && imm_expr
.X_add_number
< 0x10000)
13230 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13231 else if (imm_expr
.X_add_number
> -0x8000
13232 && imm_expr
.X_add_number
< 0)
13234 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13235 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13236 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13238 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13241 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13242 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13247 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13248 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13251 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13254 case M_SGE
: /* X >= Y <==> not (X < Y) */
13260 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13261 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13264 case M_SGE_I
: /* X >= I <==> not (X < I) */
13266 if (imm_expr
.X_add_number
>= -0x8000
13267 && imm_expr
.X_add_number
< 0x8000)
13268 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13269 op
[0], op
[1], BFD_RELOC_LO16
);
13272 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13273 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13277 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13280 case M_SGT
: /* X > Y <==> Y < X */
13286 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13289 case M_SGT_I
: /* X > I <==> I < X */
13296 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13297 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13300 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13306 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13307 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13310 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13317 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13318 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13319 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13323 if (imm_expr
.X_add_number
>= -0x8000
13324 && imm_expr
.X_add_number
< 0x8000)
13326 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13331 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13332 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13336 if (imm_expr
.X_add_number
>= -0x8000
13337 && imm_expr
.X_add_number
< 0x8000)
13339 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13344 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13345 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13350 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13351 else if (op
[2] == 0)
13352 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13355 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13356 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13361 if (imm_expr
.X_add_number
== 0)
13363 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13368 as_warn (_("instruction %s: result is always true"),
13369 ip
->insn_mo
->name
);
13370 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13371 op
[0], 0, BFD_RELOC_LO16
);
13374 if (CPU_HAS_SEQ (mips_opts
.arch
)
13375 && -512 <= imm_expr
.X_add_number
13376 && imm_expr
.X_add_number
< 512)
13378 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13379 (int) imm_expr
.X_add_number
);
13382 if (imm_expr
.X_add_number
>= 0
13383 && imm_expr
.X_add_number
< 0x10000)
13385 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13388 else if (imm_expr
.X_add_number
> -0x8000
13389 && imm_expr
.X_add_number
< 0)
13391 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13392 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13393 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13395 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13398 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13399 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13404 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13405 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13408 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13423 if (!mips_opts
.micromips
)
13425 if (imm_expr
.X_add_number
> -0x200
13426 && imm_expr
.X_add_number
<= 0x200)
13428 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13429 (int) -imm_expr
.X_add_number
);
13438 if (imm_expr
.X_add_number
> -0x8000
13439 && imm_expr
.X_add_number
<= 0x8000)
13441 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13442 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13447 load_register (AT
, &imm_expr
, dbl
);
13448 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13470 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13471 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13476 gas_assert (!mips_opts
.micromips
);
13477 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13481 * Is the double cfc1 instruction a bug in the mips assembler;
13482 * or is there a reason for it?
13484 start_noreorder ();
13485 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13486 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13487 macro_build (NULL
, "nop", "");
13488 expr1
.X_add_number
= 3;
13489 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13490 expr1
.X_add_number
= 2;
13491 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13492 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13493 macro_build (NULL
, "nop", "");
13494 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13496 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13497 macro_build (NULL
, "nop", "");
13514 offbits
= (mips_opts
.micromips
? 12 : 16);
13520 offbits
= (mips_opts
.micromips
? 12 : 16);
13532 offbits
= (mips_opts
.micromips
? 12 : 16);
13539 offbits
= (mips_opts
.micromips
? 12 : 16);
13545 large_offset
= !small_offset_p (off
, align
, offbits
);
13547 expr1
.X_add_number
= 0;
13552 if (small_offset_p (0, align
, 16))
13553 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13554 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13557 load_address (tempreg
, ep
, &used_at
);
13559 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13560 tempreg
, tempreg
, breg
);
13562 offset_reloc
[0] = BFD_RELOC_LO16
;
13563 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13564 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13569 else if (!ust
&& op
[0] == breg
)
13580 if (!target_big_endian
)
13581 ep
->X_add_number
+= off
;
13583 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13585 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13586 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13588 if (!target_big_endian
)
13589 ep
->X_add_number
-= off
;
13591 ep
->X_add_number
+= off
;
13593 macro_build (NULL
, s2
, "t,~(b)",
13594 tempreg
, (int) ep
->X_add_number
, breg
);
13596 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13597 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13599 /* If necessary, move the result in tempreg to the final destination. */
13600 if (!ust
&& op
[0] != tempreg
)
13602 /* Protect second load's delay slot. */
13604 move_register (op
[0], tempreg
);
13610 if (target_big_endian
== ust
)
13611 ep
->X_add_number
+= off
;
13612 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13613 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13614 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13616 /* For halfword transfers we need a temporary register to shuffle
13617 bytes. Unfortunately for M_USH_A we have none available before
13618 the next store as AT holds the base address. We deal with this
13619 case by clobbering TREG and then restoring it as with ULH. */
13620 tempreg
= ust
== large_offset
? op
[0] : AT
;
13622 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13624 if (target_big_endian
== ust
)
13625 ep
->X_add_number
-= off
;
13627 ep
->X_add_number
+= off
;
13628 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13629 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13631 /* For M_USH_A re-retrieve the LSB. */
13632 if (ust
&& large_offset
)
13634 if (target_big_endian
)
13635 ep
->X_add_number
+= off
;
13637 ep
->X_add_number
-= off
;
13638 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13639 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13641 /* For ULH and M_USH_A OR the LSB in. */
13642 if (!ust
|| large_offset
)
13644 tempreg
= !large_offset
? AT
: op
[0];
13645 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13646 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13651 /* FIXME: Check if this is one of the itbl macros, since they
13652 are added dynamically. */
13653 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13656 if (!mips_opts
.at
&& used_at
)
13657 as_bad (_("macro used $at after \".set noat\""));
13660 /* Implement macros in mips16 mode. */
13663 mips16_macro (struct mips_cl_insn
*ip
)
13665 const struct mips_operand_array
*operands
;
13670 const char *s
, *s2
, *s3
;
13671 unsigned int op
[MAX_OPERANDS
];
13674 mask
= ip
->insn_mo
->mask
;
13676 operands
= insn_operands (ip
);
13677 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13678 if (operands
->operand
[i
])
13679 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13683 expr1
.X_op
= O_constant
;
13684 expr1
.X_op_symbol
= NULL
;
13685 expr1
.X_add_symbol
= NULL
;
13686 expr1
.X_add_number
= 1;
13697 /* Fall through. */
13703 /* Fall through. */
13707 start_noreorder ();
13708 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13709 expr1
.X_add_number
= 2;
13710 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13711 macro_build (NULL
, "break", "6", 7);
13713 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13714 since that causes an overflow. We should do that as well,
13715 but I don't see how to do the comparisons without a temporary
13718 macro_build (NULL
, s
, "x", op
[0]);
13737 start_noreorder ();
13738 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13739 expr1
.X_add_number
= 2;
13740 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13741 macro_build (NULL
, "break", "6", 7);
13743 macro_build (NULL
, s2
, "x", op
[0]);
13748 /* Fall through. */
13750 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13751 macro_build (NULL
, "mflo", "x", op
[0]);
13759 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13760 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13764 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13765 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13769 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13770 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13792 goto do_reverse_branch
;
13796 goto do_reverse_branch
;
13808 goto do_reverse_branch
;
13819 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13820 macro_build (&offset_expr
, s2
, "p");
13847 goto do_addone_branch_i
;
13852 goto do_addone_branch_i
;
13867 goto do_addone_branch_i
;
13873 do_addone_branch_i
:
13874 ++imm_expr
.X_add_number
;
13877 macro_build (&imm_expr
, s
, s3
, op
[0]);
13878 macro_build (&offset_expr
, s2
, "p");
13882 expr1
.X_add_number
= 0;
13883 macro_build (&expr1
, "slti", "x,8", op
[1]);
13884 if (op
[0] != op
[1])
13885 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13886 expr1
.X_add_number
= 2;
13887 macro_build (&expr1
, "bteqz", "p");
13888 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13893 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13894 opcode bits in *OPCODE_EXTRA. */
13896 static struct mips_opcode
*
13897 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13898 ssize_t length
, unsigned int *opcode_extra
)
13900 char *name
, *dot
, *p
;
13901 unsigned int mask
, suffix
;
13903 struct mips_opcode
*insn
;
13905 /* Make a copy of the instruction so that we can fiddle with it. */
13906 name
= xstrndup (start
, length
);
13908 /* Look up the instruction as-is. */
13909 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13913 dot
= strchr (name
, '.');
13916 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13917 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13918 if (*p
== 0 && mask
!= 0)
13921 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13923 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13925 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13931 if (mips_opts
.micromips
)
13933 /* See if there's an instruction size override suffix,
13934 either `16' or `32', at the end of the mnemonic proper,
13935 that defines the operation, i.e. before the first `.'
13936 character if any. Strip it and retry. */
13937 opend
= dot
!= NULL
? dot
- name
: length
;
13938 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13940 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13946 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13947 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13950 forced_insn_length
= suffix
;
13962 /* Assemble an instruction into its binary format. If the instruction
13963 is a macro, set imm_expr and offset_expr to the values associated
13964 with "I" and "A" operands respectively. Otherwise store the value
13965 of the relocatable field (if any) in offset_expr. In both cases
13966 set offset_reloc to the relocation operators applied to offset_expr. */
13969 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13971 const struct mips_opcode
*first
, *past
;
13972 struct hash_control
*hash
;
13975 struct mips_operand_token
*tokens
;
13976 unsigned int opcode_extra
;
13978 if (mips_opts
.micromips
)
13980 hash
= micromips_op_hash
;
13981 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13986 past
= &mips_opcodes
[NUMOPCODES
];
13988 forced_insn_length
= 0;
13991 /* We first try to match an instruction up to a space or to the end. */
13992 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13995 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13998 set_insn_error (0, _("unrecognized opcode"));
14002 if (strcmp (first
->name
, "li.s") == 0)
14004 else if (strcmp (first
->name
, "li.d") == 0)
14008 tokens
= mips_parse_arguments (str
+ end
, format
);
14012 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14013 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14014 set_insn_error (0, _("invalid operands"));
14016 obstack_free (&mips_operand_tokens
, tokens
);
14019 /* As for mips_ip, but used when assembling MIPS16 code.
14020 Also set forced_insn_length to the resulting instruction size in
14021 bytes if the user explicitly requested a small or extended instruction. */
14024 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14027 struct mips_opcode
*first
;
14028 struct mips_operand_token
*tokens
;
14031 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14053 else if (*s
== 'e')
14060 else if (*s
++ == ' ')
14062 set_insn_error (0, _("unrecognized opcode"));
14065 forced_insn_length
= l
;
14068 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14073 set_insn_error (0, _("unrecognized opcode"));
14077 tokens
= mips_parse_arguments (s
, 0);
14081 if (!match_mips16_insns (insn
, first
, tokens
))
14082 set_insn_error (0, _("invalid operands"));
14084 obstack_free (&mips_operand_tokens
, tokens
);
14087 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14088 NBITS is the number of significant bits in VAL. */
14090 static unsigned long
14091 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14096 val
&= (1U << nbits
) - 1;
14097 if (nbits
== 16 || nbits
== 9)
14099 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14102 else if (nbits
== 15)
14104 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14107 else if (nbits
== 6)
14109 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14112 return (extval
<< 16) | val
;
14115 /* Like decode_mips16_operand, but require the operand to be defined and
14116 require it to be an integer. */
14118 static const struct mips_int_operand
*
14119 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14121 const struct mips_operand
*operand
;
14123 operand
= decode_mips16_operand (type
, extended_p
);
14124 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14126 return (const struct mips_int_operand
*) operand
;
14129 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14132 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14133 bfd_reloc_code_real_type reloc
, offsetT sval
)
14135 int min_val
, max_val
;
14137 min_val
= mips_int_operand_min (operand
);
14138 max_val
= mips_int_operand_max (operand
);
14139 if (reloc
!= BFD_RELOC_UNUSED
)
14142 sval
= SEXT_16BIT (sval
);
14147 return (sval
>= min_val
14149 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14152 /* Install immediate value VAL into MIPS16 instruction *INSN,
14153 extending it if necessary. The instruction in *INSN may
14154 already be extended.
14156 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14157 if none. In the former case, VAL is a 16-bit number with no
14158 defined signedness.
14160 TYPE is the type of the immediate field. USER_INSN_LENGTH
14161 is the length that the user requested, or 0 if none. */
14164 mips16_immed (const char *file
, unsigned int line
, int type
,
14165 bfd_reloc_code_real_type reloc
, offsetT val
,
14166 unsigned int user_insn_length
, unsigned long *insn
)
14168 const struct mips_int_operand
*operand
;
14169 unsigned int uval
, length
;
14171 operand
= mips16_immed_operand (type
, FALSE
);
14172 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14174 /* We need an extended instruction. */
14175 if (user_insn_length
== 2)
14176 as_bad_where (file
, line
, _("invalid unextended operand value"));
14178 *insn
|= MIPS16_EXTEND
;
14180 else if (user_insn_length
== 4)
14182 /* The operand doesn't force an unextended instruction to be extended.
14183 Warn if the user wanted an extended instruction anyway. */
14184 *insn
|= MIPS16_EXTEND
;
14185 as_warn_where (file
, line
,
14186 _("extended operand requested but not required"));
14189 length
= mips16_opcode_length (*insn
);
14192 operand
= mips16_immed_operand (type
, TRUE
);
14193 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14194 as_bad_where (file
, line
,
14195 _("operand value out of range for instruction"));
14197 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14198 if (length
== 2 || operand
->root
.lsb
!= 0)
14199 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14201 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14204 struct percent_op_match
14207 bfd_reloc_code_real_type reloc
;
14210 static const struct percent_op_match mips_percent_op
[] =
14212 {"%lo", BFD_RELOC_LO16
},
14213 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14214 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14215 {"%call16", BFD_RELOC_MIPS_CALL16
},
14216 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14217 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14218 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14219 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14220 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14221 {"%got", BFD_RELOC_MIPS_GOT16
},
14222 {"%gp_rel", BFD_RELOC_GPREL16
},
14223 {"%gprel", BFD_RELOC_GPREL16
},
14224 {"%half", BFD_RELOC_16
},
14225 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14226 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14227 {"%neg", BFD_RELOC_MIPS_SUB
},
14228 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14229 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14230 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14231 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14232 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14233 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14234 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14235 {"%hi", BFD_RELOC_HI16_S
},
14236 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14237 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14240 static const struct percent_op_match mips16_percent_op
[] =
14242 {"%lo", BFD_RELOC_MIPS16_LO16
},
14243 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14244 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14245 {"%got", BFD_RELOC_MIPS16_GOT16
},
14246 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14247 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14248 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14249 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14250 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14251 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14252 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14253 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14254 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14258 /* Return true if *STR points to a relocation operator. When returning true,
14259 move *STR over the operator and store its relocation code in *RELOC.
14260 Leave both *STR and *RELOC alone when returning false. */
14263 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14265 const struct percent_op_match
*percent_op
;
14268 if (mips_opts
.mips16
)
14270 percent_op
= mips16_percent_op
;
14271 limit
= ARRAY_SIZE (mips16_percent_op
);
14275 percent_op
= mips_percent_op
;
14276 limit
= ARRAY_SIZE (mips_percent_op
);
14279 for (i
= 0; i
< limit
; i
++)
14280 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14282 int len
= strlen (percent_op
[i
].str
);
14284 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14287 *str
+= strlen (percent_op
[i
].str
);
14288 *reloc
= percent_op
[i
].reloc
;
14290 /* Check whether the output BFD supports this relocation.
14291 If not, issue an error and fall back on something safe. */
14292 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14294 as_bad (_("relocation %s isn't supported by the current ABI"),
14295 percent_op
[i
].str
);
14296 *reloc
= BFD_RELOC_UNUSED
;
14304 /* Parse string STR as a 16-bit relocatable operand. Store the
14305 expression in *EP and the relocations in the array starting
14306 at RELOC. Return the number of relocation operators used.
14308 On exit, EXPR_END points to the first character after the expression. */
14311 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14314 bfd_reloc_code_real_type reversed_reloc
[3];
14315 size_t reloc_index
, i
;
14316 int crux_depth
, str_depth
;
14319 /* Search for the start of the main expression, recoding relocations
14320 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14321 of the main expression and with CRUX_DEPTH containing the number
14322 of open brackets at that point. */
14329 crux_depth
= str_depth
;
14331 /* Skip over whitespace and brackets, keeping count of the number
14333 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14338 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14339 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14341 my_getExpression (ep
, crux
);
14344 /* Match every open bracket. */
14345 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14349 if (crux_depth
> 0)
14350 as_bad (_("unclosed '('"));
14354 if (reloc_index
!= 0)
14356 prev_reloc_op_frag
= frag_now
;
14357 for (i
= 0; i
< reloc_index
; i
++)
14358 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14361 return reloc_index
;
14365 my_getExpression (expressionS
*ep
, char *str
)
14369 save_in
= input_line_pointer
;
14370 input_line_pointer
= str
;
14372 expr_end
= input_line_pointer
;
14373 input_line_pointer
= save_in
;
14377 md_atof (int type
, char *litP
, int *sizeP
)
14379 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14383 md_number_to_chars (char *buf
, valueT val
, int n
)
14385 if (target_big_endian
)
14386 number_to_chars_bigendian (buf
, val
, n
);
14388 number_to_chars_littleendian (buf
, val
, n
);
14391 static int support_64bit_objects(void)
14393 const char **list
, **l
;
14396 list
= bfd_target_list ();
14397 for (l
= list
; *l
!= NULL
; l
++)
14398 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14399 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14401 yes
= (*l
!= NULL
);
14406 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14407 NEW_VALUE. Warn if another value was already specified. Note:
14408 we have to defer parsing the -march and -mtune arguments in order
14409 to handle 'from-abi' correctly, since the ABI might be specified
14410 in a later argument. */
14413 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14415 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14416 as_warn (_("a different %s was already specified, is now %s"),
14417 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14420 *string_ptr
= new_value
;
14424 md_parse_option (int c
, const char *arg
)
14428 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14429 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14431 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14432 c
== mips_ases
[i
].option_on
);
14438 case OPTION_CONSTRUCT_FLOATS
:
14439 mips_disable_float_construction
= 0;
14442 case OPTION_NO_CONSTRUCT_FLOATS
:
14443 mips_disable_float_construction
= 1;
14455 target_big_endian
= 1;
14459 target_big_endian
= 0;
14465 else if (arg
[0] == '0')
14467 else if (arg
[0] == '1')
14477 mips_debug
= atoi (arg
);
14481 file_mips_opts
.isa
= ISA_MIPS1
;
14485 file_mips_opts
.isa
= ISA_MIPS2
;
14489 file_mips_opts
.isa
= ISA_MIPS3
;
14493 file_mips_opts
.isa
= ISA_MIPS4
;
14497 file_mips_opts
.isa
= ISA_MIPS5
;
14500 case OPTION_MIPS32
:
14501 file_mips_opts
.isa
= ISA_MIPS32
;
14504 case OPTION_MIPS32R2
:
14505 file_mips_opts
.isa
= ISA_MIPS32R2
;
14508 case OPTION_MIPS32R3
:
14509 file_mips_opts
.isa
= ISA_MIPS32R3
;
14512 case OPTION_MIPS32R5
:
14513 file_mips_opts
.isa
= ISA_MIPS32R5
;
14516 case OPTION_MIPS32R6
:
14517 file_mips_opts
.isa
= ISA_MIPS32R6
;
14520 case OPTION_MIPS64R2
:
14521 file_mips_opts
.isa
= ISA_MIPS64R2
;
14524 case OPTION_MIPS64R3
:
14525 file_mips_opts
.isa
= ISA_MIPS64R3
;
14528 case OPTION_MIPS64R5
:
14529 file_mips_opts
.isa
= ISA_MIPS64R5
;
14532 case OPTION_MIPS64R6
:
14533 file_mips_opts
.isa
= ISA_MIPS64R6
;
14536 case OPTION_MIPS64
:
14537 file_mips_opts
.isa
= ISA_MIPS64
;
14541 mips_set_option_string (&mips_tune_string
, arg
);
14545 mips_set_option_string (&mips_arch_string
, arg
);
14549 mips_set_option_string (&mips_arch_string
, "4650");
14550 mips_set_option_string (&mips_tune_string
, "4650");
14553 case OPTION_NO_M4650
:
14557 mips_set_option_string (&mips_arch_string
, "4010");
14558 mips_set_option_string (&mips_tune_string
, "4010");
14561 case OPTION_NO_M4010
:
14565 mips_set_option_string (&mips_arch_string
, "4100");
14566 mips_set_option_string (&mips_tune_string
, "4100");
14569 case OPTION_NO_M4100
:
14573 mips_set_option_string (&mips_arch_string
, "3900");
14574 mips_set_option_string (&mips_tune_string
, "3900");
14577 case OPTION_NO_M3900
:
14580 case OPTION_MICROMIPS
:
14581 if (file_mips_opts
.mips16
== 1)
14583 as_bad (_("-mmicromips cannot be used with -mips16"));
14586 file_mips_opts
.micromips
= 1;
14587 mips_no_prev_insn ();
14590 case OPTION_NO_MICROMIPS
:
14591 file_mips_opts
.micromips
= 0;
14592 mips_no_prev_insn ();
14595 case OPTION_MIPS16
:
14596 if (file_mips_opts
.micromips
== 1)
14598 as_bad (_("-mips16 cannot be used with -micromips"));
14601 file_mips_opts
.mips16
= 1;
14602 mips_no_prev_insn ();
14605 case OPTION_NO_MIPS16
:
14606 file_mips_opts
.mips16
= 0;
14607 mips_no_prev_insn ();
14610 case OPTION_FIX_24K
:
14614 case OPTION_NO_FIX_24K
:
14618 case OPTION_FIX_RM7000
:
14619 mips_fix_rm7000
= 1;
14622 case OPTION_NO_FIX_RM7000
:
14623 mips_fix_rm7000
= 0;
14626 case OPTION_FIX_LOONGSON2F_JUMP
:
14627 mips_fix_loongson2f_jump
= TRUE
;
14630 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14631 mips_fix_loongson2f_jump
= FALSE
;
14634 case OPTION_FIX_LOONGSON2F_NOP
:
14635 mips_fix_loongson2f_nop
= TRUE
;
14638 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14639 mips_fix_loongson2f_nop
= FALSE
;
14642 case OPTION_FIX_VR4120
:
14643 mips_fix_vr4120
= 1;
14646 case OPTION_NO_FIX_VR4120
:
14647 mips_fix_vr4120
= 0;
14650 case OPTION_FIX_VR4130
:
14651 mips_fix_vr4130
= 1;
14654 case OPTION_NO_FIX_VR4130
:
14655 mips_fix_vr4130
= 0;
14658 case OPTION_FIX_CN63XXP1
:
14659 mips_fix_cn63xxp1
= TRUE
;
14662 case OPTION_NO_FIX_CN63XXP1
:
14663 mips_fix_cn63xxp1
= FALSE
;
14666 case OPTION_RELAX_BRANCH
:
14667 mips_relax_branch
= 1;
14670 case OPTION_NO_RELAX_BRANCH
:
14671 mips_relax_branch
= 0;
14674 case OPTION_IGNORE_BRANCH_ISA
:
14675 mips_ignore_branch_isa
= TRUE
;
14678 case OPTION_NO_IGNORE_BRANCH_ISA
:
14679 mips_ignore_branch_isa
= FALSE
;
14682 case OPTION_INSN32
:
14683 file_mips_opts
.insn32
= TRUE
;
14686 case OPTION_NO_INSN32
:
14687 file_mips_opts
.insn32
= FALSE
;
14690 case OPTION_MSHARED
:
14691 mips_in_shared
= TRUE
;
14694 case OPTION_MNO_SHARED
:
14695 mips_in_shared
= FALSE
;
14698 case OPTION_MSYM32
:
14699 file_mips_opts
.sym32
= TRUE
;
14702 case OPTION_MNO_SYM32
:
14703 file_mips_opts
.sym32
= FALSE
;
14706 /* When generating ELF code, we permit -KPIC and -call_shared to
14707 select SVR4_PIC, and -non_shared to select no PIC. This is
14708 intended to be compatible with Irix 5. */
14709 case OPTION_CALL_SHARED
:
14710 mips_pic
= SVR4_PIC
;
14711 mips_abicalls
= TRUE
;
14714 case OPTION_CALL_NONPIC
:
14716 mips_abicalls
= TRUE
;
14719 case OPTION_NON_SHARED
:
14721 mips_abicalls
= FALSE
;
14724 /* The -xgot option tells the assembler to use 32 bit offsets
14725 when accessing the got in SVR4_PIC mode. It is for Irix
14732 g_switch_value
= atoi (arg
);
14736 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14739 mips_abi
= O32_ABI
;
14743 mips_abi
= N32_ABI
;
14747 mips_abi
= N64_ABI
;
14748 if (!support_64bit_objects())
14749 as_fatal (_("no compiled in support for 64 bit object file format"));
14753 file_mips_opts
.gp
= 32;
14757 file_mips_opts
.gp
= 64;
14761 file_mips_opts
.fp
= 32;
14765 file_mips_opts
.fp
= 0;
14769 file_mips_opts
.fp
= 64;
14772 case OPTION_ODD_SPREG
:
14773 file_mips_opts
.oddspreg
= 1;
14776 case OPTION_NO_ODD_SPREG
:
14777 file_mips_opts
.oddspreg
= 0;
14780 case OPTION_SINGLE_FLOAT
:
14781 file_mips_opts
.single_float
= 1;
14784 case OPTION_DOUBLE_FLOAT
:
14785 file_mips_opts
.single_float
= 0;
14788 case OPTION_SOFT_FLOAT
:
14789 file_mips_opts
.soft_float
= 1;
14792 case OPTION_HARD_FLOAT
:
14793 file_mips_opts
.soft_float
= 0;
14797 if (strcmp (arg
, "32") == 0)
14798 mips_abi
= O32_ABI
;
14799 else if (strcmp (arg
, "o64") == 0)
14800 mips_abi
= O64_ABI
;
14801 else if (strcmp (arg
, "n32") == 0)
14802 mips_abi
= N32_ABI
;
14803 else if (strcmp (arg
, "64") == 0)
14805 mips_abi
= N64_ABI
;
14806 if (! support_64bit_objects())
14807 as_fatal (_("no compiled in support for 64 bit object file "
14810 else if (strcmp (arg
, "eabi") == 0)
14811 mips_abi
= EABI_ABI
;
14814 as_fatal (_("invalid abi -mabi=%s"), arg
);
14819 case OPTION_M7000_HILO_FIX
:
14820 mips_7000_hilo_fix
= TRUE
;
14823 case OPTION_MNO_7000_HILO_FIX
:
14824 mips_7000_hilo_fix
= FALSE
;
14827 case OPTION_MDEBUG
:
14828 mips_flag_mdebug
= TRUE
;
14831 case OPTION_NO_MDEBUG
:
14832 mips_flag_mdebug
= FALSE
;
14836 mips_flag_pdr
= TRUE
;
14839 case OPTION_NO_PDR
:
14840 mips_flag_pdr
= FALSE
;
14843 case OPTION_MVXWORKS_PIC
:
14844 mips_pic
= VXWORKS_PIC
;
14848 if (strcmp (arg
, "2008") == 0)
14850 else if (strcmp (arg
, "legacy") == 0)
14854 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14863 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14868 /* Set up globals to tune for the ISA or processor described by INFO. */
14871 mips_set_tune (const struct mips_cpu_info
*info
)
14874 mips_tune
= info
->cpu
;
14879 mips_after_parse_args (void)
14881 const struct mips_cpu_info
*arch_info
= 0;
14882 const struct mips_cpu_info
*tune_info
= 0;
14884 /* GP relative stuff not working for PE */
14885 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14887 if (g_switch_seen
&& g_switch_value
!= 0)
14888 as_bad (_("-G not supported in this configuration"));
14889 g_switch_value
= 0;
14892 if (mips_abi
== NO_ABI
)
14893 mips_abi
= MIPS_DEFAULT_ABI
;
14895 /* The following code determines the architecture.
14896 Similar code was added to GCC 3.3 (see override_options() in
14897 config/mips/mips.c). The GAS and GCC code should be kept in sync
14898 as much as possible. */
14900 if (mips_arch_string
!= 0)
14901 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14903 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14905 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14906 ISA level specified by -mipsN, while arch_info->isa contains
14907 the -march selection (if any). */
14908 if (arch_info
!= 0)
14910 /* -march takes precedence over -mipsN, since it is more descriptive.
14911 There's no harm in specifying both as long as the ISA levels
14913 if (file_mips_opts
.isa
!= arch_info
->isa
)
14914 as_bad (_("-%s conflicts with the other architecture options,"
14915 " which imply -%s"),
14916 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14917 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14920 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14923 if (arch_info
== 0)
14925 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14926 gas_assert (arch_info
);
14929 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14930 as_bad (_("-march=%s is not compatible with the selected ABI"),
14933 file_mips_opts
.arch
= arch_info
->cpu
;
14934 file_mips_opts
.isa
= arch_info
->isa
;
14936 /* Set up initial mips_opts state. */
14937 mips_opts
= file_mips_opts
;
14939 /* The register size inference code is now placed in
14940 file_mips_check_options. */
14942 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14944 if (mips_tune_string
!= 0)
14945 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14947 if (tune_info
== 0)
14948 mips_set_tune (arch_info
);
14950 mips_set_tune (tune_info
);
14952 if (mips_flag_mdebug
< 0)
14953 mips_flag_mdebug
= 0;
14957 mips_init_after_args (void)
14959 /* initialize opcodes */
14960 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14961 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14965 md_pcrel_from (fixS
*fixP
)
14967 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14968 switch (fixP
->fx_r_type
)
14970 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14971 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14972 /* Return the address of the delay slot. */
14975 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14976 case BFD_RELOC_MICROMIPS_JMP
:
14977 case BFD_RELOC_MIPS16_16_PCREL_S1
:
14978 case BFD_RELOC_16_PCREL_S2
:
14979 case BFD_RELOC_MIPS_21_PCREL_S2
:
14980 case BFD_RELOC_MIPS_26_PCREL_S2
:
14981 case BFD_RELOC_MIPS_JMP
:
14982 /* Return the address of the delay slot. */
14985 case BFD_RELOC_MIPS_18_PCREL_S3
:
14986 /* Return the aligned address of the doubleword containing
14987 the instruction. */
14995 /* This is called before the symbol table is processed. In order to
14996 work with gcc when using mips-tfile, we must keep all local labels.
14997 However, in other cases, we want to discard them. If we were
14998 called with -g, but we didn't see any debugging information, it may
14999 mean that gcc is smuggling debugging information through to
15000 mips-tfile, in which case we must generate all local labels. */
15003 mips_frob_file_before_adjust (void)
15005 #ifndef NO_ECOFF_DEBUGGING
15006 if (ECOFF_DEBUGGING
15008 && ! ecoff_debugging_seen
)
15009 flag_keep_locals
= 1;
15013 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15014 the corresponding LO16 reloc. This is called before md_apply_fix and
15015 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15016 relocation operators.
15018 For our purposes, a %lo() expression matches a %got() or %hi()
15021 (a) it refers to the same symbol; and
15022 (b) the offset applied in the %lo() expression is no lower than
15023 the offset applied in the %got() or %hi().
15025 (b) allows us to cope with code like:
15028 lh $4,%lo(foo+2)($4)
15030 ...which is legal on RELA targets, and has a well-defined behaviour
15031 if the user knows that adding 2 to "foo" will not induce a carry to
15034 When several %lo()s match a particular %got() or %hi(), we use the
15035 following rules to distinguish them:
15037 (1) %lo()s with smaller offsets are a better match than %lo()s with
15040 (2) %lo()s with no matching %got() or %hi() are better than those
15041 that already have a matching %got() or %hi().
15043 (3) later %lo()s are better than earlier %lo()s.
15045 These rules are applied in order.
15047 (1) means, among other things, that %lo()s with identical offsets are
15048 chosen if they exist.
15050 (2) means that we won't associate several high-part relocations with
15051 the same low-part relocation unless there's no alternative. Having
15052 several high parts for the same low part is a GNU extension; this rule
15053 allows careful users to avoid it.
15055 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15056 with the last high-part relocation being at the front of the list.
15057 It therefore makes sense to choose the last matching low-part
15058 relocation, all other things being equal. It's also easier
15059 to code that way. */
15062 mips_frob_file (void)
15064 struct mips_hi_fixup
*l
;
15065 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15067 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15069 segment_info_type
*seginfo
;
15070 bfd_boolean matched_lo_p
;
15071 fixS
**hi_pos
, **lo_pos
, **pos
;
15073 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15075 /* If a GOT16 relocation turns out to be against a global symbol,
15076 there isn't supposed to be a matching LO. Ignore %gots against
15077 constants; we'll report an error for those later. */
15078 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15079 && !(l
->fixp
->fx_addsy
15080 && pic_need_relax (l
->fixp
->fx_addsy
)))
15083 /* Check quickly whether the next fixup happens to be a matching %lo. */
15084 if (fixup_has_matching_lo_p (l
->fixp
))
15087 seginfo
= seg_info (l
->seg
);
15089 /* Set HI_POS to the position of this relocation in the chain.
15090 Set LO_POS to the position of the chosen low-part relocation.
15091 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15092 relocation that matches an immediately-preceding high-part
15096 matched_lo_p
= FALSE
;
15097 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15099 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15101 if (*pos
== l
->fixp
)
15104 if ((*pos
)->fx_r_type
== looking_for_rtype
15105 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15106 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15108 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15110 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15113 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15114 && fixup_has_matching_lo_p (*pos
));
15117 /* If we found a match, remove the high-part relocation from its
15118 current position and insert it before the low-part relocation.
15119 Make the offsets match so that fixup_has_matching_lo_p()
15122 We don't warn about unmatched high-part relocations since some
15123 versions of gcc have been known to emit dead "lui ...%hi(...)"
15125 if (lo_pos
!= NULL
)
15127 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15128 if (l
->fixp
->fx_next
!= *lo_pos
)
15130 *hi_pos
= l
->fixp
->fx_next
;
15131 l
->fixp
->fx_next
= *lo_pos
;
15139 mips_force_relocation (fixS
*fixp
)
15141 if (generic_force_reloc (fixp
))
15144 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15145 so that the linker relaxation can update targets. */
15146 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15147 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15148 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15151 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15152 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15153 microMIPS symbols so that we can do cross-mode branch diagnostics
15154 and BAL to JALX conversion by the linker. */
15155 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15156 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15157 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15159 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15162 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15163 if (ISA_IS_R6 (file_mips_opts
.isa
)
15164 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15165 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15166 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15167 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15168 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15169 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15170 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15176 /* Implement TC_FORCE_RELOCATION_ABS. */
15179 mips_force_relocation_abs (fixS
*fixp
)
15181 if (generic_force_reloc (fixp
))
15184 /* These relocations do not have enough bits in the in-place addend
15185 to hold an arbitrary absolute section's offset. */
15186 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15192 /* Read the instruction associated with RELOC from BUF. */
15194 static unsigned int
15195 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15197 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15198 return read_compressed_insn (buf
, 4);
15200 return read_insn (buf
);
15203 /* Write instruction INSN to BUF, given that it has been relocated
15207 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15208 unsigned long insn
)
15210 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15211 write_compressed_insn (buf
, insn
, 4);
15213 write_insn (buf
, insn
);
15216 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15217 to a symbol in another ISA mode, which cannot be converted to JALX. */
15220 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15222 unsigned long opcode
;
15226 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15229 other
= S_GET_OTHER (fixP
->fx_addsy
);
15230 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15231 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15232 switch (fixP
->fx_r_type
)
15234 case BFD_RELOC_MIPS_JMP
:
15235 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15236 case BFD_RELOC_MICROMIPS_JMP
:
15237 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15243 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15244 jump to a symbol in the same ISA mode. */
15247 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15249 unsigned long opcode
;
15253 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15256 other
= S_GET_OTHER (fixP
->fx_addsy
);
15257 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15258 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15259 switch (fixP
->fx_r_type
)
15261 case BFD_RELOC_MIPS_JMP
:
15262 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15263 case BFD_RELOC_MIPS16_JMP
:
15264 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15265 case BFD_RELOC_MICROMIPS_JMP
:
15266 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15272 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15273 to a symbol whose value plus addend is not aligned according to the
15274 ultimate (after linker relaxation) jump instruction's immediate field
15275 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15276 regular MIPS code, to (1 << 2). */
15279 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15281 bfd_boolean micro_to_mips_p
;
15285 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15288 other
= S_GET_OTHER (fixP
->fx_addsy
);
15289 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15290 val
+= fixP
->fx_offset
;
15291 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15292 && !ELF_ST_IS_MICROMIPS (other
));
15293 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15294 != ELF_ST_IS_COMPRESSED (other
));
15297 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15298 to a symbol whose annotation indicates another ISA mode. For absolute
15299 symbols check the ISA bit instead.
15301 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15302 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15303 MIPS symbols and associated with BAL instructions as these instructions
15304 may be be converted to JALX by the linker. */
15307 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15309 bfd_boolean absolute_p
;
15310 unsigned long opcode
;
15316 if (mips_ignore_branch_isa
)
15319 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15322 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15323 absolute_p
= bfd_is_abs_section (symsec
);
15325 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15326 other
= S_GET_OTHER (fixP
->fx_addsy
);
15328 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15329 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15330 switch (fixP
->fx_r_type
)
15332 case BFD_RELOC_16_PCREL_S2
:
15333 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15334 && opcode
!= 0x0411);
15335 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15336 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15337 && opcode
!= 0x4060);
15338 case BFD_RELOC_MIPS_21_PCREL_S2
:
15339 case BFD_RELOC_MIPS_26_PCREL_S2
:
15340 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15341 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15342 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15343 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15344 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15345 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15351 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15352 branch instruction pointed to by FIXP is not aligned according to the
15353 branch instruction's immediate field requirement. We need the addend
15354 to preserve the ISA bit and also the sum must not have bit 2 set. We
15355 must explicitly OR in the ISA bit from symbol annotation as the bit
15356 won't be set in the symbol's value then. */
15359 fix_bad_misaligned_branch_p (fixS
*fixP
)
15361 bfd_boolean absolute_p
;
15368 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15371 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15372 absolute_p
= bfd_is_abs_section (symsec
);
15374 val
= S_GET_VALUE (fixP
->fx_addsy
);
15375 other
= S_GET_OTHER (fixP
->fx_addsy
);
15376 off
= fixP
->fx_offset
;
15378 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15379 val
|= ELF_ST_IS_COMPRESSED (other
);
15381 return (val
& 0x3) != isa_bit
;
15384 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15385 and its calculated value VAL. */
15388 fix_validate_branch (fixS
*fixP
, valueT val
)
15390 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15392 _("branch to misaligned address (0x%lx)"),
15393 (long) (val
+ md_pcrel_from (fixP
)));
15394 else if (fix_bad_cross_mode_branch_p (fixP
))
15395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15396 _("branch to a symbol in another ISA mode"));
15397 else if (fix_bad_misaligned_branch_p (fixP
))
15398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15399 _("branch to misaligned address (0x%lx)"),
15400 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15401 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15403 _("cannot encode misaligned addend "
15404 "in the relocatable field (0x%lx)"),
15405 (long) fixP
->fx_offset
);
15408 /* Apply a fixup to the object file. */
15411 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15414 unsigned long insn
;
15415 reloc_howto_type
*howto
;
15417 if (fixP
->fx_pcrel
)
15418 switch (fixP
->fx_r_type
)
15420 case BFD_RELOC_16_PCREL_S2
:
15421 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15422 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15423 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15424 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15425 case BFD_RELOC_32_PCREL
:
15426 case BFD_RELOC_MIPS_21_PCREL_S2
:
15427 case BFD_RELOC_MIPS_26_PCREL_S2
:
15428 case BFD_RELOC_MIPS_18_PCREL_S3
:
15429 case BFD_RELOC_MIPS_19_PCREL_S2
:
15430 case BFD_RELOC_HI16_S_PCREL
:
15431 case BFD_RELOC_LO16_PCREL
:
15435 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15440 _("PC-relative reference to a different section"));
15444 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15445 that have no MIPS ELF equivalent. */
15446 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15448 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15453 gas_assert (fixP
->fx_size
== 2
15454 || fixP
->fx_size
== 4
15455 || fixP
->fx_r_type
== BFD_RELOC_8
15456 || fixP
->fx_r_type
== BFD_RELOC_16
15457 || fixP
->fx_r_type
== BFD_RELOC_64
15458 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15459 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15460 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15461 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15462 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15463 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15464 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15466 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15468 /* Don't treat parts of a composite relocation as done. There are two
15471 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15472 should nevertheless be emitted if the first part is.
15474 (2) In normal usage, composite relocations are never assembly-time
15475 constants. The easiest way of dealing with the pathological
15476 exceptions is to generate a relocation against STN_UNDEF and
15477 leave everything up to the linker. */
15478 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15481 switch (fixP
->fx_r_type
)
15483 case BFD_RELOC_MIPS_TLS_GD
:
15484 case BFD_RELOC_MIPS_TLS_LDM
:
15485 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15486 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15487 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15488 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15489 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15490 case BFD_RELOC_MIPS_TLS_TPREL32
:
15491 case BFD_RELOC_MIPS_TLS_TPREL64
:
15492 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15493 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15494 case BFD_RELOC_MICROMIPS_TLS_GD
:
15495 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15496 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15497 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15498 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15499 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15500 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15501 case BFD_RELOC_MIPS16_TLS_GD
:
15502 case BFD_RELOC_MIPS16_TLS_LDM
:
15503 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15504 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15505 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15506 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15507 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15508 if (fixP
->fx_addsy
)
15509 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15512 _("TLS relocation against a constant"));
15515 case BFD_RELOC_MIPS_JMP
:
15516 case BFD_RELOC_MIPS16_JMP
:
15517 case BFD_RELOC_MICROMIPS_JMP
:
15521 gas_assert (!fixP
->fx_done
);
15523 /* Shift is 2, unusually, for microMIPS JALX. */
15524 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15525 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15530 if (fix_bad_cross_mode_jump_p (fixP
))
15531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15532 _("jump to a symbol in another ISA mode"));
15533 else if (fix_bad_same_mode_jalx_p (fixP
))
15534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15535 _("JALX to a symbol in the same ISA mode"));
15536 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15538 _("jump to misaligned address (0x%lx)"),
15539 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15540 + fixP
->fx_offset
));
15541 else if (HAVE_IN_PLACE_ADDENDS
15542 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15543 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15544 _("cannot encode misaligned addend "
15545 "in the relocatable field (0x%lx)"),
15546 (long) fixP
->fx_offset
);
15548 /* Fall through. */
15550 case BFD_RELOC_MIPS_SHIFT5
:
15551 case BFD_RELOC_MIPS_SHIFT6
:
15552 case BFD_RELOC_MIPS_GOT_DISP
:
15553 case BFD_RELOC_MIPS_GOT_PAGE
:
15554 case BFD_RELOC_MIPS_GOT_OFST
:
15555 case BFD_RELOC_MIPS_SUB
:
15556 case BFD_RELOC_MIPS_INSERT_A
:
15557 case BFD_RELOC_MIPS_INSERT_B
:
15558 case BFD_RELOC_MIPS_DELETE
:
15559 case BFD_RELOC_MIPS_HIGHEST
:
15560 case BFD_RELOC_MIPS_HIGHER
:
15561 case BFD_RELOC_MIPS_SCN_DISP
:
15562 case BFD_RELOC_MIPS_REL16
:
15563 case BFD_RELOC_MIPS_RELGOT
:
15564 case BFD_RELOC_MIPS_JALR
:
15565 case BFD_RELOC_HI16
:
15566 case BFD_RELOC_HI16_S
:
15567 case BFD_RELOC_LO16
:
15568 case BFD_RELOC_GPREL16
:
15569 case BFD_RELOC_MIPS_LITERAL
:
15570 case BFD_RELOC_MIPS_CALL16
:
15571 case BFD_RELOC_MIPS_GOT16
:
15572 case BFD_RELOC_GPREL32
:
15573 case BFD_RELOC_MIPS_GOT_HI16
:
15574 case BFD_RELOC_MIPS_GOT_LO16
:
15575 case BFD_RELOC_MIPS_CALL_HI16
:
15576 case BFD_RELOC_MIPS_CALL_LO16
:
15577 case BFD_RELOC_HI16_S_PCREL
:
15578 case BFD_RELOC_LO16_PCREL
:
15579 case BFD_RELOC_MIPS16_GPREL
:
15580 case BFD_RELOC_MIPS16_GOT16
:
15581 case BFD_RELOC_MIPS16_CALL16
:
15582 case BFD_RELOC_MIPS16_HI16
:
15583 case BFD_RELOC_MIPS16_HI16_S
:
15584 case BFD_RELOC_MIPS16_LO16
:
15585 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15586 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15587 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15588 case BFD_RELOC_MICROMIPS_SUB
:
15589 case BFD_RELOC_MICROMIPS_HIGHEST
:
15590 case BFD_RELOC_MICROMIPS_HIGHER
:
15591 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15592 case BFD_RELOC_MICROMIPS_JALR
:
15593 case BFD_RELOC_MICROMIPS_HI16
:
15594 case BFD_RELOC_MICROMIPS_HI16_S
:
15595 case BFD_RELOC_MICROMIPS_LO16
:
15596 case BFD_RELOC_MICROMIPS_GPREL16
:
15597 case BFD_RELOC_MICROMIPS_LITERAL
:
15598 case BFD_RELOC_MICROMIPS_CALL16
:
15599 case BFD_RELOC_MICROMIPS_GOT16
:
15600 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15601 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15602 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15603 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15604 case BFD_RELOC_MIPS_EH
:
15609 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15611 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15612 if (mips16_reloc_p (fixP
->fx_r_type
))
15613 insn
|= mips16_immed_extend (value
, 16);
15615 insn
|= (value
& 0xffff);
15616 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15620 _("unsupported constant in relocation"));
15625 /* This is handled like BFD_RELOC_32, but we output a sign
15626 extended value if we are only 32 bits. */
15629 if (8 <= sizeof (valueT
))
15630 md_number_to_chars (buf
, *valP
, 8);
15635 if ((*valP
& 0x80000000) != 0)
15639 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15640 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15645 case BFD_RELOC_RVA
:
15647 case BFD_RELOC_32_PCREL
:
15650 /* If we are deleting this reloc entry, we must fill in the
15651 value now. This can happen if we have a .word which is not
15652 resolved when it appears but is later defined. */
15654 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15657 case BFD_RELOC_MIPS_21_PCREL_S2
:
15658 fix_validate_branch (fixP
, *valP
);
15659 if (!fixP
->fx_done
)
15662 if (*valP
+ 0x400000 <= 0x7fffff)
15664 insn
= read_insn (buf
);
15665 insn
|= (*valP
>> 2) & 0x1fffff;
15666 write_insn (buf
, insn
);
15669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15670 _("branch out of range"));
15673 case BFD_RELOC_MIPS_26_PCREL_S2
:
15674 fix_validate_branch (fixP
, *valP
);
15675 if (!fixP
->fx_done
)
15678 if (*valP
+ 0x8000000 <= 0xfffffff)
15680 insn
= read_insn (buf
);
15681 insn
|= (*valP
>> 2) & 0x3ffffff;
15682 write_insn (buf
, insn
);
15685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15686 _("branch out of range"));
15689 case BFD_RELOC_MIPS_18_PCREL_S3
:
15690 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15692 _("PC-relative access using misaligned symbol (%lx)"),
15693 (long) S_GET_VALUE (fixP
->fx_addsy
));
15694 if ((fixP
->fx_offset
& 0x7) != 0)
15695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15696 _("PC-relative access using misaligned offset (%lx)"),
15697 (long) fixP
->fx_offset
);
15698 if (!fixP
->fx_done
)
15701 if (*valP
+ 0x100000 <= 0x1fffff)
15703 insn
= read_insn (buf
);
15704 insn
|= (*valP
>> 3) & 0x3ffff;
15705 write_insn (buf
, insn
);
15708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15709 _("PC-relative access out of range"));
15712 case BFD_RELOC_MIPS_19_PCREL_S2
:
15713 if ((*valP
& 0x3) != 0)
15714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15715 _("PC-relative access to misaligned address (%lx)"),
15717 if (!fixP
->fx_done
)
15720 if (*valP
+ 0x100000 <= 0x1fffff)
15722 insn
= read_insn (buf
);
15723 insn
|= (*valP
>> 2) & 0x7ffff;
15724 write_insn (buf
, insn
);
15727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15728 _("PC-relative access out of range"));
15731 case BFD_RELOC_16_PCREL_S2
:
15732 fix_validate_branch (fixP
, *valP
);
15734 /* We need to save the bits in the instruction since fixup_segment()
15735 might be deleting the relocation entry (i.e., a branch within
15736 the current segment). */
15737 if (! fixP
->fx_done
)
15740 /* Update old instruction data. */
15741 insn
= read_insn (buf
);
15743 if (*valP
+ 0x20000 <= 0x3ffff)
15745 insn
|= (*valP
>> 2) & 0xffff;
15746 write_insn (buf
, insn
);
15748 else if (fixP
->fx_tcbit2
15750 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15751 && (fixP
->fx_frag
->fr_address
15752 < text_section
->vma
+ bfd_get_section_size (text_section
))
15753 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15754 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15755 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15757 /* The branch offset is too large. If this is an
15758 unconditional branch, and we are not generating PIC code,
15759 we can convert it to an absolute jump instruction. */
15760 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15761 insn
= 0x0c000000; /* jal */
15763 insn
= 0x08000000; /* j */
15764 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15766 fixP
->fx_addsy
= section_symbol (text_section
);
15767 *valP
+= md_pcrel_from (fixP
);
15768 write_insn (buf
, insn
);
15772 /* If we got here, we have branch-relaxation disabled,
15773 and there's nothing we can do to fix this instruction
15774 without turning it into a longer sequence. */
15775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15776 _("branch out of range"));
15780 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15781 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15782 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15783 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15784 gas_assert (!fixP
->fx_done
);
15785 if (fix_bad_cross_mode_branch_p (fixP
))
15786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15787 _("branch to a symbol in another ISA mode"));
15788 else if (fixP
->fx_addsy
15789 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15790 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15791 && (fixP
->fx_offset
& 0x1) != 0)
15792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15793 _("branch to misaligned address (0x%lx)"),
15794 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15795 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15797 _("cannot encode misaligned addend "
15798 "in the relocatable field (0x%lx)"),
15799 (long) fixP
->fx_offset
);
15802 case BFD_RELOC_VTABLE_INHERIT
:
15805 && !S_IS_DEFINED (fixP
->fx_addsy
)
15806 && !S_IS_WEAK (fixP
->fx_addsy
))
15807 S_SET_WEAK (fixP
->fx_addsy
);
15810 case BFD_RELOC_NONE
:
15811 case BFD_RELOC_VTABLE_ENTRY
:
15819 /* Remember value for tc_gen_reloc. */
15820 fixP
->fx_addnumber
= *valP
;
15830 c
= get_symbol_name (&name
);
15831 p
= (symbolS
*) symbol_find_or_make (name
);
15832 (void) restore_line_pointer (c
);
15836 /* Align the current frag to a given power of two. If a particular
15837 fill byte should be used, FILL points to an integer that contains
15838 that byte, otherwise FILL is null.
15840 This function used to have the comment:
15842 The MIPS assembler also automatically adjusts any preceding label.
15844 The implementation therefore applied the adjustment to a maximum of
15845 one label. However, other label adjustments are applied to batches
15846 of labels, and adjusting just one caused problems when new labels
15847 were added for the sake of debugging or unwind information.
15848 We therefore adjust all preceding labels (given as LABELS) instead. */
15851 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15853 mips_emit_delays ();
15854 mips_record_compressed_mode ();
15855 if (fill
== NULL
&& subseg_text_p (now_seg
))
15856 frag_align_code (to
, 0);
15858 frag_align (to
, fill
? *fill
: 0, 0);
15859 record_alignment (now_seg
, to
);
15860 mips_move_labels (labels
, FALSE
);
15863 /* Align to a given power of two. .align 0 turns off the automatic
15864 alignment used by the data creating pseudo-ops. */
15867 s_align (int x ATTRIBUTE_UNUSED
)
15869 int temp
, fill_value
, *fill_ptr
;
15870 long max_alignment
= 28;
15872 /* o Note that the assembler pulls down any immediately preceding label
15873 to the aligned address.
15874 o It's not documented but auto alignment is reinstated by
15875 a .align pseudo instruction.
15876 o Note also that after auto alignment is turned off the mips assembler
15877 issues an error on attempt to assemble an improperly aligned data item.
15880 temp
= get_absolute_expression ();
15881 if (temp
> max_alignment
)
15882 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15885 as_warn (_("alignment negative, 0 assumed"));
15888 if (*input_line_pointer
== ',')
15890 ++input_line_pointer
;
15891 fill_value
= get_absolute_expression ();
15892 fill_ptr
= &fill_value
;
15898 segment_info_type
*si
= seg_info (now_seg
);
15899 struct insn_label_list
*l
= si
->label_list
;
15900 /* Auto alignment should be switched on by next section change. */
15902 mips_align (temp
, fill_ptr
, l
);
15909 demand_empty_rest_of_line ();
15913 s_change_sec (int sec
)
15917 /* The ELF backend needs to know that we are changing sections, so
15918 that .previous works correctly. We could do something like check
15919 for an obj_section_change_hook macro, but that might be confusing
15920 as it would not be appropriate to use it in the section changing
15921 functions in read.c, since obj-elf.c intercepts those. FIXME:
15922 This should be cleaner, somehow. */
15923 obj_elf_section_change_hook ();
15925 mips_emit_delays ();
15936 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15937 demand_empty_rest_of_line ();
15941 seg
= subseg_new (RDATA_SECTION_NAME
,
15942 (subsegT
) get_absolute_expression ());
15943 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15944 | SEC_READONLY
| SEC_RELOC
15946 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15947 record_alignment (seg
, 4);
15948 demand_empty_rest_of_line ();
15952 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15953 bfd_set_section_flags (stdoutput
, seg
,
15954 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15955 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15956 record_alignment (seg
, 4);
15957 demand_empty_rest_of_line ();
15961 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15962 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15963 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15964 record_alignment (seg
, 4);
15965 demand_empty_rest_of_line ();
15973 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15976 char *section_name
;
15981 int section_entry_size
;
15982 int section_alignment
;
15984 saved_ilp
= input_line_pointer
;
15985 endc
= get_symbol_name (§ion_name
);
15986 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15988 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15990 /* Do we have .section Name<,"flags">? */
15991 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15993 /* Just after name is now '\0'. */
15994 (void) restore_line_pointer (endc
);
15995 input_line_pointer
= saved_ilp
;
15996 obj_elf_section (ignore
);
16000 section_name
= xstrdup (section_name
);
16001 c
= restore_line_pointer (endc
);
16003 input_line_pointer
++;
16005 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16007 section_type
= get_absolute_expression ();
16011 if (*input_line_pointer
++ == ',')
16012 section_flag
= get_absolute_expression ();
16016 if (*input_line_pointer
++ == ',')
16017 section_entry_size
= get_absolute_expression ();
16019 section_entry_size
= 0;
16021 if (*input_line_pointer
++ == ',')
16022 section_alignment
= get_absolute_expression ();
16024 section_alignment
= 0;
16026 /* FIXME: really ignore? */
16027 (void) section_alignment
;
16029 /* When using the generic form of .section (as implemented by obj-elf.c),
16030 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16031 traditionally had to fall back on the more common @progbits instead.
16033 There's nothing really harmful in this, since bfd will correct
16034 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16035 means that, for backwards compatibility, the special_section entries
16036 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16038 Even so, we shouldn't force users of the MIPS .section syntax to
16039 incorrectly label the sections as SHT_PROGBITS. The best compromise
16040 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16041 generic type-checking code. */
16042 if (section_type
== SHT_MIPS_DWARF
)
16043 section_type
= SHT_PROGBITS
;
16045 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16046 section_entry_size
, 0, 0, 0);
16048 if (now_seg
->name
!= section_name
)
16049 free (section_name
);
16053 mips_enable_auto_align (void)
16059 s_cons (int log_size
)
16061 segment_info_type
*si
= seg_info (now_seg
);
16062 struct insn_label_list
*l
= si
->label_list
;
16064 mips_emit_delays ();
16065 if (log_size
> 0 && auto_align
)
16066 mips_align (log_size
, 0, l
);
16067 cons (1 << log_size
);
16068 mips_clear_insn_labels ();
16072 s_float_cons (int type
)
16074 segment_info_type
*si
= seg_info (now_seg
);
16075 struct insn_label_list
*l
= si
->label_list
;
16077 mips_emit_delays ();
16082 mips_align (3, 0, l
);
16084 mips_align (2, 0, l
);
16088 mips_clear_insn_labels ();
16091 /* Handle .globl. We need to override it because on Irix 5 you are
16094 where foo is an undefined symbol, to mean that foo should be
16095 considered to be the address of a function. */
16098 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16107 c
= get_symbol_name (&name
);
16108 symbolP
= symbol_find_or_make (name
);
16109 S_SET_EXTERNAL (symbolP
);
16111 *input_line_pointer
= c
;
16112 SKIP_WHITESPACE_AFTER_NAME ();
16114 /* On Irix 5, every global symbol that is not explicitly labelled as
16115 being a function is apparently labelled as being an object. */
16118 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16119 && (*input_line_pointer
!= ','))
16124 c
= get_symbol_name (&secname
);
16125 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16127 as_bad (_("%s: no such section"), secname
);
16128 (void) restore_line_pointer (c
);
16130 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16131 flag
= BSF_FUNCTION
;
16134 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16136 c
= *input_line_pointer
;
16139 input_line_pointer
++;
16140 SKIP_WHITESPACE ();
16141 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16147 demand_empty_rest_of_line ();
16151 s_option (int x ATTRIBUTE_UNUSED
)
16156 c
= get_symbol_name (&opt
);
16160 /* FIXME: What does this mean? */
16162 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16166 i
= atoi (opt
+ 3);
16167 if (i
!= 0 && i
!= 2)
16168 as_bad (_(".option pic%d not supported"), i
);
16169 else if (mips_pic
== VXWORKS_PIC
)
16170 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16175 mips_pic
= SVR4_PIC
;
16176 mips_abicalls
= TRUE
;
16179 if (mips_pic
== SVR4_PIC
)
16181 if (g_switch_seen
&& g_switch_value
!= 0)
16182 as_warn (_("-G may not be used with SVR4 PIC code"));
16183 g_switch_value
= 0;
16184 bfd_set_gp_size (stdoutput
, 0);
16188 as_warn (_("unrecognized option \"%s\""), opt
);
16190 (void) restore_line_pointer (c
);
16191 demand_empty_rest_of_line ();
16194 /* This structure is used to hold a stack of .set values. */
16196 struct mips_option_stack
16198 struct mips_option_stack
*next
;
16199 struct mips_set_options options
;
16202 static struct mips_option_stack
*mips_opts_stack
;
16204 /* Return status for .set/.module option handling. */
16206 enum code_option_type
16208 /* Unrecognized option. */
16209 OPTION_TYPE_BAD
= -1,
16211 /* Ordinary option. */
16212 OPTION_TYPE_NORMAL
,
16214 /* ISA changing option. */
16218 /* Handle common .set/.module options. Return status indicating option
16221 static enum code_option_type
16222 parse_code_option (char * name
)
16224 bfd_boolean isa_set
= FALSE
;
16225 const struct mips_ase
*ase
;
16227 if (strncmp (name
, "at=", 3) == 0)
16229 char *s
= name
+ 3;
16231 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16232 as_bad (_("unrecognized register name `%s'"), s
);
16234 else if (strcmp (name
, "at") == 0)
16235 mips_opts
.at
= ATREG
;
16236 else if (strcmp (name
, "noat") == 0)
16237 mips_opts
.at
= ZERO
;
16238 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16239 mips_opts
.nomove
= 0;
16240 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16241 mips_opts
.nomove
= 1;
16242 else if (strcmp (name
, "bopt") == 0)
16243 mips_opts
.nobopt
= 0;
16244 else if (strcmp (name
, "nobopt") == 0)
16245 mips_opts
.nobopt
= 1;
16246 else if (strcmp (name
, "gp=32") == 0)
16248 else if (strcmp (name
, "gp=64") == 0)
16250 else if (strcmp (name
, "fp=32") == 0)
16252 else if (strcmp (name
, "fp=xx") == 0)
16254 else if (strcmp (name
, "fp=64") == 0)
16256 else if (strcmp (name
, "softfloat") == 0)
16257 mips_opts
.soft_float
= 1;
16258 else if (strcmp (name
, "hardfloat") == 0)
16259 mips_opts
.soft_float
= 0;
16260 else if (strcmp (name
, "singlefloat") == 0)
16261 mips_opts
.single_float
= 1;
16262 else if (strcmp (name
, "doublefloat") == 0)
16263 mips_opts
.single_float
= 0;
16264 else if (strcmp (name
, "nooddspreg") == 0)
16265 mips_opts
.oddspreg
= 0;
16266 else if (strcmp (name
, "oddspreg") == 0)
16267 mips_opts
.oddspreg
= 1;
16268 else if (strcmp (name
, "mips16") == 0
16269 || strcmp (name
, "MIPS-16") == 0)
16270 mips_opts
.mips16
= 1;
16271 else if (strcmp (name
, "nomips16") == 0
16272 || strcmp (name
, "noMIPS-16") == 0)
16273 mips_opts
.mips16
= 0;
16274 else if (strcmp (name
, "micromips") == 0)
16275 mips_opts
.micromips
= 1;
16276 else if (strcmp (name
, "nomicromips") == 0)
16277 mips_opts
.micromips
= 0;
16278 else if (name
[0] == 'n'
16280 && (ase
= mips_lookup_ase (name
+ 2)))
16281 mips_set_ase (ase
, &mips_opts
, FALSE
);
16282 else if ((ase
= mips_lookup_ase (name
)))
16283 mips_set_ase (ase
, &mips_opts
, TRUE
);
16284 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16286 /* Permit the user to change the ISA and architecture on the fly.
16287 Needless to say, misuse can cause serious problems. */
16288 if (strncmp (name
, "arch=", 5) == 0)
16290 const struct mips_cpu_info
*p
;
16292 p
= mips_parse_cpu ("internal use", name
+ 5);
16294 as_bad (_("unknown architecture %s"), name
+ 5);
16297 mips_opts
.arch
= p
->cpu
;
16298 mips_opts
.isa
= p
->isa
;
16302 else if (strncmp (name
, "mips", 4) == 0)
16304 const struct mips_cpu_info
*p
;
16306 p
= mips_parse_cpu ("internal use", name
);
16308 as_bad (_("unknown ISA level %s"), name
+ 4);
16311 mips_opts
.arch
= p
->cpu
;
16312 mips_opts
.isa
= p
->isa
;
16317 as_bad (_("unknown ISA or architecture %s"), name
);
16319 else if (strcmp (name
, "autoextend") == 0)
16320 mips_opts
.noautoextend
= 0;
16321 else if (strcmp (name
, "noautoextend") == 0)
16322 mips_opts
.noautoextend
= 1;
16323 else if (strcmp (name
, "insn32") == 0)
16324 mips_opts
.insn32
= TRUE
;
16325 else if (strcmp (name
, "noinsn32") == 0)
16326 mips_opts
.insn32
= FALSE
;
16327 else if (strcmp (name
, "sym32") == 0)
16328 mips_opts
.sym32
= TRUE
;
16329 else if (strcmp (name
, "nosym32") == 0)
16330 mips_opts
.sym32
= FALSE
;
16332 return OPTION_TYPE_BAD
;
16334 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16337 /* Handle the .set pseudo-op. */
16340 s_mipsset (int x ATTRIBUTE_UNUSED
)
16342 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16343 char *name
= input_line_pointer
, ch
;
16345 file_mips_check_options ();
16347 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16348 ++input_line_pointer
;
16349 ch
= *input_line_pointer
;
16350 *input_line_pointer
= '\0';
16352 if (strchr (name
, ','))
16354 /* Generic ".set" directive; use the generic handler. */
16355 *input_line_pointer
= ch
;
16356 input_line_pointer
= name
;
16361 if (strcmp (name
, "reorder") == 0)
16363 if (mips_opts
.noreorder
)
16366 else if (strcmp (name
, "noreorder") == 0)
16368 if (!mips_opts
.noreorder
)
16369 start_noreorder ();
16371 else if (strcmp (name
, "macro") == 0)
16372 mips_opts
.warn_about_macros
= 0;
16373 else if (strcmp (name
, "nomacro") == 0)
16375 if (mips_opts
.noreorder
== 0)
16376 as_bad (_("`noreorder' must be set before `nomacro'"));
16377 mips_opts
.warn_about_macros
= 1;
16379 else if (strcmp (name
, "gp=default") == 0)
16380 mips_opts
.gp
= file_mips_opts
.gp
;
16381 else if (strcmp (name
, "fp=default") == 0)
16382 mips_opts
.fp
= file_mips_opts
.fp
;
16383 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16385 mips_opts
.isa
= file_mips_opts
.isa
;
16386 mips_opts
.arch
= file_mips_opts
.arch
;
16387 mips_opts
.gp
= file_mips_opts
.gp
;
16388 mips_opts
.fp
= file_mips_opts
.fp
;
16390 else if (strcmp (name
, "push") == 0)
16392 struct mips_option_stack
*s
;
16394 s
= XNEW (struct mips_option_stack
);
16395 s
->next
= mips_opts_stack
;
16396 s
->options
= mips_opts
;
16397 mips_opts_stack
= s
;
16399 else if (strcmp (name
, "pop") == 0)
16401 struct mips_option_stack
*s
;
16403 s
= mips_opts_stack
;
16405 as_bad (_(".set pop with no .set push"));
16408 /* If we're changing the reorder mode we need to handle
16409 delay slots correctly. */
16410 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16411 start_noreorder ();
16412 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16415 mips_opts
= s
->options
;
16416 mips_opts_stack
= s
->next
;
16422 type
= parse_code_option (name
);
16423 if (type
== OPTION_TYPE_BAD
)
16424 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16427 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16428 registers based on what is supported by the arch/cpu. */
16429 if (type
== OPTION_TYPE_ISA
)
16431 switch (mips_opts
.isa
)
16436 /* MIPS I cannot support FPXX. */
16438 /* fall-through. */
16445 if (mips_opts
.fp
!= 0)
16461 if (mips_opts
.fp
!= 0)
16463 if (mips_opts
.arch
== CPU_R5900
)
16470 as_bad (_("unknown ISA level %s"), name
+ 4);
16475 mips_check_options (&mips_opts
, FALSE
);
16477 mips_check_isa_supports_ases ();
16478 *input_line_pointer
= ch
;
16479 demand_empty_rest_of_line ();
16482 /* Handle the .module pseudo-op. */
16485 s_module (int ignore ATTRIBUTE_UNUSED
)
16487 char *name
= input_line_pointer
, ch
;
16489 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16490 ++input_line_pointer
;
16491 ch
= *input_line_pointer
;
16492 *input_line_pointer
= '\0';
16494 if (!file_mips_opts_checked
)
16496 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16497 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16499 /* Update module level settings from mips_opts. */
16500 file_mips_opts
= mips_opts
;
16503 as_bad (_(".module is not permitted after generating code"));
16505 *input_line_pointer
= ch
;
16506 demand_empty_rest_of_line ();
16509 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16510 .option pic2. It means to generate SVR4 PIC calls. */
16513 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16515 mips_pic
= SVR4_PIC
;
16516 mips_abicalls
= TRUE
;
16518 if (g_switch_seen
&& g_switch_value
!= 0)
16519 as_warn (_("-G may not be used with SVR4 PIC code"));
16520 g_switch_value
= 0;
16522 bfd_set_gp_size (stdoutput
, 0);
16523 demand_empty_rest_of_line ();
16526 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16527 PIC code. It sets the $gp register for the function based on the
16528 function address, which is in the register named in the argument.
16529 This uses a relocation against _gp_disp, which is handled specially
16530 by the linker. The result is:
16531 lui $gp,%hi(_gp_disp)
16532 addiu $gp,$gp,%lo(_gp_disp)
16533 addu $gp,$gp,.cpload argument
16534 The .cpload argument is normally $25 == $t9.
16536 The -mno-shared option changes this to:
16537 lui $gp,%hi(__gnu_local_gp)
16538 addiu $gp,$gp,%lo(__gnu_local_gp)
16539 and the argument is ignored. This saves an instruction, but the
16540 resulting code is not position independent; it uses an absolute
16541 address for __gnu_local_gp. Thus code assembled with -mno-shared
16542 can go into an ordinary executable, but not into a shared library. */
16545 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16551 file_mips_check_options ();
16553 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16554 .cpload is ignored. */
16555 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16561 if (mips_opts
.mips16
)
16563 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16564 ignore_rest_of_line ();
16568 /* .cpload should be in a .set noreorder section. */
16569 if (mips_opts
.noreorder
== 0)
16570 as_warn (_(".cpload not in noreorder section"));
16572 reg
= tc_get_register (0);
16574 /* If we need to produce a 64-bit address, we are better off using
16575 the default instruction sequence. */
16576 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16578 ex
.X_op
= O_symbol
;
16579 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16581 ex
.X_op_symbol
= NULL
;
16582 ex
.X_add_number
= 0;
16584 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16585 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16587 mips_mark_labels ();
16588 mips_assembling_insn
= TRUE
;
16591 macro_build_lui (&ex
, mips_gp_register
);
16592 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16593 mips_gp_register
, BFD_RELOC_LO16
);
16595 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16596 mips_gp_register
, reg
);
16599 mips_assembling_insn
= FALSE
;
16600 demand_empty_rest_of_line ();
16603 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16604 .cpsetup $reg1, offset|$reg2, label
16606 If offset is given, this results in:
16607 sd $gp, offset($sp)
16608 lui $gp, %hi(%neg(%gp_rel(label)))
16609 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16610 daddu $gp, $gp, $reg1
16612 If $reg2 is given, this results in:
16614 lui $gp, %hi(%neg(%gp_rel(label)))
16615 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16616 daddu $gp, $gp, $reg1
16617 $reg1 is normally $25 == $t9.
16619 The -mno-shared option replaces the last three instructions with
16621 addiu $gp,$gp,%lo(_gp) */
16624 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16626 expressionS ex_off
;
16627 expressionS ex_sym
;
16630 file_mips_check_options ();
16632 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16633 We also need NewABI support. */
16634 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16640 if (mips_opts
.mips16
)
16642 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16643 ignore_rest_of_line ();
16647 reg1
= tc_get_register (0);
16648 SKIP_WHITESPACE ();
16649 if (*input_line_pointer
!= ',')
16651 as_bad (_("missing argument separator ',' for .cpsetup"));
16655 ++input_line_pointer
;
16656 SKIP_WHITESPACE ();
16657 if (*input_line_pointer
== '$')
16659 mips_cpreturn_register
= tc_get_register (0);
16660 mips_cpreturn_offset
= -1;
16664 mips_cpreturn_offset
= get_absolute_expression ();
16665 mips_cpreturn_register
= -1;
16667 SKIP_WHITESPACE ();
16668 if (*input_line_pointer
!= ',')
16670 as_bad (_("missing argument separator ',' for .cpsetup"));
16674 ++input_line_pointer
;
16675 SKIP_WHITESPACE ();
16676 expression (&ex_sym
);
16678 mips_mark_labels ();
16679 mips_assembling_insn
= TRUE
;
16682 if (mips_cpreturn_register
== -1)
16684 ex_off
.X_op
= O_constant
;
16685 ex_off
.X_add_symbol
= NULL
;
16686 ex_off
.X_op_symbol
= NULL
;
16687 ex_off
.X_add_number
= mips_cpreturn_offset
;
16689 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16690 BFD_RELOC_LO16
, SP
);
16693 move_register (mips_cpreturn_register
, mips_gp_register
);
16695 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16697 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16698 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16701 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16702 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16703 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16705 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16706 mips_gp_register
, reg1
);
16712 ex
.X_op
= O_symbol
;
16713 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16714 ex
.X_op_symbol
= NULL
;
16715 ex
.X_add_number
= 0;
16717 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16718 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16720 macro_build_lui (&ex
, mips_gp_register
);
16721 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16722 mips_gp_register
, BFD_RELOC_LO16
);
16727 mips_assembling_insn
= FALSE
;
16728 demand_empty_rest_of_line ();
16732 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16734 file_mips_check_options ();
16736 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16737 .cplocal is ignored. */
16738 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16744 if (mips_opts
.mips16
)
16746 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16747 ignore_rest_of_line ();
16751 mips_gp_register
= tc_get_register (0);
16752 demand_empty_rest_of_line ();
16755 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16756 offset from $sp. The offset is remembered, and after making a PIC
16757 call $gp is restored from that location. */
16760 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16764 file_mips_check_options ();
16766 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16767 .cprestore is ignored. */
16768 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16774 if (mips_opts
.mips16
)
16776 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16777 ignore_rest_of_line ();
16781 mips_cprestore_offset
= get_absolute_expression ();
16782 mips_cprestore_valid
= 1;
16784 ex
.X_op
= O_constant
;
16785 ex
.X_add_symbol
= NULL
;
16786 ex
.X_op_symbol
= NULL
;
16787 ex
.X_add_number
= mips_cprestore_offset
;
16789 mips_mark_labels ();
16790 mips_assembling_insn
= TRUE
;
16793 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16794 SP
, HAVE_64BIT_ADDRESSES
);
16797 mips_assembling_insn
= FALSE
;
16798 demand_empty_rest_of_line ();
16801 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16802 was given in the preceding .cpsetup, it results in:
16803 ld $gp, offset($sp)
16805 If a register $reg2 was given there, it results in:
16806 or $gp, $reg2, $0 */
16809 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16813 file_mips_check_options ();
16815 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16816 We also need NewABI support. */
16817 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16823 if (mips_opts
.mips16
)
16825 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16826 ignore_rest_of_line ();
16830 mips_mark_labels ();
16831 mips_assembling_insn
= TRUE
;
16834 if (mips_cpreturn_register
== -1)
16836 ex
.X_op
= O_constant
;
16837 ex
.X_add_symbol
= NULL
;
16838 ex
.X_op_symbol
= NULL
;
16839 ex
.X_add_number
= mips_cpreturn_offset
;
16841 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16844 move_register (mips_gp_register
, mips_cpreturn_register
);
16848 mips_assembling_insn
= FALSE
;
16849 demand_empty_rest_of_line ();
16852 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16853 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16854 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16855 debug information or MIPS16 TLS. */
16858 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16859 bfd_reloc_code_real_type rtype
)
16866 if (ex
.X_op
!= O_symbol
)
16868 as_bad (_("unsupported use of %s"), dirstr
);
16869 ignore_rest_of_line ();
16872 p
= frag_more (bytes
);
16873 md_number_to_chars (p
, 0, bytes
);
16874 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16875 demand_empty_rest_of_line ();
16876 mips_clear_insn_labels ();
16879 /* Handle .dtprelword. */
16882 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16884 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16887 /* Handle .dtpreldword. */
16890 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16892 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16895 /* Handle .tprelword. */
16898 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16900 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16903 /* Handle .tpreldword. */
16906 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16908 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16911 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16912 code. It sets the offset to use in gp_rel relocations. */
16915 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16917 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16918 We also need NewABI support. */
16919 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16925 mips_gprel_offset
= get_absolute_expression ();
16927 demand_empty_rest_of_line ();
16930 /* Handle the .gpword pseudo-op. This is used when generating PIC
16931 code. It generates a 32 bit GP relative reloc. */
16934 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16936 segment_info_type
*si
;
16937 struct insn_label_list
*l
;
16941 /* When not generating PIC code, this is treated as .word. */
16942 if (mips_pic
!= SVR4_PIC
)
16948 si
= seg_info (now_seg
);
16949 l
= si
->label_list
;
16950 mips_emit_delays ();
16952 mips_align (2, 0, l
);
16955 mips_clear_insn_labels ();
16957 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16959 as_bad (_("unsupported use of .gpword"));
16960 ignore_rest_of_line ();
16964 md_number_to_chars (p
, 0, 4);
16965 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16966 BFD_RELOC_GPREL32
);
16968 demand_empty_rest_of_line ();
16972 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16974 segment_info_type
*si
;
16975 struct insn_label_list
*l
;
16979 /* When not generating PIC code, this is treated as .dword. */
16980 if (mips_pic
!= SVR4_PIC
)
16986 si
= seg_info (now_seg
);
16987 l
= si
->label_list
;
16988 mips_emit_delays ();
16990 mips_align (3, 0, l
);
16993 mips_clear_insn_labels ();
16995 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16997 as_bad (_("unsupported use of .gpdword"));
16998 ignore_rest_of_line ();
17002 md_number_to_chars (p
, 0, 8);
17003 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17004 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17006 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17007 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17008 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17010 demand_empty_rest_of_line ();
17013 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17014 tables. It generates a R_MIPS_EH reloc. */
17017 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17022 mips_emit_delays ();
17025 mips_clear_insn_labels ();
17027 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17029 as_bad (_("unsupported use of .ehword"));
17030 ignore_rest_of_line ();
17034 md_number_to_chars (p
, 0, 4);
17035 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17036 BFD_RELOC_32_PCREL
);
17038 demand_empty_rest_of_line ();
17041 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17042 tables in SVR4 PIC code. */
17045 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17049 file_mips_check_options ();
17051 /* This is ignored when not generating SVR4 PIC code. */
17052 if (mips_pic
!= SVR4_PIC
)
17058 mips_mark_labels ();
17059 mips_assembling_insn
= TRUE
;
17061 /* Add $gp to the register named as an argument. */
17063 reg
= tc_get_register (0);
17064 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17067 mips_assembling_insn
= FALSE
;
17068 demand_empty_rest_of_line ();
17071 /* Handle the .insn pseudo-op. This marks instruction labels in
17072 mips16/micromips mode. This permits the linker to handle them specially,
17073 such as generating jalx instructions when needed. We also make
17074 them odd for the duration of the assembly, in order to generate the
17075 right sort of code. We will make them even in the adjust_symtab
17076 routine, while leaving them marked. This is convenient for the
17077 debugger and the disassembler. The linker knows to make them odd
17081 s_insn (int ignore ATTRIBUTE_UNUSED
)
17083 file_mips_check_options ();
17084 file_ase_mips16
|= mips_opts
.mips16
;
17085 file_ase_micromips
|= mips_opts
.micromips
;
17087 mips_mark_labels ();
17089 demand_empty_rest_of_line ();
17092 /* Handle the .nan pseudo-op. */
17095 s_nan (int ignore ATTRIBUTE_UNUSED
)
17097 static const char str_legacy
[] = "legacy";
17098 static const char str_2008
[] = "2008";
17101 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17103 if (i
== sizeof (str_2008
) - 1
17104 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17106 else if (i
== sizeof (str_legacy
) - 1
17107 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17109 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17112 as_bad (_("`%s' does not support legacy NaN"),
17113 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17116 as_bad (_("bad .nan directive"));
17118 input_line_pointer
+= i
;
17119 demand_empty_rest_of_line ();
17122 /* Handle a .stab[snd] directive. Ideally these directives would be
17123 implemented in a transparent way, so that removing them would not
17124 have any effect on the generated instructions. However, s_stab
17125 internally changes the section, so in practice we need to decide
17126 now whether the preceding label marks compressed code. We do not
17127 support changing the compression mode of a label after a .stab*
17128 directive, such as in:
17134 so the current mode wins. */
17137 s_mips_stab (int type
)
17139 mips_mark_labels ();
17143 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17146 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17153 c
= get_symbol_name (&name
);
17154 symbolP
= symbol_find_or_make (name
);
17155 S_SET_WEAK (symbolP
);
17156 *input_line_pointer
= c
;
17158 SKIP_WHITESPACE_AFTER_NAME ();
17160 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17162 if (S_IS_DEFINED (symbolP
))
17164 as_bad (_("ignoring attempt to redefine symbol %s"),
17165 S_GET_NAME (symbolP
));
17166 ignore_rest_of_line ();
17170 if (*input_line_pointer
== ',')
17172 ++input_line_pointer
;
17173 SKIP_WHITESPACE ();
17177 if (exp
.X_op
!= O_symbol
)
17179 as_bad (_("bad .weakext directive"));
17180 ignore_rest_of_line ();
17183 symbol_set_value_expression (symbolP
, &exp
);
17186 demand_empty_rest_of_line ();
17189 /* Parse a register string into a number. Called from the ECOFF code
17190 to parse .frame. The argument is non-zero if this is the frame
17191 register, so that we can record it in mips_frame_reg. */
17194 tc_get_register (int frame
)
17198 SKIP_WHITESPACE ();
17199 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17203 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17204 mips_frame_reg_valid
= 1;
17205 mips_cprestore_valid
= 0;
17211 md_section_align (asection
*seg
, valueT addr
)
17213 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17215 /* We don't need to align ELF sections to the full alignment.
17216 However, Irix 5 may prefer that we align them at least to a 16
17217 byte boundary. We don't bother to align the sections if we
17218 are targeted for an embedded system. */
17219 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17224 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17227 /* Utility routine, called from above as well. If called while the
17228 input file is still being read, it's only an approximation. (For
17229 example, a symbol may later become defined which appeared to be
17230 undefined earlier.) */
17233 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17238 if (g_switch_value
> 0)
17240 const char *symname
;
17243 /* Find out whether this symbol can be referenced off the $gp
17244 register. It can be if it is smaller than the -G size or if
17245 it is in the .sdata or .sbss section. Certain symbols can
17246 not be referenced off the $gp, although it appears as though
17248 symname
= S_GET_NAME (sym
);
17249 if (symname
!= (const char *) NULL
17250 && (strcmp (symname
, "eprol") == 0
17251 || strcmp (symname
, "etext") == 0
17252 || strcmp (symname
, "_gp") == 0
17253 || strcmp (symname
, "edata") == 0
17254 || strcmp (symname
, "_fbss") == 0
17255 || strcmp (symname
, "_fdata") == 0
17256 || strcmp (symname
, "_ftext") == 0
17257 || strcmp (symname
, "end") == 0
17258 || strcmp (symname
, "_gp_disp") == 0))
17260 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17262 #ifndef NO_ECOFF_DEBUGGING
17263 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17264 && (symbol_get_obj (sym
)->ecoff_extern_size
17265 <= g_switch_value
))
17267 /* We must defer this decision until after the whole
17268 file has been read, since there might be a .extern
17269 after the first use of this symbol. */
17270 || (before_relaxing
17271 #ifndef NO_ECOFF_DEBUGGING
17272 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17274 && S_GET_VALUE (sym
) == 0)
17275 || (S_GET_VALUE (sym
) != 0
17276 && S_GET_VALUE (sym
) <= g_switch_value
)))
17280 const char *segname
;
17282 segname
= segment_name (S_GET_SEGMENT (sym
));
17283 gas_assert (strcmp (segname
, ".lit8") != 0
17284 && strcmp (segname
, ".lit4") != 0);
17285 change
= (strcmp (segname
, ".sdata") != 0
17286 && strcmp (segname
, ".sbss") != 0
17287 && strncmp (segname
, ".sdata.", 7) != 0
17288 && strncmp (segname
, ".sbss.", 6) != 0
17289 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17290 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17295 /* We are not optimizing for the $gp register. */
17300 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17303 pic_need_relax (symbolS
*sym
)
17307 /* Handle the case of a symbol equated to another symbol. */
17308 while (symbol_equated_reloc_p (sym
))
17312 /* It's possible to get a loop here in a badly written program. */
17313 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17319 if (symbol_section_p (sym
))
17322 symsec
= S_GET_SEGMENT (sym
);
17324 /* This must duplicate the test in adjust_reloc_syms. */
17325 return (!bfd_is_und_section (symsec
)
17326 && !bfd_is_abs_section (symsec
)
17327 && !bfd_is_com_section (symsec
)
17328 /* A global or weak symbol is treated as external. */
17329 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17332 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17333 convert a section-relative value VAL to the equivalent PC-relative
17337 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17338 offsetT val
, long stretch
)
17343 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17345 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17347 /* If the relax_marker of the symbol fragment differs from the
17348 relax_marker of this fragment, we have not yet adjusted the
17349 symbol fragment fr_address. We want to add in STRETCH in
17350 order to get a better estimate of the address. This
17351 particularly matters because of the shift bits. */
17352 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17356 /* Adjust stretch for any alignment frag. Note that if have
17357 been expanding the earlier code, the symbol may be
17358 defined in what appears to be an earlier frag. FIXME:
17359 This doesn't handle the fr_subtype field, which specifies
17360 a maximum number of bytes to skip when doing an
17362 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17364 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17367 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17369 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17378 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17380 /* The base address rules are complicated. The base address of
17381 a branch is the following instruction. The base address of a
17382 PC relative load or add is the instruction itself, but if it
17383 is in a delay slot (in which case it can not be extended) use
17384 the address of the instruction whose delay slot it is in. */
17385 if (pcrel_op
->include_isa_bit
)
17389 /* If we are currently assuming that this frag should be
17390 extended, then the current address is two bytes higher. */
17391 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17394 /* Ignore the low bit in the target, since it will be set
17395 for a text label. */
17398 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17400 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17403 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17408 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17409 extended opcode. SEC is the section the frag is in. */
17412 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17414 const struct mips_int_operand
*operand
;
17419 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17421 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17424 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17425 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17426 operand
= mips16_immed_operand (type
, FALSE
);
17427 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17428 || (operand
->root
.type
== OP_PCREL
17430 : !bfd_is_abs_section (symsec
)))
17433 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17435 if (operand
->root
.type
== OP_PCREL
)
17437 const struct mips_pcrel_operand
*pcrel_op
;
17440 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17443 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17444 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17446 /* If any of the shifted bits are set, we must use an extended
17447 opcode. If the address depends on the size of this
17448 instruction, this can lead to a loop, so we arrange to always
17449 use an extended opcode. */
17450 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17452 fragp
->fr_subtype
=
17453 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17457 /* If we are about to mark a frag as extended because the value
17458 is precisely the next value above maxtiny, then there is a
17459 chance of an infinite loop as in the following code:
17464 In this case when the la is extended, foo is 0x3fc bytes
17465 away, so the la can be shrunk, but then foo is 0x400 away, so
17466 the la must be extended. To avoid this loop, we mark the
17467 frag as extended if it was small, and is about to become
17468 extended with the next value above maxtiny. */
17469 maxtiny
= mips_int_operand_max (operand
);
17470 if (val
== maxtiny
+ (1 << operand
->shift
)
17471 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17473 fragp
->fr_subtype
=
17474 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17479 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17482 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17483 macro expansion. SEC is the section the frag is in. We only
17484 support PC-relative instructions (LA, DLA, LW, LD) here, in
17485 non-PIC code using 32-bit addressing. */
17488 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17490 const struct mips_pcrel_operand
*pcrel_op
;
17491 const struct mips_int_operand
*operand
;
17496 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17498 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17500 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17503 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17509 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17510 if (bfd_is_abs_section (symsec
))
17512 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17514 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17517 operand
= mips16_immed_operand (type
, TRUE
);
17518 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17519 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17520 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17522 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17529 /* Compute the length of a branch sequence, and adjust the
17530 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17531 worst-case length is computed, with UPDATE being used to indicate
17532 whether an unconditional (-1), branch-likely (+1) or regular (0)
17533 branch is to be computed. */
17535 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17537 bfd_boolean toofar
;
17541 && S_IS_DEFINED (fragp
->fr_symbol
)
17542 && !S_IS_WEAK (fragp
->fr_symbol
)
17543 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17548 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17550 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17554 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17557 /* If the symbol is not defined or it's in a different segment,
17558 we emit the long sequence. */
17561 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17563 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17564 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17565 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17566 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17567 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17573 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17576 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17578 /* Additional space for PIC loading of target address. */
17580 if (mips_opts
.isa
== ISA_MIPS1
)
17581 /* Additional space for $at-stabilizing nop. */
17585 /* If branch is conditional. */
17586 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17593 /* Get a FRAG's branch instruction delay slot size, either from the
17594 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17595 or SHORT_INSN_SIZE otherwise. */
17598 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17600 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17603 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17605 return short_insn_size
;
17608 /* Compute the length of a branch sequence, and adjust the
17609 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17610 worst-case length is computed, with UPDATE being used to indicate
17611 whether an unconditional (-1), or regular (0) branch is to be
17615 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17617 bfd_boolean insn32
= TRUE
;
17618 bfd_boolean nods
= TRUE
;
17619 bfd_boolean pic
= TRUE
;
17620 bfd_boolean al
= TRUE
;
17621 int short_insn_size
;
17622 bfd_boolean toofar
;
17627 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17628 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17629 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17630 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17632 short_insn_size
= insn32
? 4 : 2;
17635 && S_IS_DEFINED (fragp
->fr_symbol
)
17636 && !S_IS_WEAK (fragp
->fr_symbol
)
17637 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17642 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17643 /* Ignore the low bit in the target, since it will be set
17644 for a text label. */
17645 if ((val
& 1) != 0)
17648 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17652 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17655 /* If the symbol is not defined or it's in a different segment,
17656 we emit the long sequence. */
17659 if (fragp
&& update
17660 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17661 fragp
->fr_subtype
= (toofar
17662 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17663 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17668 bfd_boolean compact_known
= fragp
!= NULL
;
17669 bfd_boolean compact
= FALSE
;
17670 bfd_boolean uncond
;
17674 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17675 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17678 uncond
= update
< 0;
17680 /* If label is out of range, we turn branch <br>:
17682 <br> label # 4 bytes
17689 # compact && (!PIC || insn32)
17692 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17693 length
+= short_insn_size
;
17695 /* If assembling PIC code, we further turn:
17701 lw/ld at, %got(label)(gp) # 4 bytes
17702 d/addiu at, %lo(label) # 4 bytes
17703 jr/c at # 2/4 bytes
17706 length
+= 4 + short_insn_size
;
17708 /* Add an extra nop if the jump has no compact form and we need
17709 to fill the delay slot. */
17710 if ((!pic
|| al
) && nods
)
17712 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17713 : short_insn_size
);
17715 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17717 <brneg> 0f # 4 bytes
17718 nop # 2/4 bytes if !compact
17721 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17725 /* Add an extra nop to fill the delay slot. */
17726 gas_assert (fragp
);
17727 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17733 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17734 bit accordingly. */
17737 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17739 bfd_boolean toofar
;
17742 && S_IS_DEFINED (fragp
->fr_symbol
)
17743 && !S_IS_WEAK (fragp
->fr_symbol
)
17744 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17750 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17751 /* Ignore the low bit in the target, since it will be set
17752 for a text label. */
17753 if ((val
& 1) != 0)
17756 /* Assume this is a 2-byte branch. */
17757 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17759 /* We try to avoid the infinite loop by not adding 2 more bytes for
17764 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17766 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17767 else if (type
== 'E')
17768 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17773 /* If the symbol is not defined or it's in a different segment,
17774 we emit a normal 32-bit branch. */
17777 if (fragp
&& update
17778 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17780 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17781 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17789 /* Estimate the size of a frag before relaxing. Unless this is the
17790 mips16, we are not really relaxing here, and the final size is
17791 encoded in the subtype information. For the mips16, we have to
17792 decide whether we are using an extended opcode or not. */
17795 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17799 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17802 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17804 return fragp
->fr_var
;
17807 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17809 /* We don't want to modify the EXTENDED bit here; it might get us
17810 into infinite loops. We change it only in mips_relax_frag(). */
17811 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17812 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
17814 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17817 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17821 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17822 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17823 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17824 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17825 fragp
->fr_var
= length
;
17830 if (mips_pic
== VXWORKS_PIC
)
17831 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17833 else if (RELAX_PIC (fragp
->fr_subtype
))
17834 change
= pic_need_relax (fragp
->fr_symbol
);
17836 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17840 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17841 return -RELAX_FIRST (fragp
->fr_subtype
);
17844 return -RELAX_SECOND (fragp
->fr_subtype
);
17847 /* This is called to see whether a reloc against a defined symbol
17848 should be converted into a reloc against a section. */
17851 mips_fix_adjustable (fixS
*fixp
)
17853 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17854 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17857 if (fixp
->fx_addsy
== NULL
)
17860 /* Allow relocs used for EH tables. */
17861 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17864 /* If symbol SYM is in a mergeable section, relocations of the form
17865 SYM + 0 can usually be made section-relative. The mergeable data
17866 is then identified by the section offset rather than by the symbol.
17868 However, if we're generating REL LO16 relocations, the offset is split
17869 between the LO16 and partnering high part relocation. The linker will
17870 need to recalculate the complete offset in order to correctly identify
17873 The linker has traditionally not looked for the partnering high part
17874 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17875 placed anywhere. Rather than break backwards compatibility by changing
17876 this, it seems better not to force the issue, and instead keep the
17877 original symbol. This will work with either linker behavior. */
17878 if ((lo16_reloc_p (fixp
->fx_r_type
)
17879 || reloc_needs_lo_p (fixp
->fx_r_type
))
17880 && HAVE_IN_PLACE_ADDENDS
17881 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17884 /* There is no place to store an in-place offset for JALR relocations. */
17885 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17888 /* Likewise an in-range offset of limited PC-relative relocations may
17889 overflow the in-place relocatable field if recalculated against the
17890 start address of the symbol's containing section.
17892 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17893 section relative to allow linker relaxations to be performed later on. */
17894 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17895 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17898 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17899 to a floating-point stub. The same is true for non-R_MIPS16_26
17900 relocations against MIPS16 functions; in this case, the stub becomes
17901 the function's canonical address.
17903 Floating-point stubs are stored in unique .mips16.call.* or
17904 .mips16.fn.* sections. If a stub T for function F is in section S,
17905 the first relocation in section S must be against F; this is how the
17906 linker determines the target function. All relocations that might
17907 resolve to T must also be against F. We therefore have the following
17908 restrictions, which are given in an intentionally-redundant way:
17910 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17913 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17914 if that stub might be used.
17916 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17919 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17920 that stub might be used.
17922 There is a further restriction:
17924 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17925 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17926 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17927 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17928 against MIPS16 or microMIPS symbols because we need to keep the
17929 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17930 detection and JAL or BAL to JALX instruction conversion in the
17933 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17934 against a MIPS16 symbol. We deal with (5) by additionally leaving
17935 alone any jump and branch relocations against a microMIPS symbol.
17937 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17938 relocation against some symbol R, no relocation against R may be
17939 reduced. (Note that this deals with (2) as well as (1) because
17940 relocations against global symbols will never be reduced on ELF
17941 targets.) This approach is a little simpler than trying to detect
17942 stub sections, and gives the "all or nothing" per-symbol consistency
17943 that we have for MIPS16 symbols. */
17944 if (fixp
->fx_subsy
== NULL
17945 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17946 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17947 && (jmp_reloc_p (fixp
->fx_r_type
)
17948 || b_reloc_p (fixp
->fx_r_type
)))
17949 || *symbol_get_tc (fixp
->fx_addsy
)))
17955 /* Translate internal representation of relocation info to BFD target
17959 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17961 static arelent
*retval
[4];
17963 bfd_reloc_code_real_type code
;
17965 memset (retval
, 0, sizeof(retval
));
17966 reloc
= retval
[0] = XCNEW (arelent
);
17967 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17968 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17969 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17971 if (fixp
->fx_pcrel
)
17973 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17974 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
17975 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17976 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17977 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17978 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17979 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17980 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17981 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17982 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17983 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17984 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17986 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17987 Relocations want only the symbol offset. */
17988 switch (fixp
->fx_r_type
)
17990 case BFD_RELOC_MIPS_18_PCREL_S3
:
17991 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
17994 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17998 else if (HAVE_IN_PLACE_ADDENDS
17999 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18000 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18001 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18003 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18004 addend accordingly. */
18005 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18008 reloc
->addend
= fixp
->fx_addnumber
;
18010 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18011 entry to be used in the relocation's section offset. */
18012 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18014 reloc
->address
= reloc
->addend
;
18018 code
= fixp
->fx_r_type
;
18020 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18021 if (reloc
->howto
== NULL
)
18023 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18024 _("cannot represent %s relocation in this object file"
18026 bfd_get_reloc_code_name (code
));
18033 /* Relax a machine dependent frag. This returns the amount by which
18034 the current size of the frag should change. */
18037 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18039 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18041 offsetT old_var
= fragp
->fr_var
;
18043 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18045 return fragp
->fr_var
- old_var
;
18048 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18050 offsetT old_var
= fragp
->fr_var
;
18051 offsetT new_var
= 4;
18053 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18054 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18055 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18056 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18057 fragp
->fr_var
= new_var
;
18059 return new_var
- old_var
;
18062 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18065 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18067 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18069 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18070 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18072 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18074 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18080 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18082 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18084 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18085 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18086 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18088 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18090 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18098 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18100 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18102 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18103 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18104 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18108 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18109 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18116 /* Convert a machine dependent frag. */
18119 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18121 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18124 unsigned long insn
;
18128 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18129 insn
= read_insn (buf
);
18131 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18133 /* We generate a fixup instead of applying it right now
18134 because, if there are linker relaxations, we're going to
18135 need the relocations. */
18136 exp
.X_op
= O_symbol
;
18137 exp
.X_add_symbol
= fragp
->fr_symbol
;
18138 exp
.X_add_number
= fragp
->fr_offset
;
18140 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18141 BFD_RELOC_16_PCREL_S2
);
18142 fixp
->fx_file
= fragp
->fr_file
;
18143 fixp
->fx_line
= fragp
->fr_line
;
18145 buf
= write_insn (buf
, insn
);
18151 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18152 _("relaxed out-of-range branch into a jump"));
18154 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18157 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18159 /* Reverse the branch. */
18160 switch ((insn
>> 28) & 0xf)
18163 if ((insn
& 0xff000000) == 0x47000000
18164 || (insn
& 0xff600000) == 0x45600000)
18166 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18167 reversed by tweaking bit 23. */
18168 insn
^= 0x00800000;
18172 /* bc[0-3][tf]l? instructions can have the condition
18173 reversed by tweaking a single TF bit, and their
18174 opcodes all have 0x4???????. */
18175 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18176 insn
^= 0x00010000;
18181 /* bltz 0x04000000 bgez 0x04010000
18182 bltzal 0x04100000 bgezal 0x04110000 */
18183 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18184 insn
^= 0x00010000;
18188 /* beq 0x10000000 bne 0x14000000
18189 blez 0x18000000 bgtz 0x1c000000 */
18190 insn
^= 0x04000000;
18198 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18200 /* Clear the and-link bit. */
18201 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18203 /* bltzal 0x04100000 bgezal 0x04110000
18204 bltzall 0x04120000 bgezall 0x04130000 */
18205 insn
&= ~0x00100000;
18208 /* Branch over the branch (if the branch was likely) or the
18209 full jump (not likely case). Compute the offset from the
18210 current instruction to branch to. */
18211 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18215 /* How many bytes in instructions we've already emitted? */
18216 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18217 /* How many bytes in instructions from here to the end? */
18218 i
= fragp
->fr_var
- i
;
18220 /* Convert to instruction count. */
18222 /* Branch counts from the next instruction. */
18225 /* Branch over the jump. */
18226 buf
= write_insn (buf
, insn
);
18229 buf
= write_insn (buf
, 0);
18231 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18233 /* beql $0, $0, 2f */
18235 /* Compute the PC offset from the current instruction to
18236 the end of the variable frag. */
18237 /* How many bytes in instructions we've already emitted? */
18238 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18239 /* How many bytes in instructions from here to the end? */
18240 i
= fragp
->fr_var
- i
;
18241 /* Convert to instruction count. */
18243 /* Don't decrement i, because we want to branch over the
18247 buf
= write_insn (buf
, insn
);
18248 buf
= write_insn (buf
, 0);
18252 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18255 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18256 ? 0x0c000000 : 0x08000000);
18257 exp
.X_op
= O_symbol
;
18258 exp
.X_add_symbol
= fragp
->fr_symbol
;
18259 exp
.X_add_number
= fragp
->fr_offset
;
18261 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18262 FALSE
, BFD_RELOC_MIPS_JMP
);
18263 fixp
->fx_file
= fragp
->fr_file
;
18264 fixp
->fx_line
= fragp
->fr_line
;
18266 buf
= write_insn (buf
, insn
);
18270 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18272 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18273 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18274 insn
|= at
<< OP_SH_RT
;
18275 exp
.X_op
= O_symbol
;
18276 exp
.X_add_symbol
= fragp
->fr_symbol
;
18277 exp
.X_add_number
= fragp
->fr_offset
;
18279 if (fragp
->fr_offset
)
18281 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18282 exp
.X_add_number
= 0;
18285 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18286 FALSE
, BFD_RELOC_MIPS_GOT16
);
18287 fixp
->fx_file
= fragp
->fr_file
;
18288 fixp
->fx_line
= fragp
->fr_line
;
18290 buf
= write_insn (buf
, insn
);
18292 if (mips_opts
.isa
== ISA_MIPS1
)
18294 buf
= write_insn (buf
, 0);
18296 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18297 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18298 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18300 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18301 FALSE
, BFD_RELOC_LO16
);
18302 fixp
->fx_file
= fragp
->fr_file
;
18303 fixp
->fx_line
= fragp
->fr_line
;
18305 buf
= write_insn (buf
, insn
);
18308 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18312 insn
|= at
<< OP_SH_RS
;
18314 buf
= write_insn (buf
, insn
);
18318 fragp
->fr_fix
+= fragp
->fr_var
;
18319 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18323 /* Relax microMIPS branches. */
18324 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18326 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18327 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18328 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18329 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18330 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18331 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18332 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18333 bfd_boolean short_ds
;
18334 unsigned long insn
;
18338 exp
.X_op
= O_symbol
;
18339 exp
.X_add_symbol
= fragp
->fr_symbol
;
18340 exp
.X_add_number
= fragp
->fr_offset
;
18342 fragp
->fr_fix
+= fragp
->fr_var
;
18344 /* Handle 16-bit branches that fit or are forced to fit. */
18345 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18347 /* We generate a fixup instead of applying it right now,
18348 because if there is linker relaxation, we're going to
18349 need the relocations. */
18351 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18352 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18353 else if (type
== 'E')
18354 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18355 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18359 fixp
->fx_file
= fragp
->fr_file
;
18360 fixp
->fx_line
= fragp
->fr_line
;
18362 /* These relocations can have an addend that won't fit in
18364 fixp
->fx_no_overflow
= 1;
18369 /* Handle 32-bit branches that fit or are forced to fit. */
18370 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18371 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18373 /* We generate a fixup instead of applying it right now,
18374 because if there is linker relaxation, we're going to
18375 need the relocations. */
18376 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18377 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18378 fixp
->fx_file
= fragp
->fr_file
;
18379 fixp
->fx_line
= fragp
->fr_line
;
18383 insn
= read_compressed_insn (buf
, 4);
18388 /* Check the short-delay-slot bit. */
18389 if (!al
|| (insn
& 0x02000000) != 0)
18390 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18392 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18395 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18400 /* Relax 16-bit branches to 32-bit branches. */
18403 insn
= read_compressed_insn (buf
, 2);
18405 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18406 insn
= 0x94000000; /* beq */
18407 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18409 unsigned long regno
;
18411 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18412 regno
= micromips_to_32_reg_d_map
[regno
];
18413 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18414 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18419 /* Nothing else to do, just write it out. */
18420 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18421 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18423 buf
= write_compressed_insn (buf
, insn
, 4);
18425 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18426 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18431 insn
= read_compressed_insn (buf
, 4);
18433 /* Relax 32-bit branches to a sequence of instructions. */
18434 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18435 _("relaxed out-of-range branch into a jump"));
18437 /* Set the short-delay-slot bit. */
18438 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18440 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18444 /* Reverse the branch. */
18445 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18446 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18447 insn
^= 0x20000000;
18448 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18449 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18450 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18451 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18452 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18453 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18454 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18455 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18456 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18457 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18458 insn
^= 0x00400000;
18459 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18460 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18461 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18462 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18463 insn
^= 0x00200000;
18464 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18466 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18468 insn
^= 0x00800000;
18474 /* Clear the and-link and short-delay-slot bits. */
18475 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18477 /* bltzal 0x40200000 bgezal 0x40600000 */
18478 /* bltzals 0x42200000 bgezals 0x42600000 */
18479 insn
&= ~0x02200000;
18482 /* Make a label at the end for use with the branch. */
18483 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18484 micromips_label_inc ();
18485 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18488 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18489 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18490 fixp
->fx_file
= fragp
->fr_file
;
18491 fixp
->fx_line
= fragp
->fr_line
;
18493 /* Branch over the jump. */
18494 buf
= write_compressed_insn (buf
, insn
, 4);
18500 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18502 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18508 unsigned long jal
= (short_ds
|| nods
18509 ? 0x74000000 : 0xf4000000); /* jal/s */
18511 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18512 insn
= al
? jal
: 0xd4000000;
18514 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18515 BFD_RELOC_MICROMIPS_JMP
);
18516 fixp
->fx_file
= fragp
->fr_file
;
18517 fixp
->fx_line
= fragp
->fr_line
;
18519 buf
= write_compressed_insn (buf
, insn
, 4);
18521 if (compact
|| nods
)
18525 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18527 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18532 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18534 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18535 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18536 insn
|= at
<< MICROMIPSOP_SH_RT
;
18538 if (exp
.X_add_number
)
18540 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18541 exp
.X_add_number
= 0;
18544 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18545 BFD_RELOC_MICROMIPS_GOT16
);
18546 fixp
->fx_file
= fragp
->fr_file
;
18547 fixp
->fx_line
= fragp
->fr_line
;
18549 buf
= write_compressed_insn (buf
, insn
, 4);
18551 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18552 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18553 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18555 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18556 BFD_RELOC_MICROMIPS_LO16
);
18557 fixp
->fx_file
= fragp
->fr_file
;
18558 fixp
->fx_line
= fragp
->fr_line
;
18560 buf
= write_compressed_insn (buf
, insn
, 4);
18565 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18566 insn
|= at
<< MICROMIPSOP_SH_RS
;
18568 buf
= write_compressed_insn (buf
, insn
, 4);
18570 if (compact
|| nods
)
18572 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18576 /* jr/jrc/jalr/jalrs $at */
18577 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18578 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18580 insn
= al
? jalr
: jr
;
18581 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18583 buf
= write_compressed_insn (buf
, insn
, 2);
18588 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18590 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18595 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18599 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18602 const struct mips_int_operand
*operand
;
18605 unsigned int user_length
;
18606 bfd_boolean need_reloc
;
18607 unsigned long insn
;
18612 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18613 operand
= mips16_immed_operand (type
, FALSE
);
18615 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18616 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18617 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18619 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18620 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18621 || (operand
->root
.type
== OP_PCREL
&& !mac
18623 : !bfd_is_abs_section (symsec
)));
18625 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18627 const struct mips_pcrel_operand
*pcrel_op
;
18629 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18631 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18633 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18634 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18635 _("branch to a symbol in another ISA mode"));
18636 else if ((fragp
->fr_offset
& 0x1) != 0)
18637 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18638 _("branch to misaligned address (0x%lx)"),
18642 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18644 /* Make sure the section winds up with the alignment we have
18646 if (operand
->shift
> 0)
18647 record_alignment (asec
, operand
->shift
);
18650 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18651 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18654 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18655 _("macro instruction expanded into multiple "
18656 "instructions in a branch delay slot"));
18658 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18659 _("extended instruction in a branch delay slot"));
18661 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18662 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18663 _("macro instruction expanded into multiple "
18666 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18668 insn
= read_compressed_insn (buf
, 2);
18670 insn
|= MIPS16_EXTEND
;
18672 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18674 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18686 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18687 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18689 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18695 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18697 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18698 fragp
->fr_symbol
, fragp
->fr_offset
,
18699 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18700 fixp
->fx_file
= fragp
->fr_file
;
18701 fixp
->fx_line
= fragp
->fr_line
;
18703 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18704 fragp
->fr_symbol
, fragp
->fr_offset
,
18705 FALSE
, BFD_RELOC_MIPS16_LO16
);
18706 fixp
->fx_file
= fragp
->fr_file
;
18707 fixp
->fx_line
= fragp
->fr_line
;
18712 switch (insn
& 0xf800)
18714 case 0x0800: /* ADDIU */
18715 reg
= (insn
>> 8) & 0x7;
18716 op
= 0xf0004800 | (reg
<< 8);
18718 case 0xb000: /* LW */
18719 reg
= (insn
>> 8) & 0x7;
18720 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18722 case 0xf800: /* I64 */
18723 reg
= (insn
>> 5) & 0x7;
18724 switch (insn
& 0x0700)
18726 case 0x0400: /* LD */
18727 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18729 case 0x0600: /* DADDIU */
18730 op
= 0xf000fd00 | (reg
<< 5);
18740 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
18741 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18742 buf
= write_compressed_insn (buf
, new, 4);
18745 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18746 buf
= write_compressed_insn (buf
, new, 4);
18748 op
|= mips16_immed_extend (val
, 16);
18749 buf
= write_compressed_insn (buf
, op
, 4);
18751 fragp
->fr_fix
+= e2
? 8 : 12;
18755 unsigned int length
= ext
? 4 : 2;
18759 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18767 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18772 if (mac
|| reloc
== BFD_RELOC_NONE
)
18773 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18774 _("unsupported relocation"));
18777 exp
.X_op
= O_symbol
;
18778 exp
.X_add_symbol
= fragp
->fr_symbol
;
18779 exp
.X_add_number
= fragp
->fr_offset
;
18781 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18784 fixp
->fx_file
= fragp
->fr_file
;
18785 fixp
->fx_line
= fragp
->fr_line
;
18788 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18789 _("invalid unextended operand value"));
18792 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18793 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18795 gas_assert (mips16_opcode_length (insn
) == length
);
18796 write_compressed_insn (buf
, insn
, length
);
18797 fragp
->fr_fix
+= length
;
18802 relax_substateT subtype
= fragp
->fr_subtype
;
18803 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18804 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18808 first
= RELAX_FIRST (subtype
);
18809 second
= RELAX_SECOND (subtype
);
18810 fixp
= (fixS
*) fragp
->fr_opcode
;
18812 /* If the delay slot chosen does not match the size of the instruction,
18813 then emit a warning. */
18814 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18815 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18820 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18821 | RELAX_DELAY_SLOT_SIZE_FIRST
18822 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18823 msg
= macro_warning (s
);
18825 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18829 /* Possibly emit a warning if we've chosen the longer option. */
18830 if (use_second
== second_longer
)
18836 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18837 msg
= macro_warning (s
);
18839 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18843 /* Go through all the fixups for the first sequence. Disable them
18844 (by marking them as done) if we're going to use the second
18845 sequence instead. */
18847 && fixp
->fx_frag
== fragp
18848 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18850 if (subtype
& RELAX_USE_SECOND
)
18852 fixp
= fixp
->fx_next
;
18855 /* Go through the fixups for the second sequence. Disable them if
18856 we're going to use the first sequence, otherwise adjust their
18857 addresses to account for the relaxation. */
18858 while (fixp
&& fixp
->fx_frag
== fragp
)
18860 if (subtype
& RELAX_USE_SECOND
)
18861 fixp
->fx_where
-= first
;
18864 fixp
= fixp
->fx_next
;
18867 /* Now modify the frag contents. */
18868 if (subtype
& RELAX_USE_SECOND
)
18872 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18873 memmove (start
, start
+ first
, second
);
18874 fragp
->fr_fix
-= first
;
18877 fragp
->fr_fix
-= second
;
18881 /* This function is called after the relocs have been generated.
18882 We've been storing mips16 text labels as odd. Here we convert them
18883 back to even for the convenience of the debugger. */
18886 mips_frob_file_after_relocs (void)
18889 unsigned int count
, i
;
18891 syms
= bfd_get_outsymbols (stdoutput
);
18892 count
= bfd_get_symcount (stdoutput
);
18893 for (i
= 0; i
< count
; i
++, syms
++)
18894 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18895 && ((*syms
)->value
& 1) != 0)
18897 (*syms
)->value
&= ~1;
18898 /* If the symbol has an odd size, it was probably computed
18899 incorrectly, so adjust that as well. */
18900 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18901 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18905 /* This function is called whenever a label is defined, including fake
18906 labels instantiated off the dot special symbol. It is used when
18907 handling branch delays; if a branch has a label, we assume we cannot
18908 move it. This also bumps the value of the symbol by 1 in compressed
18912 mips_record_label (symbolS
*sym
)
18914 segment_info_type
*si
= seg_info (now_seg
);
18915 struct insn_label_list
*l
;
18917 if (free_insn_labels
== NULL
)
18918 l
= XNEW (struct insn_label_list
);
18921 l
= free_insn_labels
;
18922 free_insn_labels
= l
->next
;
18926 l
->next
= si
->label_list
;
18927 si
->label_list
= l
;
18930 /* This function is called as tc_frob_label() whenever a label is defined
18931 and adds a DWARF-2 record we only want for true labels. */
18934 mips_define_label (symbolS
*sym
)
18936 mips_record_label (sym
);
18937 dwarf2_emit_label (sym
);
18940 /* This function is called by tc_new_dot_label whenever a new dot symbol
18944 mips_add_dot_label (symbolS
*sym
)
18946 mips_record_label (sym
);
18947 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18948 mips_compressed_mark_label (sym
);
18951 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18952 static unsigned int
18953 mips_convert_ase_flags (int ase
)
18955 unsigned int ext_ases
= 0;
18958 ext_ases
|= AFL_ASE_DSP
;
18959 if (ase
& ASE_DSPR2
)
18960 ext_ases
|= AFL_ASE_DSPR2
;
18961 if (ase
& ASE_DSPR3
)
18962 ext_ases
|= AFL_ASE_DSPR3
;
18964 ext_ases
|= AFL_ASE_EVA
;
18966 ext_ases
|= AFL_ASE_MCU
;
18967 if (ase
& ASE_MDMX
)
18968 ext_ases
|= AFL_ASE_MDMX
;
18969 if (ase
& ASE_MIPS3D
)
18970 ext_ases
|= AFL_ASE_MIPS3D
;
18972 ext_ases
|= AFL_ASE_MT
;
18973 if (ase
& ASE_SMARTMIPS
)
18974 ext_ases
|= AFL_ASE_SMARTMIPS
;
18975 if (ase
& ASE_VIRT
)
18976 ext_ases
|= AFL_ASE_VIRT
;
18978 ext_ases
|= AFL_ASE_MSA
;
18980 ext_ases
|= AFL_ASE_XPA
;
18981 if (ase
& ASE_MIPS16E2
)
18982 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
18986 /* Some special processing for a MIPS ELF file. */
18989 mips_elf_final_processing (void)
18992 Elf_Internal_ABIFlags_v0 flags
;
18996 switch (file_mips_opts
.isa
)
18999 flags
.isa_level
= 1;
19002 flags
.isa_level
= 2;
19005 flags
.isa_level
= 3;
19008 flags
.isa_level
= 4;
19011 flags
.isa_level
= 5;
19014 flags
.isa_level
= 32;
19018 flags
.isa_level
= 32;
19022 flags
.isa_level
= 32;
19026 flags
.isa_level
= 32;
19030 flags
.isa_level
= 32;
19034 flags
.isa_level
= 64;
19038 flags
.isa_level
= 64;
19042 flags
.isa_level
= 64;
19046 flags
.isa_level
= 64;
19050 flags
.isa_level
= 64;
19055 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19056 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19057 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19058 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19060 flags
.cpr2_size
= AFL_REG_NONE
;
19061 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19062 Tag_GNU_MIPS_ABI_FP
);
19063 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19064 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19065 if (file_ase_mips16
)
19066 flags
.ases
|= AFL_ASE_MIPS16
;
19067 if (file_ase_micromips
)
19068 flags
.ases
|= AFL_ASE_MICROMIPS
;
19070 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19071 || file_mips_opts
.fp
== 64)
19072 && file_mips_opts
.oddspreg
)
19073 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19076 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19077 ((Elf_External_ABIFlags_v0
*)
19080 /* Write out the register information. */
19081 if (mips_abi
!= N64_ABI
)
19085 s
.ri_gprmask
= mips_gprmask
;
19086 s
.ri_cprmask
[0] = mips_cprmask
[0];
19087 s
.ri_cprmask
[1] = mips_cprmask
[1];
19088 s
.ri_cprmask
[2] = mips_cprmask
[2];
19089 s
.ri_cprmask
[3] = mips_cprmask
[3];
19090 /* The gp_value field is set by the MIPS ELF backend. */
19092 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19093 ((Elf32_External_RegInfo
*)
19094 mips_regmask_frag
));
19098 Elf64_Internal_RegInfo s
;
19100 s
.ri_gprmask
= mips_gprmask
;
19102 s
.ri_cprmask
[0] = mips_cprmask
[0];
19103 s
.ri_cprmask
[1] = mips_cprmask
[1];
19104 s
.ri_cprmask
[2] = mips_cprmask
[2];
19105 s
.ri_cprmask
[3] = mips_cprmask
[3];
19106 /* The gp_value field is set by the MIPS ELF backend. */
19108 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19109 ((Elf64_External_RegInfo
*)
19110 mips_regmask_frag
));
19113 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19114 sort of BFD interface for this. */
19115 if (mips_any_noreorder
)
19116 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19117 if (mips_pic
!= NO_PIC
)
19119 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19120 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19123 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19125 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19126 defined at present; this might need to change in future. */
19127 if (file_ase_mips16
)
19128 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19129 if (file_ase_micromips
)
19130 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19131 if (file_mips_opts
.ase
& ASE_MDMX
)
19132 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19134 /* Set the MIPS ELF ABI flags. */
19135 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19136 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19137 else if (mips_abi
== O64_ABI
)
19138 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19139 else if (mips_abi
== EABI_ABI
)
19141 if (file_mips_opts
.gp
== 64)
19142 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19144 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19146 else if (mips_abi
== N32_ABI
)
19147 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
19149 /* Nothing to do for N64_ABI. */
19151 if (mips_32bitmode
)
19152 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19154 if (mips_nan2008
== 1)
19155 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19157 /* 32 bit code with 64 bit FP registers. */
19158 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19159 Tag_GNU_MIPS_ABI_FP
);
19160 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19161 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19164 typedef struct proc
{
19166 symbolS
*func_end_sym
;
19167 unsigned long reg_mask
;
19168 unsigned long reg_offset
;
19169 unsigned long fpreg_mask
;
19170 unsigned long fpreg_offset
;
19171 unsigned long frame_offset
;
19172 unsigned long frame_reg
;
19173 unsigned long pc_reg
;
19176 static procS cur_proc
;
19177 static procS
*cur_proc_ptr
;
19178 static int numprocs
;
19180 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19181 as "2", and a normal nop as "0". */
19183 #define NOP_OPCODE_MIPS 0
19184 #define NOP_OPCODE_MIPS16 1
19185 #define NOP_OPCODE_MICROMIPS 2
19188 mips_nop_opcode (void)
19190 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19191 return NOP_OPCODE_MICROMIPS
;
19192 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19193 return NOP_OPCODE_MIPS16
;
19195 return NOP_OPCODE_MIPS
;
19198 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19199 32-bit microMIPS NOPs here (if applicable). */
19202 mips_handle_align (fragS
*fragp
)
19206 int bytes
, size
, excess
;
19209 if (fragp
->fr_type
!= rs_align_code
)
19212 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19214 switch (nop_opcode
)
19216 case NOP_OPCODE_MICROMIPS
:
19217 opcode
= micromips_nop32_insn
.insn_opcode
;
19220 case NOP_OPCODE_MIPS16
:
19221 opcode
= mips16_nop_insn
.insn_opcode
;
19224 case NOP_OPCODE_MIPS
:
19226 opcode
= nop_insn
.insn_opcode
;
19231 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19232 excess
= bytes
% size
;
19234 /* Handle the leading part if we're not inserting a whole number of
19235 instructions, and make it the end of the fixed part of the frag.
19236 Try to fit in a short microMIPS NOP if applicable and possible,
19237 and use zeroes otherwise. */
19238 gas_assert (excess
< 4);
19239 fragp
->fr_fix
+= excess
;
19244 /* Fall through. */
19246 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19248 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19252 /* Fall through. */
19255 /* Fall through. */
19260 md_number_to_chars (p
, opcode
, size
);
19261 fragp
->fr_var
= size
;
19270 if (*input_line_pointer
== '-')
19272 ++input_line_pointer
;
19275 if (!ISDIGIT (*input_line_pointer
))
19276 as_bad (_("expected simple number"));
19277 if (input_line_pointer
[0] == '0')
19279 if (input_line_pointer
[1] == 'x')
19281 input_line_pointer
+= 2;
19282 while (ISXDIGIT (*input_line_pointer
))
19285 val
|= hex_value (*input_line_pointer
++);
19287 return negative
? -val
: val
;
19291 ++input_line_pointer
;
19292 while (ISDIGIT (*input_line_pointer
))
19295 val
|= *input_line_pointer
++ - '0';
19297 return negative
? -val
: val
;
19300 if (!ISDIGIT (*input_line_pointer
))
19302 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19303 *input_line_pointer
, *input_line_pointer
);
19304 as_warn (_("invalid number"));
19307 while (ISDIGIT (*input_line_pointer
))
19310 val
+= *input_line_pointer
++ - '0';
19312 return negative
? -val
: val
;
19315 /* The .file directive; just like the usual .file directive, but there
19316 is an initial number which is the ECOFF file index. In the non-ECOFF
19317 case .file implies DWARF-2. */
19320 s_mips_file (int x ATTRIBUTE_UNUSED
)
19322 static int first_file_directive
= 0;
19324 if (ECOFF_DEBUGGING
)
19333 filename
= dwarf2_directive_file (0);
19335 /* Versions of GCC up to 3.1 start files with a ".file"
19336 directive even for stabs output. Make sure that this
19337 ".file" is handled. Note that you need a version of GCC
19338 after 3.1 in order to support DWARF-2 on MIPS. */
19339 if (filename
!= NULL
&& ! first_file_directive
)
19341 (void) new_logical_line (filename
, -1);
19342 s_app_file_string (filename
, 0);
19344 first_file_directive
= 1;
19348 /* The .loc directive, implying DWARF-2. */
19351 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19353 if (!ECOFF_DEBUGGING
)
19354 dwarf2_directive_loc (0);
19357 /* The .end directive. */
19360 s_mips_end (int x ATTRIBUTE_UNUSED
)
19364 /* Following functions need their own .frame and .cprestore directives. */
19365 mips_frame_reg_valid
= 0;
19366 mips_cprestore_valid
= 0;
19368 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19371 demand_empty_rest_of_line ();
19376 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19377 as_warn (_(".end not in text section"));
19381 as_warn (_(".end directive without a preceding .ent directive"));
19382 demand_empty_rest_of_line ();
19388 gas_assert (S_GET_NAME (p
));
19389 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19390 as_warn (_(".end symbol does not match .ent symbol"));
19392 if (debug_type
== DEBUG_STABS
)
19393 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19397 as_warn (_(".end directive missing or unknown symbol"));
19399 /* Create an expression to calculate the size of the function. */
19400 if (p
&& cur_proc_ptr
)
19402 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19403 expressionS
*exp
= XNEW (expressionS
);
19406 exp
->X_op
= O_subtract
;
19407 exp
->X_add_symbol
= symbol_temp_new_now ();
19408 exp
->X_op_symbol
= p
;
19409 exp
->X_add_number
= 0;
19411 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19414 #ifdef md_flush_pending_output
19415 md_flush_pending_output ();
19418 /* Generate a .pdr section. */
19419 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19421 segT saved_seg
= now_seg
;
19422 subsegT saved_subseg
= now_subseg
;
19426 gas_assert (pdr_seg
);
19427 subseg_set (pdr_seg
, 0);
19429 /* Write the symbol. */
19430 exp
.X_op
= O_symbol
;
19431 exp
.X_add_symbol
= p
;
19432 exp
.X_add_number
= 0;
19433 emit_expr (&exp
, 4);
19435 fragp
= frag_more (7 * 4);
19437 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19438 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19439 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19440 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19441 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19442 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19443 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19445 subseg_set (saved_seg
, saved_subseg
);
19448 cur_proc_ptr
= NULL
;
19451 /* The .aent and .ent directives. */
19454 s_mips_ent (int aent
)
19458 symbolP
= get_symbol ();
19459 if (*input_line_pointer
== ',')
19460 ++input_line_pointer
;
19461 SKIP_WHITESPACE ();
19462 if (ISDIGIT (*input_line_pointer
)
19463 || *input_line_pointer
== '-')
19466 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19467 as_warn (_(".ent or .aent not in text section"));
19469 if (!aent
&& cur_proc_ptr
)
19470 as_warn (_("missing .end"));
19474 /* This function needs its own .frame and .cprestore directives. */
19475 mips_frame_reg_valid
= 0;
19476 mips_cprestore_valid
= 0;
19478 cur_proc_ptr
= &cur_proc
;
19479 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19481 cur_proc_ptr
->func_sym
= symbolP
;
19485 if (debug_type
== DEBUG_STABS
)
19486 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19487 S_GET_NAME (symbolP
));
19490 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19492 demand_empty_rest_of_line ();
19495 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19496 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19497 s_mips_frame is used so that we can set the PDR information correctly.
19498 We can't use the ecoff routines because they make reference to the ecoff
19499 symbol table (in the mdebug section). */
19502 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19504 if (ECOFF_DEBUGGING
)
19510 if (cur_proc_ptr
== (procS
*) NULL
)
19512 as_warn (_(".frame outside of .ent"));
19513 demand_empty_rest_of_line ();
19517 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19519 SKIP_WHITESPACE ();
19520 if (*input_line_pointer
++ != ','
19521 || get_absolute_expression_and_terminator (&val
) != ',')
19523 as_warn (_("bad .frame directive"));
19524 --input_line_pointer
;
19525 demand_empty_rest_of_line ();
19529 cur_proc_ptr
->frame_offset
= val
;
19530 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19532 demand_empty_rest_of_line ();
19536 /* The .fmask and .mask directives. If the mdebug section is present
19537 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19538 embedded targets, s_mips_mask is used so that we can set the PDR
19539 information correctly. We can't use the ecoff routines because they
19540 make reference to the ecoff symbol table (in the mdebug section). */
19543 s_mips_mask (int reg_type
)
19545 if (ECOFF_DEBUGGING
)
19546 s_ignore (reg_type
);
19551 if (cur_proc_ptr
== (procS
*) NULL
)
19553 as_warn (_(".mask/.fmask outside of .ent"));
19554 demand_empty_rest_of_line ();
19558 if (get_absolute_expression_and_terminator (&mask
) != ',')
19560 as_warn (_("bad .mask/.fmask directive"));
19561 --input_line_pointer
;
19562 demand_empty_rest_of_line ();
19566 off
= get_absolute_expression ();
19568 if (reg_type
== 'F')
19570 cur_proc_ptr
->fpreg_mask
= mask
;
19571 cur_proc_ptr
->fpreg_offset
= off
;
19575 cur_proc_ptr
->reg_mask
= mask
;
19576 cur_proc_ptr
->reg_offset
= off
;
19579 demand_empty_rest_of_line ();
19583 /* A table describing all the processors gas knows about. Names are
19584 matched in the order listed.
19586 To ease comparison, please keep this table in the same order as
19587 gcc's mips_cpu_info_table[]. */
19588 static const struct mips_cpu_info mips_cpu_info_table
[] =
19590 /* Entries for generic ISAs */
19591 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19592 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19593 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19594 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19595 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19596 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19597 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19598 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19599 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19600 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19601 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19602 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19603 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19604 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19605 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19608 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19609 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19610 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19613 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19616 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19617 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19618 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19619 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19620 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19621 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19622 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19623 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19624 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19625 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19626 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19627 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19628 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19629 /* ST Microelectronics Loongson 2E and 2F cores */
19630 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19631 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19634 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19635 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19636 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19637 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19638 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19639 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19640 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19641 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19642 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19643 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19644 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19645 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19646 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19647 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19648 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19651 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19652 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19653 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19654 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19656 /* MIPS 32 Release 2 */
19657 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19658 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19659 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19660 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19661 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19662 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19663 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19664 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19665 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19666 ISA_MIPS32R2
, CPU_MIPS32R2
},
19667 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19668 ISA_MIPS32R2
, CPU_MIPS32R2
},
19669 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19670 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19671 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19672 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19673 /* Deprecated forms of the above. */
19674 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19675 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19676 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19677 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19678 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19679 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19680 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19681 /* Deprecated forms of the above. */
19682 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19683 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19684 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19685 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19686 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19687 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19688 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19689 /* Deprecated forms of the above. */
19690 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19691 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19692 /* 34Kn is a 34kc without DSP. */
19693 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19694 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19695 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19696 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19697 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19698 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19699 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19700 /* Deprecated forms of the above. */
19701 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19702 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19703 /* 1004K cores are multiprocessor versions of the 34K. */
19704 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19705 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19706 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19707 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19708 /* interaptiv is the new name for 1004kf */
19709 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19710 { "interaptiv-mr2", 0,
19711 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19712 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19714 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19715 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19716 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19717 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19720 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19721 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19722 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19723 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19725 /* Broadcom SB-1 CPU core */
19726 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19727 /* Broadcom SB-1A CPU core */
19728 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19730 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19732 /* MIPS 64 Release 2 */
19734 /* Cavium Networks Octeon CPU core */
19735 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19736 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19737 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19738 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19741 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19744 XLP is mostly like XLR, with the prominent exception that it is
19745 MIPS64R2 rather than MIPS64. */
19746 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19748 /* MIPS 64 Release 6 */
19749 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19750 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19753 { NULL
, 0, 0, 0, 0 }
19757 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19758 with a final "000" replaced by "k". Ignore case.
19760 Note: this function is shared between GCC and GAS. */
19763 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19765 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19766 given
++, canonical
++;
19768 return ((*given
== 0 && *canonical
== 0)
19769 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19773 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19774 CPU name. We've traditionally allowed a lot of variation here.
19776 Note: this function is shared between GCC and GAS. */
19779 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19781 /* First see if the name matches exactly, or with a final "000"
19782 turned into "k". */
19783 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19786 /* If not, try comparing based on numerical designation alone.
19787 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19788 if (TOLOWER (*given
) == 'r')
19790 if (!ISDIGIT (*given
))
19793 /* Skip over some well-known prefixes in the canonical name,
19794 hoping to find a number there too. */
19795 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19797 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19799 else if (TOLOWER (canonical
[0]) == 'r')
19802 return mips_strict_matching_cpu_name_p (canonical
, given
);
19806 /* Parse an option that takes the name of a processor as its argument.
19807 OPTION is the name of the option and CPU_STRING is the argument.
19808 Return the corresponding processor enumeration if the CPU_STRING is
19809 recognized, otherwise report an error and return null.
19811 A similar function exists in GCC. */
19813 static const struct mips_cpu_info
*
19814 mips_parse_cpu (const char *option
, const char *cpu_string
)
19816 const struct mips_cpu_info
*p
;
19818 /* 'from-abi' selects the most compatible architecture for the given
19819 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19820 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19821 version. Look first at the -mgp options, if given, otherwise base
19822 the choice on MIPS_DEFAULT_64BIT.
19824 Treat NO_ABI like the EABIs. One reason to do this is that the
19825 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19826 architecture. This code picks MIPS I for 'mips' and MIPS III for
19827 'mips64', just as we did in the days before 'from-abi'. */
19828 if (strcasecmp (cpu_string
, "from-abi") == 0)
19830 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19831 return mips_cpu_info_from_isa (ISA_MIPS1
);
19833 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19834 return mips_cpu_info_from_isa (ISA_MIPS3
);
19836 if (file_mips_opts
.gp
>= 0)
19837 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19838 ? ISA_MIPS1
: ISA_MIPS3
);
19840 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19845 /* 'default' has traditionally been a no-op. Probably not very useful. */
19846 if (strcasecmp (cpu_string
, "default") == 0)
19849 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19850 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19853 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19857 /* Return the canonical processor information for ISA (a member of the
19858 ISA_MIPS* enumeration). */
19860 static const struct mips_cpu_info
*
19861 mips_cpu_info_from_isa (int isa
)
19865 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19866 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19867 && isa
== mips_cpu_info_table
[i
].isa
)
19868 return (&mips_cpu_info_table
[i
]);
19873 static const struct mips_cpu_info
*
19874 mips_cpu_info_from_arch (int arch
)
19878 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19879 if (arch
== mips_cpu_info_table
[i
].cpu
)
19880 return (&mips_cpu_info_table
[i
]);
19886 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19890 fprintf (stream
, "%24s", "");
19895 fprintf (stream
, ", ");
19899 if (*col_p
+ strlen (string
) > 72)
19901 fprintf (stream
, "\n%24s", "");
19905 fprintf (stream
, "%s", string
);
19906 *col_p
+= strlen (string
);
19912 md_show_usage (FILE *stream
)
19917 fprintf (stream
, _("\
19919 -EB generate big endian output\n\
19920 -EL generate little endian output\n\
19921 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19922 -G NUM allow referencing objects up to NUM bytes\n\
19923 implicitly with the gp register [default 8]\n"));
19924 fprintf (stream
, _("\
19925 -mips1 generate MIPS ISA I instructions\n\
19926 -mips2 generate MIPS ISA II instructions\n\
19927 -mips3 generate MIPS ISA III instructions\n\
19928 -mips4 generate MIPS ISA IV instructions\n\
19929 -mips5 generate MIPS ISA V instructions\n\
19930 -mips32 generate MIPS32 ISA instructions\n\
19931 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19932 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19933 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19934 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19935 -mips64 generate MIPS64 ISA instructions\n\
19936 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19937 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19938 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19939 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19940 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19944 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19945 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19946 show (stream
, "from-abi", &column
, &first
);
19947 fputc ('\n', stream
);
19949 fprintf (stream
, _("\
19950 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19951 -no-mCPU don't generate code specific to CPU.\n\
19952 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19956 show (stream
, "3900", &column
, &first
);
19957 show (stream
, "4010", &column
, &first
);
19958 show (stream
, "4100", &column
, &first
);
19959 show (stream
, "4650", &column
, &first
);
19960 fputc ('\n', stream
);
19962 fprintf (stream
, _("\
19963 -mips16 generate mips16 instructions\n\
19964 -no-mips16 do not generate mips16 instructions\n"));
19965 fprintf (stream
, _("\
19966 -mmicromips generate microMIPS instructions\n\
19967 -mno-micromips do not generate microMIPS instructions\n"));
19968 fprintf (stream
, _("\
19969 -msmartmips generate smartmips instructions\n\
19970 -mno-smartmips do not generate smartmips instructions\n"));
19971 fprintf (stream
, _("\
19972 -mdsp generate DSP instructions\n\
19973 -mno-dsp do not generate DSP instructions\n"));
19974 fprintf (stream
, _("\
19975 -mdspr2 generate DSP R2 instructions\n\
19976 -mno-dspr2 do not generate DSP R2 instructions\n"));
19977 fprintf (stream
, _("\
19978 -mdspr3 generate DSP R3 instructions\n\
19979 -mno-dspr3 do not generate DSP R3 instructions\n"));
19980 fprintf (stream
, _("\
19981 -mmt generate MT instructions\n\
19982 -mno-mt do not generate MT instructions\n"));
19983 fprintf (stream
, _("\
19984 -mmcu generate MCU instructions\n\
19985 -mno-mcu do not generate MCU instructions\n"));
19986 fprintf (stream
, _("\
19987 -mmsa generate MSA instructions\n\
19988 -mno-msa do not generate MSA instructions\n"));
19989 fprintf (stream
, _("\
19990 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19991 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19992 fprintf (stream
, _("\
19993 -mvirt generate Virtualization instructions\n\
19994 -mno-virt do not generate Virtualization instructions\n"));
19995 fprintf (stream
, _("\
19996 -minsn32 only generate 32-bit microMIPS instructions\n\
19997 -mno-insn32 generate all microMIPS instructions\n"));
19998 fprintf (stream
, _("\
19999 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20000 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20001 -mfix-vr4120 work around certain VR4120 errata\n\
20002 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20003 -mfix-24k insert a nop after ERET and DERET instructions\n\
20004 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20005 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20006 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20007 -msym32 assume all symbols have 32-bit values\n\
20008 -O0 remove unneeded NOPs, do not swap branches\n\
20009 -O remove unneeded NOPs and swap branches\n\
20010 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20011 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20012 fprintf (stream
, _("\
20013 -mhard-float allow floating-point instructions\n\
20014 -msoft-float do not allow floating-point instructions\n\
20015 -msingle-float only allow 32-bit floating-point operations\n\
20016 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20017 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20018 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20019 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20020 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20021 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20025 show (stream
, "legacy", &column
, &first
);
20026 show (stream
, "2008", &column
, &first
);
20028 fputc ('\n', stream
);
20030 fprintf (stream
, _("\
20031 -KPIC, -call_shared generate SVR4 position independent code\n\
20032 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20033 -mvxworks-pic generate VxWorks position independent code\n\
20034 -non_shared do not generate code that can operate with DSOs\n\
20035 -xgot assume a 32 bit GOT\n\
20036 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20037 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20038 position dependent (non shared) code\n\
20039 -mabi=ABI create ABI conformant object file for:\n"));
20043 show (stream
, "32", &column
, &first
);
20044 show (stream
, "o64", &column
, &first
);
20045 show (stream
, "n32", &column
, &first
);
20046 show (stream
, "64", &column
, &first
);
20047 show (stream
, "eabi", &column
, &first
);
20049 fputc ('\n', stream
);
20051 fprintf (stream
, _("\
20052 -32 create o32 ABI object file (default)\n\
20053 -n32 create n32 ABI object file\n\
20054 -64 create 64 ABI object file\n"));
20059 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20061 if (HAVE_64BIT_SYMBOLS
)
20062 return dwarf2_format_64bit_irix
;
20064 return dwarf2_format_32bit
;
20069 mips_dwarf2_addr_size (void)
20071 if (HAVE_64BIT_OBJECTS
)
20077 /* Standard calling conventions leave the CFA at SP on entry. */
20079 mips_cfi_frame_initial_instructions (void)
20081 cfi_add_CFA_def_cfa_register (SP
);
20085 tc_mips_regname_to_dw2regnum (char *regname
)
20087 unsigned int regnum
= -1;
20090 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20096 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20097 Given a symbolic attribute NAME, return the proper integer value.
20098 Returns -1 if the attribute is not known. */
20101 mips_convert_symbolic_attribute (const char *name
)
20103 static const struct
20108 attribute_table
[] =
20110 #define T(tag) {#tag, tag}
20111 T (Tag_GNU_MIPS_ABI_FP
),
20112 T (Tag_GNU_MIPS_ABI_MSA
),
20120 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20121 if (streq (name
, attribute_table
[i
].name
))
20122 return attribute_table
[i
].tag
;
20130 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20132 mips_emit_delays ();
20134 as_warn (_("missing .end at end of assembly"));
20136 /* Just in case no code was emitted, do the consistency check. */
20137 file_mips_check_options ();
20139 /* Set a floating-point ABI if the user did not. */
20140 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20142 /* Perform consistency checks on the floating-point ABI. */
20143 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20144 Tag_GNU_MIPS_ABI_FP
);
20145 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20146 check_fpabi (fpabi
);
20150 /* Soft-float gets precedence over single-float, the two options should
20151 not be used together so this should not matter. */
20152 if (file_mips_opts
.soft_float
== 1)
20153 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20154 /* Single-float gets precedence over all double_float cases. */
20155 else if (file_mips_opts
.single_float
== 1)
20156 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20159 switch (file_mips_opts
.fp
)
20162 if (file_mips_opts
.gp
== 32)
20163 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20166 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20169 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20170 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20171 else if (file_mips_opts
.gp
== 32)
20172 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20174 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20179 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20180 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20184 /* Returns the relocation type required for a particular CFI encoding. */
20186 bfd_reloc_code_real_type
20187 mips_cfi_reloc_for_encoding (int encoding
)
20189 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20190 return BFD_RELOC_32_PCREL
;
20191 else return BFD_RELOC_NONE
;