1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
96 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
98 static unsigned elf_flags
= 0;
100 /* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
104 riscv_set_default_isa_spec (const char *s
)
106 enum riscv_isa_spec_class
class;
107 if (!riscv_get_isa_spec_class (s
, &class))
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s
);
114 default_isa_spec
= class;
118 /* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
124 riscv_set_default_priv_spec (const char *s
)
126 enum riscv_priv_spec_class
class;
127 unsigned major
, minor
, revision
;
130 /* Find the corresponding priv spec class. */
131 if (riscv_get_priv_spec_class (s
, &class))
133 default_priv_spec
= class;
139 as_bad (_("Unknown default privilege spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s
);
144 /* Try to set the default_priv_spec according to the priv attributes. */
145 attr
= elf_known_obj_attributes_proc (stdoutput
);
146 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
147 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
148 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
150 if (riscv_get_priv_spec_class_from_numbers (major
,
155 /* The priv attributes setting 0.0.0 is meaningless. We should have set
156 the default_priv_spec by md_parse_option and riscv_after_parse_args,
157 so just skip the following setting. */
158 if (class == PRIV_SPEC_CLASS_NONE
)
161 default_priv_spec
= class;
165 /* Still can not find the priv spec class. */
166 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
167 "privilege attributes"), major
, minor
, revision
);
171 /* This is the set of options which the .option pseudo-op may modify. */
173 struct riscv_set_options
175 int pic
; /* Generate position-independent code. */
176 int rvc
; /* Generate RVC code. */
177 int rve
; /* Generate RVE code. */
178 int relax
; /* Emit relocs the linker is allowed to relax. */
179 int arch_attr
; /* Emit arch attribute. */
180 int csr_check
; /* Enable the CSR checking. */
183 static struct riscv_set_options riscv_opts
=
189 DEFAULT_RISCV_ATTR
, /* arch_attr */
194 riscv_set_rvc (bfd_boolean rvc_value
)
197 elf_flags
|= EF_RISCV_RVC
;
199 riscv_opts
.rvc
= rvc_value
;
203 riscv_set_rve (bfd_boolean rve_value
)
205 riscv_opts
.rve
= rve_value
;
208 static riscv_subset_list_t riscv_subsets
;
211 riscv_subset_supports (const char *feature
)
213 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
216 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
220 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
224 case INSN_CLASS_I
: return riscv_subset_supports ("i");
225 case INSN_CLASS_C
: return riscv_subset_supports ("c");
226 case INSN_CLASS_A
: return riscv_subset_supports ("a");
227 case INSN_CLASS_M
: return riscv_subset_supports ("m");
228 case INSN_CLASS_F
: return riscv_subset_supports ("f");
229 case INSN_CLASS_D
: return riscv_subset_supports ("d");
230 case INSN_CLASS_D_AND_C
:
231 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
233 case INSN_CLASS_F_AND_C
:
234 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
236 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
239 as_fatal ("Unreachable");
244 /* Handle of the extension with version hash table. */
245 static struct hash_control
*ext_version_hash
= NULL
;
247 static struct hash_control
*
248 init_ext_version_hash (const struct riscv_ext_version
*table
)
251 struct hash_control
*hash
= hash_new ();
253 while (table
[i
].name
)
255 const char *name
= table
[i
].name
;
256 const char *hash_error
=
257 hash_insert (hash
, name
, (void *) &table
[i
]);
259 if (hash_error
!= NULL
)
261 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
262 table
[i
].name
, hash_error
);
263 /* Probably a memory allocation problem? Give up now. */
264 as_fatal (_("Broken assembler. No assembly attempted."));
270 && strcmp (table
[i
].name
, name
) == 0)
278 riscv_get_default_ext_version (const char *name
,
279 unsigned int *major_version
,
280 unsigned int *minor_version
)
282 struct riscv_ext_version
*ext
;
287 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
290 ext
= (struct riscv_ext_version
*) hash_find (ext_version_hash
, name
);
293 && strcmp (ext
->name
, name
) == 0)
295 if (ext
->isa_spec_class
== default_isa_spec
)
297 *major_version
= ext
->major_version
;
298 *minor_version
= ext
->minor_version
;
305 /* Set which ISA and extensions are available. */
308 riscv_set_arch (const char *s
)
310 riscv_parse_subset_t rps
;
311 rps
.subset_list
= &riscv_subsets
;
312 rps
.error_handler
= as_fatal
;
314 rps
.get_default_version
= riscv_get_default_ext_version
;
319 riscv_release_subset_list (&riscv_subsets
);
320 riscv_parse_subset (&rps
, s
);
323 /* Handle of the OPCODE hash table. */
324 static struct hash_control
*op_hash
= NULL
;
326 /* Handle of the type of .insn hash table. */
327 static struct hash_control
*insn_type_hash
= NULL
;
329 /* This array holds the chars that always start a comment. If the
330 pre-processor is disabled, these aren't very useful */
331 const char comment_chars
[] = "#";
333 /* This array holds the chars that only start a comment at the beginning of
334 a line. If the line seems to have the form '# 123 filename'
335 .line and .file directives will appear in the pre-processed output */
336 /* Note that input_file.c hand checks for '#' at the beginning of the
337 first line of the input file. This is because the compiler outputs
338 #NO_APP at the beginning of its output. */
339 /* Also note that C style comments are always supported. */
340 const char line_comment_chars
[] = "#";
342 /* This array holds machine specific line separator characters. */
343 const char line_separator_chars
[] = ";";
345 /* Chars that can be used to separate mant from exp in floating point nums */
346 const char EXP_CHARS
[] = "eE";
348 /* Chars that mean this number is a floating point constant */
351 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
353 /* Indicate we are already assemble any instructions or not. */
354 static bfd_boolean start_assemble
= FALSE
;
356 /* Indicate ELF attributes are explictly set. */
357 static bfd_boolean explicit_attr
= FALSE
;
359 /* Indicate CSR or priv instructions are explictly used. */
360 static bfd_boolean explicit_priv_attr
= FALSE
;
362 /* Macros for encoding relaxation state for RVC branches and far jumps. */
363 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
366 | ((uncond) ? 1 : 0) \
369 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
370 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
371 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
372 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
374 /* Is the given value a sign-extended 32-bit value? */
375 #define IS_SEXT_32BIT_NUM(x) \
376 (((x) &~ (offsetT) 0x7fffffff) == 0 \
377 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
379 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
380 #define IS_ZEXT_32BIT_NUM(x) \
381 (((x) &~ (offsetT) 0xffffffff) == 0 \
382 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
384 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
385 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
386 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
387 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
389 /* Determine if an instruction matches an opcode. */
390 #define OPCODE_MATCHES(OPCODE, OP) \
391 (((OPCODE) & MASK_##OP) == MATCH_##OP)
393 static char *expr_end
;
395 /* The default target format to use. */
398 riscv_target_format (void)
400 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
403 /* Return the length of instruction INSN. */
405 static inline unsigned int
406 insn_length (const struct riscv_cl_insn
*insn
)
408 return riscv_insn_length (insn
->insn_opcode
);
411 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
414 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
417 insn
->insn_opcode
= mo
->match
;
423 /* Install INSN at the location specified by its "frag" and "where" fields. */
426 install_insn (const struct riscv_cl_insn
*insn
)
428 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
429 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
432 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
433 and install the opcode in the new location. */
436 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
440 if (insn
->fixp
!= NULL
)
442 insn
->fixp
->fx_frag
= frag
;
443 insn
->fixp
->fx_where
= where
;
448 /* Add INSN to the end of the output. */
451 add_fixed_insn (struct riscv_cl_insn
*insn
)
453 char *f
= frag_more (insn_length (insn
));
454 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
458 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
459 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
461 frag_grow (max_chars
);
462 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
463 frag_var (rs_machine_dependent
, max_chars
, var
,
464 subtype
, symbol
, offset
, NULL
);
467 /* Compute the length of a branch sequence, and adjust the stored length
468 accordingly. If FRAGP is NULL, the worst-case length is returned. */
471 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
473 int jump
, rvc
, length
= 8;
478 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
479 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
480 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
482 /* Assume jumps are in range; the linker will catch any that aren't. */
483 length
= jump
? 4 : 8;
485 if (fragp
->fr_symbol
!= NULL
486 && S_IS_DEFINED (fragp
->fr_symbol
)
487 && !S_IS_WEAK (fragp
->fr_symbol
)
488 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
490 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
491 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
492 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
494 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
496 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
498 else if (!jump
&& rvc
)
503 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
508 /* Information about an opcode name, mnemonics and its value. */
515 /* List for all supported opcode name. */
516 static const struct opcode_name_t opcode_name_list
[] =
561 /* Hash table for lookup opcode name. */
562 static struct hash_control
*opcode_names_hash
= NULL
;
564 /* Initialization for hash table of opcode name. */
566 init_opcode_names_hash (void)
569 const struct opcode_name_t
*opcode
;
571 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
573 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
576 as_fatal (_("internal error: can't hash `%s': %s"),
577 opcode
->name
, retval
);
581 /* Find `s` is a valid opcode name or not,
582 return the opcode name info if found. */
583 static const struct opcode_name_t
*
584 opcode_name_lookup (char **s
)
588 struct opcode_name_t
*o
;
590 /* Find end of name. */
592 if (is_name_beginner (*e
))
594 while (is_part_of_name (*e
))
597 /* Terminate name. */
601 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
603 /* Advance to next token if one was recognized. */
622 static struct hash_control
*reg_names_hash
= NULL
;
623 static struct hash_control
*csr_extra_hash
= NULL
;
625 #define ENCODE_REG_HASH(cls, n) \
626 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
627 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
628 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
631 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
633 void *hash
= ENCODE_REG_HASH (class, n
);
634 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
637 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
641 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
645 for (i
= 0; i
< n
; i
++)
646 hash_reg_name (class, names
[i
], i
);
649 /* Init hash table csr_extra_hash to handle CSR. */
651 riscv_init_csr_hash (const char *name
,
653 enum riscv_csr_class
class,
654 enum riscv_priv_spec_class define_version
,
655 enum riscv_priv_spec_class abort_version
)
657 struct riscv_csr_extra
*entry
, *pre_entry
;
658 const char *hash_error
= NULL
;
659 bfd_boolean need_enrty
= TRUE
;
662 entry
= (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, name
);
663 while (need_enrty
&& entry
!= NULL
)
665 if (entry
->csr_class
== class
666 && entry
->address
== address
667 && entry
->define_version
== define_version
668 && entry
->abort_version
== abort_version
)
674 /* Duplicate setting for the CSR, just return and do nothing. */
678 entry
= XNEW (struct riscv_csr_extra
);
679 entry
->csr_class
= class;
680 entry
->address
= address
;
681 entry
->define_version
= define_version
;
682 entry
->abort_version
= abort_version
;
685 /* If the CSR hasn't been inserted in the hash table, then insert it.
686 Otherwise, attach the extra information to the entry which is already
687 in the hash table. */
688 if (pre_entry
== NULL
)
690 hash_error
= hash_insert (csr_extra_hash
, name
, (void *) entry
);
691 if (hash_error
!= NULL
)
693 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
695 /* Probably a memory allocation problem? Give up now. */
696 as_fatal (_("Broken assembler. No assembly attempted."));
700 pre_entry
->next
= entry
;
703 /* Return the suitable CSR address after checking the ISA dependency and
704 priv spec versions. */
707 riscv_csr_address (const char *csr_name
,
708 struct riscv_csr_extra
*entry
)
710 struct riscv_csr_extra
*saved_entry
= entry
;
711 enum riscv_csr_class csr_class
= entry
->csr_class
;
712 bfd_boolean need_check_version
= TRUE
;
713 bfd_boolean result
= TRUE
;
718 result
= riscv_subset_supports ("i");
721 result
= (xlen
== 32 && riscv_subset_supports ("i"));
724 result
= riscv_subset_supports ("f");
725 need_check_version
= FALSE
;
727 case CSR_CLASS_DEBUG
:
728 need_check_version
= FALSE
;
731 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
734 /* Don't report the ISA conflict when -mcsr-check isn't set. */
735 if (riscv_opts
.csr_check
&& !result
)
736 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name
);
738 while (entry
!= NULL
)
740 if (!need_check_version
741 || (default_priv_spec
>= entry
->define_version
742 && default_priv_spec
< entry
->abort_version
))
744 /* Find the suitable CSR according to the specific version. */
745 return entry
->address
;
750 /* We can not find the suitable CSR address according to the privilege
751 version. Therefore, we use the last defined value. Report the warning
752 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
753 otherwise, you may get the unexpected CSR address. */
754 if (riscv_opts
.csr_check
)
756 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
758 if (priv_name
!= NULL
)
759 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
760 csr_name
, priv_name
);
763 return saved_entry
->address
;
766 /* Once the CSR is defined, including the old privilege spec, then we call
767 riscv_csr_class_check and riscv_csr_version_check to do the further checking
768 and get the corresponding address. Return -1 if the CSR is never been
769 defined. Otherwise, return the address. */
772 reg_csr_lookup_internal (const char *s
)
774 struct riscv_csr_extra
*r
=
775 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
780 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
781 the CSR was defined, but isn't allowed for the current ISA setting or
782 the privilege spec. If the CSR is never been defined, then assembler
783 will regard it as a "Unknown CSR" and report error. If user use number
784 to set the CSR, but over the range (> 0xfff), then assembler will report
785 "Improper CSR" error for it. */
786 return riscv_csr_address (s
, r
);
790 reg_lookup_internal (const char *s
, enum reg_class
class)
794 if (class == RCLASS_CSR
)
795 return reg_csr_lookup_internal (s
);
797 r
= hash_find (reg_names_hash
, s
);
798 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
801 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
804 return DECODE_REG_NUM (r
);
808 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
814 /* Find end of name. */
816 if (is_name_beginner (*e
))
818 while (is_part_of_name (*e
))
821 /* Terminate name. */
825 /* Look for the register. Advance to next token if one was recognized. */
826 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
836 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
838 const char *p
= strchr (*s
, ',');
839 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
844 for (i
= 0; i
< size
; i
++)
845 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
855 /* For consistency checking, verify that all bits are specified either
856 by the match/mask part of the instruction definition, or by the
859 `length` could be 0, 4 or 8, 0 for auto detection. */
861 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
863 const char *p
= opc
->args
;
865 insn_t used_bits
= opc
->mask
;
867 insn_t required_bits
;
870 insn_width
= 8 * riscv_insn_length (opc
->match
);
872 insn_width
= 8 * length
;
874 required_bits
= ~0ULL >> (64 - insn_width
);
876 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
878 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
879 opc
->name
, opc
->args
);
883 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
890 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
891 case 'c': break; /* RS1, constrained to equal sp */
892 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
893 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
894 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
895 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
896 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
897 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
898 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
899 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
900 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
901 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
902 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
903 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
904 case 'w': break; /* RS1S, constrained to equal RD */
905 case 'x': break; /* RS2S, constrained to equal RD */
906 case 'z': break; /* RS2S, contrained to be x0 */
907 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
908 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
909 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
910 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
911 case 'U': break; /* RS1, constrained to equal RD */
912 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
913 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
914 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
915 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
916 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
917 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
918 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
919 case 'F': /* funct */
922 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
923 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
924 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
925 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
927 as_bad (_("internal: bad RISC-V opcode"
928 " (unknown operand type `CF%c'): %s %s"),
929 c
, opc
->name
, opc
->args
);
934 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
935 c
, opc
->name
, opc
->args
);
942 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
943 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
945 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
946 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
947 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
949 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
950 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
951 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
952 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
953 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
954 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
955 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
956 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
957 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
958 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
959 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
961 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
962 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
963 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
964 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
965 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
971 case 'F': /* funct */
974 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
975 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
976 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
978 as_bad (_("internal: bad RISC-V opcode"
979 " (unknown operand type `F%c'): %s %s"),
980 c
, opc
->name
, opc
->args
);
984 case 'O': /* opcode */
987 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
988 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
990 as_bad (_("internal: bad RISC-V opcode"
991 " (unknown operand type `F%c'): %s %s"),
992 c
, opc
->name
, opc
->args
);
997 as_bad (_("internal: bad RISC-V opcode "
998 "(unknown operand type `%c'): %s %s"),
999 c
, opc
->name
, opc
->args
);
1003 if (used_bits
!= required_bits
)
1005 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1006 ~(unsigned long)(used_bits
& required_bits
),
1007 opc
->name
, opc
->args
);
1013 struct percent_op_match
1016 bfd_reloc_code_real_type reloc
;
1019 /* Common hash table initialization function for
1020 instruction and .insn directive. */
1021 static struct hash_control
*
1022 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1023 bfd_boolean insn_directive_p
)
1027 struct hash_control
*hash
= hash_new ();
1028 while (opcodes
[i
].name
)
1030 const char *name
= opcodes
[i
].name
;
1031 const char *hash_error
=
1032 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
1034 if (hash_error
!= NULL
)
1036 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1037 opcodes
[i
].name
, hash_error
);
1038 /* Probably a memory allocation problem? Give up now. */
1039 as_fatal (_("Broken assembler. No assembly attempted."));
1044 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1046 if (insn_directive_p
)
1047 length
= ((name
[0] == 'c') ? 2 : 4);
1049 length
= 0; /* Let assembler determine the length. */
1050 if (!validate_riscv_insn (&opcodes
[i
], length
))
1051 as_fatal (_("Broken assembler. No assembly attempted."));
1054 gas_assert (!insn_directive_p
);
1057 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1063 /* This function is called once, at assembler startup time. It should set up
1064 all the tables, etc. that the MD part of the assembler will need. */
1069 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1071 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1072 as_warn (_("Could not set architecture and machine"));
1074 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1075 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1077 reg_names_hash
= hash_new ();
1078 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1079 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1080 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1081 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1082 /* Add "fp" as an alias for "s0". */
1083 hash_reg_name (RCLASS_GPR
, "fp", 8);
1085 /* Create and insert CSR hash tables. */
1086 csr_extra_hash
= hash_new ();
1087 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1088 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1089 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1090 DECLARE_CSR(name, num, class, define_version, abort_version);
1091 #include "opcode/riscv-opc.h"
1094 opcode_names_hash
= hash_new ();
1095 init_opcode_names_hash ();
1097 /* Set the default alignment for the text section. */
1098 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1102 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1109 case BFD_RELOC_RISCV_HI20
:
1110 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1112 case BFD_RELOC_RISCV_LO12_S
:
1113 return ENCODE_STYPE_IMM (value
);
1115 case BFD_RELOC_RISCV_LO12_I
:
1116 return ENCODE_ITYPE_IMM (value
);
1123 /* Output an instruction. IP is the instruction information.
1124 ADDRESS_EXPR is an operand of the instruction to be used with
1128 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1129 bfd_reloc_code_real_type reloc_type
)
1131 dwarf2_emit_insn (0);
1133 if (reloc_type
!= BFD_RELOC_UNUSED
)
1135 reloc_howto_type
*howto
;
1137 gas_assert (address_expr
);
1138 if (reloc_type
== BFD_RELOC_12_PCREL
1139 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1141 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1142 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1143 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1144 add_relaxed_insn (ip
, worst_case
, best_case
,
1145 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1146 address_expr
->X_add_symbol
,
1147 address_expr
->X_add_number
);
1152 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1154 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1156 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1157 bfd_get_reloc_size (howto
),
1158 address_expr
, FALSE
, reloc_type
);
1160 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1164 add_fixed_insn (ip
);
1167 /* We need to start a new frag after any instruction that can be
1168 optimized away or compressed by the linker during relaxation, to prevent
1169 the assembler from computing static offsets across such an instruction.
1170 This is necessary to get correct EH info. */
1171 if (reloc_type
== BFD_RELOC_RISCV_CALL
1172 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
1173 || reloc_type
== BFD_RELOC_RISCV_HI20
1174 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1175 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1176 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1178 frag_wane (frag_now
);
1183 /* Build an instruction created by a macro expansion. This is passed
1184 a pointer to the count of instructions created so far, an
1185 expression, the name of the instruction to build, an operand format
1186 string, and corresponding arguments. */
1189 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1191 const struct riscv_opcode
*mo
;
1192 struct riscv_cl_insn insn
;
1193 bfd_reloc_code_real_type r
;
1196 va_start (args
, fmt
);
1198 r
= BFD_RELOC_UNUSED
;
1199 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
1202 /* Find a non-RVC variant of the instruction. append_insn will compress
1204 while (riscv_insn_length (mo
->match
) < 4)
1206 gas_assert (strcmp (name
, mo
->name
) == 0);
1208 create_insn (&insn
, mo
);
1214 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1218 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1222 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1226 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1232 gas_assert (ep
!= NULL
);
1233 r
= va_arg (args
, int);
1241 as_fatal (_("internal error: invalid macro"));
1246 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1248 append_insn (&insn
, ep
, r
);
1251 /* Build an instruction created by a macro expansion. Like md_assemble but
1252 accept a printf-style format string and arguments. */
1255 md_assemblef (const char *format
, ...)
1261 va_start (ap
, format
);
1263 r
= vasprintf (&buf
, format
, ap
);
1266 as_fatal (_("internal error: vasprintf failed"));
1274 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1277 normalize_constant_expr (expressionS
*ex
)
1281 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1282 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1283 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1287 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1288 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1291 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1292 bfd_boolean maybe_csr
)
1294 if (ex
->X_op
== O_big
)
1295 as_bad (_("unsupported large constant"));
1296 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1297 as_bad (_("unknown CSR `%s'"),
1298 S_GET_NAME (ex
->X_add_symbol
));
1299 else if (ex
->X_op
!= O_constant
)
1300 as_bad (_("Instruction %s requires absolute expression"),
1302 normalize_constant_expr (ex
);
1306 make_internal_label (void)
1308 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1309 (valueT
) frag_now_fix (), frag_now
);
1312 /* Load an entry from the GOT. */
1314 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1315 const char *lo_insn
, const char *lo_pattern
,
1316 bfd_reloc_code_real_type hi_reloc
,
1317 bfd_reloc_code_real_type lo_reloc
)
1320 ep2
.X_op
= O_symbol
;
1321 ep2
.X_add_symbol
= make_internal_label ();
1322 ep2
.X_add_number
= 0;
1324 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1325 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1329 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1330 bfd_reloc_code_real_type hi_reloc
,
1331 bfd_reloc_code_real_type lo_reloc
)
1333 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1337 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1338 bfd_reloc_code_real_type hi_reloc
,
1339 bfd_reloc_code_real_type lo_reloc
)
1341 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1344 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1346 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1347 bfd_reloc_code_real_type reloc
)
1349 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1350 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1353 /* Load an integer constant into a register. */
1356 load_const (int reg
, expressionS
*ep
)
1358 int shift
= RISCV_IMM_BITS
;
1359 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1360 expressionS upper
= *ep
, lower
= *ep
;
1361 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1362 upper
.X_add_number
-= lower
.X_add_number
;
1364 if (ep
->X_op
!= O_constant
)
1366 as_bad (_("unsupported large constant"));
1370 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1372 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1373 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1376 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1377 load_const (reg
, &upper
);
1379 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1380 if (lower
.X_add_number
!= 0)
1381 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1382 lower
.X_add_number
);
1386 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1389 if (upper
.X_add_number
!= 0)
1391 /* Discard low part and zero-extend upper immediate. */
1392 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1394 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1398 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1399 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1400 lower
.X_add_number
);
1404 /* Expand RISC-V assembly macros into one or more instructions. */
1406 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1407 bfd_reloc_code_real_type
*imm_reloc
)
1409 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1410 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1411 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1412 int mask
= ip
->insn_mo
->mask
;
1417 load_const (rd
, imm_expr
);
1422 /* Load the address of a symbol into a register. */
1423 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1424 as_bad (_("offset too large"));
1426 if (imm_expr
->X_op
== O_constant
)
1427 load_const (rd
, imm_expr
);
1428 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1429 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1430 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1431 else /* Local PIC symbol, or any non-PIC symbol */
1432 pcrel_load (rd
, rd
, imm_expr
, "addi",
1433 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1437 pcrel_load (rd
, rd
, imm_expr
, "addi",
1438 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1442 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1443 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1447 pcrel_load (rd
, rd
, imm_expr
, "lb",
1448 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1452 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1453 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1457 pcrel_load (rd
, rd
, imm_expr
, "lh",
1458 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1462 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1463 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1467 pcrel_load (rd
, rd
, imm_expr
, "lw",
1468 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1472 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1473 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1477 pcrel_load (rd
, rd
, imm_expr
, "ld",
1478 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1482 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1483 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1487 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1488 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1492 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1493 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1497 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1498 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1502 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1503 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1507 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1508 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1512 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1513 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1517 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1518 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1522 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1526 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1531 static const struct percent_op_match percent_op_utype
[] =
1533 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1534 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1535 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1536 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1537 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1538 {"%hi", BFD_RELOC_RISCV_HI20
},
1542 static const struct percent_op_match percent_op_itype
[] =
1544 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1545 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1546 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1550 static const struct percent_op_match percent_op_stype
[] =
1552 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1553 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1554 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1558 static const struct percent_op_match percent_op_rtype
[] =
1560 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1564 static const struct percent_op_match percent_op_null
[] =
1569 /* Return true if *STR points to a relocation operator. When returning true,
1570 move *STR over the operator and store its relocation code in *RELOC.
1571 Leave both *STR and *RELOC alone when returning false. */
1574 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1575 const struct percent_op_match
*percent_op
)
1577 for ( ; percent_op
->str
; percent_op
++)
1578 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1580 int len
= strlen (percent_op
->str
);
1582 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1585 *str
+= strlen (percent_op
->str
);
1586 *reloc
= percent_op
->reloc
;
1588 /* Check whether the output BFD supports this relocation.
1589 If not, issue an error and fall back on something safe. */
1590 if (*reloc
!= BFD_RELOC_UNUSED
1591 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1593 as_bad ("relocation %s isn't supported by the current ABI",
1595 *reloc
= BFD_RELOC_UNUSED
;
1603 my_getExpression (expressionS
*ep
, char *str
)
1607 save_in
= input_line_pointer
;
1608 input_line_pointer
= str
;
1610 expr_end
= input_line_pointer
;
1611 input_line_pointer
= save_in
;
1614 /* Parse string STR as a 16-bit relocatable operand. Store the
1615 expression in *EP and the relocation, if any, in RELOC.
1616 Return the number of relocation operators used (0 or 1).
1618 On exit, EXPR_END points to the first character after the expression. */
1621 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1622 char *str
, const struct percent_op_match
*percent_op
)
1625 unsigned crux_depth
, str_depth
, regno
;
1628 /* First, check for integer registers. No callers can accept a reg, but
1629 we need to avoid accidentally creating a useless undefined symbol below,
1630 if this is an instruction pattern that can't match. A glibc build fails
1631 if this is removed. */
1632 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1634 ep
->X_op
= O_register
;
1635 ep
->X_add_number
= regno
;
1640 /* Search for the start of the main expression.
1641 End the loop with CRUX pointing to the start
1642 of the main expression and with CRUX_DEPTH containing the number
1643 of open brackets at that point. */
1650 crux_depth
= str_depth
;
1652 /* Skip over whitespace and brackets, keeping count of the number
1654 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1660 && parse_relocation (&str
, reloc
, percent_op
));
1662 my_getExpression (ep
, crux
);
1665 /* Match every open bracket. */
1666 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1671 as_bad ("unclosed '('");
1678 /* Parse opcode name, could be an mnemonics or number. */
1680 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1681 char *str
, const struct percent_op_match
*percent_op
)
1683 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1687 ep
->X_op
= O_constant
;
1688 ep
->X_add_number
= o
->val
;
1692 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1695 /* Detect and handle implicitly zero load-store offsets. For example,
1696 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1697 an implicit offset was detected. */
1700 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1702 /* Check whether there is only a single bracketed expression left.
1703 If so, it must be the base register and the constant must be zero. */
1704 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1706 ep
->X_op
= O_constant
;
1707 ep
->X_add_number
= 0;
1714 /* All RISC-V CSR instructions belong to one of these classes. */
1724 /* Return which CSR instruction is checking. */
1726 static enum csr_insn_type
1727 riscv_csr_insn_type (insn_t insn
)
1729 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1730 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1732 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1733 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1735 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1736 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1739 return INSN_NOT_CSR
;
1742 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1743 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1744 CSR address is 0x3. */
1747 riscv_csr_read_only_check (insn_t insn
)
1749 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1750 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1751 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1752 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1755 && (((csr_insn
== INSN_CSRRS
1756 || csr_insn
== INSN_CSRRC
)
1758 || csr_insn
== INSN_CSRRW
))
1764 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1766 uret is actually a N-ext instruction. So it is better to regard it as
1767 an user instruction rather than the priv instruction.
1769 hret is used to return from traps in H-mode. H-mode is removed since
1770 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1771 Therefore, hret should be controlled by the hypervisor spec rather than
1772 priv spec in the future.
1774 dret is defined in the debug spec, so it should be checked in the future,
1778 riscv_is_priv_insn (insn_t insn
)
1780 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1781 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1782 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1783 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1784 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1785 check it here to keep the compatible. Maybe we should issue warning
1786 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1787 We already have a similar check for CSR, but not yet for instructions.
1788 It would be good if we could check the spec versions both for CSR and
1789 instructions, but not here. */
1790 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1793 /* This routine assembles an instruction into its binary format. As a
1794 side effect, it sets the global variable imm_reloc to the type of
1795 relocation to do if one of the operands is an address expression. */
1798 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1799 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1804 struct riscv_opcode
*insn
;
1809 const struct percent_op_match
*p
;
1810 const char *error
= "unrecognized opcode";
1811 /* Indicate we are assembling instruction with CSR. */
1812 bfd_boolean insn_with_csr
= FALSE
;
1814 /* Parse the name of the instruction. Terminate the string if whitespace
1815 is found so that hash_find only sees the name part of the string. */
1816 for (s
= str
; *s
!= '\0'; ++s
)
1824 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1827 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1829 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1832 if (!riscv_multi_subset_supports (insn
->insn_class
))
1835 create_insn (ip
, insn
);
1838 imm_expr
->X_op
= O_absent
;
1839 *imm_reloc
= BFD_RELOC_UNUSED
;
1840 p
= percent_op_itype
;
1842 for (args
= insn
->args
;; ++args
)
1844 s
+= strspn (s
, " \t");
1847 case '\0': /* End of args. */
1848 if (insn
->pinfo
!= INSN_MACRO
)
1850 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1853 /* For .insn, insn->match and insn->mask are 0. */
1854 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1860 if (riscv_is_priv_insn (ip
->insn_opcode
))
1861 explicit_priv_attr
= TRUE
;
1863 /* Check if we write a read-only CSR by the CSR
1866 && riscv_opts
.csr_check
1867 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1869 /* Restore the character in advance, since we want to
1870 report the detailed warning message here. */
1872 *(argsStart
- 1) = save_c
;
1873 as_warn (_("Read-only CSR is written `%s'"), str
);
1874 insn_with_csr
= FALSE
;
1879 /* Successful assembly. */
1881 insn_with_csr
= FALSE
;
1887 case 's': /* RS1 x8-x15 */
1888 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1889 || !(regno
>= 8 && regno
<= 15))
1891 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1893 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1894 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1895 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1898 case 't': /* RS2 x8-x15 */
1899 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1900 || !(regno
>= 8 && regno
<= 15))
1902 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1904 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1905 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1906 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1909 case 'U': /* RS1, constrained to equal RD. */
1910 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1911 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1915 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1917 INSERT_OPERAND (CRS2
, *ip
, regno
);
1919 case 'c': /* RS1, constrained to equal sp. */
1920 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1924 case 'z': /* RS2, contrained to equal x0. */
1925 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1930 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1931 || imm_expr
->X_op
!= O_constant
1932 || imm_expr
->X_add_number
<= 0
1933 || imm_expr
->X_add_number
>= 64)
1935 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1938 imm_expr
->X_op
= O_absent
;
1941 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1942 || imm_expr
->X_op
!= O_constant
1943 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1944 || imm_expr
->X_add_number
<= 0
1945 || imm_expr
->X_add_number
>= 32)
1947 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1950 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1951 || imm_expr
->X_op
!= O_constant
1952 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1953 || imm_expr
->X_add_number
< 0
1954 || imm_expr
->X_add_number
>= 256)
1956 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1959 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1960 || imm_expr
->X_op
!= O_constant
1961 || imm_expr
->X_add_number
== 0
1962 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1964 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1967 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1968 || imm_expr
->X_op
!= O_constant
1969 || imm_expr
->X_add_number
== 0
1970 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1972 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1975 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1977 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1978 || imm_expr
->X_op
!= O_constant
1979 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1981 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1984 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1986 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1987 || imm_expr
->X_op
!= O_constant
1988 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1990 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1993 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1995 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1996 || imm_expr
->X_op
!= O_constant
1997 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
2000 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2003 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2005 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2006 || imm_expr
->X_op
!= O_constant
2007 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
2010 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2013 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2014 || imm_expr
->X_op
!= O_constant
2015 /* C.addiw, c.li, and c.andi allow zero immediate.
2016 C.addi allows zero immediate as hint. Otherwise this
2018 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
2020 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2023 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2024 || imm_expr
->X_op
!= O_constant
2025 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
2026 || imm_expr
->X_add_number
== 0)
2029 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2032 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2033 || imm_expr
->X_op
!= O_constant
2034 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
2035 || imm_expr
->X_add_number
== 0)
2038 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2041 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2043 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2044 || imm_expr
->X_op
!= O_constant
2045 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
2048 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2051 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2053 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2054 || imm_expr
->X_op
!= O_constant
2055 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
2058 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2061 p
= percent_op_utype
;
2062 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2065 if (imm_expr
->X_op
!= O_constant
2066 || imm_expr
->X_add_number
<= 0
2067 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2068 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2069 && (imm_expr
->X_add_number
<
2070 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2072 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2075 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2076 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2077 || ((int32_t)imm_expr
->X_add_number
2078 != imm_expr
->X_add_number
))
2080 imm_expr
->X_add_number
=
2081 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2087 case 'S': /* Floating-point RS1 x8-x15. */
2088 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2089 || !(regno
>= 8 && regno
<= 15))
2091 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2093 case 'D': /* Floating-point RS2 x8-x15. */
2094 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2095 || !(regno
>= 8 && regno
<= 15))
2097 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2099 case 'T': /* Floating-point RS2. */
2100 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2102 INSERT_OPERAND (CRS2
, *ip
, regno
);
2108 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2109 || imm_expr
->X_op
!= O_constant
2110 || imm_expr
->X_add_number
< 0
2111 || imm_expr
->X_add_number
>= 64)
2113 as_bad (_("bad value for funct6 field, "
2114 "value must be 0...64"));
2118 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2119 imm_expr
->X_op
= O_absent
;
2123 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2124 || imm_expr
->X_op
!= O_constant
2125 || imm_expr
->X_add_number
< 0
2126 || imm_expr
->X_add_number
>= 16)
2128 as_bad (_("bad value for funct4 field, "
2129 "value must be 0...15"));
2133 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2134 imm_expr
->X_op
= O_absent
;
2138 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2139 || imm_expr
->X_op
!= O_constant
2140 || imm_expr
->X_add_number
< 0
2141 || imm_expr
->X_add_number
>= 8)
2143 as_bad (_("bad value for funct3 field, "
2144 "value must be 0...7"));
2147 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2148 imm_expr
->X_op
= O_absent
;
2152 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2153 || imm_expr
->X_op
!= O_constant
2154 || imm_expr
->X_add_number
< 0
2155 || imm_expr
->X_add_number
>= 4)
2157 as_bad (_("bad value for funct2 field, "
2158 "value must be 0...3"));
2161 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2162 imm_expr
->X_op
= O_absent
;
2166 as_bad (_("bad compressed FUNCT field"
2167 " specifier 'CF%c'\n"),
2173 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2192 case '<': /* Shift amount, 0 - 31. */
2193 my_getExpression (imm_expr
, s
);
2194 check_absolute_expr (ip
, imm_expr
, FALSE
);
2195 if ((unsigned long) imm_expr
->X_add_number
> 31)
2196 as_bad (_("Improper shift amount (%lu)"),
2197 (unsigned long) imm_expr
->X_add_number
);
2198 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2199 imm_expr
->X_op
= O_absent
;
2203 case '>': /* Shift amount, 0 - (XLEN-1). */
2204 my_getExpression (imm_expr
, s
);
2205 check_absolute_expr (ip
, imm_expr
, FALSE
);
2206 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2207 as_bad (_("Improper shift amount (%lu)"),
2208 (unsigned long) imm_expr
->X_add_number
);
2209 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2210 imm_expr
->X_op
= O_absent
;
2214 case 'Z': /* CSRRxI immediate. */
2215 my_getExpression (imm_expr
, s
);
2216 check_absolute_expr (ip
, imm_expr
, FALSE
);
2217 if ((unsigned long) imm_expr
->X_add_number
> 31)
2218 as_bad (_("Improper CSRxI immediate (%lu)"),
2219 (unsigned long) imm_expr
->X_add_number
);
2220 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2221 imm_expr
->X_op
= O_absent
;
2225 case 'E': /* Control register. */
2226 insn_with_csr
= TRUE
;
2227 explicit_priv_attr
= TRUE
;
2228 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2229 INSERT_OPERAND (CSR
, *ip
, regno
);
2232 my_getExpression (imm_expr
, s
);
2233 check_absolute_expr (ip
, imm_expr
, TRUE
);
2234 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2235 as_bad (_("Improper CSR address (%lu)"),
2236 (unsigned long) imm_expr
->X_add_number
);
2237 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2238 imm_expr
->X_op
= O_absent
;
2243 case 'm': /* Rounding mode. */
2244 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2246 INSERT_OPERAND (RM
, *ip
, regno
);
2252 case 'Q': /* Fence predecessor/successor. */
2253 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2257 INSERT_OPERAND (PRED
, *ip
, regno
);
2259 INSERT_OPERAND (SUCC
, *ip
, regno
);
2264 case 'd': /* Destination register. */
2265 case 's': /* Source register. */
2266 case 't': /* Target register. */
2267 case 'r': /* rs3. */
2268 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2274 /* Now that we have assembled one operand, we use the args
2275 string to figure out where it goes in the instruction. */
2279 INSERT_OPERAND (RS1
, *ip
, regno
);
2282 INSERT_OPERAND (RD
, *ip
, regno
);
2285 INSERT_OPERAND (RS2
, *ip
, regno
);
2288 INSERT_OPERAND (RS3
, *ip
, regno
);
2295 case 'D': /* Floating point rd. */
2296 case 'S': /* Floating point rs1. */
2297 case 'T': /* Floating point rs2. */
2298 case 'U': /* Floating point rs1 and rs2. */
2299 case 'R': /* Floating point rs3. */
2300 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2308 INSERT_OPERAND (RD
, *ip
, regno
);
2311 INSERT_OPERAND (RS1
, *ip
, regno
);
2314 INSERT_OPERAND (RS1
, *ip
, regno
);
2317 INSERT_OPERAND (RS2
, *ip
, regno
);
2320 INSERT_OPERAND (RS3
, *ip
, regno
);
2329 my_getExpression (imm_expr
, s
);
2330 if (imm_expr
->X_op
!= O_big
2331 && imm_expr
->X_op
!= O_constant
)
2333 normalize_constant_expr (imm_expr
);
2338 my_getExpression (imm_expr
, s
);
2339 normalize_constant_expr (imm_expr
);
2340 /* The 'A' format specifier must be a symbol. */
2341 if (imm_expr
->X_op
!= O_symbol
)
2343 *imm_reloc
= BFD_RELOC_32
;
2348 my_getExpression (imm_expr
, s
);
2349 normalize_constant_expr (imm_expr
);
2350 /* The 'B' format specifier must be a symbol or a constant. */
2351 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2353 if (imm_expr
->X_op
== O_symbol
)
2354 *imm_reloc
= BFD_RELOC_32
;
2358 case 'j': /* Sign-extended immediate. */
2359 p
= percent_op_itype
;
2360 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2362 case 'q': /* Store displacement. */
2363 p
= percent_op_stype
;
2364 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2366 case 'o': /* Load displacement. */
2367 p
= percent_op_itype
;
2368 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2370 case '1': /* 4-operand add, must be %tprel_add. */
2371 p
= percent_op_rtype
;
2373 case '0': /* AMO "displacement," which must be zero. */
2374 p
= percent_op_null
;
2376 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2379 /* If this value won't fit into a 16 bit offset, then go
2380 find a macro that will generate the 32 bit offset
2382 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2384 normalize_constant_expr (imm_expr
);
2385 if (imm_expr
->X_op
!= O_constant
2386 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2388 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2389 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2396 case 'p': /* PC-relative offset. */
2398 *imm_reloc
= BFD_RELOC_12_PCREL
;
2399 my_getExpression (imm_expr
, s
);
2403 case 'u': /* Upper 20 bits. */
2404 p
= percent_op_utype
;
2405 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2407 if (imm_expr
->X_op
!= O_constant
)
2410 if (imm_expr
->X_add_number
< 0
2411 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2412 as_bad (_("lui expression not in range 0..1048575"));
2414 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2415 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2420 case 'a': /* 20-bit PC-relative offset. */
2422 my_getExpression (imm_expr
, s
);
2424 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2428 my_getExpression (imm_expr
, s
);
2430 if (strcmp (s
, "@plt") == 0)
2432 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2436 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2442 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2443 || imm_expr
->X_op
!= O_constant
2444 || imm_expr
->X_add_number
< 0
2445 || imm_expr
->X_add_number
>= 128
2446 || (imm_expr
->X_add_number
& 0x3) != 3)
2448 as_bad (_("bad value for opcode field, "
2449 "value must be 0...127 and "
2450 "lower 2 bits must be 0x3"));
2454 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2455 imm_expr
->X_op
= O_absent
;
2459 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2460 || imm_expr
->X_op
!= O_constant
2461 || imm_expr
->X_add_number
< 0
2462 || imm_expr
->X_add_number
>= 3)
2464 as_bad (_("bad value for opcode field, "
2465 "value must be 0...2"));
2469 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2470 imm_expr
->X_op
= O_absent
;
2474 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2482 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2483 || imm_expr
->X_op
!= O_constant
2484 || imm_expr
->X_add_number
< 0
2485 || imm_expr
->X_add_number
>= 128)
2487 as_bad (_("bad value for funct7 field, "
2488 "value must be 0...127"));
2492 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2493 imm_expr
->X_op
= O_absent
;
2497 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2498 || imm_expr
->X_op
!= O_constant
2499 || imm_expr
->X_add_number
< 0
2500 || imm_expr
->X_add_number
>= 8)
2502 as_bad (_("bad value for funct3 field, "
2503 "value must be 0...7"));
2507 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2508 imm_expr
->X_op
= O_absent
;
2512 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2513 || imm_expr
->X_op
!= O_constant
2514 || imm_expr
->X_add_number
< 0
2515 || imm_expr
->X_add_number
>= 4)
2517 as_bad (_("bad value for funct2 field, "
2518 "value must be 0...3"));
2522 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2523 imm_expr
->X_op
= O_absent
;
2528 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2533 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2534 || imm_expr
->X_op
!= O_constant
2535 || imm_expr
->X_add_number
!= 0)
2538 imm_expr
->X_op
= O_absent
;
2542 as_fatal (_("internal error: bad argument type %c"), *args
);
2547 error
= _("illegal operands");
2548 insn_with_csr
= FALSE
;
2552 /* Restore the character we might have clobbered above. */
2554 *(argsStart
- 1) = save_c
;
2560 md_assemble (char *str
)
2562 struct riscv_cl_insn insn
;
2563 expressionS imm_expr
;
2564 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2566 /* The arch and priv attributes should be set before assembling. */
2567 if (!start_assemble
)
2569 start_assemble
= TRUE
;
2571 /* Set the default_priv_spec according to the priv attributes. */
2572 if (!riscv_set_default_priv_spec (NULL
))
2576 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2580 as_bad ("%s `%s'", error
, str
);
2584 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2585 macro (&insn
, &imm_expr
, &imm_reloc
);
2587 append_insn (&insn
, &imm_expr
, imm_reloc
);
2591 md_atof (int type
, char *litP
, int *sizeP
)
2593 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2597 md_number_to_chars (char *buf
, valueT val
, int n
)
2599 number_to_chars_littleendian (buf
, val
, n
);
2602 const char *md_shortopts
= "O::g::G:";
2606 OPTION_MARCH
= OPTION_MD_BASE
,
2613 OPTION_NO_ARCH_ATTR
,
2615 OPTION_NO_CSR_CHECK
,
2621 struct option md_longopts
[] =
2623 {"march", required_argument
, NULL
, OPTION_MARCH
},
2624 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2625 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2626 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2627 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2628 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2629 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2630 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2631 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2632 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2633 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2634 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2635 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2637 {NULL
, no_argument
, NULL
, 0}
2639 size_t md_longopts_size
= sizeof (md_longopts
);
2642 FLOAT_ABI_DEFAULT
= -1,
2648 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2651 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2653 abi_xlen
= new_xlen
;
2654 float_abi
= new_float_abi
;
2659 md_parse_option (int c
, const char *arg
)
2664 /* riscv_after_parse_args will call riscv_set_arch to parse
2665 the architecture. */
2666 default_arch_with_ext
= arg
;
2670 riscv_opts
.pic
= FALSE
;
2674 riscv_opts
.pic
= TRUE
;
2678 if (strcmp (arg
, "ilp32") == 0)
2679 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2680 else if (strcmp (arg
, "ilp32e") == 0)
2681 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2682 else if (strcmp (arg
, "ilp32f") == 0)
2683 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2684 else if (strcmp (arg
, "ilp32d") == 0)
2685 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2686 else if (strcmp (arg
, "ilp32q") == 0)
2687 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2688 else if (strcmp (arg
, "lp64") == 0)
2689 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2690 else if (strcmp (arg
, "lp64f") == 0)
2691 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2692 else if (strcmp (arg
, "lp64d") == 0)
2693 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2694 else if (strcmp (arg
, "lp64q") == 0)
2695 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2701 riscv_opts
.relax
= TRUE
;
2704 case OPTION_NO_RELAX
:
2705 riscv_opts
.relax
= FALSE
;
2708 case OPTION_ARCH_ATTR
:
2709 riscv_opts
.arch_attr
= TRUE
;
2712 case OPTION_NO_ARCH_ATTR
:
2713 riscv_opts
.arch_attr
= FALSE
;
2716 case OPTION_CSR_CHECK
:
2717 riscv_opts
.csr_check
= TRUE
;
2720 case OPTION_NO_CSR_CHECK
:
2721 riscv_opts
.csr_check
= FALSE
;
2724 case OPTION_MISA_SPEC
:
2725 return riscv_set_default_isa_spec (arg
);
2727 case OPTION_MPRIV_SPEC
:
2728 return riscv_set_default_priv_spec (arg
);
2738 riscv_after_parse_args (void)
2740 /* The --with-arch is optional for now, so we have to set the xlen
2741 according to the default_arch, which is set by the --targte, first.
2742 Then, we use the xlen to set the default_arch_with_ext if the
2743 -march and --with-arch are not set. */
2746 if (strcmp (default_arch
, "riscv32") == 0)
2748 else if (strcmp (default_arch
, "riscv64") == 0)
2751 as_bad ("unknown default architecture `%s'", default_arch
);
2753 if (default_arch_with_ext
== NULL
)
2754 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2756 /* Initialize the hash table for extensions with default version. */
2757 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2759 /* If the -misa-spec isn't set, then we set the default ISA spec according
2760 to DEFAULT_RISCV_ISA_SPEC. */
2761 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2762 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2764 /* Set the architecture according to -march or or --with-arch. */
2765 riscv_set_arch (default_arch_with_ext
);
2767 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2768 riscv_set_rvc (FALSE
);
2769 if (riscv_subset_supports ("c"))
2770 riscv_set_rvc (TRUE
);
2772 /* Enable RVE if specified by the -march option. */
2773 riscv_set_rve (FALSE
);
2774 if (riscv_subset_supports ("e"))
2775 riscv_set_rve (TRUE
);
2777 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2778 according to DEFAULT_PRIV_SPEC. */
2779 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2780 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2782 /* Infer ABI from ISA if not specified on command line. */
2785 else if (abi_xlen
> xlen
)
2786 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2787 else if (abi_xlen
< xlen
)
2788 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2790 if (float_abi
== FLOAT_ABI_DEFAULT
)
2792 riscv_subset_t
*subset
;
2794 /* Assume soft-float unless D extension is present. */
2795 float_abi
= FLOAT_ABI_SOFT
;
2797 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2799 if (strcasecmp (subset
->name
, "D") == 0)
2800 float_abi
= FLOAT_ABI_DOUBLE
;
2801 if (strcasecmp (subset
->name
, "Q") == 0)
2802 float_abi
= FLOAT_ABI_QUAD
;
2807 elf_flags
|= EF_RISCV_RVE
;
2809 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2810 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2812 /* If the CIE to be produced has not been overridden on the command line,
2813 then produce version 3 by default. This allows us to use the full
2814 range of registers in a .cfi_return_column directive. */
2815 if (flag_dwarf_cie_version
== -1)
2816 flag_dwarf_cie_version
= 3;
2820 md_pcrel_from (fixS
*fixP
)
2822 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2825 /* Apply a fixup to the object file. */
2828 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2830 unsigned int subtype
;
2831 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2832 bfd_boolean relaxable
= FALSE
;
2836 /* Remember value for tc_gen_reloc. */
2837 fixP
->fx_addnumber
= *valP
;
2839 switch (fixP
->fx_r_type
)
2841 case BFD_RELOC_RISCV_HI20
:
2842 case BFD_RELOC_RISCV_LO12_I
:
2843 case BFD_RELOC_RISCV_LO12_S
:
2844 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2845 | bfd_getl32 (buf
), buf
);
2846 if (fixP
->fx_addsy
== NULL
)
2847 fixP
->fx_done
= TRUE
;
2851 case BFD_RELOC_RISCV_GOT_HI20
:
2852 case BFD_RELOC_RISCV_ADD8
:
2853 case BFD_RELOC_RISCV_ADD16
:
2854 case BFD_RELOC_RISCV_ADD32
:
2855 case BFD_RELOC_RISCV_ADD64
:
2856 case BFD_RELOC_RISCV_SUB6
:
2857 case BFD_RELOC_RISCV_SUB8
:
2858 case BFD_RELOC_RISCV_SUB16
:
2859 case BFD_RELOC_RISCV_SUB32
:
2860 case BFD_RELOC_RISCV_SUB64
:
2861 case BFD_RELOC_RISCV_RELAX
:
2864 case BFD_RELOC_RISCV_TPREL_HI20
:
2865 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2866 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2867 case BFD_RELOC_RISCV_TPREL_ADD
:
2871 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2872 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2873 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2874 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2875 if (fixP
->fx_addsy
!= NULL
)
2876 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2879 _("TLS relocation against a constant"));
2883 /* Use pc-relative relocation for FDE initial location.
2884 The symbol address in .eh_frame may be adjusted in
2885 _bfd_elf_discard_section_eh_frame, and the content of
2886 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2887 Therefore, we cannot insert a relocation whose addend symbol is
2888 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2889 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2890 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2891 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2892 && S_GET_VALUE (fixP
->fx_subsy
)
2893 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2895 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2896 fixP
->fx_subsy
= NULL
;
2903 case BFD_RELOC_RISCV_CFA
:
2904 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2906 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2907 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2908 fixP
->fx_next
->fx_subsy
= NULL
;
2909 fixP
->fx_next
->fx_offset
= 0;
2910 fixP
->fx_subsy
= NULL
;
2912 switch (fixP
->fx_r_type
)
2915 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2916 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2920 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2921 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2925 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2926 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2930 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2931 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2934 case BFD_RELOC_RISCV_CFA
:
2935 /* Load the byte to get the subtype. */
2936 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2937 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2940 case DW_CFA_advance_loc1
:
2941 fixP
->fx_where
= loc
+ 1;
2942 fixP
->fx_next
->fx_where
= loc
+ 1;
2943 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2944 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2947 case DW_CFA_advance_loc2
:
2949 fixP
->fx_next
->fx_size
= 2;
2950 fixP
->fx_where
= loc
+ 1;
2951 fixP
->fx_next
->fx_where
= loc
+ 1;
2952 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2953 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2956 case DW_CFA_advance_loc4
:
2958 fixP
->fx_next
->fx_size
= 4;
2959 fixP
->fx_where
= loc
;
2960 fixP
->fx_next
->fx_where
= loc
;
2961 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2962 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2966 if (subtype
< 0x80 && (subtype
& 0x40))
2968 /* DW_CFA_advance_loc */
2969 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2970 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2971 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2972 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2975 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2981 /* This case is unreachable. */
2988 /* If we are deleting this reloc entry, we must fill in the
2989 value now. This can happen if we have a .word which is not
2990 resolved when it appears but is later defined. */
2991 if (fixP
->fx_addsy
== NULL
)
2993 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2994 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2999 case BFD_RELOC_RISCV_JMP
:
3002 /* Fill in a tentative value to improve objdump readability. */
3003 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3004 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3005 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3009 case BFD_RELOC_12_PCREL
:
3012 /* Fill in a tentative value to improve objdump readability. */
3013 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3014 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3015 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3019 case BFD_RELOC_RISCV_RVC_BRANCH
:
3022 /* Fill in a tentative value to improve objdump readability. */
3023 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3024 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3025 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3029 case BFD_RELOC_RISCV_RVC_JUMP
:
3032 /* Fill in a tentative value to improve objdump readability. */
3033 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3034 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3035 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3039 case BFD_RELOC_RISCV_CALL
:
3040 case BFD_RELOC_RISCV_CALL_PLT
:
3044 case BFD_RELOC_RISCV_PCREL_HI20
:
3045 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3046 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3047 relaxable
= riscv_opts
.relax
;
3050 case BFD_RELOC_RISCV_ALIGN
:
3054 /* We ignore generic BFD relocations we don't know about. */
3055 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3056 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3059 if (fixP
->fx_subsy
!= NULL
)
3060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3061 _("unsupported symbol subtraction"));
3063 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3064 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3066 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3067 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3068 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3072 /* Because the value of .cfi_remember_state may changed after relaxation,
3073 we insert a fix to relocate it again in link-time. */
3076 riscv_pre_output_hook (void)
3078 const frchainS
*frch
;
3081 /* Save the current segment info. */
3083 subsegT subseg
= now_subseg
;
3085 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3086 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3090 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3092 if (frag
->fr_type
== rs_cfa
)
3095 expressionS
*symval
;
3097 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3098 exp
.X_op
= O_subtract
;
3099 exp
.X_add_symbol
= symval
->X_add_symbol
;
3100 exp
.X_add_number
= 0;
3101 exp
.X_op_symbol
= symval
->X_op_symbol
;
3103 /* We must set the segment before creating a frag after all
3104 frag chains have been chained together. */
3105 subseg_set (s
, frch
->frch_subseg
);
3107 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3108 BFD_RELOC_RISCV_CFA
);
3113 /* Restore the original segment info. */
3114 subseg_set (seg
, subseg
);
3118 /* This structure is used to hold a stack of .option values. */
3120 struct riscv_option_stack
3122 struct riscv_option_stack
*next
;
3123 struct riscv_set_options options
;
3126 static struct riscv_option_stack
*riscv_opts_stack
;
3128 /* Handle the .option pseudo-op. */
3131 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3133 char *name
= input_line_pointer
, ch
;
3135 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3136 ++input_line_pointer
;
3137 ch
= *input_line_pointer
;
3138 *input_line_pointer
= '\0';
3140 if (strcmp (name
, "rvc") == 0)
3141 riscv_set_rvc (TRUE
);
3142 else if (strcmp (name
, "norvc") == 0)
3143 riscv_set_rvc (FALSE
);
3144 else if (strcmp (name
, "pic") == 0)
3145 riscv_opts
.pic
= TRUE
;
3146 else if (strcmp (name
, "nopic") == 0)
3147 riscv_opts
.pic
= FALSE
;
3148 else if (strcmp (name
, "relax") == 0)
3149 riscv_opts
.relax
= TRUE
;
3150 else if (strcmp (name
, "norelax") == 0)
3151 riscv_opts
.relax
= FALSE
;
3152 else if (strcmp (name
, "csr-check") == 0)
3153 riscv_opts
.csr_check
= TRUE
;
3154 else if (strcmp (name
, "no-csr-check") == 0)
3155 riscv_opts
.csr_check
= FALSE
;
3156 else if (strcmp (name
, "push") == 0)
3158 struct riscv_option_stack
*s
;
3160 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3161 s
->next
= riscv_opts_stack
;
3162 s
->options
= riscv_opts
;
3163 riscv_opts_stack
= s
;
3165 else if (strcmp (name
, "pop") == 0)
3167 struct riscv_option_stack
*s
;
3169 s
= riscv_opts_stack
;
3171 as_bad (_(".option pop with no .option push"));
3174 riscv_opts
= s
->options
;
3175 riscv_opts_stack
= s
->next
;
3181 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3183 *input_line_pointer
= ch
;
3184 demand_empty_rest_of_line ();
3187 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3188 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3189 use in DWARF debug information. */
3192 s_dtprel (int bytes
)
3199 if (ex
.X_op
!= O_symbol
)
3201 as_bad (_("Unsupported use of %s"), (bytes
== 8
3204 ignore_rest_of_line ();
3207 p
= frag_more (bytes
);
3208 md_number_to_chars (p
, 0, bytes
);
3209 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3211 ? BFD_RELOC_RISCV_TLS_DTPREL64
3212 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3214 demand_empty_rest_of_line ();
3217 /* Handle the .bss pseudo-op. */
3220 s_bss (int ignore ATTRIBUTE_UNUSED
)
3222 subseg_set (bss_section
, 0);
3223 demand_empty_rest_of_line ();
3227 riscv_make_nops (char *buf
, bfd_vma bytes
)
3231 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3232 means we are not within a valid instruction sequence. It is thus safe
3233 to use a zero byte, even though that is not a valid instruction. */
3237 /* Use at most one 2-byte NOP. */
3238 if ((bytes
- i
) % 4 == 2)
3240 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3244 /* Fill the remainder with 4-byte NOPs. */
3245 for ( ; i
< bytes
; i
+= 4)
3246 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3249 /* Called from md_do_align. Used to create an alignment frag in a
3250 code section by emitting a worst-case NOP sequence that the linker
3251 will later relax to the correct number of NOPs. We can't compute
3252 the correct alignment now because of other linker relaxations. */
3255 riscv_frag_align_code (int n
)
3257 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3258 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3259 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3263 /* If we are moving to a smaller alignment than the instruction size, then no
3264 alignment is required. */
3265 if (bytes
<= insn_alignment
)
3268 /* When not relaxing, riscv_handle_align handles code alignment. */
3269 if (!riscv_opts
.relax
)
3272 nops
= frag_more (worst_case_bytes
);
3274 ex
.X_op
= O_constant
;
3275 ex
.X_add_number
= worst_case_bytes
;
3277 riscv_make_nops (nops
, worst_case_bytes
);
3279 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3280 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3285 /* Implement HANDLE_ALIGN. */
3288 riscv_handle_align (fragS
*fragP
)
3290 switch (fragP
->fr_type
)
3293 /* When relaxing, riscv_frag_align_code handles code alignment. */
3294 if (!riscv_opts
.relax
)
3296 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3297 - fragP
->fr_address
- fragP
->fr_fix
);
3298 /* We have 4 byte uncompressed nops. */
3299 bfd_signed_vma size
= 4;
3300 bfd_signed_vma excess
= bytes
% size
;
3301 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3306 /* Insert zeros or compressed nops to get 4 byte alignment. */
3309 riscv_make_nops (p
, excess
);
3310 fragP
->fr_fix
+= excess
;
3314 /* Insert variable number of 4 byte uncompressed nops. */
3315 riscv_make_nops (p
, size
);
3316 fragP
->fr_var
= size
;
3326 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3328 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3331 /* Translate internal representation of relocation info to BFD target
3335 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3337 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3339 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3340 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3341 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3342 reloc
->addend
= fixp
->fx_addnumber
;
3344 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3345 if (reloc
->howto
== NULL
)
3347 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3348 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3350 /* We don't have R_RISCV_8/16, but for this special case,
3351 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3355 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3356 _("cannot represent %s relocation in object file"),
3357 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3365 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3367 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3369 offsetT old_var
= fragp
->fr_var
;
3370 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3371 return fragp
->fr_var
- old_var
;
3377 /* Expand far branches to multi-instruction sequences. */
3380 md_convert_frag_branch (fragS
*fragp
)
3388 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3390 exp
.X_op
= O_symbol
;
3391 exp
.X_add_symbol
= fragp
->fr_symbol
;
3392 exp
.X_add_number
= fragp
->fr_offset
;
3394 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3396 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3398 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3402 /* Expand the RVC branch into a RISC-V one. */
3403 insn
= bfd_getl16 (buf
);
3404 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3405 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3407 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3408 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3409 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3410 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3411 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3412 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3415 bfd_putl32 (insn
, buf
);
3419 /* Invert the branch condition. Branch over the jump. */
3420 insn
= bfd_getl16 (buf
);
3421 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3422 insn
|= ENCODE_RVC_B_IMM (6);
3423 bfd_putl16 (insn
, buf
);
3428 /* Just keep the RVC branch. */
3429 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3430 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3431 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3432 2, &exp
, FALSE
, reloc
);
3441 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3444 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3446 /* Invert the branch condition. Branch over the jump. */
3447 insn
= bfd_getl32 (buf
);
3448 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3449 insn
|= ENCODE_SBTYPE_IMM (8);
3450 md_number_to_chars ((char *) buf
, insn
, 4);
3454 /* Jump to the target. */
3455 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3456 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3457 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3462 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3463 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3464 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3465 4, &exp
, FALSE
, reloc
);
3474 fixp
->fx_file
= fragp
->fr_file
;
3475 fixp
->fx_line
= fragp
->fr_line
;
3477 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3478 + fragp
->fr_fix
+ fragp
->fr_var
);
3480 fragp
->fr_fix
+= fragp
->fr_var
;
3483 /* Relax a machine dependent frag. This returns the amount by which
3484 the current size of the frag should change. */
3487 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3490 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3491 md_convert_frag_branch (fragp
);
3495 md_show_usage (FILE *stream
)
3497 fprintf (stream
, _("\
3499 -fpic generate position-independent code\n\
3500 -fno-pic don't generate position-independent code (default)\n\
3501 -march=ISA set the RISC-V architecture\n\
3502 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3503 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3504 -mabi=ABI set the RISC-V ABI\n\
3505 -mrelax enable relax (default)\n\
3506 -mno-relax disable relax\n\
3507 -march-attr generate RISC-V arch attribute\n\
3508 -mno-arch-attr don't generate RISC-V arch attribute\n\
3512 /* Standard calling conventions leave the CFA at SP on entry. */
3514 riscv_cfi_frame_initial_instructions (void)
3516 cfi_add_CFA_def_cfa_register (X_SP
);
3520 tc_riscv_regname_to_dw2regnum (char *regname
)
3524 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3527 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3530 /* CSRs are numbered 4096 -> 8191. */
3531 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3534 as_bad (_("unknown register `%s'"), regname
);
3539 riscv_elf_final_processing (void)
3541 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3544 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3545 since these directives break relaxation when used with symbol deltas. */
3548 s_riscv_leb128 (int sign
)
3551 char *save_in
= input_line_pointer
;
3554 if (exp
.X_op
!= O_constant
)
3555 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3556 demand_empty_rest_of_line ();
3558 input_line_pointer
= save_in
;
3559 return s_leb128 (sign
);
3562 /* Parse the .insn directive. */
3565 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3567 char *str
= input_line_pointer
;
3568 struct riscv_cl_insn insn
;
3569 expressionS imm_expr
;
3570 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3573 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3574 ++input_line_pointer
;
3576 save_c
= *input_line_pointer
;
3577 *input_line_pointer
= '\0';
3579 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3580 &imm_reloc
, insn_type_hash
);
3584 as_bad ("%s `%s'", error
, str
);
3588 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3589 append_insn (&insn
, &imm_expr
, imm_reloc
);
3592 *input_line_pointer
= save_c
;
3593 demand_empty_rest_of_line ();
3596 /* Update arch and priv attributes. If we don't set the corresponding ELF
3597 attributes, then try to output the default ones. */
3600 riscv_write_out_attrs (void)
3602 const char *arch_str
, *priv_str
, *p
;
3603 /* versions[0] is major, versions[1] is minor,
3604 and versions[3] is revision. */
3605 unsigned versions
[3] = {0}, number
= 0;
3608 /* Re-write arch attribute to normalize the arch string. */
3609 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3610 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3611 xfree ((void *)arch_str
);
3613 /* For the file without any instruction, we don't set the default_priv_spec
3614 according to the priv attributes since the md_assemble isn't called.
3615 Call riscv_set_default_priv_spec here for the above case, although
3616 it seems strange. */
3618 && !riscv_set_default_priv_spec (NULL
))
3621 /* If we already have set elf priv attributes, then no need to do anything,
3622 assembler will generate them according to what you set. Otherwise, don't
3623 generate or update them when no CSR and priv instructions are used.
3624 Generate the priv attributes according to default_priv_spec, which can be
3625 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3626 priv attribute sets. */
3627 if (!explicit_priv_attr
)
3630 /* Re-write priv attributes by default_priv_spec. */
3631 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3633 for (i
= 0; *p
; ++p
)
3635 if (*p
== '.' && i
< 3)
3637 versions
[i
++] = number
;
3640 else if (ISDIGIT (*p
))
3641 number
= (number
* 10) + (*p
- '0');
3644 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3648 versions
[i
] = number
;
3650 /* Set the priv attributes. */
3651 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3652 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3653 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3656 /* Add the default contents for the .riscv.attributes section. If any
3657 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3658 to update the arch and priv attributes. */
3661 riscv_set_public_attributes (void)
3663 if (riscv_opts
.arch_attr
|| explicit_attr
)
3664 riscv_write_out_attrs ();
3667 /* Called after all assembly has been done. */
3672 riscv_set_public_attributes ();
3675 /* Given a symbolic attribute NAME, return the proper integer value.
3676 Returns -1 if the attribute is not known. */
3679 riscv_convert_symbolic_attribute (const char *name
)
3688 /* When you modify this table you should
3689 also modify the list in doc/c-riscv.texi. */
3690 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3694 T(priv_spec_revision
),
3695 T(unaligned_access
),
3705 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3706 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3707 return attribute_table
[i
].tag
;
3712 /* Parse a .attribute directive. */
3715 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3717 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3719 obj_attribute
*attr
;
3721 explicit_attr
= TRUE
;
3724 case Tag_RISCV_arch
:
3726 attr
= elf_known_obj_attributes_proc (stdoutput
);
3727 if (!start_assemble
)
3728 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3730 as_fatal (_(".attribute arch must set before any instructions"));
3732 if (old_xlen
!= xlen
)
3734 /* We must re-init bfd again if xlen is changed. */
3735 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3736 bfd_find_target (riscv_target_format (), stdoutput
);
3738 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3739 as_warn (_("Could not set architecture and machine"));
3743 case Tag_RISCV_priv_spec
:
3744 case Tag_RISCV_priv_spec_minor
:
3745 case Tag_RISCV_priv_spec_revision
:
3747 as_fatal (_(".attribute priv spec must set before any instructions"));
3755 /* Pseudo-op table. */
3757 static const pseudo_typeS riscv_pseudo_table
[] =
3759 /* RISC-V-specific pseudo-ops. */
3760 {"option", s_riscv_option
, 0},
3764 {"dtprelword", s_dtprel
, 4},
3765 {"dtpreldword", s_dtprel
, 8},
3767 {"uleb128", s_riscv_leb128
, 0},
3768 {"sleb128", s_riscv_leb128
, 1},
3769 {"insn", s_riscv_insn
, 0},
3770 {"attribute", s_riscv_attribute
, 0},
3776 riscv_pop_insert (void)
3778 extern void pop_insert (const pseudo_typeS
*);
3780 pop_insert (riscv_pseudo_table
);