1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
96 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
98 static unsigned elf_flags
= 0;
100 /* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
104 riscv_set_default_isa_spec (const char *s
)
106 enum riscv_isa_spec_class
class;
107 if (!riscv_get_isa_spec_class (s
, &class))
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s
);
114 default_isa_spec
= class;
118 /* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
124 riscv_set_default_priv_spec (const char *s
)
126 enum riscv_priv_spec_class
class;
127 unsigned major
, minor
, revision
;
130 /* Find the corresponding priv spec class. */
131 if (riscv_get_priv_spec_class (s
, &class))
133 default_priv_spec
= class;
139 as_bad (_("Unknown default privilege spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s
);
144 /* Try to set the default_priv_spec according to the priv attributes. */
145 attr
= elf_known_obj_attributes_proc (stdoutput
);
146 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
147 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
148 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
150 if (riscv_get_priv_spec_class_from_numbers (major
,
155 /* The priv attributes setting 0.0.0 is meaningless. We should have set
156 the default_priv_spec by md_parse_option and riscv_after_parse_args,
157 so just skip the following setting. */
158 if (class == PRIV_SPEC_CLASS_NONE
)
161 default_priv_spec
= class;
165 /* Still can not find the priv spec class. */
166 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
167 "privilege attributes"), major
, minor
, revision
);
171 /* This is the set of options which the .option pseudo-op may modify. */
173 struct riscv_set_options
175 int pic
; /* Generate position-independent code. */
176 int rvc
; /* Generate RVC code. */
177 int rve
; /* Generate RVE code. */
178 int relax
; /* Emit relocs the linker is allowed to relax. */
179 int arch_attr
; /* Emit arch attribute. */
180 int csr_check
; /* Enable the CSR checking. */
183 static struct riscv_set_options riscv_opts
=
189 DEFAULT_RISCV_ATTR
, /* arch_attr */
194 riscv_set_rvc (bfd_boolean rvc_value
)
197 elf_flags
|= EF_RISCV_RVC
;
199 riscv_opts
.rvc
= rvc_value
;
203 riscv_set_rve (bfd_boolean rve_value
)
205 riscv_opts
.rve
= rve_value
;
208 static riscv_subset_list_t riscv_subsets
;
211 riscv_subset_supports (const char *feature
)
213 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
216 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
220 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
224 case INSN_CLASS_I
: return riscv_subset_supports ("i");
225 case INSN_CLASS_C
: return riscv_subset_supports ("c");
226 case INSN_CLASS_A
: return riscv_subset_supports ("a");
227 case INSN_CLASS_M
: return riscv_subset_supports ("m");
228 case INSN_CLASS_F
: return riscv_subset_supports ("f");
229 case INSN_CLASS_D
: return riscv_subset_supports ("d");
230 case INSN_CLASS_D_AND_C
:
231 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
233 case INSN_CLASS_F_AND_C
:
234 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
236 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
239 as_fatal ("Unreachable");
244 /* Handle of the extension with version hash table. */
245 static struct hash_control
*ext_version_hash
= NULL
;
247 static struct hash_control
*
248 init_ext_version_hash (const struct riscv_ext_version
*table
)
251 struct hash_control
*hash
= hash_new ();
253 while (table
[i
].name
)
255 const char *name
= table
[i
].name
;
256 const char *hash_error
=
257 hash_insert (hash
, name
, (void *) &table
[i
]);
259 if (hash_error
!= NULL
)
261 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
262 table
[i
].name
, hash_error
);
263 /* Probably a memory allocation problem? Give up now. */
264 as_fatal (_("Broken assembler. No assembly attempted."));
270 && strcmp (table
[i
].name
, name
) == 0)
278 riscv_get_default_ext_version (const char *name
,
279 unsigned int *major_version
,
280 unsigned int *minor_version
)
282 struct riscv_ext_version
*ext
;
287 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
290 ext
= (struct riscv_ext_version
*) hash_find (ext_version_hash
, name
);
293 && strcmp (ext
->name
, name
) == 0)
295 if (ext
->isa_spec_class
== default_isa_spec
)
297 *major_version
= ext
->major_version
;
298 *minor_version
= ext
->minor_version
;
305 /* Set which ISA and extensions are available. */
308 riscv_set_arch (const char *s
)
310 riscv_parse_subset_t rps
;
311 rps
.subset_list
= &riscv_subsets
;
312 rps
.error_handler
= as_fatal
;
314 rps
.get_default_version
= riscv_get_default_ext_version
;
319 riscv_release_subset_list (&riscv_subsets
);
320 riscv_parse_subset (&rps
, s
);
323 /* Handle of the OPCODE hash table. */
324 static struct hash_control
*op_hash
= NULL
;
326 /* Handle of the type of .insn hash table. */
327 static struct hash_control
*insn_type_hash
= NULL
;
329 /* This array holds the chars that always start a comment. If the
330 pre-processor is disabled, these aren't very useful */
331 const char comment_chars
[] = "#";
333 /* This array holds the chars that only start a comment at the beginning of
334 a line. If the line seems to have the form '# 123 filename'
335 .line and .file directives will appear in the pre-processed output */
336 /* Note that input_file.c hand checks for '#' at the beginning of the
337 first line of the input file. This is because the compiler outputs
338 #NO_APP at the beginning of its output. */
339 /* Also note that C style comments are always supported. */
340 const char line_comment_chars
[] = "#";
342 /* This array holds machine specific line separator characters. */
343 const char line_separator_chars
[] = ";";
345 /* Chars that can be used to separate mant from exp in floating point nums */
346 const char EXP_CHARS
[] = "eE";
348 /* Chars that mean this number is a floating point constant */
351 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
353 /* Indicate we are already assemble any instructions or not. */
354 static bfd_boolean start_assemble
= FALSE
;
356 /* Indicate ELF attributes are explictly set. */
357 static bfd_boolean explicit_attr
= FALSE
;
359 /* Indicate CSR or priv instructions are explictly used. */
360 static bfd_boolean explicit_priv_attr
= FALSE
;
362 /* Macros for encoding relaxation state for RVC branches and far jumps. */
363 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
366 | ((uncond) ? 1 : 0) \
369 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
370 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
371 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
372 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
374 /* Is the given value a sign-extended 32-bit value? */
375 #define IS_SEXT_32BIT_NUM(x) \
376 (((x) &~ (offsetT) 0x7fffffff) == 0 \
377 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
379 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
380 #define IS_ZEXT_32BIT_NUM(x) \
381 (((x) &~ (offsetT) 0xffffffff) == 0 \
382 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
384 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
385 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
386 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
387 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
389 /* Determine if an instruction matches an opcode. */
390 #define OPCODE_MATCHES(OPCODE, OP) \
391 (((OPCODE) & MASK_##OP) == MATCH_##OP)
393 static char *expr_end
;
395 /* The default target format to use. */
398 riscv_target_format (void)
400 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
403 /* Return the length of instruction INSN. */
405 static inline unsigned int
406 insn_length (const struct riscv_cl_insn
*insn
)
408 return riscv_insn_length (insn
->insn_opcode
);
411 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
414 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
417 insn
->insn_opcode
= mo
->match
;
423 /* Install INSN at the location specified by its "frag" and "where" fields. */
426 install_insn (const struct riscv_cl_insn
*insn
)
428 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
429 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
432 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
433 and install the opcode in the new location. */
436 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
440 if (insn
->fixp
!= NULL
)
442 insn
->fixp
->fx_frag
= frag
;
443 insn
->fixp
->fx_where
= where
;
448 /* Add INSN to the end of the output. */
451 add_fixed_insn (struct riscv_cl_insn
*insn
)
453 char *f
= frag_more (insn_length (insn
));
454 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
458 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
459 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
461 frag_grow (max_chars
);
462 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
463 frag_var (rs_machine_dependent
, max_chars
, var
,
464 subtype
, symbol
, offset
, NULL
);
467 /* Compute the length of a branch sequence, and adjust the stored length
468 accordingly. If FRAGP is NULL, the worst-case length is returned. */
471 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
473 int jump
, rvc
, length
= 8;
478 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
479 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
480 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
482 /* Assume jumps are in range; the linker will catch any that aren't. */
483 length
= jump
? 4 : 8;
485 if (fragp
->fr_symbol
!= NULL
486 && S_IS_DEFINED (fragp
->fr_symbol
)
487 && !S_IS_WEAK (fragp
->fr_symbol
)
488 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
490 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
491 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
492 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
494 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
496 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
498 else if (!jump
&& rvc
)
503 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
508 /* Information about an opcode name, mnemonics and its value. */
515 /* List for all supported opcode name. */
516 static const struct opcode_name_t opcode_name_list
[] =
561 /* Hash table for lookup opcode name. */
562 static struct hash_control
*opcode_names_hash
= NULL
;
564 /* Initialization for hash table of opcode name. */
566 init_opcode_names_hash (void)
569 const struct opcode_name_t
*opcode
;
571 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
573 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
576 as_fatal (_("internal error: can't hash `%s': %s"),
577 opcode
->name
, retval
);
581 /* Find `s` is a valid opcode name or not,
582 return the opcode name info if found. */
583 static const struct opcode_name_t
*
584 opcode_name_lookup (char **s
)
588 struct opcode_name_t
*o
;
590 /* Find end of name. */
592 if (is_name_beginner (*e
))
594 while (is_part_of_name (*e
))
597 /* Terminate name. */
601 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
603 /* Advance to next token if one was recognized. */
622 static struct hash_control
*reg_names_hash
= NULL
;
623 static struct hash_control
*csr_extra_hash
= NULL
;
625 #define ENCODE_REG_HASH(cls, n) \
626 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
627 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
628 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
631 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
633 void *hash
= ENCODE_REG_HASH (class, n
);
634 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
637 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
641 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
645 for (i
= 0; i
< n
; i
++)
646 hash_reg_name (class, names
[i
], i
);
649 /* Init hash table csr_extra_hash to handle CSR. */
651 riscv_init_csr_hash (const char *name
,
653 enum riscv_csr_class
class,
654 enum riscv_priv_spec_class define_version
,
655 enum riscv_priv_spec_class abort_version
)
657 struct riscv_csr_extra
*entry
, *pre_entry
;
658 const char *hash_error
= NULL
;
659 bfd_boolean need_enrty
= TRUE
;
662 entry
= (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, name
);
663 while (need_enrty
&& entry
!= NULL
)
665 if (entry
->csr_class
== class
666 && entry
->address
== address
667 && entry
->define_version
== define_version
668 && entry
->abort_version
== abort_version
)
674 /* Duplicate setting for the CSR, just return and do nothing. */
678 entry
= XNEW (struct riscv_csr_extra
);
679 entry
->csr_class
= class;
680 entry
->address
= address
;
681 entry
->define_version
= define_version
;
682 entry
->abort_version
= abort_version
;
685 /* If the CSR hasn't been inserted in the hash table, then insert it.
686 Otherwise, attach the extra information to the entry which is already
687 in the hash table. */
688 if (pre_entry
== NULL
)
690 hash_error
= hash_insert (csr_extra_hash
, name
, (void *) entry
);
691 if (hash_error
!= NULL
)
693 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
695 /* Probably a memory allocation problem? Give up now. */
696 as_fatal (_("Broken assembler. No assembly attempted."));
700 pre_entry
->next
= entry
;
703 /* Check wether the CSR is valid according to the ISA. */
706 riscv_csr_class_check (const char *s
,
707 enum riscv_csr_class csr_class
)
709 bfd_boolean result
= TRUE
;
711 /* Don't check the ISA dependency when -mcsr-check isn't set. */
712 if (!riscv_opts
.csr_check
)
718 result
= riscv_subset_supports ("i");
721 result
= riscv_subset_supports ("f");
724 result
= (xlen
== 32 && riscv_subset_supports ("i"));
727 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
731 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
734 /* Check and find the CSR address according to the privilege spec version. */
737 riscv_csr_version_check (const char *csr_name
,
738 struct riscv_csr_extra
**entryP
)
740 struct riscv_csr_extra
*entry
= *entryP
;
742 while (entry
!= NULL
)
744 if (default_priv_spec
>= entry
->define_version
745 && default_priv_spec
< entry
->abort_version
)
747 /* Find the suitable CSR according to the specific version. */
754 /* We can not find the suitable CSR address according to the privilege
755 version. Therefore, we use the last defined value. Report the warning
756 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
757 otherwise, you may get the unexpected CSR address. */
758 if (riscv_opts
.csr_check
)
760 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
762 if (priv_name
!= NULL
)
763 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
764 csr_name
, priv_name
);
768 /* Once the CSR is defined, including the old privilege spec, then we call
769 riscv_csr_class_check and riscv_csr_version_check to do the further checking
770 and get the corresponding address. Return -1 if the CSR is never been
771 defined. Otherwise, return the address. */
774 reg_csr_lookup_internal (const char *s
)
776 struct riscv_csr_extra
*r
=
777 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
782 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
783 the CSR was defined, but isn't allowed for the current ISA setting or
784 the privilege spec. If the CSR is never been defined, then assembler
785 will regard it as a "Unknown CSR" and report error. If user use number
786 to set the CSR, but over the range (> 0xfff), then assembler will report
787 "Improper CSR" error for it. */
788 riscv_csr_class_check (s
, r
->csr_class
);
789 riscv_csr_version_check (s
, &r
);
795 reg_lookup_internal (const char *s
, enum reg_class
class)
799 if (class == RCLASS_CSR
)
800 return reg_csr_lookup_internal (s
);
802 r
= hash_find (reg_names_hash
, s
);
803 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
806 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
809 return DECODE_REG_NUM (r
);
813 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
819 /* Find end of name. */
821 if (is_name_beginner (*e
))
823 while (is_part_of_name (*e
))
826 /* Terminate name. */
830 /* Look for the register. Advance to next token if one was recognized. */
831 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
841 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
843 const char *p
= strchr (*s
, ',');
844 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
849 for (i
= 0; i
< size
; i
++)
850 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
860 /* For consistency checking, verify that all bits are specified either
861 by the match/mask part of the instruction definition, or by the
864 `length` could be 0, 4 or 8, 0 for auto detection. */
866 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
868 const char *p
= opc
->args
;
870 insn_t used_bits
= opc
->mask
;
872 insn_t required_bits
;
875 insn_width
= 8 * riscv_insn_length (opc
->match
);
877 insn_width
= 8 * length
;
879 required_bits
= ~0ULL >> (64 - insn_width
);
881 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
883 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
884 opc
->name
, opc
->args
);
888 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
895 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
896 case 'c': break; /* RS1, constrained to equal sp */
897 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
898 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
899 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
900 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
901 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
902 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
903 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
904 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
905 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
906 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
907 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
908 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
909 case 'w': break; /* RS1S, constrained to equal RD */
910 case 'x': break; /* RS2S, constrained to equal RD */
911 case 'z': break; /* RS2S, contrained to be x0 */
912 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
913 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
914 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
915 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
916 case 'U': break; /* RS1, constrained to equal RD */
917 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
918 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
919 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
920 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
921 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
922 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
923 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
924 case 'F': /* funct */
927 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
928 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
929 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
930 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
932 as_bad (_("internal: bad RISC-V opcode"
933 " (unknown operand type `CF%c'): %s %s"),
934 c
, opc
->name
, opc
->args
);
939 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
940 c
, opc
->name
, opc
->args
);
947 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
948 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
950 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
951 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
952 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
954 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
955 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
956 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
957 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
958 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
959 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
960 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
961 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
962 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
963 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
964 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
966 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
967 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
968 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
969 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
970 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
976 case 'F': /* funct */
979 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
980 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
981 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
983 as_bad (_("internal: bad RISC-V opcode"
984 " (unknown operand type `F%c'): %s %s"),
985 c
, opc
->name
, opc
->args
);
989 case 'O': /* opcode */
992 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
993 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
995 as_bad (_("internal: bad RISC-V opcode"
996 " (unknown operand type `F%c'): %s %s"),
997 c
, opc
->name
, opc
->args
);
1002 as_bad (_("internal: bad RISC-V opcode "
1003 "(unknown operand type `%c'): %s %s"),
1004 c
, opc
->name
, opc
->args
);
1008 if (used_bits
!= required_bits
)
1010 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1011 ~(unsigned long)(used_bits
& required_bits
),
1012 opc
->name
, opc
->args
);
1018 struct percent_op_match
1021 bfd_reloc_code_real_type reloc
;
1024 /* Common hash table initialization function for
1025 instruction and .insn directive. */
1026 static struct hash_control
*
1027 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1028 bfd_boolean insn_directive_p
)
1032 struct hash_control
*hash
= hash_new ();
1033 while (opcodes
[i
].name
)
1035 const char *name
= opcodes
[i
].name
;
1036 const char *hash_error
=
1037 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
1039 if (hash_error
!= NULL
)
1041 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1042 opcodes
[i
].name
, hash_error
);
1043 /* Probably a memory allocation problem? Give up now. */
1044 as_fatal (_("Broken assembler. No assembly attempted."));
1049 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1051 if (insn_directive_p
)
1052 length
= ((name
[0] == 'c') ? 2 : 4);
1054 length
= 0; /* Let assembler determine the length. */
1055 if (!validate_riscv_insn (&opcodes
[i
], length
))
1056 as_fatal (_("Broken assembler. No assembly attempted."));
1059 gas_assert (!insn_directive_p
);
1062 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1068 /* This function is called once, at assembler startup time. It should set up
1069 all the tables, etc. that the MD part of the assembler will need. */
1074 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1076 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1077 as_warn (_("Could not set architecture and machine"));
1079 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1080 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1082 reg_names_hash
= hash_new ();
1083 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1084 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1085 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1086 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1087 /* Add "fp" as an alias for "s0". */
1088 hash_reg_name (RCLASS_GPR
, "fp", 8);
1090 /* Create and insert CSR hash tables. */
1091 csr_extra_hash
= hash_new ();
1092 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1093 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1094 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1095 DECLARE_CSR(name, num, class, define_version, abort_version);
1096 #include "opcode/riscv-opc.h"
1099 opcode_names_hash
= hash_new ();
1100 init_opcode_names_hash ();
1102 /* Set the default alignment for the text section. */
1103 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1107 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1114 case BFD_RELOC_RISCV_HI20
:
1115 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1117 case BFD_RELOC_RISCV_LO12_S
:
1118 return ENCODE_STYPE_IMM (value
);
1120 case BFD_RELOC_RISCV_LO12_I
:
1121 return ENCODE_ITYPE_IMM (value
);
1128 /* Output an instruction. IP is the instruction information.
1129 ADDRESS_EXPR is an operand of the instruction to be used with
1133 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1134 bfd_reloc_code_real_type reloc_type
)
1136 dwarf2_emit_insn (0);
1138 if (reloc_type
!= BFD_RELOC_UNUSED
)
1140 reloc_howto_type
*howto
;
1142 gas_assert (address_expr
);
1143 if (reloc_type
== BFD_RELOC_12_PCREL
1144 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1146 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1147 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1148 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1149 add_relaxed_insn (ip
, worst_case
, best_case
,
1150 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1151 address_expr
->X_add_symbol
,
1152 address_expr
->X_add_number
);
1157 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1159 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1161 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1162 bfd_get_reloc_size (howto
),
1163 address_expr
, FALSE
, reloc_type
);
1165 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1169 add_fixed_insn (ip
);
1172 /* We need to start a new frag after any instruction that can be
1173 optimized away or compressed by the linker during relaxation, to prevent
1174 the assembler from computing static offsets across such an instruction.
1175 This is necessary to get correct EH info. */
1176 if (reloc_type
== BFD_RELOC_RISCV_CALL
1177 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
1178 || reloc_type
== BFD_RELOC_RISCV_HI20
1179 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1180 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1181 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1183 frag_wane (frag_now
);
1188 /* Build an instruction created by a macro expansion. This is passed
1189 a pointer to the count of instructions created so far, an
1190 expression, the name of the instruction to build, an operand format
1191 string, and corresponding arguments. */
1194 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1196 const struct riscv_opcode
*mo
;
1197 struct riscv_cl_insn insn
;
1198 bfd_reloc_code_real_type r
;
1201 va_start (args
, fmt
);
1203 r
= BFD_RELOC_UNUSED
;
1204 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
1207 /* Find a non-RVC variant of the instruction. append_insn will compress
1209 while (riscv_insn_length (mo
->match
) < 4)
1211 gas_assert (strcmp (name
, mo
->name
) == 0);
1213 create_insn (&insn
, mo
);
1219 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1223 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1227 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1231 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1237 gas_assert (ep
!= NULL
);
1238 r
= va_arg (args
, int);
1246 as_fatal (_("internal error: invalid macro"));
1251 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1253 append_insn (&insn
, ep
, r
);
1256 /* Build an instruction created by a macro expansion. Like md_assemble but
1257 accept a printf-style format string and arguments. */
1260 md_assemblef (const char *format
, ...)
1266 va_start (ap
, format
);
1268 r
= vasprintf (&buf
, format
, ap
);
1271 as_fatal (_("internal error: vasprintf failed"));
1279 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1282 normalize_constant_expr (expressionS
*ex
)
1286 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1287 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1288 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1292 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1293 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1296 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1297 bfd_boolean maybe_csr
)
1299 if (ex
->X_op
== O_big
)
1300 as_bad (_("unsupported large constant"));
1301 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1302 as_bad (_("unknown CSR `%s'"),
1303 S_GET_NAME (ex
->X_add_symbol
));
1304 else if (ex
->X_op
!= O_constant
)
1305 as_bad (_("Instruction %s requires absolute expression"),
1307 normalize_constant_expr (ex
);
1311 make_internal_label (void)
1313 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1314 (valueT
) frag_now_fix (), frag_now
);
1317 /* Load an entry from the GOT. */
1319 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1320 const char *lo_insn
, const char *lo_pattern
,
1321 bfd_reloc_code_real_type hi_reloc
,
1322 bfd_reloc_code_real_type lo_reloc
)
1325 ep2
.X_op
= O_symbol
;
1326 ep2
.X_add_symbol
= make_internal_label ();
1327 ep2
.X_add_number
= 0;
1329 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1330 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1334 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1335 bfd_reloc_code_real_type hi_reloc
,
1336 bfd_reloc_code_real_type lo_reloc
)
1338 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1342 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1343 bfd_reloc_code_real_type hi_reloc
,
1344 bfd_reloc_code_real_type lo_reloc
)
1346 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1349 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1351 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1352 bfd_reloc_code_real_type reloc
)
1354 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1355 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1358 /* Load an integer constant into a register. */
1361 load_const (int reg
, expressionS
*ep
)
1363 int shift
= RISCV_IMM_BITS
;
1364 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1365 expressionS upper
= *ep
, lower
= *ep
;
1366 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1367 upper
.X_add_number
-= lower
.X_add_number
;
1369 if (ep
->X_op
!= O_constant
)
1371 as_bad (_("unsupported large constant"));
1375 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1377 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1378 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1381 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1382 load_const (reg
, &upper
);
1384 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1385 if (lower
.X_add_number
!= 0)
1386 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1387 lower
.X_add_number
);
1391 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1394 if (upper
.X_add_number
!= 0)
1396 /* Discard low part and zero-extend upper immediate. */
1397 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1399 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1403 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1404 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1405 lower
.X_add_number
);
1409 /* Expand RISC-V assembly macros into one or more instructions. */
1411 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1412 bfd_reloc_code_real_type
*imm_reloc
)
1414 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1415 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1416 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1417 int mask
= ip
->insn_mo
->mask
;
1422 load_const (rd
, imm_expr
);
1427 /* Load the address of a symbol into a register. */
1428 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1429 as_bad (_("offset too large"));
1431 if (imm_expr
->X_op
== O_constant
)
1432 load_const (rd
, imm_expr
);
1433 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1434 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1435 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1436 else /* Local PIC symbol, or any non-PIC symbol */
1437 pcrel_load (rd
, rd
, imm_expr
, "addi",
1438 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1442 pcrel_load (rd
, rd
, imm_expr
, "addi",
1443 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1447 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1448 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1452 pcrel_load (rd
, rd
, imm_expr
, "lb",
1453 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1457 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1458 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1462 pcrel_load (rd
, rd
, imm_expr
, "lh",
1463 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1467 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1468 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1472 pcrel_load (rd
, rd
, imm_expr
, "lw",
1473 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1477 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1478 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1482 pcrel_load (rd
, rd
, imm_expr
, "ld",
1483 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1487 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1488 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1492 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1493 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1497 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1498 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1502 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1503 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1507 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1508 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1512 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1513 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1517 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1518 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1522 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1523 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1527 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1531 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1536 static const struct percent_op_match percent_op_utype
[] =
1538 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1539 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1540 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1541 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1542 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1543 {"%hi", BFD_RELOC_RISCV_HI20
},
1547 static const struct percent_op_match percent_op_itype
[] =
1549 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1550 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1551 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1555 static const struct percent_op_match percent_op_stype
[] =
1557 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1558 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1559 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1563 static const struct percent_op_match percent_op_rtype
[] =
1565 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1569 static const struct percent_op_match percent_op_null
[] =
1574 /* Return true if *STR points to a relocation operator. When returning true,
1575 move *STR over the operator and store its relocation code in *RELOC.
1576 Leave both *STR and *RELOC alone when returning false. */
1579 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1580 const struct percent_op_match
*percent_op
)
1582 for ( ; percent_op
->str
; percent_op
++)
1583 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1585 int len
= strlen (percent_op
->str
);
1587 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1590 *str
+= strlen (percent_op
->str
);
1591 *reloc
= percent_op
->reloc
;
1593 /* Check whether the output BFD supports this relocation.
1594 If not, issue an error and fall back on something safe. */
1595 if (*reloc
!= BFD_RELOC_UNUSED
1596 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1598 as_bad ("relocation %s isn't supported by the current ABI",
1600 *reloc
= BFD_RELOC_UNUSED
;
1608 my_getExpression (expressionS
*ep
, char *str
)
1612 save_in
= input_line_pointer
;
1613 input_line_pointer
= str
;
1615 expr_end
= input_line_pointer
;
1616 input_line_pointer
= save_in
;
1619 /* Parse string STR as a 16-bit relocatable operand. Store the
1620 expression in *EP and the relocation, if any, in RELOC.
1621 Return the number of relocation operators used (0 or 1).
1623 On exit, EXPR_END points to the first character after the expression. */
1626 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1627 char *str
, const struct percent_op_match
*percent_op
)
1630 unsigned crux_depth
, str_depth
, regno
;
1633 /* First, check for integer registers. No callers can accept a reg, but
1634 we need to avoid accidentally creating a useless undefined symbol below,
1635 if this is an instruction pattern that can't match. A glibc build fails
1636 if this is removed. */
1637 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1639 ep
->X_op
= O_register
;
1640 ep
->X_add_number
= regno
;
1645 /* Search for the start of the main expression.
1646 End the loop with CRUX pointing to the start
1647 of the main expression and with CRUX_DEPTH containing the number
1648 of open brackets at that point. */
1655 crux_depth
= str_depth
;
1657 /* Skip over whitespace and brackets, keeping count of the number
1659 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1665 && parse_relocation (&str
, reloc
, percent_op
));
1667 my_getExpression (ep
, crux
);
1670 /* Match every open bracket. */
1671 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1676 as_bad ("unclosed '('");
1683 /* Parse opcode name, could be an mnemonics or number. */
1685 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1686 char *str
, const struct percent_op_match
*percent_op
)
1688 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1692 ep
->X_op
= O_constant
;
1693 ep
->X_add_number
= o
->val
;
1697 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1700 /* Detect and handle implicitly zero load-store offsets. For example,
1701 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1702 an implicit offset was detected. */
1705 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1707 /* Check whether there is only a single bracketed expression left.
1708 If so, it must be the base register and the constant must be zero. */
1709 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1711 ep
->X_op
= O_constant
;
1712 ep
->X_add_number
= 0;
1719 /* All RISC-V CSR instructions belong to one of these classes. */
1729 /* Return which CSR instruction is checking. */
1731 static enum csr_insn_type
1732 riscv_csr_insn_type (insn_t insn
)
1734 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1735 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1737 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1738 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1740 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1741 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1744 return INSN_NOT_CSR
;
1747 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1748 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1749 CSR address is 0x3. */
1752 riscv_csr_read_only_check (insn_t insn
)
1754 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1755 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1756 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1757 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1760 && (((csr_insn
== INSN_CSRRS
1761 || csr_insn
== INSN_CSRRC
)
1763 || csr_insn
== INSN_CSRRW
))
1769 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1771 uret is actually a N-ext instruction. So it is better to regard it as
1772 an user instruction rather than the priv instruction.
1774 hret is used to return from traps in H-mode. H-mode is removed since
1775 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1776 Therefore, hret should be controlled by the hypervisor spec rather than
1777 priv spec in the future.
1779 dret is defined in the debug spec, so it should be checked in the future,
1783 riscv_is_priv_insn (insn_t insn
)
1785 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1786 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1787 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1788 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1789 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1790 check it here to keep the compatible. Maybe we should issue warning
1791 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1792 We already have a similar check for CSR, but not yet for instructions.
1793 It would be good if we could check the spec versions both for CSR and
1794 instructions, but not here. */
1795 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1798 /* This routine assembles an instruction into its binary format. As a
1799 side effect, it sets the global variable imm_reloc to the type of
1800 relocation to do if one of the operands is an address expression. */
1803 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1804 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1809 struct riscv_opcode
*insn
;
1814 const struct percent_op_match
*p
;
1815 const char *error
= "unrecognized opcode";
1816 /* Indicate we are assembling instruction with CSR. */
1817 bfd_boolean insn_with_csr
= FALSE
;
1819 /* Parse the name of the instruction. Terminate the string if whitespace
1820 is found so that hash_find only sees the name part of the string. */
1821 for (s
= str
; *s
!= '\0'; ++s
)
1829 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1832 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1834 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1837 if (!riscv_multi_subset_supports (insn
->insn_class
))
1840 create_insn (ip
, insn
);
1843 imm_expr
->X_op
= O_absent
;
1844 *imm_reloc
= BFD_RELOC_UNUSED
;
1845 p
= percent_op_itype
;
1847 for (args
= insn
->args
;; ++args
)
1849 s
+= strspn (s
, " \t");
1852 case '\0': /* End of args. */
1853 if (insn
->pinfo
!= INSN_MACRO
)
1855 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1858 /* For .insn, insn->match and insn->mask are 0. */
1859 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1865 if (riscv_is_priv_insn (ip
->insn_opcode
))
1866 explicit_priv_attr
= TRUE
;
1868 /* Check if we write a read-only CSR by the CSR
1871 && riscv_opts
.csr_check
1872 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1874 /* Restore the character in advance, since we want to
1875 report the detailed warning message here. */
1877 *(argsStart
- 1) = save_c
;
1878 as_warn (_("Read-only CSR is written `%s'"), str
);
1879 insn_with_csr
= FALSE
;
1884 /* Successful assembly. */
1886 insn_with_csr
= FALSE
;
1892 case 's': /* RS1 x8-x15 */
1893 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1894 || !(regno
>= 8 && regno
<= 15))
1896 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1898 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1899 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1900 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1903 case 't': /* RS2 x8-x15 */
1904 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1905 || !(regno
>= 8 && regno
<= 15))
1907 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1909 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1910 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1911 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1914 case 'U': /* RS1, constrained to equal RD. */
1915 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1916 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1920 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1922 INSERT_OPERAND (CRS2
, *ip
, regno
);
1924 case 'c': /* RS1, constrained to equal sp. */
1925 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1929 case 'z': /* RS2, contrained to equal x0. */
1930 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1935 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1936 || imm_expr
->X_op
!= O_constant
1937 || imm_expr
->X_add_number
<= 0
1938 || imm_expr
->X_add_number
>= 64)
1940 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1943 imm_expr
->X_op
= O_absent
;
1946 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1947 || imm_expr
->X_op
!= O_constant
1948 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1949 || imm_expr
->X_add_number
<= 0
1950 || imm_expr
->X_add_number
>= 32)
1952 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1955 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1956 || imm_expr
->X_op
!= O_constant
1957 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1958 || imm_expr
->X_add_number
< 0
1959 || imm_expr
->X_add_number
>= 256)
1961 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1964 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1965 || imm_expr
->X_op
!= O_constant
1966 || imm_expr
->X_add_number
== 0
1967 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1969 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1972 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1973 || imm_expr
->X_op
!= O_constant
1974 || imm_expr
->X_add_number
== 0
1975 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1977 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1980 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1982 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1983 || imm_expr
->X_op
!= O_constant
1984 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1986 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1989 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1991 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1992 || imm_expr
->X_op
!= O_constant
1993 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1995 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1998 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2000 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2001 || imm_expr
->X_op
!= O_constant
2002 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
2005 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2008 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2010 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2011 || imm_expr
->X_op
!= O_constant
2012 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
2015 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2018 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2019 || imm_expr
->X_op
!= O_constant
2020 /* C.addiw, c.li, and c.andi allow zero immediate.
2021 C.addi allows zero immediate as hint. Otherwise this
2023 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
2025 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2028 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2029 || imm_expr
->X_op
!= O_constant
2030 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
2031 || imm_expr
->X_add_number
== 0)
2034 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2037 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2038 || imm_expr
->X_op
!= O_constant
2039 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
2040 || imm_expr
->X_add_number
== 0)
2043 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2046 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2048 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2049 || imm_expr
->X_op
!= O_constant
2050 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
2053 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2056 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2058 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2059 || imm_expr
->X_op
!= O_constant
2060 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
2063 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2066 p
= percent_op_utype
;
2067 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2070 if (imm_expr
->X_op
!= O_constant
2071 || imm_expr
->X_add_number
<= 0
2072 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2073 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2074 && (imm_expr
->X_add_number
<
2075 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2077 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2080 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2081 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2082 || ((int32_t)imm_expr
->X_add_number
2083 != imm_expr
->X_add_number
))
2085 imm_expr
->X_add_number
=
2086 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2092 case 'S': /* Floating-point RS1 x8-x15. */
2093 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2094 || !(regno
>= 8 && regno
<= 15))
2096 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2098 case 'D': /* Floating-point RS2 x8-x15. */
2099 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2100 || !(regno
>= 8 && regno
<= 15))
2102 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2104 case 'T': /* Floating-point RS2. */
2105 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2107 INSERT_OPERAND (CRS2
, *ip
, regno
);
2113 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2114 || imm_expr
->X_op
!= O_constant
2115 || imm_expr
->X_add_number
< 0
2116 || imm_expr
->X_add_number
>= 64)
2118 as_bad (_("bad value for funct6 field, "
2119 "value must be 0...64"));
2123 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2124 imm_expr
->X_op
= O_absent
;
2128 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2129 || imm_expr
->X_op
!= O_constant
2130 || imm_expr
->X_add_number
< 0
2131 || imm_expr
->X_add_number
>= 16)
2133 as_bad (_("bad value for funct4 field, "
2134 "value must be 0...15"));
2138 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2139 imm_expr
->X_op
= O_absent
;
2143 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2144 || imm_expr
->X_op
!= O_constant
2145 || imm_expr
->X_add_number
< 0
2146 || imm_expr
->X_add_number
>= 8)
2148 as_bad (_("bad value for funct3 field, "
2149 "value must be 0...7"));
2152 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2153 imm_expr
->X_op
= O_absent
;
2157 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2158 || imm_expr
->X_op
!= O_constant
2159 || imm_expr
->X_add_number
< 0
2160 || imm_expr
->X_add_number
>= 4)
2162 as_bad (_("bad value for funct2 field, "
2163 "value must be 0...3"));
2166 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2167 imm_expr
->X_op
= O_absent
;
2171 as_bad (_("bad compressed FUNCT field"
2172 " specifier 'CF%c'\n"),
2178 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2197 case '<': /* Shift amount, 0 - 31. */
2198 my_getExpression (imm_expr
, s
);
2199 check_absolute_expr (ip
, imm_expr
, FALSE
);
2200 if ((unsigned long) imm_expr
->X_add_number
> 31)
2201 as_bad (_("Improper shift amount (%lu)"),
2202 (unsigned long) imm_expr
->X_add_number
);
2203 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2204 imm_expr
->X_op
= O_absent
;
2208 case '>': /* Shift amount, 0 - (XLEN-1). */
2209 my_getExpression (imm_expr
, s
);
2210 check_absolute_expr (ip
, imm_expr
, FALSE
);
2211 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2212 as_bad (_("Improper shift amount (%lu)"),
2213 (unsigned long) imm_expr
->X_add_number
);
2214 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2215 imm_expr
->X_op
= O_absent
;
2219 case 'Z': /* CSRRxI immediate. */
2220 my_getExpression (imm_expr
, s
);
2221 check_absolute_expr (ip
, imm_expr
, FALSE
);
2222 if ((unsigned long) imm_expr
->X_add_number
> 31)
2223 as_bad (_("Improper CSRxI immediate (%lu)"),
2224 (unsigned long) imm_expr
->X_add_number
);
2225 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2226 imm_expr
->X_op
= O_absent
;
2230 case 'E': /* Control register. */
2231 insn_with_csr
= TRUE
;
2232 explicit_priv_attr
= TRUE
;
2233 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2234 INSERT_OPERAND (CSR
, *ip
, regno
);
2237 my_getExpression (imm_expr
, s
);
2238 check_absolute_expr (ip
, imm_expr
, TRUE
);
2239 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2240 as_bad (_("Improper CSR address (%lu)"),
2241 (unsigned long) imm_expr
->X_add_number
);
2242 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2243 imm_expr
->X_op
= O_absent
;
2248 case 'm': /* Rounding mode. */
2249 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2251 INSERT_OPERAND (RM
, *ip
, regno
);
2257 case 'Q': /* Fence predecessor/successor. */
2258 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2262 INSERT_OPERAND (PRED
, *ip
, regno
);
2264 INSERT_OPERAND (SUCC
, *ip
, regno
);
2269 case 'd': /* Destination register. */
2270 case 's': /* Source register. */
2271 case 't': /* Target register. */
2272 case 'r': /* rs3. */
2273 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2279 /* Now that we have assembled one operand, we use the args
2280 string to figure out where it goes in the instruction. */
2284 INSERT_OPERAND (RS1
, *ip
, regno
);
2287 INSERT_OPERAND (RD
, *ip
, regno
);
2290 INSERT_OPERAND (RS2
, *ip
, regno
);
2293 INSERT_OPERAND (RS3
, *ip
, regno
);
2300 case 'D': /* Floating point rd. */
2301 case 'S': /* Floating point rs1. */
2302 case 'T': /* Floating point rs2. */
2303 case 'U': /* Floating point rs1 and rs2. */
2304 case 'R': /* Floating point rs3. */
2305 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2313 INSERT_OPERAND (RD
, *ip
, regno
);
2316 INSERT_OPERAND (RS1
, *ip
, regno
);
2319 INSERT_OPERAND (RS1
, *ip
, regno
);
2322 INSERT_OPERAND (RS2
, *ip
, regno
);
2325 INSERT_OPERAND (RS3
, *ip
, regno
);
2334 my_getExpression (imm_expr
, s
);
2335 if (imm_expr
->X_op
!= O_big
2336 && imm_expr
->X_op
!= O_constant
)
2338 normalize_constant_expr (imm_expr
);
2343 my_getExpression (imm_expr
, s
);
2344 normalize_constant_expr (imm_expr
);
2345 /* The 'A' format specifier must be a symbol. */
2346 if (imm_expr
->X_op
!= O_symbol
)
2348 *imm_reloc
= BFD_RELOC_32
;
2353 my_getExpression (imm_expr
, s
);
2354 normalize_constant_expr (imm_expr
);
2355 /* The 'B' format specifier must be a symbol or a constant. */
2356 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2358 if (imm_expr
->X_op
== O_symbol
)
2359 *imm_reloc
= BFD_RELOC_32
;
2363 case 'j': /* Sign-extended immediate. */
2364 p
= percent_op_itype
;
2365 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2367 case 'q': /* Store displacement. */
2368 p
= percent_op_stype
;
2369 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2371 case 'o': /* Load displacement. */
2372 p
= percent_op_itype
;
2373 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2375 case '1': /* 4-operand add, must be %tprel_add. */
2376 p
= percent_op_rtype
;
2378 case '0': /* AMO "displacement," which must be zero. */
2379 p
= percent_op_null
;
2381 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2384 /* If this value won't fit into a 16 bit offset, then go
2385 find a macro that will generate the 32 bit offset
2387 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2389 normalize_constant_expr (imm_expr
);
2390 if (imm_expr
->X_op
!= O_constant
2391 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2393 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2394 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2401 case 'p': /* PC-relative offset. */
2403 *imm_reloc
= BFD_RELOC_12_PCREL
;
2404 my_getExpression (imm_expr
, s
);
2408 case 'u': /* Upper 20 bits. */
2409 p
= percent_op_utype
;
2410 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2412 if (imm_expr
->X_op
!= O_constant
)
2415 if (imm_expr
->X_add_number
< 0
2416 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2417 as_bad (_("lui expression not in range 0..1048575"));
2419 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2420 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2425 case 'a': /* 20-bit PC-relative offset. */
2427 my_getExpression (imm_expr
, s
);
2429 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2433 my_getExpression (imm_expr
, s
);
2435 if (strcmp (s
, "@plt") == 0)
2437 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2441 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2447 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2448 || imm_expr
->X_op
!= O_constant
2449 || imm_expr
->X_add_number
< 0
2450 || imm_expr
->X_add_number
>= 128
2451 || (imm_expr
->X_add_number
& 0x3) != 3)
2453 as_bad (_("bad value for opcode field, "
2454 "value must be 0...127 and "
2455 "lower 2 bits must be 0x3"));
2459 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2460 imm_expr
->X_op
= O_absent
;
2464 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2465 || imm_expr
->X_op
!= O_constant
2466 || imm_expr
->X_add_number
< 0
2467 || imm_expr
->X_add_number
>= 3)
2469 as_bad (_("bad value for opcode field, "
2470 "value must be 0...2"));
2474 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2475 imm_expr
->X_op
= O_absent
;
2479 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2487 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2488 || imm_expr
->X_op
!= O_constant
2489 || imm_expr
->X_add_number
< 0
2490 || imm_expr
->X_add_number
>= 128)
2492 as_bad (_("bad value for funct7 field, "
2493 "value must be 0...127"));
2497 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2498 imm_expr
->X_op
= O_absent
;
2502 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2503 || imm_expr
->X_op
!= O_constant
2504 || imm_expr
->X_add_number
< 0
2505 || imm_expr
->X_add_number
>= 8)
2507 as_bad (_("bad value for funct3 field, "
2508 "value must be 0...7"));
2512 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2513 imm_expr
->X_op
= O_absent
;
2517 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2518 || imm_expr
->X_op
!= O_constant
2519 || imm_expr
->X_add_number
< 0
2520 || imm_expr
->X_add_number
>= 4)
2522 as_bad (_("bad value for funct2 field, "
2523 "value must be 0...3"));
2527 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2528 imm_expr
->X_op
= O_absent
;
2533 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2538 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2539 || imm_expr
->X_op
!= O_constant
2540 || imm_expr
->X_add_number
!= 0)
2543 imm_expr
->X_op
= O_absent
;
2547 as_fatal (_("internal error: bad argument type %c"), *args
);
2552 error
= _("illegal operands");
2553 insn_with_csr
= FALSE
;
2557 /* Restore the character we might have clobbered above. */
2559 *(argsStart
- 1) = save_c
;
2565 md_assemble (char *str
)
2567 struct riscv_cl_insn insn
;
2568 expressionS imm_expr
;
2569 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2571 /* The arch and priv attributes should be set before assembling. */
2572 if (!start_assemble
)
2574 start_assemble
= TRUE
;
2576 /* Set the default_priv_spec according to the priv attributes. */
2577 if (!riscv_set_default_priv_spec (NULL
))
2581 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2585 as_bad ("%s `%s'", error
, str
);
2589 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2590 macro (&insn
, &imm_expr
, &imm_reloc
);
2592 append_insn (&insn
, &imm_expr
, imm_reloc
);
2596 md_atof (int type
, char *litP
, int *sizeP
)
2598 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2602 md_number_to_chars (char *buf
, valueT val
, int n
)
2604 number_to_chars_littleendian (buf
, val
, n
);
2607 const char *md_shortopts
= "O::g::G:";
2611 OPTION_MARCH
= OPTION_MD_BASE
,
2618 OPTION_NO_ARCH_ATTR
,
2620 OPTION_NO_CSR_CHECK
,
2626 struct option md_longopts
[] =
2628 {"march", required_argument
, NULL
, OPTION_MARCH
},
2629 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2630 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2631 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2632 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2633 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2634 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2635 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2636 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2637 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2638 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2639 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2640 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2642 {NULL
, no_argument
, NULL
, 0}
2644 size_t md_longopts_size
= sizeof (md_longopts
);
2647 FLOAT_ABI_DEFAULT
= -1,
2653 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2656 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2658 abi_xlen
= new_xlen
;
2659 float_abi
= new_float_abi
;
2664 md_parse_option (int c
, const char *arg
)
2669 /* riscv_after_parse_args will call riscv_set_arch to parse
2670 the architecture. */
2671 default_arch_with_ext
= arg
;
2675 riscv_opts
.pic
= FALSE
;
2679 riscv_opts
.pic
= TRUE
;
2683 if (strcmp (arg
, "ilp32") == 0)
2684 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2685 else if (strcmp (arg
, "ilp32e") == 0)
2686 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2687 else if (strcmp (arg
, "ilp32f") == 0)
2688 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2689 else if (strcmp (arg
, "ilp32d") == 0)
2690 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2691 else if (strcmp (arg
, "ilp32q") == 0)
2692 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2693 else if (strcmp (arg
, "lp64") == 0)
2694 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2695 else if (strcmp (arg
, "lp64f") == 0)
2696 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2697 else if (strcmp (arg
, "lp64d") == 0)
2698 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2699 else if (strcmp (arg
, "lp64q") == 0)
2700 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2706 riscv_opts
.relax
= TRUE
;
2709 case OPTION_NO_RELAX
:
2710 riscv_opts
.relax
= FALSE
;
2713 case OPTION_ARCH_ATTR
:
2714 riscv_opts
.arch_attr
= TRUE
;
2717 case OPTION_NO_ARCH_ATTR
:
2718 riscv_opts
.arch_attr
= FALSE
;
2721 case OPTION_CSR_CHECK
:
2722 riscv_opts
.csr_check
= TRUE
;
2725 case OPTION_NO_CSR_CHECK
:
2726 riscv_opts
.csr_check
= FALSE
;
2729 case OPTION_MISA_SPEC
:
2730 return riscv_set_default_isa_spec (arg
);
2732 case OPTION_MPRIV_SPEC
:
2733 return riscv_set_default_priv_spec (arg
);
2743 riscv_after_parse_args (void)
2745 /* The --with-arch is optional for now, so we have to set the xlen
2746 according to the default_arch, which is set by the --targte, first.
2747 Then, we use the xlen to set the default_arch_with_ext if the
2748 -march and --with-arch are not set. */
2751 if (strcmp (default_arch
, "riscv32") == 0)
2753 else if (strcmp (default_arch
, "riscv64") == 0)
2756 as_bad ("unknown default architecture `%s'", default_arch
);
2758 if (default_arch_with_ext
== NULL
)
2759 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2761 /* Initialize the hash table for extensions with default version. */
2762 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2764 /* If the -misa-spec isn't set, then we set the default ISA spec according
2765 to DEFAULT_RISCV_ISA_SPEC. */
2766 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2767 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2769 /* Set the architecture according to -march or or --with-arch. */
2770 riscv_set_arch (default_arch_with_ext
);
2772 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2773 riscv_set_rvc (FALSE
);
2774 if (riscv_subset_supports ("c"))
2775 riscv_set_rvc (TRUE
);
2777 /* Enable RVE if specified by the -march option. */
2778 riscv_set_rve (FALSE
);
2779 if (riscv_subset_supports ("e"))
2780 riscv_set_rve (TRUE
);
2782 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2783 according to DEFAULT_PRIV_SPEC. */
2784 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2785 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2787 /* Infer ABI from ISA if not specified on command line. */
2790 else if (abi_xlen
> xlen
)
2791 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2792 else if (abi_xlen
< xlen
)
2793 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2795 if (float_abi
== FLOAT_ABI_DEFAULT
)
2797 riscv_subset_t
*subset
;
2799 /* Assume soft-float unless D extension is present. */
2800 float_abi
= FLOAT_ABI_SOFT
;
2802 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2804 if (strcasecmp (subset
->name
, "D") == 0)
2805 float_abi
= FLOAT_ABI_DOUBLE
;
2806 if (strcasecmp (subset
->name
, "Q") == 0)
2807 float_abi
= FLOAT_ABI_QUAD
;
2812 elf_flags
|= EF_RISCV_RVE
;
2814 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2815 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2817 /* If the CIE to be produced has not been overridden on the command line,
2818 then produce version 3 by default. This allows us to use the full
2819 range of registers in a .cfi_return_column directive. */
2820 if (flag_dwarf_cie_version
== -1)
2821 flag_dwarf_cie_version
= 3;
2825 md_pcrel_from (fixS
*fixP
)
2827 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2830 /* Apply a fixup to the object file. */
2833 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2835 unsigned int subtype
;
2836 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2837 bfd_boolean relaxable
= FALSE
;
2841 /* Remember value for tc_gen_reloc. */
2842 fixP
->fx_addnumber
= *valP
;
2844 switch (fixP
->fx_r_type
)
2846 case BFD_RELOC_RISCV_HI20
:
2847 case BFD_RELOC_RISCV_LO12_I
:
2848 case BFD_RELOC_RISCV_LO12_S
:
2849 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2850 | bfd_getl32 (buf
), buf
);
2851 if (fixP
->fx_addsy
== NULL
)
2852 fixP
->fx_done
= TRUE
;
2856 case BFD_RELOC_RISCV_GOT_HI20
:
2857 case BFD_RELOC_RISCV_ADD8
:
2858 case BFD_RELOC_RISCV_ADD16
:
2859 case BFD_RELOC_RISCV_ADD32
:
2860 case BFD_RELOC_RISCV_ADD64
:
2861 case BFD_RELOC_RISCV_SUB6
:
2862 case BFD_RELOC_RISCV_SUB8
:
2863 case BFD_RELOC_RISCV_SUB16
:
2864 case BFD_RELOC_RISCV_SUB32
:
2865 case BFD_RELOC_RISCV_SUB64
:
2866 case BFD_RELOC_RISCV_RELAX
:
2869 case BFD_RELOC_RISCV_TPREL_HI20
:
2870 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2871 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2872 case BFD_RELOC_RISCV_TPREL_ADD
:
2876 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2877 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2878 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2879 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2880 if (fixP
->fx_addsy
!= NULL
)
2881 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2884 _("TLS relocation against a constant"));
2888 /* Use pc-relative relocation for FDE initial location.
2889 The symbol address in .eh_frame may be adjusted in
2890 _bfd_elf_discard_section_eh_frame, and the content of
2891 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2892 Therefore, we cannot insert a relocation whose addend symbol is
2893 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2894 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2895 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2896 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2897 && S_GET_VALUE (fixP
->fx_subsy
)
2898 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2900 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2901 fixP
->fx_subsy
= NULL
;
2908 case BFD_RELOC_RISCV_CFA
:
2909 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2911 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2912 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2913 fixP
->fx_next
->fx_subsy
= NULL
;
2914 fixP
->fx_next
->fx_offset
= 0;
2915 fixP
->fx_subsy
= NULL
;
2917 switch (fixP
->fx_r_type
)
2920 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2921 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2925 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2926 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2930 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2931 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2935 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2936 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2939 case BFD_RELOC_RISCV_CFA
:
2940 /* Load the byte to get the subtype. */
2941 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2942 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2945 case DW_CFA_advance_loc1
:
2946 fixP
->fx_where
= loc
+ 1;
2947 fixP
->fx_next
->fx_where
= loc
+ 1;
2948 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2949 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2952 case DW_CFA_advance_loc2
:
2954 fixP
->fx_next
->fx_size
= 2;
2955 fixP
->fx_where
= loc
+ 1;
2956 fixP
->fx_next
->fx_where
= loc
+ 1;
2957 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2958 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2961 case DW_CFA_advance_loc4
:
2963 fixP
->fx_next
->fx_size
= 4;
2964 fixP
->fx_where
= loc
;
2965 fixP
->fx_next
->fx_where
= loc
;
2966 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2967 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2971 if (subtype
< 0x80 && (subtype
& 0x40))
2973 /* DW_CFA_advance_loc */
2974 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2975 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2976 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2977 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2980 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2986 /* This case is unreachable. */
2993 /* If we are deleting this reloc entry, we must fill in the
2994 value now. This can happen if we have a .word which is not
2995 resolved when it appears but is later defined. */
2996 if (fixP
->fx_addsy
== NULL
)
2998 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2999 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3004 case BFD_RELOC_RISCV_JMP
:
3007 /* Fill in a tentative value to improve objdump readability. */
3008 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3009 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3010 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3014 case BFD_RELOC_12_PCREL
:
3017 /* Fill in a tentative value to improve objdump readability. */
3018 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3019 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3020 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3024 case BFD_RELOC_RISCV_RVC_BRANCH
:
3027 /* Fill in a tentative value to improve objdump readability. */
3028 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3029 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3030 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3034 case BFD_RELOC_RISCV_RVC_JUMP
:
3037 /* Fill in a tentative value to improve objdump readability. */
3038 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3039 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3040 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3044 case BFD_RELOC_RISCV_CALL
:
3045 case BFD_RELOC_RISCV_CALL_PLT
:
3049 case BFD_RELOC_RISCV_PCREL_HI20
:
3050 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3051 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3052 relaxable
= riscv_opts
.relax
;
3055 case BFD_RELOC_RISCV_ALIGN
:
3059 /* We ignore generic BFD relocations we don't know about. */
3060 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3061 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3064 if (fixP
->fx_subsy
!= NULL
)
3065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3066 _("unsupported symbol subtraction"));
3068 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3069 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3071 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3072 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3073 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3077 /* Because the value of .cfi_remember_state may changed after relaxation,
3078 we insert a fix to relocate it again in link-time. */
3081 riscv_pre_output_hook (void)
3083 const frchainS
*frch
;
3086 /* Save the current segment info. */
3088 subsegT subseg
= now_subseg
;
3090 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3091 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3095 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3097 if (frag
->fr_type
== rs_cfa
)
3100 expressionS
*symval
;
3102 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3103 exp
.X_op
= O_subtract
;
3104 exp
.X_add_symbol
= symval
->X_add_symbol
;
3105 exp
.X_add_number
= 0;
3106 exp
.X_op_symbol
= symval
->X_op_symbol
;
3108 /* We must set the segment before creating a frag after all
3109 frag chains have been chained together. */
3110 subseg_set (s
, frch
->frch_subseg
);
3112 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3113 BFD_RELOC_RISCV_CFA
);
3118 /* Restore the original segment info. */
3119 subseg_set (seg
, subseg
);
3123 /* This structure is used to hold a stack of .option values. */
3125 struct riscv_option_stack
3127 struct riscv_option_stack
*next
;
3128 struct riscv_set_options options
;
3131 static struct riscv_option_stack
*riscv_opts_stack
;
3133 /* Handle the .option pseudo-op. */
3136 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3138 char *name
= input_line_pointer
, ch
;
3140 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3141 ++input_line_pointer
;
3142 ch
= *input_line_pointer
;
3143 *input_line_pointer
= '\0';
3145 if (strcmp (name
, "rvc") == 0)
3146 riscv_set_rvc (TRUE
);
3147 else if (strcmp (name
, "norvc") == 0)
3148 riscv_set_rvc (FALSE
);
3149 else if (strcmp (name
, "pic") == 0)
3150 riscv_opts
.pic
= TRUE
;
3151 else if (strcmp (name
, "nopic") == 0)
3152 riscv_opts
.pic
= FALSE
;
3153 else if (strcmp (name
, "relax") == 0)
3154 riscv_opts
.relax
= TRUE
;
3155 else if (strcmp (name
, "norelax") == 0)
3156 riscv_opts
.relax
= FALSE
;
3157 else if (strcmp (name
, "csr-check") == 0)
3158 riscv_opts
.csr_check
= TRUE
;
3159 else if (strcmp (name
, "no-csr-check") == 0)
3160 riscv_opts
.csr_check
= FALSE
;
3161 else if (strcmp (name
, "push") == 0)
3163 struct riscv_option_stack
*s
;
3165 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3166 s
->next
= riscv_opts_stack
;
3167 s
->options
= riscv_opts
;
3168 riscv_opts_stack
= s
;
3170 else if (strcmp (name
, "pop") == 0)
3172 struct riscv_option_stack
*s
;
3174 s
= riscv_opts_stack
;
3176 as_bad (_(".option pop with no .option push"));
3179 riscv_opts
= s
->options
;
3180 riscv_opts_stack
= s
->next
;
3186 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3188 *input_line_pointer
= ch
;
3189 demand_empty_rest_of_line ();
3192 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3193 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3194 use in DWARF debug information. */
3197 s_dtprel (int bytes
)
3204 if (ex
.X_op
!= O_symbol
)
3206 as_bad (_("Unsupported use of %s"), (bytes
== 8
3209 ignore_rest_of_line ();
3212 p
= frag_more (bytes
);
3213 md_number_to_chars (p
, 0, bytes
);
3214 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3216 ? BFD_RELOC_RISCV_TLS_DTPREL64
3217 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3219 demand_empty_rest_of_line ();
3222 /* Handle the .bss pseudo-op. */
3225 s_bss (int ignore ATTRIBUTE_UNUSED
)
3227 subseg_set (bss_section
, 0);
3228 demand_empty_rest_of_line ();
3232 riscv_make_nops (char *buf
, bfd_vma bytes
)
3236 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3237 means we are not within a valid instruction sequence. It is thus safe
3238 to use a zero byte, even though that is not a valid instruction. */
3242 /* Use at most one 2-byte NOP. */
3243 if ((bytes
- i
) % 4 == 2)
3245 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3249 /* Fill the remainder with 4-byte NOPs. */
3250 for ( ; i
< bytes
; i
+= 4)
3251 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3254 /* Called from md_do_align. Used to create an alignment frag in a
3255 code section by emitting a worst-case NOP sequence that the linker
3256 will later relax to the correct number of NOPs. We can't compute
3257 the correct alignment now because of other linker relaxations. */
3260 riscv_frag_align_code (int n
)
3262 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3263 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3264 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3268 /* If we are moving to a smaller alignment than the instruction size, then no
3269 alignment is required. */
3270 if (bytes
<= insn_alignment
)
3273 /* When not relaxing, riscv_handle_align handles code alignment. */
3274 if (!riscv_opts
.relax
)
3277 nops
= frag_more (worst_case_bytes
);
3279 ex
.X_op
= O_constant
;
3280 ex
.X_add_number
= worst_case_bytes
;
3282 riscv_make_nops (nops
, worst_case_bytes
);
3284 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3285 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3290 /* Implement HANDLE_ALIGN. */
3293 riscv_handle_align (fragS
*fragP
)
3295 switch (fragP
->fr_type
)
3298 /* When relaxing, riscv_frag_align_code handles code alignment. */
3299 if (!riscv_opts
.relax
)
3301 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3302 - fragP
->fr_address
- fragP
->fr_fix
);
3303 /* We have 4 byte uncompressed nops. */
3304 bfd_signed_vma size
= 4;
3305 bfd_signed_vma excess
= bytes
% size
;
3306 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3311 /* Insert zeros or compressed nops to get 4 byte alignment. */
3314 riscv_make_nops (p
, excess
);
3315 fragP
->fr_fix
+= excess
;
3319 /* Insert variable number of 4 byte uncompressed nops. */
3320 riscv_make_nops (p
, size
);
3321 fragP
->fr_var
= size
;
3331 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3333 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3336 /* Translate internal representation of relocation info to BFD target
3340 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3342 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3344 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3345 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3346 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3347 reloc
->addend
= fixp
->fx_addnumber
;
3349 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3350 if (reloc
->howto
== NULL
)
3352 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3353 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3355 /* We don't have R_RISCV_8/16, but for this special case,
3356 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3360 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3361 _("cannot represent %s relocation in object file"),
3362 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3370 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3372 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3374 offsetT old_var
= fragp
->fr_var
;
3375 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3376 return fragp
->fr_var
- old_var
;
3382 /* Expand far branches to multi-instruction sequences. */
3385 md_convert_frag_branch (fragS
*fragp
)
3393 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3395 exp
.X_op
= O_symbol
;
3396 exp
.X_add_symbol
= fragp
->fr_symbol
;
3397 exp
.X_add_number
= fragp
->fr_offset
;
3399 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3401 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3403 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3407 /* Expand the RVC branch into a RISC-V one. */
3408 insn
= bfd_getl16 (buf
);
3409 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3410 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3412 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3413 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3414 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3415 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3416 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3417 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3420 bfd_putl32 (insn
, buf
);
3424 /* Invert the branch condition. Branch over the jump. */
3425 insn
= bfd_getl16 (buf
);
3426 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3427 insn
|= ENCODE_RVC_B_IMM (6);
3428 bfd_putl16 (insn
, buf
);
3433 /* Just keep the RVC branch. */
3434 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3435 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3436 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3437 2, &exp
, FALSE
, reloc
);
3446 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3449 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3451 /* Invert the branch condition. Branch over the jump. */
3452 insn
= bfd_getl32 (buf
);
3453 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3454 insn
|= ENCODE_SBTYPE_IMM (8);
3455 md_number_to_chars ((char *) buf
, insn
, 4);
3459 /* Jump to the target. */
3460 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3461 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3462 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3467 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3468 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3469 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3470 4, &exp
, FALSE
, reloc
);
3479 fixp
->fx_file
= fragp
->fr_file
;
3480 fixp
->fx_line
= fragp
->fr_line
;
3482 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3483 + fragp
->fr_fix
+ fragp
->fr_var
);
3485 fragp
->fr_fix
+= fragp
->fr_var
;
3488 /* Relax a machine dependent frag. This returns the amount by which
3489 the current size of the frag should change. */
3492 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3495 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3496 md_convert_frag_branch (fragp
);
3500 md_show_usage (FILE *stream
)
3502 fprintf (stream
, _("\
3504 -fpic generate position-independent code\n\
3505 -fno-pic don't generate position-independent code (default)\n\
3506 -march=ISA set the RISC-V architecture\n\
3507 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3508 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3509 -mabi=ABI set the RISC-V ABI\n\
3510 -mrelax enable relax (default)\n\
3511 -mno-relax disable relax\n\
3512 -march-attr generate RISC-V arch attribute\n\
3513 -mno-arch-attr don't generate RISC-V arch attribute\n\
3517 /* Standard calling conventions leave the CFA at SP on entry. */
3519 riscv_cfi_frame_initial_instructions (void)
3521 cfi_add_CFA_def_cfa_register (X_SP
);
3525 tc_riscv_regname_to_dw2regnum (char *regname
)
3529 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3532 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3535 /* CSRs are numbered 4096 -> 8191. */
3536 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3539 as_bad (_("unknown register `%s'"), regname
);
3544 riscv_elf_final_processing (void)
3546 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3549 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3550 since these directives break relaxation when used with symbol deltas. */
3553 s_riscv_leb128 (int sign
)
3556 char *save_in
= input_line_pointer
;
3559 if (exp
.X_op
!= O_constant
)
3560 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3561 demand_empty_rest_of_line ();
3563 input_line_pointer
= save_in
;
3564 return s_leb128 (sign
);
3567 /* Parse the .insn directive. */
3570 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3572 char *str
= input_line_pointer
;
3573 struct riscv_cl_insn insn
;
3574 expressionS imm_expr
;
3575 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3578 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3579 ++input_line_pointer
;
3581 save_c
= *input_line_pointer
;
3582 *input_line_pointer
= '\0';
3584 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3585 &imm_reloc
, insn_type_hash
);
3589 as_bad ("%s `%s'", error
, str
);
3593 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3594 append_insn (&insn
, &imm_expr
, imm_reloc
);
3597 *input_line_pointer
= save_c
;
3598 demand_empty_rest_of_line ();
3601 /* Update arch and priv attributes. If we don't set the corresponding ELF
3602 attributes, then try to output the default ones. */
3605 riscv_write_out_attrs (void)
3607 const char *arch_str
, *priv_str
, *p
;
3608 /* versions[0] is major, versions[1] is minor,
3609 and versions[3] is revision. */
3610 unsigned versions
[3] = {0}, number
= 0;
3613 /* Re-write arch attribute to normalize the arch string. */
3614 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3615 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3616 xfree ((void *)arch_str
);
3618 /* For the file without any instruction, we don't set the default_priv_spec
3619 according to the priv attributes since the md_assemble isn't called.
3620 Call riscv_set_default_priv_spec here for the above case, although
3621 it seems strange. */
3623 && !riscv_set_default_priv_spec (NULL
))
3626 /* If we already have set elf priv attributes, then no need to do anything,
3627 assembler will generate them according to what you set. Otherwise, don't
3628 generate or update them when no CSR and priv instructions are used.
3629 Generate the priv attributes according to default_priv_spec, which can be
3630 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3631 priv attribute sets. */
3632 if (!explicit_priv_attr
)
3635 /* Re-write priv attributes by default_priv_spec. */
3636 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3638 for (i
= 0; *p
; ++p
)
3640 if (*p
== '.' && i
< 3)
3642 versions
[i
++] = number
;
3645 else if (ISDIGIT (*p
))
3646 number
= (number
* 10) + (*p
- '0');
3649 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3653 versions
[i
] = number
;
3655 /* Set the priv attributes. */
3656 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3657 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3658 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3661 /* Add the default contents for the .riscv.attributes section. If any
3662 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3663 to update the arch and priv attributes. */
3666 riscv_set_public_attributes (void)
3668 if (riscv_opts
.arch_attr
|| explicit_attr
)
3669 riscv_write_out_attrs ();
3672 /* Called after all assembly has been done. */
3677 riscv_set_public_attributes ();
3680 /* Given a symbolic attribute NAME, return the proper integer value.
3681 Returns -1 if the attribute is not known. */
3684 riscv_convert_symbolic_attribute (const char *name
)
3693 /* When you modify this table you should
3694 also modify the list in doc/c-riscv.texi. */
3695 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3699 T(priv_spec_revision
),
3700 T(unaligned_access
),
3710 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3711 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3712 return attribute_table
[i
].tag
;
3717 /* Parse a .attribute directive. */
3720 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3722 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3724 obj_attribute
*attr
;
3726 explicit_attr
= TRUE
;
3729 case Tag_RISCV_arch
:
3731 attr
= elf_known_obj_attributes_proc (stdoutput
);
3732 if (!start_assemble
)
3733 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3735 as_fatal (_(".attribute arch must set before any instructions"));
3737 if (old_xlen
!= xlen
)
3739 /* We must re-init bfd again if xlen is changed. */
3740 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3741 bfd_find_target (riscv_target_format (), stdoutput
);
3743 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3744 as_warn (_("Could not set architecture and machine"));
3748 case Tag_RISCV_priv_spec
:
3749 case Tag_RISCV_priv_spec_minor
:
3750 case Tag_RISCV_priv_spec_revision
:
3752 as_fatal (_(".attribute priv spec must set before any instructions"));
3760 /* Pseudo-op table. */
3762 static const pseudo_typeS riscv_pseudo_table
[] =
3764 /* RISC-V-specific pseudo-ops. */
3765 {"option", s_riscv_option
, 0},
3769 {"dtprelword", s_dtprel
, 4},
3770 {"dtpreldword", s_dtprel
, 8},
3772 {"uleb128", s_riscv_leb128
, 0},
3773 {"sleb128", s_riscv_leb128
, 1},
3774 {"insn", s_riscv_insn
, 0},
3775 {"attribute", s_riscv_attribute
, 0},
3781 riscv_pop_insert (void)
3783 extern void pop_insert (const pseudo_typeS
*);
3785 pop_insert (riscv_pseudo_table
);