1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int relax
; /* Emit relocs the linker is allowed to relax. */
81 static struct riscv_set_options riscv_opts
=
89 riscv_set_rvc (bfd_boolean rvc_value
)
92 elf_flags
|= EF_RISCV_RVC
;
94 riscv_opts
.rvc
= rvc_value
;
101 struct riscv_subset
*next
;
104 static struct riscv_subset
*riscv_subsets
;
107 riscv_subset_supports (const char *feature
)
109 struct riscv_subset
*s
;
111 unsigned xlen_required
= strtoul (feature
, &p
, 10);
113 if (xlen_required
&& xlen
!= xlen_required
)
116 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
117 if (strcasecmp (s
->name
, p
) == 0)
124 riscv_clear_subsets (void)
126 while (riscv_subsets
!= NULL
)
128 struct riscv_subset
*next
= riscv_subsets
->next
;
129 free ((void *) riscv_subsets
->name
);
130 free (riscv_subsets
);
131 riscv_subsets
= next
;
136 riscv_add_subset (const char *subset
)
138 struct riscv_subset
*s
= xmalloc (sizeof *s
);
140 s
->name
= xstrdup (subset
);
141 s
->next
= riscv_subsets
;
145 /* Set which ISA and extensions are available. */
148 riscv_set_arch (const char *s
)
150 const char *all_subsets
= "imafdqc";
151 char *extension
= NULL
;
154 riscv_clear_subsets();
156 if (strncmp (p
, "rv32", 4) == 0)
161 else if (strncmp (p
, "rv64", 4) == 0)
167 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
176 for ( ; *all_subsets
!= 'q'; all_subsets
++)
178 const char subset
[] = {*all_subsets
, '\0'};
179 riscv_add_subset (subset
);
184 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s
);
191 char *subset
= xstrdup (p
);
194 while (*++q
!= '\0' && *q
!= '_')
199 as_fatal ("-march=%s: only one non-standard extension is supported"
200 " (found `%s' and `%s')", s
, extension
, subset
);
202 riscv_add_subset (subset
);
203 p
+= strlen (subset
);
207 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
209 const char subset
[] = {*p
, 0};
210 riscv_add_subset (subset
);
215 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
221 /* Handle of the OPCODE hash table. */
222 static struct hash_control
*op_hash
= NULL
;
224 /* This array holds the chars that always start a comment. If the
225 pre-processor is disabled, these aren't very useful */
226 const char comment_chars
[] = "#";
228 /* This array holds the chars that only start a comment at the beginning of
229 a line. If the line seems to have the form '# 123 filename'
230 .line and .file directives will appear in the pre-processed output */
231 /* Note that input_file.c hand checks for '#' at the beginning of the
232 first line of the input file. This is because the compiler outputs
233 #NO_APP at the beginning of its output. */
234 /* Also note that C style comments are always supported. */
235 const char line_comment_chars
[] = "#";
237 /* This array holds machine specific line separator characters. */
238 const char line_separator_chars
[] = ";";
240 /* Chars that can be used to separate mant from exp in floating point nums */
241 const char EXP_CHARS
[] = "eE";
243 /* Chars that mean this number is a floating point constant */
246 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
248 /* Macros for encoding relaxation state for RVC branches and far jumps. */
249 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
252 | ((uncond) ? 1 : 0) \
255 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
256 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
257 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
258 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
260 /* Is the given value a sign-extended 32-bit value? */
261 #define IS_SEXT_32BIT_NUM(x) \
262 (((x) &~ (offsetT) 0x7fffffff) == 0 \
263 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
265 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
266 #define IS_ZEXT_32BIT_NUM(x) \
267 (((x) &~ (offsetT) 0xffffffff) == 0 \
268 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
270 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
271 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
272 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
273 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
275 /* Determine if an instruction matches an opcode. */
276 #define OPCODE_MATCHES(OPCODE, OP) \
277 (((OPCODE) & MASK_##OP) == MATCH_##OP)
279 static char *expr_end
;
281 /* The default target format to use. */
284 riscv_target_format (void)
286 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
289 /* Return the length of instruction INSN. */
291 static inline unsigned int
292 insn_length (const struct riscv_cl_insn
*insn
)
294 return riscv_insn_length (insn
->insn_opcode
);
297 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
300 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
303 insn
->insn_opcode
= mo
->match
;
309 /* Install INSN at the location specified by its "frag" and "where" fields. */
312 install_insn (const struct riscv_cl_insn
*insn
)
314 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
315 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
318 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
319 and install the opcode in the new location. */
322 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
326 if (insn
->fixp
!= NULL
)
328 insn
->fixp
->fx_frag
= frag
;
329 insn
->fixp
->fx_where
= where
;
334 /* Add INSN to the end of the output. */
337 add_fixed_insn (struct riscv_cl_insn
*insn
)
339 char *f
= frag_more (insn_length (insn
));
340 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
344 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
345 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
347 frag_grow (max_chars
);
348 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
349 frag_var (rs_machine_dependent
, max_chars
, var
,
350 subtype
, symbol
, offset
, NULL
);
353 /* Compute the length of a branch sequence, and adjust the stored length
354 accordingly. If FRAGP is NULL, the worst-case length is returned. */
357 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
359 int jump
, rvc
, length
= 8;
364 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
365 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
366 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
368 /* Assume jumps are in range; the linker will catch any that aren't. */
369 length
= jump
? 4 : 8;
371 if (fragp
->fr_symbol
!= NULL
372 && S_IS_DEFINED (fragp
->fr_symbol
)
373 && !S_IS_WEAK (fragp
->fr_symbol
)
374 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
376 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
377 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
378 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
380 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
382 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
384 else if (!jump
&& rvc
)
389 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
408 static struct hash_control
*reg_names_hash
= NULL
;
410 #define ENCODE_REG_HASH(cls, n) \
411 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
412 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
413 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
416 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
418 void *hash
= ENCODE_REG_HASH (class, n
);
419 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
422 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
426 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
430 for (i
= 0; i
< n
; i
++)
431 hash_reg_name (class, names
[i
], i
);
435 reg_lookup_internal (const char *s
, enum reg_class
class)
437 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
439 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
441 return DECODE_REG_NUM (r
);
445 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
451 /* Find end of name. */
453 if (is_name_beginner (*e
))
455 while (is_part_of_name (*e
))
458 /* Terminate name. */
462 /* Look for the register. Advance to next token if one was recognized. */
463 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
473 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
475 const char *p
= strchr (*s
, ',');
476 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
478 for (i
= 0; i
< size
; i
++)
479 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
489 /* For consistency checking, verify that all bits are specified either
490 by the match/mask part of the instruction definition, or by the
493 validate_riscv_insn (const struct riscv_opcode
*opc
)
495 const char *p
= opc
->args
;
497 insn_t used_bits
= opc
->mask
;
498 int insn_width
= 8 * riscv_insn_length (opc
->match
);
499 insn_t required_bits
= ~0ULL >> (64 - insn_width
);
501 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
503 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
504 opc
->name
, opc
->args
);
508 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
515 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
516 case 'c': break; /* RS1, constrained to equal sp */
517 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
518 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
519 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
520 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
521 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
522 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
523 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
524 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
525 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
526 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
527 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
528 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
529 case 'w': break; /* RS1S, constrained to equal RD */
530 case 'x': break; /* RS2S, constrained to equal RD */
531 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
532 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
533 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
534 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
535 case 'U': break; /* RS1, constrained to equal RD */
536 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
537 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
538 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
539 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
540 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
542 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
543 c
, opc
->name
, opc
->args
);
550 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
551 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
553 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
554 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
555 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
557 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
558 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
559 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
560 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
561 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
562 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
563 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
564 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
565 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
566 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
568 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
569 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
570 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
571 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
572 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
577 as_bad (_("internal: bad RISC-V opcode "
578 "(unknown operand type `%c'): %s %s"),
579 c
, opc
->name
, opc
->args
);
583 if (used_bits
!= required_bits
)
585 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
586 ~(unsigned long)(used_bits
& required_bits
),
587 opc
->name
, opc
->args
);
593 struct percent_op_match
596 bfd_reloc_code_real_type reloc
;
599 /* This function is called once, at assembler startup time. It should set up
600 all the tables, etc. that the MD part of the assembler will need. */
606 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
608 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
609 as_warn (_("Could not set architecture and machine"));
611 op_hash
= hash_new ();
613 while (riscv_opcodes
[i
].name
)
615 const char *name
= riscv_opcodes
[i
].name
;
616 const char *hash_error
=
617 hash_insert (op_hash
, name
, (void *) &riscv_opcodes
[i
]);
621 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
622 riscv_opcodes
[i
].name
, hash_error
);
623 /* Probably a memory allocation problem? Give up now. */
624 as_fatal (_("Broken assembler. No assembly attempted."));
629 if (riscv_opcodes
[i
].pinfo
!= INSN_MACRO
)
631 if (!validate_riscv_insn (&riscv_opcodes
[i
]))
632 as_fatal (_("Broken assembler. No assembly attempted."));
636 while (riscv_opcodes
[i
].name
&& !strcmp (riscv_opcodes
[i
].name
, name
));
639 reg_names_hash
= hash_new ();
640 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
641 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
642 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
643 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
645 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
646 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
647 #include "opcode/riscv-opc.h"
650 /* Set the default alignment for the text section. */
651 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
655 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
662 case BFD_RELOC_RISCV_HI20
:
663 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
665 case BFD_RELOC_RISCV_LO12_S
:
666 return ENCODE_STYPE_IMM (value
);
668 case BFD_RELOC_RISCV_LO12_I
:
669 return ENCODE_ITYPE_IMM (value
);
676 /* Output an instruction. IP is the instruction information.
677 ADDRESS_EXPR is an operand of the instruction to be used with
681 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
682 bfd_reloc_code_real_type reloc_type
)
684 dwarf2_emit_insn (0);
686 if (reloc_type
!= BFD_RELOC_UNUSED
)
688 reloc_howto_type
*howto
;
690 gas_assert (address_expr
);
691 if (reloc_type
== BFD_RELOC_12_PCREL
692 || reloc_type
== BFD_RELOC_RISCV_JMP
)
694 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
695 int best_case
= riscv_insn_length (ip
->insn_opcode
);
696 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
697 add_relaxed_insn (ip
, worst_case
, best_case
,
698 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
699 address_expr
->X_add_symbol
,
700 address_expr
->X_add_number
);
705 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
707 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
709 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
710 bfd_get_reloc_size (howto
),
711 address_expr
, FALSE
, reloc_type
);
713 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
720 /* We need to start a new frag after any instruction that can be
721 optimized away or compressed by the linker during relaxation, to prevent
722 the assembler from computing static offsets across such an instruction.
723 This is necessary to get correct EH info. */
724 if (reloc_type
== BFD_RELOC_RISCV_CALL
725 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
726 || reloc_type
== BFD_RELOC_RISCV_HI20
727 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
728 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
729 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
731 frag_wane (frag_now
);
736 /* Build an instruction created by a macro expansion. This is passed
737 a pointer to the count of instructions created so far, an
738 expression, the name of the instruction to build, an operand format
739 string, and corresponding arguments. */
742 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
744 const struct riscv_opcode
*mo
;
745 struct riscv_cl_insn insn
;
746 bfd_reloc_code_real_type r
;
749 va_start (args
, fmt
);
751 r
= BFD_RELOC_UNUSED
;
752 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
755 /* Find a non-RVC variant of the instruction. append_insn will compress
757 while (riscv_insn_length (mo
->match
) < 4)
759 gas_assert (strcmp (name
, mo
->name
) == 0);
761 create_insn (&insn
, mo
);
767 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
771 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
775 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
779 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
785 gas_assert (ep
!= NULL
);
786 r
= va_arg (args
, int);
794 as_fatal (_("internal error: invalid macro"));
799 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
801 append_insn (&insn
, ep
, r
);
804 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
807 normalize_constant_expr (expressionS
*ex
)
811 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
812 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
813 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
817 /* Fail if an expression is not a constant. */
820 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
)
822 if (ex
->X_op
== O_big
)
823 as_bad (_("unsupported large constant"));
824 else if (ex
->X_op
!= O_constant
)
825 as_bad (_("Instruction %s requires absolute expression"),
827 normalize_constant_expr (ex
);
831 make_internal_label (void)
833 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
834 (valueT
) frag_now_fix (), frag_now
);
837 /* Load an entry from the GOT. */
839 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
840 const char *lo_insn
, const char *lo_pattern
,
841 bfd_reloc_code_real_type hi_reloc
,
842 bfd_reloc_code_real_type lo_reloc
)
846 ep2
.X_add_symbol
= make_internal_label ();
847 ep2
.X_add_number
= 0;
849 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
850 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
854 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
855 bfd_reloc_code_real_type hi_reloc
,
856 bfd_reloc_code_real_type lo_reloc
)
858 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
862 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
863 bfd_reloc_code_real_type hi_reloc
,
864 bfd_reloc_code_real_type lo_reloc
)
866 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
869 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
871 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
872 bfd_reloc_code_real_type reloc
)
874 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
875 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
878 /* Load an integer constant into a register. */
881 load_const (int reg
, expressionS
*ep
)
883 int shift
= RISCV_IMM_BITS
;
884 expressionS upper
= *ep
, lower
= *ep
;
885 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
886 upper
.X_add_number
-= lower
.X_add_number
;
888 if (ep
->X_op
!= O_constant
)
890 as_bad (_("unsupported large constant"));
894 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
896 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
897 while (((upper
.X_add_number
>> shift
) & 1) == 0)
900 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
901 load_const (reg
, &upper
);
903 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
904 if (lower
.X_add_number
!= 0)
905 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
909 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
912 if (upper
.X_add_number
!= 0)
914 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
918 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
919 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
920 BFD_RELOC_RISCV_LO12_I
);
924 /* Expand RISC-V assembly macros into one or more instructions. */
926 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
927 bfd_reloc_code_real_type
*imm_reloc
)
929 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
930 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
931 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
932 int mask
= ip
->insn_mo
->mask
;
937 load_const (rd
, imm_expr
);
942 /* Load the address of a symbol into a register. */
943 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
944 as_bad (_("offset too large"));
946 if (imm_expr
->X_op
== O_constant
)
947 load_const (rd
, imm_expr
);
948 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
949 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
950 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
951 else /* Local PIC symbol, or any non-PIC symbol */
952 pcrel_load (rd
, rd
, imm_expr
, "addi",
953 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
957 pcrel_load (rd
, rd
, imm_expr
, "addi",
958 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
962 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
963 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
967 pcrel_load (rd
, rd
, imm_expr
, "lb",
968 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
972 pcrel_load (rd
, rd
, imm_expr
, "lbu",
973 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
977 pcrel_load (rd
, rd
, imm_expr
, "lh",
978 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
982 pcrel_load (rd
, rd
, imm_expr
, "lhu",
983 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
987 pcrel_load (rd
, rd
, imm_expr
, "lw",
988 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
992 pcrel_load (rd
, rd
, imm_expr
, "lwu",
993 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
997 pcrel_load (rd
, rd
, imm_expr
, "ld",
998 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1002 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1003 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1007 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1008 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1012 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1013 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1017 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1018 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1022 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1023 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1027 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1028 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1032 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1033 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1037 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1038 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1042 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1046 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1051 static const struct percent_op_match percent_op_utype
[] =
1053 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1054 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1055 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1056 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1057 {"%hi", BFD_RELOC_RISCV_HI20
},
1061 static const struct percent_op_match percent_op_itype
[] =
1063 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1064 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1065 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1069 static const struct percent_op_match percent_op_stype
[] =
1071 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1072 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1073 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1077 static const struct percent_op_match percent_op_rtype
[] =
1079 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1083 /* Return true if *STR points to a relocation operator. When returning true,
1084 move *STR over the operator and store its relocation code in *RELOC.
1085 Leave both *STR and *RELOC alone when returning false. */
1088 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1089 const struct percent_op_match
*percent_op
)
1091 for ( ; percent_op
->str
; percent_op
++)
1092 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1094 int len
= strlen (percent_op
->str
);
1096 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1099 *str
+= strlen (percent_op
->str
);
1100 *reloc
= percent_op
->reloc
;
1102 /* Check whether the output BFD supports this relocation.
1103 If not, issue an error and fall back on something safe. */
1104 if (*reloc
!= BFD_RELOC_UNUSED
1105 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1107 as_bad ("relocation %s isn't supported by the current ABI",
1109 *reloc
= BFD_RELOC_UNUSED
;
1117 my_getExpression (expressionS
*ep
, char *str
)
1121 save_in
= input_line_pointer
;
1122 input_line_pointer
= str
;
1124 expr_end
= input_line_pointer
;
1125 input_line_pointer
= save_in
;
1128 /* Parse string STR as a 16-bit relocatable operand. Store the
1129 expression in *EP and the relocation, if any, in RELOC.
1130 Return the number of relocation operators used (0 or 1).
1132 On exit, EXPR_END points to the first character after the expression. */
1135 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1136 char *str
, const struct percent_op_match
*percent_op
)
1139 unsigned crux_depth
, str_depth
, regno
;
1142 /* First, check for integer registers. */
1143 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1145 ep
->X_op
= O_register
;
1146 ep
->X_add_number
= regno
;
1150 /* Search for the start of the main expression.
1151 End the loop with CRUX pointing to the start
1152 of the main expression and with CRUX_DEPTH containing the number
1153 of open brackets at that point. */
1160 crux_depth
= str_depth
;
1162 /* Skip over whitespace and brackets, keeping count of the number
1164 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1170 && parse_relocation (&str
, reloc
, percent_op
));
1172 my_getExpression (ep
, crux
);
1175 /* Match every open bracket. */
1176 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1181 as_bad ("unclosed '('");
1188 /* Detect and handle implicitly zero load-store offsets. For example,
1189 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1190 an implicit offset was detected. */
1193 riscv_handle_implicit_zero_offset (expressionS
*expr
, const char *s
)
1195 /* Check whether there is only a single bracketed expression left.
1196 If so, it must be the base register and the constant must be zero. */
1197 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1199 expr
->X_op
= O_constant
;
1200 expr
->X_add_number
= 0;
1207 /* This routine assembles an instruction into its binary format. As a
1208 side effect, it sets the global variable imm_reloc to the type of
1209 relocation to do if one of the operands is an address expression. */
1212 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1213 bfd_reloc_code_real_type
*imm_reloc
)
1218 struct riscv_opcode
*insn
;
1223 const struct percent_op_match
*p
;
1224 const char *error
= "unrecognized opcode";
1226 /* Parse the name of the instruction. Terminate the string if whitespace
1227 is found so that hash_find only sees the name part of the string. */
1228 for (s
= str
; *s
!= '\0'; ++s
)
1236 insn
= (struct riscv_opcode
*) hash_find (op_hash
, str
);
1239 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1241 if (!riscv_subset_supports (insn
->subset
))
1244 create_insn (ip
, insn
);
1247 imm_expr
->X_op
= O_absent
;
1248 *imm_reloc
= BFD_RELOC_UNUSED
;
1249 p
= percent_op_itype
;
1251 for (args
= insn
->args
;; ++args
)
1253 s
+= strspn (s
, " \t");
1256 case '\0': /* End of args. */
1257 if (insn
->pinfo
!= INSN_MACRO
)
1259 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1261 if (riscv_insn_length (insn
->match
) == 2 && !riscv_opts
.rvc
)
1266 /* Successful assembly. */
1273 case 's': /* RS1 x8-x15 */
1274 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1275 || !(regno
>= 8 && regno
<= 15))
1277 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1279 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1280 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1281 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1284 case 't': /* RS2 x8-x15 */
1285 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1286 || !(regno
>= 8 && regno
<= 15))
1288 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1290 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1291 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1292 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1295 case 'U': /* RS1, constrained to equal RD. */
1296 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1297 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1301 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1303 INSERT_OPERAND (CRS2
, *ip
, regno
);
1305 case 'c': /* RS1, constrained to equal sp. */
1306 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1311 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1312 || imm_expr
->X_op
!= O_constant
1313 || imm_expr
->X_add_number
<= 0
1314 || imm_expr
->X_add_number
>= 64)
1316 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1319 imm_expr
->X_op
= O_absent
;
1322 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1323 || imm_expr
->X_op
!= O_constant
1324 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1325 || imm_expr
->X_add_number
<= 0
1326 || imm_expr
->X_add_number
>= 32)
1328 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1331 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1332 || imm_expr
->X_op
!= O_constant
1333 || imm_expr
->X_add_number
== 0
1334 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1336 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1339 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1340 || imm_expr
->X_op
!= O_constant
1341 || imm_expr
->X_add_number
== 0
1342 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1344 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1347 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1349 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1350 || imm_expr
->X_op
!= O_constant
1351 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1353 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1356 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1358 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1359 || imm_expr
->X_op
!= O_constant
1360 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1362 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1365 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1367 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1368 || imm_expr
->X_op
!= O_constant
1369 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1372 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1375 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1377 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1378 || imm_expr
->X_op
!= O_constant
1379 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1382 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1385 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1386 || imm_expr
->X_op
!= O_constant
1387 /* C.addiw, c.li, and c.andi allow zero immediate.
1388 C.addi allows zero immediate as hint. Otherwise this
1390 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1392 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1395 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1396 || imm_expr
->X_op
!= O_constant
1397 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1398 || imm_expr
->X_add_number
== 0)
1401 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1404 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1405 || imm_expr
->X_op
!= O_constant
1406 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1407 || imm_expr
->X_add_number
== 0)
1410 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1413 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1415 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1416 || imm_expr
->X_op
!= O_constant
1417 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1420 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1423 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1425 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1426 || imm_expr
->X_op
!= O_constant
1427 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1430 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1433 p
= percent_op_utype
;
1434 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1437 if (imm_expr
->X_op
!= O_constant
1438 || imm_expr
->X_add_number
<= 0
1439 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1440 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1441 && (imm_expr
->X_add_number
<
1442 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1444 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1447 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1448 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1449 || ((int32_t)imm_expr
->X_add_number
1450 != imm_expr
->X_add_number
))
1452 imm_expr
->X_add_number
=
1453 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1459 case 'D': /* Floating-point RS2 x8-x15. */
1460 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1461 || !(regno
>= 8 && regno
<= 15))
1463 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1465 case 'T': /* Floating-point RS2. */
1466 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1468 INSERT_OPERAND (CRS2
, *ip
, regno
);
1471 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1490 case '<': /* Shift amount, 0 - 31. */
1491 my_getExpression (imm_expr
, s
);
1492 check_absolute_expr (ip
, imm_expr
);
1493 if ((unsigned long) imm_expr
->X_add_number
> 31)
1494 as_bad (_("Improper shift amount (%lu)"),
1495 (unsigned long) imm_expr
->X_add_number
);
1496 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1497 imm_expr
->X_op
= O_absent
;
1501 case '>': /* Shift amount, 0 - (XLEN-1). */
1502 my_getExpression (imm_expr
, s
);
1503 check_absolute_expr (ip
, imm_expr
);
1504 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1505 as_bad (_("Improper shift amount (%lu)"),
1506 (unsigned long) imm_expr
->X_add_number
);
1507 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1508 imm_expr
->X_op
= O_absent
;
1512 case 'Z': /* CSRRxI immediate. */
1513 my_getExpression (imm_expr
, s
);
1514 check_absolute_expr (ip
, imm_expr
);
1515 if ((unsigned long) imm_expr
->X_add_number
> 31)
1516 as_bad (_("Improper CSRxI immediate (%lu)"),
1517 (unsigned long) imm_expr
->X_add_number
);
1518 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1519 imm_expr
->X_op
= O_absent
;
1523 case 'E': /* Control register. */
1524 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1525 INSERT_OPERAND (CSR
, *ip
, regno
);
1528 my_getExpression (imm_expr
, s
);
1529 check_absolute_expr (ip
, imm_expr
);
1530 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1531 as_bad (_("Improper CSR address (%lu)"),
1532 (unsigned long) imm_expr
->X_add_number
);
1533 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1534 imm_expr
->X_op
= O_absent
;
1539 case 'm': /* Rounding mode. */
1540 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1542 INSERT_OPERAND (RM
, *ip
, regno
);
1548 case 'Q': /* Fence predecessor/successor. */
1549 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1553 INSERT_OPERAND (PRED
, *ip
, regno
);
1555 INSERT_OPERAND (SUCC
, *ip
, regno
);
1560 case 'd': /* Destination register. */
1561 case 's': /* Source register. */
1562 case 't': /* Target register. */
1563 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1569 /* Now that we have assembled one operand, we use the args
1570 string to figure out where it goes in the instruction. */
1574 INSERT_OPERAND (RS1
, *ip
, regno
);
1577 INSERT_OPERAND (RD
, *ip
, regno
);
1580 INSERT_OPERAND (RS2
, *ip
, regno
);
1587 case 'D': /* Floating point rd. */
1588 case 'S': /* Floating point rs1. */
1589 case 'T': /* Floating point rs2. */
1590 case 'U': /* Floating point rs1 and rs2. */
1591 case 'R': /* Floating point rs3. */
1592 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1600 INSERT_OPERAND (RD
, *ip
, regno
);
1603 INSERT_OPERAND (RS1
, *ip
, regno
);
1606 INSERT_OPERAND (RS1
, *ip
, regno
);
1609 INSERT_OPERAND (RS2
, *ip
, regno
);
1612 INSERT_OPERAND (RS3
, *ip
, regno
);
1621 my_getExpression (imm_expr
, s
);
1622 if (imm_expr
->X_op
!= O_big
1623 && imm_expr
->X_op
!= O_constant
)
1625 normalize_constant_expr (imm_expr
);
1630 my_getExpression (imm_expr
, s
);
1631 normalize_constant_expr (imm_expr
);
1632 /* The 'A' format specifier must be a symbol. */
1633 if (imm_expr
->X_op
!= O_symbol
)
1635 *imm_reloc
= BFD_RELOC_32
;
1639 case 'j': /* Sign-extended immediate. */
1640 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1641 p
= percent_op_itype
;
1643 case 'q': /* Store displacement. */
1644 p
= percent_op_stype
;
1645 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1647 case 'o': /* Load displacement. */
1648 p
= percent_op_itype
;
1649 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1651 case '0': /* AMO "displacement," which must be zero. */
1652 p
= percent_op_rtype
;
1653 *imm_reloc
= BFD_RELOC_UNUSED
;
1655 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1658 /* If this value won't fit into a 16 bit offset, then go
1659 find a macro that will generate the 32 bit offset
1661 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1663 normalize_constant_expr (imm_expr
);
1664 if (imm_expr
->X_op
!= O_constant
1665 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1666 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1667 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1674 case 'p': /* PC-relative offset. */
1676 *imm_reloc
= BFD_RELOC_12_PCREL
;
1677 my_getExpression (imm_expr
, s
);
1681 case 'u': /* Upper 20 bits. */
1682 p
= percent_op_utype
;
1683 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1684 && imm_expr
->X_op
== O_constant
)
1686 if (imm_expr
->X_add_number
< 0
1687 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1688 as_bad (_("lui expression not in range 0..1048575"));
1690 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1691 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1696 case 'a': /* 20-bit PC-relative offset. */
1698 my_getExpression (imm_expr
, s
);
1700 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1704 my_getExpression (imm_expr
, s
);
1706 if (strcmp (s
, "@plt") == 0)
1708 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1712 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1716 as_fatal (_("internal error: bad argument type %c"), *args
);
1721 error
= _("illegal operands");
1725 /* Restore the character we might have clobbered above. */
1727 *(argsStart
- 1) = save_c
;
1733 md_assemble (char *str
)
1735 struct riscv_cl_insn insn
;
1736 expressionS imm_expr
;
1737 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
1739 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
);
1743 as_bad ("%s `%s'", error
, str
);
1747 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1748 macro (&insn
, &imm_expr
, &imm_reloc
);
1750 append_insn (&insn
, &imm_expr
, imm_reloc
);
1754 md_atof (int type
, char *litP
, int *sizeP
)
1756 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
1760 md_number_to_chars (char *buf
, valueT val
, int n
)
1762 number_to_chars_littleendian (buf
, val
, n
);
1765 const char *md_shortopts
= "O::g::G:";
1769 OPTION_MARCH
= OPTION_MD_BASE
,
1776 struct option md_longopts
[] =
1778 {"march", required_argument
, NULL
, OPTION_MARCH
},
1779 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
1780 {"fpic", no_argument
, NULL
, OPTION_PIC
},
1781 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
1782 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1784 {NULL
, no_argument
, NULL
, 0}
1786 size_t md_longopts_size
= sizeof (md_longopts
);
1789 FLOAT_ABI_DEFAULT
= -1,
1795 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
1798 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
)
1800 abi_xlen
= new_xlen
;
1801 float_abi
= new_float_abi
;
1805 md_parse_option (int c
, const char *arg
)
1810 riscv_set_arch (arg
);
1814 riscv_opts
.pic
= FALSE
;
1818 riscv_opts
.pic
= TRUE
;
1822 if (strcmp (arg
, "ilp32") == 0)
1823 riscv_set_abi (32, FLOAT_ABI_SOFT
);
1824 else if (strcmp (arg
, "ilp32f") == 0)
1825 riscv_set_abi (32, FLOAT_ABI_SINGLE
);
1826 else if (strcmp (arg
, "ilp32d") == 0)
1827 riscv_set_abi (32, FLOAT_ABI_DOUBLE
);
1828 else if (strcmp (arg
, "ilp32q") == 0)
1829 riscv_set_abi (32, FLOAT_ABI_QUAD
);
1830 else if (strcmp (arg
, "lp64") == 0)
1831 riscv_set_abi (64, FLOAT_ABI_SOFT
);
1832 else if (strcmp (arg
, "lp64f") == 0)
1833 riscv_set_abi (64, FLOAT_ABI_SINGLE
);
1834 else if (strcmp (arg
, "lp64d") == 0)
1835 riscv_set_abi (64, FLOAT_ABI_DOUBLE
);
1836 else if (strcmp (arg
, "lp64q") == 0)
1837 riscv_set_abi (64, FLOAT_ABI_QUAD
);
1850 riscv_after_parse_args (void)
1854 if (strcmp (default_arch
, "riscv32") == 0)
1856 else if (strcmp (default_arch
, "riscv64") == 0)
1859 as_bad ("unknown default architecture `%s'", default_arch
);
1862 if (riscv_subsets
== NULL
)
1863 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
1865 /* Add the RVC extension, regardless of -march, to support .option rvc. */
1866 riscv_set_rvc (FALSE
);
1867 if (riscv_subset_supports ("c"))
1868 riscv_set_rvc (TRUE
);
1870 riscv_add_subset ("c");
1872 /* Infer ABI from ISA if not specified on command line. */
1875 else if (abi_xlen
> xlen
)
1876 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
1877 else if (abi_xlen
< xlen
)
1878 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
1880 if (float_abi
== FLOAT_ABI_DEFAULT
)
1882 struct riscv_subset
*subset
;
1884 /* Assume soft-float unless D extension is present. */
1885 float_abi
= FLOAT_ABI_SOFT
;
1887 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
1889 if (strcasecmp (subset
->name
, "D") == 0)
1890 float_abi
= FLOAT_ABI_DOUBLE
;
1891 if (strcasecmp (subset
->name
, "Q") == 0)
1892 float_abi
= FLOAT_ABI_QUAD
;
1896 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
1897 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
1901 md_pcrel_from (fixS
*fixP
)
1903 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1906 /* Apply a fixup to the object file. */
1909 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1911 unsigned int subtype
;
1912 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
1913 bfd_boolean relaxable
= FALSE
;
1917 /* Remember value for tc_gen_reloc. */
1918 fixP
->fx_addnumber
= *valP
;
1920 switch (fixP
->fx_r_type
)
1922 case BFD_RELOC_RISCV_HI20
:
1923 case BFD_RELOC_RISCV_LO12_I
:
1924 case BFD_RELOC_RISCV_LO12_S
:
1925 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
1926 | bfd_getl32 (buf
), buf
);
1927 if (fixP
->fx_addsy
== NULL
)
1928 fixP
->fx_done
= TRUE
;
1932 case BFD_RELOC_RISCV_GOT_HI20
:
1933 case BFD_RELOC_RISCV_ADD8
:
1934 case BFD_RELOC_RISCV_ADD16
:
1935 case BFD_RELOC_RISCV_ADD32
:
1936 case BFD_RELOC_RISCV_ADD64
:
1937 case BFD_RELOC_RISCV_SUB6
:
1938 case BFD_RELOC_RISCV_SUB8
:
1939 case BFD_RELOC_RISCV_SUB16
:
1940 case BFD_RELOC_RISCV_SUB32
:
1941 case BFD_RELOC_RISCV_SUB64
:
1942 case BFD_RELOC_RISCV_RELAX
:
1945 case BFD_RELOC_RISCV_TPREL_HI20
:
1946 case BFD_RELOC_RISCV_TPREL_LO12_I
:
1947 case BFD_RELOC_RISCV_TPREL_LO12_S
:
1948 case BFD_RELOC_RISCV_TPREL_ADD
:
1952 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
1953 case BFD_RELOC_RISCV_TLS_GD_HI20
:
1954 case BFD_RELOC_RISCV_TLS_DTPREL32
:
1955 case BFD_RELOC_RISCV_TLS_DTPREL64
:
1956 if (fixP
->fx_addsy
!= NULL
)
1957 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
1959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1960 _("TLS relocation against a constant"));
1964 /* Use pc-relative relocation for FDE initial location.
1965 The symbol address in .eh_frame may be adjusted in
1966 _bfd_elf_discard_section_eh_frame, and the content of
1967 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
1968 Therefore, we cannot insert a relocation whose addend symbol is
1969 in .eh_frame. Othrewise, the value may be adjusted twice.*/
1970 if (fixP
->fx_addsy
&& fixP
->fx_subsy
1971 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
1972 && strcmp (sub_segment
->name
, ".eh_frame") == 0
1973 && S_GET_VALUE (fixP
->fx_subsy
)
1974 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
1976 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
1977 fixP
->fx_subsy
= NULL
;
1984 case BFD_RELOC_RISCV_CFA
:
1985 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
1987 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
1988 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
1989 fixP
->fx_next
->fx_subsy
= NULL
;
1990 fixP
->fx_next
->fx_offset
= 0;
1991 fixP
->fx_subsy
= NULL
;
1993 switch (fixP
->fx_r_type
)
1996 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
1997 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2001 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2002 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2006 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2007 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2011 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2012 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2015 case BFD_RELOC_RISCV_CFA
:
2016 /* Load the byte to get the subtype. */
2017 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2018 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2021 case DW_CFA_advance_loc1
:
2022 fixP
->fx_where
= loc
+ 1;
2023 fixP
->fx_next
->fx_where
= loc
+ 1;
2024 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2025 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2028 case DW_CFA_advance_loc2
:
2030 fixP
->fx_next
->fx_size
= 2;
2031 fixP
->fx_where
= loc
+ 1;
2032 fixP
->fx_next
->fx_where
= loc
+ 1;
2033 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2034 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2037 case DW_CFA_advance_loc4
:
2039 fixP
->fx_next
->fx_size
= 4;
2040 fixP
->fx_where
= loc
;
2041 fixP
->fx_next
->fx_where
= loc
;
2042 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2043 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2047 if (subtype
< 0x80 && (subtype
& 0x40))
2049 /* DW_CFA_advance_loc */
2050 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2051 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2052 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2053 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2056 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2062 /* This case is unreachable. */
2069 /* If we are deleting this reloc entry, we must fill in the
2070 value now. This can happen if we have a .word which is not
2071 resolved when it appears but is later defined. */
2072 if (fixP
->fx_addsy
== NULL
)
2074 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2075 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2080 case BFD_RELOC_RISCV_JMP
:
2083 /* Fill in a tentative value to improve objdump readability. */
2084 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2085 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2086 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2090 case BFD_RELOC_12_PCREL
:
2093 /* Fill in a tentative value to improve objdump readability. */
2094 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2095 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2096 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2100 case BFD_RELOC_RISCV_RVC_BRANCH
:
2103 /* Fill in a tentative value to improve objdump readability. */
2104 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2105 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2106 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2110 case BFD_RELOC_RISCV_RVC_JUMP
:
2113 /* Fill in a tentative value to improve objdump readability. */
2114 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2115 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2116 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2120 case BFD_RELOC_RISCV_CALL
:
2121 case BFD_RELOC_RISCV_CALL_PLT
:
2125 case BFD_RELOC_RISCV_PCREL_HI20
:
2126 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2127 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2128 relaxable
= riscv_opts
.relax
;
2131 case BFD_RELOC_RISCV_ALIGN
:
2135 /* We ignore generic BFD relocations we don't know about. */
2136 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2137 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2140 if (fixP
->fx_subsy
!= NULL
)
2141 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2142 _("unsupported symbol subtraction"));
2144 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2145 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2147 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2148 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2149 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2153 /* Because the value of .cfi_remember_state may changed after relaxation,
2154 we insert a fix to relocate it again in link-time. */
2157 riscv_pre_output_hook (void)
2159 const frchainS
*frch
;
2162 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2163 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2167 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2169 if (frag
->fr_type
== rs_cfa
)
2173 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2174 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2176 exp
.X_op
= O_subtract
;
2177 exp
.X_add_symbol
= add_symbol
;
2178 exp
.X_add_number
= 0;
2179 exp
.X_op_symbol
= op_symbol
;
2181 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2182 BFD_RELOC_RISCV_CFA
);
2189 /* This structure is used to hold a stack of .option values. */
2191 struct riscv_option_stack
2193 struct riscv_option_stack
*next
;
2194 struct riscv_set_options options
;
2197 static struct riscv_option_stack
*riscv_opts_stack
;
2199 /* Handle the .option pseudo-op. */
2202 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2204 char *name
= input_line_pointer
, ch
;
2206 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2207 ++input_line_pointer
;
2208 ch
= *input_line_pointer
;
2209 *input_line_pointer
= '\0';
2211 if (strcmp (name
, "rvc") == 0)
2212 riscv_set_rvc (TRUE
);
2213 else if (strcmp (name
, "norvc") == 0)
2214 riscv_set_rvc (FALSE
);
2215 else if (strcmp (name
, "pic") == 0)
2216 riscv_opts
.pic
= TRUE
;
2217 else if (strcmp (name
, "nopic") == 0)
2218 riscv_opts
.pic
= FALSE
;
2219 else if (strcmp (name
, "relax") == 0)
2220 riscv_opts
.relax
= TRUE
;
2221 else if (strcmp (name
, "norelax") == 0)
2222 riscv_opts
.relax
= FALSE
;
2223 else if (strcmp (name
, "push") == 0)
2225 struct riscv_option_stack
*s
;
2227 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2228 s
->next
= riscv_opts_stack
;
2229 s
->options
= riscv_opts
;
2230 riscv_opts_stack
= s
;
2232 else if (strcmp (name
, "pop") == 0)
2234 struct riscv_option_stack
*s
;
2236 s
= riscv_opts_stack
;
2238 as_bad (_(".option pop with no .option push"));
2241 riscv_opts
= s
->options
;
2242 riscv_opts_stack
= s
->next
;
2248 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2250 *input_line_pointer
= ch
;
2251 demand_empty_rest_of_line ();
2254 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2255 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2256 use in DWARF debug information. */
2259 s_dtprel (int bytes
)
2266 if (ex
.X_op
!= O_symbol
)
2268 as_bad (_("Unsupported use of %s"), (bytes
== 8
2271 ignore_rest_of_line ();
2274 p
= frag_more (bytes
);
2275 md_number_to_chars (p
, 0, bytes
);
2276 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2278 ? BFD_RELOC_RISCV_TLS_DTPREL64
2279 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2281 demand_empty_rest_of_line ();
2284 /* Handle the .bss pseudo-op. */
2287 s_bss (int ignore ATTRIBUTE_UNUSED
)
2289 subseg_set (bss_section
, 0);
2290 demand_empty_rest_of_line ();
2294 riscv_make_nops (char *buf
, bfd_vma bytes
)
2298 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2299 means we are not within a valid instruction sequence. It is thus safe
2300 to use a zero byte, even though that is not a valid instruction. */
2304 /* Use at most one 2-byte NOP. */
2305 if ((bytes
- i
) % 4 == 2)
2307 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2311 /* Fill the remainder with 4-byte NOPs. */
2312 for ( ; i
< bytes
; i
+= 4)
2313 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2316 /* Called from md_do_align. Used to create an alignment frag in a
2317 code section by emitting a worst-case NOP sequence that the linker
2318 will later relax to the correct number of NOPs. We can't compute
2319 the correct alignment now because of other linker relaxations. */
2322 riscv_frag_align_code (int n
)
2324 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2325 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2326 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2330 /* If we are moving to a smaller alignment than the instruction size, then no
2331 alignment is required. */
2332 if (bytes
<= insn_alignment
)
2335 nops
= frag_more (worst_case_bytes
);
2337 /* When not relaxing, riscv_handle_align handles code alignment. */
2338 if (!riscv_opts
.relax
)
2341 ex
.X_op
= O_constant
;
2342 ex
.X_add_number
= worst_case_bytes
;
2344 riscv_make_nops (nops
, worst_case_bytes
);
2346 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2347 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2352 /* Implement HANDLE_ALIGN. */
2355 riscv_handle_align (fragS
*fragP
)
2357 switch (fragP
->fr_type
)
2360 /* When relaxing, riscv_frag_align_code handles code alignment. */
2361 if (!riscv_opts
.relax
)
2363 bfd_signed_vma count
= fragP
->fr_next
->fr_address
2364 - fragP
->fr_address
- fragP
->fr_fix
;
2369 count
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
2370 riscv_make_nops (fragP
->fr_literal
+ fragP
->fr_fix
, count
);
2371 fragP
->fr_var
= count
;
2381 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2383 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2386 /* Translate internal representation of relocation info to BFD target
2390 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2392 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2394 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2395 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2396 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2397 reloc
->addend
= fixp
->fx_addnumber
;
2399 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2400 if (reloc
->howto
== NULL
)
2402 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2403 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2405 /* We don't have R_RISCV_8/16, but for this special case,
2406 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2410 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2411 _("cannot represent %s relocation in object file"),
2412 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2420 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2422 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2424 offsetT old_var
= fragp
->fr_var
;
2425 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2426 return fragp
->fr_var
- old_var
;
2432 /* Expand far branches to multi-instruction sequences. */
2435 md_convert_frag_branch (fragS
*fragp
)
2443 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2445 exp
.X_op
= O_symbol
;
2446 exp
.X_add_symbol
= fragp
->fr_symbol
;
2447 exp
.X_add_number
= fragp
->fr_offset
;
2449 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2451 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2453 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2457 /* Expand the RVC branch into a RISC-V one. */
2458 insn
= bfd_getl16 (buf
);
2459 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2460 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2462 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2463 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2464 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2465 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2466 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2467 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2470 bfd_putl32 (insn
, buf
);
2474 /* Invert the branch condition. Branch over the jump. */
2475 insn
= bfd_getl16 (buf
);
2476 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2477 insn
|= ENCODE_RVC_B_IMM (6);
2478 bfd_putl16 (insn
, buf
);
2483 /* Just keep the RVC branch. */
2484 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2485 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2486 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2487 2, &exp
, FALSE
, reloc
);
2496 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2499 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2501 /* Invert the branch condition. Branch over the jump. */
2502 insn
= bfd_getl32 (buf
);
2503 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2504 insn
|= ENCODE_SBTYPE_IMM (8);
2505 md_number_to_chars ((char *) buf
, insn
, 4);
2509 /* Jump to the target. */
2510 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2511 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2512 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2517 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2518 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2519 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2520 4, &exp
, FALSE
, reloc
);
2529 fixp
->fx_file
= fragp
->fr_file
;
2530 fixp
->fx_line
= fragp
->fr_line
;
2532 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2533 + fragp
->fr_fix
+ fragp
->fr_var
);
2535 fragp
->fr_fix
+= fragp
->fr_var
;
2538 /* Relax a machine dependent frag. This returns the amount by which
2539 the current size of the frag should change. */
2542 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2545 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2546 md_convert_frag_branch (fragp
);
2550 md_show_usage (FILE *stream
)
2552 fprintf (stream
, _("\
2554 -fpic generate position-independent code\n\
2555 -fno-pic don't generate position-independent code (default)\n\
2556 -march=ISA set the RISC-V architecture\n\
2557 -mabi=ABI set the RISC-V ABI\n\
2561 /* Standard calling conventions leave the CFA at SP on entry. */
2563 riscv_cfi_frame_initial_instructions (void)
2565 cfi_add_CFA_def_cfa_register (X_SP
);
2569 tc_riscv_regname_to_dw2regnum (char *regname
)
2573 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2576 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2579 as_bad (_("unknown register `%s'"), regname
);
2584 riscv_elf_final_processing (void)
2586 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2589 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2590 since these directives break relaxation when used with symbol deltas. */
2593 s_riscv_leb128 (int sign
)
2596 char *save_in
= input_line_pointer
;
2599 if (exp
.X_op
!= O_constant
)
2600 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2601 demand_empty_rest_of_line ();
2603 input_line_pointer
= save_in
;
2604 return s_leb128 (sign
);
2607 /* Pseudo-op table. */
2609 static const pseudo_typeS riscv_pseudo_table
[] =
2611 /* RISC-V-specific pseudo-ops. */
2612 {"option", s_riscv_option
, 0},
2616 {"dtprelword", s_dtprel
, 4},
2617 {"dtpreldword", s_dtprel
, 8},
2619 {"uleb128", s_riscv_leb128
, 0},
2620 {"sleb128", s_riscv_leb128
, 1},
2626 riscv_pop_insert (void)
2628 extern void pop_insert (const pseudo_typeS
*);
2630 pop_insert (riscv_pseudo_table
);