1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "elf/riscv.h"
33 #include "opcode/riscv.h"
37 /* Information about an instruction, including its format, operands
41 /* The opcode's entry in riscv_opcodes. */
42 const struct riscv_opcode
*insn_mo
;
44 /* The encoded instruction bits. */
47 /* The frag that contains the instruction. */
50 /* The offset into FRAG of the first instruction byte. */
53 /* The relocs associated with the instruction, if any. */
58 #define DEFAULT_ARCH "riscv64"
61 static const char default_arch
[] = DEFAULT_ARCH
;
63 static unsigned xlen
= 0; /* width of an x-register */
64 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
65 static bfd_boolean rve_abi
= FALSE
;
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int rve
; /* Generate RVE code. */
79 int relax
; /* Emit relocs the linker is allowed to relax. */
82 static struct riscv_set_options riscv_opts
=
91 riscv_set_rvc (bfd_boolean rvc_value
)
94 elf_flags
|= EF_RISCV_RVC
;
96 riscv_opts
.rvc
= rvc_value
;
100 riscv_set_rve (bfd_boolean rve_value
)
102 riscv_opts
.rve
= rve_value
;
109 struct riscv_subset
*next
;
112 static struct riscv_subset
*riscv_subsets
;
115 riscv_subset_supports (unsigned xlen_required
, const char *feature
)
117 struct riscv_subset
*s
;
119 if (xlen_required
&& xlen
!= xlen_required
)
122 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
123 if (strcasecmp (s
->name
, feature
) == 0)
130 riscv_multi_subset_supports (unsigned xlen_required
, const char *features
[])
133 bfd_boolean supported
= TRUE
;
135 for (;features
[i
]; ++i
)
136 supported
= supported
&& riscv_subset_supports (xlen_required
, features
[i
]);
142 riscv_clear_subsets (void)
144 while (riscv_subsets
!= NULL
)
146 struct riscv_subset
*next
= riscv_subsets
->next
;
147 free ((void *) riscv_subsets
->name
);
148 free (riscv_subsets
);
149 riscv_subsets
= next
;
154 riscv_add_subset (const char *subset
)
156 struct riscv_subset
*s
= xmalloc (sizeof *s
);
158 s
->name
= xstrdup (subset
);
159 s
->next
= riscv_subsets
;
163 /* Set which ISA and extensions are available. */
166 riscv_set_arch (const char *s
)
168 const char *all_subsets
= "imafdqc";
169 char *extension
= NULL
;
172 riscv_clear_subsets();
174 if (strncmp (p
, "rv32", 4) == 0)
179 else if (strncmp (p
, "rv64", 4) == 0)
185 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
194 riscv_add_subset ("e");
195 riscv_add_subset ("i");
198 as_fatal ("-march=%s: rv%de is not a valid base ISA", s
, xlen
);
204 for ( ; *all_subsets
!= 'q'; all_subsets
++)
206 const char subset
[] = {*all_subsets
, '\0'};
207 riscv_add_subset (subset
);
212 as_fatal ("-march=%s: first ISA subset must be `e', `i' or `g'", s
);
219 char *subset
= xstrdup (p
);
222 while (*++q
!= '\0' && *q
!= '_')
227 as_fatal ("-march=%s: only one non-standard extension is supported"
228 " (found `%s' and `%s')", s
, extension
, subset
);
230 riscv_add_subset (subset
);
231 p
+= strlen (subset
);
235 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
237 const char subset
[] = {*p
, 0};
238 riscv_add_subset (subset
);
243 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
246 if (riscv_subset_supports (0, "e") && riscv_subset_supports (0, "f"))
247 as_fatal ("-march=%s: rv32e does not support the `f' extension", s
);
249 if (riscv_subset_supports (0, "d") && !riscv_subset_supports (0, "f"))
250 as_fatal ("-march=%s: `d' extension requires `f' extension", s
);
252 if (riscv_subset_supports (0, "q") && !riscv_subset_supports (0, "d"))
253 as_fatal ("-march=%s: `q' extension requires `d' extension", s
);
255 if (riscv_subset_supports (0, "q") && xlen
< 64)
256 as_fatal ("-march=%s: rv32 does not support the `q' extension", s
);
261 /* Handle of the OPCODE hash table. */
262 static struct hash_control
*op_hash
= NULL
;
264 /* Handle of the type of .insn hash table. */
265 static struct hash_control
*insn_type_hash
= NULL
;
267 /* This array holds the chars that always start a comment. If the
268 pre-processor is disabled, these aren't very useful */
269 const char comment_chars
[] = "#";
271 /* This array holds the chars that only start a comment at the beginning of
272 a line. If the line seems to have the form '# 123 filename'
273 .line and .file directives will appear in the pre-processed output */
274 /* Note that input_file.c hand checks for '#' at the beginning of the
275 first line of the input file. This is because the compiler outputs
276 #NO_APP at the beginning of its output. */
277 /* Also note that C style comments are always supported. */
278 const char line_comment_chars
[] = "#";
280 /* This array holds machine specific line separator characters. */
281 const char line_separator_chars
[] = ";";
283 /* Chars that can be used to separate mant from exp in floating point nums */
284 const char EXP_CHARS
[] = "eE";
286 /* Chars that mean this number is a floating point constant */
289 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
291 /* Macros for encoding relaxation state for RVC branches and far jumps. */
292 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
295 | ((uncond) ? 1 : 0) \
298 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
299 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
300 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
301 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
303 /* Is the given value a sign-extended 32-bit value? */
304 #define IS_SEXT_32BIT_NUM(x) \
305 (((x) &~ (offsetT) 0x7fffffff) == 0 \
306 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
308 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
309 #define IS_ZEXT_32BIT_NUM(x) \
310 (((x) &~ (offsetT) 0xffffffff) == 0 \
311 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
313 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
314 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
315 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
316 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
318 /* Determine if an instruction matches an opcode. */
319 #define OPCODE_MATCHES(OPCODE, OP) \
320 (((OPCODE) & MASK_##OP) == MATCH_##OP)
322 static char *expr_end
;
324 /* The default target format to use. */
327 riscv_target_format (void)
329 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
332 /* Return the length of instruction INSN. */
334 static inline unsigned int
335 insn_length (const struct riscv_cl_insn
*insn
)
337 return riscv_insn_length (insn
->insn_opcode
);
340 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
343 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
346 insn
->insn_opcode
= mo
->match
;
352 /* Install INSN at the location specified by its "frag" and "where" fields. */
355 install_insn (const struct riscv_cl_insn
*insn
)
357 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
358 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
361 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
362 and install the opcode in the new location. */
365 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
369 if (insn
->fixp
!= NULL
)
371 insn
->fixp
->fx_frag
= frag
;
372 insn
->fixp
->fx_where
= where
;
377 /* Add INSN to the end of the output. */
380 add_fixed_insn (struct riscv_cl_insn
*insn
)
382 char *f
= frag_more (insn_length (insn
));
383 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
387 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
388 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
390 frag_grow (max_chars
);
391 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
392 frag_var (rs_machine_dependent
, max_chars
, var
,
393 subtype
, symbol
, offset
, NULL
);
396 /* Compute the length of a branch sequence, and adjust the stored length
397 accordingly. If FRAGP is NULL, the worst-case length is returned. */
400 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
402 int jump
, rvc
, length
= 8;
407 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
408 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
409 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
411 /* Assume jumps are in range; the linker will catch any that aren't. */
412 length
= jump
? 4 : 8;
414 if (fragp
->fr_symbol
!= NULL
415 && S_IS_DEFINED (fragp
->fr_symbol
)
416 && !S_IS_WEAK (fragp
->fr_symbol
)
417 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
419 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
420 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
421 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
423 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
425 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
427 else if (!jump
&& rvc
)
432 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
437 /* Information about an opcode name, mnemonics and its value. */
444 /* List for all supported opcode name. */
445 static const struct opcode_name_t opcode_name_list
[] =
490 /* Hash table for lookup opcode name. */
491 static struct hash_control
*opcode_names_hash
= NULL
;
493 /* Initialization for hash table of opcode name. */
495 init_opcode_names_hash (void)
498 const struct opcode_name_t
*opcode
;
500 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
502 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
505 as_fatal (_("internal error: can't hash `%s': %s"),
506 opcode
->name
, retval
);
510 /* Find `s` is a valid opcode name or not,
511 return the opcode name info if found. */
512 static const struct opcode_name_t
*
513 opcode_name_lookup (char **s
)
517 struct opcode_name_t
*o
;
519 /* Find end of name. */
521 if (is_name_beginner (*e
))
523 while (is_part_of_name (*e
))
526 /* Terminate name. */
530 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
532 /* Advance to next token if one was recognized. */
556 static struct hash_control
*reg_names_hash
= NULL
;
558 #define ENCODE_REG_HASH(cls, n) \
559 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
560 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
561 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
564 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
566 void *hash
= ENCODE_REG_HASH (class, n
);
567 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
570 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
574 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
578 for (i
= 0; i
< n
; i
++)
579 hash_reg_name (class, names
[i
], i
);
583 reg_lookup_internal (const char *s
, enum reg_class
class)
585 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
587 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
590 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
593 return DECODE_REG_NUM (r
);
597 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
603 /* Find end of name. */
605 if (is_name_beginner (*e
))
607 while (is_part_of_name (*e
))
610 /* Terminate name. */
614 /* Look for the register. Advance to next token if one was recognized. */
615 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
625 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
627 const char *p
= strchr (*s
, ',');
628 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
633 for (i
= 0; i
< size
; i
++)
634 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
644 /* For consistency checking, verify that all bits are specified either
645 by the match/mask part of the instruction definition, or by the
648 `length` could be 0, 4 or 8, 0 for auto detection. */
650 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
652 const char *p
= opc
->args
;
654 insn_t used_bits
= opc
->mask
;
656 insn_t required_bits
;
659 insn_width
= 8 * riscv_insn_length (opc
->match
);
661 insn_width
= 8 * length
;
663 required_bits
= ~0ULL >> (64 - insn_width
);
665 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
667 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
668 opc
->name
, opc
->args
);
672 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
679 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
680 case 'c': break; /* RS1, constrained to equal sp */
681 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
682 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
683 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
684 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
685 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
686 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
687 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
688 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
689 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
690 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
691 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
692 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
693 case 'w': break; /* RS1S, constrained to equal RD */
694 case 'x': break; /* RS2S, constrained to equal RD */
695 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
696 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
697 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
698 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
699 case 'U': break; /* RS1, constrained to equal RD */
700 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
701 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
702 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
703 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
704 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
705 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
706 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
707 case 'F': /* funct */
710 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
711 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
712 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
713 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
715 as_bad (_("internal: bad RISC-V opcode"
716 " (unknown operand type `CF%c'): %s %s"),
717 c
, opc
->name
, opc
->args
);
722 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
723 c
, opc
->name
, opc
->args
);
730 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
731 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
733 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
734 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
735 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
737 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
738 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
739 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
740 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
741 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
742 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
743 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
744 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
745 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
746 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
747 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
749 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
750 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
751 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
752 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
753 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
758 case 'F': /* funct */
761 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
762 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
763 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
765 as_bad (_("internal: bad RISC-V opcode"
766 " (unknown operand type `F%c'): %s %s"),
767 c
, opc
->name
, opc
->args
);
771 case 'O': /* opcode */
774 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
775 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
777 as_bad (_("internal: bad RISC-V opcode"
778 " (unknown operand type `F%c'): %s %s"),
779 c
, opc
->name
, opc
->args
);
784 as_bad (_("internal: bad RISC-V opcode "
785 "(unknown operand type `%c'): %s %s"),
786 c
, opc
->name
, opc
->args
);
790 if (used_bits
!= required_bits
)
792 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
793 ~(unsigned long)(used_bits
& required_bits
),
794 opc
->name
, opc
->args
);
800 struct percent_op_match
803 bfd_reloc_code_real_type reloc
;
806 /* Common hash table initialization function for
807 instruction and .insn directive. */
808 static struct hash_control
*
809 init_opcode_hash (const struct riscv_opcode
*opcodes
,
810 bfd_boolean insn_directive_p
)
814 struct hash_control
*hash
= hash_new ();
815 while (opcodes
[i
].name
)
817 const char *name
= opcodes
[i
].name
;
818 const char *hash_error
=
819 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
823 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
824 opcodes
[i
].name
, hash_error
);
825 /* Probably a memory allocation problem? Give up now. */
826 as_fatal (_("Broken assembler. No assembly attempted."));
831 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
833 if (insn_directive_p
)
834 length
= ((name
[0] == 'c') ? 2 : 4);
836 length
= 0; /* Let assembler determine the length. */
837 if (!validate_riscv_insn (&opcodes
[i
], length
))
838 as_fatal (_("Broken assembler. No assembly attempted."));
841 gas_assert (!insn_directive_p
);
844 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
850 /* This function is called once, at assembler startup time. It should set up
851 all the tables, etc. that the MD part of the assembler will need. */
856 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
858 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
859 as_warn (_("Could not set architecture and machine"));
861 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
862 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
864 reg_names_hash
= hash_new ();
865 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
866 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
867 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
868 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
870 /* Add "fp" as an alias for "s0". */
871 hash_reg_name (RCLASS_GPR
, "fp", 8);
873 opcode_names_hash
= hash_new ();
874 init_opcode_names_hash ();
876 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
877 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
878 #include "opcode/riscv-opc.h"
881 /* Set the default alignment for the text section. */
882 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
886 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
893 case BFD_RELOC_RISCV_HI20
:
894 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
896 case BFD_RELOC_RISCV_LO12_S
:
897 return ENCODE_STYPE_IMM (value
);
899 case BFD_RELOC_RISCV_LO12_I
:
900 return ENCODE_ITYPE_IMM (value
);
907 /* Output an instruction. IP is the instruction information.
908 ADDRESS_EXPR is an operand of the instruction to be used with
912 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
913 bfd_reloc_code_real_type reloc_type
)
915 dwarf2_emit_insn (0);
917 if (reloc_type
!= BFD_RELOC_UNUSED
)
919 reloc_howto_type
*howto
;
921 gas_assert (address_expr
);
922 if (reloc_type
== BFD_RELOC_12_PCREL
923 || reloc_type
== BFD_RELOC_RISCV_JMP
)
925 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
926 int best_case
= riscv_insn_length (ip
->insn_opcode
);
927 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
928 add_relaxed_insn (ip
, worst_case
, best_case
,
929 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
930 address_expr
->X_add_symbol
,
931 address_expr
->X_add_number
);
936 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
938 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
940 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
941 bfd_get_reloc_size (howto
),
942 address_expr
, FALSE
, reloc_type
);
944 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
951 /* We need to start a new frag after any instruction that can be
952 optimized away or compressed by the linker during relaxation, to prevent
953 the assembler from computing static offsets across such an instruction.
954 This is necessary to get correct EH info. */
955 if (reloc_type
== BFD_RELOC_RISCV_CALL
956 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
957 || reloc_type
== BFD_RELOC_RISCV_HI20
958 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
959 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
960 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
962 frag_wane (frag_now
);
967 /* Build an instruction created by a macro expansion. This is passed
968 a pointer to the count of instructions created so far, an
969 expression, the name of the instruction to build, an operand format
970 string, and corresponding arguments. */
973 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
975 const struct riscv_opcode
*mo
;
976 struct riscv_cl_insn insn
;
977 bfd_reloc_code_real_type r
;
980 va_start (args
, fmt
);
982 r
= BFD_RELOC_UNUSED
;
983 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
986 /* Find a non-RVC variant of the instruction. append_insn will compress
988 while (riscv_insn_length (mo
->match
) < 4)
990 gas_assert (strcmp (name
, mo
->name
) == 0);
992 create_insn (&insn
, mo
);
998 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1002 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1006 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1010 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1016 gas_assert (ep
!= NULL
);
1017 r
= va_arg (args
, int);
1025 as_fatal (_("internal error: invalid macro"));
1030 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1032 append_insn (&insn
, ep
, r
);
1035 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1038 normalize_constant_expr (expressionS
*ex
)
1042 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1043 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1044 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1048 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1049 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1052 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1053 bfd_boolean maybe_csr
)
1055 if (ex
->X_op
== O_big
)
1056 as_bad (_("unsupported large constant"));
1057 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1058 as_bad (_("unknown CSR `%s'"),
1059 S_GET_NAME (ex
->X_add_symbol
));
1060 else if (ex
->X_op
!= O_constant
)
1061 as_bad (_("Instruction %s requires absolute expression"),
1063 normalize_constant_expr (ex
);
1067 make_internal_label (void)
1069 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1070 (valueT
) frag_now_fix (), frag_now
);
1073 /* Load an entry from the GOT. */
1075 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1076 const char *lo_insn
, const char *lo_pattern
,
1077 bfd_reloc_code_real_type hi_reloc
,
1078 bfd_reloc_code_real_type lo_reloc
)
1081 ep2
.X_op
= O_symbol
;
1082 ep2
.X_add_symbol
= make_internal_label ();
1083 ep2
.X_add_number
= 0;
1085 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1086 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1090 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1091 bfd_reloc_code_real_type hi_reloc
,
1092 bfd_reloc_code_real_type lo_reloc
)
1094 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1098 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1099 bfd_reloc_code_real_type hi_reloc
,
1100 bfd_reloc_code_real_type lo_reloc
)
1102 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1105 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1107 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1108 bfd_reloc_code_real_type reloc
)
1110 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1111 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1114 /* Load an integer constant into a register. */
1117 load_const (int reg
, expressionS
*ep
)
1119 int shift
= RISCV_IMM_BITS
;
1120 expressionS upper
= *ep
, lower
= *ep
;
1121 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1122 upper
.X_add_number
-= lower
.X_add_number
;
1124 if (ep
->X_op
!= O_constant
)
1126 as_bad (_("unsupported large constant"));
1130 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1132 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1133 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1136 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1137 load_const (reg
, &upper
);
1139 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
1140 if (lower
.X_add_number
!= 0)
1141 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
1145 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1148 if (upper
.X_add_number
!= 0)
1150 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
1154 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1155 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
1156 BFD_RELOC_RISCV_LO12_I
);
1160 /* Expand RISC-V assembly macros into one or more instructions. */
1162 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1163 bfd_reloc_code_real_type
*imm_reloc
)
1165 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1166 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1167 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1168 int mask
= ip
->insn_mo
->mask
;
1173 load_const (rd
, imm_expr
);
1178 /* Load the address of a symbol into a register. */
1179 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1180 as_bad (_("offset too large"));
1182 if (imm_expr
->X_op
== O_constant
)
1183 load_const (rd
, imm_expr
);
1184 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1185 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1186 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1187 else /* Local PIC symbol, or any non-PIC symbol */
1188 pcrel_load (rd
, rd
, imm_expr
, "addi",
1189 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1193 pcrel_load (rd
, rd
, imm_expr
, "addi",
1194 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1198 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1199 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1203 pcrel_load (rd
, rd
, imm_expr
, "lb",
1204 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1208 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1209 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1213 pcrel_load (rd
, rd
, imm_expr
, "lh",
1214 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1218 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1219 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1223 pcrel_load (rd
, rd
, imm_expr
, "lw",
1224 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1228 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1229 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1233 pcrel_load (rd
, rd
, imm_expr
, "ld",
1234 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1238 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1239 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1243 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1244 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1248 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1249 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1253 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1254 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1258 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1259 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1263 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1264 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1268 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1269 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1273 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1274 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1278 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1282 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1287 static const struct percent_op_match percent_op_utype
[] =
1289 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1290 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1291 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1292 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1293 {"%hi", BFD_RELOC_RISCV_HI20
},
1297 static const struct percent_op_match percent_op_itype
[] =
1299 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1300 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1301 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1305 static const struct percent_op_match percent_op_stype
[] =
1307 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1308 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1309 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1313 static const struct percent_op_match percent_op_rtype
[] =
1315 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1319 /* Return true if *STR points to a relocation operator. When returning true,
1320 move *STR over the operator and store its relocation code in *RELOC.
1321 Leave both *STR and *RELOC alone when returning false. */
1324 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1325 const struct percent_op_match
*percent_op
)
1327 for ( ; percent_op
->str
; percent_op
++)
1328 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1330 int len
= strlen (percent_op
->str
);
1332 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1335 *str
+= strlen (percent_op
->str
);
1336 *reloc
= percent_op
->reloc
;
1338 /* Check whether the output BFD supports this relocation.
1339 If not, issue an error and fall back on something safe. */
1340 if (*reloc
!= BFD_RELOC_UNUSED
1341 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1343 as_bad ("relocation %s isn't supported by the current ABI",
1345 *reloc
= BFD_RELOC_UNUSED
;
1353 my_getExpression (expressionS
*ep
, char *str
)
1357 save_in
= input_line_pointer
;
1358 input_line_pointer
= str
;
1360 expr_end
= input_line_pointer
;
1361 input_line_pointer
= save_in
;
1364 /* Parse string STR as a 16-bit relocatable operand. Store the
1365 expression in *EP and the relocation, if any, in RELOC.
1366 Return the number of relocation operators used (0 or 1).
1368 On exit, EXPR_END points to the first character after the expression. */
1371 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1372 char *str
, const struct percent_op_match
*percent_op
)
1375 unsigned crux_depth
, str_depth
, regno
;
1378 /* First, check for integer registers. */
1379 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1381 ep
->X_op
= O_register
;
1382 ep
->X_add_number
= regno
;
1386 /* Search for the start of the main expression.
1387 End the loop with CRUX pointing to the start
1388 of the main expression and with CRUX_DEPTH containing the number
1389 of open brackets at that point. */
1396 crux_depth
= str_depth
;
1398 /* Skip over whitespace and brackets, keeping count of the number
1400 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1406 && parse_relocation (&str
, reloc
, percent_op
));
1408 my_getExpression (ep
, crux
);
1411 /* Match every open bracket. */
1412 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1417 as_bad ("unclosed '('");
1424 /* Parse opcode name, could be an mnemonics or number. */
1426 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1427 char *str
, const struct percent_op_match
*percent_op
)
1429 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1433 ep
->X_op
= O_constant
;
1434 ep
->X_add_number
= o
->val
;
1438 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1441 /* Detect and handle implicitly zero load-store offsets. For example,
1442 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1443 an implicit offset was detected. */
1446 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1448 /* Check whether there is only a single bracketed expression left.
1449 If so, it must be the base register and the constant must be zero. */
1450 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1452 ep
->X_op
= O_constant
;
1453 ep
->X_add_number
= 0;
1460 /* This routine assembles an instruction into its binary format. As a
1461 side effect, it sets the global variable imm_reloc to the type of
1462 relocation to do if one of the operands is an address expression. */
1465 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1466 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1471 struct riscv_opcode
*insn
;
1476 const struct percent_op_match
*p
;
1477 const char *error
= "unrecognized opcode";
1479 /* Parse the name of the instruction. Terminate the string if whitespace
1480 is found so that hash_find only sees the name part of the string. */
1481 for (s
= str
; *s
!= '\0'; ++s
)
1489 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1492 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1494 if (!riscv_multi_subset_supports (insn
->xlen_requirement
, insn
->subset
))
1497 create_insn (ip
, insn
);
1500 imm_expr
->X_op
= O_absent
;
1501 *imm_reloc
= BFD_RELOC_UNUSED
;
1502 p
= percent_op_itype
;
1504 for (args
= insn
->args
;; ++args
)
1506 s
+= strspn (s
, " \t");
1509 case '\0': /* End of args. */
1510 if (insn
->pinfo
!= INSN_MACRO
)
1512 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1515 /* For .insn, insn->match and insn->mask are 0. */
1516 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1524 /* Successful assembly. */
1531 case 's': /* RS1 x8-x15 */
1532 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1533 || !(regno
>= 8 && regno
<= 15))
1535 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1537 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1538 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1539 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1542 case 't': /* RS2 x8-x15 */
1543 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1544 || !(regno
>= 8 && regno
<= 15))
1546 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1548 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1549 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1550 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1553 case 'U': /* RS1, constrained to equal RD. */
1554 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1555 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1559 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1561 INSERT_OPERAND (CRS2
, *ip
, regno
);
1563 case 'c': /* RS1, constrained to equal sp. */
1564 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1569 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1570 || imm_expr
->X_op
!= O_constant
1571 || imm_expr
->X_add_number
<= 0
1572 || imm_expr
->X_add_number
>= 64)
1574 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1577 imm_expr
->X_op
= O_absent
;
1580 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1581 || imm_expr
->X_op
!= O_constant
1582 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1583 || imm_expr
->X_add_number
<= 0
1584 || imm_expr
->X_add_number
>= 32)
1586 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1589 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1590 || imm_expr
->X_op
!= O_constant
1591 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1592 || imm_expr
->X_add_number
< 0
1593 || imm_expr
->X_add_number
>= 256)
1595 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1598 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1599 || imm_expr
->X_op
!= O_constant
1600 || imm_expr
->X_add_number
== 0
1601 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1603 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1606 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1607 || imm_expr
->X_op
!= O_constant
1608 || imm_expr
->X_add_number
== 0
1609 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1611 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1614 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1616 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1617 || imm_expr
->X_op
!= O_constant
1618 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1620 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1623 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1625 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1626 || imm_expr
->X_op
!= O_constant
1627 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1629 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1632 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1634 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1635 || imm_expr
->X_op
!= O_constant
1636 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1639 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1642 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1644 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1645 || imm_expr
->X_op
!= O_constant
1646 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1649 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1652 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1653 || imm_expr
->X_op
!= O_constant
1654 /* C.addiw, c.li, and c.andi allow zero immediate.
1655 C.addi allows zero immediate as hint. Otherwise this
1657 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1659 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1662 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1663 || imm_expr
->X_op
!= O_constant
1664 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1665 || imm_expr
->X_add_number
== 0)
1668 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1671 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1672 || imm_expr
->X_op
!= O_constant
1673 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1674 || imm_expr
->X_add_number
== 0)
1677 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1680 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1682 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1683 || imm_expr
->X_op
!= O_constant
1684 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1687 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1690 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1692 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1693 || imm_expr
->X_op
!= O_constant
1694 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1697 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1700 p
= percent_op_utype
;
1701 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1704 if (imm_expr
->X_op
!= O_constant
1705 || imm_expr
->X_add_number
<= 0
1706 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1707 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1708 && (imm_expr
->X_add_number
<
1709 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1711 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1714 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1715 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1716 || ((int32_t)imm_expr
->X_add_number
1717 != imm_expr
->X_add_number
))
1719 imm_expr
->X_add_number
=
1720 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1726 case 'S': /* Floating-point RS1 x8-x15. */
1727 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1728 || !(regno
>= 8 && regno
<= 15))
1730 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1732 case 'D': /* Floating-point RS2 x8-x15. */
1733 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1734 || !(regno
>= 8 && regno
<= 15))
1736 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1738 case 'T': /* Floating-point RS2. */
1739 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1741 INSERT_OPERAND (CRS2
, *ip
, regno
);
1747 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1748 || imm_expr
->X_op
!= O_constant
1749 || imm_expr
->X_add_number
< 0
1750 || imm_expr
->X_add_number
>= 64)
1752 as_bad (_("bad value for funct6 field, "
1753 "value must be 0...64"));
1757 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1758 imm_expr
->X_op
= O_absent
;
1762 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1763 || imm_expr
->X_op
!= O_constant
1764 || imm_expr
->X_add_number
< 0
1765 || imm_expr
->X_add_number
>= 16)
1767 as_bad (_("bad value for funct4 field, "
1768 "value must be 0...15"));
1772 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1773 imm_expr
->X_op
= O_absent
;
1777 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1778 || imm_expr
->X_op
!= O_constant
1779 || imm_expr
->X_add_number
< 0
1780 || imm_expr
->X_add_number
>= 8)
1782 as_bad (_("bad value for funct3 field, "
1783 "value must be 0...7"));
1786 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1787 imm_expr
->X_op
= O_absent
;
1791 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1792 || imm_expr
->X_op
!= O_constant
1793 || imm_expr
->X_add_number
< 0
1794 || imm_expr
->X_add_number
>= 4)
1796 as_bad (_("bad value for funct2 field, "
1797 "value must be 0...3"));
1800 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1801 imm_expr
->X_op
= O_absent
;
1805 as_bad (_("bad compressed FUNCT field"
1806 " specifier 'CF%c'\n"),
1812 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1831 case '<': /* Shift amount, 0 - 31. */
1832 my_getExpression (imm_expr
, s
);
1833 check_absolute_expr (ip
, imm_expr
, FALSE
);
1834 if ((unsigned long) imm_expr
->X_add_number
> 31)
1835 as_bad (_("Improper shift amount (%lu)"),
1836 (unsigned long) imm_expr
->X_add_number
);
1837 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1838 imm_expr
->X_op
= O_absent
;
1842 case '>': /* Shift amount, 0 - (XLEN-1). */
1843 my_getExpression (imm_expr
, s
);
1844 check_absolute_expr (ip
, imm_expr
, FALSE
);
1845 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1846 as_bad (_("Improper shift amount (%lu)"),
1847 (unsigned long) imm_expr
->X_add_number
);
1848 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1849 imm_expr
->X_op
= O_absent
;
1853 case 'Z': /* CSRRxI immediate. */
1854 my_getExpression (imm_expr
, s
);
1855 check_absolute_expr (ip
, imm_expr
, FALSE
);
1856 if ((unsigned long) imm_expr
->X_add_number
> 31)
1857 as_bad (_("Improper CSRxI immediate (%lu)"),
1858 (unsigned long) imm_expr
->X_add_number
);
1859 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1860 imm_expr
->X_op
= O_absent
;
1864 case 'E': /* Control register. */
1865 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1866 INSERT_OPERAND (CSR
, *ip
, regno
);
1869 my_getExpression (imm_expr
, s
);
1870 check_absolute_expr (ip
, imm_expr
, TRUE
);
1871 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1872 as_bad (_("Improper CSR address (%lu)"),
1873 (unsigned long) imm_expr
->X_add_number
);
1874 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1875 imm_expr
->X_op
= O_absent
;
1880 case 'm': /* Rounding mode. */
1881 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1883 INSERT_OPERAND (RM
, *ip
, regno
);
1889 case 'Q': /* Fence predecessor/successor. */
1890 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1894 INSERT_OPERAND (PRED
, *ip
, regno
);
1896 INSERT_OPERAND (SUCC
, *ip
, regno
);
1901 case 'd': /* Destination register. */
1902 case 's': /* Source register. */
1903 case 't': /* Target register. */
1904 case 'r': /* rs3. */
1905 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1911 /* Now that we have assembled one operand, we use the args
1912 string to figure out where it goes in the instruction. */
1916 INSERT_OPERAND (RS1
, *ip
, regno
);
1919 INSERT_OPERAND (RD
, *ip
, regno
);
1922 INSERT_OPERAND (RS2
, *ip
, regno
);
1925 INSERT_OPERAND (RS3
, *ip
, regno
);
1932 case 'D': /* Floating point rd. */
1933 case 'S': /* Floating point rs1. */
1934 case 'T': /* Floating point rs2. */
1935 case 'U': /* Floating point rs1 and rs2. */
1936 case 'R': /* Floating point rs3. */
1937 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1945 INSERT_OPERAND (RD
, *ip
, regno
);
1948 INSERT_OPERAND (RS1
, *ip
, regno
);
1951 INSERT_OPERAND (RS1
, *ip
, regno
);
1954 INSERT_OPERAND (RS2
, *ip
, regno
);
1957 INSERT_OPERAND (RS3
, *ip
, regno
);
1966 my_getExpression (imm_expr
, s
);
1967 if (imm_expr
->X_op
!= O_big
1968 && imm_expr
->X_op
!= O_constant
)
1970 normalize_constant_expr (imm_expr
);
1975 my_getExpression (imm_expr
, s
);
1976 normalize_constant_expr (imm_expr
);
1977 /* The 'A' format specifier must be a symbol. */
1978 if (imm_expr
->X_op
!= O_symbol
)
1980 *imm_reloc
= BFD_RELOC_32
;
1985 my_getExpression (imm_expr
, s
);
1986 normalize_constant_expr (imm_expr
);
1987 /* The 'B' format specifier must be a symbol or a constant. */
1988 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1990 if (imm_expr
->X_op
== O_symbol
)
1991 *imm_reloc
= BFD_RELOC_32
;
1995 case 'j': /* Sign-extended immediate. */
1996 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1997 p
= percent_op_itype
;
1999 case 'q': /* Store displacement. */
2000 p
= percent_op_stype
;
2001 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2003 case 'o': /* Load displacement. */
2004 p
= percent_op_itype
;
2005 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2007 case '0': /* AMO "displacement," which must be zero. */
2008 p
= percent_op_rtype
;
2009 *imm_reloc
= BFD_RELOC_UNUSED
;
2011 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2014 /* If this value won't fit into a 16 bit offset, then go
2015 find a macro that will generate the 32 bit offset
2017 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2019 normalize_constant_expr (imm_expr
);
2020 if (imm_expr
->X_op
!= O_constant
2021 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2022 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2023 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2030 case 'p': /* PC-relative offset. */
2032 *imm_reloc
= BFD_RELOC_12_PCREL
;
2033 my_getExpression (imm_expr
, s
);
2037 case 'u': /* Upper 20 bits. */
2038 p
= percent_op_utype
;
2039 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2040 && imm_expr
->X_op
== O_constant
)
2042 if (imm_expr
->X_add_number
< 0
2043 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2044 as_bad (_("lui expression not in range 0..1048575"));
2046 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2047 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2052 case 'a': /* 20-bit PC-relative offset. */
2054 my_getExpression (imm_expr
, s
);
2056 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2060 my_getExpression (imm_expr
, s
);
2062 if (strcmp (s
, "@plt") == 0)
2064 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2068 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2074 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2075 || imm_expr
->X_op
!= O_constant
2076 || imm_expr
->X_add_number
< 0
2077 || imm_expr
->X_add_number
>= 128
2078 || (imm_expr
->X_add_number
& 0x3) != 3)
2080 as_bad (_("bad value for opcode field, "
2081 "value must be 0...127 and "
2082 "lower 2 bits must be 0x3"));
2086 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2087 imm_expr
->X_op
= O_absent
;
2091 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2092 || imm_expr
->X_op
!= O_constant
2093 || imm_expr
->X_add_number
< 0
2094 || imm_expr
->X_add_number
>= 3)
2096 as_bad (_("bad value for opcode field, "
2097 "value must be 0...2"));
2101 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2102 imm_expr
->X_op
= O_absent
;
2106 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2114 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2115 || imm_expr
->X_op
!= O_constant
2116 || imm_expr
->X_add_number
< 0
2117 || imm_expr
->X_add_number
>= 128)
2119 as_bad (_("bad value for funct7 field, "
2120 "value must be 0...127"));
2124 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2125 imm_expr
->X_op
= O_absent
;
2129 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2130 || imm_expr
->X_op
!= O_constant
2131 || imm_expr
->X_add_number
< 0
2132 || imm_expr
->X_add_number
>= 8)
2134 as_bad (_("bad value for funct3 field, "
2135 "value must be 0...7"));
2139 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2140 imm_expr
->X_op
= O_absent
;
2144 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2145 || imm_expr
->X_op
!= O_constant
2146 || imm_expr
->X_add_number
< 0
2147 || imm_expr
->X_add_number
>= 4)
2149 as_bad (_("bad value for funct2 field, "
2150 "value must be 0...3"));
2154 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2155 imm_expr
->X_op
= O_absent
;
2160 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2165 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2166 || imm_expr
->X_op
!= O_constant
2167 || imm_expr
->X_add_number
!= 0)
2170 imm_expr
->X_op
= O_absent
;
2174 as_fatal (_("internal error: bad argument type %c"), *args
);
2179 error
= _("illegal operands");
2183 /* Restore the character we might have clobbered above. */
2185 *(argsStart
- 1) = save_c
;
2191 md_assemble (char *str
)
2193 struct riscv_cl_insn insn
;
2194 expressionS imm_expr
;
2195 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2197 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2201 as_bad ("%s `%s'", error
, str
);
2205 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2206 macro (&insn
, &imm_expr
, &imm_reloc
);
2208 append_insn (&insn
, &imm_expr
, imm_reloc
);
2212 md_atof (int type
, char *litP
, int *sizeP
)
2214 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2218 md_number_to_chars (char *buf
, valueT val
, int n
)
2220 number_to_chars_littleendian (buf
, val
, n
);
2223 const char *md_shortopts
= "O::g::G:";
2227 OPTION_MARCH
= OPTION_MD_BASE
,
2236 struct option md_longopts
[] =
2238 {"march", required_argument
, NULL
, OPTION_MARCH
},
2239 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2240 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2241 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2242 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2243 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2244 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2246 {NULL
, no_argument
, NULL
, 0}
2248 size_t md_longopts_size
= sizeof (md_longopts
);
2251 FLOAT_ABI_DEFAULT
= -1,
2257 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2260 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2262 abi_xlen
= new_xlen
;
2263 float_abi
= new_float_abi
;
2268 md_parse_option (int c
, const char *arg
)
2273 riscv_set_arch (arg
);
2277 riscv_opts
.pic
= FALSE
;
2281 riscv_opts
.pic
= TRUE
;
2285 if (strcmp (arg
, "ilp32") == 0)
2286 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2287 else if (strcmp (arg
, "ilp32e") == 0)
2288 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2289 else if (strcmp (arg
, "ilp32f") == 0)
2290 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2291 else if (strcmp (arg
, "ilp32d") == 0)
2292 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2293 else if (strcmp (arg
, "ilp32q") == 0)
2294 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2295 else if (strcmp (arg
, "lp64") == 0)
2296 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2297 else if (strcmp (arg
, "lp64f") == 0)
2298 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2299 else if (strcmp (arg
, "lp64d") == 0)
2300 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2301 else if (strcmp (arg
, "lp64q") == 0)
2302 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2308 riscv_opts
.relax
= TRUE
;
2311 case OPTION_NO_RELAX
:
2312 riscv_opts
.relax
= FALSE
;
2323 riscv_after_parse_args (void)
2327 if (strcmp (default_arch
, "riscv32") == 0)
2329 else if (strcmp (default_arch
, "riscv64") == 0)
2332 as_bad ("unknown default architecture `%s'", default_arch
);
2335 if (riscv_subsets
== NULL
)
2336 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2338 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2339 riscv_set_rvc (FALSE
);
2340 if (riscv_subset_supports (0, "c"))
2341 riscv_set_rvc (TRUE
);
2343 riscv_add_subset ("c");
2345 /* Enable RVE if specified by the -march option. */
2346 riscv_set_rve (FALSE
);
2347 if (riscv_subset_supports (0, "e"))
2348 riscv_set_rve (TRUE
);
2350 /* Infer ABI from ISA if not specified on command line. */
2353 else if (abi_xlen
> xlen
)
2354 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2355 else if (abi_xlen
< xlen
)
2356 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2358 if (float_abi
== FLOAT_ABI_DEFAULT
)
2360 struct riscv_subset
*subset
;
2362 /* Assume soft-float unless D extension is present. */
2363 float_abi
= FLOAT_ABI_SOFT
;
2365 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
2367 if (strcasecmp (subset
->name
, "D") == 0)
2368 float_abi
= FLOAT_ABI_DOUBLE
;
2369 if (strcasecmp (subset
->name
, "Q") == 0)
2370 float_abi
= FLOAT_ABI_QUAD
;
2375 elf_flags
|= EF_RISCV_RVE
;
2377 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2378 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2382 md_pcrel_from (fixS
*fixP
)
2384 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2387 /* Apply a fixup to the object file. */
2390 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2392 unsigned int subtype
;
2393 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2394 bfd_boolean relaxable
= FALSE
;
2398 /* Remember value for tc_gen_reloc. */
2399 fixP
->fx_addnumber
= *valP
;
2401 switch (fixP
->fx_r_type
)
2403 case BFD_RELOC_RISCV_HI20
:
2404 case BFD_RELOC_RISCV_LO12_I
:
2405 case BFD_RELOC_RISCV_LO12_S
:
2406 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2407 | bfd_getl32 (buf
), buf
);
2408 if (fixP
->fx_addsy
== NULL
)
2409 fixP
->fx_done
= TRUE
;
2413 case BFD_RELOC_RISCV_GOT_HI20
:
2414 case BFD_RELOC_RISCV_ADD8
:
2415 case BFD_RELOC_RISCV_ADD16
:
2416 case BFD_RELOC_RISCV_ADD32
:
2417 case BFD_RELOC_RISCV_ADD64
:
2418 case BFD_RELOC_RISCV_SUB6
:
2419 case BFD_RELOC_RISCV_SUB8
:
2420 case BFD_RELOC_RISCV_SUB16
:
2421 case BFD_RELOC_RISCV_SUB32
:
2422 case BFD_RELOC_RISCV_SUB64
:
2423 case BFD_RELOC_RISCV_RELAX
:
2426 case BFD_RELOC_RISCV_TPREL_HI20
:
2427 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2428 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2429 case BFD_RELOC_RISCV_TPREL_ADD
:
2433 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2434 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2435 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2436 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2437 if (fixP
->fx_addsy
!= NULL
)
2438 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2441 _("TLS relocation against a constant"));
2445 /* Use pc-relative relocation for FDE initial location.
2446 The symbol address in .eh_frame may be adjusted in
2447 _bfd_elf_discard_section_eh_frame, and the content of
2448 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2449 Therefore, we cannot insert a relocation whose addend symbol is
2450 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2451 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2452 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2453 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2454 && S_GET_VALUE (fixP
->fx_subsy
)
2455 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2457 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2458 fixP
->fx_subsy
= NULL
;
2465 case BFD_RELOC_RISCV_CFA
:
2466 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2468 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2469 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2470 fixP
->fx_next
->fx_subsy
= NULL
;
2471 fixP
->fx_next
->fx_offset
= 0;
2472 fixP
->fx_subsy
= NULL
;
2474 switch (fixP
->fx_r_type
)
2477 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2478 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2482 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2483 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2487 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2488 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2492 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2493 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2496 case BFD_RELOC_RISCV_CFA
:
2497 /* Load the byte to get the subtype. */
2498 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2499 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2502 case DW_CFA_advance_loc1
:
2503 fixP
->fx_where
= loc
+ 1;
2504 fixP
->fx_next
->fx_where
= loc
+ 1;
2505 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2506 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2509 case DW_CFA_advance_loc2
:
2511 fixP
->fx_next
->fx_size
= 2;
2512 fixP
->fx_where
= loc
+ 1;
2513 fixP
->fx_next
->fx_where
= loc
+ 1;
2514 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2515 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2518 case DW_CFA_advance_loc4
:
2520 fixP
->fx_next
->fx_size
= 4;
2521 fixP
->fx_where
= loc
;
2522 fixP
->fx_next
->fx_where
= loc
;
2523 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2524 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2528 if (subtype
< 0x80 && (subtype
& 0x40))
2530 /* DW_CFA_advance_loc */
2531 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2532 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2533 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2534 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2537 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2543 /* This case is unreachable. */
2550 /* If we are deleting this reloc entry, we must fill in the
2551 value now. This can happen if we have a .word which is not
2552 resolved when it appears but is later defined. */
2553 if (fixP
->fx_addsy
== NULL
)
2555 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2556 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2561 case BFD_RELOC_RISCV_JMP
:
2564 /* Fill in a tentative value to improve objdump readability. */
2565 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2566 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2567 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2571 case BFD_RELOC_12_PCREL
:
2574 /* Fill in a tentative value to improve objdump readability. */
2575 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2576 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2577 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2581 case BFD_RELOC_RISCV_RVC_BRANCH
:
2584 /* Fill in a tentative value to improve objdump readability. */
2585 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2586 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2587 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2591 case BFD_RELOC_RISCV_RVC_JUMP
:
2594 /* Fill in a tentative value to improve objdump readability. */
2595 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2596 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2597 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2601 case BFD_RELOC_RISCV_CALL
:
2602 case BFD_RELOC_RISCV_CALL_PLT
:
2606 case BFD_RELOC_RISCV_PCREL_HI20
:
2607 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2608 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2609 relaxable
= riscv_opts
.relax
;
2612 case BFD_RELOC_RISCV_ALIGN
:
2616 /* We ignore generic BFD relocations we don't know about. */
2617 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2618 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2621 if (fixP
->fx_subsy
!= NULL
)
2622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2623 _("unsupported symbol subtraction"));
2625 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2626 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2628 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2629 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2630 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2634 /* Because the value of .cfi_remember_state may changed after relaxation,
2635 we insert a fix to relocate it again in link-time. */
2638 riscv_pre_output_hook (void)
2640 const frchainS
*frch
;
2643 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2644 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2648 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2650 if (frag
->fr_type
== rs_cfa
)
2653 expressionS
*symval
;
2655 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2656 exp
.X_op
= O_subtract
;
2657 exp
.X_add_symbol
= symval
->X_add_symbol
;
2658 exp
.X_add_number
= 0;
2659 exp
.X_op_symbol
= symval
->X_op_symbol
;
2661 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2662 BFD_RELOC_RISCV_CFA
);
2669 /* This structure is used to hold a stack of .option values. */
2671 struct riscv_option_stack
2673 struct riscv_option_stack
*next
;
2674 struct riscv_set_options options
;
2677 static struct riscv_option_stack
*riscv_opts_stack
;
2679 /* Handle the .option pseudo-op. */
2682 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2684 char *name
= input_line_pointer
, ch
;
2686 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2687 ++input_line_pointer
;
2688 ch
= *input_line_pointer
;
2689 *input_line_pointer
= '\0';
2691 if (strcmp (name
, "rvc") == 0)
2692 riscv_set_rvc (TRUE
);
2693 else if (strcmp (name
, "norvc") == 0)
2694 riscv_set_rvc (FALSE
);
2695 else if (strcmp (name
, "pic") == 0)
2696 riscv_opts
.pic
= TRUE
;
2697 else if (strcmp (name
, "nopic") == 0)
2698 riscv_opts
.pic
= FALSE
;
2699 else if (strcmp (name
, "relax") == 0)
2700 riscv_opts
.relax
= TRUE
;
2701 else if (strcmp (name
, "norelax") == 0)
2702 riscv_opts
.relax
= FALSE
;
2703 else if (strcmp (name
, "push") == 0)
2705 struct riscv_option_stack
*s
;
2707 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2708 s
->next
= riscv_opts_stack
;
2709 s
->options
= riscv_opts
;
2710 riscv_opts_stack
= s
;
2712 else if (strcmp (name
, "pop") == 0)
2714 struct riscv_option_stack
*s
;
2716 s
= riscv_opts_stack
;
2718 as_bad (_(".option pop with no .option push"));
2721 riscv_opts
= s
->options
;
2722 riscv_opts_stack
= s
->next
;
2728 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2730 *input_line_pointer
= ch
;
2731 demand_empty_rest_of_line ();
2734 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2735 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2736 use in DWARF debug information. */
2739 s_dtprel (int bytes
)
2746 if (ex
.X_op
!= O_symbol
)
2748 as_bad (_("Unsupported use of %s"), (bytes
== 8
2751 ignore_rest_of_line ();
2754 p
= frag_more (bytes
);
2755 md_number_to_chars (p
, 0, bytes
);
2756 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2758 ? BFD_RELOC_RISCV_TLS_DTPREL64
2759 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2761 demand_empty_rest_of_line ();
2764 /* Handle the .bss pseudo-op. */
2767 s_bss (int ignore ATTRIBUTE_UNUSED
)
2769 subseg_set (bss_section
, 0);
2770 demand_empty_rest_of_line ();
2774 riscv_make_nops (char *buf
, bfd_vma bytes
)
2778 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2779 means we are not within a valid instruction sequence. It is thus safe
2780 to use a zero byte, even though that is not a valid instruction. */
2784 /* Use at most one 2-byte NOP. */
2785 if ((bytes
- i
) % 4 == 2)
2787 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2791 /* Fill the remainder with 4-byte NOPs. */
2792 for ( ; i
< bytes
; i
+= 4)
2793 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2796 /* Called from md_do_align. Used to create an alignment frag in a
2797 code section by emitting a worst-case NOP sequence that the linker
2798 will later relax to the correct number of NOPs. We can't compute
2799 the correct alignment now because of other linker relaxations. */
2802 riscv_frag_align_code (int n
)
2804 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2805 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2806 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2810 /* If we are moving to a smaller alignment than the instruction size, then no
2811 alignment is required. */
2812 if (bytes
<= insn_alignment
)
2815 /* When not relaxing, riscv_handle_align handles code alignment. */
2816 if (!riscv_opts
.relax
)
2819 nops
= frag_more (worst_case_bytes
);
2821 ex
.X_op
= O_constant
;
2822 ex
.X_add_number
= worst_case_bytes
;
2824 riscv_make_nops (nops
, worst_case_bytes
);
2826 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2827 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2832 /* Implement HANDLE_ALIGN. */
2835 riscv_handle_align (fragS
*fragP
)
2837 switch (fragP
->fr_type
)
2840 /* When relaxing, riscv_frag_align_code handles code alignment. */
2841 if (!riscv_opts
.relax
)
2843 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2844 - fragP
->fr_address
- fragP
->fr_fix
);
2845 /* We have 4 byte uncompressed nops. */
2846 bfd_signed_vma size
= 4;
2847 bfd_signed_vma excess
= bytes
% size
;
2848 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2853 /* Insert zeros or compressed nops to get 4 byte alignment. */
2856 riscv_make_nops (p
, excess
);
2857 fragP
->fr_fix
+= excess
;
2861 /* Insert variable number of 4 byte uncompressed nops. */
2862 riscv_make_nops (p
, size
);
2863 fragP
->fr_var
= size
;
2873 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2875 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2878 /* Translate internal representation of relocation info to BFD target
2882 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2884 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2886 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2887 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2888 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2889 reloc
->addend
= fixp
->fx_addnumber
;
2891 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2892 if (reloc
->howto
== NULL
)
2894 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2895 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2897 /* We don't have R_RISCV_8/16, but for this special case,
2898 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2902 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2903 _("cannot represent %s relocation in object file"),
2904 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2912 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2914 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2916 offsetT old_var
= fragp
->fr_var
;
2917 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2918 return fragp
->fr_var
- old_var
;
2924 /* Expand far branches to multi-instruction sequences. */
2927 md_convert_frag_branch (fragS
*fragp
)
2935 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2937 exp
.X_op
= O_symbol
;
2938 exp
.X_add_symbol
= fragp
->fr_symbol
;
2939 exp
.X_add_number
= fragp
->fr_offset
;
2941 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2943 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2945 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2949 /* Expand the RVC branch into a RISC-V one. */
2950 insn
= bfd_getl16 (buf
);
2951 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2952 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2954 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2955 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2956 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2957 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2958 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2959 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2962 bfd_putl32 (insn
, buf
);
2966 /* Invert the branch condition. Branch over the jump. */
2967 insn
= bfd_getl16 (buf
);
2968 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2969 insn
|= ENCODE_RVC_B_IMM (6);
2970 bfd_putl16 (insn
, buf
);
2975 /* Just keep the RVC branch. */
2976 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2977 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2978 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2979 2, &exp
, FALSE
, reloc
);
2988 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2991 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2993 /* Invert the branch condition. Branch over the jump. */
2994 insn
= bfd_getl32 (buf
);
2995 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2996 insn
|= ENCODE_SBTYPE_IMM (8);
2997 md_number_to_chars ((char *) buf
, insn
, 4);
3001 /* Jump to the target. */
3002 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3003 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3004 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3009 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3010 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3011 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3012 4, &exp
, FALSE
, reloc
);
3021 fixp
->fx_file
= fragp
->fr_file
;
3022 fixp
->fx_line
= fragp
->fr_line
;
3024 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3025 + fragp
->fr_fix
+ fragp
->fr_var
);
3027 fragp
->fr_fix
+= fragp
->fr_var
;
3030 /* Relax a machine dependent frag. This returns the amount by which
3031 the current size of the frag should change. */
3034 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3037 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3038 md_convert_frag_branch (fragp
);
3042 md_show_usage (FILE *stream
)
3044 fprintf (stream
, _("\
3046 -fpic generate position-independent code\n\
3047 -fno-pic don't generate position-independent code (default)\n\
3048 -march=ISA set the RISC-V architecture\n\
3049 -mabi=ABI set the RISC-V ABI\n\
3050 -mrelax enable relax (default)\n\
3051 -mno-relax disable relax\n\
3055 /* Standard calling conventions leave the CFA at SP on entry. */
3057 riscv_cfi_frame_initial_instructions (void)
3059 cfi_add_CFA_def_cfa_register (X_SP
);
3063 tc_riscv_regname_to_dw2regnum (char *regname
)
3067 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3070 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3073 as_bad (_("unknown register `%s'"), regname
);
3078 riscv_elf_final_processing (void)
3080 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3083 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3084 since these directives break relaxation when used with symbol deltas. */
3087 s_riscv_leb128 (int sign
)
3090 char *save_in
= input_line_pointer
;
3093 if (exp
.X_op
!= O_constant
)
3094 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3095 demand_empty_rest_of_line ();
3097 input_line_pointer
= save_in
;
3098 return s_leb128 (sign
);
3101 /* Parse the .insn directive. */
3104 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3106 char *str
= input_line_pointer
;
3107 struct riscv_cl_insn insn
;
3108 expressionS imm_expr
;
3109 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3112 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3113 ++input_line_pointer
;
3115 save_c
= *input_line_pointer
;
3116 *input_line_pointer
= '\0';
3118 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3119 &imm_reloc
, insn_type_hash
);
3123 as_bad ("%s `%s'", error
, str
);
3127 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3128 append_insn (&insn
, &imm_expr
, imm_reloc
);
3131 *input_line_pointer
= save_c
;
3132 demand_empty_rest_of_line ();
3135 /* Pseudo-op table. */
3137 static const pseudo_typeS riscv_pseudo_table
[] =
3139 /* RISC-V-specific pseudo-ops. */
3140 {"option", s_riscv_option
, 0},
3144 {"dtprelword", s_dtprel
, 4},
3145 {"dtpreldword", s_dtprel
, 8},
3147 {"uleb128", s_riscv_leb128
, 0},
3148 {"sleb128", s_riscv_leb128
, 1},
3149 {"insn", s_riscv_insn
, 0},
3155 riscv_pop_insert (void)
3157 extern void pop_insert (const pseudo_typeS
*);
3159 pop_insert (riscv_pseudo_table
);