1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits
46 (first bits enough to extract instruction length on a long opcode). */
49 /* The long encoded instruction bits ([0] is non-zero on a long opcode). */
50 char insn_long_opcode
[RISCV_MAX_INSN_LEN
];
52 /* The frag that contains the instruction. */
55 /* The offset into FRAG of the first instruction byte. */
58 /* The relocs associated with the instruction, if any. */
62 /* All RISC-V CSR belong to one of these classes. */
68 CSR_CLASS_I_32
, /* rv32 only */
69 CSR_CLASS_F
, /* f-ext only */
70 CSR_CLASS_ZKR
, /* zkr only */
71 CSR_CLASS_V
, /* rvv only */
72 CSR_CLASS_DEBUG
, /* debug CSR */
73 CSR_CLASS_H
, /* hypervisor */
74 CSR_CLASS_H_32
, /* hypervisor, rv32 only */
75 CSR_CLASS_SMAIA
, /* Smaia */
76 CSR_CLASS_SMAIA_32
, /* Smaia, rv32 only */
77 CSR_CLASS_SMSTATEEN
, /* Smstateen only */
78 CSR_CLASS_SMSTATEEN_32
, /* Smstateen RV32 only */
79 CSR_CLASS_SSAIA
, /* Ssaia */
80 CSR_CLASS_SSAIA_AND_H
, /* Ssaia with H */
81 CSR_CLASS_SSAIA_32
, /* Ssaia, rv32 only */
82 CSR_CLASS_SSAIA_AND_H_32
, /* Ssaia with H, rv32 only */
83 CSR_CLASS_SSSTATEEN
, /* S[ms]stateen only */
84 CSR_CLASS_SSSTATEEN_AND_H
, /* S[ms]stateen only (with H) */
85 CSR_CLASS_SSSTATEEN_AND_H_32
, /* S[ms]stateen RV32 only (with H) */
86 CSR_CLASS_SSCOFPMF
, /* Sscofpmf only */
87 CSR_CLASS_SSCOFPMF_32
, /* Sscofpmf RV32 only */
88 CSR_CLASS_SSTC
, /* Sstc only */
89 CSR_CLASS_SSTC_AND_H
, /* Sstc only (with H) */
90 CSR_CLASS_SSTC_32
, /* Sstc RV32 only */
91 CSR_CLASS_SSTC_AND_H_32
, /* Sstc RV32 only (with H) */
94 /* This structure holds all restricted conditions for a CSR. */
95 struct riscv_csr_extra
97 /* Class to which this CSR belongs. Used to decide whether or
98 not this CSR is legal in the current -march context. */
99 enum riscv_csr_class csr_class
;
101 /* CSR may have differnet numbers in the previous priv spec. */
104 /* Record the CSR is defined/valid in which versions. */
105 enum riscv_spec_class define_version
;
107 /* Record the CSR is aborted/invalid from which versions. If it isn't
108 aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
109 enum riscv_spec_class abort_version
;
111 /* The CSR may have more than one setting. */
112 struct riscv_csr_extra
*next
;
115 /* This structure contains information about errors that occur within the
117 struct riscv_ip_error
119 /* General error message */
122 /* Statement that caused the error */
125 /* Missing extension that needs to be enabled */
126 const char* missing_ext
;
130 #define DEFAULT_ARCH "riscv64"
133 #ifndef DEFAULT_RISCV_ATTR
134 #define DEFAULT_RISCV_ATTR 0
137 /* Let riscv_after_parse_args set the default value according to xlen. */
138 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
139 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
142 /* Need to sync the version with RISC-V compiler. */
143 #ifndef DEFAULT_RISCV_ISA_SPEC
144 #define DEFAULT_RISCV_ISA_SPEC "20191213"
147 #ifndef DEFAULT_RISCV_PRIV_SPEC
148 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
151 static const char default_arch
[] = DEFAULT_ARCH
;
152 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
153 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
154 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
156 static unsigned xlen
= 0; /* The width of an x-register. */
157 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
158 static bool rve_abi
= false;
161 FLOAT_ABI_DEFAULT
= -1,
167 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
169 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
170 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
172 static unsigned elf_flags
= 0;
174 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
175 Otherwise, return 1. */
178 riscv_set_default_isa_spec (const char *s
)
180 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
181 RISCV_GET_ISA_SPEC_CLASS (s
, class);
182 if (class == ISA_SPEC_CLASS_NONE
)
184 as_bad ("unknown default ISA spec `%s' set by "
185 "-misa-spec or --with-isa-spec", s
);
189 default_isa_spec
= class;
193 /* Set the default_priv_spec. Find the privileged elf attributes when
194 the input string is NULL. Return 0 if the spec isn't supported.
195 Otherwise, return 1. */
198 riscv_set_default_priv_spec (const char *s
)
200 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
201 unsigned major
, minor
, revision
;
204 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
205 if (class != PRIV_SPEC_CLASS_NONE
)
207 default_priv_spec
= class;
213 as_bad (_("unknown default privileged spec `%s' set by "
214 "-mpriv-spec or --with-priv-spec"), s
);
218 /* Set the default_priv_spec by the privileged elf attributes. */
219 attr
= elf_known_obj_attributes_proc (stdoutput
);
220 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
221 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
222 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
223 /* Version 0.0.0 is the default value and meningless. */
224 if (major
== 0 && minor
== 0 && revision
== 0)
227 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
228 if (class != PRIV_SPEC_CLASS_NONE
)
230 default_priv_spec
= class;
234 /* Still can not find the privileged spec class. */
235 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
236 "privileged elf attributes"), major
, minor
, revision
);
240 /* This is the set of options which the .option pseudo-op may modify. */
241 struct riscv_set_options
243 int pic
; /* Generate position-independent code. */
244 int rvc
; /* Generate RVC code. */
245 int relax
; /* Emit relocs the linker is allowed to relax. */
246 int arch_attr
; /* Emit architecture and privileged elf attributes. */
247 int csr_check
; /* Enable the CSR checking. */
250 static struct riscv_set_options riscv_opts
=
255 DEFAULT_RISCV_ATTR
, /* arch_attr */
259 /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag
260 for elf_flags once we have enabled c extension. */
263 riscv_set_rvc (bool rvc_value
)
266 elf_flags
|= EF_RISCV_RVC
;
268 riscv_opts
.rvc
= rvc_value
;
271 /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */
276 elf_flags
|= EF_RISCV_TSO
;
279 /* The linked list hanging off of .subsets_list records all enabled extensions,
280 which are parsed from the architecture string. The architecture string can
281 be set by the -march option, the elf architecture attributes, and the
282 --with-arch configure option. */
283 static riscv_parse_subset_t riscv_rps_as
=
285 NULL
, /* subset_list, we will set it later once
286 riscv_opts_stack is created or updated. */
287 as_bad
, /* error_handler. */
289 &default_isa_spec
, /* isa_spec. */
290 true, /* check_unknown_prefixed_ext. */
293 /* Update the architecture string in the subset_list. */
296 riscv_reset_subsets_list_arch_str (void)
298 riscv_subset_list_t
*subsets
= riscv_rps_as
.subset_list
;
299 if (subsets
->arch_str
!= NULL
)
300 free ((void *) subsets
->arch_str
);
301 subsets
->arch_str
= riscv_arch_str (xlen
, subsets
);
304 /* This structure is used to hold a stack of .option values. */
305 struct riscv_option_stack
307 struct riscv_option_stack
*next
;
308 struct riscv_set_options options
;
309 riscv_subset_list_t
*subset_list
;
312 static struct riscv_option_stack
*riscv_opts_stack
= NULL
;
314 /* Set which ISA and extensions are available. */
317 riscv_set_arch (const char *s
)
319 if (s
!= NULL
&& strcmp (s
, "") == 0)
321 as_bad (_("the architecture string of -march and elf architecture "
322 "attributes cannot be empty"));
326 if (riscv_rps_as
.subset_list
== NULL
)
328 riscv_rps_as
.subset_list
= XNEW (riscv_subset_list_t
);
329 riscv_rps_as
.subset_list
->head
= NULL
;
330 riscv_rps_as
.subset_list
->tail
= NULL
;
331 riscv_rps_as
.subset_list
->arch_str
= NULL
;
333 riscv_release_subset_list (riscv_rps_as
.subset_list
);
334 riscv_parse_subset (&riscv_rps_as
, s
);
335 riscv_reset_subsets_list_arch_str ();
337 riscv_set_rvc (false);
338 if (riscv_subset_supports (&riscv_rps_as
, "c"))
339 riscv_set_rvc (true);
341 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
345 /* Indicate -mabi option is explictly set. */
346 static bool explicit_mabi
= false;
348 /* Set the abi information. */
351 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
354 float_abi
= new_float_abi
;
358 /* If the -mabi option isn't set, then set the abi according to the
359 ISA string. Otherwise, check if there is any conflict. */
362 riscv_set_abi_by_arch (void)
366 if (riscv_subset_supports (&riscv_rps_as
, "q"))
367 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
368 else if (riscv_subset_supports (&riscv_rps_as
, "d"))
369 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
370 else if (riscv_subset_supports (&riscv_rps_as
, "e"))
371 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
373 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
377 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
379 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
380 else if (abi_xlen
< xlen
)
381 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
383 if (riscv_subset_supports (&riscv_rps_as
, "e") && !rve_abi
)
384 as_bad ("only the ilp32e ABI is supported for e extension");
386 if (float_abi
== FLOAT_ABI_SINGLE
387 && !riscv_subset_supports (&riscv_rps_as
, "f"))
388 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
390 else if (float_abi
== FLOAT_ABI_DOUBLE
391 && !riscv_subset_supports (&riscv_rps_as
, "d"))
392 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
394 else if (float_abi
== FLOAT_ABI_QUAD
395 && !riscv_subset_supports (&riscv_rps_as
, "q"))
396 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
400 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
401 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
402 elf_flags
|= float_abi
<< 1;
405 elf_flags
|= EF_RISCV_RVE
;
408 /* Handle of the OPCODE hash table. */
409 static htab_t op_hash
= NULL
;
411 /* Handle of the type of .insn hash table. */
412 static htab_t insn_type_hash
= NULL
;
414 /* This array holds the chars that always start a comment. If the
415 pre-processor is disabled, these aren't very useful. */
416 const char comment_chars
[] = "#";
418 /* This array holds the chars that only start a comment at the beginning of
419 a line. If the line seems to have the form '# 123 filename'
420 .line and .file directives will appear in the pre-processed output
422 Note that input_file.c hand checks for '#' at the beginning of the
423 first line of the input file. This is because the compiler outputs
424 #NO_APP at the beginning of its output.
426 Also note that C style comments are always supported. */
427 const char line_comment_chars
[] = "#";
429 /* This array holds machine specific line separator characters. */
430 const char line_separator_chars
[] = ";";
432 /* Chars that can be used to separate mant from exp in floating point nums. */
433 const char EXP_CHARS
[] = "eE";
435 /* Chars that mean this number is a floating point constant.
436 As in 0f12.456 or 0d1.2345e12. */
437 const char FLT_CHARS
[] = "rRsSfFdDxXpPhH";
439 /* Indicate we are already assemble any instructions or not. */
440 static bool start_assemble
= false;
442 /* Indicate ELF attributes are explicitly set. */
443 static bool explicit_attr
= false;
445 /* Indicate CSR or priv instructions are explicitly used. */
446 static bool explicit_priv_attr
= false;
448 static char *expr_parse_end
;
450 /* Macros for encoding relaxation state for RVC branches and far jumps. */
451 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
454 | ((uncond) ? 1 : 0) \
457 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
458 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
459 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
460 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
462 /* Is the given value a sign-extended 32-bit value? */
463 #define IS_SEXT_32BIT_NUM(x) \
464 (((x) &~ (offsetT) 0x7fffffff) == 0 \
465 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
467 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
468 #define IS_ZEXT_32BIT_NUM(x) \
469 (((x) &~ (offsetT) 0xffffffff) == 0 \
470 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
472 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
473 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
474 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
475 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
477 #define INSERT_IMM(n, s, INSN, VALUE) \
478 INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s)
480 /* Determine if an instruction matches an opcode. */
481 #define OPCODE_MATCHES(OPCODE, OP) \
482 (((OPCODE) & MASK_##OP) == MATCH_##OP)
484 /* Create a new mapping symbol for the transition to STATE. */
487 make_mapping_symbol (enum riscv_seg_mstate state
,
490 const char *arch_str
,
491 bool odd_data_padding
)
501 if (arch_str
!= NULL
)
503 size_t size
= strlen (arch_str
) + 3; /* "$x" + '\0' */
504 buff
= xmalloc (size
);
505 snprintf (buff
, size
, "$x%s", arch_str
);
515 symbolS
*symbol
= symbol_new (name
, now_seg
, frag
, value
);
516 symbol_get_bfdsym (symbol
)->flags
|= (BSF_NO_FLAGS
| BSF_LOCAL
);
517 if (arch_str
!= NULL
)
519 /* Store current $x+arch into tc_segment_info. */
520 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
= symbol
;
521 xfree ((void *) buff
);
524 /* If .fill or other data filling directive generates zero sized data,
525 then mapping symbol for the following code will have the same value.
527 Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first
528 and .text.zero.fill.last. */
529 symbolS
*first
= frag
->tc_frag_data
.first_map_symbol
;
530 symbolS
*last
= frag
->tc_frag_data
.last_map_symbol
;
531 symbolS
*removed
= NULL
;
536 know (S_GET_VALUE (first
) == S_GET_VALUE (symbol
)
538 /* Remove the old one. */
541 frag
->tc_frag_data
.first_map_symbol
= symbol
;
543 else if (last
!= NULL
)
545 /* The mapping symbols should be added in offset order. */
546 know (S_GET_VALUE (last
) <= S_GET_VALUE (symbol
));
547 /* Remove the old one. */
548 if (S_GET_VALUE (last
) == S_GET_VALUE (symbol
))
551 frag
->tc_frag_data
.last_map_symbol
= symbol
;
556 if (odd_data_padding
)
558 /* If the removed mapping symbol is $x+arch, then add it back to
560 const char *str
= strncmp (S_GET_NAME (removed
), "$xrv", 4) == 0
561 ? S_GET_NAME (removed
) + 2 : NULL
;
562 make_mapping_symbol (MAP_INSN
, frag
->fr_fix
+ 1, frag
, str
,
563 false/* odd_data_padding */);
565 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
568 /* Set the mapping state for frag_now. */
571 riscv_mapping_state (enum riscv_seg_mstate to_state
,
575 enum riscv_seg_mstate from_state
=
576 seg_info (now_seg
)->tc_segment_info_data
.map_state
;
577 bool reset_seg_arch_str
= false;
579 if (!SEG_NORMAL (now_seg
)
580 /* For now we only add the mapping symbols to text sections.
581 Therefore, the dis-assembler only show the actual contents
582 distribution for text. Other sections will be shown as
583 data without the details. */
584 || !subseg_text_p (now_seg
))
587 /* The mapping symbol should be emitted if not in the right
589 symbolS
*seg_arch_symbol
=
590 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
;
591 if (to_state
== MAP_INSN
&& seg_arch_symbol
== 0)
593 /* Always add $x+arch at the first instruction of section. */
594 reset_seg_arch_str
= true;
596 else if (seg_arch_symbol
!= 0
597 && to_state
== MAP_INSN
599 && strcmp (riscv_rps_as
.subset_list
->arch_str
,
600 S_GET_NAME (seg_arch_symbol
) + 2) != 0)
602 reset_seg_arch_str
= true;
604 else if (from_state
== to_state
)
607 valueT value
= (valueT
) (frag_now_fix () - max_chars
);
608 seg_info (now_seg
)->tc_segment_info_data
.map_state
= to_state
;
609 const char *arch_str
= reset_seg_arch_str
610 ? riscv_rps_as
.subset_list
->arch_str
: NULL
;
611 make_mapping_symbol (to_state
, value
, frag_now
, arch_str
,
612 false/* odd_data_padding */);
615 /* Add the odd bytes of paddings for riscv_handle_align. */
618 riscv_add_odd_padding_symbol (fragS
*frag
)
620 /* If there was already a mapping symbol, it should be
621 removed in the make_mapping_symbol.
623 Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */
624 make_mapping_symbol (MAP_DATA
, frag
->fr_fix
, frag
,
625 NULL
/* arch_str */, true/* odd_data_padding */);
628 /* Remove any excess mapping symbols generated for alignment frags in
629 SEC. We may have created a mapping symbol before a zero byte
630 alignment; remove it if there's a mapping symbol after the
634 riscv_check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
,
636 void *dummy ATTRIBUTE_UNUSED
)
638 segment_info_type
*seginfo
= seg_info (sec
);
641 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
644 for (fragp
= seginfo
->frchainP
->frch_root
;
646 fragp
= fragp
->fr_next
)
648 symbolS
*last
= fragp
->tc_frag_data
.last_map_symbol
;
649 fragS
*next
= fragp
->fr_next
;
651 if (last
== NULL
|| next
== NULL
)
654 /* Check the last mapping symbol if it is at the boundary of
656 if (S_GET_VALUE (last
) < next
->fr_address
)
658 know (S_GET_VALUE (last
) == next
->fr_address
);
662 symbolS
*next_first
= next
->tc_frag_data
.first_map_symbol
;
663 if (next_first
!= NULL
)
665 /* The last mapping symbol overlaps with another one
666 which at the start of the next frag.
668 Please see the gas/testsuite/gas/riscv/mapping.s:
669 .text.zero.fill.align.A and .text.zero.fill.align.B. */
670 know (S_GET_VALUE (last
) == S_GET_VALUE (next_first
));
671 symbolS
*removed
= last
;
672 if (strncmp (S_GET_NAME (last
), "$xrv", 4) == 0
673 && strcmp (S_GET_NAME (next_first
), "$x") == 0)
674 removed
= next_first
;
675 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
679 if (next
->fr_next
== NULL
)
681 /* The last mapping symbol is at the end of the section.
683 Please see the gas/testsuite/gas/riscv/mapping.s:
684 .text.last.section. */
685 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
686 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
690 /* Since we may have empty frags without any mapping symbols,
691 keep looking until the non-empty frag. */
692 if (next
->fr_address
!= next
->fr_next
->fr_address
)
695 next
= next
->fr_next
;
697 while (next
!= NULL
);
701 /* The default target format to use. */
704 riscv_target_format (void)
706 if (target_big_endian
)
707 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
709 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
712 /* Return the length of instruction INSN. */
714 static inline unsigned int
715 insn_length (const struct riscv_cl_insn
*insn
)
717 return riscv_insn_length (insn
->insn_opcode
);
720 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
723 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
726 insn
->insn_opcode
= mo
->match
;
727 insn
->insn_long_opcode
[0] = 0;
733 /* Install INSN at the location specified by its "frag" and "where" fields. */
736 install_insn (const struct riscv_cl_insn
*insn
)
738 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
739 if (insn
->insn_long_opcode
[0] != 0)
740 memcpy (f
, insn
->insn_long_opcode
, insn_length (insn
));
742 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
745 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
746 and install the opcode in the new location. */
749 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
753 if (insn
->fixp
!= NULL
)
755 insn
->fixp
->fx_frag
= frag
;
756 insn
->fixp
->fx_where
= where
;
761 /* Add INSN to the end of the output. */
764 add_fixed_insn (struct riscv_cl_insn
*insn
)
766 char *f
= frag_more (insn_length (insn
));
767 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
771 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
772 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
774 frag_grow (max_chars
);
775 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
776 frag_var (rs_machine_dependent
, max_chars
, var
,
777 subtype
, symbol
, offset
, NULL
);
780 /* Compute the length of a branch sequence, and adjust the stored length
781 accordingly. If FRAGP is NULL, the worst-case length is returned. */
784 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
786 int jump
, rvc
, length
= 8;
791 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
792 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
793 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
795 /* Assume jumps are in range; the linker will catch any that aren't. */
796 length
= jump
? 4 : 8;
798 if (fragp
->fr_symbol
!= NULL
799 && S_IS_DEFINED (fragp
->fr_symbol
)
800 && !S_IS_WEAK (fragp
->fr_symbol
)
801 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
803 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
804 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
805 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
807 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
809 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
811 else if (!jump
&& rvc
)
816 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
821 /* Information about an opcode name, mnemonics and its value. */
828 /* List for all supported opcode name. */
829 static const struct opcode_name_t opcode_name_list
[] =
874 /* Hash table for lookup opcode name. */
875 static htab_t opcode_names_hash
= NULL
;
877 /* Initialization for hash table of opcode name. */
880 init_opcode_names_hash (void)
882 const struct opcode_name_t
*opcode
;
884 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
885 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
886 as_fatal (_("internal: duplicate %s"), opcode
->name
);
889 /* Find `s` is a valid opcode name or not, return the opcode name info
892 static const struct opcode_name_t
*
893 opcode_name_lookup (char **s
)
897 struct opcode_name_t
*o
;
899 /* Find end of name. */
901 if (is_name_beginner (*e
))
903 while (is_part_of_name (*e
))
906 /* Terminate name. */
910 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
912 /* Advance to next token if one was recognized. */
922 /* All RISC-V registers belong to one of these classes. */
934 static htab_t reg_names_hash
= NULL
;
935 static htab_t csr_extra_hash
= NULL
;
937 #define ENCODE_REG_HASH(cls, n) \
938 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
939 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
940 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
943 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
945 void *hash
= ENCODE_REG_HASH (class, n
);
946 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
947 as_fatal (_("internal: duplicate %s"), name
);
951 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
955 for (i
= 0; i
< n
; i
++)
956 hash_reg_name (class, names
[i
], i
);
959 /* Init hash table csr_extra_hash to handle CSR. */
962 riscv_init_csr_hash (const char *name
,
964 enum riscv_csr_class
class,
965 enum riscv_spec_class define_version
,
966 enum riscv_spec_class abort_version
)
968 struct riscv_csr_extra
*entry
, *pre_entry
;
969 bool need_enrty
= true;
972 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
973 while (need_enrty
&& entry
!= NULL
)
975 if (entry
->csr_class
== class
976 && entry
->address
== address
977 && entry
->define_version
== define_version
978 && entry
->abort_version
== abort_version
)
988 entry
= notes_alloc (sizeof (*entry
));
989 entry
->csr_class
= class;
990 entry
->address
= address
;
991 entry
->define_version
= define_version
;
992 entry
->abort_version
= abort_version
;
995 if (pre_entry
== NULL
)
996 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
998 pre_entry
->next
= entry
;
1001 /* Return the CSR address after checking the ISA dependency and
1002 the privileged spec version.
1004 There are one warning and two errors for CSR,
1006 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
1007 or the privileged spec, report warning only if -mcsr-check is set.
1008 Unknown CSR: the CSR has never been defined, report error.
1009 Improper CSR: the CSR number over the range (> 0xfff), report error. */
1012 riscv_csr_address (const char *csr_name
,
1013 struct riscv_csr_extra
*entry
)
1015 struct riscv_csr_extra
*saved_entry
= entry
;
1016 enum riscv_csr_class csr_class
= entry
->csr_class
;
1017 bool need_check_version
= false;
1018 bool is_rv32_only
= false;
1019 bool is_h_required
= false;
1020 const char* extension
= NULL
;
1024 case CSR_CLASS_I_32
:
1025 is_rv32_only
= true;
1028 need_check_version
= true;
1031 case CSR_CLASS_H_32
:
1032 is_rv32_only
= true;
1044 extension
= "zve32x";
1046 case CSR_CLASS_SMAIA_32
:
1047 is_rv32_only
= true;
1049 case CSR_CLASS_SMAIA
:
1050 extension
= "smaia";
1052 case CSR_CLASS_SMSTATEEN_32
:
1053 is_rv32_only
= true;
1055 case CSR_CLASS_SMSTATEEN
:
1056 extension
= "smstateen";
1058 case CSR_CLASS_SSAIA
:
1059 case CSR_CLASS_SSAIA_AND_H
:
1060 case CSR_CLASS_SSAIA_32
:
1061 case CSR_CLASS_SSAIA_AND_H_32
:
1062 is_rv32_only
= (csr_class
== CSR_CLASS_SSAIA_32
1063 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1064 is_h_required
= (csr_class
== CSR_CLASS_SSAIA_AND_H
1065 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1066 extension
= "ssaia";
1068 case CSR_CLASS_SSSTATEEN_AND_H_32
:
1069 is_rv32_only
= true;
1071 case CSR_CLASS_SSSTATEEN_AND_H
:
1072 is_h_required
= true;
1074 case CSR_CLASS_SSSTATEEN
:
1075 extension
= "ssstateen";
1077 case CSR_CLASS_SSCOFPMF_32
:
1078 is_rv32_only
= true;
1080 case CSR_CLASS_SSCOFPMF
:
1081 extension
= "sscofpmf";
1083 case CSR_CLASS_SSTC
:
1084 case CSR_CLASS_SSTC_AND_H
:
1085 case CSR_CLASS_SSTC_32
:
1086 case CSR_CLASS_SSTC_AND_H_32
:
1087 is_rv32_only
= (csr_class
== CSR_CLASS_SSTC_32
1088 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1089 is_h_required
= (csr_class
== CSR_CLASS_SSTC_AND_H
1090 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1093 case CSR_CLASS_DEBUG
:
1096 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
1099 if (riscv_opts
.csr_check
)
1101 if (is_rv32_only
&& xlen
!= 32)
1102 as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name
);
1103 if (is_h_required
&& !riscv_subset_supports (&riscv_rps_as
, "h"))
1104 as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name
);
1106 if (extension
!= NULL
1107 && !riscv_subset_supports (&riscv_rps_as
, extension
))
1108 as_warn (_("invalid CSR `%s', needs `%s' extension"),
1109 csr_name
, extension
);
1112 while (entry
!= NULL
)
1114 if (!need_check_version
1115 || (default_priv_spec
>= entry
->define_version
1116 && default_priv_spec
< entry
->abort_version
))
1118 /* Find the CSR according to the specific version. */
1119 return entry
->address
;
1121 entry
= entry
->next
;
1124 /* Can not find the CSR address from the chosen privileged version,
1125 so use the newly defined value. */
1126 if (riscv_opts
.csr_check
)
1128 const char *priv_name
= NULL
;
1129 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
1130 if (priv_name
!= NULL
)
1131 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
1132 csr_name
, priv_name
);
1135 return saved_entry
->address
;
1138 /* Return -1 if the CSR has never been defined. Otherwise, return
1142 reg_csr_lookup_internal (const char *s
)
1144 struct riscv_csr_extra
*r
=
1145 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
1150 return riscv_csr_address (s
, r
);
1154 reg_lookup_internal (const char *s
, enum reg_class
class)
1158 if (class == RCLASS_CSR
)
1159 return reg_csr_lookup_internal (s
);
1161 r
= str_hash_find (reg_names_hash
, s
);
1162 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
1165 if (riscv_subset_supports (&riscv_rps_as
, "e")
1166 && class == RCLASS_GPR
1167 && DECODE_REG_NUM (r
) > 15)
1170 return DECODE_REG_NUM (r
);
1174 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
1180 /* Find end of name. */
1182 if (is_name_beginner (*e
))
1184 while (is_part_of_name (*e
))
1187 /* Terminate name. */
1191 /* Look for the register. Advance to next token if one was recognized. */
1192 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
1202 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
1204 const char *p
= strchr (*s
, ',');
1205 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
1210 for (i
= 0; i
< size
; i
++)
1211 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0
1212 && array
[i
][len
] == '\0')
1222 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1223 #define USE_IMM(n, s) \
1224 (used_bits |= ((insn_t)((1ull<<n)-1) << (s)))
1226 /* For consistency checking, verify that all bits are specified either
1227 by the match/mask part of the instruction definition, or by the
1228 operand list. The `length` could be the actual instruction length or
1229 0 for auto-detection. */
1232 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1234 const char *oparg
, *opargStart
;
1235 insn_t used_bits
= opc
->mask
;
1237 insn_t required_bits
;
1240 length
= riscv_insn_length (opc
->match
);
1241 /* We don't support instructions longer than 64-bits yet. */
1244 insn_width
= 8 * length
;
1246 required_bits
= ((insn_t
)~0ULL) >> (64 - insn_width
);
1248 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1250 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1251 opc
->name
, opc
->args
);
1255 for (oparg
= opc
->args
; *oparg
; ++oparg
)
1263 case 'U': break; /* CRS1, constrained to equal RD. */
1264 case 'c': break; /* CRS1, constrained to equal sp. */
1265 case 'T': /* CRS2, floating point. */
1266 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1267 case 'S': /* CRS1S, floating point. */
1268 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1269 case 'w': break; /* CRS1S, constrained to equal RD. */
1270 case 'D': /* CRS2S, floating point. */
1271 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1272 case 'x': break; /* CRS2S, constrained to equal RD. */
1273 case 'z': break; /* CRS2S, constrained to be x0. */
1274 case '>': /* CITYPE immediate, compressed shift. */
1275 case 'u': /* CITYPE immediate, compressed lui. */
1276 case 'v': /* CITYPE immediate, li to compressed lui. */
1277 case 'o': /* CITYPE immediate, allow zero. */
1278 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1279 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1280 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1281 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1282 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1283 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1284 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1285 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1286 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1287 /* CLTYPE and CSTYPE have the same immediate encoding. */
1288 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1289 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1290 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1291 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1292 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1293 case 'F': /* Compressed funct for .insn directive. */
1296 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1297 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1298 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1299 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1301 goto unknown_validate_operand
;
1305 goto unknown_validate_operand
;
1307 break; /* end RVC */
1312 case 'f': USE_BITS (OP_MASK_VD
, OP_SH_VD
); break;
1313 case 'e': USE_BITS (OP_MASK_VWD
, OP_SH_VWD
); break;
1314 case 's': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
); break;
1315 case 't': USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1316 case 'u': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1317 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1318 case 'v': USE_BITS (OP_MASK_VD
, OP_SH_VD
);
1319 USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1320 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1322 case 'b': used_bits
|= ENCODE_RVV_VB_IMM (-1U); break;
1323 case 'c': used_bits
|= ENCODE_RVV_VC_IMM (-1U); break;
1326 case 'k': USE_BITS (OP_MASK_VIMM
, OP_SH_VIMM
); break;
1327 case 'm': USE_BITS (OP_MASK_VMASK
, OP_SH_VMASK
); break;
1328 case 'M': break; /* Macro operand, must be a mask register. */
1329 case 'T': break; /* Macro operand, must be a vector register. */
1331 goto unknown_validate_operand
;
1333 break; /* end RVV */
1337 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1338 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1339 case 'A': break; /* Macro operand, must be symbol. */
1340 case 'B': break; /* Macro operand, must be symbol or constant. */
1341 case 'c': break; /* Macro operand, must be symbol or constant. */
1342 case 'I': break; /* Macro operand, must be constant. */
1343 case 'D': /* RD, floating point. */
1344 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1345 case 'y': USE_BITS (OP_MASK_BS
, OP_SH_BS
); break;
1346 case 'Y': USE_BITS (OP_MASK_RNUM
, OP_SH_RNUM
); break;
1347 case 'Z': /* RS1, CSR number. */
1348 case 'S': /* RS1, floating point. */
1349 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1350 case 'U': /* RS1 and RS2 are the same, floating point. */
1351 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1353 case 'T': /* RS2, floating point. */
1354 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1355 case 'R': /* RS3, floating point. */
1356 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1357 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1358 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1359 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1360 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1361 case 'o': /* ITYPE immediate, load displacement. */
1362 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1363 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1364 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1365 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1366 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1367 case 'z': break; /* Zero immediate. */
1368 case '[': break; /* Unused operand. */
1369 case ']': break; /* Unused operand. */
1370 case '0': break; /* AMO displacement, must to zero. */
1371 case '1': break; /* Relaxation operand. */
1372 case 'F': /* Funct for .insn directive. */
1375 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1376 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1377 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1379 goto unknown_validate_operand
;
1382 case 'O': /* Opcode for .insn directive. */
1385 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1386 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1388 goto unknown_validate_operand
;
1391 case 'W': /* Various operands. */
1397 case 'f': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1399 goto unknown_validate_operand
;
1403 goto unknown_validate_operand
;
1406 case 'X': /* Integer immediate. */
1413 case 'l': /* Literal. */
1414 oparg
+= strcspn(oparg
, ",") - 1;
1416 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
1418 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
1421 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1423 goto unknown_validate_operand
;
1424 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1430 goto unknown_validate_operand
;
1435 unknown_validate_operand
:
1436 as_bad (_("internal: bad RISC-V opcode "
1437 "(unknown operand type `%s'): %s %s"),
1438 opargStart
, opc
->name
, opc
->args
);
1443 if (used_bits
!= required_bits
)
1445 as_bad (_("internal: bad RISC-V opcode "
1446 "(bits %#llx undefined or invalid): %s %s"),
1447 (unsigned long long)(used_bits
^ required_bits
),
1448 opc
->name
, opc
->args
);
1456 struct percent_op_match
1459 bfd_reloc_code_real_type reloc
;
1462 /* Common hash table initialization function for instruction and .insn
1466 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1467 bool insn_directive_p
)
1471 htab_t hash
= str_htab_create ();
1472 while (opcodes
[i
].name
)
1474 const char *name
= opcodes
[i
].name
;
1475 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1476 as_fatal (_("internal: duplicate %s"), name
);
1480 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1482 if (insn_directive_p
)
1483 length
= ((name
[0] == 'c') ? 2 : 4);
1485 length
= 0; /* Let assembler determine the length. */
1486 if (!validate_riscv_insn (&opcodes
[i
], length
))
1487 as_fatal (_("internal: broken assembler. "
1488 "No assembly attempted"));
1491 gas_assert (!insn_directive_p
);
1494 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1500 /* This function is called once, at assembler startup time. It should set up
1501 all the tables, etc. that the MD part of the assembler will need. */
1506 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1508 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1509 as_warn (_("could not set architecture and machine"));
1511 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1512 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1514 reg_names_hash
= str_htab_create ();
1515 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1516 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1517 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1518 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1519 hash_reg_names (RCLASS_VECR
, riscv_vecr_names_numeric
, NVECR
);
1520 hash_reg_names (RCLASS_VECM
, riscv_vecm_names_numeric
, NVECM
);
1521 /* Add "fp" as an alias for "s0". */
1522 hash_reg_name (RCLASS_GPR
, "fp", 8);
1524 /* Create and insert CSR hash tables. */
1525 csr_extra_hash
= str_htab_create ();
1526 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1527 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1528 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1529 DECLARE_CSR(name, num, class, define_version, abort_version);
1530 #include "opcode/riscv-opc.h"
1533 opcode_names_hash
= str_htab_create ();
1534 init_opcode_names_hash ();
1536 /* Set the default alignment for the text section. */
1537 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1541 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1548 case BFD_RELOC_RISCV_HI20
:
1549 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1551 case BFD_RELOC_RISCV_LO12_S
:
1552 return ENCODE_STYPE_IMM (value
);
1554 case BFD_RELOC_RISCV_LO12_I
:
1555 return ENCODE_ITYPE_IMM (value
);
1562 /* Output an instruction. IP is the instruction information.
1563 ADDRESS_EXPR is an operand of the instruction to be used with
1567 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1568 bfd_reloc_code_real_type reloc_type
)
1570 dwarf2_emit_insn (0);
1572 if (reloc_type
!= BFD_RELOC_UNUSED
)
1574 reloc_howto_type
*howto
;
1576 gas_assert (address_expr
);
1577 if (reloc_type
== BFD_RELOC_12_PCREL
1578 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1580 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1581 int best_case
= insn_length (ip
);
1582 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1584 if (now_seg
== absolute_section
)
1586 as_bad (_("relaxable branches not supported in absolute section"));
1590 add_relaxed_insn (ip
, worst_case
, best_case
,
1591 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1592 address_expr
->X_add_symbol
,
1593 address_expr
->X_add_number
);
1598 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1600 as_bad (_("internal: unsupported RISC-V relocation number %d"),
1603 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1604 bfd_get_reloc_size (howto
),
1605 address_expr
, false, reloc_type
);
1607 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1611 add_fixed_insn (ip
);
1613 /* We need to start a new frag after any instruction that can be
1614 optimized away or compressed by the linker during relaxation, to prevent
1615 the assembler from computing static offsets across such an instruction.
1616 This is necessary to get correct EH info. */
1617 if (reloc_type
== BFD_RELOC_RISCV_HI20
1618 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1619 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1620 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1622 frag_wane (frag_now
);
1627 /* Build an instruction created by a macro expansion. This is passed
1628 a pointer to the count of instructions created so far, an expression,
1629 the name of the instruction to build, an operand format string, and
1630 corresponding arguments. */
1633 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1635 const struct riscv_opcode
*mo
;
1636 struct riscv_cl_insn insn
;
1637 bfd_reloc_code_real_type r
;
1639 const char *fmtStart
;
1641 va_start (args
, fmt
);
1643 r
= BFD_RELOC_UNUSED
;
1644 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1647 /* Find a non-RVC variant of the instruction. append_insn will compress
1649 while (riscv_insn_length (mo
->match
) < 4)
1651 gas_assert (strcmp (name
, mo
->name
) == 0);
1653 create_insn (&insn
, mo
);
1663 INSERT_OPERAND (VD
, insn
, va_arg (args
, int));
1666 INSERT_OPERAND (VS1
, insn
, va_arg (args
, int));
1669 INSERT_OPERAND (VS2
, insn
, va_arg (args
, int));
1673 int reg
= va_arg (args
, int);
1676 INSERT_OPERAND (VMASK
, insn
, 1);
1681 INSERT_OPERAND (VMASK
, insn
, 0);
1685 goto unknown_macro_argument
;
1688 goto unknown_macro_argument
;
1693 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1696 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1699 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1705 gas_assert (ep
!= NULL
);
1706 r
= va_arg (args
, int);
1714 unknown_macro_argument
:
1715 as_fatal (_("internal: invalid macro argument `%s'"), fmtStart
);
1720 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1722 append_insn (&insn
, ep
, r
);
1725 /* Build an instruction created by a macro expansion. Like md_assemble but
1726 accept a printf-style format string and arguments. */
1729 md_assemblef (const char *format
, ...)
1735 va_start (ap
, format
);
1737 r
= vasprintf (&buf
, format
, ap
);
1740 as_fatal (_("internal: vasprintf failed"));
1748 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1752 normalize_constant_expr (expressionS
*ex
)
1756 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1757 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1758 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1762 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1763 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1766 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1769 if (ex
->X_op
== O_big
)
1770 as_bad (_("unsupported large constant"));
1771 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1772 as_bad (_("unknown CSR `%s'"),
1773 S_GET_NAME (ex
->X_add_symbol
));
1774 else if (ex
->X_op
!= O_constant
)
1775 as_bad (_("instruction %s requires absolute expression"),
1777 normalize_constant_expr (ex
);
1781 make_internal_label (void)
1783 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1787 /* Load an entry from the GOT. */
1790 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1791 const char *lo_insn
, const char *lo_pattern
,
1792 bfd_reloc_code_real_type hi_reloc
,
1793 bfd_reloc_code_real_type lo_reloc
)
1796 ep2
.X_op
= O_symbol
;
1797 ep2
.X_add_symbol
= make_internal_label ();
1798 ep2
.X_add_number
= 0;
1800 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1801 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1805 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1806 bfd_reloc_code_real_type hi_reloc
,
1807 bfd_reloc_code_real_type lo_reloc
)
1809 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1813 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1814 bfd_reloc_code_real_type hi_reloc
,
1815 bfd_reloc_code_real_type lo_reloc
)
1817 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1820 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1823 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1824 bfd_reloc_code_real_type reloc
)
1826 /* Ensure the jalr is emitted to the same frag as the auipc. */
1828 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1829 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1830 /* See comment at end of append_insn. */
1831 frag_wane (frag_now
);
1835 /* Load an integer constant into a register. */
1838 load_const (int reg
, expressionS
*ep
)
1840 int shift
= RISCV_IMM_BITS
;
1841 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1842 expressionS upper
= *ep
, lower
= *ep
;
1843 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1844 upper
.X_add_number
-= lower
.X_add_number
;
1846 if (ep
->X_op
!= O_constant
)
1848 as_bad (_("unsupported large constant"));
1852 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1854 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1855 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1858 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1859 load_const (reg
, &upper
);
1861 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1862 if (lower
.X_add_number
!= 0)
1863 md_assemblef ("addi x%d, x%d, %" PRId64
, reg
, reg
,
1864 (int64_t) lower
.X_add_number
);
1868 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1871 if (upper
.X_add_number
!= 0)
1873 /* Discard low part and zero-extend upper immediate. */
1874 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1876 md_assemblef ("lui x%d, 0x%" PRIx64
, reg
, (uint64_t) upper_imm
);
1880 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1881 md_assemblef ("%s x%d, x%d, %" PRId64
, ADD32_INSN
, reg
, hi_reg
,
1882 (int64_t) lower
.X_add_number
);
1886 /* Zero extend and sign extend byte/half-word/word. */
1889 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1893 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1894 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1898 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1899 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1903 /* Expand RISC-V Vector macros into one or more instructions. */
1906 vector_macro (struct riscv_cl_insn
*ip
)
1908 int vd
= (ip
->insn_opcode
>> OP_SH_VD
) & OP_MASK_VD
;
1909 int vs1
= (ip
->insn_opcode
>> OP_SH_VS1
) & OP_MASK_VS1
;
1910 int vs2
= (ip
->insn_opcode
>> OP_SH_VS2
) & OP_MASK_VS2
;
1911 int vm
= (ip
->insn_opcode
>> OP_SH_VMASK
) & OP_MASK_VMASK
;
1912 int vtemp
= (ip
->insn_opcode
>> OP_SH_VFUNCT6
) & OP_MASK_VFUNCT6
;
1913 int mask
= ip
->insn_mo
->mask
;
1921 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1922 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1927 /* Masked. Have vtemp to avoid overlap constraints. */
1930 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1931 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1935 /* Preserve the value of vd if not updating by vm. */
1936 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1937 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1938 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1939 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1944 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1945 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1946 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1949 as_bad (_("must provide temp if destination overlaps mask"));
1956 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1957 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1962 /* Masked. Have vtemp to avoid overlap constraints. */
1965 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1966 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1970 /* Preserve the value of vd if not updating by vm. */
1971 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1972 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1973 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1974 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1979 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1980 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1981 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1984 as_bad (_("must provide temp if destination overlaps mask"));
1992 /* Expand RISC-V assembly macros into one or more instructions. */
1995 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1996 bfd_reloc_code_real_type
*imm_reloc
)
1998 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1999 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
2000 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
2001 int mask
= ip
->insn_mo
->mask
;
2006 load_const (rd
, imm_expr
);
2011 /* Load the address of a symbol into a register. */
2012 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
2013 as_bad (_("offset too large"));
2015 if (imm_expr
->X_op
== O_constant
)
2016 load_const (rd
, imm_expr
);
2017 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
2018 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2019 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2020 else /* Local PIC symbol, or any non-PIC symbol. */
2021 pcrel_load (rd
, rd
, imm_expr
, "addi",
2022 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2026 pcrel_load (rd
, rd
, imm_expr
, "addi",
2027 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2031 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2032 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2036 pcrel_load (rd
, rd
, imm_expr
, "lb",
2037 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2041 pcrel_load (rd
, rd
, imm_expr
, "lbu",
2042 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2046 pcrel_load (rd
, rd
, imm_expr
, "lh",
2047 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2051 pcrel_load (rd
, rd
, imm_expr
, "lhu",
2052 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2056 pcrel_load (rd
, rd
, imm_expr
, "lw",
2057 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2061 pcrel_load (rd
, rd
, imm_expr
, "lwu",
2062 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2066 pcrel_load (rd
, rd
, imm_expr
, "ld",
2067 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2071 pcrel_load (rd
, rs1
, imm_expr
, "flw",
2072 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2076 pcrel_load (rd
, rs1
, imm_expr
, "fld",
2077 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2081 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
2082 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2086 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
2087 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2091 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
2092 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2096 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
2097 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2101 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
2102 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2106 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
2107 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2111 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
2115 riscv_ext (rd
, rs1
, xlen
- 16, false);
2119 riscv_ext (rd
, rs1
, xlen
- 32, false);
2123 riscv_ext (rd
, rs1
, xlen
- 8, true);
2127 riscv_ext (rd
, rs1
, xlen
- 16, true);
2136 pcrel_load (rd
, rs1
, imm_expr
, "flh",
2137 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2140 pcrel_store (rs2
, rs1
, imm_expr
, "fsh",
2141 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2145 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
2150 static const struct percent_op_match percent_op_utype
[] =
2152 {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
2153 {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
2154 {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
2155 {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
2156 {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
2157 {"hi", BFD_RELOC_RISCV_HI20
},
2161 static const struct percent_op_match percent_op_itype
[] =
2163 {"lo", BFD_RELOC_RISCV_LO12_I
},
2164 {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
2165 {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
2169 static const struct percent_op_match percent_op_stype
[] =
2171 {"lo", BFD_RELOC_RISCV_LO12_S
},
2172 {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
2173 {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
2177 static const struct percent_op_match percent_op_rtype
[] =
2179 {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
2183 static const struct percent_op_match percent_op_null
[] =
2188 /* Return true if *STR points to a relocation operator. When returning true,
2189 move *STR over the operator and store its relocation code in *RELOC.
2190 Leave both *STR and *RELOC alone when returning false. */
2193 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
2194 const struct percent_op_match
*percent_op
)
2196 for ( ; percent_op
->str
; percent_op
++)
2197 if (strncasecmp (*str
+ 1, percent_op
->str
, strlen (percent_op
->str
)) == 0)
2199 size_t len
= 1 + strlen (percent_op
->str
);
2201 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
2205 *reloc
= percent_op
->reloc
;
2207 /* Check whether the output BFD supports this relocation.
2208 If not, issue an error and fall back on something safe. */
2209 if (*reloc
!= BFD_RELOC_UNUSED
2210 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
2212 as_bad ("internal: relocation %s isn't supported by the "
2213 "current ABI", percent_op
->str
);
2214 *reloc
= BFD_RELOC_UNUSED
;
2222 my_getExpression (expressionS
*ep
, char *str
)
2226 save_in
= input_line_pointer
;
2227 input_line_pointer
= str
;
2229 expr_parse_end
= input_line_pointer
;
2230 input_line_pointer
= save_in
;
2233 /* Parse string STR as a 16-bit relocatable operand. Store the
2234 expression in *EP and the relocation, if any, in RELOC.
2235 Return the number of relocation operators used (0 or 1).
2237 On exit, EXPR_PARSE_END points to the first character after the
2241 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2242 char *str
, const struct percent_op_match
*percent_op
)
2245 unsigned crux_depth
, str_depth
, regno
;
2248 /* First, check for integer registers. No callers can accept a reg, but
2249 we need to avoid accidentally creating a useless undefined symbol below,
2250 if this is an instruction pattern that can't match. A glibc build fails
2251 if this is removed. */
2252 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
2254 ep
->X_op
= O_register
;
2255 ep
->X_add_number
= regno
;
2256 expr_parse_end
= str
;
2260 /* Search for the start of the main expression.
2262 End the loop with CRUX pointing to the start of the main expression and
2263 with CRUX_DEPTH containing the number of open brackets at that point. */
2270 crux_depth
= str_depth
;
2272 /* Skip over whitespace and brackets, keeping count of the number
2274 while (*str
== ' ' || *str
== '\t' || *str
== '(')
2280 && parse_relocation (&str
, reloc
, percent_op
));
2282 my_getExpression (ep
, crux
);
2283 str
= expr_parse_end
;
2285 /* Match every open bracket. */
2286 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
2291 as_bad ("unclosed '('");
2293 expr_parse_end
= str
;
2298 /* Parse opcode name, could be an mnemonics or number. */
2301 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2302 char *str
, const struct percent_op_match
*percent_op
)
2304 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
2308 ep
->X_op
= O_constant
;
2309 ep
->X_add_number
= o
->val
;
2313 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
2316 /* Parse string STR as a vsetvli operand. Store the expression in *EP.
2317 On exit, EXPR_PARSE_END points to the first character after the
2321 my_getVsetvliExpression (expressionS
*ep
, char *str
)
2323 unsigned int vsew_value
= 0, vlmul_value
= 0;
2324 unsigned int vta_value
= 0, vma_value
= 0;
2325 bfd_boolean vsew_found
= FALSE
, vlmul_found
= FALSE
;
2326 bfd_boolean vta_found
= FALSE
, vma_found
= FALSE
;
2328 if (arg_lookup (&str
, riscv_vsew
, ARRAY_SIZE (riscv_vsew
), &vsew_value
))
2333 as_bad (_("multiple vsew constants"));
2336 if (arg_lookup (&str
, riscv_vlmul
, ARRAY_SIZE (riscv_vlmul
), &vlmul_value
))
2341 as_bad (_("multiple vlmul constants"));
2344 if (arg_lookup (&str
, riscv_vta
, ARRAY_SIZE (riscv_vta
), &vta_value
))
2349 as_bad (_("multiple vta constants"));
2352 if (arg_lookup (&str
, riscv_vma
, ARRAY_SIZE (riscv_vma
), &vma_value
))
2357 as_bad (_("multiple vma constants"));
2361 if (vsew_found
|| vlmul_found
|| vta_found
|| vma_found
)
2363 ep
->X_op
= O_constant
;
2364 ep
->X_add_number
= (vlmul_value
<< OP_SH_VLMUL
)
2365 | (vsew_value
<< OP_SH_VSEW
)
2366 | (vta_value
<< OP_SH_VTA
)
2367 | (vma_value
<< OP_SH_VMA
);
2368 expr_parse_end
= str
;
2372 my_getExpression (ep
, str
);
2373 str
= expr_parse_end
;
2377 /* Detect and handle implicitly zero load-store offsets. For example,
2378 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such
2379 an implicit offset was detected. */
2382 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
2384 /* Check whether there is only a single bracketed expression left.
2385 If so, it must be the base register and the constant must be zero. */
2386 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
2388 ep
->X_op
= O_constant
;
2389 ep
->X_add_number
= 0;
2396 /* All RISC-V CSR instructions belong to one of these classes. */
2405 /* Return which CSR instruction is checking. */
2407 static enum csr_insn_type
2408 riscv_csr_insn_type (insn_t insn
)
2410 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
2411 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
2413 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
2414 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
2416 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
2417 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
2420 return INSN_NOT_CSR
;
2423 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
2424 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
2425 CSR address is 0x3. */
2428 riscv_csr_read_only_check (insn_t insn
)
2430 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
2431 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
2432 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
2433 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
2436 && (((csr_insn
== INSN_CSRRS
2437 || csr_insn
== INSN_CSRRC
)
2439 || csr_insn
== INSN_CSRRW
))
2445 /* Return true if it is a privileged instruction. Otherwise, return false.
2447 uret is actually a N-ext instruction. So it is better to regard it as
2448 an user instruction rather than the priv instruction.
2450 hret is used to return from traps in H-mode. H-mode is removed since
2451 the v1.10 priv spec, but probably be added in the new hypervisor spec.
2452 Therefore, hret should be controlled by the hypervisor spec rather than
2453 priv spec in the future.
2455 dret is defined in the debug spec, so it should be checked in the future,
2459 riscv_is_priv_insn (insn_t insn
)
2461 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
2462 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
2463 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
2464 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
2465 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
2466 check it here to keep the compatible. */
2467 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
2470 /* This routine assembles an instruction into its binary format. As a
2471 side effect, it sets the global variable imm_reloc to the type of
2472 relocation to do if one of the operands is an address expression. */
2474 static struct riscv_ip_error
2475 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
2476 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
2478 /* The operand string defined in the riscv_opcodes. */
2479 const char *oparg
, *opargStart
;
2480 /* The parsed operands from assembly. */
2481 char *asarg
, *asargStart
;
2483 struct riscv_opcode
*insn
;
2485 const struct percent_op_match
*p
;
2486 struct riscv_ip_error error
;
2487 error
.msg
= "unrecognized opcode";
2488 error
.statement
= str
;
2489 error
.missing_ext
= NULL
;
2490 /* Indicate we are assembling instruction with CSR. */
2491 bool insn_with_csr
= false;
2493 /* Parse the name of the instruction. Terminate the string if whitespace
2494 is found so that str_hash_find only sees the name part of the string. */
2495 for (asarg
= str
; *asarg
!= '\0'; ++asarg
)
2496 if (ISSPACE (*asarg
))
2503 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2506 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2508 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2511 if (!riscv_multi_subset_supports (&riscv_rps_as
, insn
->insn_class
))
2513 error
.missing_ext
= riscv_multi_subset_supports_ext (&riscv_rps_as
,
2518 /* Reset error message of the previous round. */
2519 error
.msg
= _("illegal operands");
2520 error
.missing_ext
= NULL
;
2521 create_insn (ip
, insn
);
2523 imm_expr
->X_op
= O_absent
;
2524 *imm_reloc
= BFD_RELOC_UNUSED
;
2525 p
= percent_op_itype
;
2527 for (oparg
= insn
->args
;; ++oparg
)
2530 asarg
+= strspn (asarg
, " \t");
2533 case '\0': /* End of args. */
2534 if (insn
->pinfo
!= INSN_MACRO
)
2536 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2539 /* For .insn, insn->match and insn->mask are 0. */
2540 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2546 if (riscv_is_priv_insn (ip
->insn_opcode
))
2547 explicit_priv_attr
= true;
2549 /* Check if we write a read-only CSR by the CSR
2552 && riscv_opts
.csr_check
2553 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2555 /* Restore the character in advance, since we want to
2556 report the detailed warning message here. */
2558 *(asargStart
- 1) = save_c
;
2559 as_warn (_("read-only CSR is written `%s'"), str
);
2560 insn_with_csr
= false;
2563 /* The (segmant) load and store with EEW 64 cannot be used
2564 when zve32x is enabled. */
2565 if (ip
->insn_mo
->pinfo
& INSN_V_EEW64
2566 && riscv_subset_supports (&riscv_rps_as
, "zve32x")
2567 && !riscv_subset_supports (&riscv_rps_as
, "zve64x"))
2569 error
.msg
= _("illegal opcode for zve32x");
2575 /* Successful assembly. */
2577 insn_with_csr
= false;
2583 case 's': /* RS1 x8-x15. */
2584 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2585 || !(regno
>= 8 && regno
<= 15))
2587 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2589 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2590 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2591 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2594 case 't': /* RS2 x8-x15. */
2595 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2596 || !(regno
>= 8 && regno
<= 15))
2598 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2600 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2601 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2602 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2605 case 'U': /* RS1, constrained to equal RD. */
2606 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2607 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2611 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2613 INSERT_OPERAND (CRS2
, *ip
, regno
);
2615 case 'c': /* RS1, constrained to equal sp. */
2616 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2620 case 'z': /* RS2, constrained to equal x0. */
2621 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2625 case '>': /* Shift amount, 0 - (XLEN-1). */
2626 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2627 || imm_expr
->X_op
!= O_constant
2628 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2630 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2632 asarg
= expr_parse_end
;
2633 imm_expr
->X_op
= O_absent
;
2636 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2637 || imm_expr
->X_op
!= O_constant
2638 || imm_expr
->X_add_number
< 0
2639 || imm_expr
->X_add_number
>= 32
2640 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2642 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2645 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2646 || imm_expr
->X_op
!= O_constant
2647 || imm_expr
->X_add_number
< 0
2648 || imm_expr
->X_add_number
>= 64
2649 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2651 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2654 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2655 || imm_expr
->X_op
!= O_constant
2656 || imm_expr
->X_add_number
< 0
2657 || imm_expr
->X_add_number
>= 256
2658 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2660 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2663 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2664 || imm_expr
->X_op
!= O_constant
2665 || imm_expr
->X_add_number
== 0
2666 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2668 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2671 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2673 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2674 || imm_expr
->X_op
!= O_constant
2675 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2677 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2680 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2682 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2683 || imm_expr
->X_op
!= O_constant
2684 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2686 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2689 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2691 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2692 || imm_expr
->X_op
!= O_constant
2693 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2696 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2699 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2701 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2702 || imm_expr
->X_op
!= O_constant
2703 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2706 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2709 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2710 || imm_expr
->X_op
!= O_constant
2711 /* C.addiw, c.li, and c.andi allow zero immediate.
2712 C.addi allows zero immediate as hint. Otherwise this
2714 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2716 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2719 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2720 || imm_expr
->X_op
!= O_constant
2721 || imm_expr
->X_add_number
== 0
2722 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2725 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2728 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2729 || imm_expr
->X_op
!= O_constant
2730 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2733 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2736 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2738 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2739 || imm_expr
->X_op
!= O_constant
2740 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2743 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2746 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2748 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2749 || imm_expr
->X_op
!= O_constant
2750 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2753 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2756 p
= percent_op_utype
;
2757 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
2760 if (imm_expr
->X_op
!= O_constant
2761 || imm_expr
->X_add_number
<= 0
2762 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2763 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2764 && (imm_expr
->X_add_number
<
2765 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2767 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2770 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2771 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2772 || ((int32_t)imm_expr
->X_add_number
2773 != imm_expr
->X_add_number
))
2775 imm_expr
->X_add_number
=
2776 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2781 if (oparg
== insn
->args
+ 1)
2782 goto jump_check_gpr
;
2784 case 'S': /* Floating-point RS1 x8-x15. */
2785 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2786 || !(regno
>= 8 && regno
<= 15))
2788 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2790 case 'D': /* Floating-point RS2 x8-x15. */
2791 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2792 || !(regno
>= 8 && regno
<= 15))
2794 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2796 case 'T': /* Floating-point RS2. */
2797 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
))
2799 INSERT_OPERAND (CRS2
, *ip
, regno
);
2805 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2806 || imm_expr
->X_op
!= O_constant
2807 || imm_expr
->X_add_number
< 0
2808 || imm_expr
->X_add_number
>= 64)
2810 as_bad (_("bad value for compressed funct6 "
2811 "field, value must be 0...63"));
2814 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2815 imm_expr
->X_op
= O_absent
;
2816 asarg
= expr_parse_end
;
2820 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2821 || imm_expr
->X_op
!= O_constant
2822 || imm_expr
->X_add_number
< 0
2823 || imm_expr
->X_add_number
>= 16)
2825 as_bad (_("bad value for compressed funct4 "
2826 "field, value must be 0...15"));
2829 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2830 imm_expr
->X_op
= O_absent
;
2831 asarg
= expr_parse_end
;
2835 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2836 || imm_expr
->X_op
!= O_constant
2837 || imm_expr
->X_add_number
< 0
2838 || imm_expr
->X_add_number
>= 8)
2840 as_bad (_("bad value for compressed funct3 "
2841 "field, value must be 0...7"));
2844 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2845 imm_expr
->X_op
= O_absent
;
2846 asarg
= expr_parse_end
;
2850 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2851 || imm_expr
->X_op
!= O_constant
2852 || imm_expr
->X_add_number
< 0
2853 || imm_expr
->X_add_number
>= 4)
2855 as_bad (_("bad value for compressed funct2 "
2856 "field, value must be 0...3"));
2859 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2860 imm_expr
->X_op
= O_absent
;
2861 asarg
= expr_parse_end
;
2865 goto unknown_riscv_ip_operand
;
2870 goto unknown_riscv_ip_operand
;
2872 break; /* end RVC */
2878 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2880 INSERT_OPERAND (VD
, *ip
, regno
);
2883 case 'e': /* AMO VD */
2884 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
) && regno
== 0)
2885 INSERT_OPERAND (VWD
, *ip
, 0);
2886 else if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2888 INSERT_OPERAND (VWD
, *ip
, 1);
2889 INSERT_OPERAND (VD
, *ip
, regno
);
2895 case 'f': /* AMO VS3 */
2896 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2898 if (!EXTRACT_OPERAND (VWD
, ip
->insn_opcode
))
2899 INSERT_OPERAND (VD
, *ip
, regno
);
2902 /* VS3 must match VD. */
2903 if (EXTRACT_OPERAND (VD
, ip
->insn_opcode
) != regno
)
2909 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2911 INSERT_OPERAND (VS1
, *ip
, regno
);
2915 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2917 INSERT_OPERAND (VS2
, *ip
, regno
);
2920 case 'u': /* VS1 == VS2 */
2921 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2923 INSERT_OPERAND (VS1
, *ip
, regno
);
2924 INSERT_OPERAND (VS2
, *ip
, regno
);
2927 case 'v': /* VD == VS1 == VS2 */
2928 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2930 INSERT_OPERAND (VD
, *ip
, regno
);
2931 INSERT_OPERAND (VS1
, *ip
, regno
);
2932 INSERT_OPERAND (VS2
, *ip
, regno
);
2935 /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
2936 and is used to choose vs1/rs1/frs1/imm or vs2 for
2937 v[f]merge. It use the same encoding as the vector mask
2940 if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
) && regno
== 0)
2944 case 'b': /* vtypei for vsetivli */
2945 my_getVsetvliExpression (imm_expr
, asarg
);
2946 check_absolute_expr (ip
, imm_expr
, FALSE
);
2947 if (!VALID_RVV_VB_IMM (imm_expr
->X_add_number
))
2948 as_bad (_("bad value for vsetivli immediate field, "
2949 "value must be 0..1023"));
2951 |= ENCODE_RVV_VB_IMM (imm_expr
->X_add_number
);
2952 imm_expr
->X_op
= O_absent
;
2953 asarg
= expr_parse_end
;
2956 case 'c': /* vtypei for vsetvli */
2957 my_getVsetvliExpression (imm_expr
, asarg
);
2958 check_absolute_expr (ip
, imm_expr
, FALSE
);
2959 if (!VALID_RVV_VC_IMM (imm_expr
->X_add_number
))
2960 as_bad (_("bad value for vsetvli immediate field, "
2961 "value must be 0..2047"));
2963 |= ENCODE_RVV_VC_IMM (imm_expr
->X_add_number
);
2964 imm_expr
->X_op
= O_absent
;
2965 asarg
= expr_parse_end
;
2968 case 'i': /* vector arith signed immediate */
2969 my_getExpression (imm_expr
, asarg
);
2970 check_absolute_expr (ip
, imm_expr
, FALSE
);
2971 if (imm_expr
->X_add_number
> 15
2972 || imm_expr
->X_add_number
< -16)
2973 as_bad (_("bad value for vector immediate field, "
2974 "value must be -16...15"));
2975 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2976 imm_expr
->X_op
= O_absent
;
2977 asarg
= expr_parse_end
;
2980 case 'j': /* vector arith unsigned immediate */
2981 my_getExpression (imm_expr
, asarg
);
2982 check_absolute_expr (ip
, imm_expr
, FALSE
);
2983 if (imm_expr
->X_add_number
< 0
2984 || imm_expr
->X_add_number
>= 32)
2985 as_bad (_("bad value for vector immediate field, "
2986 "value must be 0...31"));
2987 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2988 imm_expr
->X_op
= O_absent
;
2989 asarg
= expr_parse_end
;
2992 case 'k': /* vector arith signed immediate, minus 1 */
2993 my_getExpression (imm_expr
, asarg
);
2994 check_absolute_expr (ip
, imm_expr
, FALSE
);
2995 if (imm_expr
->X_add_number
> 16
2996 || imm_expr
->X_add_number
< -15)
2997 as_bad (_("bad value for vector immediate field, "
2998 "value must be -15...16"));
2999 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
- 1);
3000 imm_expr
->X_op
= O_absent
;
3001 asarg
= expr_parse_end
;
3004 case 'm': /* optional vector mask */
3007 INSERT_OPERAND (VMASK
, *ip
, 1);
3010 else if (*asarg
== ',' && asarg
++
3011 && reg_lookup (&asarg
, RCLASS_VECM
, ®no
)
3014 INSERT_OPERAND (VMASK
, *ip
, 0);
3019 case 'M': /* required vector mask */
3020 if (reg_lookup (&asarg
, RCLASS_VECM
, ®no
) && regno
== 0)
3022 INSERT_OPERAND (VMASK
, *ip
, 0);
3027 case 'T': /* vector macro temporary register */
3028 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
) || regno
== 0)
3030 /* Store it in the FUNCT6 field as we don't have anyplace
3031 else to store it. */
3032 INSERT_OPERAND (VFUNCT6
, *ip
, regno
);
3036 goto unknown_riscv_ip_operand
;
3038 break; /* end RVV */
3041 if (*asarg
++ == *oparg
)
3050 if (*asarg
++ == *oparg
)
3054 case '<': /* Shift amount, 0 - 31. */
3055 my_getExpression (imm_expr
, asarg
);
3056 check_absolute_expr (ip
, imm_expr
, false);
3057 if ((unsigned long) imm_expr
->X_add_number
> 31)
3058 as_bad (_("improper shift amount (%"PRIu64
")"),
3059 imm_expr
->X_add_number
);
3060 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
3061 imm_expr
->X_op
= O_absent
;
3062 asarg
= expr_parse_end
;
3065 case '>': /* Shift amount, 0 - (XLEN-1). */
3066 my_getExpression (imm_expr
, asarg
);
3067 check_absolute_expr (ip
, imm_expr
, false);
3068 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
3069 as_bad (_("improper shift amount (%"PRIu64
")"),
3070 imm_expr
->X_add_number
);
3071 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
3072 imm_expr
->X_op
= O_absent
;
3073 asarg
= expr_parse_end
;
3076 case 'Z': /* CSRRxI immediate. */
3077 my_getExpression (imm_expr
, asarg
);
3078 check_absolute_expr (ip
, imm_expr
, false);
3079 if ((unsigned long) imm_expr
->X_add_number
> 31)
3080 as_bad (_("improper CSRxI immediate (%"PRIu64
")"),
3081 imm_expr
->X_add_number
);
3082 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
3083 imm_expr
->X_op
= O_absent
;
3084 asarg
= expr_parse_end
;
3087 case 'E': /* Control register. */
3088 insn_with_csr
= true;
3089 explicit_priv_attr
= true;
3090 if (reg_lookup (&asarg
, RCLASS_CSR
, ®no
))
3091 INSERT_OPERAND (CSR
, *ip
, regno
);
3094 my_getExpression (imm_expr
, asarg
);
3095 check_absolute_expr (ip
, imm_expr
, true);
3096 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
3097 as_bad (_("improper CSR address (%"PRIu64
")"),
3098 imm_expr
->X_add_number
);
3099 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
3100 imm_expr
->X_op
= O_absent
;
3101 asarg
= expr_parse_end
;
3105 case 'm': /* Rounding mode. */
3106 if (arg_lookup (&asarg
, riscv_rm
,
3107 ARRAY_SIZE (riscv_rm
), ®no
))
3109 INSERT_OPERAND (RM
, *ip
, regno
);
3115 case 'Q': /* Fence predecessor/successor. */
3116 if (arg_lookup (&asarg
, riscv_pred_succ
,
3117 ARRAY_SIZE (riscv_pred_succ
), ®no
))
3120 INSERT_OPERAND (PRED
, *ip
, regno
);
3122 INSERT_OPERAND (SUCC
, *ip
, regno
);
3127 case 'd': /* Destination register. */
3128 case 's': /* Source register. */
3129 case 't': /* Target register. */
3131 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
3137 /* Now that we have assembled one operand, we use the args
3138 string to figure out where it goes in the instruction. */
3142 INSERT_OPERAND (RS1
, *ip
, regno
);
3145 INSERT_OPERAND (RD
, *ip
, regno
);
3148 INSERT_OPERAND (RS2
, *ip
, regno
);
3151 INSERT_OPERAND (RS3
, *ip
, regno
);
3158 case 'D': /* Floating point RD. */
3159 case 'S': /* Floating point RS1. */
3160 case 'T': /* Floating point RS2. */
3161 case 'U': /* Floating point RS1 and RS2. */
3162 case 'R': /* Floating point RS3. */
3163 if (reg_lookup (&asarg
,
3164 (riscv_subset_supports (&riscv_rps_as
, "zfinx")
3165 ? RCLASS_GPR
: RCLASS_FPR
), ®no
))
3173 INSERT_OPERAND (RD
, *ip
, regno
);
3176 INSERT_OPERAND (RS1
, *ip
, regno
);
3179 INSERT_OPERAND (RS1
, *ip
, regno
);
3182 INSERT_OPERAND (RS2
, *ip
, regno
);
3185 INSERT_OPERAND (RS3
, *ip
, regno
);
3193 my_getExpression (imm_expr
, asarg
);
3194 if (imm_expr
->X_op
!= O_big
3195 && imm_expr
->X_op
!= O_constant
)
3197 normalize_constant_expr (imm_expr
);
3198 asarg
= expr_parse_end
;
3202 my_getExpression (imm_expr
, asarg
);
3203 normalize_constant_expr (imm_expr
);
3204 /* The 'A' format specifier must be a symbol. */
3205 if (imm_expr
->X_op
!= O_symbol
)
3207 *imm_reloc
= BFD_RELOC_32
;
3208 asarg
= expr_parse_end
;
3212 my_getExpression (imm_expr
, asarg
);
3213 normalize_constant_expr (imm_expr
);
3214 /* The 'B' format specifier must be a symbol or a constant. */
3215 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
3217 if (imm_expr
->X_op
== O_symbol
)
3218 *imm_reloc
= BFD_RELOC_32
;
3219 asarg
= expr_parse_end
;
3222 case 'j': /* Sign-extended immediate. */
3223 p
= percent_op_itype
;
3224 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3226 case 'q': /* Store displacement. */
3227 p
= percent_op_stype
;
3228 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
3230 case 'o': /* Load displacement. */
3231 p
= percent_op_itype
;
3232 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3235 /* This is used for TLS, where the fourth operand is
3236 %tprel_add, to get a relocation applied to an add
3237 instruction, for relaxation to use. */
3238 p
= percent_op_rtype
;
3240 case '0': /* AMO displacement, which must be zero. */
3241 p
= percent_op_null
;
3243 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3246 /* If this value won't fit into a 16 bit offset, then go
3247 find a macro that will generate the 32 bit offset
3249 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3251 normalize_constant_expr (imm_expr
);
3252 if (imm_expr
->X_op
!= O_constant
3253 || (*oparg
== '0' && imm_expr
->X_add_number
!= 0)
3255 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
3256 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
3259 asarg
= expr_parse_end
;
3262 case 'p': /* PC-relative offset. */
3264 *imm_reloc
= BFD_RELOC_12_PCREL
;
3265 my_getExpression (imm_expr
, asarg
);
3266 asarg
= expr_parse_end
;
3269 case 'u': /* Upper 20 bits. */
3270 p
= percent_op_utype
;
3271 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3273 if (imm_expr
->X_op
!= O_constant
)
3276 if (imm_expr
->X_add_number
< 0
3277 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
3278 as_bad (_("lui expression not in range 0..1048575"));
3280 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
3281 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
3283 asarg
= expr_parse_end
;
3286 case 'a': /* 20-bit PC-relative offset. */
3287 /* Like in my_getSmallExpression() we need to avoid emitting
3288 a stray undefined symbol if the 1st JAL entry doesn't match,
3289 but the 2nd (with 2 operands) might. */
3290 if (oparg
== insn
->args
)
3294 if (reg_lookup (&asarg
, RCLASS_GPR
, NULL
)
3295 && (*asarg
== ',' || (ISSPACE (*asarg
) && asarg
[1] == ',')))
3300 my_getExpression (imm_expr
, asarg
);
3301 asarg
= expr_parse_end
;
3302 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
3306 my_getExpression (imm_expr
, asarg
);
3307 asarg
= expr_parse_end
;
3308 if (strcmp (asarg
, "@plt") == 0)
3310 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
3317 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3318 || imm_expr
->X_op
!= O_constant
3319 || imm_expr
->X_add_number
< 0
3320 || imm_expr
->X_add_number
>= 128
3321 || (imm_expr
->X_add_number
& 0x3) != 3)
3323 as_bad (_("bad value for opcode field, "
3324 "value must be 0...127 and "
3325 "lower 2 bits must be 0x3"));
3328 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
3329 imm_expr
->X_op
= O_absent
;
3330 asarg
= expr_parse_end
;
3334 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3335 || imm_expr
->X_op
!= O_constant
3336 || imm_expr
->X_add_number
< 0
3337 || imm_expr
->X_add_number
>= 3)
3339 as_bad (_("bad value for opcode field, "
3340 "value must be 0...2"));
3343 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
3344 imm_expr
->X_op
= O_absent
;
3345 asarg
= expr_parse_end
;
3349 goto unknown_riscv_ip_operand
;
3357 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3358 || imm_expr
->X_op
!= O_constant
3359 || imm_expr
->X_add_number
< 0
3360 || imm_expr
->X_add_number
>= 128)
3362 as_bad (_("bad value for funct7 field, "
3363 "value must be 0...127"));
3366 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
3367 imm_expr
->X_op
= O_absent
;
3368 asarg
= expr_parse_end
;
3372 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3373 || imm_expr
->X_op
!= O_constant
3374 || imm_expr
->X_add_number
< 0
3375 || imm_expr
->X_add_number
>= 8)
3377 as_bad (_("bad value for funct3 field, "
3378 "value must be 0...7"));
3381 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
3382 imm_expr
->X_op
= O_absent
;
3383 asarg
= expr_parse_end
;
3387 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3388 || imm_expr
->X_op
!= O_constant
3389 || imm_expr
->X_add_number
< 0
3390 || imm_expr
->X_add_number
>= 4)
3392 as_bad (_("bad value for funct2 field, "
3393 "value must be 0...3"));
3396 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
3397 imm_expr
->X_op
= O_absent
;
3398 asarg
= expr_parse_end
;
3402 goto unknown_riscv_ip_operand
;
3406 case 'y': /* bs immediate */
3407 my_getExpression (imm_expr
, asarg
);
3408 check_absolute_expr (ip
, imm_expr
, FALSE
);
3409 if ((unsigned long)imm_expr
->X_add_number
> 3)
3410 as_bad(_("Improper bs immediate (%lu)"),
3411 (unsigned long)imm_expr
->X_add_number
);
3412 INSERT_OPERAND(BS
, *ip
, imm_expr
->X_add_number
);
3413 imm_expr
->X_op
= O_absent
;
3414 asarg
= expr_parse_end
;
3417 case 'Y': /* rnum immediate */
3418 my_getExpression (imm_expr
, asarg
);
3419 check_absolute_expr (ip
, imm_expr
, FALSE
);
3420 if ((unsigned long)imm_expr
->X_add_number
> 10)
3421 as_bad(_("Improper rnum immediate (%lu)"),
3422 (unsigned long)imm_expr
->X_add_number
);
3423 INSERT_OPERAND(RNUM
, *ip
, imm_expr
->X_add_number
);
3424 imm_expr
->X_op
= O_absent
;
3425 asarg
= expr_parse_end
;
3429 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3430 || imm_expr
->X_op
!= O_constant
3431 || imm_expr
->X_add_number
!= 0)
3433 asarg
= expr_parse_end
;
3434 imm_expr
->X_op
= O_absent
;
3437 case 'W': /* Various operands. */
3444 /* Prefetch offset for 'Zicbop' extension.
3445 pseudo S-type but lower 5-bits zero. */
3446 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3448 my_getExpression (imm_expr
, asarg
);
3449 check_absolute_expr (ip
, imm_expr
, false);
3450 if (((unsigned) (imm_expr
->X_add_number
) & 0x1fU
)
3451 || imm_expr
->X_add_number
>= RISCV_IMM_REACH
/ 2
3452 || imm_expr
->X_add_number
< -RISCV_IMM_REACH
/ 2)
3453 as_bad (_ ("improper prefetch offset (%ld)"),
3454 (long) imm_expr
->X_add_number
);
3455 ip
->insn_opcode
|= ENCODE_STYPE_IMM (
3456 (unsigned) (imm_expr
->X_add_number
) & ~0x1fU
);
3457 imm_expr
->X_op
= O_absent
;
3458 asarg
= expr_parse_end
;
3461 goto unknown_riscv_ip_operand
;
3465 goto unknown_riscv_ip_operand
;
3469 case 'X': /* Integer immediate. */
3477 case 'l': /* Literal. */
3478 n
= strcspn (++oparg
, ",");
3479 if (strncmp (oparg
, asarg
, n
))
3480 as_bad (_("unexpected literal (%s)"), asarg
);
3484 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
3487 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
3491 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3493 goto unknown_riscv_ip_operand
;
3494 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3497 my_getExpression (imm_expr
, asarg
);
3498 check_absolute_expr (ip
, imm_expr
, false);
3501 if (!VALIDATE_U_IMM (imm_expr
->X_add_number
, n
))
3502 as_bad (_("improper immediate value (%"PRIu64
")"),
3503 imm_expr
->X_add_number
);
3507 if (!VALIDATE_S_IMM (imm_expr
->X_add_number
, n
))
3508 as_bad (_("improper immediate value (%"PRIi64
")"),
3509 imm_expr
->X_add_number
);
3511 INSERT_IMM (n
, s
, *ip
, imm_expr
->X_add_number
);
3512 imm_expr
->X_op
= O_absent
;
3513 asarg
= expr_parse_end
;
3516 goto unknown_riscv_ip_operand
;
3522 unknown_riscv_ip_operand
:
3523 as_fatal (_("internal: unknown argument type `%s'"),
3529 insn_with_csr
= false;
3533 /* Restore the character we might have clobbered above. */
3535 *(asargStart
- 1) = save_c
;
3540 /* Similar to riscv_ip, but assembles an instruction according to the
3541 hardcode values of .insn directive. */
3544 riscv_ip_hardcode (char *str
,
3545 struct riscv_cl_insn
*ip
,
3546 expressionS
*imm_expr
,
3549 struct riscv_opcode
*insn
;
3550 insn_t values
[2] = {0, 0};
3551 unsigned int num
= 0;
3553 input_line_pointer
= str
;
3556 expression (imm_expr
);
3557 switch (imm_expr
->X_op
)
3560 values
[num
++] = (insn_t
) imm_expr
->X_add_number
;
3563 /* Extract lower 32-bits of a big number.
3564 Assume that generic_bignum_to_int32 work on such number. */
3565 values
[num
++] = (insn_t
) generic_bignum_to_int32 ();
3568 /* The first value isn't constant, so it should be
3569 .insn <type> <operands>. We have been parsed it
3573 return _("values must be constant");
3576 while (*input_line_pointer
++ == ',' && num
< 2 && imm_expr
->X_op
!= O_big
);
3578 input_line_pointer
--;
3579 if (*input_line_pointer
!= '\0')
3580 return _("unrecognized values");
3582 insn
= XNEW (struct riscv_opcode
);
3583 insn
->match
= values
[num
- 1];
3584 create_insn (ip
, insn
);
3585 unsigned int bytes
= riscv_insn_length (insn
->match
);
3587 if (num
== 2 && values
[0] != bytes
)
3588 return _("value conflicts with instruction length");
3590 if (imm_expr
->X_op
== O_big
)
3592 unsigned int llen
= 0;
3593 for (LITTLENUM_TYPE lval
= generic_bignum
[imm_expr
->X_add_number
- 1];
3595 lval
>>= BITS_PER_CHAR
;
3596 unsigned int repr_bytes
3597 = (imm_expr
->X_add_number
- 1) * CHARS_PER_LITTLENUM
+ llen
;
3598 if (bytes
< repr_bytes
)
3599 return _("value conflicts with instruction length");
3600 for (num
= 0; num
< imm_expr
->X_add_number
- 1; ++num
)
3601 number_to_chars_littleendian (
3602 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3603 generic_bignum
[num
],
3604 CHARS_PER_LITTLENUM
);
3606 number_to_chars_littleendian (
3607 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3608 generic_bignum
[num
],
3610 memset(ip
->insn_long_opcode
+ repr_bytes
, 0, bytes
- repr_bytes
);
3614 if (bytes
< sizeof(values
[0]) && values
[num
- 1] >> (8 * bytes
) != 0)
3615 return _("value conflicts with instruction length");
3621 md_assemble (char *str
)
3623 struct riscv_cl_insn insn
;
3624 expressionS imm_expr
;
3625 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3627 /* The architecture and privileged elf attributes should be set
3628 before assembling. */
3629 if (!start_assemble
)
3631 start_assemble
= true;
3633 riscv_set_abi_by_arch ();
3634 if (!riscv_set_default_priv_spec (NULL
))
3638 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
3640 const struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
3641 &imm_reloc
, op_hash
);
3645 if (error
.missing_ext
)
3646 as_bad ("%s `%s', extension `%s' required", error
.msg
,
3647 error
.statement
, error
.missing_ext
);
3649 as_bad ("%s `%s'", error
.msg
, error
.statement
);
3653 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3654 macro (&insn
, &imm_expr
, &imm_reloc
);
3656 append_insn (&insn
, &imm_expr
, imm_reloc
);
3660 md_atof (int type
, char *litP
, int *sizeP
)
3662 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
3666 md_number_to_chars (char *buf
, valueT val
, int n
)
3668 if (target_big_endian
)
3669 number_to_chars_bigendian (buf
, val
, n
);
3671 number_to_chars_littleendian (buf
, val
, n
);
3674 const char *md_shortopts
= "O::g::G:";
3678 OPTION_MARCH
= OPTION_MD_BASE
,
3685 OPTION_NO_ARCH_ATTR
,
3687 OPTION_NO_CSR_CHECK
,
3691 OPTION_LITTLE_ENDIAN
,
3695 struct option md_longopts
[] =
3697 {"march", required_argument
, NULL
, OPTION_MARCH
},
3698 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
3699 {"fpic", no_argument
, NULL
, OPTION_PIC
},
3700 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
3701 {"mabi", required_argument
, NULL
, OPTION_MABI
},
3702 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
3703 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
3704 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
3705 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
3706 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
3707 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
3708 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
3709 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
3710 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
3711 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
3713 {NULL
, no_argument
, NULL
, 0}
3715 size_t md_longopts_size
= sizeof (md_longopts
);
3718 md_parse_option (int c
, const char *arg
)
3723 default_arch_with_ext
= arg
;
3727 riscv_opts
.pic
= false;
3731 riscv_opts
.pic
= true;
3735 if (strcmp (arg
, "ilp32") == 0)
3736 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
3737 else if (strcmp (arg
, "ilp32e") == 0)
3738 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
3739 else if (strcmp (arg
, "ilp32f") == 0)
3740 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
3741 else if (strcmp (arg
, "ilp32d") == 0)
3742 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
3743 else if (strcmp (arg
, "ilp32q") == 0)
3744 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
3745 else if (strcmp (arg
, "lp64") == 0)
3746 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
3747 else if (strcmp (arg
, "lp64f") == 0)
3748 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
3749 else if (strcmp (arg
, "lp64d") == 0)
3750 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
3751 else if (strcmp (arg
, "lp64q") == 0)
3752 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
3755 explicit_mabi
= true;
3759 riscv_opts
.relax
= true;
3762 case OPTION_NO_RELAX
:
3763 riscv_opts
.relax
= false;
3766 case OPTION_ARCH_ATTR
:
3767 riscv_opts
.arch_attr
= true;
3770 case OPTION_NO_ARCH_ATTR
:
3771 riscv_opts
.arch_attr
= false;
3774 case OPTION_CSR_CHECK
:
3775 riscv_opts
.csr_check
= true;
3778 case OPTION_NO_CSR_CHECK
:
3779 riscv_opts
.csr_check
= false;
3782 case OPTION_MISA_SPEC
:
3783 return riscv_set_default_isa_spec (arg
);
3785 case OPTION_MPRIV_SPEC
:
3786 return riscv_set_default_priv_spec (arg
);
3788 case OPTION_BIG_ENDIAN
:
3789 target_big_endian
= 1;
3792 case OPTION_LITTLE_ENDIAN
:
3793 target_big_endian
= 0;
3804 riscv_after_parse_args (void)
3806 /* The --with-arch is optional for now, so we still need to set the xlen
3807 according to the default_arch, which is set by the --target. */
3810 if (strcmp (default_arch
, "riscv32") == 0)
3812 else if (strcmp (default_arch
, "riscv64") == 0)
3815 as_bad ("unknown default architecture `%s'", default_arch
);
3818 /* Set default specs. */
3819 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
3820 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
3821 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
3822 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
3824 riscv_set_arch (default_arch_with_ext
);
3826 /* If the CIE to be produced has not been overridden on the command line,
3827 then produce version 3 by default. This allows us to use the full
3828 range of registers in a .cfi_return_column directive. */
3829 if (flag_dwarf_cie_version
== -1)
3830 flag_dwarf_cie_version
= 3;
3834 md_pcrel_from (fixS
*fixP
)
3836 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3839 /* Apply a fixup to the object file. */
3842 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
3844 unsigned int subtype
;
3845 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
3846 bool relaxable
= false;
3850 /* Remember value for tc_gen_reloc. */
3851 fixP
->fx_addnumber
= *valP
;
3853 switch (fixP
->fx_r_type
)
3855 case BFD_RELOC_RISCV_HI20
:
3856 case BFD_RELOC_RISCV_LO12_I
:
3857 case BFD_RELOC_RISCV_LO12_S
:
3858 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
3859 | bfd_getl32 (buf
), buf
);
3860 if (fixP
->fx_addsy
== NULL
)
3861 fixP
->fx_done
= true;
3865 case BFD_RELOC_RISCV_GOT_HI20
:
3866 case BFD_RELOC_RISCV_ADD8
:
3867 case BFD_RELOC_RISCV_ADD16
:
3868 case BFD_RELOC_RISCV_ADD32
:
3869 case BFD_RELOC_RISCV_ADD64
:
3870 case BFD_RELOC_RISCV_SUB6
:
3871 case BFD_RELOC_RISCV_SUB8
:
3872 case BFD_RELOC_RISCV_SUB16
:
3873 case BFD_RELOC_RISCV_SUB32
:
3874 case BFD_RELOC_RISCV_SUB64
:
3875 case BFD_RELOC_RISCV_RELAX
:
3878 case BFD_RELOC_RISCV_TPREL_HI20
:
3879 case BFD_RELOC_RISCV_TPREL_LO12_I
:
3880 case BFD_RELOC_RISCV_TPREL_LO12_S
:
3881 case BFD_RELOC_RISCV_TPREL_ADD
:
3885 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
3886 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3887 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3888 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3889 if (fixP
->fx_addsy
!= NULL
)
3890 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3893 _("TLS relocation against a constant"));
3897 /* Use pc-relative relocation for FDE initial location.
3898 The symbol address in .eh_frame may be adjusted in
3899 _bfd_elf_discard_section_eh_frame, and the content of
3900 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3901 Therefore, we cannot insert a relocation whose addend symbol is
3902 in .eh_frame. Othrewise, the value may be adjusted twice. */
3903 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3904 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3905 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3906 && S_GET_VALUE (fixP
->fx_subsy
)
3907 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3909 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3910 fixP
->fx_subsy
= NULL
;
3917 case BFD_RELOC_RISCV_CFA
:
3918 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3920 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3921 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3922 fixP
->fx_next
->fx_subsy
= NULL
;
3923 fixP
->fx_next
->fx_offset
= 0;
3924 fixP
->fx_subsy
= NULL
;
3926 switch (fixP
->fx_r_type
)
3929 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3930 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3934 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3935 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3939 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3940 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3944 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3945 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3948 case BFD_RELOC_RISCV_CFA
:
3949 /* Load the byte to get the subtype. */
3950 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3951 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3954 case DW_CFA_advance_loc1
:
3955 fixP
->fx_where
= loc
+ 1;
3956 fixP
->fx_next
->fx_where
= loc
+ 1;
3957 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3958 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3961 case DW_CFA_advance_loc2
:
3963 fixP
->fx_next
->fx_size
= 2;
3964 fixP
->fx_where
= loc
+ 1;
3965 fixP
->fx_next
->fx_where
= loc
+ 1;
3966 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3967 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3970 case DW_CFA_advance_loc4
:
3972 fixP
->fx_next
->fx_size
= 4;
3973 fixP
->fx_where
= loc
;
3974 fixP
->fx_next
->fx_where
= loc
;
3975 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3976 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3980 if (subtype
< 0x80 && (subtype
& 0x40))
3982 /* DW_CFA_advance_loc */
3983 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3984 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3985 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3986 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3989 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3995 /* This case is unreachable. */
4002 /* If we are deleting this reloc entry, we must fill in the
4003 value now. This can happen if we have a .word which is not
4004 resolved when it appears but is later defined. */
4005 if (fixP
->fx_addsy
== NULL
)
4007 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
4008 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
4013 case BFD_RELOC_RISCV_JMP
:
4016 /* Fill in a tentative value to improve objdump readability. */
4017 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4018 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4019 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
4023 case BFD_RELOC_12_PCREL
:
4026 /* Fill in a tentative value to improve objdump readability. */
4027 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4028 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4029 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
4033 case BFD_RELOC_RISCV_RVC_BRANCH
:
4036 /* Fill in a tentative value to improve objdump readability. */
4037 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4038 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4039 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
4043 case BFD_RELOC_RISCV_RVC_JUMP
:
4046 /* Fill in a tentative value to improve objdump readability. */
4047 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4048 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4049 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
4053 case BFD_RELOC_RISCV_CALL
:
4054 case BFD_RELOC_RISCV_CALL_PLT
:
4058 case BFD_RELOC_RISCV_PCREL_HI20
:
4059 case BFD_RELOC_RISCV_PCREL_LO12_S
:
4060 case BFD_RELOC_RISCV_PCREL_LO12_I
:
4061 relaxable
= riscv_opts
.relax
;
4064 case BFD_RELOC_RISCV_ALIGN
:
4068 /* We ignore generic BFD relocations we don't know about. */
4069 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
4070 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
4073 if (fixP
->fx_subsy
!= NULL
)
4074 as_bad_subtract (fixP
);
4076 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
4077 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
4079 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
4080 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
4081 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
4082 fixP
->fx_next
->fx_size
= 0;
4086 /* Because the value of .cfi_remember_state may changed after relaxation,
4087 we insert a fix to relocate it again in link-time. */
4090 riscv_pre_output_hook (void)
4092 const frchainS
*frch
;
4095 /* Save the current segment info. */
4097 subsegT subseg
= now_subseg
;
4099 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
4100 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
4104 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
4106 if (frag
->fr_type
== rs_cfa
)
4109 expressionS
*symval
;
4111 symval
= symbol_get_value_expression (frag
->fr_symbol
);
4112 exp
.X_op
= O_subtract
;
4113 exp
.X_add_symbol
= symval
->X_add_symbol
;
4114 exp
.X_add_number
= 0;
4115 exp
.X_op_symbol
= symval
->X_op_symbol
;
4117 /* We must set the segment before creating a frag after all
4118 frag chains have been chained together. */
4119 subseg_set (s
, frch
->frch_subseg
);
4121 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
4122 BFD_RELOC_RISCV_CFA
);
4127 /* Restore the original segment info. */
4128 subseg_set (seg
, subseg
);
4131 /* Handle the .option pseudo-op. */
4134 s_riscv_option (int x ATTRIBUTE_UNUSED
)
4136 char *name
= input_line_pointer
, ch
;
4138 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4139 ++input_line_pointer
;
4140 ch
= *input_line_pointer
;
4141 *input_line_pointer
= '\0';
4143 if (strcmp (name
, "rvc") == 0)
4145 riscv_update_subset (&riscv_rps_as
, "+c");
4146 riscv_reset_subsets_list_arch_str ();
4147 riscv_set_rvc (true);
4149 else if (strcmp (name
, "norvc") == 0)
4151 riscv_update_subset (&riscv_rps_as
, "-c");
4152 riscv_reset_subsets_list_arch_str ();
4153 riscv_set_rvc (false);
4155 else if (strcmp (name
, "pic") == 0)
4156 riscv_opts
.pic
= true;
4157 else if (strcmp (name
, "nopic") == 0)
4158 riscv_opts
.pic
= false;
4159 else if (strcmp (name
, "relax") == 0)
4160 riscv_opts
.relax
= true;
4161 else if (strcmp (name
, "norelax") == 0)
4162 riscv_opts
.relax
= false;
4163 else if (strcmp (name
, "csr-check") == 0)
4164 riscv_opts
.csr_check
= true;
4165 else if (strcmp (name
, "no-csr-check") == 0)
4166 riscv_opts
.csr_check
= false;
4167 else if (strncmp (name
, "arch,", 5) == 0)
4170 if (ISSPACE (*name
) && *name
!= '\0')
4172 riscv_update_subset (&riscv_rps_as
, name
);
4173 riscv_reset_subsets_list_arch_str ();
4175 riscv_set_rvc (false);
4176 if (riscv_subset_supports (&riscv_rps_as
, "c"))
4177 riscv_set_rvc (true);
4179 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
4182 else if (strcmp (name
, "push") == 0)
4184 struct riscv_option_stack
*s
;
4186 s
= XNEW (struct riscv_option_stack
);
4187 s
->next
= riscv_opts_stack
;
4188 s
->options
= riscv_opts
;
4189 s
->subset_list
= riscv_rps_as
.subset_list
;
4190 riscv_opts_stack
= s
;
4191 riscv_rps_as
.subset_list
= riscv_copy_subset_list (s
->subset_list
);
4193 else if (strcmp (name
, "pop") == 0)
4195 struct riscv_option_stack
*s
;
4197 s
= riscv_opts_stack
;
4199 as_bad (_(".option pop with no .option push"));
4202 riscv_subset_list_t
*release_subsets
= riscv_rps_as
.subset_list
;
4203 riscv_opts_stack
= s
->next
;
4204 riscv_opts
= s
->options
;
4205 riscv_rps_as
.subset_list
= s
->subset_list
;
4206 riscv_release_subset_list (release_subsets
);
4212 as_warn (_("unrecognized .option directive: %s"), name
);
4214 *input_line_pointer
= ch
;
4215 demand_empty_rest_of_line ();
4218 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
4219 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
4220 use in DWARF debug information. */
4223 s_dtprel (int bytes
)
4230 if (ex
.X_op
!= O_symbol
)
4232 as_bad (_("unsupported use of %s"), (bytes
== 8
4235 ignore_rest_of_line ();
4238 p
= frag_more (bytes
);
4239 md_number_to_chars (p
, 0, bytes
);
4240 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
4242 ? BFD_RELOC_RISCV_TLS_DTPREL64
4243 : BFD_RELOC_RISCV_TLS_DTPREL32
));
4245 demand_empty_rest_of_line ();
4248 /* Handle the .bss pseudo-op. */
4251 s_bss (int ignore ATTRIBUTE_UNUSED
)
4253 subseg_set (bss_section
, 0);
4254 demand_empty_rest_of_line ();
4258 riscv_make_nops (char *buf
, bfd_vma bytes
)
4262 /* RISC-V instructions cannot begin or end on odd addresses, so this case
4263 means we are not within a valid instruction sequence. It is thus safe
4264 to use a zero byte, even though that is not a valid instruction. */
4268 /* Use at most one 2-byte NOP. */
4269 if ((bytes
- i
) % 4 == 2)
4271 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
4275 /* Fill the remainder with 4-byte NOPs. */
4276 for ( ; i
< bytes
; i
+= 4)
4277 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
4280 /* Called from md_do_align. Used to create an alignment frag in a
4281 code section by emitting a worst-case NOP sequence that the linker
4282 will later relax to the correct number of NOPs. We can't compute
4283 the correct alignment now because of other linker relaxations. */
4286 riscv_frag_align_code (int n
)
4288 bfd_vma bytes
= (bfd_vma
) 1 << n
;
4289 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
4290 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
4294 /* If we are moving to a smaller alignment than the instruction size, then no
4295 alignment is required. */
4296 if (bytes
<= insn_alignment
)
4299 /* When not relaxing, riscv_handle_align handles code alignment. */
4300 if (!riscv_opts
.relax
)
4303 /* Maybe we should use frag_var to create a new rs_align_code fragment,
4304 rather than just use frag_more to handle an alignment here? So that we
4305 don't need to call riscv_mapping_state again later, and then only need
4306 to check frag->fr_type to see if it is frag_align_code. */
4307 nops
= frag_more (worst_case_bytes
);
4309 ex
.X_op
= O_constant
;
4310 ex
.X_add_number
= worst_case_bytes
;
4312 riscv_make_nops (nops
, worst_case_bytes
);
4314 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
4315 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
4317 riscv_mapping_state (MAP_INSN
, worst_case_bytes
, true/* fr_align_code */);
4319 /* We need to start a new frag after the alignment which may be removed by
4320 the linker, to prevent the assembler from computing static offsets.
4321 This is necessary to get correct EH info. */
4322 frag_wane (frag_now
);
4328 /* Implement HANDLE_ALIGN. */
4331 riscv_handle_align (fragS
*fragP
)
4333 switch (fragP
->fr_type
)
4336 /* When relaxing, riscv_frag_align_code handles code alignment. */
4337 if (!riscv_opts
.relax
)
4339 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
4340 - fragP
->fr_address
- fragP
->fr_fix
);
4341 /* We have 4 byte uncompressed nops. */
4342 bfd_signed_vma size
= 4;
4343 bfd_signed_vma excess
= bytes
% size
;
4344 bfd_boolean odd_padding
= (excess
% 2 == 1);
4345 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
4350 /* Insert zeros or compressed nops to get 4 byte alignment. */
4354 riscv_add_odd_padding_symbol (fragP
);
4355 riscv_make_nops (p
, excess
);
4356 fragP
->fr_fix
+= excess
;
4360 /* The frag will be changed to `rs_fill` later. The function
4361 `write_contents` will try to fill the remaining spaces
4362 according to the patterns we give. In this case, we give
4363 a 4 byte uncompressed nop as the pattern, and set the size
4364 of the pattern into `fr_var`. The nop will be output to the
4365 file `fr_offset` times. However, `fr_offset` could be zero
4366 if we don't need to pad the boundary finally. */
4367 riscv_make_nops (p
, size
);
4368 fragP
->fr_var
= size
;
4377 /* This usually called from frag_var. */
4380 riscv_init_frag (fragS
* fragP
, int max_chars
)
4382 /* Do not add mapping symbol to debug sections. */
4383 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
4386 switch (fragP
->fr_type
)
4391 riscv_mapping_state (MAP_DATA
, max_chars
, false/* fr_align_code */);
4394 riscv_mapping_state (MAP_INSN
, max_chars
, true/* fr_align_code */);
4402 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
4404 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
4407 /* Translate internal representation of relocation info to BFD target
4411 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
4413 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4415 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4416 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4417 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4418 reloc
->addend
= fixp
->fx_addnumber
;
4420 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4421 if (reloc
->howto
== NULL
)
4423 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
4424 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
4426 /* We don't have R_RISCV_8/16, but for this special case,
4427 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
4431 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4432 _("cannot represent %s relocation in object file"),
4433 bfd_get_reloc_code_name (fixp
->fx_r_type
));
4441 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
4443 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
4445 offsetT old_var
= fragp
->fr_var
;
4446 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
4447 return fragp
->fr_var
- old_var
;
4453 /* Expand far branches to multi-instruction sequences. */
4456 md_convert_frag_branch (fragS
*fragp
)
4464 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
4466 exp
.X_op
= O_symbol
;
4467 exp
.X_add_symbol
= fragp
->fr_symbol
;
4468 exp
.X_add_number
= fragp
->fr_offset
;
4470 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
4472 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
4474 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4478 /* Expand the RVC branch into a RISC-V one. */
4479 insn
= bfd_getl16 (buf
);
4480 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
4481 if ((insn
& MASK_C_J
) == MATCH_C_J
)
4483 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
4484 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
4485 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
4486 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
4487 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
4488 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
4491 bfd_putl32 (insn
, buf
);
4495 /* Invert the branch condition. Branch over the jump. */
4496 insn
= bfd_getl16 (buf
);
4497 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
4498 insn
|= ENCODE_CBTYPE_IMM (6);
4499 bfd_putl16 (insn
, buf
);
4504 /* Just keep the RVC branch. */
4505 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4506 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
4507 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4508 2, &exp
, false, reloc
);
4517 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4520 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
4522 /* Invert the branch condition. Branch over the jump. */
4523 insn
= bfd_getl32 (buf
);
4524 insn
^= MATCH_BEQ
^ MATCH_BNE
;
4525 insn
|= ENCODE_BTYPE_IMM (8);
4526 bfd_putl32 (insn
, buf
);
4530 /* Jump to the target. */
4531 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4532 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
4533 bfd_putl32 (MATCH_JAL
, buf
);
4538 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4539 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
4540 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4541 4, &exp
, false, reloc
);
4550 fixp
->fx_file
= fragp
->fr_file
;
4551 fixp
->fx_line
= fragp
->fr_line
;
4553 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
4554 + fragp
->fr_fix
+ fragp
->fr_var
);
4556 fragp
->fr_fix
+= fragp
->fr_var
;
4559 /* Relax a machine dependent frag. This returns the amount by which
4560 the current size of the frag should change. */
4563 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
4566 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
4567 md_convert_frag_branch (fragp
);
4571 md_show_usage (FILE *stream
)
4573 fprintf (stream
, _("\
4575 -fpic or -fPIC generate position-independent code\n\
4576 -fno-pic don't generate position-independent code (default)\n\
4577 -march=ISA set the RISC-V architecture\n\
4578 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
4579 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
4580 -mabi=ABI set the RISC-V ABI\n\
4581 -mrelax enable relax (default)\n\
4582 -mno-relax disable relax\n\
4583 -march-attr generate RISC-V arch attribute\n\
4584 -mno-arch-attr don't generate RISC-V arch attribute\n\
4585 -mcsr-check enable the csr ISA and privilege spec version checks\n\
4586 -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\
4587 -mbig-endian assemble for big-endian\n\
4588 -mlittle-endian assemble for little-endian\n\
4592 /* Standard calling conventions leave the CFA at SP on entry. */
4595 riscv_cfi_frame_initial_instructions (void)
4597 cfi_add_CFA_def_cfa_register (X_SP
);
4601 tc_riscv_regname_to_dw2regnum (char *regname
)
4605 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
4608 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
4611 if ((reg
= reg_lookup_internal (regname
, RCLASS_VECR
)) >= 0)
4614 /* CSRs are numbered 4096 -> 8191. */
4615 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
4618 as_bad (_("unknown register `%s'"), regname
);
4623 riscv_elf_final_processing (void)
4625 riscv_set_abi_by_arch ();
4626 riscv_release_subset_list (riscv_rps_as
.subset_list
);
4627 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4630 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
4631 since these directives break relaxation when used with symbol deltas. */
4634 s_riscv_leb128 (int sign
)
4637 char *save_in
= input_line_pointer
;
4640 if (exp
.X_op
!= O_constant
)
4641 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
4642 demand_empty_rest_of_line ();
4644 input_line_pointer
= save_in
;
4645 return s_leb128 (sign
);
4648 /* Parse the .insn directive. There are three formats,
4649 Format 1: .insn <type> <operand1>, <operand2>, ...
4650 Format 2: .insn <length>, <value>
4651 Format 3: .insn <value>. */
4654 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
4656 char *str
= input_line_pointer
;
4657 struct riscv_cl_insn insn
;
4658 expressionS imm_expr
;
4659 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
4662 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4663 ++input_line_pointer
;
4665 save_c
= *input_line_pointer
;
4666 *input_line_pointer
= '\0';
4668 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
4670 struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
4671 &imm_reloc
, insn_type_hash
);
4674 char *save_in
= input_line_pointer
;
4675 error
.msg
= riscv_ip_hardcode (str
, &insn
, &imm_expr
, error
.msg
);
4676 input_line_pointer
= save_in
;
4681 if (error
.missing_ext
)
4682 as_bad ("%s `%s', extension `%s' required", error
.msg
, error
.statement
,
4685 as_bad ("%s `%s'", error
.msg
, error
.statement
);
4689 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
4690 append_insn (&insn
, &imm_expr
, imm_reloc
);
4693 *input_line_pointer
= save_c
;
4694 demand_empty_rest_of_line ();
4697 /* Update architecture and privileged elf attributes. If we don't set
4698 them, then try to output the default ones. */
4701 riscv_write_out_attrs (void)
4703 const char *arch_str
, *priv_str
, *p
;
4704 /* versions[0]: major version.
4705 versions[1]: minor version.
4706 versions[2]: revision version. */
4707 unsigned versions
[3] = {0}, number
= 0;
4710 /* Re-write architecture elf attribute. */
4711 arch_str
= riscv_rps_as
.subset_list
->arch_str
;
4712 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
4714 /* For the file without any instruction, we don't set the default_priv_spec
4715 according to the privileged elf attributes since the md_assemble isn't
4718 && !riscv_set_default_priv_spec (NULL
))
4721 /* If we already have set privileged elf attributes, then no need to do
4722 anything. Otherwise, don't generate or update them when no CSR and
4723 privileged instructions are used. */
4724 if (!explicit_priv_attr
)
4727 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
4729 for (i
= 0; *p
; ++p
)
4731 if (*p
== '.' && i
< 3)
4733 versions
[i
++] = number
;
4736 else if (ISDIGIT (*p
))
4737 number
= (number
* 10) + (*p
- '0');
4740 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
4744 versions
[i
] = number
;
4746 /* Re-write privileged elf attributes. */
4747 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
4748 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
4749 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
4752 /* Add the default contents for the .riscv.attributes section. */
4755 riscv_set_public_attributes (void)
4757 if (riscv_opts
.arch_attr
|| explicit_attr
)
4758 riscv_write_out_attrs ();
4761 /* Called after all assembly has been done. */
4764 riscv_md_finish (void)
4766 riscv_set_public_attributes ();
4769 /* Adjust the symbol table. */
4772 riscv_adjust_symtab (void)
4774 bfd_map_over_sections (stdoutput
, riscv_check_mapping_symbols
, (char *) 0);
4775 elf_adjust_symtab ();
4778 /* Given a symbolic attribute NAME, return the proper integer value.
4779 Returns -1 if the attribute is not known. */
4782 riscv_convert_symbolic_attribute (const char *name
)
4791 /* When you modify this table you should
4792 also modify the list in doc/c-riscv.texi. */
4793 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
4797 T(priv_spec_revision
),
4798 T(unaligned_access
),
4807 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
4808 if (strcmp (name
, attribute_table
[i
].name
) == 0)
4809 return attribute_table
[i
].tag
;
4814 /* Parse a .attribute directive. */
4817 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
4819 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4821 obj_attribute
*attr
;
4823 explicit_attr
= true;
4826 case Tag_RISCV_arch
:
4828 attr
= elf_known_obj_attributes_proc (stdoutput
);
4829 if (!start_assemble
)
4830 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
4832 as_fatal (_("architecture elf attributes must set before "
4833 "any instructions"));
4835 if (old_xlen
!= xlen
)
4837 /* We must re-init bfd again if xlen is changed. */
4838 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
4839 bfd_find_target (riscv_target_format (), stdoutput
);
4841 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
4842 as_warn (_("could not set architecture and machine"));
4846 case Tag_RISCV_priv_spec
:
4847 case Tag_RISCV_priv_spec_minor
:
4848 case Tag_RISCV_priv_spec_revision
:
4850 as_fatal (_("privileged elf attributes must set before "
4851 "any instructions"));
4859 /* Mark symbol that it follows a variant CC convention. */
4862 s_variant_cc (int ignored ATTRIBUTE_UNUSED
)
4868 elf_symbol_type
*elfsym
;
4870 c
= get_symbol_name (&name
);
4872 as_bad (_("missing symbol name for .variant_cc directive"));
4873 sym
= symbol_find_or_make (name
);
4874 restore_line_pointer (c
);
4875 demand_empty_rest_of_line ();
4877 bfdsym
= symbol_get_bfdsym (sym
);
4878 elfsym
= elf_symbol_from (bfdsym
);
4879 gas_assert (elfsym
);
4880 elfsym
->internal_elf_sym
.st_other
|= STO_RISCV_VARIANT_CC
;
4883 /* Same as elf_copy_symbol_attributes, but without copying st_other.
4884 This is needed so RISC-V specific st_other values can be independently
4885 specified for an IFUNC resolver (that is called by the dynamic linker)
4886 and the symbol it resolves (aliased to the resolver). In particular,
4887 if a function symbol has special st_other value set via directives,
4888 then attaching an IFUNC resolver to that symbol should not override
4889 the st_other setting. Requiring the directive on the IFUNC resolver
4890 symbol would be unexpected and problematic in C code, where the two
4891 symbols appear as two independent function declarations. */
4894 riscv_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
4896 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
4897 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
4898 /* If size is unset, copy size from src. Because we don't track whether
4899 .size has been used, we can't differentiate .size dest, 0 from the case
4900 where dest's size is unset. */
4901 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
4905 destelf
->size
= XNEW (expressionS
);
4906 *destelf
->size
= *srcelf
->size
;
4908 S_SET_SIZE (dest
, S_GET_SIZE (src
));
4912 /* RISC-V pseudo-ops table. */
4913 static const pseudo_typeS riscv_pseudo_table
[] =
4915 {"option", s_riscv_option
, 0},
4919 {"dtprelword", s_dtprel
, 4},
4920 {"dtpreldword", s_dtprel
, 8},
4922 {"uleb128", s_riscv_leb128
, 0},
4923 {"sleb128", s_riscv_leb128
, 1},
4924 {"insn", s_riscv_insn
, 0},
4925 {"attribute", s_riscv_attribute
, 0},
4926 {"variant_cc", s_variant_cc
, 0},
4927 {"float16", float_cons
, 'h'},
4933 riscv_pop_insert (void)
4935 extern void pop_insert (const pseudo_typeS
*);
4937 pop_insert (riscv_pseudo_table
);