1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits
46 (first bits enough to extract instruction length on a long opcode). */
49 /* The long encoded instruction bits ([0] is non-zero on a long opcode). */
50 char insn_long_opcode
[RISCV_MAX_INSN_LEN
];
52 /* The frag that contains the instruction. */
55 /* The offset into FRAG of the first instruction byte. */
58 /* The relocs associated with the instruction, if any. */
62 /* All RISC-V CSR belong to one of these classes. */
68 CSR_CLASS_I_32
, /* rv32 only */
69 CSR_CLASS_F
, /* f-ext only */
70 CSR_CLASS_ZKR
, /* zkr only */
71 CSR_CLASS_V
, /* rvv only */
72 CSR_CLASS_DEBUG
, /* debug CSR */
73 CSR_CLASS_H
, /* hypervisor */
74 CSR_CLASS_H_32
, /* hypervisor, rv32 only */
75 CSR_CLASS_SMAIA
, /* Smaia */
76 CSR_CLASS_SMAIA_32
, /* Smaia, rv32 only */
77 CSR_CLASS_SMSTATEEN
, /* Smstateen only */
78 CSR_CLASS_SMSTATEEN_32
, /* Smstateen RV32 only */
79 CSR_CLASS_SSAIA
, /* Ssaia */
80 CSR_CLASS_SSAIA_AND_H
, /* Ssaia with H */
81 CSR_CLASS_SSAIA_32
, /* Ssaia, rv32 only */
82 CSR_CLASS_SSAIA_AND_H_32
, /* Ssaia with H, rv32 only */
83 CSR_CLASS_SSSTATEEN
, /* S[ms]stateen only */
84 CSR_CLASS_SSSTATEEN_AND_H
, /* S[ms]stateen only (with H) */
85 CSR_CLASS_SSSTATEEN_AND_H_32
, /* S[ms]stateen RV32 only (with H) */
86 CSR_CLASS_SSCOFPMF
, /* Sscofpmf only */
87 CSR_CLASS_SSCOFPMF_32
, /* Sscofpmf RV32 only */
88 CSR_CLASS_SSTC
, /* Sstc only */
89 CSR_CLASS_SSTC_AND_H
, /* Sstc only (with H) */
90 CSR_CLASS_SSTC_32
, /* Sstc RV32 only */
91 CSR_CLASS_SSTC_AND_H_32
, /* Sstc RV32 only (with H) */
94 /* This structure holds all restricted conditions for a CSR. */
95 struct riscv_csr_extra
97 /* Class to which this CSR belongs. Used to decide whether or
98 not this CSR is legal in the current -march context. */
99 enum riscv_csr_class csr_class
;
101 /* CSR may have differnet numbers in the previous priv spec. */
104 /* Record the CSR is defined/valid in which versions. */
105 enum riscv_spec_class define_version
;
107 /* Record the CSR is aborted/invalid from which versions. If it isn't
108 aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
109 enum riscv_spec_class abort_version
;
111 /* The CSR may have more than one setting. */
112 struct riscv_csr_extra
*next
;
115 /* This structure contains information about errors that occur within the
117 struct riscv_ip_error
119 /* General error message */
122 /* Statement that caused the error */
125 /* Missing extension that needs to be enabled */
126 const char* missing_ext
;
130 #define DEFAULT_ARCH "riscv64"
133 #ifndef DEFAULT_RISCV_ATTR
134 #define DEFAULT_RISCV_ATTR 0
137 /* Let riscv_after_parse_args set the default value according to xlen. */
138 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
139 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
142 /* Need to sync the version with RISC-V compiler. */
143 #ifndef DEFAULT_RISCV_ISA_SPEC
144 #define DEFAULT_RISCV_ISA_SPEC "20191213"
147 #ifndef DEFAULT_RISCV_PRIV_SPEC
148 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
151 static const char default_arch
[] = DEFAULT_ARCH
;
152 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
153 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
154 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
156 static unsigned xlen
= 0; /* The width of an x-register. */
157 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
158 static bool rve_abi
= false;
161 FLOAT_ABI_DEFAULT
= -1,
167 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
169 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
170 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
172 static unsigned elf_flags
= 0;
174 static bool probing_insn_operands
;
176 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
177 Otherwise, return 1. */
180 riscv_set_default_isa_spec (const char *s
)
182 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
183 RISCV_GET_ISA_SPEC_CLASS (s
, class);
184 if (class == ISA_SPEC_CLASS_NONE
)
186 as_bad ("unknown default ISA spec `%s' set by "
187 "-misa-spec or --with-isa-spec", s
);
191 default_isa_spec
= class;
195 /* Set the default_priv_spec. Find the privileged elf attributes when
196 the input string is NULL. Return 0 if the spec isn't supported.
197 Otherwise, return 1. */
200 riscv_set_default_priv_spec (const char *s
)
202 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
203 unsigned major
, minor
, revision
;
206 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
207 if (class != PRIV_SPEC_CLASS_NONE
)
209 default_priv_spec
= class;
215 as_bad (_("unknown default privileged spec `%s' set by "
216 "-mpriv-spec or --with-priv-spec"), s
);
220 /* Set the default_priv_spec by the privileged elf attributes. */
221 attr
= elf_known_obj_attributes_proc (stdoutput
);
222 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
223 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
224 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
225 /* Version 0.0.0 is the default value and meningless. */
226 if (major
== 0 && minor
== 0 && revision
== 0)
229 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
230 if (class != PRIV_SPEC_CLASS_NONE
)
232 default_priv_spec
= class;
236 /* Still can not find the privileged spec class. */
237 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
238 "privileged elf attributes"), major
, minor
, revision
);
242 /* This is the set of options which the .option pseudo-op may modify. */
243 struct riscv_set_options
245 int pic
; /* Generate position-independent code. */
246 int rvc
; /* Generate RVC code. */
247 int relax
; /* Emit relocs the linker is allowed to relax. */
248 int arch_attr
; /* Emit architecture and privileged elf attributes. */
249 int csr_check
; /* Enable the CSR checking. */
252 static struct riscv_set_options riscv_opts
=
257 DEFAULT_RISCV_ATTR
, /* arch_attr */
261 /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag
262 for elf_flags once we have enabled c extension. */
265 riscv_set_rvc (bool rvc_value
)
268 elf_flags
|= EF_RISCV_RVC
;
270 riscv_opts
.rvc
= rvc_value
;
273 /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */
278 elf_flags
|= EF_RISCV_TSO
;
281 /* The linked list hanging off of .subsets_list records all enabled extensions,
282 which are parsed from the architecture string. The architecture string can
283 be set by the -march option, the elf architecture attributes, and the
284 --with-arch configure option. */
285 static riscv_parse_subset_t riscv_rps_as
=
287 NULL
, /* subset_list, we will set it later once
288 riscv_opts_stack is created or updated. */
289 as_bad
, /* error_handler. */
291 &default_isa_spec
, /* isa_spec. */
292 true, /* check_unknown_prefixed_ext. */
295 /* Update the architecture string in the subset_list. */
298 riscv_reset_subsets_list_arch_str (void)
300 riscv_subset_list_t
*subsets
= riscv_rps_as
.subset_list
;
301 if (subsets
->arch_str
!= NULL
)
302 free ((void *) subsets
->arch_str
);
303 subsets
->arch_str
= riscv_arch_str (xlen
, subsets
);
306 /* This structure is used to hold a stack of .option values. */
307 struct riscv_option_stack
309 struct riscv_option_stack
*next
;
310 struct riscv_set_options options
;
311 riscv_subset_list_t
*subset_list
;
314 static struct riscv_option_stack
*riscv_opts_stack
= NULL
;
316 /* Set which ISA and extensions are available. */
319 riscv_set_arch (const char *s
)
321 if (s
!= NULL
&& strcmp (s
, "") == 0)
323 as_bad (_("the architecture string of -march and elf architecture "
324 "attributes cannot be empty"));
328 if (riscv_rps_as
.subset_list
== NULL
)
330 riscv_rps_as
.subset_list
= XNEW (riscv_subset_list_t
);
331 riscv_rps_as
.subset_list
->head
= NULL
;
332 riscv_rps_as
.subset_list
->tail
= NULL
;
333 riscv_rps_as
.subset_list
->arch_str
= NULL
;
335 riscv_release_subset_list (riscv_rps_as
.subset_list
);
336 riscv_parse_subset (&riscv_rps_as
, s
);
337 riscv_reset_subsets_list_arch_str ();
339 riscv_set_rvc (false);
340 if (riscv_subset_supports (&riscv_rps_as
, "c")
341 || riscv_subset_supports (&riscv_rps_as
, "zca"))
342 riscv_set_rvc (true);
344 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
348 /* Indicate -mabi option is explictly set. */
349 static bool explicit_mabi
= false;
351 /* Set the abi information. */
354 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
357 float_abi
= new_float_abi
;
361 /* If the -mabi option isn't set, then set the abi according to the
362 ISA string. Otherwise, check if there is any conflict. */
365 riscv_set_abi_by_arch (void)
369 if (riscv_subset_supports (&riscv_rps_as
, "q"))
370 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
371 else if (riscv_subset_supports (&riscv_rps_as
, "d"))
372 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
373 else if (riscv_subset_supports (&riscv_rps_as
, "e"))
374 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
376 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
380 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
382 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
383 else if (abi_xlen
< xlen
)
384 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
386 if (riscv_subset_supports (&riscv_rps_as
, "e") && !rve_abi
)
387 as_bad ("only the ilp32e ABI is supported for e extension");
389 if (float_abi
== FLOAT_ABI_SINGLE
390 && !riscv_subset_supports (&riscv_rps_as
, "f"))
391 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
393 else if (float_abi
== FLOAT_ABI_DOUBLE
394 && !riscv_subset_supports (&riscv_rps_as
, "d"))
395 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
397 else if (float_abi
== FLOAT_ABI_QUAD
398 && !riscv_subset_supports (&riscv_rps_as
, "q"))
399 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
403 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
404 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
405 elf_flags
|= float_abi
<< 1;
408 elf_flags
|= EF_RISCV_RVE
;
411 /* Handle of the OPCODE hash table. */
412 static htab_t op_hash
= NULL
;
414 /* Handle of the type of .insn hash table. */
415 static htab_t insn_type_hash
= NULL
;
417 /* This array holds the chars that always start a comment. If the
418 pre-processor is disabled, these aren't very useful. */
419 const char comment_chars
[] = "#";
421 /* This array holds the chars that only start a comment at the beginning of
422 a line. If the line seems to have the form '# 123 filename'
423 .line and .file directives will appear in the pre-processed output
425 Note that input_file.c hand checks for '#' at the beginning of the
426 first line of the input file. This is because the compiler outputs
427 #NO_APP at the beginning of its output.
429 Also note that C style comments are always supported. */
430 const char line_comment_chars
[] = "#";
432 /* This array holds machine specific line separator characters. */
433 const char line_separator_chars
[] = ";";
435 /* Chars that can be used to separate mant from exp in floating point nums. */
436 const char EXP_CHARS
[] = "eE";
438 /* Chars that mean this number is a floating point constant.
439 As in 0f12.456 or 0d1.2345e12. */
440 const char FLT_CHARS
[] = "rRsSfFdDxXpPhH";
442 /* Indicate we are already assemble any instructions or not. */
443 static bool start_assemble
= false;
445 /* Indicate ELF attributes are explicitly set. */
446 static bool explicit_attr
= false;
448 /* Indicate CSR or priv instructions are explicitly used. */
449 static bool explicit_priv_attr
= false;
451 static char *expr_parse_end
;
453 /* Macros for encoding relaxation state for RVC branches and far jumps. */
454 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
457 | ((uncond) ? 1 : 0) \
460 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
461 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
462 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
463 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
465 /* Is the given value a sign-extended 32-bit value? */
466 #define IS_SEXT_32BIT_NUM(x) \
467 (((x) &~ (offsetT) 0x7fffffff) == 0 \
468 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
470 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
471 #define IS_ZEXT_32BIT_NUM(x) \
472 (((x) &~ (offsetT) 0xffffffff) == 0 \
473 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
475 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
476 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
477 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
478 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
480 #define INSERT_IMM(n, s, INSN, VALUE) \
481 INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s)
483 /* Determine if an instruction matches an opcode. */
484 #define OPCODE_MATCHES(OPCODE, OP) \
485 (((OPCODE) & MASK_##OP) == MATCH_##OP)
487 /* Create a new mapping symbol for the transition to STATE. */
490 make_mapping_symbol (enum riscv_seg_mstate state
,
493 const char *arch_str
,
494 bool odd_data_padding
)
504 if (arch_str
!= NULL
)
506 size_t size
= strlen (arch_str
) + 3; /* "$x" + '\0' */
507 buff
= xmalloc (size
);
508 snprintf (buff
, size
, "$x%s", arch_str
);
518 symbolS
*symbol
= symbol_new (name
, now_seg
, frag
, value
);
519 symbol_get_bfdsym (symbol
)->flags
|= (BSF_NO_FLAGS
| BSF_LOCAL
);
520 if (arch_str
!= NULL
)
522 /* Store current $x+arch into tc_segment_info. */
523 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
= symbol
;
524 xfree ((void *) buff
);
527 /* If .fill or other data filling directive generates zero sized data,
528 then mapping symbol for the following code will have the same value.
530 Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first
531 and .text.zero.fill.last. */
532 symbolS
*first
= frag
->tc_frag_data
.first_map_symbol
;
533 symbolS
*last
= frag
->tc_frag_data
.last_map_symbol
;
534 symbolS
*removed
= NULL
;
539 know (S_GET_VALUE (first
) == S_GET_VALUE (symbol
)
541 /* Remove the old one. */
544 frag
->tc_frag_data
.first_map_symbol
= symbol
;
546 else if (last
!= NULL
)
548 /* The mapping symbols should be added in offset order. */
549 know (S_GET_VALUE (last
) <= S_GET_VALUE (symbol
));
550 /* Remove the old one. */
551 if (S_GET_VALUE (last
) == S_GET_VALUE (symbol
))
554 frag
->tc_frag_data
.last_map_symbol
= symbol
;
559 if (odd_data_padding
)
561 /* If the removed mapping symbol is $x+arch, then add it back to
563 const char *str
= strncmp (S_GET_NAME (removed
), "$xrv", 4) == 0
564 ? S_GET_NAME (removed
) + 2 : NULL
;
565 make_mapping_symbol (MAP_INSN
, frag
->fr_fix
+ 1, frag
, str
,
566 false/* odd_data_padding */);
568 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
571 /* Set the mapping state for frag_now. */
574 riscv_mapping_state (enum riscv_seg_mstate to_state
,
578 enum riscv_seg_mstate from_state
=
579 seg_info (now_seg
)->tc_segment_info_data
.map_state
;
580 bool reset_seg_arch_str
= false;
582 if (!SEG_NORMAL (now_seg
)
583 /* For now we only add the mapping symbols to text sections.
584 Therefore, the dis-assembler only show the actual contents
585 distribution for text. Other sections will be shown as
586 data without the details. */
587 || !subseg_text_p (now_seg
))
590 /* The mapping symbol should be emitted if not in the right
592 symbolS
*seg_arch_symbol
=
593 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
;
594 if (to_state
== MAP_INSN
&& seg_arch_symbol
== 0)
596 /* Always add $x+arch at the first instruction of section. */
597 reset_seg_arch_str
= true;
599 else if (seg_arch_symbol
!= 0
600 && to_state
== MAP_INSN
602 && strcmp (riscv_rps_as
.subset_list
->arch_str
,
603 S_GET_NAME (seg_arch_symbol
) + 2) != 0)
605 reset_seg_arch_str
= true;
607 else if (from_state
== to_state
)
610 valueT value
= (valueT
) (frag_now_fix () - max_chars
);
611 seg_info (now_seg
)->tc_segment_info_data
.map_state
= to_state
;
612 const char *arch_str
= reset_seg_arch_str
613 ? riscv_rps_as
.subset_list
->arch_str
: NULL
;
614 make_mapping_symbol (to_state
, value
, frag_now
, arch_str
,
615 false/* odd_data_padding */);
618 /* Add the odd bytes of paddings for riscv_handle_align. */
621 riscv_add_odd_padding_symbol (fragS
*frag
)
623 /* If there was already a mapping symbol, it should be
624 removed in the make_mapping_symbol.
626 Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */
627 make_mapping_symbol (MAP_DATA
, frag
->fr_fix
, frag
,
628 NULL
/* arch_str */, true/* odd_data_padding */);
631 /* Remove any excess mapping symbols generated for alignment frags in
632 SEC. We may have created a mapping symbol before a zero byte
633 alignment; remove it if there's a mapping symbol after the
637 riscv_check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
,
639 void *dummy ATTRIBUTE_UNUSED
)
641 segment_info_type
*seginfo
= seg_info (sec
);
644 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
647 for (fragp
= seginfo
->frchainP
->frch_root
;
649 fragp
= fragp
->fr_next
)
651 symbolS
*last
= fragp
->tc_frag_data
.last_map_symbol
;
652 fragS
*next
= fragp
->fr_next
;
654 if (last
== NULL
|| next
== NULL
)
657 /* Check the last mapping symbol if it is at the boundary of
659 if (S_GET_VALUE (last
) < next
->fr_address
)
661 know (S_GET_VALUE (last
) == next
->fr_address
);
665 symbolS
*next_first
= next
->tc_frag_data
.first_map_symbol
;
666 if (next_first
!= NULL
)
668 /* The last mapping symbol overlaps with another one
669 which at the start of the next frag.
671 Please see the gas/testsuite/gas/riscv/mapping.s:
672 .text.zero.fill.align.A and .text.zero.fill.align.B. */
673 know (S_GET_VALUE (last
) == S_GET_VALUE (next_first
));
674 symbolS
*removed
= last
;
675 if (strncmp (S_GET_NAME (last
), "$xrv", 4) == 0
676 && strcmp (S_GET_NAME (next_first
), "$x") == 0)
677 removed
= next_first
;
678 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
682 if (next
->fr_next
== NULL
)
684 /* The last mapping symbol is at the end of the section.
686 Please see the gas/testsuite/gas/riscv/mapping.s:
687 .text.last.section. */
688 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
689 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
693 /* Since we may have empty frags without any mapping symbols,
694 keep looking until the non-empty frag. */
695 if (next
->fr_address
!= next
->fr_next
->fr_address
)
698 next
= next
->fr_next
;
700 while (next
!= NULL
);
704 /* The default target format to use. */
707 riscv_target_format (void)
709 if (target_big_endian
)
710 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
712 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
715 /* Return the length of instruction INSN. */
717 static inline unsigned int
718 insn_length (const struct riscv_cl_insn
*insn
)
720 return riscv_insn_length (insn
->insn_opcode
);
723 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
726 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
729 insn
->insn_opcode
= mo
->match
;
730 insn
->insn_long_opcode
[0] = 0;
736 /* Install INSN at the location specified by its "frag" and "where" fields. */
739 install_insn (const struct riscv_cl_insn
*insn
)
741 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
742 if (insn
->insn_long_opcode
[0] != 0)
743 memcpy (f
, insn
->insn_long_opcode
, insn_length (insn
));
745 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
748 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
749 and install the opcode in the new location. */
752 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
756 if (insn
->fixp
!= NULL
)
758 insn
->fixp
->fx_frag
= frag
;
759 insn
->fixp
->fx_where
= where
;
764 /* Add INSN to the end of the output. */
767 add_fixed_insn (struct riscv_cl_insn
*insn
)
769 char *f
= frag_more (insn_length (insn
));
770 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
774 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
775 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
777 frag_grow (max_chars
);
778 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
779 frag_var (rs_machine_dependent
, max_chars
, var
,
780 subtype
, symbol
, offset
, NULL
);
783 /* Compute the length of a branch sequence, and adjust the stored length
784 accordingly. If FRAGP is NULL, the worst-case length is returned. */
787 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
789 int jump
, rvc
, length
= 8;
794 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
795 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
796 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
798 /* Assume jumps are in range; the linker will catch any that aren't. */
799 length
= jump
? 4 : 8;
801 if (fragp
->fr_symbol
!= NULL
802 && S_IS_DEFINED (fragp
->fr_symbol
)
803 && !S_IS_WEAK (fragp
->fr_symbol
)
804 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
806 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
807 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
808 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
810 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
812 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
814 else if (!jump
&& rvc
)
819 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
824 /* Information about an opcode name, mnemonics and its value. */
831 /* List for all supported opcode name. */
832 static const struct opcode_name_t opcode_name_list
[] =
877 /* Hash table for lookup opcode name. */
878 static htab_t opcode_names_hash
= NULL
;
880 /* Initialization for hash table of opcode name. */
883 init_opcode_names_hash (void)
885 const struct opcode_name_t
*opcode
;
887 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
888 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
889 as_fatal (_("internal: duplicate %s"), opcode
->name
);
892 /* Find `s` is a valid opcode name or not, return the opcode name info
895 static const struct opcode_name_t
*
896 opcode_name_lookup (char **s
)
900 struct opcode_name_t
*o
;
902 /* Find end of name. */
904 if (is_name_beginner (*e
))
906 while (is_part_of_name (*e
))
909 /* Terminate name. */
913 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
915 /* Advance to next token if one was recognized. */
925 /* All RISC-V registers belong to one of these classes. */
937 static htab_t reg_names_hash
= NULL
;
938 static htab_t csr_extra_hash
= NULL
;
940 #define ENCODE_REG_HASH(cls, n) \
941 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
942 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
943 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
946 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
948 void *hash
= ENCODE_REG_HASH (class, n
);
949 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
950 as_fatal (_("internal: duplicate %s"), name
);
954 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
958 for (i
= 0; i
< n
; i
++)
959 hash_reg_name (class, names
[i
], i
);
962 /* Init hash table csr_extra_hash to handle CSR. */
965 riscv_init_csr_hash (const char *name
,
967 enum riscv_csr_class
class,
968 enum riscv_spec_class define_version
,
969 enum riscv_spec_class abort_version
)
971 struct riscv_csr_extra
*entry
, *pre_entry
;
972 bool need_enrty
= true;
975 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
976 while (need_enrty
&& entry
!= NULL
)
978 if (entry
->csr_class
== class
979 && entry
->address
== address
980 && entry
->define_version
== define_version
981 && entry
->abort_version
== abort_version
)
991 entry
= notes_alloc (sizeof (*entry
));
992 entry
->csr_class
= class;
993 entry
->address
= address
;
994 entry
->define_version
= define_version
;
995 entry
->abort_version
= abort_version
;
998 if (pre_entry
== NULL
)
999 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
1001 pre_entry
->next
= entry
;
1004 /* Return the CSR address after checking the ISA dependency and
1005 the privileged spec version.
1007 There are one warning and two errors for CSR,
1009 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
1010 or the privileged spec, report warning only if -mcsr-check is set.
1011 Unknown CSR: the CSR has never been defined, report error.
1012 Improper CSR: the CSR number over the range (> 0xfff), report error. */
1015 riscv_csr_address (const char *csr_name
,
1016 struct riscv_csr_extra
*entry
)
1018 struct riscv_csr_extra
*saved_entry
= entry
;
1019 enum riscv_csr_class csr_class
= entry
->csr_class
;
1020 bool need_check_version
= false;
1021 bool is_rv32_only
= false;
1022 bool is_h_required
= false;
1023 const char* extension
= NULL
;
1027 case CSR_CLASS_I_32
:
1028 is_rv32_only
= true;
1031 need_check_version
= true;
1034 case CSR_CLASS_H_32
:
1035 is_rv32_only
= true;
1047 extension
= "zve32x";
1049 case CSR_CLASS_SMAIA_32
:
1050 is_rv32_only
= true;
1052 case CSR_CLASS_SMAIA
:
1053 extension
= "smaia";
1055 case CSR_CLASS_SMSTATEEN_32
:
1056 is_rv32_only
= true;
1058 case CSR_CLASS_SMSTATEEN
:
1059 extension
= "smstateen";
1061 case CSR_CLASS_SSAIA
:
1062 case CSR_CLASS_SSAIA_AND_H
:
1063 case CSR_CLASS_SSAIA_32
:
1064 case CSR_CLASS_SSAIA_AND_H_32
:
1065 is_rv32_only
= (csr_class
== CSR_CLASS_SSAIA_32
1066 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1067 is_h_required
= (csr_class
== CSR_CLASS_SSAIA_AND_H
1068 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1069 extension
= "ssaia";
1071 case CSR_CLASS_SSSTATEEN_AND_H_32
:
1072 is_rv32_only
= true;
1074 case CSR_CLASS_SSSTATEEN_AND_H
:
1075 is_h_required
= true;
1077 case CSR_CLASS_SSSTATEEN
:
1078 extension
= "ssstateen";
1080 case CSR_CLASS_SSCOFPMF_32
:
1081 is_rv32_only
= true;
1083 case CSR_CLASS_SSCOFPMF
:
1084 extension
= "sscofpmf";
1086 case CSR_CLASS_SSTC
:
1087 case CSR_CLASS_SSTC_AND_H
:
1088 case CSR_CLASS_SSTC_32
:
1089 case CSR_CLASS_SSTC_AND_H_32
:
1090 is_rv32_only
= (csr_class
== CSR_CLASS_SSTC_32
1091 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1092 is_h_required
= (csr_class
== CSR_CLASS_SSTC_AND_H
1093 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1096 case CSR_CLASS_DEBUG
:
1099 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
1102 if (riscv_opts
.csr_check
)
1104 if (is_rv32_only
&& xlen
!= 32)
1105 as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name
);
1106 if (is_h_required
&& !riscv_subset_supports (&riscv_rps_as
, "h"))
1107 as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name
);
1109 if (extension
!= NULL
1110 && !riscv_subset_supports (&riscv_rps_as
, extension
))
1111 as_warn (_("invalid CSR `%s', needs `%s' extension"),
1112 csr_name
, extension
);
1115 while (entry
!= NULL
)
1117 if (!need_check_version
1118 || (default_priv_spec
>= entry
->define_version
1119 && default_priv_spec
< entry
->abort_version
))
1121 /* Find the CSR according to the specific version. */
1122 return entry
->address
;
1124 entry
= entry
->next
;
1127 /* Can not find the CSR address from the chosen privileged version,
1128 so use the newly defined value. */
1129 if (riscv_opts
.csr_check
)
1131 const char *priv_name
= NULL
;
1132 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
1133 if (priv_name
!= NULL
)
1134 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
1135 csr_name
, priv_name
);
1138 return saved_entry
->address
;
1141 /* Return -1 if the CSR has never been defined. Otherwise, return
1145 reg_csr_lookup_internal (const char *s
)
1147 struct riscv_csr_extra
*r
=
1148 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
1153 return riscv_csr_address (s
, r
);
1157 reg_lookup_internal (const char *s
, enum reg_class
class)
1161 if (class == RCLASS_CSR
)
1162 return reg_csr_lookup_internal (s
);
1164 r
= str_hash_find (reg_names_hash
, s
);
1165 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
1168 if (riscv_subset_supports (&riscv_rps_as
, "e")
1169 && class == RCLASS_GPR
1170 && DECODE_REG_NUM (r
) > 15)
1173 return DECODE_REG_NUM (r
);
1177 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
1183 /* Find end of name. */
1185 if (is_name_beginner (*e
))
1187 while (is_part_of_name (*e
))
1190 /* Terminate name. */
1194 /* Look for the register. Advance to next token if one was recognized. */
1195 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
1205 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
1207 const char *p
= strchr (*s
, ',');
1208 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
1213 for (i
= 0; i
< size
; i
++)
1214 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0
1215 && array
[i
][len
] == '\0')
1226 flt_lookup (float f
, const float *array
, size_t size
, unsigned *regnop
)
1230 for (i
= 0; i
< size
; i
++)
1240 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1241 #define USE_IMM(n, s) \
1242 (used_bits |= ((insn_t)((1ull<<n)-1) << (s)))
1244 /* For consistency checking, verify that all bits are specified either
1245 by the match/mask part of the instruction definition, or by the
1246 operand list. The `length` could be the actual instruction length or
1247 0 for auto-detection. */
1250 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1252 const char *oparg
, *opargStart
;
1253 insn_t used_bits
= opc
->mask
;
1255 insn_t required_bits
;
1258 length
= riscv_insn_length (opc
->match
);
1259 /* We don't support instructions longer than 64-bits yet. */
1262 insn_width
= 8 * length
;
1264 required_bits
= ((insn_t
)~0ULL) >> (64 - insn_width
);
1266 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1268 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1269 opc
->name
, opc
->args
);
1273 for (oparg
= opc
->args
; *oparg
; ++oparg
)
1281 case 'U': break; /* CRS1, constrained to equal RD. */
1282 case 'c': break; /* CRS1, constrained to equal sp. */
1283 case 'T': /* CRS2, floating point. */
1284 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1285 case 'S': /* CRS1S, floating point. */
1286 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1287 case 'w': break; /* CRS1S, constrained to equal RD. */
1288 case 'D': /* CRS2S, floating point. */
1289 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1290 case 'x': break; /* CRS2S, constrained to equal RD. */
1291 case 'z': break; /* CRS2S, constrained to be x0. */
1292 case '>': /* CITYPE immediate, compressed shift. */
1293 case 'u': /* CITYPE immediate, compressed lui. */
1294 case 'v': /* CITYPE immediate, li to compressed lui. */
1295 case 'o': /* CITYPE immediate, allow zero. */
1296 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1297 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1298 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1299 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1300 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1301 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1302 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1303 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1304 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1305 /* CLTYPE and CSTYPE have the same immediate encoding. */
1306 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1307 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1308 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1309 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1310 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1311 case 'F': /* Compressed funct for .insn directive. */
1314 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1315 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1316 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1317 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1319 goto unknown_validate_operand
;
1323 goto unknown_validate_operand
;
1325 break; /* end RVC */
1330 case 'f': USE_BITS (OP_MASK_VD
, OP_SH_VD
); break;
1331 case 'e': USE_BITS (OP_MASK_VWD
, OP_SH_VWD
); break;
1332 case 's': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
); break;
1333 case 't': USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1334 case 'u': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1335 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1336 case 'v': USE_BITS (OP_MASK_VD
, OP_SH_VD
);
1337 USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1338 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1340 case 'b': used_bits
|= ENCODE_RVV_VB_IMM (-1U); break;
1341 case 'c': used_bits
|= ENCODE_RVV_VC_IMM (-1U); break;
1344 case 'k': USE_BITS (OP_MASK_VIMM
, OP_SH_VIMM
); break;
1345 case 'l': used_bits
|= ENCODE_RVV_VI_UIMM6 (-1U); break;
1346 case 'm': USE_BITS (OP_MASK_VMASK
, OP_SH_VMASK
); break;
1347 case 'M': break; /* Macro operand, must be a mask register. */
1348 case 'T': break; /* Macro operand, must be a vector register. */
1350 goto unknown_validate_operand
;
1352 break; /* end RVV */
1356 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1357 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1358 case 'A': break; /* Macro operand, must be symbol. */
1359 case 'B': break; /* Macro operand, must be symbol or constant. */
1360 case 'c': break; /* Macro operand, must be symbol or constant. */
1361 case 'I': break; /* Macro operand, must be constant. */
1362 case 'D': /* RD, floating point. */
1363 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1364 case 'y': USE_BITS (OP_MASK_BS
, OP_SH_BS
); break;
1365 case 'Y': USE_BITS (OP_MASK_RNUM
, OP_SH_RNUM
); break;
1366 case 'Z': /* RS1, CSR number. */
1367 case 'S': /* RS1, floating point. */
1368 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1369 case 'U': /* RS1 and RS2 are the same, floating point. */
1370 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1372 case 'T': /* RS2, floating point. */
1373 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1374 case 'R': /* RS3, floating point. */
1375 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1376 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1377 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1378 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1379 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1380 case 'o': /* ITYPE immediate, load displacement. */
1381 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1382 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1383 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1384 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1385 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1386 case 'z': break; /* Zero immediate. */
1387 case '[': break; /* Unused operand. */
1388 case ']': break; /* Unused operand. */
1389 case '0': break; /* AMO displacement, must to zero. */
1390 case '1': break; /* Relaxation operand. */
1391 case 'F': /* Funct for .insn directive. */
1394 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1395 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1396 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1398 goto unknown_validate_operand
;
1401 case 'O': /* Opcode for .insn directive. */
1404 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1405 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1407 goto unknown_validate_operand
;
1410 case 'W': /* Various operands. */
1416 case 'f': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1418 goto unknown_validate_operand
;
1424 case 'v': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1426 goto unknown_validate_operand
;
1432 /* byte immediate operators, load/store byte insns. */
1433 case 'h': used_bits
|= ENCODE_ZCB_HALFWORD_UIMM (-1U); break;
1434 /* halfword immediate operators, load/store halfword insns. */
1435 case 'b': used_bits
|= ENCODE_ZCB_BYTE_UIMM (-1U); break;
1438 goto unknown_validate_operand
;
1442 goto unknown_validate_operand
;
1445 case 'X': /* Integer immediate. */
1452 case 'l': /* Literal. */
1453 oparg
+= strcspn(oparg
, ",") - 1;
1455 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
1457 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
1460 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1462 goto unknown_validate_operand
;
1463 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1469 goto unknown_validate_operand
;
1474 unknown_validate_operand
:
1475 as_bad (_("internal: bad RISC-V opcode "
1476 "(unknown operand type `%s'): %s %s"),
1477 opargStart
, opc
->name
, opc
->args
);
1482 if (used_bits
!= required_bits
)
1484 as_bad (_("internal: bad RISC-V opcode "
1485 "(bits %#llx undefined or invalid): %s %s"),
1486 (unsigned long long)(used_bits
^ required_bits
),
1487 opc
->name
, opc
->args
);
1495 struct percent_op_match
1498 bfd_reloc_code_real_type reloc
;
1501 /* Common hash table initialization function for instruction and .insn
1505 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1506 bool insn_directive_p
)
1510 htab_t hash
= str_htab_create ();
1511 while (opcodes
[i
].name
)
1513 const char *name
= opcodes
[i
].name
;
1514 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1515 as_fatal (_("internal: duplicate %s"), name
);
1519 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1521 if (insn_directive_p
)
1522 length
= ((name
[0] == 'c') ? 2 : 4);
1524 length
= 0; /* Let assembler determine the length. */
1525 if (!validate_riscv_insn (&opcodes
[i
], length
))
1526 as_fatal (_("internal: broken assembler. "
1527 "No assembly attempted"));
1530 gas_assert (!insn_directive_p
);
1533 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1539 /* This function is called once, at assembler startup time. It should set up
1540 all the tables, etc. that the MD part of the assembler will need. */
1545 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1547 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1548 as_warn (_("could not set architecture and machine"));
1550 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1551 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1553 reg_names_hash
= str_htab_create ();
1554 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1555 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1556 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1557 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1558 hash_reg_names (RCLASS_VECR
, riscv_vecr_names_numeric
, NVECR
);
1559 hash_reg_names (RCLASS_VECM
, riscv_vecm_names_numeric
, NVECM
);
1560 /* Add "fp" as an alias for "s0". */
1561 hash_reg_name (RCLASS_GPR
, "fp", 8);
1563 /* Create and insert CSR hash tables. */
1564 csr_extra_hash
= str_htab_create ();
1565 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1566 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1567 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1568 DECLARE_CSR(name, num, class, define_version, abort_version);
1569 #include "opcode/riscv-opc.h"
1572 opcode_names_hash
= str_htab_create ();
1573 init_opcode_names_hash ();
1575 /* Set the default alignment for the text section. */
1576 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1580 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1587 case BFD_RELOC_RISCV_HI20
:
1588 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1590 case BFD_RELOC_RISCV_LO12_S
:
1591 return ENCODE_STYPE_IMM (value
);
1593 case BFD_RELOC_RISCV_LO12_I
:
1594 return ENCODE_ITYPE_IMM (value
);
1601 /* Output an instruction. IP is the instruction information.
1602 ADDRESS_EXPR is an operand of the instruction to be used with
1606 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1607 bfd_reloc_code_real_type reloc_type
)
1609 dwarf2_emit_insn (0);
1611 if (reloc_type
!= BFD_RELOC_UNUSED
)
1613 reloc_howto_type
*howto
;
1615 gas_assert (address_expr
);
1616 if (reloc_type
== BFD_RELOC_12_PCREL
1617 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1619 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1620 int best_case
= insn_length (ip
);
1621 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1623 if (now_seg
== absolute_section
)
1625 as_bad (_("relaxable branches not supported in absolute section"));
1629 add_relaxed_insn (ip
, worst_case
, best_case
,
1630 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1631 address_expr
->X_add_symbol
,
1632 address_expr
->X_add_number
);
1637 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1639 as_bad (_("internal: unsupported RISC-V relocation number %d"),
1642 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1643 bfd_get_reloc_size (howto
),
1644 address_expr
, false, reloc_type
);
1646 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1650 add_fixed_insn (ip
);
1652 /* We need to start a new frag after any instruction that can be
1653 optimized away or compressed by the linker during relaxation, to prevent
1654 the assembler from computing static offsets across such an instruction.
1655 This is necessary to get correct EH info. */
1656 if (reloc_type
== BFD_RELOC_RISCV_HI20
1657 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1658 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1659 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1661 frag_wane (frag_now
);
1666 /* Build an instruction created by a macro expansion. This is passed
1667 a pointer to the count of instructions created so far, an expression,
1668 the name of the instruction to build, an operand format string, and
1669 corresponding arguments. */
1672 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1674 const struct riscv_opcode
*mo
;
1675 struct riscv_cl_insn insn
;
1676 bfd_reloc_code_real_type r
;
1678 const char *fmtStart
;
1680 va_start (args
, fmt
);
1682 r
= BFD_RELOC_UNUSED
;
1683 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1686 /* Find a non-RVC variant of the instruction. append_insn will compress
1688 while (riscv_insn_length (mo
->match
) < 4)
1690 gas_assert (strcmp (name
, mo
->name
) == 0);
1692 create_insn (&insn
, mo
);
1702 INSERT_OPERAND (VD
, insn
, va_arg (args
, int));
1705 INSERT_OPERAND (VS1
, insn
, va_arg (args
, int));
1708 INSERT_OPERAND (VS2
, insn
, va_arg (args
, int));
1712 int reg
= va_arg (args
, int);
1715 INSERT_OPERAND (VMASK
, insn
, 1);
1720 INSERT_OPERAND (VMASK
, insn
, 0);
1724 goto unknown_macro_argument
;
1727 goto unknown_macro_argument
;
1732 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1735 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1738 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1744 gas_assert (ep
!= NULL
);
1745 r
= va_arg (args
, int);
1753 unknown_macro_argument
:
1754 as_fatal (_("internal: invalid macro argument `%s'"), fmtStart
);
1759 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1761 append_insn (&insn
, ep
, r
);
1764 /* Build an instruction created by a macro expansion. Like md_assemble but
1765 accept a printf-style format string and arguments. */
1768 md_assemblef (const char *format
, ...)
1774 va_start (ap
, format
);
1776 r
= vasprintf (&buf
, format
, ap
);
1779 as_fatal (_("internal: vasprintf failed"));
1787 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1791 normalize_constant_expr (expressionS
*ex
)
1795 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1796 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1797 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1801 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1802 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1805 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1808 if (ex
->X_op
== O_big
)
1809 as_bad (_("unsupported large constant"));
1810 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1811 as_bad (_("unknown CSR `%s'"),
1812 S_GET_NAME (ex
->X_add_symbol
));
1813 else if (ex
->X_op
!= O_constant
)
1814 as_bad (_("instruction %s requires absolute expression"),
1816 normalize_constant_expr (ex
);
1820 make_internal_label (void)
1822 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1826 /* Load an entry from the GOT. */
1829 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1830 const char *lo_insn
, const char *lo_pattern
,
1831 bfd_reloc_code_real_type hi_reloc
,
1832 bfd_reloc_code_real_type lo_reloc
)
1835 ep2
.X_op
= O_symbol
;
1836 ep2
.X_add_symbol
= make_internal_label ();
1837 ep2
.X_add_number
= 0;
1839 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1840 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1844 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1845 bfd_reloc_code_real_type hi_reloc
,
1846 bfd_reloc_code_real_type lo_reloc
)
1848 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1852 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1853 bfd_reloc_code_real_type hi_reloc
,
1854 bfd_reloc_code_real_type lo_reloc
)
1856 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1859 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1862 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1863 bfd_reloc_code_real_type reloc
)
1865 /* Ensure the jalr is emitted to the same frag as the auipc. */
1867 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1868 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1869 /* See comment at end of append_insn. */
1870 frag_wane (frag_now
);
1874 /* Load an integer constant into a register. */
1877 load_const (int reg
, expressionS
*ep
)
1879 int shift
= RISCV_IMM_BITS
;
1880 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1881 expressionS upper
= *ep
, lower
= *ep
;
1882 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1883 upper
.X_add_number
-= lower
.X_add_number
;
1885 if (ep
->X_op
!= O_constant
)
1887 as_bad (_("unsupported large constant"));
1891 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1893 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1894 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1897 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1898 load_const (reg
, &upper
);
1900 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1901 if (lower
.X_add_number
!= 0)
1902 md_assemblef ("addi x%d, x%d, %" PRId64
, reg
, reg
,
1903 (int64_t) lower
.X_add_number
);
1907 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1910 if (upper
.X_add_number
!= 0)
1912 /* Discard low part and zero-extend upper immediate. */
1913 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1915 md_assemblef ("lui x%d, 0x%" PRIx64
, reg
, (uint64_t) upper_imm
);
1919 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1920 md_assemblef ("%s x%d, x%d, %" PRId64
, ADD32_INSN
, reg
, hi_reg
,
1921 (int64_t) lower
.X_add_number
);
1925 /* Zero extend and sign extend byte/half-word/word. */
1928 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1932 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1933 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1937 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1938 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1942 /* Expand RISC-V Vector macros into one or more instructions. */
1945 vector_macro (struct riscv_cl_insn
*ip
)
1947 int vd
= (ip
->insn_opcode
>> OP_SH_VD
) & OP_MASK_VD
;
1948 int vs1
= (ip
->insn_opcode
>> OP_SH_VS1
) & OP_MASK_VS1
;
1949 int vs2
= (ip
->insn_opcode
>> OP_SH_VS2
) & OP_MASK_VS2
;
1950 int vm
= (ip
->insn_opcode
>> OP_SH_VMASK
) & OP_MASK_VMASK
;
1951 int vtemp
= (ip
->insn_opcode
>> OP_SH_VFUNCT6
) & OP_MASK_VFUNCT6
;
1952 int mask
= ip
->insn_mo
->mask
;
1960 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1961 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1966 /* Masked. Have vtemp to avoid overlap constraints. */
1969 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1970 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1974 /* Preserve the value of vd if not updating by vm. */
1975 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1976 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1977 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1978 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1983 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1984 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1985 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1988 as_bad (_("must provide temp if destination overlaps mask"));
1995 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1996 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
2001 /* Masked. Have vtemp to avoid overlap constraints. */
2004 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
2005 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
2009 /* Preserve the value of vd if not updating by vm. */
2010 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
2011 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
2012 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
2013 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
2018 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
2019 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
2020 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
2023 as_bad (_("must provide temp if destination overlaps mask"));
2031 /* Expand RISC-V assembly macros into one or more instructions. */
2034 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
2035 bfd_reloc_code_real_type
*imm_reloc
)
2037 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
2038 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
2039 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
2040 int mask
= ip
->insn_mo
->mask
;
2045 load_const (rd
, imm_expr
);
2051 /* Load the address of a symbol into a register. */
2052 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
2053 as_bad (_("offset too large"));
2055 if (imm_expr
->X_op
== O_constant
)
2056 load_const (rd
, imm_expr
);
2057 /* Global PIC symbol. */
2058 else if ((riscv_opts
.pic
&& mask
== M_LA
)
2060 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2061 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2062 /* Local PIC symbol, or any non-PIC symbol. */
2064 pcrel_load (rd
, rd
, imm_expr
, "addi",
2065 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2069 pcrel_load (rd
, rd
, imm_expr
, "addi",
2070 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2074 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2075 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2079 pcrel_load (rd
, rd
, imm_expr
, "lb",
2080 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2084 pcrel_load (rd
, rd
, imm_expr
, "lbu",
2085 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2089 pcrel_load (rd
, rd
, imm_expr
, "lh",
2090 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2094 pcrel_load (rd
, rd
, imm_expr
, "lhu",
2095 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2099 pcrel_load (rd
, rd
, imm_expr
, "lw",
2100 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2104 pcrel_load (rd
, rd
, imm_expr
, "lwu",
2105 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2109 pcrel_load (rd
, rd
, imm_expr
, "ld",
2110 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2114 pcrel_load (rd
, rs1
, imm_expr
, "flw",
2115 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2119 pcrel_load (rd
, rs1
, imm_expr
, "fld",
2120 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2124 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
2125 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2129 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
2130 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2134 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
2135 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2139 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
2140 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2144 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
2145 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2149 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
2150 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2154 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
2158 riscv_ext (rd
, rs1
, xlen
- 16, false);
2162 riscv_ext (rd
, rs1
, xlen
- 32, false);
2166 riscv_ext (rd
, rs1
, xlen
- 8, true);
2170 riscv_ext (rd
, rs1
, xlen
- 16, true);
2179 pcrel_load (rd
, rs1
, imm_expr
, "flh",
2180 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2183 pcrel_store (rs2
, rs1
, imm_expr
, "fsh",
2184 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2188 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
2193 static const struct percent_op_match percent_op_utype
[] =
2195 {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
2196 {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
2197 {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
2198 {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
2199 {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
2200 {"hi", BFD_RELOC_RISCV_HI20
},
2204 static const struct percent_op_match percent_op_itype
[] =
2206 {"lo", BFD_RELOC_RISCV_LO12_I
},
2207 {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
2208 {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
2212 static const struct percent_op_match percent_op_stype
[] =
2214 {"lo", BFD_RELOC_RISCV_LO12_S
},
2215 {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
2216 {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
2220 static const struct percent_op_match percent_op_rtype
[] =
2222 {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
2226 static const struct percent_op_match percent_op_null
[] =
2231 /* Return true if *STR points to a relocation operator. When returning true,
2232 move *STR over the operator and store its relocation code in *RELOC.
2233 Leave both *STR and *RELOC alone when returning false. */
2236 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
2237 const struct percent_op_match
*percent_op
)
2239 for ( ; percent_op
->str
; percent_op
++)
2240 if (strncasecmp (*str
+ 1, percent_op
->str
, strlen (percent_op
->str
)) == 0)
2242 size_t len
= 1 + strlen (percent_op
->str
);
2244 while (ISSPACE ((*str
)[len
]))
2246 if ((*str
)[len
] != '(')
2250 *reloc
= percent_op
->reloc
;
2252 /* Check whether the output BFD supports this relocation.
2253 If not, issue an error and fall back on something safe. */
2254 if (*reloc
!= BFD_RELOC_UNUSED
2255 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
2257 as_bad ("internal: relocation %s isn't supported by the "
2258 "current ABI", percent_op
->str
);
2259 *reloc
= BFD_RELOC_UNUSED
;
2267 my_getExpression (expressionS
*ep
, char *str
)
2271 save_in
= input_line_pointer
;
2272 input_line_pointer
= str
;
2274 expr_parse_end
= input_line_pointer
;
2275 input_line_pointer
= save_in
;
2278 /* Parse string STR as a 16-bit relocatable operand. Store the
2279 expression in *EP and the relocation, if any, in RELOC.
2280 Return the number of relocation operators used (0 or 1).
2282 On exit, EXPR_PARSE_END points to the first character after the
2286 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2287 char *str
, const struct percent_op_match
*percent_op
)
2290 unsigned crux_depth
, str_depth
;
2291 bool orig_probing
= probing_insn_operands
;
2294 /* Search for the start of the main expression.
2296 End the loop with CRUX pointing to the start of the main expression and
2297 with CRUX_DEPTH containing the number of open brackets at that point. */
2304 crux_depth
= str_depth
;
2306 /* Skip over whitespace and brackets, keeping count of the number
2308 while (*str
== ' ' || *str
== '\t' || *str
== '(')
2314 && parse_relocation (&str
, reloc
, percent_op
));
2318 /* expression() will choke on anything looking like an (unrecognized)
2319 relocation specifier. Don't even call it, avoiding multiple (and
2320 perhaps redundant) error messages; our caller will issue one. */
2321 ep
->X_op
= O_illegal
;
2325 /* Anything inside parentheses or subject to a relocation operator cannot
2326 be a register and hence can be treated the same as operands to
2327 directives (other than .insn). */
2328 if (str_depth
|| reloc_index
)
2329 probing_insn_operands
= false;
2331 my_getExpression (ep
, crux
);
2332 str
= expr_parse_end
;
2334 probing_insn_operands
= orig_probing
;
2336 /* Match every open bracket. */
2337 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
2342 as_bad ("unclosed '('");
2344 expr_parse_end
= str
;
2349 /* Parse opcode name, could be an mnemonics or number. */
2352 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2355 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
2359 ep
->X_op
= O_constant
;
2360 ep
->X_add_number
= o
->val
;
2364 return my_getSmallExpression (ep
, reloc
, str
, percent_op_null
);
2367 /* Parse string STR as a vsetvli operand. Store the expression in *EP.
2368 On exit, EXPR_PARSE_END points to the first character after the
2372 my_getVsetvliExpression (expressionS
*ep
, char *str
)
2374 unsigned int vsew_value
= 0, vlmul_value
= 0;
2375 unsigned int vta_value
= 0, vma_value
= 0;
2376 bfd_boolean vsew_found
= FALSE
, vlmul_found
= FALSE
;
2377 bfd_boolean vta_found
= FALSE
, vma_found
= FALSE
;
2379 if (arg_lookup (&str
, riscv_vsew
, ARRAY_SIZE (riscv_vsew
), &vsew_value
))
2384 as_bad (_("multiple vsew constants"));
2387 if (arg_lookup (&str
, riscv_vlmul
, ARRAY_SIZE (riscv_vlmul
), &vlmul_value
))
2392 as_bad (_("multiple vlmul constants"));
2395 if (arg_lookup (&str
, riscv_vta
, ARRAY_SIZE (riscv_vta
), &vta_value
))
2400 as_bad (_("multiple vta constants"));
2403 if (arg_lookup (&str
, riscv_vma
, ARRAY_SIZE (riscv_vma
), &vma_value
))
2408 as_bad (_("multiple vma constants"));
2412 if (vsew_found
|| vlmul_found
|| vta_found
|| vma_found
)
2414 ep
->X_op
= O_constant
;
2415 ep
->X_add_number
= (vlmul_value
<< OP_SH_VLMUL
)
2416 | (vsew_value
<< OP_SH_VSEW
)
2417 | (vta_value
<< OP_SH_VTA
)
2418 | (vma_value
<< OP_SH_VMA
);
2419 expr_parse_end
= str
;
2423 my_getExpression (ep
, str
);
2424 str
= expr_parse_end
;
2428 /* Detect and handle implicitly zero load-store offsets. For example,
2429 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such
2430 an implicit offset was detected. */
2433 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
2435 /* Check whether there is only a single bracketed expression left.
2436 If so, it must be the base register and the constant must be zero. */
2437 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
2439 ep
->X_op
= O_constant
;
2440 ep
->X_add_number
= 0;
2447 /* All RISC-V CSR instructions belong to one of these classes. */
2456 /* Return which CSR instruction is checking. */
2458 static enum csr_insn_type
2459 riscv_csr_insn_type (insn_t insn
)
2461 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
2462 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
2464 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
2465 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
2467 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
2468 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
2471 return INSN_NOT_CSR
;
2474 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
2475 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
2476 CSR address is 0x3. */
2479 riscv_csr_read_only_check (insn_t insn
)
2481 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
2482 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
2483 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
2484 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
2487 && (((csr_insn
== INSN_CSRRS
2488 || csr_insn
== INSN_CSRRC
)
2490 || csr_insn
== INSN_CSRRW
))
2496 /* Return true if it is a privileged instruction. Otherwise, return false.
2498 uret is actually a N-ext instruction. So it is better to regard it as
2499 an user instruction rather than the priv instruction.
2501 hret is used to return from traps in H-mode. H-mode is removed since
2502 the v1.10 priv spec, but probably be added in the new hypervisor spec.
2503 Therefore, hret should be controlled by the hypervisor spec rather than
2504 priv spec in the future.
2506 dret is defined in the debug spec, so it should be checked in the future,
2510 riscv_is_priv_insn (insn_t insn
)
2512 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
2513 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
2514 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
2515 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
2516 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
2517 check it here to keep the compatible. */
2518 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
2521 static symbolS
*deferred_sym_rootP
;
2522 static symbolS
*deferred_sym_lastP
;
2523 /* Since symbols can't easily be freed, try to recycle ones which weren't
2525 static symbolS
*orphan_sym_rootP
;
2526 static symbolS
*orphan_sym_lastP
;
2528 /* This routine assembles an instruction into its binary format. As a
2529 side effect, it sets the global variable imm_reloc to the type of
2530 relocation to do if one of the operands is an address expression. */
2532 static struct riscv_ip_error
2533 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
2534 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
2536 /* The operand string defined in the riscv_opcodes. */
2537 const char *oparg
, *opargStart
;
2538 /* The parsed operands from assembly. */
2539 char *asarg
, *asargStart
;
2541 struct riscv_opcode
*insn
;
2543 const struct percent_op_match
*p
;
2544 struct riscv_ip_error error
;
2545 error
.msg
= "unrecognized opcode";
2546 error
.statement
= str
;
2547 error
.missing_ext
= NULL
;
2548 /* Indicate we are assembling instruction with CSR. */
2549 bool insn_with_csr
= false;
2551 /* Parse the name of the instruction. Terminate the string if whitespace
2552 is found so that str_hash_find only sees the name part of the string. */
2553 for (asarg
= str
; *asarg
!= '\0'; ++asarg
)
2554 if (ISSPACE (*asarg
))
2561 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2563 probing_insn_operands
= true;
2566 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2568 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2571 if (!riscv_multi_subset_supports (&riscv_rps_as
, insn
->insn_class
))
2573 error
.missing_ext
= riscv_multi_subset_supports_ext (&riscv_rps_as
,
2578 /* Reset error message of the previous round. */
2579 error
.msg
= _("illegal operands");
2580 error
.missing_ext
= NULL
;
2582 /* Purge deferred symbols from the previous round, if any. */
2583 while (deferred_sym_rootP
)
2585 symbolS
*sym
= deferred_sym_rootP
;
2587 symbol_remove (sym
, &deferred_sym_rootP
, &deferred_sym_lastP
);
2588 symbol_append (sym
, orphan_sym_lastP
, &orphan_sym_rootP
,
2592 create_insn (ip
, insn
);
2594 imm_expr
->X_op
= O_absent
;
2595 *imm_reloc
= BFD_RELOC_UNUSED
;
2596 p
= percent_op_null
;
2598 for (oparg
= insn
->args
;; ++oparg
)
2601 asarg
+= strspn (asarg
, " \t");
2604 case '\0': /* End of args. */
2605 if (insn
->pinfo
!= INSN_MACRO
)
2607 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2610 /* For .insn, insn->match and insn->mask are 0. */
2611 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2617 if (riscv_is_priv_insn (ip
->insn_opcode
))
2618 explicit_priv_attr
= true;
2620 /* Check if we write a read-only CSR by the CSR
2623 && riscv_opts
.csr_check
2624 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2626 /* Restore the character in advance, since we want to
2627 report the detailed warning message here. */
2629 *(asargStart
- 1) = save_c
;
2630 as_warn (_("read-only CSR is written `%s'"), str
);
2631 insn_with_csr
= false;
2634 /* The (segmant) load and store with EEW 64 cannot be used
2635 when zve32x is enabled. */
2636 if (ip
->insn_mo
->pinfo
& INSN_V_EEW64
2637 && riscv_subset_supports (&riscv_rps_as
, "zve32x")
2638 && !riscv_subset_supports (&riscv_rps_as
, "zve64x"))
2640 error
.msg
= _("illegal opcode for zve32x");
2647 /* Successful assembly. */
2649 insn_with_csr
= false;
2651 /* Commit deferred symbols, if any. */
2652 while (deferred_sym_rootP
)
2654 symbolS
*sym
= deferred_sym_rootP
;
2656 symbol_remove (sym
, &deferred_sym_rootP
,
2657 &deferred_sym_lastP
);
2658 symbol_append (sym
, symbol_lastP
, &symbol_rootP
,
2660 symbol_table_insert (sym
);
2667 case 's': /* RS1 x8-x15. */
2668 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2669 || !(regno
>= 8 && regno
<= 15))
2671 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2673 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2674 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2675 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2678 case 't': /* RS2 x8-x15. */
2679 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2680 || !(regno
>= 8 && regno
<= 15))
2682 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2684 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2685 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2686 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2689 case 'U': /* RS1, constrained to equal RD. */
2690 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2691 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2695 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2697 INSERT_OPERAND (CRS2
, *ip
, regno
);
2699 case 'c': /* RS1, constrained to equal sp. */
2700 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2704 case 'z': /* RS2, constrained to equal x0. */
2705 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2709 case '>': /* Shift amount, 0 - (XLEN-1). */
2710 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2711 || imm_expr
->X_op
!= O_constant
2712 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2714 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2716 asarg
= expr_parse_end
;
2717 imm_expr
->X_op
= O_absent
;
2720 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2721 || imm_expr
->X_op
!= O_constant
2722 || imm_expr
->X_add_number
< 0
2723 || imm_expr
->X_add_number
>= 32
2724 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2726 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2729 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2730 || imm_expr
->X_op
!= O_constant
2731 || imm_expr
->X_add_number
< 0
2732 || imm_expr
->X_add_number
>= 64
2733 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2735 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2738 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2739 || imm_expr
->X_op
!= O_constant
2740 || imm_expr
->X_add_number
< 0
2741 || imm_expr
->X_add_number
>= 256
2742 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2744 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2747 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2748 || imm_expr
->X_op
!= O_constant
2749 || imm_expr
->X_add_number
== 0
2750 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2752 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2755 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2757 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2758 || imm_expr
->X_op
!= O_constant
2759 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2761 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2764 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2766 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2767 || imm_expr
->X_op
!= O_constant
2768 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2770 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2773 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2775 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2776 || imm_expr
->X_op
!= O_constant
2777 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2780 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2783 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2785 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2786 || imm_expr
->X_op
!= O_constant
2787 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2790 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2793 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2794 || imm_expr
->X_op
!= O_constant
2795 /* C.addiw, c.li, and c.andi allow zero immediate.
2796 C.addi allows zero immediate as hint. Otherwise this
2798 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2800 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2803 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2804 || imm_expr
->X_op
!= O_constant
2805 || imm_expr
->X_add_number
== 0
2806 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2809 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2812 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2813 || imm_expr
->X_op
!= O_constant
2814 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2817 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2820 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2822 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2823 || imm_expr
->X_op
!= O_constant
2824 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2827 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2830 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2832 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2833 || imm_expr
->X_op
!= O_constant
2834 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2837 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2840 p
= percent_op_utype
;
2841 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
2844 if (imm_expr
->X_op
!= O_constant
2845 || imm_expr
->X_add_number
<= 0
2846 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2847 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2848 && (imm_expr
->X_add_number
<
2849 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2851 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2854 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2855 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2856 || ((int32_t)imm_expr
->X_add_number
2857 != imm_expr
->X_add_number
))
2859 imm_expr
->X_add_number
=
2860 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2866 case 'S': /* Floating-point RS1 x8-x15. */
2867 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2868 || !(regno
>= 8 && regno
<= 15))
2870 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2872 case 'D': /* Floating-point RS2 x8-x15. */
2873 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2874 || !(regno
>= 8 && regno
<= 15))
2876 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2878 case 'T': /* Floating-point RS2. */
2879 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
))
2881 INSERT_OPERAND (CRS2
, *ip
, regno
);
2887 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2888 || imm_expr
->X_op
!= O_constant
2889 || imm_expr
->X_add_number
< 0
2890 || imm_expr
->X_add_number
>= 64)
2892 as_bad (_("bad value for compressed funct6 "
2893 "field, value must be 0...63"));
2896 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2897 imm_expr
->X_op
= O_absent
;
2898 asarg
= expr_parse_end
;
2902 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2903 || imm_expr
->X_op
!= O_constant
2904 || imm_expr
->X_add_number
< 0
2905 || imm_expr
->X_add_number
>= 16)
2907 as_bad (_("bad value for compressed funct4 "
2908 "field, value must be 0...15"));
2911 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2912 imm_expr
->X_op
= O_absent
;
2913 asarg
= expr_parse_end
;
2917 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2918 || imm_expr
->X_op
!= O_constant
2919 || imm_expr
->X_add_number
< 0
2920 || imm_expr
->X_add_number
>= 8)
2922 as_bad (_("bad value for compressed funct3 "
2923 "field, value must be 0...7"));
2926 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2927 imm_expr
->X_op
= O_absent
;
2928 asarg
= expr_parse_end
;
2932 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2933 || imm_expr
->X_op
!= O_constant
2934 || imm_expr
->X_add_number
< 0
2935 || imm_expr
->X_add_number
>= 4)
2937 as_bad (_("bad value for compressed funct2 "
2938 "field, value must be 0...3"));
2941 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2942 imm_expr
->X_op
= O_absent
;
2943 asarg
= expr_parse_end
;
2947 goto unknown_riscv_ip_operand
;
2952 goto unknown_riscv_ip_operand
;
2954 break; /* end RVC */
2960 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2962 INSERT_OPERAND (VD
, *ip
, regno
);
2965 case 'e': /* AMO VD */
2966 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
) && regno
== 0)
2967 INSERT_OPERAND (VWD
, *ip
, 0);
2968 else if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2970 INSERT_OPERAND (VWD
, *ip
, 1);
2971 INSERT_OPERAND (VD
, *ip
, regno
);
2977 case 'f': /* AMO VS3 */
2978 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2980 if (!EXTRACT_OPERAND (VWD
, ip
->insn_opcode
))
2981 INSERT_OPERAND (VD
, *ip
, regno
);
2984 /* VS3 must match VD. */
2985 if (EXTRACT_OPERAND (VD
, ip
->insn_opcode
) != regno
)
2991 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2993 INSERT_OPERAND (VS1
, *ip
, regno
);
2997 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2999 INSERT_OPERAND (VS2
, *ip
, regno
);
3002 case 'u': /* VS1 == VS2 */
3003 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
3005 INSERT_OPERAND (VS1
, *ip
, regno
);
3006 INSERT_OPERAND (VS2
, *ip
, regno
);
3009 case 'v': /* VD == VS1 == VS2 */
3010 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
3012 INSERT_OPERAND (VD
, *ip
, regno
);
3013 INSERT_OPERAND (VS1
, *ip
, regno
);
3014 INSERT_OPERAND (VS2
, *ip
, regno
);
3017 /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
3018 and is used to choose vs1/rs1/frs1/imm or vs2 for
3019 v[f]merge. It use the same encoding as the vector mask
3022 if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
) && regno
== 0)
3026 case 'b': /* vtypei for vsetivli */
3027 my_getVsetvliExpression (imm_expr
, asarg
);
3028 check_absolute_expr (ip
, imm_expr
, FALSE
);
3029 if (!VALID_RVV_VB_IMM (imm_expr
->X_add_number
))
3030 as_bad (_("bad value for vsetivli immediate field, "
3031 "value must be 0..1023"));
3033 |= ENCODE_RVV_VB_IMM (imm_expr
->X_add_number
);
3034 imm_expr
->X_op
= O_absent
;
3035 asarg
= expr_parse_end
;
3038 case 'c': /* vtypei for vsetvli */
3039 my_getVsetvliExpression (imm_expr
, asarg
);
3040 check_absolute_expr (ip
, imm_expr
, FALSE
);
3041 if (!VALID_RVV_VC_IMM (imm_expr
->X_add_number
))
3042 as_bad (_("bad value for vsetvli immediate field, "
3043 "value must be 0..2047"));
3045 |= ENCODE_RVV_VC_IMM (imm_expr
->X_add_number
);
3046 imm_expr
->X_op
= O_absent
;
3047 asarg
= expr_parse_end
;
3050 case 'i': /* vector arith signed immediate */
3051 my_getExpression (imm_expr
, asarg
);
3052 check_absolute_expr (ip
, imm_expr
, FALSE
);
3053 if (imm_expr
->X_add_number
> 15
3054 || imm_expr
->X_add_number
< -16)
3055 as_bad (_("bad value for vector immediate field, "
3056 "value must be -16...15"));
3057 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
3058 imm_expr
->X_op
= O_absent
;
3059 asarg
= expr_parse_end
;
3062 case 'j': /* vector arith unsigned immediate */
3063 my_getExpression (imm_expr
, asarg
);
3064 check_absolute_expr (ip
, imm_expr
, FALSE
);
3065 if (imm_expr
->X_add_number
< 0
3066 || imm_expr
->X_add_number
>= 32)
3067 as_bad (_("bad value for vector immediate field, "
3068 "value must be 0...31"));
3069 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
3070 imm_expr
->X_op
= O_absent
;
3071 asarg
= expr_parse_end
;
3074 case 'k': /* vector arith signed immediate, minus 1 */
3075 my_getExpression (imm_expr
, asarg
);
3076 check_absolute_expr (ip
, imm_expr
, FALSE
);
3077 if (imm_expr
->X_add_number
> 16
3078 || imm_expr
->X_add_number
< -15)
3079 as_bad (_("bad value for vector immediate field, "
3080 "value must be -15...16"));
3081 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
- 1);
3082 imm_expr
->X_op
= O_absent
;
3083 asarg
= expr_parse_end
;
3086 case 'l': /* 6-bit vector arith unsigned immediate */
3087 my_getExpression (imm_expr
, asarg
);
3088 check_absolute_expr (ip
, imm_expr
, FALSE
);
3089 if (imm_expr
->X_add_number
< 0
3090 || imm_expr
->X_add_number
>= 64)
3091 as_bad (_("bad value for vector immediate field, "
3092 "value must be 0...63"));
3093 ip
->insn_opcode
|= ENCODE_RVV_VI_UIMM6 (imm_expr
->X_add_number
);
3094 imm_expr
->X_op
= O_absent
;
3095 asarg
= expr_parse_end
;
3098 case 'm': /* optional vector mask */
3101 INSERT_OPERAND (VMASK
, *ip
, 1);
3104 else if (*asarg
== ',' && asarg
++
3105 && reg_lookup (&asarg
, RCLASS_VECM
, ®no
)
3108 INSERT_OPERAND (VMASK
, *ip
, 0);
3113 case 'M': /* required vector mask */
3114 if (reg_lookup (&asarg
, RCLASS_VECM
, ®no
) && regno
== 0)
3116 INSERT_OPERAND (VMASK
, *ip
, 0);
3121 case 'T': /* vector macro temporary register */
3122 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
) || regno
== 0)
3124 /* Store it in the FUNCT6 field as we don't have anyplace
3125 else to store it. */
3126 INSERT_OPERAND (VFUNCT6
, *ip
, regno
);
3130 goto unknown_riscv_ip_operand
;
3132 break; /* end RVV */
3135 if (*asarg
++ == *oparg
)
3144 if (*asarg
++ == *oparg
)
3148 case '<': /* Shift amount, 0 - 31. */
3149 my_getExpression (imm_expr
, asarg
);
3150 check_absolute_expr (ip
, imm_expr
, false);
3151 if ((unsigned long) imm_expr
->X_add_number
> 31)
3152 as_bad (_("improper shift amount (%"PRIu64
")"),
3153 imm_expr
->X_add_number
);
3154 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
3155 imm_expr
->X_op
= O_absent
;
3156 asarg
= expr_parse_end
;
3159 case '>': /* Shift amount, 0 - (XLEN-1). */
3160 my_getExpression (imm_expr
, asarg
);
3161 check_absolute_expr (ip
, imm_expr
, false);
3162 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
3163 as_bad (_("improper shift amount (%"PRIu64
")"),
3164 imm_expr
->X_add_number
);
3165 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
3166 imm_expr
->X_op
= O_absent
;
3167 asarg
= expr_parse_end
;
3170 case 'Z': /* CSRRxI immediate. */
3171 my_getExpression (imm_expr
, asarg
);
3172 check_absolute_expr (ip
, imm_expr
, false);
3173 if ((unsigned long) imm_expr
->X_add_number
> 31)
3174 as_bad (_("improper CSRxI immediate (%"PRIu64
")"),
3175 imm_expr
->X_add_number
);
3176 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
3177 imm_expr
->X_op
= O_absent
;
3178 asarg
= expr_parse_end
;
3181 case 'E': /* Control register. */
3182 insn_with_csr
= true;
3183 explicit_priv_attr
= true;
3184 if (reg_lookup (&asarg
, RCLASS_CSR
, ®no
))
3185 INSERT_OPERAND (CSR
, *ip
, regno
);
3188 my_getExpression (imm_expr
, asarg
);
3189 check_absolute_expr (ip
, imm_expr
, true);
3190 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
3191 as_bad (_("improper CSR address (%"PRIu64
")"),
3192 imm_expr
->X_add_number
);
3193 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
3194 imm_expr
->X_op
= O_absent
;
3195 asarg
= expr_parse_end
;
3199 case 'm': /* Rounding mode. */
3200 if (arg_lookup (&asarg
, riscv_rm
,
3201 ARRAY_SIZE (riscv_rm
), ®no
))
3203 INSERT_OPERAND (RM
, *ip
, regno
);
3209 case 'Q': /* Fence predecessor/successor. */
3210 if (arg_lookup (&asarg
, riscv_pred_succ
,
3211 ARRAY_SIZE (riscv_pred_succ
), ®no
))
3214 INSERT_OPERAND (PRED
, *ip
, regno
);
3216 INSERT_OPERAND (SUCC
, *ip
, regno
);
3221 case 'd': /* Destination register. */
3222 case 's': /* Source register. */
3223 case 't': /* Target register. */
3225 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
3231 /* Now that we have assembled one operand, we use the args
3232 string to figure out where it goes in the instruction. */
3236 INSERT_OPERAND (RS1
, *ip
, regno
);
3239 INSERT_OPERAND (RD
, *ip
, regno
);
3242 INSERT_OPERAND (RS2
, *ip
, regno
);
3245 INSERT_OPERAND (RS3
, *ip
, regno
);
3252 case 'D': /* Floating point RD. */
3253 case 'S': /* Floating point RS1. */
3254 case 'T': /* Floating point RS2. */
3255 case 'U': /* Floating point RS1 and RS2. */
3256 case 'R': /* Floating point RS3. */
3257 if (reg_lookup (&asarg
,
3258 (riscv_subset_supports (&riscv_rps_as
, "zfinx")
3259 ? RCLASS_GPR
: RCLASS_FPR
), ®no
))
3267 INSERT_OPERAND (RD
, *ip
, regno
);
3270 INSERT_OPERAND (RS1
, *ip
, regno
);
3273 INSERT_OPERAND (RS1
, *ip
, regno
);
3276 INSERT_OPERAND (RS2
, *ip
, regno
);
3279 INSERT_OPERAND (RS3
, *ip
, regno
);
3287 my_getExpression (imm_expr
, asarg
);
3288 if (imm_expr
->X_op
!= O_big
3289 && imm_expr
->X_op
!= O_constant
)
3291 normalize_constant_expr (imm_expr
);
3292 asarg
= expr_parse_end
;
3296 my_getExpression (imm_expr
, asarg
);
3297 normalize_constant_expr (imm_expr
);
3298 /* The 'A' format specifier must be a symbol. */
3299 if (imm_expr
->X_op
!= O_symbol
)
3301 *imm_reloc
= BFD_RELOC_32
;
3302 asarg
= expr_parse_end
;
3306 my_getExpression (imm_expr
, asarg
);
3307 normalize_constant_expr (imm_expr
);
3308 /* The 'B' format specifier must be a symbol or a constant. */
3309 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
3311 if (imm_expr
->X_op
== O_symbol
)
3312 *imm_reloc
= BFD_RELOC_32
;
3313 asarg
= expr_parse_end
;
3316 case 'j': /* Sign-extended immediate. */
3317 p
= percent_op_itype
;
3318 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3320 case 'q': /* Store displacement. */
3321 p
= percent_op_stype
;
3322 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
3324 case 'o': /* Load displacement. */
3325 p
= percent_op_itype
;
3326 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3329 /* This is used for TLS, where the fourth operand is
3330 %tprel_add, to get a relocation applied to an add
3331 instruction, for relaxation to use. */
3332 p
= percent_op_rtype
;
3334 case '0': /* AMO displacement, which must be zero. */
3336 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3339 /* If this value won't fit into a 16 bit offset, then go
3340 find a macro that will generate the 32 bit offset
3342 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3344 normalize_constant_expr (imm_expr
);
3345 if (imm_expr
->X_op
!= O_constant
3346 || (*oparg
== '0' && imm_expr
->X_add_number
!= 0)
3348 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
3349 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
3352 asarg
= expr_parse_end
;
3355 case 'p': /* PC-relative offset. */
3357 *imm_reloc
= BFD_RELOC_12_PCREL
;
3358 my_getExpression (imm_expr
, asarg
);
3359 asarg
= expr_parse_end
;
3362 case 'u': /* Upper 20 bits. */
3363 p
= percent_op_utype
;
3364 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3366 if (imm_expr
->X_op
!= O_constant
)
3369 if (imm_expr
->X_add_number
< 0
3370 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
3371 as_bad (_("lui expression not in range 0..1048575"));
3373 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
3374 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
3376 asarg
= expr_parse_end
;
3379 case 'a': /* 20-bit PC-relative offset. */
3381 my_getExpression (imm_expr
, asarg
);
3382 asarg
= expr_parse_end
;
3383 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
3387 my_getExpression (imm_expr
, asarg
);
3388 asarg
= expr_parse_end
;
3389 if (strcmp (asarg
, "@plt") == 0)
3391 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
3398 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
)
3399 || imm_expr
->X_op
!= O_constant
3400 || imm_expr
->X_add_number
< 0
3401 || imm_expr
->X_add_number
>= 128
3402 || (imm_expr
->X_add_number
& 0x3) != 3)
3404 as_bad (_("bad value for opcode field, "
3405 "value must be 0...127 and "
3406 "lower 2 bits must be 0x3"));
3409 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
3410 imm_expr
->X_op
= O_absent
;
3411 asarg
= expr_parse_end
;
3415 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
)
3416 || imm_expr
->X_op
!= O_constant
3417 || imm_expr
->X_add_number
< 0
3418 || imm_expr
->X_add_number
>= 3)
3420 as_bad (_("bad value for opcode field, "
3421 "value must be 0...2"));
3424 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
3425 imm_expr
->X_op
= O_absent
;
3426 asarg
= expr_parse_end
;
3430 goto unknown_riscv_ip_operand
;
3438 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3439 || imm_expr
->X_op
!= O_constant
3440 || imm_expr
->X_add_number
< 0
3441 || imm_expr
->X_add_number
>= 128)
3443 as_bad (_("bad value for funct7 field, "
3444 "value must be 0...127"));
3447 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
3448 imm_expr
->X_op
= O_absent
;
3449 asarg
= expr_parse_end
;
3453 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3454 || imm_expr
->X_op
!= O_constant
3455 || imm_expr
->X_add_number
< 0
3456 || imm_expr
->X_add_number
>= 8)
3458 as_bad (_("bad value for funct3 field, "
3459 "value must be 0...7"));
3462 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
3463 imm_expr
->X_op
= O_absent
;
3464 asarg
= expr_parse_end
;
3468 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3469 || imm_expr
->X_op
!= O_constant
3470 || imm_expr
->X_add_number
< 0
3471 || imm_expr
->X_add_number
>= 4)
3473 as_bad (_("bad value for funct2 field, "
3474 "value must be 0...3"));
3477 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
3478 imm_expr
->X_op
= O_absent
;
3479 asarg
= expr_parse_end
;
3483 goto unknown_riscv_ip_operand
;
3487 case 'y': /* bs immediate */
3488 my_getExpression (imm_expr
, asarg
);
3489 check_absolute_expr (ip
, imm_expr
, FALSE
);
3490 if ((unsigned long)imm_expr
->X_add_number
> 3)
3491 as_bad(_("Improper bs immediate (%lu)"),
3492 (unsigned long)imm_expr
->X_add_number
);
3493 INSERT_OPERAND(BS
, *ip
, imm_expr
->X_add_number
);
3494 imm_expr
->X_op
= O_absent
;
3495 asarg
= expr_parse_end
;
3498 case 'Y': /* rnum immediate */
3499 my_getExpression (imm_expr
, asarg
);
3500 check_absolute_expr (ip
, imm_expr
, FALSE
);
3501 if ((unsigned long)imm_expr
->X_add_number
> 10)
3502 as_bad(_("Improper rnum immediate (%lu)"),
3503 (unsigned long)imm_expr
->X_add_number
);
3504 INSERT_OPERAND(RNUM
, *ip
, imm_expr
->X_add_number
);
3505 imm_expr
->X_op
= O_absent
;
3506 asarg
= expr_parse_end
;
3510 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3511 || imm_expr
->X_op
!= O_constant
3512 || imm_expr
->X_add_number
!= 0)
3514 asarg
= expr_parse_end
;
3515 imm_expr
->X_op
= O_absent
;
3518 case 'W': /* Various operands. */
3525 /* Prefetch offset for 'Zicbop' extension.
3526 pseudo S-type but lower 5-bits zero. */
3527 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3529 my_getExpression (imm_expr
, asarg
);
3530 check_absolute_expr (ip
, imm_expr
, false);
3531 if (((unsigned) (imm_expr
->X_add_number
) & 0x1fU
)
3532 || imm_expr
->X_add_number
>= RISCV_IMM_REACH
/ 2
3533 || imm_expr
->X_add_number
< -RISCV_IMM_REACH
/ 2)
3534 as_bad (_ ("improper prefetch offset (%ld)"),
3535 (long) imm_expr
->X_add_number
);
3536 ip
->insn_opcode
|= ENCODE_STYPE_IMM (
3537 (unsigned) (imm_expr
->X_add_number
) & ~0x1fU
);
3538 imm_expr
->X_op
= O_absent
;
3539 asarg
= expr_parse_end
;
3542 goto unknown_riscv_ip_operand
;
3549 /* FLI.[HSDQ] value field for 'Zfa' extension. */
3550 if (!arg_lookup (&asarg
, riscv_fli_symval
,
3551 ARRAY_SIZE (riscv_fli_symval
), ®no
))
3553 /* 0.0 is not a valid entry in riscv_fli_numval. */
3555 float f
= strtof (asarg
, &asarg
);
3556 if (errno
!= 0 || f
== 0.0
3557 || !flt_lookup (f
, riscv_fli_numval
,
3558 ARRAY_SIZE(riscv_fli_numval
),
3561 as_bad (_("bad fli constant operand, "
3562 "supported constants must be in "
3563 "decimal or hexadecimal floating-point "
3568 INSERT_OPERAND (RS1
, *ip
, regno
);
3571 goto unknown_riscv_ip_operand
;
3578 case 'h': /* Immediate field for c.lh/c.lhu/c.sh. */
3579 /* Handle cases, such as c.sh rs2', (rs1'). */
3580 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3582 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3583 || imm_expr
->X_op
!= O_constant
3584 || !VALID_ZCB_HALFWORD_UIMM ((valueT
) imm_expr
->X_add_number
))
3586 ip
->insn_opcode
|= ENCODE_ZCB_HALFWORD_UIMM (imm_expr
->X_add_number
);
3589 case 'b': /* Immediate field for c.lbu/c.sb. */
3590 /* Handle cases, such as c.lbu rd', (rs1'). */
3591 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3593 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3594 || imm_expr
->X_op
!= O_constant
3595 || !VALID_ZCB_BYTE_UIMM ((valueT
) imm_expr
->X_add_number
))
3597 ip
->insn_opcode
|= ENCODE_ZCB_BYTE_UIMM (imm_expr
->X_add_number
);
3600 case 'f': /* Operand for matching immediate 255. */
3601 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3602 || imm_expr
->X_op
!= O_constant
3603 || imm_expr
->X_add_number
!= 255)
3605 /* This operand is used for matching immediate 255, and
3606 we do not write anything to encoding by this operand. */
3607 asarg
= expr_parse_end
;
3608 imm_expr
->X_op
= O_absent
;
3612 goto unknown_riscv_ip_operand
;
3616 goto unknown_riscv_ip_operand
;
3620 case 'X': /* Integer immediate. */
3628 case 'l': /* Literal. */
3629 n
= strcspn (++oparg
, ",");
3630 if (strncmp (oparg
, asarg
, n
))
3631 as_bad (_("unexpected literal (%s)"), asarg
);
3635 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
3638 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
3642 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3644 goto unknown_riscv_ip_operand
;
3645 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3648 my_getExpression (imm_expr
, asarg
);
3649 check_absolute_expr (ip
, imm_expr
, false);
3652 if (!VALIDATE_U_IMM (imm_expr
->X_add_number
, n
))
3653 as_bad (_("improper immediate value (%"PRIu64
")"),
3654 imm_expr
->X_add_number
);
3658 if (!VALIDATE_S_IMM (imm_expr
->X_add_number
, n
))
3659 as_bad (_("improper immediate value (%"PRIi64
")"),
3660 imm_expr
->X_add_number
);
3662 INSERT_IMM (n
, s
, *ip
, imm_expr
->X_add_number
);
3663 imm_expr
->X_op
= O_absent
;
3664 asarg
= expr_parse_end
;
3667 goto unknown_riscv_ip_operand
;
3673 unknown_riscv_ip_operand
:
3674 as_fatal (_("internal: unknown argument type `%s'"),
3680 insn_with_csr
= false;
3684 /* Restore the character we might have clobbered above. */
3686 *(asargStart
- 1) = save_c
;
3688 probing_insn_operands
= false;
3693 /* Similar to riscv_ip, but assembles an instruction according to the
3694 hardcode values of .insn directive. */
3697 riscv_ip_hardcode (char *str
,
3698 struct riscv_cl_insn
*ip
,
3699 expressionS
*imm_expr
,
3702 struct riscv_opcode
*insn
;
3703 insn_t values
[2] = {0, 0};
3704 unsigned int num
= 0;
3706 input_line_pointer
= str
;
3709 expression (imm_expr
);
3710 switch (imm_expr
->X_op
)
3713 values
[num
++] = (insn_t
) imm_expr
->X_add_number
;
3716 /* Extract lower 32-bits of a big number.
3717 Assume that generic_bignum_to_int32 work on such number. */
3718 values
[num
++] = (insn_t
) generic_bignum_to_int32 ();
3721 /* The first value isn't constant, so it should be
3722 .insn <type> <operands>. We have been parsed it
3726 return _("values must be constant");
3729 while (*input_line_pointer
++ == ',' && num
< 2 && imm_expr
->X_op
!= O_big
);
3731 input_line_pointer
--;
3732 if (*input_line_pointer
!= '\0')
3733 return _("unrecognized values");
3735 insn
= XNEW (struct riscv_opcode
);
3736 insn
->match
= values
[num
- 1];
3737 create_insn (ip
, insn
);
3738 unsigned int bytes
= riscv_insn_length (insn
->match
);
3740 if (num
== 2 && values
[0] != bytes
)
3741 return _("value conflicts with instruction length");
3743 if (imm_expr
->X_op
== O_big
)
3745 unsigned int llen
= 0;
3746 for (LITTLENUM_TYPE lval
= generic_bignum
[imm_expr
->X_add_number
- 1];
3748 lval
>>= BITS_PER_CHAR
;
3749 unsigned int repr_bytes
3750 = (imm_expr
->X_add_number
- 1) * CHARS_PER_LITTLENUM
+ llen
;
3751 if (bytes
< repr_bytes
)
3752 return _("value conflicts with instruction length");
3753 for (num
= 0; num
< imm_expr
->X_add_number
- 1; ++num
)
3754 number_to_chars_littleendian (
3755 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3756 generic_bignum
[num
],
3757 CHARS_PER_LITTLENUM
);
3759 number_to_chars_littleendian (
3760 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3761 generic_bignum
[num
],
3763 memset(ip
->insn_long_opcode
+ repr_bytes
, 0, bytes
- repr_bytes
);
3767 if (bytes
< sizeof(values
[0]) && values
[num
- 1] >> (8 * bytes
) != 0)
3768 return _("value conflicts with instruction length");
3774 md_assemble (char *str
)
3776 struct riscv_cl_insn insn
;
3777 expressionS imm_expr
;
3778 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3780 /* The architecture and privileged elf attributes should be set
3781 before assembling. */
3782 if (!start_assemble
)
3784 start_assemble
= true;
3786 riscv_set_abi_by_arch ();
3787 if (!riscv_set_default_priv_spec (NULL
))
3791 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
3793 const struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
3794 &imm_reloc
, op_hash
);
3798 if (error
.missing_ext
)
3799 as_bad ("%s `%s', extension `%s' required", error
.msg
,
3800 error
.statement
, error
.missing_ext
);
3802 as_bad ("%s `%s'", error
.msg
, error
.statement
);
3806 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3807 macro (&insn
, &imm_expr
, &imm_reloc
);
3809 append_insn (&insn
, &imm_expr
, imm_reloc
);
3813 md_atof (int type
, char *litP
, int *sizeP
)
3815 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3819 md_number_to_chars (char *buf
, valueT val
, int n
)
3821 if (target_big_endian
)
3822 number_to_chars_bigendian (buf
, val
, n
);
3824 number_to_chars_littleendian (buf
, val
, n
);
3827 const char *md_shortopts
= "O::g::G:";
3831 OPTION_MARCH
= OPTION_MD_BASE
,
3838 OPTION_NO_ARCH_ATTR
,
3840 OPTION_NO_CSR_CHECK
,
3844 OPTION_LITTLE_ENDIAN
,
3848 struct option md_longopts
[] =
3850 {"march", required_argument
, NULL
, OPTION_MARCH
},
3851 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
3852 {"fpic", no_argument
, NULL
, OPTION_PIC
},
3853 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
3854 {"mabi", required_argument
, NULL
, OPTION_MABI
},
3855 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
3856 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
3857 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
3858 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
3859 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
3860 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
3861 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
3862 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
3863 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
3864 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
3866 {NULL
, no_argument
, NULL
, 0}
3868 size_t md_longopts_size
= sizeof (md_longopts
);
3871 md_parse_option (int c
, const char *arg
)
3876 default_arch_with_ext
= arg
;
3880 riscv_opts
.pic
= false;
3884 riscv_opts
.pic
= true;
3888 if (strcmp (arg
, "ilp32") == 0)
3889 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
3890 else if (strcmp (arg
, "ilp32e") == 0)
3891 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
3892 else if (strcmp (arg
, "ilp32f") == 0)
3893 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
3894 else if (strcmp (arg
, "ilp32d") == 0)
3895 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
3896 else if (strcmp (arg
, "ilp32q") == 0)
3897 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
3898 else if (strcmp (arg
, "lp64") == 0)
3899 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
3900 else if (strcmp (arg
, "lp64f") == 0)
3901 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
3902 else if (strcmp (arg
, "lp64d") == 0)
3903 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
3904 else if (strcmp (arg
, "lp64q") == 0)
3905 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
3908 explicit_mabi
= true;
3912 riscv_opts
.relax
= true;
3915 case OPTION_NO_RELAX
:
3916 riscv_opts
.relax
= false;
3919 case OPTION_ARCH_ATTR
:
3920 riscv_opts
.arch_attr
= true;
3923 case OPTION_NO_ARCH_ATTR
:
3924 riscv_opts
.arch_attr
= false;
3927 case OPTION_CSR_CHECK
:
3928 riscv_opts
.csr_check
= true;
3931 case OPTION_NO_CSR_CHECK
:
3932 riscv_opts
.csr_check
= false;
3935 case OPTION_MISA_SPEC
:
3936 return riscv_set_default_isa_spec (arg
);
3938 case OPTION_MPRIV_SPEC
:
3939 return riscv_set_default_priv_spec (arg
);
3941 case OPTION_BIG_ENDIAN
:
3942 target_big_endian
= 1;
3945 case OPTION_LITTLE_ENDIAN
:
3946 target_big_endian
= 0;
3957 riscv_after_parse_args (void)
3959 /* The --with-arch is optional for now, so we still need to set the xlen
3960 according to the default_arch, which is set by the --target. */
3963 if (strcmp (default_arch
, "riscv32") == 0)
3965 else if (strcmp (default_arch
, "riscv64") == 0)
3968 as_bad ("unknown default architecture `%s'", default_arch
);
3971 /* Set default specs. */
3972 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
3973 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
3974 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
3975 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
3977 riscv_set_arch (default_arch_with_ext
);
3979 /* If the CIE to be produced has not been overridden on the command line,
3980 then produce version 3 by default. This allows us to use the full
3981 range of registers in a .cfi_return_column directive. */
3982 if (flag_dwarf_cie_version
== -1)
3983 flag_dwarf_cie_version
= 3;
3986 bool riscv_parse_name (const char *name
, struct expressionS
*ep
,
3987 enum expr_mode mode
)
3992 if (!probing_insn_operands
)
3995 gas_assert (mode
== expr_normal
);
3997 regno
= reg_lookup_internal (name
, RCLASS_GPR
);
3998 if (regno
== (unsigned int)-1)
4001 if (symbol_find (name
) != NULL
)
4004 /* Create a symbol without adding it to the symbol table yet.
4005 Insertion will happen only once we commit to using the insn
4006 we're probing operands for. */
4007 for (sym
= deferred_sym_rootP
; sym
; sym
= symbol_next (sym
))
4008 if (strcmp (name
, S_GET_NAME (sym
)) == 0)
4012 for (sym
= orphan_sym_rootP
; sym
; sym
= symbol_next (sym
))
4013 if (strcmp (name
, S_GET_NAME (sym
)) == 0)
4015 symbol_remove (sym
, &orphan_sym_rootP
, &orphan_sym_lastP
);
4019 sym
= symbol_create (name
, undefined_section
,
4020 &zero_address_frag
, 0);
4022 symbol_append (sym
, deferred_sym_lastP
, &deferred_sym_rootP
,
4023 &deferred_sym_lastP
);
4026 ep
->X_op
= O_symbol
;
4027 ep
->X_add_symbol
= sym
;
4028 ep
->X_add_number
= 0;
4034 md_pcrel_from (fixS
*fixP
)
4036 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4039 /* Apply a fixup to the object file. */
4042 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4044 unsigned int subtype
;
4045 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
4046 bool relaxable
= false;
4050 /* Remember value for tc_gen_reloc. */
4051 fixP
->fx_addnumber
= *valP
;
4053 switch (fixP
->fx_r_type
)
4055 case BFD_RELOC_RISCV_HI20
:
4056 case BFD_RELOC_RISCV_LO12_I
:
4057 case BFD_RELOC_RISCV_LO12_S
:
4058 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
4059 | bfd_getl32 (buf
), buf
);
4060 if (fixP
->fx_addsy
== NULL
)
4061 fixP
->fx_done
= true;
4065 case BFD_RELOC_RISCV_GOT_HI20
:
4066 case BFD_RELOC_RISCV_ADD8
:
4067 case BFD_RELOC_RISCV_ADD16
:
4068 case BFD_RELOC_RISCV_ADD32
:
4069 case BFD_RELOC_RISCV_ADD64
:
4070 case BFD_RELOC_RISCV_SUB6
:
4071 case BFD_RELOC_RISCV_SUB8
:
4072 case BFD_RELOC_RISCV_SUB16
:
4073 case BFD_RELOC_RISCV_SUB32
:
4074 case BFD_RELOC_RISCV_SUB64
:
4075 case BFD_RELOC_RISCV_RELAX
:
4076 /* cvt_frag_to_fill () has called output_leb128 (). */
4077 case BFD_RELOC_RISCV_SET_ULEB128
:
4078 case BFD_RELOC_RISCV_SUB_ULEB128
:
4081 case BFD_RELOC_RISCV_TPREL_HI20
:
4082 case BFD_RELOC_RISCV_TPREL_LO12_I
:
4083 case BFD_RELOC_RISCV_TPREL_LO12_S
:
4084 case BFD_RELOC_RISCV_TPREL_ADD
:
4088 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
4089 case BFD_RELOC_RISCV_TLS_GD_HI20
:
4090 case BFD_RELOC_RISCV_TLS_DTPREL32
:
4091 case BFD_RELOC_RISCV_TLS_DTPREL64
:
4092 if (fixP
->fx_addsy
!= NULL
)
4093 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4096 _("TLS relocation against a constant"));
4100 /* Use pc-relative relocation for FDE initial location.
4101 The symbol address in .eh_frame may be adjusted in
4102 _bfd_elf_discard_section_eh_frame, and the content of
4103 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
4104 Therefore, we cannot insert a relocation whose addend symbol is
4105 in .eh_frame. Othrewise, the value may be adjusted twice. */
4106 if (fixP
->fx_addsy
&& fixP
->fx_subsy
4107 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
4108 && strcmp (sub_segment
->name
, ".eh_frame") == 0
4109 && S_GET_VALUE (fixP
->fx_subsy
)
4110 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
4112 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
4113 fixP
->fx_subsy
= NULL
;
4120 case BFD_RELOC_RISCV_CFA
:
4121 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
4123 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
4124 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
4125 fixP
->fx_next
->fx_subsy
= NULL
;
4126 fixP
->fx_next
->fx_offset
= 0;
4127 fixP
->fx_subsy
= NULL
;
4129 switch (fixP
->fx_r_type
)
4132 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
4133 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
4137 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
4138 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
4142 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
4143 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
4147 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
4148 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
4151 case BFD_RELOC_RISCV_CFA
:
4152 /* Load the byte to get the subtype. */
4153 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
4154 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
4157 case DW_CFA_advance_loc1
:
4158 fixP
->fx_where
= loc
+ 1;
4159 fixP
->fx_next
->fx_where
= loc
+ 1;
4160 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
4161 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
4164 case DW_CFA_advance_loc2
:
4166 fixP
->fx_next
->fx_size
= 2;
4167 fixP
->fx_where
= loc
+ 1;
4168 fixP
->fx_next
->fx_where
= loc
+ 1;
4169 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
4170 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
4173 case DW_CFA_advance_loc4
:
4175 fixP
->fx_next
->fx_size
= 4;
4176 fixP
->fx_where
= loc
;
4177 fixP
->fx_next
->fx_where
= loc
;
4178 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
4179 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
4183 if (subtype
< 0x80 && (subtype
& 0x40))
4185 /* DW_CFA_advance_loc */
4186 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
4187 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
4188 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
4189 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
4192 as_fatal (_("internal: bad CFA value #%d"), subtype
);
4198 /* This case is unreachable. */
4205 /* If we are deleting this reloc entry, we must fill in the
4206 value now. This can happen if we have a .word which is not
4207 resolved when it appears but is later defined. */
4208 if (fixP
->fx_addsy
== NULL
)
4210 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
4211 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
4216 case BFD_RELOC_RISCV_JMP
:
4219 /* Fill in a tentative value to improve objdump readability. */
4220 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4221 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4222 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
4226 case BFD_RELOC_12_PCREL
:
4229 /* Fill in a tentative value to improve objdump readability. */
4230 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4231 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4232 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
4236 case BFD_RELOC_RISCV_RVC_BRANCH
:
4239 /* Fill in a tentative value to improve objdump readability. */
4240 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4241 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4242 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
4246 case BFD_RELOC_RISCV_RVC_JUMP
:
4249 /* Fill in a tentative value to improve objdump readability. */
4250 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4251 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4252 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
4256 case BFD_RELOC_RISCV_CALL
:
4257 case BFD_RELOC_RISCV_CALL_PLT
:
4261 case BFD_RELOC_RISCV_PCREL_HI20
:
4262 case BFD_RELOC_RISCV_PCREL_LO12_S
:
4263 case BFD_RELOC_RISCV_PCREL_LO12_I
:
4264 relaxable
= riscv_opts
.relax
;
4267 case BFD_RELOC_RISCV_ALIGN
:
4271 /* We ignore generic BFD relocations we don't know about. */
4272 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
4273 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
4276 if (fixP
->fx_subsy
!= NULL
)
4277 as_bad_subtract (fixP
);
4279 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
4280 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
4282 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
4283 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
4284 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
4285 fixP
->fx_next
->fx_size
= 0;
4289 /* Because the value of .cfi_remember_state may changed after relaxation,
4290 we insert a fix to relocate it again in link-time. */
4293 riscv_pre_output_hook (void)
4295 const frchainS
*frch
;
4298 /* Save the current segment info. */
4300 subsegT subseg
= now_subseg
;
4302 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
4303 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
4307 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
4309 if (frag
->fr_type
== rs_cfa
)
4312 expressionS
*symval
;
4314 symval
= symbol_get_value_expression (frag
->fr_symbol
);
4315 exp
.X_op
= O_subtract
;
4316 exp
.X_add_symbol
= symval
->X_add_symbol
;
4317 exp
.X_add_number
= 0;
4318 exp
.X_op_symbol
= symval
->X_op_symbol
;
4320 /* We must set the segment before creating a frag after all
4321 frag chains have been chained together. */
4322 subseg_set (s
, frch
->frch_subseg
);
4324 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
4325 BFD_RELOC_RISCV_CFA
);
4330 /* Restore the original segment info. */
4331 subseg_set (seg
, subseg
);
4334 /* Handle the .option pseudo-op. */
4337 s_riscv_option (int x ATTRIBUTE_UNUSED
)
4339 char *name
= input_line_pointer
, ch
;
4341 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4342 ++input_line_pointer
;
4343 ch
= *input_line_pointer
;
4344 *input_line_pointer
= '\0';
4346 if (strcmp (name
, "rvc") == 0)
4348 riscv_update_subset (&riscv_rps_as
, "+c");
4349 riscv_reset_subsets_list_arch_str ();
4350 riscv_set_rvc (true);
4352 else if (strcmp (name
, "norvc") == 0)
4354 riscv_update_subset (&riscv_rps_as
, "-c");
4355 riscv_reset_subsets_list_arch_str ();
4356 riscv_set_rvc (false);
4358 else if (strcmp (name
, "pic") == 0)
4359 riscv_opts
.pic
= true;
4360 else if (strcmp (name
, "nopic") == 0)
4361 riscv_opts
.pic
= false;
4362 else if (strcmp (name
, "relax") == 0)
4363 riscv_opts
.relax
= true;
4364 else if (strcmp (name
, "norelax") == 0)
4365 riscv_opts
.relax
= false;
4366 else if (strcmp (name
, "csr-check") == 0)
4367 riscv_opts
.csr_check
= true;
4368 else if (strcmp (name
, "no-csr-check") == 0)
4369 riscv_opts
.csr_check
= false;
4370 else if (strncmp (name
, "arch,", 5) == 0)
4373 if (ISSPACE (*name
) && *name
!= '\0')
4375 riscv_update_subset (&riscv_rps_as
, name
);
4376 riscv_reset_subsets_list_arch_str ();
4378 riscv_set_rvc (false);
4379 if (riscv_subset_supports (&riscv_rps_as
, "c"))
4380 riscv_set_rvc (true);
4382 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
4385 else if (strcmp (name
, "push") == 0)
4387 struct riscv_option_stack
*s
;
4389 s
= XNEW (struct riscv_option_stack
);
4390 s
->next
= riscv_opts_stack
;
4391 s
->options
= riscv_opts
;
4392 s
->subset_list
= riscv_rps_as
.subset_list
;
4393 riscv_opts_stack
= s
;
4394 riscv_rps_as
.subset_list
= riscv_copy_subset_list (s
->subset_list
);
4396 else if (strcmp (name
, "pop") == 0)
4398 struct riscv_option_stack
*s
;
4400 s
= riscv_opts_stack
;
4402 as_bad (_(".option pop with no .option push"));
4405 riscv_subset_list_t
*release_subsets
= riscv_rps_as
.subset_list
;
4406 riscv_opts_stack
= s
->next
;
4407 riscv_opts
= s
->options
;
4408 riscv_rps_as
.subset_list
= s
->subset_list
;
4409 riscv_release_subset_list (release_subsets
);
4415 as_warn (_("unrecognized .option directive: %s"), name
);
4417 *input_line_pointer
= ch
;
4418 demand_empty_rest_of_line ();
4421 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
4422 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
4423 use in DWARF debug information. */
4426 s_dtprel (int bytes
)
4433 if (ex
.X_op
!= O_symbol
)
4435 as_bad (_("unsupported use of %s"), (bytes
== 8
4438 ignore_rest_of_line ();
4441 p
= frag_more (bytes
);
4442 md_number_to_chars (p
, 0, bytes
);
4443 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
4445 ? BFD_RELOC_RISCV_TLS_DTPREL64
4446 : BFD_RELOC_RISCV_TLS_DTPREL32
));
4448 demand_empty_rest_of_line ();
4451 /* Handle the .bss pseudo-op. */
4454 s_bss (int ignore ATTRIBUTE_UNUSED
)
4456 subseg_set (bss_section
, 0);
4457 demand_empty_rest_of_line ();
4461 riscv_make_nops (char *buf
, bfd_vma bytes
)
4465 /* RISC-V instructions cannot begin or end on odd addresses, so this case
4466 means we are not within a valid instruction sequence. It is thus safe
4467 to use a zero byte, even though that is not a valid instruction. */
4471 /* Use at most one 2-byte NOP. */
4472 if ((bytes
- i
) % 4 == 2)
4474 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
4478 /* Fill the remainder with 4-byte NOPs. */
4479 for ( ; i
< bytes
; i
+= 4)
4480 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
4483 /* Called from md_do_align. Used to create an alignment frag in a
4484 code section by emitting a worst-case NOP sequence that the linker
4485 will later relax to the correct number of NOPs. We can't compute
4486 the correct alignment now because of other linker relaxations. */
4489 riscv_frag_align_code (int n
)
4491 bfd_vma bytes
= (bfd_vma
) 1 << n
;
4492 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
4493 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
4497 /* If we are moving to a smaller alignment than the instruction size, then no
4498 alignment is required. */
4499 if (bytes
<= insn_alignment
)
4502 /* When not relaxing, riscv_handle_align handles code alignment. */
4503 if (!riscv_opts
.relax
)
4506 /* Maybe we should use frag_var to create a new rs_align_code fragment,
4507 rather than just use frag_more to handle an alignment here? So that we
4508 don't need to call riscv_mapping_state again later, and then only need
4509 to check frag->fr_type to see if it is frag_align_code. */
4510 nops
= frag_more (worst_case_bytes
);
4512 ex
.X_op
= O_constant
;
4513 ex
.X_add_number
= worst_case_bytes
;
4515 riscv_make_nops (nops
, worst_case_bytes
);
4517 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
4518 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
4520 riscv_mapping_state (MAP_INSN
, worst_case_bytes
, true/* fr_align_code */);
4522 /* We need to start a new frag after the alignment which may be removed by
4523 the linker, to prevent the assembler from computing static offsets.
4524 This is necessary to get correct EH info. */
4525 frag_wane (frag_now
);
4531 /* Implement HANDLE_ALIGN. */
4534 riscv_handle_align (fragS
*fragP
)
4536 switch (fragP
->fr_type
)
4539 /* When relaxing, riscv_frag_align_code handles code alignment. */
4540 if (!riscv_opts
.relax
)
4542 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
4543 - fragP
->fr_address
- fragP
->fr_fix
);
4544 /* We have 4 byte uncompressed nops. */
4545 bfd_signed_vma size
= 4;
4546 bfd_signed_vma excess
= bytes
% size
;
4547 bfd_boolean odd_padding
= (excess
% 2 == 1);
4548 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
4553 /* Insert zeros or compressed nops to get 4 byte alignment. */
4557 riscv_add_odd_padding_symbol (fragP
);
4558 riscv_make_nops (p
, excess
);
4559 fragP
->fr_fix
+= excess
;
4563 /* The frag will be changed to `rs_fill` later. The function
4564 `write_contents` will try to fill the remaining spaces
4565 according to the patterns we give. In this case, we give
4566 a 4 byte uncompressed nop as the pattern, and set the size
4567 of the pattern into `fr_var`. The nop will be output to the
4568 file `fr_offset` times. However, `fr_offset` could be zero
4569 if we don't need to pad the boundary finally. */
4570 riscv_make_nops (p
, size
);
4571 fragP
->fr_var
= size
;
4580 /* This usually called from frag_var. */
4583 riscv_init_frag (fragS
* fragP
, int max_chars
)
4585 /* Do not add mapping symbol to debug sections. */
4586 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
4589 switch (fragP
->fr_type
)
4594 riscv_mapping_state (MAP_DATA
, max_chars
, false/* fr_align_code */);
4597 riscv_mapping_state (MAP_INSN
, max_chars
, true/* fr_align_code */);
4605 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
4607 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
4610 /* Translate internal representation of relocation info to BFD target
4614 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
4616 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4618 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4619 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4620 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4621 reloc
->addend
= fixp
->fx_addnumber
;
4623 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4624 if (reloc
->howto
== NULL
)
4626 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
4627 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
4629 /* We don't have R_RISCV_8/16, but for this special case,
4630 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
4634 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4635 _("cannot represent %s relocation in object file"),
4636 bfd_get_reloc_code_name (fixp
->fx_r_type
));
4644 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
4646 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
4648 offsetT old_var
= fragp
->fr_var
;
4649 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
4650 return fragp
->fr_var
- old_var
;
4656 /* Expand far branches to multi-instruction sequences. */
4659 md_convert_frag_branch (fragS
*fragp
)
4667 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
4669 exp
.X_op
= O_symbol
;
4670 exp
.X_add_symbol
= fragp
->fr_symbol
;
4671 exp
.X_add_number
= fragp
->fr_offset
;
4673 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
4675 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
4677 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4681 /* Expand the RVC branch into a RISC-V one. */
4682 insn
= bfd_getl16 (buf
);
4683 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
4684 if ((insn
& MASK_C_J
) == MATCH_C_J
)
4686 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
4687 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
4688 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
4689 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
4690 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
4691 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
4694 bfd_putl32 (insn
, buf
);
4698 /* Invert the branch condition. Branch over the jump. */
4699 insn
= bfd_getl16 (buf
);
4700 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
4701 insn
|= ENCODE_CBTYPE_IMM (6);
4702 bfd_putl16 (insn
, buf
);
4707 /* Just keep the RVC branch. */
4708 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4709 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
4710 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4711 2, &exp
, false, reloc
);
4720 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4723 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
4725 /* Invert the branch condition. Branch over the jump. */
4726 insn
= bfd_getl32 (buf
);
4727 insn
^= MATCH_BEQ
^ MATCH_BNE
;
4728 insn
|= ENCODE_BTYPE_IMM (8);
4729 bfd_putl32 (insn
, buf
);
4733 /* Jump to the target. */
4734 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4735 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
4736 bfd_putl32 (MATCH_JAL
, buf
);
4741 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4742 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
4743 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4744 4, &exp
, false, reloc
);
4753 fixp
->fx_file
= fragp
->fr_file
;
4754 fixp
->fx_line
= fragp
->fr_line
;
4756 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
4757 + fragp
->fr_fix
+ fragp
->fr_var
);
4759 fragp
->fr_fix
+= fragp
->fr_var
;
4762 /* Relax a machine dependent frag. This returns the amount by which
4763 the current size of the frag should change. */
4766 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
4769 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
4770 md_convert_frag_branch (fragp
);
4774 md_show_usage (FILE *stream
)
4776 fprintf (stream
, _("\
4778 -fpic or -fPIC generate position-independent code\n\
4779 -fno-pic don't generate position-independent code (default)\n\
4780 -march=ISA set the RISC-V architecture\n\
4781 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
4782 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
4783 -mabi=ABI set the RISC-V ABI\n\
4784 -mrelax enable relax (default)\n\
4785 -mno-relax disable relax\n\
4786 -march-attr generate RISC-V arch attribute\n\
4787 -mno-arch-attr don't generate RISC-V arch attribute\n\
4788 -mcsr-check enable the csr ISA and privilege spec version checks\n\
4789 -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\
4790 -mbig-endian assemble for big-endian\n\
4791 -mlittle-endian assemble for little-endian\n\
4795 /* Standard calling conventions leave the CFA at SP on entry. */
4798 riscv_cfi_frame_initial_instructions (void)
4800 cfi_add_CFA_def_cfa_register (X_SP
);
4804 tc_riscv_regname_to_dw2regnum (char *regname
)
4808 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
4811 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
4814 if ((reg
= reg_lookup_internal (regname
, RCLASS_VECR
)) >= 0)
4817 /* CSRs are numbered 4096 -> 8191. */
4818 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
4821 as_bad (_("unknown register `%s'"), regname
);
4826 riscv_elf_final_processing (void)
4828 riscv_set_abi_by_arch ();
4829 riscv_release_subset_list (riscv_rps_as
.subset_list
);
4830 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4833 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
4834 since these directives break relaxation when used with symbol deltas. */
4837 s_riscv_leb128 (int sign
)
4840 char *save_in
= input_line_pointer
;
4843 if (sign
&& exp
.X_op
!= O_constant
)
4844 as_bad (_("non-constant .sleb128 is not supported"));
4845 else if (!sign
&& exp
.X_op
!= O_constant
&& exp
.X_op
!= O_subtract
)
4846 as_bad (_(".uleb128 only supports constant or subtract expressions"));
4848 demand_empty_rest_of_line ();
4850 input_line_pointer
= save_in
;
4851 return s_leb128 (sign
);
4854 /* Parse the .insn directive. There are three formats,
4855 Format 1: .insn <type> <operand1>, <operand2>, ...
4856 Format 2: .insn <length>, <value>
4857 Format 3: .insn <value>. */
4860 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
4862 char *str
= input_line_pointer
;
4863 struct riscv_cl_insn insn
;
4864 expressionS imm_expr
;
4865 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
4868 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4869 ++input_line_pointer
;
4871 save_c
= *input_line_pointer
;
4872 *input_line_pointer
= '\0';
4874 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
4876 struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
4877 &imm_reloc
, insn_type_hash
);
4880 char *save_in
= input_line_pointer
;
4881 error
.msg
= riscv_ip_hardcode (str
, &insn
, &imm_expr
, error
.msg
);
4882 input_line_pointer
= save_in
;
4887 if (error
.missing_ext
)
4888 as_bad ("%s `%s', extension `%s' required", error
.msg
, error
.statement
,
4891 as_bad ("%s `%s'", error
.msg
, error
.statement
);
4895 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
4896 append_insn (&insn
, &imm_expr
, imm_reloc
);
4899 *input_line_pointer
= save_c
;
4900 demand_empty_rest_of_line ();
4903 /* Update architecture and privileged elf attributes. If we don't set
4904 them, then try to output the default ones. */
4907 riscv_write_out_attrs (void)
4909 const char *arch_str
, *priv_str
, *p
;
4910 /* versions[0]: major version.
4911 versions[1]: minor version.
4912 versions[2]: revision version. */
4913 unsigned versions
[3] = {0}, number
= 0;
4916 /* Re-write architecture elf attribute. */
4917 arch_str
= riscv_rps_as
.subset_list
->arch_str
;
4918 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
4920 /* For the file without any instruction, we don't set the default_priv_spec
4921 according to the privileged elf attributes since the md_assemble isn't
4924 && !riscv_set_default_priv_spec (NULL
))
4927 /* If we already have set privileged elf attributes, then no need to do
4928 anything. Otherwise, don't generate or update them when no CSR and
4929 privileged instructions are used. */
4930 if (!explicit_priv_attr
)
4933 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
4935 for (i
= 0; *p
; ++p
)
4937 if (*p
== '.' && i
< 3)
4939 versions
[i
++] = number
;
4942 else if (ISDIGIT (*p
))
4943 number
= (number
* 10) + (*p
- '0');
4946 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
4950 versions
[i
] = number
;
4952 /* Re-write privileged elf attributes. */
4953 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
4954 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
4955 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
4958 /* Add the default contents for the .riscv.attributes section. */
4961 riscv_set_public_attributes (void)
4963 if (riscv_opts
.arch_attr
|| explicit_attr
)
4964 riscv_write_out_attrs ();
4967 /* Scan uleb128 subtraction expressions and insert fixups for them.
4968 e.g., .uleb128 .L1 - .L0
4969 Because relaxation may change the value of the subtraction, we
4970 must resolve them at link-time. */
4973 riscv_insert_uleb128_fixes (bfd
*abfd ATTRIBUTE_UNUSED
,
4974 asection
*sec
, void *xxx ATTRIBUTE_UNUSED
)
4976 segment_info_type
*seginfo
= seg_info (sec
);
4979 subseg_set (sec
, 0);
4981 for (fragP
= seginfo
->frchainP
->frch_root
;
4982 fragP
; fragP
= fragP
->fr_next
)
4984 expressionS
*exp
, *exp_dup
;
4986 if (fragP
->fr_type
!= rs_leb128
|| fragP
->fr_symbol
== NULL
)
4989 exp
= symbol_get_value_expression (fragP
->fr_symbol
);
4991 if (exp
->X_op
!= O_subtract
)
4994 /* Only unsigned leb128 can be handled. */
4995 gas_assert (fragP
->fr_subtype
== 0);
4996 exp_dup
= xmemdup (exp
, sizeof (*exp
), sizeof (*exp
));
4997 exp_dup
->X_op
= O_symbol
;
4998 exp_dup
->X_op_symbol
= NULL
;
5000 /* Insert relocations to resolve the subtraction at link-time.
5001 Emit the SET relocation first in riscv. */
5002 exp_dup
->X_add_symbol
= exp
->X_add_symbol
;
5003 fix_new_exp (fragP
, fragP
->fr_fix
, 0,
5004 exp_dup
, 0, BFD_RELOC_RISCV_SET_ULEB128
);
5005 exp_dup
->X_add_symbol
= exp
->X_op_symbol
;
5006 fix_new_exp (fragP
, fragP
->fr_fix
, 0,
5007 exp_dup
, 0, BFD_RELOC_RISCV_SUB_ULEB128
);
5011 /* Called after all assembly has been done. */
5014 riscv_md_finish (void)
5016 riscv_set_public_attributes ();
5017 if (riscv_opts
.relax
)
5018 bfd_map_over_sections (stdoutput
, riscv_insert_uleb128_fixes
, NULL
);
5021 /* Adjust the symbol table. */
5024 riscv_adjust_symtab (void)
5026 bfd_map_over_sections (stdoutput
, riscv_check_mapping_symbols
, (char *) 0);
5027 elf_adjust_symtab ();
5030 /* Given a symbolic attribute NAME, return the proper integer value.
5031 Returns -1 if the attribute is not known. */
5034 riscv_convert_symbolic_attribute (const char *name
)
5043 /* When you modify this table you should
5044 also modify the list in doc/c-riscv.texi. */
5045 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
5049 T(priv_spec_revision
),
5050 T(unaligned_access
),
5059 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5060 if (strcmp (name
, attribute_table
[i
].name
) == 0)
5061 return attribute_table
[i
].tag
;
5066 /* Parse a .attribute directive. */
5069 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
5071 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
5073 obj_attribute
*attr
;
5075 explicit_attr
= true;
5078 case Tag_RISCV_arch
:
5080 attr
= elf_known_obj_attributes_proc (stdoutput
);
5081 if (!start_assemble
)
5082 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
5084 as_fatal (_("architecture elf attributes must set before "
5085 "any instructions"));
5087 if (old_xlen
!= xlen
)
5089 /* We must re-init bfd again if xlen is changed. */
5090 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
5091 bfd_find_target (riscv_target_format (), stdoutput
);
5093 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
5094 as_warn (_("could not set architecture and machine"));
5098 case Tag_RISCV_priv_spec
:
5099 case Tag_RISCV_priv_spec_minor
:
5100 case Tag_RISCV_priv_spec_revision
:
5102 as_fatal (_("privileged elf attributes must set before "
5103 "any instructions"));
5111 /* Mark symbol that it follows a variant CC convention. */
5114 s_variant_cc (int ignored ATTRIBUTE_UNUSED
)
5120 elf_symbol_type
*elfsym
;
5122 c
= get_symbol_name (&name
);
5124 as_bad (_("missing symbol name for .variant_cc directive"));
5125 sym
= symbol_find_or_make (name
);
5126 restore_line_pointer (c
);
5127 demand_empty_rest_of_line ();
5129 bfdsym
= symbol_get_bfdsym (sym
);
5130 elfsym
= elf_symbol_from (bfdsym
);
5131 gas_assert (elfsym
);
5132 elfsym
->internal_elf_sym
.st_other
|= STO_RISCV_VARIANT_CC
;
5135 /* Same as elf_copy_symbol_attributes, but without copying st_other.
5136 This is needed so RISC-V specific st_other values can be independently
5137 specified for an IFUNC resolver (that is called by the dynamic linker)
5138 and the symbol it resolves (aliased to the resolver). In particular,
5139 if a function symbol has special st_other value set via directives,
5140 then attaching an IFUNC resolver to that symbol should not override
5141 the st_other setting. Requiring the directive on the IFUNC resolver
5142 symbol would be unexpected and problematic in C code, where the two
5143 symbols appear as two independent function declarations. */
5146 riscv_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5148 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
5149 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
5150 /* If size is unset, copy size from src. Because we don't track whether
5151 .size has been used, we can't differentiate .size dest, 0 from the case
5152 where dest's size is unset. */
5153 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
5157 destelf
->size
= XNEW (expressionS
);
5158 *destelf
->size
= *srcelf
->size
;
5160 S_SET_SIZE (dest
, S_GET_SIZE (src
));
5164 /* RISC-V pseudo-ops table. */
5165 static const pseudo_typeS riscv_pseudo_table
[] =
5167 {"option", s_riscv_option
, 0},
5171 {"dtprelword", s_dtprel
, 4},
5172 {"dtpreldword", s_dtprel
, 8},
5174 {"uleb128", s_riscv_leb128
, 0},
5175 {"sleb128", s_riscv_leb128
, 1},
5176 {"insn", s_riscv_insn
, 0},
5177 {"attribute", s_riscv_attribute
, 0},
5178 {"variant_cc", s_variant_cc
, 0},
5179 {"float16", float_cons
, 'h'},
5185 riscv_pop_insert (void)
5187 extern void pop_insert (const pseudo_typeS
*);
5189 pop_insert (riscv_pseudo_table
);