1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 static const char default_arch
[] = DEFAULT_ARCH
;
68 static unsigned xlen
= 0; /* width of an x-register */
69 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
70 static bfd_boolean rve_abi
= FALSE
;
72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
75 static unsigned elf_flags
= 0;
77 /* This is the set of options which the .option pseudo-op may modify. */
79 struct riscv_set_options
81 int pic
; /* Generate position-independent code. */
82 int rvc
; /* Generate RVC code. */
83 int rve
; /* Generate RVE code. */
84 int relax
; /* Emit relocs the linker is allowed to relax. */
85 int arch_attr
; /* Emit arch attribute. */
88 static struct riscv_set_options riscv_opts
=
94 DEFAULT_RISCV_ATTR
, /* arch_attr */
98 riscv_set_rvc (bfd_boolean rvc_value
)
101 elf_flags
|= EF_RISCV_RVC
;
103 riscv_opts
.rvc
= rvc_value
;
107 riscv_set_rve (bfd_boolean rve_value
)
109 riscv_opts
.rve
= rve_value
;
112 static riscv_subset_list_t riscv_subsets
;
115 riscv_subset_supports (const char *feature
)
117 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
120 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
124 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
128 case INSN_CLASS_I
: return riscv_subset_supports ("i");
129 case INSN_CLASS_C
: return riscv_subset_supports ("c");
130 case INSN_CLASS_A
: return riscv_subset_supports ("a");
131 case INSN_CLASS_M
: return riscv_subset_supports ("m");
132 case INSN_CLASS_F
: return riscv_subset_supports ("f");
133 case INSN_CLASS_D
: return riscv_subset_supports ("d");
134 case INSN_CLASS_D_AND_C
:
135 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
137 case INSN_CLASS_F_AND_C
:
138 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
140 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
143 as_fatal ("Unreachable");
148 /* Set which ISA and extensions are available. */
151 riscv_set_arch (const char *s
)
153 riscv_parse_subset_t rps
;
154 rps
.subset_list
= &riscv_subsets
;
155 rps
.error_handler
= as_fatal
;
158 riscv_release_subset_list (&riscv_subsets
);
159 riscv_parse_subset (&rps
, s
);
162 /* Handle of the OPCODE hash table. */
163 static struct hash_control
*op_hash
= NULL
;
165 /* Handle of the type of .insn hash table. */
166 static struct hash_control
*insn_type_hash
= NULL
;
168 /* This array holds the chars that always start a comment. If the
169 pre-processor is disabled, these aren't very useful */
170 const char comment_chars
[] = "#";
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that C style comments are always supported. */
179 const char line_comment_chars
[] = "#";
181 /* This array holds machine specific line separator characters. */
182 const char line_separator_chars
[] = ";";
184 /* Chars that can be used to separate mant from exp in floating point nums */
185 const char EXP_CHARS
[] = "eE";
187 /* Chars that mean this number is a floating point constant */
190 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
192 /* Indicate we are already assemble any instructions or not. */
193 static bfd_boolean start_assemble
= FALSE
;
195 /* Indicate arch attribute is explictly set. */
196 static bfd_boolean explicit_arch_attr
= FALSE
;
198 /* Macros for encoding relaxation state for RVC branches and far jumps. */
199 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
202 | ((uncond) ? 1 : 0) \
205 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
206 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
207 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
208 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
210 /* Is the given value a sign-extended 32-bit value? */
211 #define IS_SEXT_32BIT_NUM(x) \
212 (((x) &~ (offsetT) 0x7fffffff) == 0 \
213 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
215 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
216 #define IS_ZEXT_32BIT_NUM(x) \
217 (((x) &~ (offsetT) 0xffffffff) == 0 \
218 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
220 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
221 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
222 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
223 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
225 /* Determine if an instruction matches an opcode. */
226 #define OPCODE_MATCHES(OPCODE, OP) \
227 (((OPCODE) & MASK_##OP) == MATCH_##OP)
229 static char *expr_end
;
231 /* The default target format to use. */
234 riscv_target_format (void)
236 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
239 /* Return the length of instruction INSN. */
241 static inline unsigned int
242 insn_length (const struct riscv_cl_insn
*insn
)
244 return riscv_insn_length (insn
->insn_opcode
);
247 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
250 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
253 insn
->insn_opcode
= mo
->match
;
259 /* Install INSN at the location specified by its "frag" and "where" fields. */
262 install_insn (const struct riscv_cl_insn
*insn
)
264 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
265 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
268 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
269 and install the opcode in the new location. */
272 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
276 if (insn
->fixp
!= NULL
)
278 insn
->fixp
->fx_frag
= frag
;
279 insn
->fixp
->fx_where
= where
;
284 /* Add INSN to the end of the output. */
287 add_fixed_insn (struct riscv_cl_insn
*insn
)
289 char *f
= frag_more (insn_length (insn
));
290 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
294 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
295 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
297 frag_grow (max_chars
);
298 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
299 frag_var (rs_machine_dependent
, max_chars
, var
,
300 subtype
, symbol
, offset
, NULL
);
303 /* Compute the length of a branch sequence, and adjust the stored length
304 accordingly. If FRAGP is NULL, the worst-case length is returned. */
307 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
309 int jump
, rvc
, length
= 8;
314 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
315 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
316 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
318 /* Assume jumps are in range; the linker will catch any that aren't. */
319 length
= jump
? 4 : 8;
321 if (fragp
->fr_symbol
!= NULL
322 && S_IS_DEFINED (fragp
->fr_symbol
)
323 && !S_IS_WEAK (fragp
->fr_symbol
)
324 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
326 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
327 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
328 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
330 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
332 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
334 else if (!jump
&& rvc
)
339 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
344 /* Information about an opcode name, mnemonics and its value. */
351 /* List for all supported opcode name. */
352 static const struct opcode_name_t opcode_name_list
[] =
397 /* Hash table for lookup opcode name. */
398 static struct hash_control
*opcode_names_hash
= NULL
;
400 /* Initialization for hash table of opcode name. */
402 init_opcode_names_hash (void)
405 const struct opcode_name_t
*opcode
;
407 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
409 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
412 as_fatal (_("internal error: can't hash `%s': %s"),
413 opcode
->name
, retval
);
417 /* Find `s` is a valid opcode name or not,
418 return the opcode name info if found. */
419 static const struct opcode_name_t
*
420 opcode_name_lookup (char **s
)
424 struct opcode_name_t
*o
;
426 /* Find end of name. */
428 if (is_name_beginner (*e
))
430 while (is_part_of_name (*e
))
433 /* Terminate name. */
437 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
439 /* Advance to next token if one was recognized. */
457 static struct hash_control
*reg_names_hash
= NULL
;
458 static struct hash_control
*csr_extra_hash
= NULL
;
460 #define ENCODE_REG_HASH(cls, n) \
461 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
462 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
463 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
466 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
468 void *hash
= ENCODE_REG_HASH (class, n
);
469 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
472 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
476 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
480 for (i
= 0; i
< n
; i
++)
481 hash_reg_name (class, names
[i
], i
);
484 /* All RISC-V CSRs belong to one of these classes. */
491 CSR_CLASS_I_32
, /* rv32 only */
492 CSR_CLASS_F
, /* f-ext only */
495 /* This structure holds all restricted conditions for a CSR. */
497 struct riscv_csr_extra
499 /* Class to which this CSR belongs. Used to decide whether or
500 not this CSR is legal in the current -march context. */
501 enum riscv_csr_class csr_class
;
504 /* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */
507 riscv_init_csr_hashes (const char *name
,
509 enum riscv_csr_class
class)
511 struct riscv_csr_extra
*entry
= XNEW (struct riscv_csr_extra
);
512 entry
->csr_class
= class;
514 const char *hash_error
=
515 hash_insert (csr_extra_hash
, name
, (void *) entry
);
516 if (hash_error
!= NULL
)
518 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
520 /* Probably a memory allocation problem? Give up now. */
521 as_fatal (_("Broken assembler. No assembly attempted."));
524 hash_reg_name (RCLASS_CSR
, name
, address
);
527 /* Check wether the CSR is valid according to the ISA. */
530 riscv_csr_class_check (enum riscv_csr_class csr_class
)
534 case CSR_CLASS_I
: return riscv_subset_supports ("i");
535 case CSR_CLASS_F
: return riscv_subset_supports ("f");
537 return (xlen
== 32 && riscv_subset_supports ("i"));
544 /* If the CSR is defined, then we call `riscv_csr_class_check` to do the
545 further checking. Return FALSE if the CSR is not defined. Otherwise,
549 reg_csr_lookup_internal (const char *s
)
551 struct riscv_csr_extra
*r
=
552 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
557 /* We just report the warning when the CSR is invalid. */
558 if (!riscv_csr_class_check (r
->csr_class
))
559 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
565 reg_lookup_internal (const char *s
, enum reg_class
class)
567 void *r
= hash_find (reg_names_hash
, s
);
569 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
572 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
575 if (class == RCLASS_CSR
&& !reg_csr_lookup_internal (s
))
578 return DECODE_REG_NUM (r
);
582 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
588 /* Find end of name. */
590 if (is_name_beginner (*e
))
592 while (is_part_of_name (*e
))
595 /* Terminate name. */
599 /* Look for the register. Advance to next token if one was recognized. */
600 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
610 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
612 const char *p
= strchr (*s
, ',');
613 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
618 for (i
= 0; i
< size
; i
++)
619 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
629 /* For consistency checking, verify that all bits are specified either
630 by the match/mask part of the instruction definition, or by the
633 `length` could be 0, 4 or 8, 0 for auto detection. */
635 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
637 const char *p
= opc
->args
;
639 insn_t used_bits
= opc
->mask
;
641 insn_t required_bits
;
644 insn_width
= 8 * riscv_insn_length (opc
->match
);
646 insn_width
= 8 * length
;
648 required_bits
= ~0ULL >> (64 - insn_width
);
650 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
652 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
653 opc
->name
, opc
->args
);
657 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
664 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
665 case 'c': break; /* RS1, constrained to equal sp */
666 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
667 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
668 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
669 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
670 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
671 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
672 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
673 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
674 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
675 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
676 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
677 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
678 case 'w': break; /* RS1S, constrained to equal RD */
679 case 'x': break; /* RS2S, constrained to equal RD */
680 case 'z': break; /* RS2S, contrained to be x0 */
681 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
682 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
683 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
684 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
685 case 'U': break; /* RS1, constrained to equal RD */
686 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
687 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
688 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
689 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
690 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
691 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
692 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
693 case 'F': /* funct */
696 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
697 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
698 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
699 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
701 as_bad (_("internal: bad RISC-V opcode"
702 " (unknown operand type `CF%c'): %s %s"),
703 c
, opc
->name
, opc
->args
);
708 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
709 c
, opc
->name
, opc
->args
);
716 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
717 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
719 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
720 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
721 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
723 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
724 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
725 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
726 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
727 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
728 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
729 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
730 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
731 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
732 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
733 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
735 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
736 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
737 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
738 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
739 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
745 case 'F': /* funct */
748 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
749 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
750 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
752 as_bad (_("internal: bad RISC-V opcode"
753 " (unknown operand type `F%c'): %s %s"),
754 c
, opc
->name
, opc
->args
);
758 case 'O': /* opcode */
761 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
762 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
764 as_bad (_("internal: bad RISC-V opcode"
765 " (unknown operand type `F%c'): %s %s"),
766 c
, opc
->name
, opc
->args
);
771 as_bad (_("internal: bad RISC-V opcode "
772 "(unknown operand type `%c'): %s %s"),
773 c
, opc
->name
, opc
->args
);
777 if (used_bits
!= required_bits
)
779 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
780 ~(unsigned long)(used_bits
& required_bits
),
781 opc
->name
, opc
->args
);
787 struct percent_op_match
790 bfd_reloc_code_real_type reloc
;
793 /* Common hash table initialization function for
794 instruction and .insn directive. */
795 static struct hash_control
*
796 init_opcode_hash (const struct riscv_opcode
*opcodes
,
797 bfd_boolean insn_directive_p
)
801 struct hash_control
*hash
= hash_new ();
802 while (opcodes
[i
].name
)
804 const char *name
= opcodes
[i
].name
;
805 const char *hash_error
=
806 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
808 if (hash_error
!= NULL
)
810 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
811 opcodes
[i
].name
, hash_error
);
812 /* Probably a memory allocation problem? Give up now. */
813 as_fatal (_("Broken assembler. No assembly attempted."));
818 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
820 if (insn_directive_p
)
821 length
= ((name
[0] == 'c') ? 2 : 4);
823 length
= 0; /* Let assembler determine the length. */
824 if (!validate_riscv_insn (&opcodes
[i
], length
))
825 as_fatal (_("Broken assembler. No assembly attempted."));
828 gas_assert (!insn_directive_p
);
831 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
837 /* This function is called once, at assembler startup time. It should set up
838 all the tables, etc. that the MD part of the assembler will need. */
843 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
845 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
846 as_warn (_("Could not set architecture and machine"));
848 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
849 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
851 reg_names_hash
= hash_new ();
852 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
853 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
854 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
855 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
856 /* Add "fp" as an alias for "s0". */
857 hash_reg_name (RCLASS_GPR
, "fp", 8);
859 /* Create and insert CSR hash tables. */
860 csr_extra_hash
= hash_new ();
861 #define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
862 #define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
863 #include "opcode/riscv-opc.h"
866 opcode_names_hash
= hash_new ();
867 init_opcode_names_hash ();
869 /* Set the default alignment for the text section. */
870 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
874 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
881 case BFD_RELOC_RISCV_HI20
:
882 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
884 case BFD_RELOC_RISCV_LO12_S
:
885 return ENCODE_STYPE_IMM (value
);
887 case BFD_RELOC_RISCV_LO12_I
:
888 return ENCODE_ITYPE_IMM (value
);
895 /* Output an instruction. IP is the instruction information.
896 ADDRESS_EXPR is an operand of the instruction to be used with
900 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
901 bfd_reloc_code_real_type reloc_type
)
903 dwarf2_emit_insn (0);
905 if (reloc_type
!= BFD_RELOC_UNUSED
)
907 reloc_howto_type
*howto
;
909 gas_assert (address_expr
);
910 if (reloc_type
== BFD_RELOC_12_PCREL
911 || reloc_type
== BFD_RELOC_RISCV_JMP
)
913 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
914 int best_case
= riscv_insn_length (ip
->insn_opcode
);
915 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
916 add_relaxed_insn (ip
, worst_case
, best_case
,
917 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
918 address_expr
->X_add_symbol
,
919 address_expr
->X_add_number
);
924 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
926 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
928 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
929 bfd_get_reloc_size (howto
),
930 address_expr
, FALSE
, reloc_type
);
932 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
939 /* We need to start a new frag after any instruction that can be
940 optimized away or compressed by the linker during relaxation, to prevent
941 the assembler from computing static offsets across such an instruction.
942 This is necessary to get correct EH info. */
943 if (reloc_type
== BFD_RELOC_RISCV_CALL
944 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
945 || reloc_type
== BFD_RELOC_RISCV_HI20
946 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
947 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
948 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
950 frag_wane (frag_now
);
955 /* Build an instruction created by a macro expansion. This is passed
956 a pointer to the count of instructions created so far, an
957 expression, the name of the instruction to build, an operand format
958 string, and corresponding arguments. */
961 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
963 const struct riscv_opcode
*mo
;
964 struct riscv_cl_insn insn
;
965 bfd_reloc_code_real_type r
;
968 va_start (args
, fmt
);
970 r
= BFD_RELOC_UNUSED
;
971 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
974 /* Find a non-RVC variant of the instruction. append_insn will compress
976 while (riscv_insn_length (mo
->match
) < 4)
978 gas_assert (strcmp (name
, mo
->name
) == 0);
980 create_insn (&insn
, mo
);
986 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
990 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
994 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
998 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1004 gas_assert (ep
!= NULL
);
1005 r
= va_arg (args
, int);
1013 as_fatal (_("internal error: invalid macro"));
1018 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1020 append_insn (&insn
, ep
, r
);
1023 /* Build an instruction created by a macro expansion. Like md_assemble but
1024 accept a printf-style format string and arguments. */
1027 md_assemblef (const char *format
, ...)
1033 va_start (ap
, format
);
1035 r
= vasprintf (&buf
, format
, ap
);
1038 as_fatal (_("internal error: vasprintf failed"));
1046 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1049 normalize_constant_expr (expressionS
*ex
)
1053 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1054 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1055 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1059 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1060 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1063 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1064 bfd_boolean maybe_csr
)
1066 if (ex
->X_op
== O_big
)
1067 as_bad (_("unsupported large constant"));
1068 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1069 as_bad (_("unknown CSR `%s'"),
1070 S_GET_NAME (ex
->X_add_symbol
));
1071 else if (ex
->X_op
!= O_constant
)
1072 as_bad (_("Instruction %s requires absolute expression"),
1074 normalize_constant_expr (ex
);
1078 make_internal_label (void)
1080 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1081 (valueT
) frag_now_fix (), frag_now
);
1084 /* Load an entry from the GOT. */
1086 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1087 const char *lo_insn
, const char *lo_pattern
,
1088 bfd_reloc_code_real_type hi_reloc
,
1089 bfd_reloc_code_real_type lo_reloc
)
1092 ep2
.X_op
= O_symbol
;
1093 ep2
.X_add_symbol
= make_internal_label ();
1094 ep2
.X_add_number
= 0;
1096 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1097 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1101 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1102 bfd_reloc_code_real_type hi_reloc
,
1103 bfd_reloc_code_real_type lo_reloc
)
1105 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1109 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1110 bfd_reloc_code_real_type hi_reloc
,
1111 bfd_reloc_code_real_type lo_reloc
)
1113 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1116 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1118 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1119 bfd_reloc_code_real_type reloc
)
1121 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1122 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1125 /* Load an integer constant into a register. */
1128 load_const (int reg
, expressionS
*ep
)
1130 int shift
= RISCV_IMM_BITS
;
1131 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1132 expressionS upper
= *ep
, lower
= *ep
;
1133 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1134 upper
.X_add_number
-= lower
.X_add_number
;
1136 if (ep
->X_op
!= O_constant
)
1138 as_bad (_("unsupported large constant"));
1142 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1144 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1145 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1148 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1149 load_const (reg
, &upper
);
1151 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1152 if (lower
.X_add_number
!= 0)
1153 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1154 lower
.X_add_number
);
1158 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1161 if (upper
.X_add_number
!= 0)
1163 /* Discard low part and zero-extend upper immediate. */
1164 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1166 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1170 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1171 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1172 lower
.X_add_number
);
1176 /* Expand RISC-V assembly macros into one or more instructions. */
1178 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1179 bfd_reloc_code_real_type
*imm_reloc
)
1181 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1182 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1183 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1184 int mask
= ip
->insn_mo
->mask
;
1189 load_const (rd
, imm_expr
);
1194 /* Load the address of a symbol into a register. */
1195 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1196 as_bad (_("offset too large"));
1198 if (imm_expr
->X_op
== O_constant
)
1199 load_const (rd
, imm_expr
);
1200 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1201 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1202 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1203 else /* Local PIC symbol, or any non-PIC symbol */
1204 pcrel_load (rd
, rd
, imm_expr
, "addi",
1205 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1209 pcrel_load (rd
, rd
, imm_expr
, "addi",
1210 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1214 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1215 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1219 pcrel_load (rd
, rd
, imm_expr
, "lb",
1220 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1224 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1225 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1229 pcrel_load (rd
, rd
, imm_expr
, "lh",
1230 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1234 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1235 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1239 pcrel_load (rd
, rd
, imm_expr
, "lw",
1240 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1244 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1245 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1249 pcrel_load (rd
, rd
, imm_expr
, "ld",
1250 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1254 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1255 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1259 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1260 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1264 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1265 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1269 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1270 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1274 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1275 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1279 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1280 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1284 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1285 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1289 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1290 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1294 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1298 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1303 static const struct percent_op_match percent_op_utype
[] =
1305 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1306 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1307 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1308 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1309 {"%hi", BFD_RELOC_RISCV_HI20
},
1313 static const struct percent_op_match percent_op_itype
[] =
1315 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1316 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1317 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1321 static const struct percent_op_match percent_op_stype
[] =
1323 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1324 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1325 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1329 static const struct percent_op_match percent_op_rtype
[] =
1331 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1335 static const struct percent_op_match percent_op_null
[] =
1340 /* Return true if *STR points to a relocation operator. When returning true,
1341 move *STR over the operator and store its relocation code in *RELOC.
1342 Leave both *STR and *RELOC alone when returning false. */
1345 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1346 const struct percent_op_match
*percent_op
)
1348 for ( ; percent_op
->str
; percent_op
++)
1349 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1351 int len
= strlen (percent_op
->str
);
1353 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1356 *str
+= strlen (percent_op
->str
);
1357 *reloc
= percent_op
->reloc
;
1359 /* Check whether the output BFD supports this relocation.
1360 If not, issue an error and fall back on something safe. */
1361 if (*reloc
!= BFD_RELOC_UNUSED
1362 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1364 as_bad ("relocation %s isn't supported by the current ABI",
1366 *reloc
= BFD_RELOC_UNUSED
;
1374 my_getExpression (expressionS
*ep
, char *str
)
1378 save_in
= input_line_pointer
;
1379 input_line_pointer
= str
;
1381 expr_end
= input_line_pointer
;
1382 input_line_pointer
= save_in
;
1385 /* Parse string STR as a 16-bit relocatable operand. Store the
1386 expression in *EP and the relocation, if any, in RELOC.
1387 Return the number of relocation operators used (0 or 1).
1389 On exit, EXPR_END points to the first character after the expression. */
1392 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1393 char *str
, const struct percent_op_match
*percent_op
)
1396 unsigned crux_depth
, str_depth
, regno
;
1399 /* First, check for integer registers. No callers can accept a reg, but
1400 we need to avoid accidentally creating a useless undefined symbol below,
1401 if this is an instruction pattern that can't match. A glibc build fails
1402 if this is removed. */
1403 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1405 ep
->X_op
= O_register
;
1406 ep
->X_add_number
= regno
;
1411 /* Search for the start of the main expression.
1412 End the loop with CRUX pointing to the start
1413 of the main expression and with CRUX_DEPTH containing the number
1414 of open brackets at that point. */
1421 crux_depth
= str_depth
;
1423 /* Skip over whitespace and brackets, keeping count of the number
1425 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1431 && parse_relocation (&str
, reloc
, percent_op
));
1433 my_getExpression (ep
, crux
);
1436 /* Match every open bracket. */
1437 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1442 as_bad ("unclosed '('");
1449 /* Parse opcode name, could be an mnemonics or number. */
1451 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1452 char *str
, const struct percent_op_match
*percent_op
)
1454 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1458 ep
->X_op
= O_constant
;
1459 ep
->X_add_number
= o
->val
;
1463 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1466 /* Detect and handle implicitly zero load-store offsets. For example,
1467 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1468 an implicit offset was detected. */
1471 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1473 /* Check whether there is only a single bracketed expression left.
1474 If so, it must be the base register and the constant must be zero. */
1475 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1477 ep
->X_op
= O_constant
;
1478 ep
->X_add_number
= 0;
1485 /* This routine assembles an instruction into its binary format. As a
1486 side effect, it sets the global variable imm_reloc to the type of
1487 relocation to do if one of the operands is an address expression. */
1490 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1491 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1496 struct riscv_opcode
*insn
;
1501 const struct percent_op_match
*p
;
1502 const char *error
= "unrecognized opcode";
1504 /* Parse the name of the instruction. Terminate the string if whitespace
1505 is found so that hash_find only sees the name part of the string. */
1506 for (s
= str
; *s
!= '\0'; ++s
)
1514 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1517 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1519 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1522 if (!riscv_multi_subset_supports (insn
->insn_class
))
1525 create_insn (ip
, insn
);
1528 imm_expr
->X_op
= O_absent
;
1529 *imm_reloc
= BFD_RELOC_UNUSED
;
1530 p
= percent_op_itype
;
1532 for (args
= insn
->args
;; ++args
)
1534 s
+= strspn (s
, " \t");
1537 case '\0': /* End of args. */
1538 if (insn
->pinfo
!= INSN_MACRO
)
1540 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1543 /* For .insn, insn->match and insn->mask are 0. */
1544 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1552 /* Successful assembly. */
1559 case 's': /* RS1 x8-x15 */
1560 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1561 || !(regno
>= 8 && regno
<= 15))
1563 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1565 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1566 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1567 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1570 case 't': /* RS2 x8-x15 */
1571 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1572 || !(regno
>= 8 && regno
<= 15))
1574 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1576 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1577 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1578 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1581 case 'U': /* RS1, constrained to equal RD. */
1582 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1583 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1587 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1589 INSERT_OPERAND (CRS2
, *ip
, regno
);
1591 case 'c': /* RS1, constrained to equal sp. */
1592 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1596 case 'z': /* RS2, contrained to equal x0. */
1597 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1602 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1603 || imm_expr
->X_op
!= O_constant
1604 || imm_expr
->X_add_number
<= 0
1605 || imm_expr
->X_add_number
>= 64)
1607 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1610 imm_expr
->X_op
= O_absent
;
1613 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1614 || imm_expr
->X_op
!= O_constant
1615 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1616 || imm_expr
->X_add_number
<= 0
1617 || imm_expr
->X_add_number
>= 32)
1619 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1622 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1623 || imm_expr
->X_op
!= O_constant
1624 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1625 || imm_expr
->X_add_number
< 0
1626 || imm_expr
->X_add_number
>= 256)
1628 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1631 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1632 || imm_expr
->X_op
!= O_constant
1633 || imm_expr
->X_add_number
== 0
1634 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1636 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1639 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1640 || imm_expr
->X_op
!= O_constant
1641 || imm_expr
->X_add_number
== 0
1642 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1644 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1647 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1649 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1650 || imm_expr
->X_op
!= O_constant
1651 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1653 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1656 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1658 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1659 || imm_expr
->X_op
!= O_constant
1660 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1662 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1665 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1667 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1668 || imm_expr
->X_op
!= O_constant
1669 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1672 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1675 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1677 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1678 || imm_expr
->X_op
!= O_constant
1679 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1682 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1685 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1686 || imm_expr
->X_op
!= O_constant
1687 /* C.addiw, c.li, and c.andi allow zero immediate.
1688 C.addi allows zero immediate as hint. Otherwise this
1690 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1692 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1695 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1696 || imm_expr
->X_op
!= O_constant
1697 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1698 || imm_expr
->X_add_number
== 0)
1701 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1704 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1705 || imm_expr
->X_op
!= O_constant
1706 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1707 || imm_expr
->X_add_number
== 0)
1710 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1713 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1715 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1716 || imm_expr
->X_op
!= O_constant
1717 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1720 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1723 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1725 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1726 || imm_expr
->X_op
!= O_constant
1727 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1730 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1733 p
= percent_op_utype
;
1734 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1737 if (imm_expr
->X_op
!= O_constant
1738 || imm_expr
->X_add_number
<= 0
1739 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1740 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1741 && (imm_expr
->X_add_number
<
1742 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1744 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1747 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1748 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1749 || ((int32_t)imm_expr
->X_add_number
1750 != imm_expr
->X_add_number
))
1752 imm_expr
->X_add_number
=
1753 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1759 case 'S': /* Floating-point RS1 x8-x15. */
1760 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1761 || !(regno
>= 8 && regno
<= 15))
1763 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1765 case 'D': /* Floating-point RS2 x8-x15. */
1766 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1767 || !(regno
>= 8 && regno
<= 15))
1769 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1771 case 'T': /* Floating-point RS2. */
1772 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1774 INSERT_OPERAND (CRS2
, *ip
, regno
);
1780 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1781 || imm_expr
->X_op
!= O_constant
1782 || imm_expr
->X_add_number
< 0
1783 || imm_expr
->X_add_number
>= 64)
1785 as_bad (_("bad value for funct6 field, "
1786 "value must be 0...64"));
1790 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1791 imm_expr
->X_op
= O_absent
;
1795 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1796 || imm_expr
->X_op
!= O_constant
1797 || imm_expr
->X_add_number
< 0
1798 || imm_expr
->X_add_number
>= 16)
1800 as_bad (_("bad value for funct4 field, "
1801 "value must be 0...15"));
1805 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1806 imm_expr
->X_op
= O_absent
;
1810 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1811 || imm_expr
->X_op
!= O_constant
1812 || imm_expr
->X_add_number
< 0
1813 || imm_expr
->X_add_number
>= 8)
1815 as_bad (_("bad value for funct3 field, "
1816 "value must be 0...7"));
1819 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1820 imm_expr
->X_op
= O_absent
;
1824 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1825 || imm_expr
->X_op
!= O_constant
1826 || imm_expr
->X_add_number
< 0
1827 || imm_expr
->X_add_number
>= 4)
1829 as_bad (_("bad value for funct2 field, "
1830 "value must be 0...3"));
1833 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1834 imm_expr
->X_op
= O_absent
;
1838 as_bad (_("bad compressed FUNCT field"
1839 " specifier 'CF%c'\n"),
1845 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1864 case '<': /* Shift amount, 0 - 31. */
1865 my_getExpression (imm_expr
, s
);
1866 check_absolute_expr (ip
, imm_expr
, FALSE
);
1867 if ((unsigned long) imm_expr
->X_add_number
> 31)
1868 as_bad (_("Improper shift amount (%lu)"),
1869 (unsigned long) imm_expr
->X_add_number
);
1870 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1871 imm_expr
->X_op
= O_absent
;
1875 case '>': /* Shift amount, 0 - (XLEN-1). */
1876 my_getExpression (imm_expr
, s
);
1877 check_absolute_expr (ip
, imm_expr
, FALSE
);
1878 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1879 as_bad (_("Improper shift amount (%lu)"),
1880 (unsigned long) imm_expr
->X_add_number
);
1881 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1882 imm_expr
->X_op
= O_absent
;
1886 case 'Z': /* CSRRxI immediate. */
1887 my_getExpression (imm_expr
, s
);
1888 check_absolute_expr (ip
, imm_expr
, FALSE
);
1889 if ((unsigned long) imm_expr
->X_add_number
> 31)
1890 as_bad (_("Improper CSRxI immediate (%lu)"),
1891 (unsigned long) imm_expr
->X_add_number
);
1892 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1893 imm_expr
->X_op
= O_absent
;
1897 case 'E': /* Control register. */
1898 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1899 INSERT_OPERAND (CSR
, *ip
, regno
);
1902 my_getExpression (imm_expr
, s
);
1903 check_absolute_expr (ip
, imm_expr
, TRUE
);
1904 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1905 as_bad (_("Improper CSR address (%lu)"),
1906 (unsigned long) imm_expr
->X_add_number
);
1907 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1908 imm_expr
->X_op
= O_absent
;
1913 case 'm': /* Rounding mode. */
1914 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1916 INSERT_OPERAND (RM
, *ip
, regno
);
1922 case 'Q': /* Fence predecessor/successor. */
1923 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1927 INSERT_OPERAND (PRED
, *ip
, regno
);
1929 INSERT_OPERAND (SUCC
, *ip
, regno
);
1934 case 'd': /* Destination register. */
1935 case 's': /* Source register. */
1936 case 't': /* Target register. */
1937 case 'r': /* rs3. */
1938 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1944 /* Now that we have assembled one operand, we use the args
1945 string to figure out where it goes in the instruction. */
1949 INSERT_OPERAND (RS1
, *ip
, regno
);
1952 INSERT_OPERAND (RD
, *ip
, regno
);
1955 INSERT_OPERAND (RS2
, *ip
, regno
);
1958 INSERT_OPERAND (RS3
, *ip
, regno
);
1965 case 'D': /* Floating point rd. */
1966 case 'S': /* Floating point rs1. */
1967 case 'T': /* Floating point rs2. */
1968 case 'U': /* Floating point rs1 and rs2. */
1969 case 'R': /* Floating point rs3. */
1970 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1978 INSERT_OPERAND (RD
, *ip
, regno
);
1981 INSERT_OPERAND (RS1
, *ip
, regno
);
1984 INSERT_OPERAND (RS1
, *ip
, regno
);
1987 INSERT_OPERAND (RS2
, *ip
, regno
);
1990 INSERT_OPERAND (RS3
, *ip
, regno
);
1999 my_getExpression (imm_expr
, s
);
2000 if (imm_expr
->X_op
!= O_big
2001 && imm_expr
->X_op
!= O_constant
)
2003 normalize_constant_expr (imm_expr
);
2008 my_getExpression (imm_expr
, s
);
2009 normalize_constant_expr (imm_expr
);
2010 /* The 'A' format specifier must be a symbol. */
2011 if (imm_expr
->X_op
!= O_symbol
)
2013 *imm_reloc
= BFD_RELOC_32
;
2018 my_getExpression (imm_expr
, s
);
2019 normalize_constant_expr (imm_expr
);
2020 /* The 'B' format specifier must be a symbol or a constant. */
2021 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2023 if (imm_expr
->X_op
== O_symbol
)
2024 *imm_reloc
= BFD_RELOC_32
;
2028 case 'j': /* Sign-extended immediate. */
2029 p
= percent_op_itype
;
2030 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2032 case 'q': /* Store displacement. */
2033 p
= percent_op_stype
;
2034 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2036 case 'o': /* Load displacement. */
2037 p
= percent_op_itype
;
2038 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2040 case '1': /* 4-operand add, must be %tprel_add. */
2041 p
= percent_op_rtype
;
2043 case '0': /* AMO "displacement," which must be zero. */
2044 p
= percent_op_null
;
2046 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2049 /* If this value won't fit into a 16 bit offset, then go
2050 find a macro that will generate the 32 bit offset
2052 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2054 normalize_constant_expr (imm_expr
);
2055 if (imm_expr
->X_op
!= O_constant
2056 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2058 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2059 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2066 case 'p': /* PC-relative offset. */
2068 *imm_reloc
= BFD_RELOC_12_PCREL
;
2069 my_getExpression (imm_expr
, s
);
2073 case 'u': /* Upper 20 bits. */
2074 p
= percent_op_utype
;
2075 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2077 if (imm_expr
->X_op
!= O_constant
)
2080 if (imm_expr
->X_add_number
< 0
2081 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2082 as_bad (_("lui expression not in range 0..1048575"));
2084 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2085 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2090 case 'a': /* 20-bit PC-relative offset. */
2092 my_getExpression (imm_expr
, s
);
2094 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2098 my_getExpression (imm_expr
, s
);
2100 if (strcmp (s
, "@plt") == 0)
2102 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2106 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2112 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2113 || imm_expr
->X_op
!= O_constant
2114 || imm_expr
->X_add_number
< 0
2115 || imm_expr
->X_add_number
>= 128
2116 || (imm_expr
->X_add_number
& 0x3) != 3)
2118 as_bad (_("bad value for opcode field, "
2119 "value must be 0...127 and "
2120 "lower 2 bits must be 0x3"));
2124 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2125 imm_expr
->X_op
= O_absent
;
2129 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2130 || imm_expr
->X_op
!= O_constant
2131 || imm_expr
->X_add_number
< 0
2132 || imm_expr
->X_add_number
>= 3)
2134 as_bad (_("bad value for opcode field, "
2135 "value must be 0...2"));
2139 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2140 imm_expr
->X_op
= O_absent
;
2144 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2152 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2153 || imm_expr
->X_op
!= O_constant
2154 || imm_expr
->X_add_number
< 0
2155 || imm_expr
->X_add_number
>= 128)
2157 as_bad (_("bad value for funct7 field, "
2158 "value must be 0...127"));
2162 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2163 imm_expr
->X_op
= O_absent
;
2167 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2168 || imm_expr
->X_op
!= O_constant
2169 || imm_expr
->X_add_number
< 0
2170 || imm_expr
->X_add_number
>= 8)
2172 as_bad (_("bad value for funct3 field, "
2173 "value must be 0...7"));
2177 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2178 imm_expr
->X_op
= O_absent
;
2182 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2183 || imm_expr
->X_op
!= O_constant
2184 || imm_expr
->X_add_number
< 0
2185 || imm_expr
->X_add_number
>= 4)
2187 as_bad (_("bad value for funct2 field, "
2188 "value must be 0...3"));
2192 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2193 imm_expr
->X_op
= O_absent
;
2198 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2203 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2204 || imm_expr
->X_op
!= O_constant
2205 || imm_expr
->X_add_number
!= 0)
2208 imm_expr
->X_op
= O_absent
;
2212 as_fatal (_("internal error: bad argument type %c"), *args
);
2217 error
= _("illegal operands");
2221 /* Restore the character we might have clobbered above. */
2223 *(argsStart
- 1) = save_c
;
2229 md_assemble (char *str
)
2231 struct riscv_cl_insn insn
;
2232 expressionS imm_expr
;
2233 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2235 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2237 start_assemble
= TRUE
;
2241 as_bad ("%s `%s'", error
, str
);
2245 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2246 macro (&insn
, &imm_expr
, &imm_reloc
);
2248 append_insn (&insn
, &imm_expr
, imm_reloc
);
2252 md_atof (int type
, char *litP
, int *sizeP
)
2254 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2258 md_number_to_chars (char *buf
, valueT val
, int n
)
2260 number_to_chars_littleendian (buf
, val
, n
);
2263 const char *md_shortopts
= "O::g::G:";
2267 OPTION_MARCH
= OPTION_MD_BASE
,
2274 OPTION_NO_ARCH_ATTR
,
2278 struct option md_longopts
[] =
2280 {"march", required_argument
, NULL
, OPTION_MARCH
},
2281 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2282 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2283 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2284 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2285 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2286 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2287 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2288 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2290 {NULL
, no_argument
, NULL
, 0}
2292 size_t md_longopts_size
= sizeof (md_longopts
);
2295 FLOAT_ABI_DEFAULT
= -1,
2301 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2304 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2306 abi_xlen
= new_xlen
;
2307 float_abi
= new_float_abi
;
2312 md_parse_option (int c
, const char *arg
)
2317 riscv_set_arch (arg
);
2321 riscv_opts
.pic
= FALSE
;
2325 riscv_opts
.pic
= TRUE
;
2329 if (strcmp (arg
, "ilp32") == 0)
2330 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2331 else if (strcmp (arg
, "ilp32e") == 0)
2332 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2333 else if (strcmp (arg
, "ilp32f") == 0)
2334 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2335 else if (strcmp (arg
, "ilp32d") == 0)
2336 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2337 else if (strcmp (arg
, "ilp32q") == 0)
2338 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2339 else if (strcmp (arg
, "lp64") == 0)
2340 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2341 else if (strcmp (arg
, "lp64f") == 0)
2342 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2343 else if (strcmp (arg
, "lp64d") == 0)
2344 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2345 else if (strcmp (arg
, "lp64q") == 0)
2346 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2352 riscv_opts
.relax
= TRUE
;
2355 case OPTION_NO_RELAX
:
2356 riscv_opts
.relax
= FALSE
;
2359 case OPTION_ARCH_ATTR
:
2360 riscv_opts
.arch_attr
= TRUE
;
2363 case OPTION_NO_ARCH_ATTR
:
2364 riscv_opts
.arch_attr
= FALSE
;
2375 riscv_after_parse_args (void)
2379 if (strcmp (default_arch
, "riscv32") == 0)
2381 else if (strcmp (default_arch
, "riscv64") == 0)
2384 as_bad ("unknown default architecture `%s'", default_arch
);
2387 if (riscv_subsets
.head
== NULL
)
2388 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2390 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2391 riscv_set_rvc (FALSE
);
2392 if (riscv_subset_supports ("c"))
2393 riscv_set_rvc (TRUE
);
2395 /* Enable RVE if specified by the -march option. */
2396 riscv_set_rve (FALSE
);
2397 if (riscv_subset_supports ("e"))
2398 riscv_set_rve (TRUE
);
2400 /* Infer ABI from ISA if not specified on command line. */
2403 else if (abi_xlen
> xlen
)
2404 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2405 else if (abi_xlen
< xlen
)
2406 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2408 if (float_abi
== FLOAT_ABI_DEFAULT
)
2410 riscv_subset_t
*subset
;
2412 /* Assume soft-float unless D extension is present. */
2413 float_abi
= FLOAT_ABI_SOFT
;
2415 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2417 if (strcasecmp (subset
->name
, "D") == 0)
2418 float_abi
= FLOAT_ABI_DOUBLE
;
2419 if (strcasecmp (subset
->name
, "Q") == 0)
2420 float_abi
= FLOAT_ABI_QUAD
;
2425 elf_flags
|= EF_RISCV_RVE
;
2427 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2428 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2430 /* If the CIE to be produced has not been overridden on the command line,
2431 then produce version 3 by default. This allows us to use the full
2432 range of registers in a .cfi_return_column directive. */
2433 if (flag_dwarf_cie_version
== -1)
2434 flag_dwarf_cie_version
= 3;
2438 md_pcrel_from (fixS
*fixP
)
2440 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2443 /* Apply a fixup to the object file. */
2446 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2448 unsigned int subtype
;
2449 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2450 bfd_boolean relaxable
= FALSE
;
2454 /* Remember value for tc_gen_reloc. */
2455 fixP
->fx_addnumber
= *valP
;
2457 switch (fixP
->fx_r_type
)
2459 case BFD_RELOC_RISCV_HI20
:
2460 case BFD_RELOC_RISCV_LO12_I
:
2461 case BFD_RELOC_RISCV_LO12_S
:
2462 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2463 | bfd_getl32 (buf
), buf
);
2464 if (fixP
->fx_addsy
== NULL
)
2465 fixP
->fx_done
= TRUE
;
2469 case BFD_RELOC_RISCV_GOT_HI20
:
2470 case BFD_RELOC_RISCV_ADD8
:
2471 case BFD_RELOC_RISCV_ADD16
:
2472 case BFD_RELOC_RISCV_ADD32
:
2473 case BFD_RELOC_RISCV_ADD64
:
2474 case BFD_RELOC_RISCV_SUB6
:
2475 case BFD_RELOC_RISCV_SUB8
:
2476 case BFD_RELOC_RISCV_SUB16
:
2477 case BFD_RELOC_RISCV_SUB32
:
2478 case BFD_RELOC_RISCV_SUB64
:
2479 case BFD_RELOC_RISCV_RELAX
:
2482 case BFD_RELOC_RISCV_TPREL_HI20
:
2483 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2484 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2485 case BFD_RELOC_RISCV_TPREL_ADD
:
2489 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2490 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2491 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2492 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2493 if (fixP
->fx_addsy
!= NULL
)
2494 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2497 _("TLS relocation against a constant"));
2501 /* Use pc-relative relocation for FDE initial location.
2502 The symbol address in .eh_frame may be adjusted in
2503 _bfd_elf_discard_section_eh_frame, and the content of
2504 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2505 Therefore, we cannot insert a relocation whose addend symbol is
2506 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2507 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2508 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2509 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2510 && S_GET_VALUE (fixP
->fx_subsy
)
2511 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2513 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2514 fixP
->fx_subsy
= NULL
;
2521 case BFD_RELOC_RISCV_CFA
:
2522 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2524 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2525 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2526 fixP
->fx_next
->fx_subsy
= NULL
;
2527 fixP
->fx_next
->fx_offset
= 0;
2528 fixP
->fx_subsy
= NULL
;
2530 switch (fixP
->fx_r_type
)
2533 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2534 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2538 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2539 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2543 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2544 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2548 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2549 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2552 case BFD_RELOC_RISCV_CFA
:
2553 /* Load the byte to get the subtype. */
2554 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2555 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2558 case DW_CFA_advance_loc1
:
2559 fixP
->fx_where
= loc
+ 1;
2560 fixP
->fx_next
->fx_where
= loc
+ 1;
2561 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2562 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2565 case DW_CFA_advance_loc2
:
2567 fixP
->fx_next
->fx_size
= 2;
2568 fixP
->fx_where
= loc
+ 1;
2569 fixP
->fx_next
->fx_where
= loc
+ 1;
2570 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2571 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2574 case DW_CFA_advance_loc4
:
2576 fixP
->fx_next
->fx_size
= 4;
2577 fixP
->fx_where
= loc
;
2578 fixP
->fx_next
->fx_where
= loc
;
2579 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2580 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2584 if (subtype
< 0x80 && (subtype
& 0x40))
2586 /* DW_CFA_advance_loc */
2587 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2588 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2589 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2590 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2593 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2599 /* This case is unreachable. */
2606 /* If we are deleting this reloc entry, we must fill in the
2607 value now. This can happen if we have a .word which is not
2608 resolved when it appears but is later defined. */
2609 if (fixP
->fx_addsy
== NULL
)
2611 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2612 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2617 case BFD_RELOC_RISCV_JMP
:
2620 /* Fill in a tentative value to improve objdump readability. */
2621 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2622 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2623 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2627 case BFD_RELOC_12_PCREL
:
2630 /* Fill in a tentative value to improve objdump readability. */
2631 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2632 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2633 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2637 case BFD_RELOC_RISCV_RVC_BRANCH
:
2640 /* Fill in a tentative value to improve objdump readability. */
2641 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2642 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2643 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2647 case BFD_RELOC_RISCV_RVC_JUMP
:
2650 /* Fill in a tentative value to improve objdump readability. */
2651 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2652 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2653 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2657 case BFD_RELOC_RISCV_CALL
:
2658 case BFD_RELOC_RISCV_CALL_PLT
:
2662 case BFD_RELOC_RISCV_PCREL_HI20
:
2663 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2664 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2665 relaxable
= riscv_opts
.relax
;
2668 case BFD_RELOC_RISCV_ALIGN
:
2672 /* We ignore generic BFD relocations we don't know about. */
2673 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2674 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2677 if (fixP
->fx_subsy
!= NULL
)
2678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2679 _("unsupported symbol subtraction"));
2681 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2682 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2684 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2685 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2686 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2690 /* Because the value of .cfi_remember_state may changed after relaxation,
2691 we insert a fix to relocate it again in link-time. */
2694 riscv_pre_output_hook (void)
2696 const frchainS
*frch
;
2699 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2700 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2704 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2706 if (frag
->fr_type
== rs_cfa
)
2709 expressionS
*symval
;
2711 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2712 exp
.X_op
= O_subtract
;
2713 exp
.X_add_symbol
= symval
->X_add_symbol
;
2714 exp
.X_add_number
= 0;
2715 exp
.X_op_symbol
= symval
->X_op_symbol
;
2717 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2718 BFD_RELOC_RISCV_CFA
);
2725 /* This structure is used to hold a stack of .option values. */
2727 struct riscv_option_stack
2729 struct riscv_option_stack
*next
;
2730 struct riscv_set_options options
;
2733 static struct riscv_option_stack
*riscv_opts_stack
;
2735 /* Handle the .option pseudo-op. */
2738 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2740 char *name
= input_line_pointer
, ch
;
2742 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2743 ++input_line_pointer
;
2744 ch
= *input_line_pointer
;
2745 *input_line_pointer
= '\0';
2747 if (strcmp (name
, "rvc") == 0)
2748 riscv_set_rvc (TRUE
);
2749 else if (strcmp (name
, "norvc") == 0)
2750 riscv_set_rvc (FALSE
);
2751 else if (strcmp (name
, "pic") == 0)
2752 riscv_opts
.pic
= TRUE
;
2753 else if (strcmp (name
, "nopic") == 0)
2754 riscv_opts
.pic
= FALSE
;
2755 else if (strcmp (name
, "relax") == 0)
2756 riscv_opts
.relax
= TRUE
;
2757 else if (strcmp (name
, "norelax") == 0)
2758 riscv_opts
.relax
= FALSE
;
2759 else if (strcmp (name
, "push") == 0)
2761 struct riscv_option_stack
*s
;
2763 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2764 s
->next
= riscv_opts_stack
;
2765 s
->options
= riscv_opts
;
2766 riscv_opts_stack
= s
;
2768 else if (strcmp (name
, "pop") == 0)
2770 struct riscv_option_stack
*s
;
2772 s
= riscv_opts_stack
;
2774 as_bad (_(".option pop with no .option push"));
2777 riscv_opts
= s
->options
;
2778 riscv_opts_stack
= s
->next
;
2784 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2786 *input_line_pointer
= ch
;
2787 demand_empty_rest_of_line ();
2790 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2791 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2792 use in DWARF debug information. */
2795 s_dtprel (int bytes
)
2802 if (ex
.X_op
!= O_symbol
)
2804 as_bad (_("Unsupported use of %s"), (bytes
== 8
2807 ignore_rest_of_line ();
2810 p
= frag_more (bytes
);
2811 md_number_to_chars (p
, 0, bytes
);
2812 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2814 ? BFD_RELOC_RISCV_TLS_DTPREL64
2815 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2817 demand_empty_rest_of_line ();
2820 /* Handle the .bss pseudo-op. */
2823 s_bss (int ignore ATTRIBUTE_UNUSED
)
2825 subseg_set (bss_section
, 0);
2826 demand_empty_rest_of_line ();
2830 riscv_make_nops (char *buf
, bfd_vma bytes
)
2834 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2835 means we are not within a valid instruction sequence. It is thus safe
2836 to use a zero byte, even though that is not a valid instruction. */
2840 /* Use at most one 2-byte NOP. */
2841 if ((bytes
- i
) % 4 == 2)
2843 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2847 /* Fill the remainder with 4-byte NOPs. */
2848 for ( ; i
< bytes
; i
+= 4)
2849 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2852 /* Called from md_do_align. Used to create an alignment frag in a
2853 code section by emitting a worst-case NOP sequence that the linker
2854 will later relax to the correct number of NOPs. We can't compute
2855 the correct alignment now because of other linker relaxations. */
2858 riscv_frag_align_code (int n
)
2860 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2861 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2862 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2866 /* If we are moving to a smaller alignment than the instruction size, then no
2867 alignment is required. */
2868 if (bytes
<= insn_alignment
)
2871 /* When not relaxing, riscv_handle_align handles code alignment. */
2872 if (!riscv_opts
.relax
)
2875 nops
= frag_more (worst_case_bytes
);
2877 ex
.X_op
= O_constant
;
2878 ex
.X_add_number
= worst_case_bytes
;
2880 riscv_make_nops (nops
, worst_case_bytes
);
2882 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2883 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2888 /* Implement HANDLE_ALIGN. */
2891 riscv_handle_align (fragS
*fragP
)
2893 switch (fragP
->fr_type
)
2896 /* When relaxing, riscv_frag_align_code handles code alignment. */
2897 if (!riscv_opts
.relax
)
2899 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2900 - fragP
->fr_address
- fragP
->fr_fix
);
2901 /* We have 4 byte uncompressed nops. */
2902 bfd_signed_vma size
= 4;
2903 bfd_signed_vma excess
= bytes
% size
;
2904 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2909 /* Insert zeros or compressed nops to get 4 byte alignment. */
2912 riscv_make_nops (p
, excess
);
2913 fragP
->fr_fix
+= excess
;
2917 /* Insert variable number of 4 byte uncompressed nops. */
2918 riscv_make_nops (p
, size
);
2919 fragP
->fr_var
= size
;
2929 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2931 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2934 /* Translate internal representation of relocation info to BFD target
2938 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2940 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2942 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2943 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2944 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2945 reloc
->addend
= fixp
->fx_addnumber
;
2947 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2948 if (reloc
->howto
== NULL
)
2950 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2951 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2953 /* We don't have R_RISCV_8/16, but for this special case,
2954 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2958 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2959 _("cannot represent %s relocation in object file"),
2960 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2968 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2970 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2972 offsetT old_var
= fragp
->fr_var
;
2973 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2974 return fragp
->fr_var
- old_var
;
2980 /* Expand far branches to multi-instruction sequences. */
2983 md_convert_frag_branch (fragS
*fragp
)
2991 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2993 exp
.X_op
= O_symbol
;
2994 exp
.X_add_symbol
= fragp
->fr_symbol
;
2995 exp
.X_add_number
= fragp
->fr_offset
;
2997 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2999 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3001 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3005 /* Expand the RVC branch into a RISC-V one. */
3006 insn
= bfd_getl16 (buf
);
3007 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3008 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3010 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3011 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3012 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3013 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3014 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3015 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3018 bfd_putl32 (insn
, buf
);
3022 /* Invert the branch condition. Branch over the jump. */
3023 insn
= bfd_getl16 (buf
);
3024 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3025 insn
|= ENCODE_RVC_B_IMM (6);
3026 bfd_putl16 (insn
, buf
);
3031 /* Just keep the RVC branch. */
3032 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3033 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3034 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3035 2, &exp
, FALSE
, reloc
);
3044 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3047 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3049 /* Invert the branch condition. Branch over the jump. */
3050 insn
= bfd_getl32 (buf
);
3051 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3052 insn
|= ENCODE_SBTYPE_IMM (8);
3053 md_number_to_chars ((char *) buf
, insn
, 4);
3057 /* Jump to the target. */
3058 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3059 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3060 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3065 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3066 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3067 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3068 4, &exp
, FALSE
, reloc
);
3077 fixp
->fx_file
= fragp
->fr_file
;
3078 fixp
->fx_line
= fragp
->fr_line
;
3080 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3081 + fragp
->fr_fix
+ fragp
->fr_var
);
3083 fragp
->fr_fix
+= fragp
->fr_var
;
3086 /* Relax a machine dependent frag. This returns the amount by which
3087 the current size of the frag should change. */
3090 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3093 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3094 md_convert_frag_branch (fragp
);
3098 md_show_usage (FILE *stream
)
3100 fprintf (stream
, _("\
3102 -fpic generate position-independent code\n\
3103 -fno-pic don't generate position-independent code (default)\n\
3104 -march=ISA set the RISC-V architecture\n\
3105 -mabi=ABI set the RISC-V ABI\n\
3106 -mrelax enable relax (default)\n\
3107 -mno-relax disable relax\n\
3108 -march-attr generate RISC-V arch attribute\n\
3109 -mno-arch-attr don't generate RISC-V arch attribute\n\
3113 /* Standard calling conventions leave the CFA at SP on entry. */
3115 riscv_cfi_frame_initial_instructions (void)
3117 cfi_add_CFA_def_cfa_register (X_SP
);
3121 tc_riscv_regname_to_dw2regnum (char *regname
)
3125 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3128 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3131 /* CSRs are numbered 4096 -> 8191. */
3132 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3135 as_bad (_("unknown register `%s'"), regname
);
3140 riscv_elf_final_processing (void)
3142 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3145 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3146 since these directives break relaxation when used with symbol deltas. */
3149 s_riscv_leb128 (int sign
)
3152 char *save_in
= input_line_pointer
;
3155 if (exp
.X_op
!= O_constant
)
3156 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3157 demand_empty_rest_of_line ();
3159 input_line_pointer
= save_in
;
3160 return s_leb128 (sign
);
3163 /* Parse the .insn directive. */
3166 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3168 char *str
= input_line_pointer
;
3169 struct riscv_cl_insn insn
;
3170 expressionS imm_expr
;
3171 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3174 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3175 ++input_line_pointer
;
3177 save_c
= *input_line_pointer
;
3178 *input_line_pointer
= '\0';
3180 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3181 &imm_reloc
, insn_type_hash
);
3185 as_bad ("%s `%s'", error
, str
);
3189 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3190 append_insn (&insn
, &imm_expr
, imm_reloc
);
3193 *input_line_pointer
= save_c
;
3194 demand_empty_rest_of_line ();
3197 /* Update arch attributes. */
3200 riscv_write_out_arch_attr (void)
3202 const char *arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3204 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3206 xfree ((void *)arch_str
);
3209 /* Add the default contents for the .riscv.attributes section. */
3212 riscv_set_public_attributes (void)
3214 if (riscv_opts
.arch_attr
|| explicit_arch_attr
)
3215 /* Re-write arch attribute to normalize the arch string. */
3216 riscv_write_out_arch_attr ();
3219 /* Called after all assembly has been done. */
3224 riscv_set_public_attributes ();
3227 /* Given a symbolic attribute NAME, return the proper integer value.
3228 Returns -1 if the attribute is not known. */
3231 riscv_convert_symbolic_attribute (const char *name
)
3240 /* When you modify this table you should
3241 also modify the list in doc/c-riscv.texi. */
3242 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3246 T(priv_spec_revision
),
3247 T(unaligned_access
),
3257 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3258 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3259 return attribute_table
[i
].tag
;
3264 /* Parse a .attribute directive. */
3267 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3269 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3271 if (tag
== Tag_RISCV_arch
)
3273 unsigned old_xlen
= xlen
;
3275 explicit_arch_attr
= TRUE
;
3276 obj_attribute
*attr
;
3277 attr
= elf_known_obj_attributes_proc (stdoutput
);
3278 if (!start_assemble
)
3279 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3281 as_fatal (_(".attribute arch must set before any instructions"));
3283 if (old_xlen
!= xlen
)
3285 /* We must re-init bfd again if xlen is changed. */
3286 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3287 bfd_find_target (riscv_target_format (), stdoutput
);
3289 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3290 as_warn (_("Could not set architecture and machine"));
3295 /* Pseudo-op table. */
3297 static const pseudo_typeS riscv_pseudo_table
[] =
3299 /* RISC-V-specific pseudo-ops. */
3300 {"option", s_riscv_option
, 0},
3304 {"dtprelword", s_dtprel
, 4},
3305 {"dtpreldword", s_dtprel
, 8},
3307 {"uleb128", s_riscv_leb128
, 0},
3308 {"sleb128", s_riscv_leb128
, 1},
3309 {"insn", s_riscv_insn
, 0},
3310 {"attribute", s_riscv_attribute
, 0},
3316 riscv_pop_insert (void)
3318 extern void pop_insert (const pseudo_typeS
*);
3320 pop_insert (riscv_pseudo_table
);