1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 static const char default_arch
[] = DEFAULT_ARCH
;
68 static unsigned xlen
= 0; /* width of an x-register */
69 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
70 static bfd_boolean rve_abi
= FALSE
;
72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
75 static unsigned elf_flags
= 0;
77 /* This is the set of options which the .option pseudo-op may modify. */
79 struct riscv_set_options
81 int pic
; /* Generate position-independent code. */
82 int rvc
; /* Generate RVC code. */
83 int rve
; /* Generate RVE code. */
84 int relax
; /* Emit relocs the linker is allowed to relax. */
85 int arch_attr
; /* Emit arch attribute. */
86 int csr_check
; /* Enable the CSR checking. */
89 static struct riscv_set_options riscv_opts
=
95 DEFAULT_RISCV_ATTR
, /* arch_attr */
100 riscv_set_rvc (bfd_boolean rvc_value
)
103 elf_flags
|= EF_RISCV_RVC
;
105 riscv_opts
.rvc
= rvc_value
;
109 riscv_set_rve (bfd_boolean rve_value
)
111 riscv_opts
.rve
= rve_value
;
114 static riscv_subset_list_t riscv_subsets
;
117 riscv_subset_supports (const char *feature
)
119 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
122 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
126 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
130 case INSN_CLASS_I
: return riscv_subset_supports ("i");
131 case INSN_CLASS_C
: return riscv_subset_supports ("c");
132 case INSN_CLASS_A
: return riscv_subset_supports ("a");
133 case INSN_CLASS_M
: return riscv_subset_supports ("m");
134 case INSN_CLASS_F
: return riscv_subset_supports ("f");
135 case INSN_CLASS_D
: return riscv_subset_supports ("d");
136 case INSN_CLASS_D_AND_C
:
137 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
139 case INSN_CLASS_F_AND_C
:
140 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
142 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
145 as_fatal ("Unreachable");
150 /* Set which ISA and extensions are available. */
153 riscv_set_arch (const char *s
)
155 riscv_parse_subset_t rps
;
156 rps
.subset_list
= &riscv_subsets
;
157 rps
.error_handler
= as_fatal
;
160 riscv_release_subset_list (&riscv_subsets
);
161 riscv_parse_subset (&rps
, s
);
164 /* Handle of the OPCODE hash table. */
165 static struct hash_control
*op_hash
= NULL
;
167 /* Handle of the type of .insn hash table. */
168 static struct hash_control
*insn_type_hash
= NULL
;
170 /* This array holds the chars that always start a comment. If the
171 pre-processor is disabled, these aren't very useful */
172 const char comment_chars
[] = "#";
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that C style comments are always supported. */
181 const char line_comment_chars
[] = "#";
183 /* This array holds machine specific line separator characters. */
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point nums */
187 const char EXP_CHARS
[] = "eE";
189 /* Chars that mean this number is a floating point constant */
192 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
194 /* Indicate we are already assemble any instructions or not. */
195 static bfd_boolean start_assemble
= FALSE
;
197 /* Indicate arch attribute is explictly set. */
198 static bfd_boolean explicit_arch_attr
= FALSE
;
200 /* Macros for encoding relaxation state for RVC branches and far jumps. */
201 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
204 | ((uncond) ? 1 : 0) \
207 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
208 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
209 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
210 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
212 /* Is the given value a sign-extended 32-bit value? */
213 #define IS_SEXT_32BIT_NUM(x) \
214 (((x) &~ (offsetT) 0x7fffffff) == 0 \
215 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
217 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
218 #define IS_ZEXT_32BIT_NUM(x) \
219 (((x) &~ (offsetT) 0xffffffff) == 0 \
220 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
223 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
224 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
225 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
227 /* Determine if an instruction matches an opcode. */
228 #define OPCODE_MATCHES(OPCODE, OP) \
229 (((OPCODE) & MASK_##OP) == MATCH_##OP)
231 static char *expr_end
;
233 /* The default target format to use. */
236 riscv_target_format (void)
238 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
241 /* Return the length of instruction INSN. */
243 static inline unsigned int
244 insn_length (const struct riscv_cl_insn
*insn
)
246 return riscv_insn_length (insn
->insn_opcode
);
249 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
252 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
255 insn
->insn_opcode
= mo
->match
;
261 /* Install INSN at the location specified by its "frag" and "where" fields. */
264 install_insn (const struct riscv_cl_insn
*insn
)
266 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
267 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
270 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
271 and install the opcode in the new location. */
274 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
278 if (insn
->fixp
!= NULL
)
280 insn
->fixp
->fx_frag
= frag
;
281 insn
->fixp
->fx_where
= where
;
286 /* Add INSN to the end of the output. */
289 add_fixed_insn (struct riscv_cl_insn
*insn
)
291 char *f
= frag_more (insn_length (insn
));
292 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
296 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
297 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
299 frag_grow (max_chars
);
300 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
301 frag_var (rs_machine_dependent
, max_chars
, var
,
302 subtype
, symbol
, offset
, NULL
);
305 /* Compute the length of a branch sequence, and adjust the stored length
306 accordingly. If FRAGP is NULL, the worst-case length is returned. */
309 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
311 int jump
, rvc
, length
= 8;
316 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
317 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
318 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
320 /* Assume jumps are in range; the linker will catch any that aren't. */
321 length
= jump
? 4 : 8;
323 if (fragp
->fr_symbol
!= NULL
324 && S_IS_DEFINED (fragp
->fr_symbol
)
325 && !S_IS_WEAK (fragp
->fr_symbol
)
326 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
328 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
329 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
330 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
332 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
334 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
336 else if (!jump
&& rvc
)
341 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
346 /* Information about an opcode name, mnemonics and its value. */
353 /* List for all supported opcode name. */
354 static const struct opcode_name_t opcode_name_list
[] =
399 /* Hash table for lookup opcode name. */
400 static struct hash_control
*opcode_names_hash
= NULL
;
402 /* Initialization for hash table of opcode name. */
404 init_opcode_names_hash (void)
407 const struct opcode_name_t
*opcode
;
409 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
411 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
414 as_fatal (_("internal error: can't hash `%s': %s"),
415 opcode
->name
, retval
);
419 /* Find `s` is a valid opcode name or not,
420 return the opcode name info if found. */
421 static const struct opcode_name_t
*
422 opcode_name_lookup (char **s
)
426 struct opcode_name_t
*o
;
428 /* Find end of name. */
430 if (is_name_beginner (*e
))
432 while (is_part_of_name (*e
))
435 /* Terminate name. */
439 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
441 /* Advance to next token if one was recognized. */
459 static struct hash_control
*reg_names_hash
= NULL
;
460 static struct hash_control
*csr_extra_hash
= NULL
;
462 #define ENCODE_REG_HASH(cls, n) \
463 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
464 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
465 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
468 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
470 void *hash
= ENCODE_REG_HASH (class, n
);
471 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
474 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
478 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
482 for (i
= 0; i
< n
; i
++)
483 hash_reg_name (class, names
[i
], i
);
486 /* All RISC-V CSRs belong to one of these classes. */
493 CSR_CLASS_I_32
, /* rv32 only */
494 CSR_CLASS_F
, /* f-ext only */
497 /* This structure holds all restricted conditions for a CSR. */
499 struct riscv_csr_extra
501 /* Class to which this CSR belongs. Used to decide whether or
502 not this CSR is legal in the current -march context. */
503 enum riscv_csr_class csr_class
;
506 /* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */
509 riscv_init_csr_hashes (const char *name
,
511 enum riscv_csr_class
class)
513 struct riscv_csr_extra
*entry
= XNEW (struct riscv_csr_extra
);
514 entry
->csr_class
= class;
516 const char *hash_error
=
517 hash_insert (csr_extra_hash
, name
, (void *) entry
);
518 if (hash_error
!= NULL
)
520 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
522 /* Probably a memory allocation problem? Give up now. */
523 as_fatal (_("Broken assembler. No assembly attempted."));
526 hash_reg_name (RCLASS_CSR
, name
, address
);
529 /* Check wether the CSR is valid according to the ISA. */
532 riscv_csr_class_check (enum riscv_csr_class csr_class
)
536 case CSR_CLASS_I
: return riscv_subset_supports ("i");
537 case CSR_CLASS_F
: return riscv_subset_supports ("f");
539 return (xlen
== 32 && riscv_subset_supports ("i"));
546 /* If the CSR is defined, then we call `riscv_csr_class_check` to do the
547 further checking. Return FALSE if the CSR is not defined. Otherwise,
551 reg_csr_lookup_internal (const char *s
)
553 struct riscv_csr_extra
*r
=
554 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
559 /* We just report the warning when the CSR is invalid. */
560 if (!riscv_csr_class_check (r
->csr_class
))
561 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
567 reg_lookup_internal (const char *s
, enum reg_class
class)
569 void *r
= hash_find (reg_names_hash
, s
);
571 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
574 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
577 if (class == RCLASS_CSR
578 && riscv_opts
.csr_check
579 && !reg_csr_lookup_internal (s
))
582 return DECODE_REG_NUM (r
);
586 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
592 /* Find end of name. */
594 if (is_name_beginner (*e
))
596 while (is_part_of_name (*e
))
599 /* Terminate name. */
603 /* Look for the register. Advance to next token if one was recognized. */
604 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
614 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
616 const char *p
= strchr (*s
, ',');
617 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
622 for (i
= 0; i
< size
; i
++)
623 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
633 /* For consistency checking, verify that all bits are specified either
634 by the match/mask part of the instruction definition, or by the
637 `length` could be 0, 4 or 8, 0 for auto detection. */
639 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
641 const char *p
= opc
->args
;
643 insn_t used_bits
= opc
->mask
;
645 insn_t required_bits
;
648 insn_width
= 8 * riscv_insn_length (opc
->match
);
650 insn_width
= 8 * length
;
652 required_bits
= ~0ULL >> (64 - insn_width
);
654 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
656 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
657 opc
->name
, opc
->args
);
661 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
668 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
669 case 'c': break; /* RS1, constrained to equal sp */
670 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
671 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
672 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
673 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
674 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
675 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
676 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
677 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
678 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
679 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
680 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
681 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
682 case 'w': break; /* RS1S, constrained to equal RD */
683 case 'x': break; /* RS2S, constrained to equal RD */
684 case 'z': break; /* RS2S, contrained to be x0 */
685 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
686 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
687 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
688 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
689 case 'U': break; /* RS1, constrained to equal RD */
690 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
691 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
692 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
693 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
694 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
695 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
696 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
697 case 'F': /* funct */
700 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
701 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
702 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
703 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
705 as_bad (_("internal: bad RISC-V opcode"
706 " (unknown operand type `CF%c'): %s %s"),
707 c
, opc
->name
, opc
->args
);
712 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
713 c
, opc
->name
, opc
->args
);
720 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
721 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
723 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
724 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
725 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
727 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
728 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
729 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
730 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
731 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
732 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
733 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
734 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
735 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
736 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
737 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
739 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
740 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
741 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
742 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
743 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
749 case 'F': /* funct */
752 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
753 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
754 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
756 as_bad (_("internal: bad RISC-V opcode"
757 " (unknown operand type `F%c'): %s %s"),
758 c
, opc
->name
, opc
->args
);
762 case 'O': /* opcode */
765 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
766 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
768 as_bad (_("internal: bad RISC-V opcode"
769 " (unknown operand type `F%c'): %s %s"),
770 c
, opc
->name
, opc
->args
);
775 as_bad (_("internal: bad RISC-V opcode "
776 "(unknown operand type `%c'): %s %s"),
777 c
, opc
->name
, opc
->args
);
781 if (used_bits
!= required_bits
)
783 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
784 ~(unsigned long)(used_bits
& required_bits
),
785 opc
->name
, opc
->args
);
791 struct percent_op_match
794 bfd_reloc_code_real_type reloc
;
797 /* Common hash table initialization function for
798 instruction and .insn directive. */
799 static struct hash_control
*
800 init_opcode_hash (const struct riscv_opcode
*opcodes
,
801 bfd_boolean insn_directive_p
)
805 struct hash_control
*hash
= hash_new ();
806 while (opcodes
[i
].name
)
808 const char *name
= opcodes
[i
].name
;
809 const char *hash_error
=
810 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
812 if (hash_error
!= NULL
)
814 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
815 opcodes
[i
].name
, hash_error
);
816 /* Probably a memory allocation problem? Give up now. */
817 as_fatal (_("Broken assembler. No assembly attempted."));
822 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
824 if (insn_directive_p
)
825 length
= ((name
[0] == 'c') ? 2 : 4);
827 length
= 0; /* Let assembler determine the length. */
828 if (!validate_riscv_insn (&opcodes
[i
], length
))
829 as_fatal (_("Broken assembler. No assembly attempted."));
832 gas_assert (!insn_directive_p
);
835 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
841 /* This function is called once, at assembler startup time. It should set up
842 all the tables, etc. that the MD part of the assembler will need. */
847 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
849 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
850 as_warn (_("Could not set architecture and machine"));
852 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
853 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
855 reg_names_hash
= hash_new ();
856 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
857 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
858 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
859 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
860 /* Add "fp" as an alias for "s0". */
861 hash_reg_name (RCLASS_GPR
, "fp", 8);
863 /* Create and insert CSR hash tables. */
864 csr_extra_hash
= hash_new ();
865 #define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
866 #define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
867 #include "opcode/riscv-opc.h"
870 opcode_names_hash
= hash_new ();
871 init_opcode_names_hash ();
873 /* Set the default alignment for the text section. */
874 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
878 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
885 case BFD_RELOC_RISCV_HI20
:
886 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
888 case BFD_RELOC_RISCV_LO12_S
:
889 return ENCODE_STYPE_IMM (value
);
891 case BFD_RELOC_RISCV_LO12_I
:
892 return ENCODE_ITYPE_IMM (value
);
899 /* Output an instruction. IP is the instruction information.
900 ADDRESS_EXPR is an operand of the instruction to be used with
904 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
905 bfd_reloc_code_real_type reloc_type
)
907 dwarf2_emit_insn (0);
909 if (reloc_type
!= BFD_RELOC_UNUSED
)
911 reloc_howto_type
*howto
;
913 gas_assert (address_expr
);
914 if (reloc_type
== BFD_RELOC_12_PCREL
915 || reloc_type
== BFD_RELOC_RISCV_JMP
)
917 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
918 int best_case
= riscv_insn_length (ip
->insn_opcode
);
919 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
920 add_relaxed_insn (ip
, worst_case
, best_case
,
921 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
922 address_expr
->X_add_symbol
,
923 address_expr
->X_add_number
);
928 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
930 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
932 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
933 bfd_get_reloc_size (howto
),
934 address_expr
, FALSE
, reloc_type
);
936 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
943 /* We need to start a new frag after any instruction that can be
944 optimized away or compressed by the linker during relaxation, to prevent
945 the assembler from computing static offsets across such an instruction.
946 This is necessary to get correct EH info. */
947 if (reloc_type
== BFD_RELOC_RISCV_CALL
948 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
949 || reloc_type
== BFD_RELOC_RISCV_HI20
950 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
951 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
952 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
954 frag_wane (frag_now
);
959 /* Build an instruction created by a macro expansion. This is passed
960 a pointer to the count of instructions created so far, an
961 expression, the name of the instruction to build, an operand format
962 string, and corresponding arguments. */
965 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
967 const struct riscv_opcode
*mo
;
968 struct riscv_cl_insn insn
;
969 bfd_reloc_code_real_type r
;
972 va_start (args
, fmt
);
974 r
= BFD_RELOC_UNUSED
;
975 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
978 /* Find a non-RVC variant of the instruction. append_insn will compress
980 while (riscv_insn_length (mo
->match
) < 4)
982 gas_assert (strcmp (name
, mo
->name
) == 0);
984 create_insn (&insn
, mo
);
990 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
994 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
998 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1002 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1008 gas_assert (ep
!= NULL
);
1009 r
= va_arg (args
, int);
1017 as_fatal (_("internal error: invalid macro"));
1022 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1024 append_insn (&insn
, ep
, r
);
1027 /* Build an instruction created by a macro expansion. Like md_assemble but
1028 accept a printf-style format string and arguments. */
1031 md_assemblef (const char *format
, ...)
1037 va_start (ap
, format
);
1039 r
= vasprintf (&buf
, format
, ap
);
1042 as_fatal (_("internal error: vasprintf failed"));
1050 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1053 normalize_constant_expr (expressionS
*ex
)
1057 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1058 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1059 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1063 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1064 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1067 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1068 bfd_boolean maybe_csr
)
1070 if (ex
->X_op
== O_big
)
1071 as_bad (_("unsupported large constant"));
1072 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1073 as_bad (_("unknown CSR `%s'"),
1074 S_GET_NAME (ex
->X_add_symbol
));
1075 else if (ex
->X_op
!= O_constant
)
1076 as_bad (_("Instruction %s requires absolute expression"),
1078 normalize_constant_expr (ex
);
1082 make_internal_label (void)
1084 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1085 (valueT
) frag_now_fix (), frag_now
);
1088 /* Load an entry from the GOT. */
1090 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1091 const char *lo_insn
, const char *lo_pattern
,
1092 bfd_reloc_code_real_type hi_reloc
,
1093 bfd_reloc_code_real_type lo_reloc
)
1096 ep2
.X_op
= O_symbol
;
1097 ep2
.X_add_symbol
= make_internal_label ();
1098 ep2
.X_add_number
= 0;
1100 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1101 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1105 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1106 bfd_reloc_code_real_type hi_reloc
,
1107 bfd_reloc_code_real_type lo_reloc
)
1109 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1113 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1114 bfd_reloc_code_real_type hi_reloc
,
1115 bfd_reloc_code_real_type lo_reloc
)
1117 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1120 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1122 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1123 bfd_reloc_code_real_type reloc
)
1125 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1126 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1129 /* Load an integer constant into a register. */
1132 load_const (int reg
, expressionS
*ep
)
1134 int shift
= RISCV_IMM_BITS
;
1135 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1136 expressionS upper
= *ep
, lower
= *ep
;
1137 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1138 upper
.X_add_number
-= lower
.X_add_number
;
1140 if (ep
->X_op
!= O_constant
)
1142 as_bad (_("unsupported large constant"));
1146 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1148 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1149 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1152 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1153 load_const (reg
, &upper
);
1155 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1156 if (lower
.X_add_number
!= 0)
1157 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1158 lower
.X_add_number
);
1162 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1165 if (upper
.X_add_number
!= 0)
1167 /* Discard low part and zero-extend upper immediate. */
1168 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1170 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1174 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1175 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1176 lower
.X_add_number
);
1180 /* Expand RISC-V assembly macros into one or more instructions. */
1182 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1183 bfd_reloc_code_real_type
*imm_reloc
)
1185 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1186 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1187 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1188 int mask
= ip
->insn_mo
->mask
;
1193 load_const (rd
, imm_expr
);
1198 /* Load the address of a symbol into a register. */
1199 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1200 as_bad (_("offset too large"));
1202 if (imm_expr
->X_op
== O_constant
)
1203 load_const (rd
, imm_expr
);
1204 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1205 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1206 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1207 else /* Local PIC symbol, or any non-PIC symbol */
1208 pcrel_load (rd
, rd
, imm_expr
, "addi",
1209 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1213 pcrel_load (rd
, rd
, imm_expr
, "addi",
1214 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1218 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1219 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1223 pcrel_load (rd
, rd
, imm_expr
, "lb",
1224 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1228 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1229 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1233 pcrel_load (rd
, rd
, imm_expr
, "lh",
1234 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1238 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1239 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1243 pcrel_load (rd
, rd
, imm_expr
, "lw",
1244 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1248 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1249 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1253 pcrel_load (rd
, rd
, imm_expr
, "ld",
1254 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1258 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1259 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1263 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1264 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1268 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1269 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1273 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1274 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1278 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1279 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1283 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1284 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1288 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1289 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1293 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1294 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1298 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1302 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1307 static const struct percent_op_match percent_op_utype
[] =
1309 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1310 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1311 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1312 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1313 {"%hi", BFD_RELOC_RISCV_HI20
},
1317 static const struct percent_op_match percent_op_itype
[] =
1319 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1320 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1321 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1325 static const struct percent_op_match percent_op_stype
[] =
1327 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1328 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1329 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1333 static const struct percent_op_match percent_op_rtype
[] =
1335 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1339 static const struct percent_op_match percent_op_null
[] =
1344 /* Return true if *STR points to a relocation operator. When returning true,
1345 move *STR over the operator and store its relocation code in *RELOC.
1346 Leave both *STR and *RELOC alone when returning false. */
1349 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1350 const struct percent_op_match
*percent_op
)
1352 for ( ; percent_op
->str
; percent_op
++)
1353 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1355 int len
= strlen (percent_op
->str
);
1357 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1360 *str
+= strlen (percent_op
->str
);
1361 *reloc
= percent_op
->reloc
;
1363 /* Check whether the output BFD supports this relocation.
1364 If not, issue an error and fall back on something safe. */
1365 if (*reloc
!= BFD_RELOC_UNUSED
1366 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1368 as_bad ("relocation %s isn't supported by the current ABI",
1370 *reloc
= BFD_RELOC_UNUSED
;
1378 my_getExpression (expressionS
*ep
, char *str
)
1382 save_in
= input_line_pointer
;
1383 input_line_pointer
= str
;
1385 expr_end
= input_line_pointer
;
1386 input_line_pointer
= save_in
;
1389 /* Parse string STR as a 16-bit relocatable operand. Store the
1390 expression in *EP and the relocation, if any, in RELOC.
1391 Return the number of relocation operators used (0 or 1).
1393 On exit, EXPR_END points to the first character after the expression. */
1396 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1397 char *str
, const struct percent_op_match
*percent_op
)
1400 unsigned crux_depth
, str_depth
, regno
;
1403 /* First, check for integer registers. No callers can accept a reg, but
1404 we need to avoid accidentally creating a useless undefined symbol below,
1405 if this is an instruction pattern that can't match. A glibc build fails
1406 if this is removed. */
1407 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1409 ep
->X_op
= O_register
;
1410 ep
->X_add_number
= regno
;
1415 /* Search for the start of the main expression.
1416 End the loop with CRUX pointing to the start
1417 of the main expression and with CRUX_DEPTH containing the number
1418 of open brackets at that point. */
1425 crux_depth
= str_depth
;
1427 /* Skip over whitespace and brackets, keeping count of the number
1429 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1435 && parse_relocation (&str
, reloc
, percent_op
));
1437 my_getExpression (ep
, crux
);
1440 /* Match every open bracket. */
1441 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1446 as_bad ("unclosed '('");
1453 /* Parse opcode name, could be an mnemonics or number. */
1455 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1456 char *str
, const struct percent_op_match
*percent_op
)
1458 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1462 ep
->X_op
= O_constant
;
1463 ep
->X_add_number
= o
->val
;
1467 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1470 /* Detect and handle implicitly zero load-store offsets. For example,
1471 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1472 an implicit offset was detected. */
1475 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1477 /* Check whether there is only a single bracketed expression left.
1478 If so, it must be the base register and the constant must be zero. */
1479 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1481 ep
->X_op
= O_constant
;
1482 ep
->X_add_number
= 0;
1489 /* All RISC-V CSR instructions belong to one of these classes. */
1499 /* Return which CSR instruction is checking. */
1501 static enum csr_insn_type
1502 riscv_csr_insn_type (insn_t insn
)
1504 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1505 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1507 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1508 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1510 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1511 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1514 return INSN_NOT_CSR
;
1517 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1518 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1519 CSR address is 0x3. */
1522 riscv_csr_read_only_check (insn_t insn
)
1524 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1525 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1526 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1527 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1530 && (((csr_insn
== INSN_CSRRS
1531 || csr_insn
== INSN_CSRRC
)
1533 || csr_insn
== INSN_CSRRW
))
1539 /* This routine assembles an instruction into its binary format. As a
1540 side effect, it sets the global variable imm_reloc to the type of
1541 relocation to do if one of the operands is an address expression. */
1544 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1545 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1550 struct riscv_opcode
*insn
;
1555 const struct percent_op_match
*p
;
1556 const char *error
= "unrecognized opcode";
1557 /* Indicate we are assembling instruction with CSR. */
1558 bfd_boolean insn_with_csr
= FALSE
;
1560 /* Parse the name of the instruction. Terminate the string if whitespace
1561 is found so that hash_find only sees the name part of the string. */
1562 for (s
= str
; *s
!= '\0'; ++s
)
1570 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1573 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1575 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1578 if (!riscv_multi_subset_supports (insn
->insn_class
))
1581 create_insn (ip
, insn
);
1584 imm_expr
->X_op
= O_absent
;
1585 *imm_reloc
= BFD_RELOC_UNUSED
;
1586 p
= percent_op_itype
;
1588 for (args
= insn
->args
;; ++args
)
1590 s
+= strspn (s
, " \t");
1593 case '\0': /* End of args. */
1594 if (insn
->pinfo
!= INSN_MACRO
)
1596 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1599 /* For .insn, insn->match and insn->mask are 0. */
1600 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1606 /* Check if we write a read-only CSR by the CSR
1609 && riscv_opts
.csr_check
1610 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1612 /* Restore the character in advance, since we want to
1613 report the detailed warning message here. */
1615 *(argsStart
- 1) = save_c
;
1616 as_warn (_("Read-only CSR is written `%s'"), str
);
1617 insn_with_csr
= FALSE
;
1622 /* Successful assembly. */
1624 insn_with_csr
= FALSE
;
1630 case 's': /* RS1 x8-x15 */
1631 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1632 || !(regno
>= 8 && regno
<= 15))
1634 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1636 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1637 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1638 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1641 case 't': /* RS2 x8-x15 */
1642 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1643 || !(regno
>= 8 && regno
<= 15))
1645 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1647 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1648 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1649 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1652 case 'U': /* RS1, constrained to equal RD. */
1653 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1654 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1658 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1660 INSERT_OPERAND (CRS2
, *ip
, regno
);
1662 case 'c': /* RS1, constrained to equal sp. */
1663 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1667 case 'z': /* RS2, contrained to equal x0. */
1668 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1673 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1674 || imm_expr
->X_op
!= O_constant
1675 || imm_expr
->X_add_number
<= 0
1676 || imm_expr
->X_add_number
>= 64)
1678 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1681 imm_expr
->X_op
= O_absent
;
1684 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1685 || imm_expr
->X_op
!= O_constant
1686 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1687 || imm_expr
->X_add_number
<= 0
1688 || imm_expr
->X_add_number
>= 32)
1690 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1693 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1694 || imm_expr
->X_op
!= O_constant
1695 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1696 || imm_expr
->X_add_number
< 0
1697 || imm_expr
->X_add_number
>= 256)
1699 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1702 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1703 || imm_expr
->X_op
!= O_constant
1704 || imm_expr
->X_add_number
== 0
1705 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1707 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1710 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1711 || imm_expr
->X_op
!= O_constant
1712 || imm_expr
->X_add_number
== 0
1713 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1715 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1718 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1720 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1721 || imm_expr
->X_op
!= O_constant
1722 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1724 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1727 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1729 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1730 || imm_expr
->X_op
!= O_constant
1731 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1733 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1736 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1738 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1739 || imm_expr
->X_op
!= O_constant
1740 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1743 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1746 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1748 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1749 || imm_expr
->X_op
!= O_constant
1750 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1753 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1756 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1757 || imm_expr
->X_op
!= O_constant
1758 /* C.addiw, c.li, and c.andi allow zero immediate.
1759 C.addi allows zero immediate as hint. Otherwise this
1761 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1763 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1766 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1767 || imm_expr
->X_op
!= O_constant
1768 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1769 || imm_expr
->X_add_number
== 0)
1772 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1775 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1776 || imm_expr
->X_op
!= O_constant
1777 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1778 || imm_expr
->X_add_number
== 0)
1781 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1784 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1786 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1787 || imm_expr
->X_op
!= O_constant
1788 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1791 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1794 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1796 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1797 || imm_expr
->X_op
!= O_constant
1798 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1801 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1804 p
= percent_op_utype
;
1805 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1808 if (imm_expr
->X_op
!= O_constant
1809 || imm_expr
->X_add_number
<= 0
1810 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1811 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1812 && (imm_expr
->X_add_number
<
1813 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1815 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1818 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1819 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1820 || ((int32_t)imm_expr
->X_add_number
1821 != imm_expr
->X_add_number
))
1823 imm_expr
->X_add_number
=
1824 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1830 case 'S': /* Floating-point RS1 x8-x15. */
1831 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1832 || !(regno
>= 8 && regno
<= 15))
1834 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1836 case 'D': /* Floating-point RS2 x8-x15. */
1837 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1838 || !(regno
>= 8 && regno
<= 15))
1840 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1842 case 'T': /* Floating-point RS2. */
1843 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1845 INSERT_OPERAND (CRS2
, *ip
, regno
);
1851 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1852 || imm_expr
->X_op
!= O_constant
1853 || imm_expr
->X_add_number
< 0
1854 || imm_expr
->X_add_number
>= 64)
1856 as_bad (_("bad value for funct6 field, "
1857 "value must be 0...64"));
1861 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1862 imm_expr
->X_op
= O_absent
;
1866 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1867 || imm_expr
->X_op
!= O_constant
1868 || imm_expr
->X_add_number
< 0
1869 || imm_expr
->X_add_number
>= 16)
1871 as_bad (_("bad value for funct4 field, "
1872 "value must be 0...15"));
1876 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1877 imm_expr
->X_op
= O_absent
;
1881 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1882 || imm_expr
->X_op
!= O_constant
1883 || imm_expr
->X_add_number
< 0
1884 || imm_expr
->X_add_number
>= 8)
1886 as_bad (_("bad value for funct3 field, "
1887 "value must be 0...7"));
1890 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1891 imm_expr
->X_op
= O_absent
;
1895 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1896 || imm_expr
->X_op
!= O_constant
1897 || imm_expr
->X_add_number
< 0
1898 || imm_expr
->X_add_number
>= 4)
1900 as_bad (_("bad value for funct2 field, "
1901 "value must be 0...3"));
1904 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1905 imm_expr
->X_op
= O_absent
;
1909 as_bad (_("bad compressed FUNCT field"
1910 " specifier 'CF%c'\n"),
1916 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1935 case '<': /* Shift amount, 0 - 31. */
1936 my_getExpression (imm_expr
, s
);
1937 check_absolute_expr (ip
, imm_expr
, FALSE
);
1938 if ((unsigned long) imm_expr
->X_add_number
> 31)
1939 as_bad (_("Improper shift amount (%lu)"),
1940 (unsigned long) imm_expr
->X_add_number
);
1941 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1942 imm_expr
->X_op
= O_absent
;
1946 case '>': /* Shift amount, 0 - (XLEN-1). */
1947 my_getExpression (imm_expr
, s
);
1948 check_absolute_expr (ip
, imm_expr
, FALSE
);
1949 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1950 as_bad (_("Improper shift amount (%lu)"),
1951 (unsigned long) imm_expr
->X_add_number
);
1952 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1953 imm_expr
->X_op
= O_absent
;
1957 case 'Z': /* CSRRxI immediate. */
1958 my_getExpression (imm_expr
, s
);
1959 check_absolute_expr (ip
, imm_expr
, FALSE
);
1960 if ((unsigned long) imm_expr
->X_add_number
> 31)
1961 as_bad (_("Improper CSRxI immediate (%lu)"),
1962 (unsigned long) imm_expr
->X_add_number
);
1963 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1964 imm_expr
->X_op
= O_absent
;
1968 case 'E': /* Control register. */
1969 insn_with_csr
= TRUE
;
1970 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1971 INSERT_OPERAND (CSR
, *ip
, regno
);
1974 my_getExpression (imm_expr
, s
);
1975 check_absolute_expr (ip
, imm_expr
, TRUE
);
1976 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1977 as_bad (_("Improper CSR address (%lu)"),
1978 (unsigned long) imm_expr
->X_add_number
);
1979 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1980 imm_expr
->X_op
= O_absent
;
1985 case 'm': /* Rounding mode. */
1986 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1988 INSERT_OPERAND (RM
, *ip
, regno
);
1994 case 'Q': /* Fence predecessor/successor. */
1995 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1999 INSERT_OPERAND (PRED
, *ip
, regno
);
2001 INSERT_OPERAND (SUCC
, *ip
, regno
);
2006 case 'd': /* Destination register. */
2007 case 's': /* Source register. */
2008 case 't': /* Target register. */
2009 case 'r': /* rs3. */
2010 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2016 /* Now that we have assembled one operand, we use the args
2017 string to figure out where it goes in the instruction. */
2021 INSERT_OPERAND (RS1
, *ip
, regno
);
2024 INSERT_OPERAND (RD
, *ip
, regno
);
2027 INSERT_OPERAND (RS2
, *ip
, regno
);
2030 INSERT_OPERAND (RS3
, *ip
, regno
);
2037 case 'D': /* Floating point rd. */
2038 case 'S': /* Floating point rs1. */
2039 case 'T': /* Floating point rs2. */
2040 case 'U': /* Floating point rs1 and rs2. */
2041 case 'R': /* Floating point rs3. */
2042 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2050 INSERT_OPERAND (RD
, *ip
, regno
);
2053 INSERT_OPERAND (RS1
, *ip
, regno
);
2056 INSERT_OPERAND (RS1
, *ip
, regno
);
2059 INSERT_OPERAND (RS2
, *ip
, regno
);
2062 INSERT_OPERAND (RS3
, *ip
, regno
);
2071 my_getExpression (imm_expr
, s
);
2072 if (imm_expr
->X_op
!= O_big
2073 && imm_expr
->X_op
!= O_constant
)
2075 normalize_constant_expr (imm_expr
);
2080 my_getExpression (imm_expr
, s
);
2081 normalize_constant_expr (imm_expr
);
2082 /* The 'A' format specifier must be a symbol. */
2083 if (imm_expr
->X_op
!= O_symbol
)
2085 *imm_reloc
= BFD_RELOC_32
;
2090 my_getExpression (imm_expr
, s
);
2091 normalize_constant_expr (imm_expr
);
2092 /* The 'B' format specifier must be a symbol or a constant. */
2093 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2095 if (imm_expr
->X_op
== O_symbol
)
2096 *imm_reloc
= BFD_RELOC_32
;
2100 case 'j': /* Sign-extended immediate. */
2101 p
= percent_op_itype
;
2102 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2104 case 'q': /* Store displacement. */
2105 p
= percent_op_stype
;
2106 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2108 case 'o': /* Load displacement. */
2109 p
= percent_op_itype
;
2110 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2112 case '1': /* 4-operand add, must be %tprel_add. */
2113 p
= percent_op_rtype
;
2115 case '0': /* AMO "displacement," which must be zero. */
2116 p
= percent_op_null
;
2118 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2121 /* If this value won't fit into a 16 bit offset, then go
2122 find a macro that will generate the 32 bit offset
2124 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2126 normalize_constant_expr (imm_expr
);
2127 if (imm_expr
->X_op
!= O_constant
2128 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2130 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2131 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2138 case 'p': /* PC-relative offset. */
2140 *imm_reloc
= BFD_RELOC_12_PCREL
;
2141 my_getExpression (imm_expr
, s
);
2145 case 'u': /* Upper 20 bits. */
2146 p
= percent_op_utype
;
2147 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2149 if (imm_expr
->X_op
!= O_constant
)
2152 if (imm_expr
->X_add_number
< 0
2153 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2154 as_bad (_("lui expression not in range 0..1048575"));
2156 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2157 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2162 case 'a': /* 20-bit PC-relative offset. */
2164 my_getExpression (imm_expr
, s
);
2166 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2170 my_getExpression (imm_expr
, s
);
2172 if (strcmp (s
, "@plt") == 0)
2174 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2178 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2184 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2185 || imm_expr
->X_op
!= O_constant
2186 || imm_expr
->X_add_number
< 0
2187 || imm_expr
->X_add_number
>= 128
2188 || (imm_expr
->X_add_number
& 0x3) != 3)
2190 as_bad (_("bad value for opcode field, "
2191 "value must be 0...127 and "
2192 "lower 2 bits must be 0x3"));
2196 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2197 imm_expr
->X_op
= O_absent
;
2201 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2202 || imm_expr
->X_op
!= O_constant
2203 || imm_expr
->X_add_number
< 0
2204 || imm_expr
->X_add_number
>= 3)
2206 as_bad (_("bad value for opcode field, "
2207 "value must be 0...2"));
2211 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2212 imm_expr
->X_op
= O_absent
;
2216 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2224 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2225 || imm_expr
->X_op
!= O_constant
2226 || imm_expr
->X_add_number
< 0
2227 || imm_expr
->X_add_number
>= 128)
2229 as_bad (_("bad value for funct7 field, "
2230 "value must be 0...127"));
2234 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2235 imm_expr
->X_op
= O_absent
;
2239 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2240 || imm_expr
->X_op
!= O_constant
2241 || imm_expr
->X_add_number
< 0
2242 || imm_expr
->X_add_number
>= 8)
2244 as_bad (_("bad value for funct3 field, "
2245 "value must be 0...7"));
2249 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2250 imm_expr
->X_op
= O_absent
;
2254 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2255 || imm_expr
->X_op
!= O_constant
2256 || imm_expr
->X_add_number
< 0
2257 || imm_expr
->X_add_number
>= 4)
2259 as_bad (_("bad value for funct2 field, "
2260 "value must be 0...3"));
2264 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2265 imm_expr
->X_op
= O_absent
;
2270 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2275 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2276 || imm_expr
->X_op
!= O_constant
2277 || imm_expr
->X_add_number
!= 0)
2280 imm_expr
->X_op
= O_absent
;
2284 as_fatal (_("internal error: bad argument type %c"), *args
);
2289 error
= _("illegal operands");
2290 insn_with_csr
= FALSE
;
2294 /* Restore the character we might have clobbered above. */
2296 *(argsStart
- 1) = save_c
;
2302 md_assemble (char *str
)
2304 struct riscv_cl_insn insn
;
2305 expressionS imm_expr
;
2306 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2308 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2310 start_assemble
= TRUE
;
2314 as_bad ("%s `%s'", error
, str
);
2318 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2319 macro (&insn
, &imm_expr
, &imm_reloc
);
2321 append_insn (&insn
, &imm_expr
, imm_reloc
);
2325 md_atof (int type
, char *litP
, int *sizeP
)
2327 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2331 md_number_to_chars (char *buf
, valueT val
, int n
)
2333 number_to_chars_littleendian (buf
, val
, n
);
2336 const char *md_shortopts
= "O::g::G:";
2340 OPTION_MARCH
= OPTION_MD_BASE
,
2347 OPTION_NO_ARCH_ATTR
,
2349 OPTION_NO_CSR_CHECK
,
2353 struct option md_longopts
[] =
2355 {"march", required_argument
, NULL
, OPTION_MARCH
},
2356 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2357 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2358 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2359 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2360 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2361 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2362 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2363 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2364 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2365 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2367 {NULL
, no_argument
, NULL
, 0}
2369 size_t md_longopts_size
= sizeof (md_longopts
);
2372 FLOAT_ABI_DEFAULT
= -1,
2378 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2381 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2383 abi_xlen
= new_xlen
;
2384 float_abi
= new_float_abi
;
2389 md_parse_option (int c
, const char *arg
)
2394 riscv_set_arch (arg
);
2398 riscv_opts
.pic
= FALSE
;
2402 riscv_opts
.pic
= TRUE
;
2406 if (strcmp (arg
, "ilp32") == 0)
2407 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2408 else if (strcmp (arg
, "ilp32e") == 0)
2409 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2410 else if (strcmp (arg
, "ilp32f") == 0)
2411 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2412 else if (strcmp (arg
, "ilp32d") == 0)
2413 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2414 else if (strcmp (arg
, "ilp32q") == 0)
2415 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2416 else if (strcmp (arg
, "lp64") == 0)
2417 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2418 else if (strcmp (arg
, "lp64f") == 0)
2419 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2420 else if (strcmp (arg
, "lp64d") == 0)
2421 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2422 else if (strcmp (arg
, "lp64q") == 0)
2423 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2429 riscv_opts
.relax
= TRUE
;
2432 case OPTION_NO_RELAX
:
2433 riscv_opts
.relax
= FALSE
;
2436 case OPTION_ARCH_ATTR
:
2437 riscv_opts
.arch_attr
= TRUE
;
2440 case OPTION_NO_ARCH_ATTR
:
2441 riscv_opts
.arch_attr
= FALSE
;
2444 case OPTION_CSR_CHECK
:
2445 riscv_opts
.csr_check
= TRUE
;
2448 case OPTION_NO_CSR_CHECK
:
2449 riscv_opts
.csr_check
= FALSE
;
2460 riscv_after_parse_args (void)
2464 if (strcmp (default_arch
, "riscv32") == 0)
2466 else if (strcmp (default_arch
, "riscv64") == 0)
2469 as_bad ("unknown default architecture `%s'", default_arch
);
2472 if (riscv_subsets
.head
== NULL
)
2473 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2475 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2476 riscv_set_rvc (FALSE
);
2477 if (riscv_subset_supports ("c"))
2478 riscv_set_rvc (TRUE
);
2480 /* Enable RVE if specified by the -march option. */
2481 riscv_set_rve (FALSE
);
2482 if (riscv_subset_supports ("e"))
2483 riscv_set_rve (TRUE
);
2485 /* Infer ABI from ISA if not specified on command line. */
2488 else if (abi_xlen
> xlen
)
2489 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2490 else if (abi_xlen
< xlen
)
2491 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2493 if (float_abi
== FLOAT_ABI_DEFAULT
)
2495 riscv_subset_t
*subset
;
2497 /* Assume soft-float unless D extension is present. */
2498 float_abi
= FLOAT_ABI_SOFT
;
2500 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2502 if (strcasecmp (subset
->name
, "D") == 0)
2503 float_abi
= FLOAT_ABI_DOUBLE
;
2504 if (strcasecmp (subset
->name
, "Q") == 0)
2505 float_abi
= FLOAT_ABI_QUAD
;
2510 elf_flags
|= EF_RISCV_RVE
;
2512 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2513 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2515 /* If the CIE to be produced has not been overridden on the command line,
2516 then produce version 3 by default. This allows us to use the full
2517 range of registers in a .cfi_return_column directive. */
2518 if (flag_dwarf_cie_version
== -1)
2519 flag_dwarf_cie_version
= 3;
2523 md_pcrel_from (fixS
*fixP
)
2525 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2528 /* Apply a fixup to the object file. */
2531 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2533 unsigned int subtype
;
2534 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2535 bfd_boolean relaxable
= FALSE
;
2539 /* Remember value for tc_gen_reloc. */
2540 fixP
->fx_addnumber
= *valP
;
2542 switch (fixP
->fx_r_type
)
2544 case BFD_RELOC_RISCV_HI20
:
2545 case BFD_RELOC_RISCV_LO12_I
:
2546 case BFD_RELOC_RISCV_LO12_S
:
2547 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2548 | bfd_getl32 (buf
), buf
);
2549 if (fixP
->fx_addsy
== NULL
)
2550 fixP
->fx_done
= TRUE
;
2554 case BFD_RELOC_RISCV_GOT_HI20
:
2555 case BFD_RELOC_RISCV_ADD8
:
2556 case BFD_RELOC_RISCV_ADD16
:
2557 case BFD_RELOC_RISCV_ADD32
:
2558 case BFD_RELOC_RISCV_ADD64
:
2559 case BFD_RELOC_RISCV_SUB6
:
2560 case BFD_RELOC_RISCV_SUB8
:
2561 case BFD_RELOC_RISCV_SUB16
:
2562 case BFD_RELOC_RISCV_SUB32
:
2563 case BFD_RELOC_RISCV_SUB64
:
2564 case BFD_RELOC_RISCV_RELAX
:
2567 case BFD_RELOC_RISCV_TPREL_HI20
:
2568 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2569 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2570 case BFD_RELOC_RISCV_TPREL_ADD
:
2574 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2575 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2576 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2577 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2578 if (fixP
->fx_addsy
!= NULL
)
2579 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2582 _("TLS relocation against a constant"));
2586 /* Use pc-relative relocation for FDE initial location.
2587 The symbol address in .eh_frame may be adjusted in
2588 _bfd_elf_discard_section_eh_frame, and the content of
2589 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2590 Therefore, we cannot insert a relocation whose addend symbol is
2591 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2592 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2593 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2594 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2595 && S_GET_VALUE (fixP
->fx_subsy
)
2596 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2598 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2599 fixP
->fx_subsy
= NULL
;
2606 case BFD_RELOC_RISCV_CFA
:
2607 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2609 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2610 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2611 fixP
->fx_next
->fx_subsy
= NULL
;
2612 fixP
->fx_next
->fx_offset
= 0;
2613 fixP
->fx_subsy
= NULL
;
2615 switch (fixP
->fx_r_type
)
2618 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2619 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2623 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2624 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2628 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2629 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2633 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2634 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2637 case BFD_RELOC_RISCV_CFA
:
2638 /* Load the byte to get the subtype. */
2639 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2640 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2643 case DW_CFA_advance_loc1
:
2644 fixP
->fx_where
= loc
+ 1;
2645 fixP
->fx_next
->fx_where
= loc
+ 1;
2646 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2647 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2650 case DW_CFA_advance_loc2
:
2652 fixP
->fx_next
->fx_size
= 2;
2653 fixP
->fx_where
= loc
+ 1;
2654 fixP
->fx_next
->fx_where
= loc
+ 1;
2655 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2656 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2659 case DW_CFA_advance_loc4
:
2661 fixP
->fx_next
->fx_size
= 4;
2662 fixP
->fx_where
= loc
;
2663 fixP
->fx_next
->fx_where
= loc
;
2664 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2665 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2669 if (subtype
< 0x80 && (subtype
& 0x40))
2671 /* DW_CFA_advance_loc */
2672 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2673 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2674 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2675 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2678 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2684 /* This case is unreachable. */
2691 /* If we are deleting this reloc entry, we must fill in the
2692 value now. This can happen if we have a .word which is not
2693 resolved when it appears but is later defined. */
2694 if (fixP
->fx_addsy
== NULL
)
2696 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2697 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2702 case BFD_RELOC_RISCV_JMP
:
2705 /* Fill in a tentative value to improve objdump readability. */
2706 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2707 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2708 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2712 case BFD_RELOC_12_PCREL
:
2715 /* Fill in a tentative value to improve objdump readability. */
2716 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2717 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2718 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2722 case BFD_RELOC_RISCV_RVC_BRANCH
:
2725 /* Fill in a tentative value to improve objdump readability. */
2726 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2727 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2728 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2732 case BFD_RELOC_RISCV_RVC_JUMP
:
2735 /* Fill in a tentative value to improve objdump readability. */
2736 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2737 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2738 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2742 case BFD_RELOC_RISCV_CALL
:
2743 case BFD_RELOC_RISCV_CALL_PLT
:
2747 case BFD_RELOC_RISCV_PCREL_HI20
:
2748 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2749 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2750 relaxable
= riscv_opts
.relax
;
2753 case BFD_RELOC_RISCV_ALIGN
:
2757 /* We ignore generic BFD relocations we don't know about. */
2758 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2759 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2762 if (fixP
->fx_subsy
!= NULL
)
2763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2764 _("unsupported symbol subtraction"));
2766 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2767 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2769 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2770 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2771 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2775 /* Because the value of .cfi_remember_state may changed after relaxation,
2776 we insert a fix to relocate it again in link-time. */
2779 riscv_pre_output_hook (void)
2781 const frchainS
*frch
;
2784 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2785 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2789 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2791 if (frag
->fr_type
== rs_cfa
)
2794 expressionS
*symval
;
2796 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2797 exp
.X_op
= O_subtract
;
2798 exp
.X_add_symbol
= symval
->X_add_symbol
;
2799 exp
.X_add_number
= 0;
2800 exp
.X_op_symbol
= symval
->X_op_symbol
;
2802 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2803 BFD_RELOC_RISCV_CFA
);
2810 /* This structure is used to hold a stack of .option values. */
2812 struct riscv_option_stack
2814 struct riscv_option_stack
*next
;
2815 struct riscv_set_options options
;
2818 static struct riscv_option_stack
*riscv_opts_stack
;
2820 /* Handle the .option pseudo-op. */
2823 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2825 char *name
= input_line_pointer
, ch
;
2827 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2828 ++input_line_pointer
;
2829 ch
= *input_line_pointer
;
2830 *input_line_pointer
= '\0';
2832 if (strcmp (name
, "rvc") == 0)
2833 riscv_set_rvc (TRUE
);
2834 else if (strcmp (name
, "norvc") == 0)
2835 riscv_set_rvc (FALSE
);
2836 else if (strcmp (name
, "pic") == 0)
2837 riscv_opts
.pic
= TRUE
;
2838 else if (strcmp (name
, "nopic") == 0)
2839 riscv_opts
.pic
= FALSE
;
2840 else if (strcmp (name
, "relax") == 0)
2841 riscv_opts
.relax
= TRUE
;
2842 else if (strcmp (name
, "norelax") == 0)
2843 riscv_opts
.relax
= FALSE
;
2844 else if (strcmp (name
, "csr-check") == 0)
2845 riscv_opts
.csr_check
= TRUE
;
2846 else if (strcmp (name
, "no-csr-check") == 0)
2847 riscv_opts
.csr_check
= FALSE
;
2848 else if (strcmp (name
, "push") == 0)
2850 struct riscv_option_stack
*s
;
2852 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2853 s
->next
= riscv_opts_stack
;
2854 s
->options
= riscv_opts
;
2855 riscv_opts_stack
= s
;
2857 else if (strcmp (name
, "pop") == 0)
2859 struct riscv_option_stack
*s
;
2861 s
= riscv_opts_stack
;
2863 as_bad (_(".option pop with no .option push"));
2866 riscv_opts
= s
->options
;
2867 riscv_opts_stack
= s
->next
;
2873 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2875 *input_line_pointer
= ch
;
2876 demand_empty_rest_of_line ();
2879 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2880 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2881 use in DWARF debug information. */
2884 s_dtprel (int bytes
)
2891 if (ex
.X_op
!= O_symbol
)
2893 as_bad (_("Unsupported use of %s"), (bytes
== 8
2896 ignore_rest_of_line ();
2899 p
= frag_more (bytes
);
2900 md_number_to_chars (p
, 0, bytes
);
2901 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2903 ? BFD_RELOC_RISCV_TLS_DTPREL64
2904 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2906 demand_empty_rest_of_line ();
2909 /* Handle the .bss pseudo-op. */
2912 s_bss (int ignore ATTRIBUTE_UNUSED
)
2914 subseg_set (bss_section
, 0);
2915 demand_empty_rest_of_line ();
2919 riscv_make_nops (char *buf
, bfd_vma bytes
)
2923 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2924 means we are not within a valid instruction sequence. It is thus safe
2925 to use a zero byte, even though that is not a valid instruction. */
2929 /* Use at most one 2-byte NOP. */
2930 if ((bytes
- i
) % 4 == 2)
2932 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2936 /* Fill the remainder with 4-byte NOPs. */
2937 for ( ; i
< bytes
; i
+= 4)
2938 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2941 /* Called from md_do_align. Used to create an alignment frag in a
2942 code section by emitting a worst-case NOP sequence that the linker
2943 will later relax to the correct number of NOPs. We can't compute
2944 the correct alignment now because of other linker relaxations. */
2947 riscv_frag_align_code (int n
)
2949 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2950 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2951 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2955 /* If we are moving to a smaller alignment than the instruction size, then no
2956 alignment is required. */
2957 if (bytes
<= insn_alignment
)
2960 /* When not relaxing, riscv_handle_align handles code alignment. */
2961 if (!riscv_opts
.relax
)
2964 nops
= frag_more (worst_case_bytes
);
2966 ex
.X_op
= O_constant
;
2967 ex
.X_add_number
= worst_case_bytes
;
2969 riscv_make_nops (nops
, worst_case_bytes
);
2971 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2972 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2977 /* Implement HANDLE_ALIGN. */
2980 riscv_handle_align (fragS
*fragP
)
2982 switch (fragP
->fr_type
)
2985 /* When relaxing, riscv_frag_align_code handles code alignment. */
2986 if (!riscv_opts
.relax
)
2988 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2989 - fragP
->fr_address
- fragP
->fr_fix
);
2990 /* We have 4 byte uncompressed nops. */
2991 bfd_signed_vma size
= 4;
2992 bfd_signed_vma excess
= bytes
% size
;
2993 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2998 /* Insert zeros or compressed nops to get 4 byte alignment. */
3001 riscv_make_nops (p
, excess
);
3002 fragP
->fr_fix
+= excess
;
3006 /* Insert variable number of 4 byte uncompressed nops. */
3007 riscv_make_nops (p
, size
);
3008 fragP
->fr_var
= size
;
3018 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3020 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3023 /* Translate internal representation of relocation info to BFD target
3027 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3029 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3031 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3032 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3033 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3034 reloc
->addend
= fixp
->fx_addnumber
;
3036 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3037 if (reloc
->howto
== NULL
)
3039 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3040 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3042 /* We don't have R_RISCV_8/16, but for this special case,
3043 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3047 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3048 _("cannot represent %s relocation in object file"),
3049 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3057 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3059 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3061 offsetT old_var
= fragp
->fr_var
;
3062 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3063 return fragp
->fr_var
- old_var
;
3069 /* Expand far branches to multi-instruction sequences. */
3072 md_convert_frag_branch (fragS
*fragp
)
3080 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3082 exp
.X_op
= O_symbol
;
3083 exp
.X_add_symbol
= fragp
->fr_symbol
;
3084 exp
.X_add_number
= fragp
->fr_offset
;
3086 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3088 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3090 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3094 /* Expand the RVC branch into a RISC-V one. */
3095 insn
= bfd_getl16 (buf
);
3096 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3097 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3099 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3100 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3101 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3102 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3103 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3104 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3107 bfd_putl32 (insn
, buf
);
3111 /* Invert the branch condition. Branch over the jump. */
3112 insn
= bfd_getl16 (buf
);
3113 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3114 insn
|= ENCODE_RVC_B_IMM (6);
3115 bfd_putl16 (insn
, buf
);
3120 /* Just keep the RVC branch. */
3121 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3122 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3123 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3124 2, &exp
, FALSE
, reloc
);
3133 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3136 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3138 /* Invert the branch condition. Branch over the jump. */
3139 insn
= bfd_getl32 (buf
);
3140 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3141 insn
|= ENCODE_SBTYPE_IMM (8);
3142 md_number_to_chars ((char *) buf
, insn
, 4);
3146 /* Jump to the target. */
3147 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3148 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3149 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3154 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3155 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3156 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3157 4, &exp
, FALSE
, reloc
);
3166 fixp
->fx_file
= fragp
->fr_file
;
3167 fixp
->fx_line
= fragp
->fr_line
;
3169 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3170 + fragp
->fr_fix
+ fragp
->fr_var
);
3172 fragp
->fr_fix
+= fragp
->fr_var
;
3175 /* Relax a machine dependent frag. This returns the amount by which
3176 the current size of the frag should change. */
3179 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3182 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3183 md_convert_frag_branch (fragp
);
3187 md_show_usage (FILE *stream
)
3189 fprintf (stream
, _("\
3191 -fpic generate position-independent code\n\
3192 -fno-pic don't generate position-independent code (default)\n\
3193 -march=ISA set the RISC-V architecture\n\
3194 -mabi=ABI set the RISC-V ABI\n\
3195 -mrelax enable relax (default)\n\
3196 -mno-relax disable relax\n\
3197 -march-attr generate RISC-V arch attribute\n\
3198 -mno-arch-attr don't generate RISC-V arch attribute\n\
3202 /* Standard calling conventions leave the CFA at SP on entry. */
3204 riscv_cfi_frame_initial_instructions (void)
3206 cfi_add_CFA_def_cfa_register (X_SP
);
3210 tc_riscv_regname_to_dw2regnum (char *regname
)
3214 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3217 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3220 /* CSRs are numbered 4096 -> 8191. */
3221 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3224 as_bad (_("unknown register `%s'"), regname
);
3229 riscv_elf_final_processing (void)
3231 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3234 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3235 since these directives break relaxation when used with symbol deltas. */
3238 s_riscv_leb128 (int sign
)
3241 char *save_in
= input_line_pointer
;
3244 if (exp
.X_op
!= O_constant
)
3245 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3246 demand_empty_rest_of_line ();
3248 input_line_pointer
= save_in
;
3249 return s_leb128 (sign
);
3252 /* Parse the .insn directive. */
3255 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3257 char *str
= input_line_pointer
;
3258 struct riscv_cl_insn insn
;
3259 expressionS imm_expr
;
3260 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3263 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3264 ++input_line_pointer
;
3266 save_c
= *input_line_pointer
;
3267 *input_line_pointer
= '\0';
3269 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3270 &imm_reloc
, insn_type_hash
);
3274 as_bad ("%s `%s'", error
, str
);
3278 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3279 append_insn (&insn
, &imm_expr
, imm_reloc
);
3282 *input_line_pointer
= save_c
;
3283 demand_empty_rest_of_line ();
3286 /* Update arch attributes. */
3289 riscv_write_out_arch_attr (void)
3291 const char *arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3293 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3295 xfree ((void *)arch_str
);
3298 /* Add the default contents for the .riscv.attributes section. */
3301 riscv_set_public_attributes (void)
3303 if (riscv_opts
.arch_attr
|| explicit_arch_attr
)
3304 /* Re-write arch attribute to normalize the arch string. */
3305 riscv_write_out_arch_attr ();
3308 /* Called after all assembly has been done. */
3313 riscv_set_public_attributes ();
3316 /* Given a symbolic attribute NAME, return the proper integer value.
3317 Returns -1 if the attribute is not known. */
3320 riscv_convert_symbolic_attribute (const char *name
)
3329 /* When you modify this table you should
3330 also modify the list in doc/c-riscv.texi. */
3331 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3335 T(priv_spec_revision
),
3336 T(unaligned_access
),
3346 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3347 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3348 return attribute_table
[i
].tag
;
3353 /* Parse a .attribute directive. */
3356 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3358 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3360 if (tag
== Tag_RISCV_arch
)
3362 unsigned old_xlen
= xlen
;
3364 explicit_arch_attr
= TRUE
;
3365 obj_attribute
*attr
;
3366 attr
= elf_known_obj_attributes_proc (stdoutput
);
3367 if (!start_assemble
)
3368 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3370 as_fatal (_(".attribute arch must set before any instructions"));
3372 if (old_xlen
!= xlen
)
3374 /* We must re-init bfd again if xlen is changed. */
3375 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3376 bfd_find_target (riscv_target_format (), stdoutput
);
3378 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3379 as_warn (_("Could not set architecture and machine"));
3384 /* Pseudo-op table. */
3386 static const pseudo_typeS riscv_pseudo_table
[] =
3388 /* RISC-V-specific pseudo-ops. */
3389 {"option", s_riscv_option
, 0},
3393 {"dtprelword", s_dtprel
, 4},
3394 {"dtpreldword", s_dtprel
, 8},
3396 {"uleb128", s_riscv_leb128
, 0},
3397 {"sleb128", s_riscv_leb128
, 1},
3398 {"insn", s_riscv_insn
, 0},
3399 {"attribute", s_riscv_attribute
, 0},
3405 riscv_pop_insert (void)
3407 extern void pop_insert (const pseudo_typeS
*);
3409 pop_insert (riscv_pseudo_table
);