1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
96 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
98 static unsigned elf_flags
= 0;
100 /* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
104 riscv_set_default_isa_spec (const char *s
)
106 enum riscv_isa_spec_class
class;
107 if (!riscv_get_isa_spec_class (s
, &class))
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s
);
114 default_isa_spec
= class;
118 /* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
124 riscv_set_default_priv_spec (const char *s
)
126 enum riscv_priv_spec_class
class;
127 unsigned major
, minor
, revision
;
130 /* Find the corresponding priv spec class. */
131 if (riscv_get_priv_spec_class (s
, &class))
133 default_priv_spec
= class;
139 as_bad (_("Unknown default privilege spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s
);
144 /* Try to set the default_priv_spec according to the priv attributes. */
145 attr
= elf_known_obj_attributes_proc (stdoutput
);
146 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
147 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
148 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
150 if (riscv_get_priv_spec_class_from_numbers (major
,
155 /* The priv attributes setting 0.0.0 is meaningless. We should have set
156 the default_priv_spec by md_parse_option and riscv_after_parse_args,
157 so just skip the following setting. */
158 if (class == PRIV_SPEC_CLASS_NONE
)
161 default_priv_spec
= class;
165 /* Still can not find the priv spec class. */
166 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
167 "privilege attributes"), major
, minor
, revision
);
171 /* This is the set of options which the .option pseudo-op may modify. */
173 struct riscv_set_options
175 int pic
; /* Generate position-independent code. */
176 int rvc
; /* Generate RVC code. */
177 int rve
; /* Generate RVE code. */
178 int relax
; /* Emit relocs the linker is allowed to relax. */
179 int arch_attr
; /* Emit arch attribute. */
180 int csr_check
; /* Enable the CSR checking. */
183 static struct riscv_set_options riscv_opts
=
189 DEFAULT_RISCV_ATTR
, /* arch_attr */
194 riscv_set_rvc (bfd_boolean rvc_value
)
197 elf_flags
|= EF_RISCV_RVC
;
199 riscv_opts
.rvc
= rvc_value
;
203 riscv_set_rve (bfd_boolean rve_value
)
205 riscv_opts
.rve
= rve_value
;
208 static riscv_subset_list_t riscv_subsets
;
211 riscv_subset_supports (const char *feature
)
213 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
216 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
220 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
224 case INSN_CLASS_I
: return riscv_subset_supports ("i");
225 case INSN_CLASS_C
: return riscv_subset_supports ("c");
226 case INSN_CLASS_A
: return riscv_subset_supports ("a");
227 case INSN_CLASS_M
: return riscv_subset_supports ("m");
228 case INSN_CLASS_F
: return riscv_subset_supports ("f");
229 case INSN_CLASS_D
: return riscv_subset_supports ("d");
230 case INSN_CLASS_D_AND_C
:
231 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
233 case INSN_CLASS_F_AND_C
:
234 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
236 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
239 as_fatal ("Unreachable");
244 /* Handle of the extension with version hash table. */
245 static htab_t ext_version_hash
= NULL
;
248 init_ext_version_hash (const struct riscv_ext_version
*table
)
251 htab_t hash
= str_htab_create ();
253 while (table
[i
].name
)
255 const char *name
= table
[i
].name
;
256 str_hash_insert (hash
, name
, (void *) &table
[i
]);
260 && strcmp (table
[i
].name
, name
) == 0)
268 riscv_get_default_ext_version (const char *name
,
269 unsigned int *major_version
,
270 unsigned int *minor_version
)
272 struct riscv_ext_version
*ext
;
277 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
280 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
283 && strcmp (ext
->name
, name
) == 0)
285 if (ext
->isa_spec_class
== default_isa_spec
)
287 *major_version
= ext
->major_version
;
288 *minor_version
= ext
->minor_version
;
295 /* Set which ISA and extensions are available. */
298 riscv_set_arch (const char *s
)
300 riscv_parse_subset_t rps
;
301 rps
.subset_list
= &riscv_subsets
;
302 rps
.error_handler
= as_fatal
;
304 rps
.get_default_version
= riscv_get_default_ext_version
;
309 riscv_release_subset_list (&riscv_subsets
);
310 riscv_parse_subset (&rps
, s
);
313 /* Handle of the OPCODE hash table. */
314 static htab_t op_hash
= NULL
;
316 /* Handle of the type of .insn hash table. */
317 static htab_t insn_type_hash
= NULL
;
319 /* This array holds the chars that always start a comment. If the
320 pre-processor is disabled, these aren't very useful */
321 const char comment_chars
[] = "#";
323 /* This array holds the chars that only start a comment at the beginning of
324 a line. If the line seems to have the form '# 123 filename'
325 .line and .file directives will appear in the pre-processed output */
326 /* Note that input_file.c hand checks for '#' at the beginning of the
327 first line of the input file. This is because the compiler outputs
328 #NO_APP at the beginning of its output. */
329 /* Also note that C style comments are always supported. */
330 const char line_comment_chars
[] = "#";
332 /* This array holds machine specific line separator characters. */
333 const char line_separator_chars
[] = ";";
335 /* Chars that can be used to separate mant from exp in floating point nums */
336 const char EXP_CHARS
[] = "eE";
338 /* Chars that mean this number is a floating point constant */
341 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
343 /* Indicate we are already assemble any instructions or not. */
344 static bfd_boolean start_assemble
= FALSE
;
346 /* Indicate ELF attributes are explictly set. */
347 static bfd_boolean explicit_attr
= FALSE
;
349 /* Indicate CSR or priv instructions are explictly used. */
350 static bfd_boolean explicit_priv_attr
= FALSE
;
352 /* Macros for encoding relaxation state for RVC branches and far jumps. */
353 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
356 | ((uncond) ? 1 : 0) \
359 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
360 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
361 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
362 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
364 /* Is the given value a sign-extended 32-bit value? */
365 #define IS_SEXT_32BIT_NUM(x) \
366 (((x) &~ (offsetT) 0x7fffffff) == 0 \
367 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
369 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
370 #define IS_ZEXT_32BIT_NUM(x) \
371 (((x) &~ (offsetT) 0xffffffff) == 0 \
372 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
374 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
375 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
376 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
377 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
379 /* Determine if an instruction matches an opcode. */
380 #define OPCODE_MATCHES(OPCODE, OP) \
381 (((OPCODE) & MASK_##OP) == MATCH_##OP)
383 static char *expr_end
;
385 /* The default target format to use. */
388 riscv_target_format (void)
390 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
393 /* Return the length of instruction INSN. */
395 static inline unsigned int
396 insn_length (const struct riscv_cl_insn
*insn
)
398 return riscv_insn_length (insn
->insn_opcode
);
401 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
404 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
407 insn
->insn_opcode
= mo
->match
;
413 /* Install INSN at the location specified by its "frag" and "where" fields. */
416 install_insn (const struct riscv_cl_insn
*insn
)
418 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
419 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
422 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
423 and install the opcode in the new location. */
426 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
430 if (insn
->fixp
!= NULL
)
432 insn
->fixp
->fx_frag
= frag
;
433 insn
->fixp
->fx_where
= where
;
438 /* Add INSN to the end of the output. */
441 add_fixed_insn (struct riscv_cl_insn
*insn
)
443 char *f
= frag_more (insn_length (insn
));
444 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
448 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
449 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
451 frag_grow (max_chars
);
452 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
453 frag_var (rs_machine_dependent
, max_chars
, var
,
454 subtype
, symbol
, offset
, NULL
);
457 /* Compute the length of a branch sequence, and adjust the stored length
458 accordingly. If FRAGP is NULL, the worst-case length is returned. */
461 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
463 int jump
, rvc
, length
= 8;
468 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
469 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
470 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
472 /* Assume jumps are in range; the linker will catch any that aren't. */
473 length
= jump
? 4 : 8;
475 if (fragp
->fr_symbol
!= NULL
476 && S_IS_DEFINED (fragp
->fr_symbol
)
477 && !S_IS_WEAK (fragp
->fr_symbol
)
478 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
480 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
481 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
482 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
484 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
486 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
488 else if (!jump
&& rvc
)
493 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
498 /* Information about an opcode name, mnemonics and its value. */
505 /* List for all supported opcode name. */
506 static const struct opcode_name_t opcode_name_list
[] =
551 /* Hash table for lookup opcode name. */
552 static htab_t opcode_names_hash
= NULL
;
554 /* Initialization for hash table of opcode name. */
556 init_opcode_names_hash (void)
558 const struct opcode_name_t
*opcode
;
560 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
561 str_hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
564 /* Find `s` is a valid opcode name or not,
565 return the opcode name info if found. */
566 static const struct opcode_name_t
*
567 opcode_name_lookup (char **s
)
571 struct opcode_name_t
*o
;
573 /* Find end of name. */
575 if (is_name_beginner (*e
))
577 while (is_part_of_name (*e
))
580 /* Terminate name. */
584 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
586 /* Advance to next token if one was recognized. */
605 static htab_t reg_names_hash
= NULL
;
606 static htab_t csr_extra_hash
= NULL
;
608 #define ENCODE_REG_HASH(cls, n) \
609 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
610 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
611 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
614 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
616 void *hash
= ENCODE_REG_HASH (class, n
);
617 str_hash_insert (reg_names_hash
, name
, hash
);
621 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
625 for (i
= 0; i
< n
; i
++)
626 hash_reg_name (class, names
[i
], i
);
629 /* Init hash table csr_extra_hash to handle CSR. */
631 riscv_init_csr_hash (const char *name
,
633 enum riscv_csr_class
class,
634 enum riscv_priv_spec_class define_version
,
635 enum riscv_priv_spec_class abort_version
)
637 struct riscv_csr_extra
*entry
, *pre_entry
;
638 bfd_boolean need_enrty
= TRUE
;
641 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
642 while (need_enrty
&& entry
!= NULL
)
644 if (entry
->csr_class
== class
645 && entry
->address
== address
646 && entry
->define_version
== define_version
647 && entry
->abort_version
== abort_version
)
653 /* Duplicate setting for the CSR, just return and do nothing. */
657 entry
= XNEW (struct riscv_csr_extra
);
658 entry
->csr_class
= class;
659 entry
->address
= address
;
660 entry
->define_version
= define_version
;
661 entry
->abort_version
= abort_version
;
664 /* If the CSR hasn't been inserted in the hash table, then insert it.
665 Otherwise, attach the extra information to the entry which is already
666 in the hash table. */
667 if (pre_entry
== NULL
)
668 str_hash_insert (csr_extra_hash
, name
, (void *) entry
);
670 pre_entry
->next
= entry
;
673 /* Return the suitable CSR address after checking the ISA dependency and
674 priv spec versions. */
677 riscv_csr_address (const char *csr_name
,
678 struct riscv_csr_extra
*entry
)
680 struct riscv_csr_extra
*saved_entry
= entry
;
681 enum riscv_csr_class csr_class
= entry
->csr_class
;
682 bfd_boolean need_check_version
= TRUE
;
683 bfd_boolean result
= TRUE
;
688 result
= riscv_subset_supports ("i");
691 result
= (xlen
== 32 && riscv_subset_supports ("i"));
694 result
= riscv_subset_supports ("f");
695 need_check_version
= FALSE
;
697 case CSR_CLASS_DEBUG
:
698 need_check_version
= FALSE
;
701 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
704 /* Don't report the ISA conflict when -mcsr-check isn't set. */
705 if (riscv_opts
.csr_check
&& !result
)
706 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name
);
708 while (entry
!= NULL
)
710 if (!need_check_version
711 || (default_priv_spec
>= entry
->define_version
712 && default_priv_spec
< entry
->abort_version
))
714 /* Find the suitable CSR according to the specific version. */
715 return entry
->address
;
720 /* We can not find the suitable CSR address according to the privilege
721 version. Therefore, we use the last defined value. Report the warning
722 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
723 otherwise, you may get the unexpected CSR address. */
724 if (riscv_opts
.csr_check
)
726 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
728 if (priv_name
!= NULL
)
729 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
730 csr_name
, priv_name
);
733 return saved_entry
->address
;
736 /* Once the CSR is defined, including the old privilege spec, then we call
737 riscv_csr_class_check and riscv_csr_version_check to do the further checking
738 and get the corresponding address. Return -1 if the CSR is never been
739 defined. Otherwise, return the address. */
742 reg_csr_lookup_internal (const char *s
)
744 struct riscv_csr_extra
*r
=
745 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
750 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
751 the CSR was defined, but isn't allowed for the current ISA setting or
752 the privilege spec. If the CSR is never been defined, then assembler
753 will regard it as a "Unknown CSR" and report error. If user use number
754 to set the CSR, but over the range (> 0xfff), then assembler will report
755 "Improper CSR" error for it. */
756 return riscv_csr_address (s
, r
);
760 reg_lookup_internal (const char *s
, enum reg_class
class)
764 if (class == RCLASS_CSR
)
765 return reg_csr_lookup_internal (s
);
767 r
= str_hash_find (reg_names_hash
, s
);
768 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
771 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
774 return DECODE_REG_NUM (r
);
778 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
784 /* Find end of name. */
786 if (is_name_beginner (*e
))
788 while (is_part_of_name (*e
))
791 /* Terminate name. */
795 /* Look for the register. Advance to next token if one was recognized. */
796 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
806 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
808 const char *p
= strchr (*s
, ',');
809 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
814 for (i
= 0; i
< size
; i
++)
815 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
825 /* For consistency checking, verify that all bits are specified either
826 by the match/mask part of the instruction definition, or by the
829 `length` could be 0, 4 or 8, 0 for auto detection. */
831 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
833 const char *p
= opc
->args
;
835 insn_t used_bits
= opc
->mask
;
837 insn_t required_bits
;
840 insn_width
= 8 * riscv_insn_length (opc
->match
);
842 insn_width
= 8 * length
;
844 required_bits
= ~0ULL >> (64 - insn_width
);
846 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
848 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
849 opc
->name
, opc
->args
);
853 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
860 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
861 case 'c': break; /* RS1, constrained to equal sp */
862 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
863 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
864 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
865 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
866 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
867 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
868 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
869 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
870 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
871 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
872 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
873 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
874 case 'w': break; /* RS1S, constrained to equal RD */
875 case 'x': break; /* RS2S, constrained to equal RD */
876 case 'z': break; /* RS2S, contrained to be x0 */
877 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
878 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
879 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
880 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
881 case 'U': break; /* RS1, constrained to equal RD */
882 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
883 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
884 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
885 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
886 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
887 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
888 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
889 case 'F': /* funct */
892 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
893 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
894 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
895 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
897 as_bad (_("internal: bad RISC-V opcode"
898 " (unknown operand type `CF%c'): %s %s"),
899 c
, opc
->name
, opc
->args
);
904 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
905 c
, opc
->name
, opc
->args
);
912 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
913 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
915 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
916 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
917 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
919 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
920 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
921 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
922 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
923 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
924 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
925 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
926 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
927 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
928 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
929 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
931 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
932 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
933 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
934 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
935 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
941 case 'F': /* funct */
944 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
945 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
946 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
948 as_bad (_("internal: bad RISC-V opcode"
949 " (unknown operand type `F%c'): %s %s"),
950 c
, opc
->name
, opc
->args
);
954 case 'O': /* opcode */
957 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
958 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
960 as_bad (_("internal: bad RISC-V opcode"
961 " (unknown operand type `F%c'): %s %s"),
962 c
, opc
->name
, opc
->args
);
967 as_bad (_("internal: bad RISC-V opcode "
968 "(unknown operand type `%c'): %s %s"),
969 c
, opc
->name
, opc
->args
);
973 if (used_bits
!= required_bits
)
975 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
976 ~(unsigned long)(used_bits
& required_bits
),
977 opc
->name
, opc
->args
);
983 struct percent_op_match
986 bfd_reloc_code_real_type reloc
;
989 /* Common hash table initialization function for
990 instruction and .insn directive. */
992 init_opcode_hash (const struct riscv_opcode
*opcodes
,
993 bfd_boolean insn_directive_p
)
997 htab_t hash
= str_htab_create ();
998 while (opcodes
[i
].name
)
1000 const char *name
= opcodes
[i
].name
;
1001 str_hash_insert (hash
, name
, (void *) &opcodes
[i
]);
1005 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1007 if (insn_directive_p
)
1008 length
= ((name
[0] == 'c') ? 2 : 4);
1010 length
= 0; /* Let assembler determine the length. */
1011 if (!validate_riscv_insn (&opcodes
[i
], length
))
1012 as_fatal (_("Broken assembler. No assembly attempted."));
1015 gas_assert (!insn_directive_p
);
1018 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1024 /* This function is called once, at assembler startup time. It should set up
1025 all the tables, etc. that the MD part of the assembler will need. */
1030 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1032 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1033 as_warn (_("Could not set architecture and machine"));
1035 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1036 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1038 reg_names_hash
= str_htab_create ();
1039 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1040 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1041 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1042 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1043 /* Add "fp" as an alias for "s0". */
1044 hash_reg_name (RCLASS_GPR
, "fp", 8);
1046 /* Create and insert CSR hash tables. */
1047 csr_extra_hash
= str_htab_create ();
1048 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1049 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1050 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1051 DECLARE_CSR(name, num, class, define_version, abort_version);
1052 #include "opcode/riscv-opc.h"
1055 opcode_names_hash
= str_htab_create ();
1056 init_opcode_names_hash ();
1058 /* Set the default alignment for the text section. */
1059 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1063 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1070 case BFD_RELOC_RISCV_HI20
:
1071 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1073 case BFD_RELOC_RISCV_LO12_S
:
1074 return ENCODE_STYPE_IMM (value
);
1076 case BFD_RELOC_RISCV_LO12_I
:
1077 return ENCODE_ITYPE_IMM (value
);
1084 /* Output an instruction. IP is the instruction information.
1085 ADDRESS_EXPR is an operand of the instruction to be used with
1089 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1090 bfd_reloc_code_real_type reloc_type
)
1092 dwarf2_emit_insn (0);
1094 if (reloc_type
!= BFD_RELOC_UNUSED
)
1096 reloc_howto_type
*howto
;
1098 gas_assert (address_expr
);
1099 if (reloc_type
== BFD_RELOC_12_PCREL
1100 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1102 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1103 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1104 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1105 add_relaxed_insn (ip
, worst_case
, best_case
,
1106 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1107 address_expr
->X_add_symbol
,
1108 address_expr
->X_add_number
);
1113 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1115 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1117 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1118 bfd_get_reloc_size (howto
),
1119 address_expr
, FALSE
, reloc_type
);
1121 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1125 add_fixed_insn (ip
);
1128 /* We need to start a new frag after any instruction that can be
1129 optimized away or compressed by the linker during relaxation, to prevent
1130 the assembler from computing static offsets across such an instruction.
1131 This is necessary to get correct EH info. */
1132 if (reloc_type
== BFD_RELOC_RISCV_CALL
1133 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
1134 || reloc_type
== BFD_RELOC_RISCV_HI20
1135 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1136 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1137 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1139 frag_wane (frag_now
);
1144 /* Build an instruction created by a macro expansion. This is passed
1145 a pointer to the count of instructions created so far, an
1146 expression, the name of the instruction to build, an operand format
1147 string, and corresponding arguments. */
1150 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1152 const struct riscv_opcode
*mo
;
1153 struct riscv_cl_insn insn
;
1154 bfd_reloc_code_real_type r
;
1157 va_start (args
, fmt
);
1159 r
= BFD_RELOC_UNUSED
;
1160 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1163 /* Find a non-RVC variant of the instruction. append_insn will compress
1165 while (riscv_insn_length (mo
->match
) < 4)
1167 gas_assert (strcmp (name
, mo
->name
) == 0);
1169 create_insn (&insn
, mo
);
1175 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1179 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1183 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1187 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1193 gas_assert (ep
!= NULL
);
1194 r
= va_arg (args
, int);
1202 as_fatal (_("internal error: invalid macro"));
1207 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1209 append_insn (&insn
, ep
, r
);
1212 /* Build an instruction created by a macro expansion. Like md_assemble but
1213 accept a printf-style format string and arguments. */
1216 md_assemblef (const char *format
, ...)
1222 va_start (ap
, format
);
1224 r
= vasprintf (&buf
, format
, ap
);
1227 as_fatal (_("internal error: vasprintf failed"));
1235 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1238 normalize_constant_expr (expressionS
*ex
)
1242 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1243 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1244 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1248 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1249 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1252 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1253 bfd_boolean maybe_csr
)
1255 if (ex
->X_op
== O_big
)
1256 as_bad (_("unsupported large constant"));
1257 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1258 as_bad (_("unknown CSR `%s'"),
1259 S_GET_NAME (ex
->X_add_symbol
));
1260 else if (ex
->X_op
!= O_constant
)
1261 as_bad (_("Instruction %s requires absolute expression"),
1263 normalize_constant_expr (ex
);
1267 make_internal_label (void)
1269 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1273 /* Load an entry from the GOT. */
1275 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1276 const char *lo_insn
, const char *lo_pattern
,
1277 bfd_reloc_code_real_type hi_reloc
,
1278 bfd_reloc_code_real_type lo_reloc
)
1281 ep2
.X_op
= O_symbol
;
1282 ep2
.X_add_symbol
= make_internal_label ();
1283 ep2
.X_add_number
= 0;
1285 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1286 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1290 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1291 bfd_reloc_code_real_type hi_reloc
,
1292 bfd_reloc_code_real_type lo_reloc
)
1294 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1298 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1299 bfd_reloc_code_real_type hi_reloc
,
1300 bfd_reloc_code_real_type lo_reloc
)
1302 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1305 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1307 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1308 bfd_reloc_code_real_type reloc
)
1310 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1311 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1314 /* Load an integer constant into a register. */
1317 load_const (int reg
, expressionS
*ep
)
1319 int shift
= RISCV_IMM_BITS
;
1320 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1321 expressionS upper
= *ep
, lower
= *ep
;
1322 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1323 upper
.X_add_number
-= lower
.X_add_number
;
1325 if (ep
->X_op
!= O_constant
)
1327 as_bad (_("unsupported large constant"));
1331 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1333 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1334 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1337 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1338 load_const (reg
, &upper
);
1340 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1341 if (lower
.X_add_number
!= 0)
1342 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1343 lower
.X_add_number
);
1347 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1350 if (upper
.X_add_number
!= 0)
1352 /* Discard low part and zero-extend upper immediate. */
1353 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1355 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1359 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1360 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1361 lower
.X_add_number
);
1365 /* Expand RISC-V assembly macros into one or more instructions. */
1367 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1368 bfd_reloc_code_real_type
*imm_reloc
)
1370 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1371 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1372 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1373 int mask
= ip
->insn_mo
->mask
;
1378 load_const (rd
, imm_expr
);
1383 /* Load the address of a symbol into a register. */
1384 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1385 as_bad (_("offset too large"));
1387 if (imm_expr
->X_op
== O_constant
)
1388 load_const (rd
, imm_expr
);
1389 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1390 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1391 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1392 else /* Local PIC symbol, or any non-PIC symbol */
1393 pcrel_load (rd
, rd
, imm_expr
, "addi",
1394 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1398 pcrel_load (rd
, rd
, imm_expr
, "addi",
1399 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1403 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1404 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1408 pcrel_load (rd
, rd
, imm_expr
, "lb",
1409 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1413 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1414 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1418 pcrel_load (rd
, rd
, imm_expr
, "lh",
1419 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1423 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1424 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1428 pcrel_load (rd
, rd
, imm_expr
, "lw",
1429 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1433 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1434 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1438 pcrel_load (rd
, rd
, imm_expr
, "ld",
1439 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1443 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1444 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1448 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1449 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1453 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1454 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1458 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1459 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1463 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1464 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1468 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1469 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1473 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1474 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1478 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1479 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1483 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1487 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1492 static const struct percent_op_match percent_op_utype
[] =
1494 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1495 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1496 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1497 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1498 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1499 {"%hi", BFD_RELOC_RISCV_HI20
},
1503 static const struct percent_op_match percent_op_itype
[] =
1505 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1506 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1507 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1511 static const struct percent_op_match percent_op_stype
[] =
1513 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1514 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1515 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1519 static const struct percent_op_match percent_op_rtype
[] =
1521 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1525 static const struct percent_op_match percent_op_null
[] =
1530 /* Return true if *STR points to a relocation operator. When returning true,
1531 move *STR over the operator and store its relocation code in *RELOC.
1532 Leave both *STR and *RELOC alone when returning false. */
1535 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1536 const struct percent_op_match
*percent_op
)
1538 for ( ; percent_op
->str
; percent_op
++)
1539 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1541 int len
= strlen (percent_op
->str
);
1543 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1546 *str
+= strlen (percent_op
->str
);
1547 *reloc
= percent_op
->reloc
;
1549 /* Check whether the output BFD supports this relocation.
1550 If not, issue an error and fall back on something safe. */
1551 if (*reloc
!= BFD_RELOC_UNUSED
1552 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1554 as_bad ("relocation %s isn't supported by the current ABI",
1556 *reloc
= BFD_RELOC_UNUSED
;
1564 my_getExpression (expressionS
*ep
, char *str
)
1568 save_in
= input_line_pointer
;
1569 input_line_pointer
= str
;
1571 expr_end
= input_line_pointer
;
1572 input_line_pointer
= save_in
;
1575 /* Parse string STR as a 16-bit relocatable operand. Store the
1576 expression in *EP and the relocation, if any, in RELOC.
1577 Return the number of relocation operators used (0 or 1).
1579 On exit, EXPR_END points to the first character after the expression. */
1582 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1583 char *str
, const struct percent_op_match
*percent_op
)
1586 unsigned crux_depth
, str_depth
, regno
;
1589 /* First, check for integer registers. No callers can accept a reg, but
1590 we need to avoid accidentally creating a useless undefined symbol below,
1591 if this is an instruction pattern that can't match. A glibc build fails
1592 if this is removed. */
1593 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1595 ep
->X_op
= O_register
;
1596 ep
->X_add_number
= regno
;
1601 /* Search for the start of the main expression.
1602 End the loop with CRUX pointing to the start
1603 of the main expression and with CRUX_DEPTH containing the number
1604 of open brackets at that point. */
1611 crux_depth
= str_depth
;
1613 /* Skip over whitespace and brackets, keeping count of the number
1615 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1621 && parse_relocation (&str
, reloc
, percent_op
));
1623 my_getExpression (ep
, crux
);
1626 /* Match every open bracket. */
1627 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1632 as_bad ("unclosed '('");
1639 /* Parse opcode name, could be an mnemonics or number. */
1641 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1642 char *str
, const struct percent_op_match
*percent_op
)
1644 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1648 ep
->X_op
= O_constant
;
1649 ep
->X_add_number
= o
->val
;
1653 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1656 /* Detect and handle implicitly zero load-store offsets. For example,
1657 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1658 an implicit offset was detected. */
1661 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1663 /* Check whether there is only a single bracketed expression left.
1664 If so, it must be the base register and the constant must be zero. */
1665 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1667 ep
->X_op
= O_constant
;
1668 ep
->X_add_number
= 0;
1675 /* All RISC-V CSR instructions belong to one of these classes. */
1685 /* Return which CSR instruction is checking. */
1687 static enum csr_insn_type
1688 riscv_csr_insn_type (insn_t insn
)
1690 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1691 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1693 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1694 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1696 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1697 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1700 return INSN_NOT_CSR
;
1703 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1704 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1705 CSR address is 0x3. */
1708 riscv_csr_read_only_check (insn_t insn
)
1710 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1711 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1712 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1713 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1716 && (((csr_insn
== INSN_CSRRS
1717 || csr_insn
== INSN_CSRRC
)
1719 || csr_insn
== INSN_CSRRW
))
1725 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1727 uret is actually a N-ext instruction. So it is better to regard it as
1728 an user instruction rather than the priv instruction.
1730 hret is used to return from traps in H-mode. H-mode is removed since
1731 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1732 Therefore, hret should be controlled by the hypervisor spec rather than
1733 priv spec in the future.
1735 dret is defined in the debug spec, so it should be checked in the future,
1739 riscv_is_priv_insn (insn_t insn
)
1741 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1742 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1743 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1744 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1745 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1746 check it here to keep the compatible. Maybe we should issue warning
1747 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1748 We already have a similar check for CSR, but not yet for instructions.
1749 It would be good if we could check the spec versions both for CSR and
1750 instructions, but not here. */
1751 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1754 /* This routine assembles an instruction into its binary format. As a
1755 side effect, it sets the global variable imm_reloc to the type of
1756 relocation to do if one of the operands is an address expression. */
1759 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1760 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1765 struct riscv_opcode
*insn
;
1770 const struct percent_op_match
*p
;
1771 const char *error
= "unrecognized opcode";
1772 /* Indicate we are assembling instruction with CSR. */
1773 bfd_boolean insn_with_csr
= FALSE
;
1775 /* Parse the name of the instruction. Terminate the string if whitespace
1776 is found so that str_hash_find only sees the name part of the string. */
1777 for (s
= str
; *s
!= '\0'; ++s
)
1785 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1788 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1790 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1793 if (!riscv_multi_subset_supports (insn
->insn_class
))
1796 create_insn (ip
, insn
);
1799 imm_expr
->X_op
= O_absent
;
1800 *imm_reloc
= BFD_RELOC_UNUSED
;
1801 p
= percent_op_itype
;
1803 for (args
= insn
->args
;; ++args
)
1805 s
+= strspn (s
, " \t");
1808 case '\0': /* End of args. */
1809 if (insn
->pinfo
!= INSN_MACRO
)
1811 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1814 /* For .insn, insn->match and insn->mask are 0. */
1815 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1821 if (riscv_is_priv_insn (ip
->insn_opcode
))
1822 explicit_priv_attr
= TRUE
;
1824 /* Check if we write a read-only CSR by the CSR
1827 && riscv_opts
.csr_check
1828 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1830 /* Restore the character in advance, since we want to
1831 report the detailed warning message here. */
1833 *(argsStart
- 1) = save_c
;
1834 as_warn (_("Read-only CSR is written `%s'"), str
);
1835 insn_with_csr
= FALSE
;
1840 /* Successful assembly. */
1842 insn_with_csr
= FALSE
;
1848 case 's': /* RS1 x8-x15 */
1849 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1850 || !(regno
>= 8 && regno
<= 15))
1852 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1854 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1855 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1856 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1859 case 't': /* RS2 x8-x15 */
1860 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1861 || !(regno
>= 8 && regno
<= 15))
1863 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1865 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1866 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1867 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1870 case 'U': /* RS1, constrained to equal RD. */
1871 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1872 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1876 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1878 INSERT_OPERAND (CRS2
, *ip
, regno
);
1880 case 'c': /* RS1, constrained to equal sp. */
1881 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1885 case 'z': /* RS2, contrained to equal x0. */
1886 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1891 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1892 || imm_expr
->X_op
!= O_constant
1893 || imm_expr
->X_add_number
<= 0
1894 || imm_expr
->X_add_number
>= 64)
1896 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1899 imm_expr
->X_op
= O_absent
;
1902 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1903 || imm_expr
->X_op
!= O_constant
1904 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1905 || imm_expr
->X_add_number
<= 0
1906 || imm_expr
->X_add_number
>= 32)
1908 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1911 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1912 || imm_expr
->X_op
!= O_constant
1913 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1914 || imm_expr
->X_add_number
< 0
1915 || imm_expr
->X_add_number
>= 256)
1917 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1920 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1921 || imm_expr
->X_op
!= O_constant
1922 || imm_expr
->X_add_number
== 0
1923 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1925 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1928 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1929 || imm_expr
->X_op
!= O_constant
1930 || imm_expr
->X_add_number
== 0
1931 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1933 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1936 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1938 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1939 || imm_expr
->X_op
!= O_constant
1940 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1942 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1945 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1947 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1948 || imm_expr
->X_op
!= O_constant
1949 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1951 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1954 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1956 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1957 || imm_expr
->X_op
!= O_constant
1958 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1961 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1964 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1966 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1967 || imm_expr
->X_op
!= O_constant
1968 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1971 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1974 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1975 || imm_expr
->X_op
!= O_constant
1976 /* C.addiw, c.li, and c.andi allow zero immediate.
1977 C.addi allows zero immediate as hint. Otherwise this
1979 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1981 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1984 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1985 || imm_expr
->X_op
!= O_constant
1986 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1987 || imm_expr
->X_add_number
== 0)
1990 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1993 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1994 || imm_expr
->X_op
!= O_constant
1995 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1996 || imm_expr
->X_add_number
== 0)
1999 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2002 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2004 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2005 || imm_expr
->X_op
!= O_constant
2006 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
2009 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2012 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2014 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2015 || imm_expr
->X_op
!= O_constant
2016 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
2019 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2022 p
= percent_op_utype
;
2023 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2026 if (imm_expr
->X_op
!= O_constant
2027 || imm_expr
->X_add_number
<= 0
2028 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2029 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2030 && (imm_expr
->X_add_number
<
2031 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2033 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2036 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2037 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2038 || ((int32_t)imm_expr
->X_add_number
2039 != imm_expr
->X_add_number
))
2041 imm_expr
->X_add_number
=
2042 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2048 case 'S': /* Floating-point RS1 x8-x15. */
2049 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2050 || !(regno
>= 8 && regno
<= 15))
2052 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2054 case 'D': /* Floating-point RS2 x8-x15. */
2055 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2056 || !(regno
>= 8 && regno
<= 15))
2058 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2060 case 'T': /* Floating-point RS2. */
2061 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2063 INSERT_OPERAND (CRS2
, *ip
, regno
);
2069 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2070 || imm_expr
->X_op
!= O_constant
2071 || imm_expr
->X_add_number
< 0
2072 || imm_expr
->X_add_number
>= 64)
2074 as_bad (_("bad value for funct6 field, "
2075 "value must be 0...64"));
2079 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2080 imm_expr
->X_op
= O_absent
;
2084 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2085 || imm_expr
->X_op
!= O_constant
2086 || imm_expr
->X_add_number
< 0
2087 || imm_expr
->X_add_number
>= 16)
2089 as_bad (_("bad value for funct4 field, "
2090 "value must be 0...15"));
2094 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2095 imm_expr
->X_op
= O_absent
;
2099 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2100 || imm_expr
->X_op
!= O_constant
2101 || imm_expr
->X_add_number
< 0
2102 || imm_expr
->X_add_number
>= 8)
2104 as_bad (_("bad value for funct3 field, "
2105 "value must be 0...7"));
2108 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2109 imm_expr
->X_op
= O_absent
;
2113 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2114 || imm_expr
->X_op
!= O_constant
2115 || imm_expr
->X_add_number
< 0
2116 || imm_expr
->X_add_number
>= 4)
2118 as_bad (_("bad value for funct2 field, "
2119 "value must be 0...3"));
2122 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2123 imm_expr
->X_op
= O_absent
;
2127 as_bad (_("bad compressed FUNCT field"
2128 " specifier 'CF%c'\n"),
2134 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2153 case '<': /* Shift amount, 0 - 31. */
2154 my_getExpression (imm_expr
, s
);
2155 check_absolute_expr (ip
, imm_expr
, FALSE
);
2156 if ((unsigned long) imm_expr
->X_add_number
> 31)
2157 as_bad (_("Improper shift amount (%lu)"),
2158 (unsigned long) imm_expr
->X_add_number
);
2159 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2160 imm_expr
->X_op
= O_absent
;
2164 case '>': /* Shift amount, 0 - (XLEN-1). */
2165 my_getExpression (imm_expr
, s
);
2166 check_absolute_expr (ip
, imm_expr
, FALSE
);
2167 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2168 as_bad (_("Improper shift amount (%lu)"),
2169 (unsigned long) imm_expr
->X_add_number
);
2170 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2171 imm_expr
->X_op
= O_absent
;
2175 case 'Z': /* CSRRxI immediate. */
2176 my_getExpression (imm_expr
, s
);
2177 check_absolute_expr (ip
, imm_expr
, FALSE
);
2178 if ((unsigned long) imm_expr
->X_add_number
> 31)
2179 as_bad (_("Improper CSRxI immediate (%lu)"),
2180 (unsigned long) imm_expr
->X_add_number
);
2181 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2182 imm_expr
->X_op
= O_absent
;
2186 case 'E': /* Control register. */
2187 insn_with_csr
= TRUE
;
2188 explicit_priv_attr
= TRUE
;
2189 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2190 INSERT_OPERAND (CSR
, *ip
, regno
);
2193 my_getExpression (imm_expr
, s
);
2194 check_absolute_expr (ip
, imm_expr
, TRUE
);
2195 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2196 as_bad (_("Improper CSR address (%lu)"),
2197 (unsigned long) imm_expr
->X_add_number
);
2198 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2199 imm_expr
->X_op
= O_absent
;
2204 case 'm': /* Rounding mode. */
2205 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2207 INSERT_OPERAND (RM
, *ip
, regno
);
2213 case 'Q': /* Fence predecessor/successor. */
2214 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2218 INSERT_OPERAND (PRED
, *ip
, regno
);
2220 INSERT_OPERAND (SUCC
, *ip
, regno
);
2225 case 'd': /* Destination register. */
2226 case 's': /* Source register. */
2227 case 't': /* Target register. */
2228 case 'r': /* rs3. */
2229 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2235 /* Now that we have assembled one operand, we use the args
2236 string to figure out where it goes in the instruction. */
2240 INSERT_OPERAND (RS1
, *ip
, regno
);
2243 INSERT_OPERAND (RD
, *ip
, regno
);
2246 INSERT_OPERAND (RS2
, *ip
, regno
);
2249 INSERT_OPERAND (RS3
, *ip
, regno
);
2256 case 'D': /* Floating point rd. */
2257 case 'S': /* Floating point rs1. */
2258 case 'T': /* Floating point rs2. */
2259 case 'U': /* Floating point rs1 and rs2. */
2260 case 'R': /* Floating point rs3. */
2261 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2269 INSERT_OPERAND (RD
, *ip
, regno
);
2272 INSERT_OPERAND (RS1
, *ip
, regno
);
2275 INSERT_OPERAND (RS1
, *ip
, regno
);
2278 INSERT_OPERAND (RS2
, *ip
, regno
);
2281 INSERT_OPERAND (RS3
, *ip
, regno
);
2290 my_getExpression (imm_expr
, s
);
2291 if (imm_expr
->X_op
!= O_big
2292 && imm_expr
->X_op
!= O_constant
)
2294 normalize_constant_expr (imm_expr
);
2299 my_getExpression (imm_expr
, s
);
2300 normalize_constant_expr (imm_expr
);
2301 /* The 'A' format specifier must be a symbol. */
2302 if (imm_expr
->X_op
!= O_symbol
)
2304 *imm_reloc
= BFD_RELOC_32
;
2309 my_getExpression (imm_expr
, s
);
2310 normalize_constant_expr (imm_expr
);
2311 /* The 'B' format specifier must be a symbol or a constant. */
2312 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2314 if (imm_expr
->X_op
== O_symbol
)
2315 *imm_reloc
= BFD_RELOC_32
;
2319 case 'j': /* Sign-extended immediate. */
2320 p
= percent_op_itype
;
2321 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2323 case 'q': /* Store displacement. */
2324 p
= percent_op_stype
;
2325 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2327 case 'o': /* Load displacement. */
2328 p
= percent_op_itype
;
2329 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2331 case '1': /* 4-operand add, must be %tprel_add. */
2332 p
= percent_op_rtype
;
2334 case '0': /* AMO "displacement," which must be zero. */
2335 p
= percent_op_null
;
2337 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2340 /* If this value won't fit into a 16 bit offset, then go
2341 find a macro that will generate the 32 bit offset
2343 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2345 normalize_constant_expr (imm_expr
);
2346 if (imm_expr
->X_op
!= O_constant
2347 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2349 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2350 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2357 case 'p': /* PC-relative offset. */
2359 *imm_reloc
= BFD_RELOC_12_PCREL
;
2360 my_getExpression (imm_expr
, s
);
2364 case 'u': /* Upper 20 bits. */
2365 p
= percent_op_utype
;
2366 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2368 if (imm_expr
->X_op
!= O_constant
)
2371 if (imm_expr
->X_add_number
< 0
2372 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2373 as_bad (_("lui expression not in range 0..1048575"));
2375 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2376 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2381 case 'a': /* 20-bit PC-relative offset. */
2383 my_getExpression (imm_expr
, s
);
2385 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2389 my_getExpression (imm_expr
, s
);
2391 if (strcmp (s
, "@plt") == 0)
2393 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2397 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2403 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2404 || imm_expr
->X_op
!= O_constant
2405 || imm_expr
->X_add_number
< 0
2406 || imm_expr
->X_add_number
>= 128
2407 || (imm_expr
->X_add_number
& 0x3) != 3)
2409 as_bad (_("bad value for opcode field, "
2410 "value must be 0...127 and "
2411 "lower 2 bits must be 0x3"));
2415 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2416 imm_expr
->X_op
= O_absent
;
2420 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2421 || imm_expr
->X_op
!= O_constant
2422 || imm_expr
->X_add_number
< 0
2423 || imm_expr
->X_add_number
>= 3)
2425 as_bad (_("bad value for opcode field, "
2426 "value must be 0...2"));
2430 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2431 imm_expr
->X_op
= O_absent
;
2435 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2443 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2444 || imm_expr
->X_op
!= O_constant
2445 || imm_expr
->X_add_number
< 0
2446 || imm_expr
->X_add_number
>= 128)
2448 as_bad (_("bad value for funct7 field, "
2449 "value must be 0...127"));
2453 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2454 imm_expr
->X_op
= O_absent
;
2458 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2459 || imm_expr
->X_op
!= O_constant
2460 || imm_expr
->X_add_number
< 0
2461 || imm_expr
->X_add_number
>= 8)
2463 as_bad (_("bad value for funct3 field, "
2464 "value must be 0...7"));
2468 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2469 imm_expr
->X_op
= O_absent
;
2473 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2474 || imm_expr
->X_op
!= O_constant
2475 || imm_expr
->X_add_number
< 0
2476 || imm_expr
->X_add_number
>= 4)
2478 as_bad (_("bad value for funct2 field, "
2479 "value must be 0...3"));
2483 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2484 imm_expr
->X_op
= O_absent
;
2489 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2494 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2495 || imm_expr
->X_op
!= O_constant
2496 || imm_expr
->X_add_number
!= 0)
2499 imm_expr
->X_op
= O_absent
;
2503 as_fatal (_("internal error: bad argument type %c"), *args
);
2508 error
= _("illegal operands");
2509 insn_with_csr
= FALSE
;
2513 /* Restore the character we might have clobbered above. */
2515 *(argsStart
- 1) = save_c
;
2521 md_assemble (char *str
)
2523 struct riscv_cl_insn insn
;
2524 expressionS imm_expr
;
2525 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2527 /* The arch and priv attributes should be set before assembling. */
2528 if (!start_assemble
)
2530 start_assemble
= TRUE
;
2532 /* Set the default_priv_spec according to the priv attributes. */
2533 if (!riscv_set_default_priv_spec (NULL
))
2537 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2541 as_bad ("%s `%s'", error
, str
);
2545 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2546 macro (&insn
, &imm_expr
, &imm_reloc
);
2548 append_insn (&insn
, &imm_expr
, imm_reloc
);
2552 md_atof (int type
, char *litP
, int *sizeP
)
2554 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2558 md_number_to_chars (char *buf
, valueT val
, int n
)
2560 number_to_chars_littleendian (buf
, val
, n
);
2563 const char *md_shortopts
= "O::g::G:";
2567 OPTION_MARCH
= OPTION_MD_BASE
,
2574 OPTION_NO_ARCH_ATTR
,
2576 OPTION_NO_CSR_CHECK
,
2582 struct option md_longopts
[] =
2584 {"march", required_argument
, NULL
, OPTION_MARCH
},
2585 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2586 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2587 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2588 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2589 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2590 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2591 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2592 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2593 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2594 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2595 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2596 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2598 {NULL
, no_argument
, NULL
, 0}
2600 size_t md_longopts_size
= sizeof (md_longopts
);
2603 FLOAT_ABI_DEFAULT
= -1,
2609 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2612 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2614 abi_xlen
= new_xlen
;
2615 float_abi
= new_float_abi
;
2620 md_parse_option (int c
, const char *arg
)
2625 /* riscv_after_parse_args will call riscv_set_arch to parse
2626 the architecture. */
2627 default_arch_with_ext
= arg
;
2631 riscv_opts
.pic
= FALSE
;
2635 riscv_opts
.pic
= TRUE
;
2639 if (strcmp (arg
, "ilp32") == 0)
2640 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2641 else if (strcmp (arg
, "ilp32e") == 0)
2642 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2643 else if (strcmp (arg
, "ilp32f") == 0)
2644 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2645 else if (strcmp (arg
, "ilp32d") == 0)
2646 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2647 else if (strcmp (arg
, "ilp32q") == 0)
2648 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2649 else if (strcmp (arg
, "lp64") == 0)
2650 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2651 else if (strcmp (arg
, "lp64f") == 0)
2652 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2653 else if (strcmp (arg
, "lp64d") == 0)
2654 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2655 else if (strcmp (arg
, "lp64q") == 0)
2656 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2662 riscv_opts
.relax
= TRUE
;
2665 case OPTION_NO_RELAX
:
2666 riscv_opts
.relax
= FALSE
;
2669 case OPTION_ARCH_ATTR
:
2670 riscv_opts
.arch_attr
= TRUE
;
2673 case OPTION_NO_ARCH_ATTR
:
2674 riscv_opts
.arch_attr
= FALSE
;
2677 case OPTION_CSR_CHECK
:
2678 riscv_opts
.csr_check
= TRUE
;
2681 case OPTION_NO_CSR_CHECK
:
2682 riscv_opts
.csr_check
= FALSE
;
2685 case OPTION_MISA_SPEC
:
2686 return riscv_set_default_isa_spec (arg
);
2688 case OPTION_MPRIV_SPEC
:
2689 return riscv_set_default_priv_spec (arg
);
2699 riscv_after_parse_args (void)
2701 /* The --with-arch is optional for now, so we have to set the xlen
2702 according to the default_arch, which is set by the --targte, first.
2703 Then, we use the xlen to set the default_arch_with_ext if the
2704 -march and --with-arch are not set. */
2707 if (strcmp (default_arch
, "riscv32") == 0)
2709 else if (strcmp (default_arch
, "riscv64") == 0)
2712 as_bad ("unknown default architecture `%s'", default_arch
);
2714 if (default_arch_with_ext
== NULL
)
2715 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2717 /* Initialize the hash table for extensions with default version. */
2718 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2720 /* If the -misa-spec isn't set, then we set the default ISA spec according
2721 to DEFAULT_RISCV_ISA_SPEC. */
2722 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2723 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2725 /* Set the architecture according to -march or or --with-arch. */
2726 riscv_set_arch (default_arch_with_ext
);
2728 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2729 riscv_set_rvc (FALSE
);
2730 if (riscv_subset_supports ("c"))
2731 riscv_set_rvc (TRUE
);
2733 /* Enable RVE if specified by the -march option. */
2734 riscv_set_rve (FALSE
);
2735 if (riscv_subset_supports ("e"))
2736 riscv_set_rve (TRUE
);
2738 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2739 according to DEFAULT_PRIV_SPEC. */
2740 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2741 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2743 /* Infer ABI from ISA if not specified on command line. */
2746 else if (abi_xlen
> xlen
)
2747 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2748 else if (abi_xlen
< xlen
)
2749 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2751 if (float_abi
== FLOAT_ABI_DEFAULT
)
2753 riscv_subset_t
*subset
;
2755 /* Assume soft-float unless D extension is present. */
2756 float_abi
= FLOAT_ABI_SOFT
;
2758 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2760 if (strcasecmp (subset
->name
, "D") == 0)
2761 float_abi
= FLOAT_ABI_DOUBLE
;
2762 if (strcasecmp (subset
->name
, "Q") == 0)
2763 float_abi
= FLOAT_ABI_QUAD
;
2768 elf_flags
|= EF_RISCV_RVE
;
2770 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2771 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2773 /* If the CIE to be produced has not been overridden on the command line,
2774 then produce version 3 by default. This allows us to use the full
2775 range of registers in a .cfi_return_column directive. */
2776 if (flag_dwarf_cie_version
== -1)
2777 flag_dwarf_cie_version
= 3;
2781 md_pcrel_from (fixS
*fixP
)
2783 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2786 /* Apply a fixup to the object file. */
2789 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2791 unsigned int subtype
;
2792 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2793 bfd_boolean relaxable
= FALSE
;
2797 /* Remember value for tc_gen_reloc. */
2798 fixP
->fx_addnumber
= *valP
;
2800 switch (fixP
->fx_r_type
)
2802 case BFD_RELOC_RISCV_HI20
:
2803 case BFD_RELOC_RISCV_LO12_I
:
2804 case BFD_RELOC_RISCV_LO12_S
:
2805 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2806 | bfd_getl32 (buf
), buf
);
2807 if (fixP
->fx_addsy
== NULL
)
2808 fixP
->fx_done
= TRUE
;
2812 case BFD_RELOC_RISCV_GOT_HI20
:
2813 case BFD_RELOC_RISCV_ADD8
:
2814 case BFD_RELOC_RISCV_ADD16
:
2815 case BFD_RELOC_RISCV_ADD32
:
2816 case BFD_RELOC_RISCV_ADD64
:
2817 case BFD_RELOC_RISCV_SUB6
:
2818 case BFD_RELOC_RISCV_SUB8
:
2819 case BFD_RELOC_RISCV_SUB16
:
2820 case BFD_RELOC_RISCV_SUB32
:
2821 case BFD_RELOC_RISCV_SUB64
:
2822 case BFD_RELOC_RISCV_RELAX
:
2825 case BFD_RELOC_RISCV_TPREL_HI20
:
2826 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2827 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2828 case BFD_RELOC_RISCV_TPREL_ADD
:
2832 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2833 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2834 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2835 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2836 if (fixP
->fx_addsy
!= NULL
)
2837 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2840 _("TLS relocation against a constant"));
2844 /* Use pc-relative relocation for FDE initial location.
2845 The symbol address in .eh_frame may be adjusted in
2846 _bfd_elf_discard_section_eh_frame, and the content of
2847 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2848 Therefore, we cannot insert a relocation whose addend symbol is
2849 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2850 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2851 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2852 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2853 && S_GET_VALUE (fixP
->fx_subsy
)
2854 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2856 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2857 fixP
->fx_subsy
= NULL
;
2864 case BFD_RELOC_RISCV_CFA
:
2865 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2867 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2868 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2869 fixP
->fx_next
->fx_subsy
= NULL
;
2870 fixP
->fx_next
->fx_offset
= 0;
2871 fixP
->fx_subsy
= NULL
;
2873 switch (fixP
->fx_r_type
)
2876 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2877 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2881 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2882 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2886 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2887 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2891 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2892 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2895 case BFD_RELOC_RISCV_CFA
:
2896 /* Load the byte to get the subtype. */
2897 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2898 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2901 case DW_CFA_advance_loc1
:
2902 fixP
->fx_where
= loc
+ 1;
2903 fixP
->fx_next
->fx_where
= loc
+ 1;
2904 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2905 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2908 case DW_CFA_advance_loc2
:
2910 fixP
->fx_next
->fx_size
= 2;
2911 fixP
->fx_where
= loc
+ 1;
2912 fixP
->fx_next
->fx_where
= loc
+ 1;
2913 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2914 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2917 case DW_CFA_advance_loc4
:
2919 fixP
->fx_next
->fx_size
= 4;
2920 fixP
->fx_where
= loc
;
2921 fixP
->fx_next
->fx_where
= loc
;
2922 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2923 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2927 if (subtype
< 0x80 && (subtype
& 0x40))
2929 /* DW_CFA_advance_loc */
2930 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2931 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2932 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2933 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2936 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2942 /* This case is unreachable. */
2949 /* If we are deleting this reloc entry, we must fill in the
2950 value now. This can happen if we have a .word which is not
2951 resolved when it appears but is later defined. */
2952 if (fixP
->fx_addsy
== NULL
)
2954 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2955 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2960 case BFD_RELOC_RISCV_JMP
:
2963 /* Fill in a tentative value to improve objdump readability. */
2964 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2965 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2966 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2970 case BFD_RELOC_12_PCREL
:
2973 /* Fill in a tentative value to improve objdump readability. */
2974 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2975 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2976 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2980 case BFD_RELOC_RISCV_RVC_BRANCH
:
2983 /* Fill in a tentative value to improve objdump readability. */
2984 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2985 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2986 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2990 case BFD_RELOC_RISCV_RVC_JUMP
:
2993 /* Fill in a tentative value to improve objdump readability. */
2994 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2995 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2996 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3000 case BFD_RELOC_RISCV_CALL
:
3001 case BFD_RELOC_RISCV_CALL_PLT
:
3005 case BFD_RELOC_RISCV_PCREL_HI20
:
3006 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3007 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3008 relaxable
= riscv_opts
.relax
;
3011 case BFD_RELOC_RISCV_ALIGN
:
3015 /* We ignore generic BFD relocations we don't know about. */
3016 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3017 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3020 if (fixP
->fx_subsy
!= NULL
)
3021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3022 _("unsupported symbol subtraction"));
3024 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3025 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3027 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3028 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3029 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3033 /* Because the value of .cfi_remember_state may changed after relaxation,
3034 we insert a fix to relocate it again in link-time. */
3037 riscv_pre_output_hook (void)
3039 const frchainS
*frch
;
3042 /* Save the current segment info. */
3044 subsegT subseg
= now_subseg
;
3046 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3047 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3051 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3053 if (frag
->fr_type
== rs_cfa
)
3056 expressionS
*symval
;
3058 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3059 exp
.X_op
= O_subtract
;
3060 exp
.X_add_symbol
= symval
->X_add_symbol
;
3061 exp
.X_add_number
= 0;
3062 exp
.X_op_symbol
= symval
->X_op_symbol
;
3064 /* We must set the segment before creating a frag after all
3065 frag chains have been chained together. */
3066 subseg_set (s
, frch
->frch_subseg
);
3068 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3069 BFD_RELOC_RISCV_CFA
);
3074 /* Restore the original segment info. */
3075 subseg_set (seg
, subseg
);
3079 /* This structure is used to hold a stack of .option values. */
3081 struct riscv_option_stack
3083 struct riscv_option_stack
*next
;
3084 struct riscv_set_options options
;
3087 static struct riscv_option_stack
*riscv_opts_stack
;
3089 /* Handle the .option pseudo-op. */
3092 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3094 char *name
= input_line_pointer
, ch
;
3096 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3097 ++input_line_pointer
;
3098 ch
= *input_line_pointer
;
3099 *input_line_pointer
= '\0';
3101 if (strcmp (name
, "rvc") == 0)
3102 riscv_set_rvc (TRUE
);
3103 else if (strcmp (name
, "norvc") == 0)
3104 riscv_set_rvc (FALSE
);
3105 else if (strcmp (name
, "pic") == 0)
3106 riscv_opts
.pic
= TRUE
;
3107 else if (strcmp (name
, "nopic") == 0)
3108 riscv_opts
.pic
= FALSE
;
3109 else if (strcmp (name
, "relax") == 0)
3110 riscv_opts
.relax
= TRUE
;
3111 else if (strcmp (name
, "norelax") == 0)
3112 riscv_opts
.relax
= FALSE
;
3113 else if (strcmp (name
, "csr-check") == 0)
3114 riscv_opts
.csr_check
= TRUE
;
3115 else if (strcmp (name
, "no-csr-check") == 0)
3116 riscv_opts
.csr_check
= FALSE
;
3117 else if (strcmp (name
, "push") == 0)
3119 struct riscv_option_stack
*s
;
3121 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3122 s
->next
= riscv_opts_stack
;
3123 s
->options
= riscv_opts
;
3124 riscv_opts_stack
= s
;
3126 else if (strcmp (name
, "pop") == 0)
3128 struct riscv_option_stack
*s
;
3130 s
= riscv_opts_stack
;
3132 as_bad (_(".option pop with no .option push"));
3135 riscv_opts
= s
->options
;
3136 riscv_opts_stack
= s
->next
;
3142 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3144 *input_line_pointer
= ch
;
3145 demand_empty_rest_of_line ();
3148 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3149 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3150 use in DWARF debug information. */
3153 s_dtprel (int bytes
)
3160 if (ex
.X_op
!= O_symbol
)
3162 as_bad (_("Unsupported use of %s"), (bytes
== 8
3165 ignore_rest_of_line ();
3168 p
= frag_more (bytes
);
3169 md_number_to_chars (p
, 0, bytes
);
3170 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3172 ? BFD_RELOC_RISCV_TLS_DTPREL64
3173 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3175 demand_empty_rest_of_line ();
3178 /* Handle the .bss pseudo-op. */
3181 s_bss (int ignore ATTRIBUTE_UNUSED
)
3183 subseg_set (bss_section
, 0);
3184 demand_empty_rest_of_line ();
3188 riscv_make_nops (char *buf
, bfd_vma bytes
)
3192 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3193 means we are not within a valid instruction sequence. It is thus safe
3194 to use a zero byte, even though that is not a valid instruction. */
3198 /* Use at most one 2-byte NOP. */
3199 if ((bytes
- i
) % 4 == 2)
3201 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3205 /* Fill the remainder with 4-byte NOPs. */
3206 for ( ; i
< bytes
; i
+= 4)
3207 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3210 /* Called from md_do_align. Used to create an alignment frag in a
3211 code section by emitting a worst-case NOP sequence that the linker
3212 will later relax to the correct number of NOPs. We can't compute
3213 the correct alignment now because of other linker relaxations. */
3216 riscv_frag_align_code (int n
)
3218 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3219 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3220 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3224 /* If we are moving to a smaller alignment than the instruction size, then no
3225 alignment is required. */
3226 if (bytes
<= insn_alignment
)
3229 /* When not relaxing, riscv_handle_align handles code alignment. */
3230 if (!riscv_opts
.relax
)
3233 nops
= frag_more (worst_case_bytes
);
3235 ex
.X_op
= O_constant
;
3236 ex
.X_add_number
= worst_case_bytes
;
3238 riscv_make_nops (nops
, worst_case_bytes
);
3240 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3241 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3246 /* Implement HANDLE_ALIGN. */
3249 riscv_handle_align (fragS
*fragP
)
3251 switch (fragP
->fr_type
)
3254 /* When relaxing, riscv_frag_align_code handles code alignment. */
3255 if (!riscv_opts
.relax
)
3257 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3258 - fragP
->fr_address
- fragP
->fr_fix
);
3259 /* We have 4 byte uncompressed nops. */
3260 bfd_signed_vma size
= 4;
3261 bfd_signed_vma excess
= bytes
% size
;
3262 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3267 /* Insert zeros or compressed nops to get 4 byte alignment. */
3270 riscv_make_nops (p
, excess
);
3271 fragP
->fr_fix
+= excess
;
3275 /* Insert variable number of 4 byte uncompressed nops. */
3276 riscv_make_nops (p
, size
);
3277 fragP
->fr_var
= size
;
3287 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3289 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3292 /* Translate internal representation of relocation info to BFD target
3296 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3298 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3300 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3301 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3302 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3303 reloc
->addend
= fixp
->fx_addnumber
;
3305 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3306 if (reloc
->howto
== NULL
)
3308 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3309 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3311 /* We don't have R_RISCV_8/16, but for this special case,
3312 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3316 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3317 _("cannot represent %s relocation in object file"),
3318 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3326 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3328 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3330 offsetT old_var
= fragp
->fr_var
;
3331 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3332 return fragp
->fr_var
- old_var
;
3338 /* Expand far branches to multi-instruction sequences. */
3341 md_convert_frag_branch (fragS
*fragp
)
3349 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3351 exp
.X_op
= O_symbol
;
3352 exp
.X_add_symbol
= fragp
->fr_symbol
;
3353 exp
.X_add_number
= fragp
->fr_offset
;
3355 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3357 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3359 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3363 /* Expand the RVC branch into a RISC-V one. */
3364 insn
= bfd_getl16 (buf
);
3365 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3366 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3368 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3369 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3370 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3371 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3372 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3373 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3376 bfd_putl32 (insn
, buf
);
3380 /* Invert the branch condition. Branch over the jump. */
3381 insn
= bfd_getl16 (buf
);
3382 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3383 insn
|= ENCODE_RVC_B_IMM (6);
3384 bfd_putl16 (insn
, buf
);
3389 /* Just keep the RVC branch. */
3390 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3391 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3392 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3393 2, &exp
, FALSE
, reloc
);
3402 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3405 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3407 /* Invert the branch condition. Branch over the jump. */
3408 insn
= bfd_getl32 (buf
);
3409 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3410 insn
|= ENCODE_SBTYPE_IMM (8);
3411 md_number_to_chars ((char *) buf
, insn
, 4);
3415 /* Jump to the target. */
3416 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3417 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3418 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3423 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3424 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3425 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3426 4, &exp
, FALSE
, reloc
);
3435 fixp
->fx_file
= fragp
->fr_file
;
3436 fixp
->fx_line
= fragp
->fr_line
;
3438 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3439 + fragp
->fr_fix
+ fragp
->fr_var
);
3441 fragp
->fr_fix
+= fragp
->fr_var
;
3444 /* Relax a machine dependent frag. This returns the amount by which
3445 the current size of the frag should change. */
3448 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3451 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3452 md_convert_frag_branch (fragp
);
3456 md_show_usage (FILE *stream
)
3458 fprintf (stream
, _("\
3460 -fpic generate position-independent code\n\
3461 -fno-pic don't generate position-independent code (default)\n\
3462 -march=ISA set the RISC-V architecture\n\
3463 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3464 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3465 -mabi=ABI set the RISC-V ABI\n\
3466 -mrelax enable relax (default)\n\
3467 -mno-relax disable relax\n\
3468 -march-attr generate RISC-V arch attribute\n\
3469 -mno-arch-attr don't generate RISC-V arch attribute\n\
3473 /* Standard calling conventions leave the CFA at SP on entry. */
3475 riscv_cfi_frame_initial_instructions (void)
3477 cfi_add_CFA_def_cfa_register (X_SP
);
3481 tc_riscv_regname_to_dw2regnum (char *regname
)
3485 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3488 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3491 /* CSRs are numbered 4096 -> 8191. */
3492 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3495 as_bad (_("unknown register `%s'"), regname
);
3500 riscv_elf_final_processing (void)
3502 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3505 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3506 since these directives break relaxation when used with symbol deltas. */
3509 s_riscv_leb128 (int sign
)
3512 char *save_in
= input_line_pointer
;
3515 if (exp
.X_op
!= O_constant
)
3516 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3517 demand_empty_rest_of_line ();
3519 input_line_pointer
= save_in
;
3520 return s_leb128 (sign
);
3523 /* Parse the .insn directive. */
3526 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3528 char *str
= input_line_pointer
;
3529 struct riscv_cl_insn insn
;
3530 expressionS imm_expr
;
3531 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3534 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3535 ++input_line_pointer
;
3537 save_c
= *input_line_pointer
;
3538 *input_line_pointer
= '\0';
3540 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3541 &imm_reloc
, insn_type_hash
);
3545 as_bad ("%s `%s'", error
, str
);
3549 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3550 append_insn (&insn
, &imm_expr
, imm_reloc
);
3553 *input_line_pointer
= save_c
;
3554 demand_empty_rest_of_line ();
3557 /* Update arch and priv attributes. If we don't set the corresponding ELF
3558 attributes, then try to output the default ones. */
3561 riscv_write_out_attrs (void)
3563 const char *arch_str
, *priv_str
, *p
;
3564 /* versions[0] is major, versions[1] is minor,
3565 and versions[3] is revision. */
3566 unsigned versions
[3] = {0}, number
= 0;
3569 /* Re-write arch attribute to normalize the arch string. */
3570 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3571 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3572 xfree ((void *)arch_str
);
3574 /* For the file without any instruction, we don't set the default_priv_spec
3575 according to the priv attributes since the md_assemble isn't called.
3576 Call riscv_set_default_priv_spec here for the above case, although
3577 it seems strange. */
3579 && !riscv_set_default_priv_spec (NULL
))
3582 /* If we already have set elf priv attributes, then no need to do anything,
3583 assembler will generate them according to what you set. Otherwise, don't
3584 generate or update them when no CSR and priv instructions are used.
3585 Generate the priv attributes according to default_priv_spec, which can be
3586 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3587 priv attribute sets. */
3588 if (!explicit_priv_attr
)
3591 /* Re-write priv attributes by default_priv_spec. */
3592 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3594 for (i
= 0; *p
; ++p
)
3596 if (*p
== '.' && i
< 3)
3598 versions
[i
++] = number
;
3601 else if (ISDIGIT (*p
))
3602 number
= (number
* 10) + (*p
- '0');
3605 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3609 versions
[i
] = number
;
3611 /* Set the priv attributes. */
3612 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3613 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3614 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3617 /* Add the default contents for the .riscv.attributes section. If any
3618 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3619 to update the arch and priv attributes. */
3622 riscv_set_public_attributes (void)
3624 if (riscv_opts
.arch_attr
|| explicit_attr
)
3625 riscv_write_out_attrs ();
3628 /* Called after all assembly has been done. */
3633 riscv_set_public_attributes ();
3636 /* Given a symbolic attribute NAME, return the proper integer value.
3637 Returns -1 if the attribute is not known. */
3640 riscv_convert_symbolic_attribute (const char *name
)
3649 /* When you modify this table you should
3650 also modify the list in doc/c-riscv.texi. */
3651 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3655 T(priv_spec_revision
),
3656 T(unaligned_access
),
3666 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3667 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3668 return attribute_table
[i
].tag
;
3673 /* Parse a .attribute directive. */
3676 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3678 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3680 obj_attribute
*attr
;
3682 explicit_attr
= TRUE
;
3685 case Tag_RISCV_arch
:
3687 attr
= elf_known_obj_attributes_proc (stdoutput
);
3688 if (!start_assemble
)
3689 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3691 as_fatal (_(".attribute arch must set before any instructions"));
3693 if (old_xlen
!= xlen
)
3695 /* We must re-init bfd again if xlen is changed. */
3696 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3697 bfd_find_target (riscv_target_format (), stdoutput
);
3699 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3700 as_warn (_("Could not set architecture and machine"));
3704 case Tag_RISCV_priv_spec
:
3705 case Tag_RISCV_priv_spec_minor
:
3706 case Tag_RISCV_priv_spec_revision
:
3708 as_fatal (_(".attribute priv spec must set before any instructions"));
3716 /* Pseudo-op table. */
3718 static const pseudo_typeS riscv_pseudo_table
[] =
3720 /* RISC-V-specific pseudo-ops. */
3721 {"option", s_riscv_option
, 0},
3725 {"dtprelword", s_dtprel
, 4},
3726 {"dtpreldword", s_dtprel
, 8},
3728 {"uleb128", s_riscv_leb128
, 0},
3729 {"sleb128", s_riscv_leb128
, 1},
3730 {"insn", s_riscv_insn
, 0},
3731 {"attribute", s_riscv_attribute
, 0},
3737 riscv_pop_insert (void)
3739 extern void pop_insert (const pseudo_typeS
*);
3741 pop_insert (riscv_pseudo_table
);