1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2024 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
27 #include "elf/sparc.h"
28 #include "dwarf2dbg.h"
30 /* Some ancient Sun C compilers would not take such hex constants as
31 unsigned, and would end up sign-extending them to form an offsetT,
32 so use these constants instead. */
33 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
34 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
36 static int sparc_ip (char *, const struct sparc_opcode
**);
37 static int parse_sparc_asi (char **, const sparc_asi
**);
38 static int parse_keyword_arg (int (*) (const char *), char **, int *);
39 static int parse_const_expr_arg (char **, int *);
40 static int get_expression (char *);
42 /* Default architecture. */
43 /* ??? The default value should be V8, but sparclite support was added
44 by making it the default. GCC now passes -Asparclite, so maybe sometime in
45 the future we can set this to V8. */
47 #define DEFAULT_ARCH "sparclite"
49 static const char *default_arch
= DEFAULT_ARCH
;
51 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
53 static int default_init_p
;
55 /* Current architecture. We don't bump up unless necessary. */
56 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
58 /* The maximum architecture level we can bump up to.
59 In a 32 bit environment, don't allow bumping up to v9 by default.
60 The native assembler works this way. The user is required to pass
61 an explicit argument before we'll create v9 object files. However, if
62 we don't see any v9 insns, a v8plus object file is not created. */
63 static enum sparc_opcode_arch_val max_architecture
;
65 /* Either 32 or 64, selects file format. */
66 static int sparc_arch_size
;
67 /* Initial (default) value, recorded separately in case a user option
68 changes the value before md_show_usage is called. */
69 static int default_arch_size
;
71 /* The currently selected v9 memory model. Currently only used for
73 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
76 /* Bitmask of instruction types seen so far, used to populate the
77 GNU attributes section with hwcap information. */
78 static uint64_t hwcap_seen
;
81 static uint64_t hwcap_allowed
;
83 static int architecture_requested
;
84 static int warn_on_bump
;
86 /* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88 static enum sparc_opcode_arch_val warn_after_architecture
;
90 /* Non-zero if the assembler should generate error if an undeclared
91 g[23] register has been used in -64. */
92 static int no_undeclared_regs
;
94 /* Non-zero if the assembler should generate a warning if an
95 unpredictable DCTI (delayed control transfer instruction) couple is
97 static int dcti_couples_detect
;
99 /* Non-zero if we should try to relax jumps and calls. */
100 static int sparc_relax
;
102 /* Non-zero if we are generating PIC code. */
105 /* Non-zero if we should give an error when misaligned data is seen. */
106 static int enforce_aligned_data
;
108 extern int target_big_endian
;
110 static int target_little_endian_data
;
112 /* Symbols for global registers on v9. */
113 static symbolS
*globals
[8];
115 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
116 int sparc_cie_data_alignment
;
118 /* V9 and 86x have big and little endian data, but instructions are always big
119 endian. The sparclet has bi-endian support but both data and insns have
120 the same endianness. Global `target_big_endian' is used for data.
121 The following macro is used for instructions. */
122 #ifndef INSN_BIG_ENDIAN
123 #define INSN_BIG_ENDIAN (target_big_endian \
124 || default_arch_type == sparc86x \
125 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
128 /* Handle of the OPCODE hash table. */
129 static htab_t op_hash
;
131 static void s_data1 (void);
132 static void s_seg (int);
133 static void s_proc (int);
134 static void s_reserve (int);
135 static void s_common (int);
136 static void s_empty (int);
137 static void s_uacons (int);
138 static void s_ncons (int);
139 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
159 /* These are specific to sparc/svr4. */
160 {"2byte", s_uacons
, 2},
161 {"4byte", s_uacons
, 4},
162 {"8byte", s_uacons
, 8},
163 {"register", s_register
, 0},
167 /* This array holds the chars that always start a comment. If the
168 pre-processor is disabled, these aren't very useful. */
169 const char comment_chars
[] = "!"; /* JF removed '|' from
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output. */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that comments started like this one will always
179 work if '/' isn't otherwise defined. */
180 const char line_comment_chars
[] = "#";
182 const char line_separator_chars
[] = ";";
184 /* Chars that can be used to separate mant from exp in floating point
186 const char EXP_CHARS
[] = "eE";
188 /* Chars that mean this number is a floating point constant.
191 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
193 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
194 changed in read.c. Ideally it shouldn't have to know about it at all,
195 but nothing is ideal around here. */
197 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
202 unsigned long opcode
;
203 struct nlist
*nlistp
;
207 bfd_reloc_code_real_type reloc
;
210 struct sparc_it the_insn
, set_insn
;
212 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
219 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
220 v8plusa
, v9
, v9a
, v9b
, v9_64
};
222 static struct sparc_arch
{
224 const char *opcode_arch
;
225 enum sparc_arch_types arch_type
;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size
;
229 /* Allowable arg to -A? */
231 /* Extra hardware capabilities allowed. These are added to the
232 hardware capabilities associated with the opcode
236 } sparc_arch_table
[] = {
237 { "v6", "v6", v6
, 0, 1, 0, 0 },
238 { "v7", "v7", v7
, 0, 1, 0, 0 },
239 { "v8", "v8", v8
, 32, 1, 0, 0 },
240 { "v8a", "v8", v8
, 32, 1, 0, 0 },
241 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
242 { "sparcvis", "v9a", v9
, 0, 1, 0, 0 },
243 { "sparcvis2", "v9b", v9
, 0, 1, 0, 0 },
244 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_FMAF
, 0 },
245 { "sparcima", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_IMA
, 0 },
246 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
247 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
249 { "sparc4", "v9v", v9
, 0, 1, 0, 0 },
250 { "sparc5", "v9m", v9
, 0, 1, 0, 0 },
251 { "sparc6", "m8", v9
, 0, 1, 0, 0 },
253 { "leon", "leon", leon
, 32, 1, 0, 0 },
254 { "sparclet", "sparclet", sparclet
, 32, 1, 0, 0 },
255 { "sparclite", "sparclite", sparclite
, 32, 1, 0, 0 },
256 { "sparc86x", "sparclite", sparc86x
, 32, 1, 0, 0 },
258 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
259 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
260 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
261 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
262 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
263 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
264 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
265 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
266 { "v8plusm8", "m8", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
268 { "v9", "v9", v9
, 0, 1, 0, 0 },
269 { "v9a", "v9a", v9
, 0, 1, 0, 0 },
270 { "v9b", "v9b", v9
, 0, 1, 0, 0 },
271 { "v9c", "v9c", v9
, 0, 1, 0, 0 },
272 { "v9d", "v9d", v9
, 0, 1, 0, 0 },
273 { "v9e", "v9e", v9
, 0, 1, 0, 0 },
274 { "v9v", "v9v", v9
, 0, 1, 0, 0 },
275 { "v9m", "v9m", v9
, 0, 1, 0, 0 },
276 { "v9m8", "m8", v9
, 0, 1, 0, 0 },
278 /* This exists to allow configure.tgt to pass one
279 value to specify both the default machine and default word size. */
280 { "v9-64", "v9", v9
, 64, 0, 0, 0 },
281 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
284 /* Variant of default_arch */
285 static enum sparc_arch_types default_arch_type
;
287 static struct sparc_arch
*
288 lookup_arch (const char *name
)
290 struct sparc_arch
*sa
;
292 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
293 if (strcmp (sa
->name
, name
) == 0)
295 if (sa
->name
== NULL
)
300 /* Initialize the default opcode arch and word size from the default
301 architecture name. */
304 init_default_arch (void)
306 struct sparc_arch
*sa
= lookup_arch (default_arch
);
309 || sa
->default_arch_size
== 0)
310 as_fatal (_("Invalid default architecture, broken assembler."));
312 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
313 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
314 as_fatal (_("Bad opcode table, broken assembler."));
315 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
317 default_arch_type
= sa
->arch_type
;
320 /* Called by TARGET_MACH. */
325 /* We don't get a chance to initialize anything before we're called,
326 so handle that now. */
327 if (! default_init_p
)
328 init_default_arch ();
330 return sparc_arch_size
== 64 ? bfd_mach_sparc_v9
: bfd_mach_sparc
;
333 /* Called by TARGET_FORMAT. */
336 sparc_target_format (void)
338 /* We don't get a chance to initialize anything before we're called,
339 so handle that now. */
340 if (! default_init_p
)
341 init_default_arch ();
344 return "elf32-sparc-vxworks";
347 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
351 * Invocation line includes a switch not recognized by the base assembler.
352 * See if it's a processor-specific option. These are:
355 * Warn on architecture bumps. See also -A.
357 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
358 * Standard 32 bit architectures.
360 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
361 * This used to only mean 64 bits, but properly specifying it
362 * complicated gcc's ASM_SPECs, so now opcode selection is
363 * specified orthogonally to word size (except when specifying
364 * the default, but that is an internal implementation detail).
365 * -Av8plus, -Av8plusa, -Av8plusb
366 * Same as -Av9{,a,b}.
367 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
368 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
370 * -xarch=v9, -xarch=v9a, -xarch=v9b
371 * Same as -Av9{,a,b} -64, for compatibility with Sun's
374 * Select the architecture and possibly the file format.
375 * Instructions or features not supported by the selected
376 * architecture cause fatal errors.
378 * The default is to start at v6, and bump the architecture up
379 * whenever an instruction is seen at a higher level. In 32 bit
380 * environments, v9 is not bumped up to, the user must pass
383 * If -bump is specified, a warning is printing when bumping to
386 * If an architecture is specified, all instructions must match
387 * that architecture. Any higher level instructions are flagged
388 * as errors. Note that in the 32 bit environment specifying
389 * -Av8plus does not automatically create a v8plus object file, a
390 * v9 insn must be seen.
392 * If both an architecture and -bump are specified, the
393 * architecture starts at the specified level, but bumps are
394 * warnings. Note that we can't set `current_architecture' to
395 * the requested level in this case: in the 32 bit environment,
396 * we still must avoid creating v8plus object files unless v9
400 * Bumping between incompatible architectures is always an
401 * error. For example, from sparclite to v9.
404 const char *md_shortopts
= "A:K:VQ:sq";
405 struct option md_longopts
[] = {
406 #define OPTION_BUMP (OPTION_MD_BASE)
407 {"bump", no_argument
, NULL
, OPTION_BUMP
},
408 #define OPTION_SPARC (OPTION_MD_BASE + 1)
409 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
410 #define OPTION_XARCH (OPTION_MD_BASE + 2)
411 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
412 #define OPTION_32 (OPTION_MD_BASE + 3)
413 {"32", no_argument
, NULL
, OPTION_32
},
414 #define OPTION_64 (OPTION_MD_BASE + 4)
415 {"64", no_argument
, NULL
, OPTION_64
},
416 #define OPTION_TSO (OPTION_MD_BASE + 5)
417 {"TSO", no_argument
, NULL
, OPTION_TSO
},
418 #define OPTION_PSO (OPTION_MD_BASE + 6)
419 {"PSO", no_argument
, NULL
, OPTION_PSO
},
420 #define OPTION_RMO (OPTION_MD_BASE + 7)
421 {"RMO", no_argument
, NULL
, OPTION_RMO
},
422 #ifdef SPARC_BIENDIAN
423 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
424 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
425 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
426 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
428 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
429 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
430 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
431 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
432 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
433 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
434 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
435 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
436 #define OPTION_RELAX (OPTION_MD_BASE + 14)
437 {"relax", no_argument
, NULL
, OPTION_RELAX
},
438 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
439 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
440 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
441 {"dcti-couples-detect", no_argument
, NULL
, OPTION_DCTI_COUPLES_DETECT
},
442 {NULL
, no_argument
, NULL
, 0}
445 size_t md_longopts_size
= sizeof (md_longopts
);
448 md_parse_option (int c
, const char *arg
)
450 /* We don't get a chance to initialize anything before we're called,
451 so handle that now. */
452 if (! default_init_p
)
453 init_default_arch ();
459 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
463 if (startswith (arg
, "v9"))
464 md_parse_option (OPTION_64
, NULL
);
467 if (startswith (arg
, "v8")
468 || startswith (arg
, "v7")
469 || startswith (arg
, "v6")
470 || !strcmp (arg
, "sparclet")
471 || !strcmp (arg
, "sparclite")
472 || !strcmp (arg
, "sparc86x"))
473 md_parse_option (OPTION_32
, NULL
);
479 struct sparc_arch
*sa
;
480 enum sparc_opcode_arch_val opcode_arch
;
482 sa
= lookup_arch (arg
);
484 || ! sa
->user_option_p
)
486 if (c
== OPTION_XARCH
)
487 as_bad (_("invalid architecture -xarch=%s"), arg
);
489 as_bad (_("invalid architecture -A%s"), arg
);
493 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
494 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
495 as_fatal (_("Bad opcode table, broken assembler."));
497 if (!architecture_requested
498 || opcode_arch
> max_architecture
)
499 max_architecture
= opcode_arch
;
501 /* The allowed hardware capabilities are the implied by the
502 opcodes arch plus any extra capabilities defined in the GAS
506 | ((uint64_t) sparc_opcode_archs
[opcode_arch
].hwcaps2
<< 32)
507 | ((uint64_t) sa
->hwcap2_allowed
<< 32)
508 | sparc_opcode_archs
[opcode_arch
].hwcaps
509 | sa
->hwcap_allowed
);
510 architecture_requested
= 1;
515 /* Ignore -sparc, used by SunOS make default .s.o rule. */
518 case OPTION_ENFORCE_ALIGNED_DATA
:
519 enforce_aligned_data
= 1;
522 #ifdef SPARC_BIENDIAN
523 case OPTION_LITTLE_ENDIAN
:
524 target_big_endian
= 0;
525 if (default_arch_type
!= sparclet
)
526 as_fatal ("This target does not support -EL");
528 case OPTION_LITTLE_ENDIAN_DATA
:
529 target_little_endian_data
= 1;
530 target_big_endian
= 0;
531 if (default_arch_type
!= sparc86x
532 && default_arch_type
!= v9
)
533 as_fatal ("This target does not support --little-endian-data");
535 case OPTION_BIG_ENDIAN
:
536 target_big_endian
= 1;
543 const char **list
, **l
;
545 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
546 list
= bfd_target_list ();
547 for (l
= list
; *l
!= NULL
; l
++)
549 if (sparc_arch_size
== 32)
551 if (startswith (*l
, "elf32-sparc"))
556 if (startswith (*l
, "elf64-sparc"))
561 as_fatal (_("No compiled in support for %d bit object file format"),
565 if (sparc_arch_size
== 64
566 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
567 max_architecture
= SPARC_OPCODE_ARCH_V9
;
572 sparc_memory_model
= MM_TSO
;
576 sparc_memory_model
= MM_PSO
;
580 sparc_memory_model
= MM_RMO
;
588 /* Qy - do emit .comment
589 Qn - do not emit .comment. */
593 /* Use .stab instead of .stab.excl. */
597 /* quick -- Native assembler does fewer checks. */
601 if (strcmp (arg
, "PIC") != 0)
602 as_warn (_("Unrecognized option following -K"));
607 case OPTION_NO_UNDECLARED_REGS
:
608 no_undeclared_regs
= 1;
611 case OPTION_UNDECLARED_REGS
:
612 no_undeclared_regs
= 0;
619 case OPTION_NO_RELAX
:
623 case OPTION_DCTI_COUPLES_DETECT
:
624 dcti_couples_detect
= 1;
635 md_show_usage (FILE *stream
)
637 const struct sparc_arch
*arch
;
640 /* We don't get a chance to initialize anything before we're called,
641 so handle that now. */
642 if (! default_init_p
)
643 init_default_arch ();
645 fprintf (stream
, _("SPARC options:\n"));
647 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
649 if (!arch
->user_option_p
)
651 if (arch
!= &sparc_arch_table
[0])
652 fprintf (stream
, " | ");
653 if (column
+ strlen (arch
->name
) > 70)
656 fputc ('\n', stream
);
658 column
+= 5 + 2 + strlen (arch
->name
);
659 fprintf (stream
, "-A%s", arch
->name
);
661 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
663 if (!arch
->user_option_p
)
665 fprintf (stream
, " | ");
666 if (column
+ strlen (arch
->name
) > 65)
669 fputc ('\n', stream
);
671 column
+= 5 + 7 + strlen (arch
->name
);
672 fprintf (stream
, "-xarch=%s", arch
->name
);
674 fprintf (stream
, _("\n\
675 specify variant of SPARC architecture\n\
676 -bump warn when assembler switches architectures\n\
678 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
679 -relax relax jumps and branches (default)\n\
680 -no-relax avoid changing any jumps and branches\n"));
681 fprintf (stream
, _("\
682 -32 create 32 bit object file\n\
683 -64 create 64 bit object file\n"));
684 fprintf (stream
, _("\
685 [default is %d]\n"), default_arch_size
);
686 fprintf (stream
, _("\
687 -TSO use Total Store Ordering\n\
688 -PSO use Partial Store Ordering\n\
689 -RMO use Relaxed Memory Ordering\n"));
690 fprintf (stream
, _("\
691 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
692 fprintf (stream
, _("\
693 -KPIC generate PIC\n\
694 -V print assembler version number\n\
695 -undeclared-regs ignore application global register usage without\n\
696 appropriate .register directive (default)\n\
697 -no-undeclared-regs force error on application global register usage\n\
698 without appropriate .register directive\n\
699 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
703 #ifdef SPARC_BIENDIAN
704 fprintf (stream
, _("\
705 -EL generate code for a little endian machine\n\
706 -EB generate code for a big endian machine\n\
707 --little-endian-data generate code for a machine having big endian\n\
708 instructions and little endian data.\n"));
712 /* Native operand size opcode translation. */
718 } native_op_table
[] =
720 {"ldn", "ld", "ldx"},
721 {"ldna", "lda", "ldxa"},
722 {"stn", "st", "stx"},
723 {"stna", "sta", "stxa"},
724 {"slln", "sll", "sllx"},
725 {"srln", "srl", "srlx"},
726 {"sran", "sra", "srax"},
727 {"casn", "cas", "casx"},
728 {"casna", "casa", "casxa"},
729 {"clrn", "clr", "clrx"},
733 /* sparc64 privileged and hyperprivileged registers. */
735 struct priv_reg_entry
741 struct priv_reg_entry priv_reg_table
[] =
762 {NULL
, -1}, /* End marker. */
765 struct priv_reg_entry hpriv_reg_table
[] =
775 {"hstick_offset", 28},
776 {"hstick_enable", 29},
778 {NULL
, -1}, /* End marker. */
781 /* v9a or later specific ancillary state registers. */
783 struct priv_reg_entry v9a_asr_table
[] =
786 {"sys_tick_cmpr", 25},
790 {"softint_clear", 21},
801 {"clear_softint", 21},
802 {NULL
, -1}, /* End marker. */
806 cmp_reg_entry (const void *parg
, const void *qarg
)
808 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
809 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
811 if (p
->name
== q
->name
)
813 else if (p
->name
== NULL
)
815 else if (q
->name
== NULL
)
818 return strcmp (q
->name
, p
->name
);
821 /* sparc %-pseudo-operations. */
824 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
825 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
827 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
828 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
830 instruction. (Generally they can appear
831 anywhere an immediate operand is
835 /* The name as it appears in assembler. */
837 /* The reloc this pseudo-op translates to. */
838 bfd_reloc_code_real_type reloc
;
839 /* Flags. See F_POP_* above. */
843 struct pop_entry pop_table
[] =
845 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
846 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
847 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
848 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
849 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
850 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
851 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
852 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
853 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
854 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
855 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
856 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
857 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
858 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
859 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
860 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
861 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
862 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
863 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
864 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
865 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
866 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
867 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
868 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
869 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
870 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
871 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
872 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
873 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
874 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
875 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
876 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
877 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
878 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
879 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
880 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
881 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
884 /* Table of %-names that can appear in a sparc assembly program. This
885 table is initialized in md_begin and contains entries for each
886 privileged/hyperprivileged/alternate register and %-pseudo-op. */
899 enum perc_entry_type type
;
900 /* Name of the %-entity. */
904 /* Value. Either a pop or a reg depending on type.*/
907 struct pop_entry
*pop
;
908 struct priv_reg_entry
*reg
;
912 #define NUM_PERC_ENTRIES \
913 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
914 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
915 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
916 + ARRAY_SIZE (pop_table) \
919 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
922 cmp_perc_entry (const void *parg
, const void *qarg
)
924 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
925 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
927 if (p
->name
== q
->name
)
929 else if (p
->name
== NULL
)
931 else if (q
->name
== NULL
)
934 return strcmp (q
->name
, p
->name
);
937 /* This function is called once, at assembler startup time. It should
938 set up all the tables, etc. that the MD part of the assembler will
947 /* We don't get a chance to initialize anything before md_parse_option
948 is called, and it may not be called, so handle default initialization
949 now if not already done. */
950 if (! default_init_p
)
951 init_default_arch ();
953 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
954 op_hash
= str_htab_create ();
956 while (i
< (unsigned int) sparc_num_opcodes
)
958 const char *name
= sparc_opcodes
[i
].name
;
959 if (str_hash_insert (op_hash
, name
, &sparc_opcodes
[i
], 0) != NULL
)
961 as_bad (_("duplicate %s"), name
);
966 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
968 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
969 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
974 while (i
< (unsigned int) sparc_num_opcodes
975 && !strcmp (sparc_opcodes
[i
].name
, name
));
978 for (i
= 0; native_op_table
[i
].name
; i
++)
980 const struct sparc_opcode
*insn
;
981 const char *name
= ((sparc_arch_size
== 32)
982 ? native_op_table
[i
].name32
983 : native_op_table
[i
].name64
);
984 insn
= (struct sparc_opcode
*) str_hash_find (op_hash
, name
);
987 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
988 name
, native_op_table
[i
].name
);
991 else if (str_hash_insert (op_hash
, native_op_table
[i
].name
, insn
, 0))
993 as_bad (_("duplicate %s"), native_op_table
[i
].name
);
999 as_fatal (_("Broken assembler. No assembly attempted."));
1001 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1002 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1003 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1004 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1005 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1006 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1008 /* If -bump, record the architecture level at which we start issuing
1009 warnings. The behaviour is different depending upon whether an
1010 architecture was explicitly specified. If it wasn't, we issue warnings
1011 for all upwards bumps. If it was, we don't start issuing warnings until
1012 we need to bump beyond the requested architecture or when we bump between
1013 conflicting architectures. */
1016 && architecture_requested
)
1018 /* `max_architecture' records the requested architecture.
1019 Issue warnings if we go above it. */
1020 warn_after_architecture
= max_architecture
;
1023 /* Find the highest architecture level that doesn't conflict with
1024 the requested one. */
1027 || !architecture_requested
)
1029 enum sparc_opcode_arch_val current_max_architecture
1032 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1033 max_architecture
> warn_after_architecture
;
1035 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1036 current_max_architecture
))
1040 /* Prepare the tables of %-pseudo-ops. */
1042 struct priv_reg_entry
*reg_tables
[]
1043 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1044 struct priv_reg_entry
**reg_table
;
1047 /* Add registers. */
1048 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1050 struct priv_reg_entry
*reg
;
1051 for (reg
= *reg_table
; reg
->name
; reg
++)
1053 struct perc_entry
*p
= &perc_table
[entry
++];
1054 p
->type
= perc_entry_reg
;
1055 p
->name
= reg
->name
;
1056 p
->len
= strlen (reg
->name
);
1061 /* Add %-pseudo-ops. */
1062 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1064 struct perc_entry
*p
= &perc_table
[entry
++];
1065 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1066 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1067 p
->name
= pop_table
[i
].name
;
1068 p
->len
= strlen (pop_table
[i
].name
);
1069 p
->pop
= &pop_table
[i
];
1072 /* Last entry is the sentinel. */
1073 perc_table
[entry
].type
= perc_entry_none
;
1075 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1076 sizeof (perc_table
[0]), cmp_perc_entry
);
1081 /* Called after all assembly has been done. */
1084 sparc_md_finish (void)
1088 int hwcaps
, hwcaps2
;
1091 if (sparc_arch_size
== 64)
1092 switch (current_architecture
)
1094 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1095 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1096 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1097 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1098 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1099 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1100 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1101 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v9m8
; break;
1102 default: mach
= bfd_mach_sparc_v9
; break;
1105 switch (current_architecture
)
1107 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1108 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1109 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1110 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1111 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1112 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1113 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1114 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1115 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1116 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v8plusm8
; break;
1117 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1118 be but for now it is (since that's the way it's always been
1120 default: mach
= bfd_mach_sparc
; break;
1122 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1125 hwcaps
= hwcap_seen
& U0xffffffff
;
1126 hwcaps2
= hwcap_seen
>> 32;
1129 && !bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
1130 Tag_GNU_Sparc_HWCAPS
, hwcaps
))
1132 && !bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
1133 Tag_GNU_Sparc_HWCAPS2
, hwcaps2
)))
1134 as_fatal (_("error adding attribute: %s"),
1135 bfd_errmsg (bfd_get_error ()));
1139 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1142 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1146 /* Sign-extend the value from the architecture word size, so that
1147 0xffffffff is always considered -1 on sparc32. */
1148 if (sparc_arch_size
== 32)
1150 bfd_vma sign
= (bfd_vma
) 1 << 31;
1151 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1160 /* Return non-zero if VAL is in the range 0 to MAX. */
1163 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1170 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1171 (e.g. -15 to +31). */
1174 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1180 if (val
< ~(max
>> 1))
1186 sparc_ffs (unsigned int mask
)
1193 for (i
= 0; (mask
& 1) == 0; ++i
)
1198 /* Implement big shift right. */
1200 BSR (bfd_vma val
, int amount
)
1202 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1203 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1204 return val
>> amount
;
1207 /* For communication between sparc_ip and get_expression. */
1208 static char *expr_parse_end
;
1210 /* Values for `special_case'.
1211 Instructions that require weird handling because they're longer than
1213 #define SPECIAL_CASE_NONE 0
1214 #define SPECIAL_CASE_SET 1
1215 #define SPECIAL_CASE_SETSW 2
1216 #define SPECIAL_CASE_SETX 3
1217 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1218 #define SPECIAL_CASE_FDIV 4
1220 /* Bit masks of various insns. */
1221 #define NOP_INSN 0x01000000
1222 #define OR_INSN 0x80100000
1223 #define XOR_INSN 0x80180000
1224 #define FMOVS_INSN 0x81A00020
1225 #define SETHI_INSN 0x01000000
1226 #define SLLX_INSN 0x81281000
1227 #define SRA_INSN 0x81380000
1229 /* The last instruction to be assembled. */
1230 static const struct sparc_opcode
*last_insn
;
1231 /* The assembled opcode of `last_insn'. */
1232 static unsigned long last_opcode
;
1234 /* Handle the set and setuw synthetic instructions. */
1237 synthetize_setuw (const struct sparc_opcode
*insn
)
1239 int need_hi22_p
= 0;
1240 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1242 if (the_insn
.exp
.X_op
== O_constant
)
1244 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1246 if (sizeof (offsetT
) > 4
1247 && (the_insn
.exp
.X_add_number
< 0
1248 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1249 as_warn (_("set: number not in 0..4294967295 range"));
1253 if (sizeof (offsetT
) > 4
1254 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1255 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1256 as_warn (_("set: number not in -2147483648..4294967295 range"));
1257 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1261 /* See if operand is absolute and small; skip sethi if so. */
1262 if (the_insn
.exp
.X_op
!= O_constant
1263 || the_insn
.exp
.X_add_number
>= (1 << 12)
1264 || the_insn
.exp
.X_add_number
< -(1 << 12))
1266 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1267 | ((the_insn
.exp
.X_add_number
>> 10)
1268 & (the_insn
.exp
.X_op
== O_constant
1270 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1271 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1272 output_insn (insn
, &the_insn
);
1276 /* See if operand has no low-order bits; skip OR if so. */
1277 if (the_insn
.exp
.X_op
!= O_constant
1278 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1281 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1283 | (the_insn
.exp
.X_add_number
1284 & (the_insn
.exp
.X_op
!= O_constant
1285 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1286 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1287 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1288 output_insn (insn
, &the_insn
);
1292 /* Handle the setsw synthetic instruction. */
1295 synthetize_setsw (const struct sparc_opcode
*insn
)
1299 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1301 if (the_insn
.exp
.X_op
!= O_constant
)
1303 synthetize_setuw (insn
);
1305 /* Need to sign extend it. */
1306 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1307 the_insn
.reloc
= BFD_RELOC_NONE
;
1308 output_insn (insn
, &the_insn
);
1312 if (sizeof (offsetT
) > 4
1313 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1314 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1315 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1317 low32
= the_insn
.exp
.X_add_number
;
1321 synthetize_setuw (insn
);
1327 the_insn
.reloc
= BFD_RELOC_NONE
;
1328 /* See if operand is absolute and small; skip sethi if so. */
1329 if (low32
< -(1 << 12))
1331 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1332 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1333 output_insn (insn
, &the_insn
);
1334 low32
= 0x1c00 | (low32
& 0x3ff);
1335 opc
= RS1 (rd
) | XOR_INSN
;
1338 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1339 | (low32
& 0x1fff));
1340 output_insn (insn
, &the_insn
);
1343 /* Handle the setx synthetic instruction. */
1346 synthetize_setx (const struct sparc_opcode
*insn
)
1348 int upper32
, lower32
;
1349 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1350 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1352 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1353 int need_xor10_p
= 0;
1355 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1356 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1357 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1360 upper_dstreg
= tmpreg
;
1361 /* The tmp reg should not be the dst reg. */
1362 if (tmpreg
== dstreg
)
1363 as_warn (_("setx: temporary register same as destination register"));
1365 /* ??? Obviously there are other optimizations we can do
1366 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1367 doing some of these. Later. If you do change things, try to
1368 change all of this to be table driven as well. */
1369 /* What to output depends on the number if it's constant.
1370 Compute that first, then output what we've decided upon. */
1371 if (the_insn
.exp
.X_op
!= O_constant
)
1373 if (sparc_arch_size
== 32)
1375 /* When arch size is 32, we want setx to be equivalent
1376 to setuw for anything but constants. */
1377 the_insn
.exp
.X_add_number
&= 0xffffffff;
1378 synthetize_setuw (insn
);
1381 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1387 /* Reset X_add_number, we've extracted it as upper32/lower32.
1388 Otherwise fixup_segment will complain about not being able to
1389 write an 8 byte number in a 4 byte field. */
1390 the_insn
.exp
.X_add_number
= 0;
1392 /* Only need hh22 if `or' insn can't handle constant. */
1393 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1396 /* Does bottom part (after sethi) have bits? */
1397 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1398 /* No hh22, but does upper32 still have bits we can't set
1400 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1403 /* If the lower half is all zero, we build the upper half directly
1404 into the dst reg. */
1406 /* Need lower half if number is zero or 0xffffffff00000000. */
1407 || (! need_hh22_p
&& ! need_hm10_p
))
1409 /* No need for sethi if `or' insn can handle constant. */
1410 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1411 /* Note that we can't use a negative constant in the `or'
1412 insn unless the upper 32 bits are all ones. */
1413 || (lower32
< 0 && upper32
!= -1)
1414 || (lower32
>= 0 && upper32
== -1))
1417 if (need_hi22_p
&& upper32
== -1)
1420 /* Does bottom part (after sethi) have bits? */
1421 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1423 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1424 /* Need `or' if we didn't set anything else. */
1425 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1429 /* Output directly to dst reg if lower 32 bits are all zero. */
1430 upper_dstreg
= dstreg
;
1433 if (!upper_dstreg
&& dstreg
)
1434 as_warn (_("setx: illegal temporary register g0"));
1438 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1439 | ((upper32
>> 10) & 0x3fffff));
1440 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1441 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1442 output_insn (insn
, &the_insn
);
1447 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1448 | (((need_xor10_p
? ~lower32
: lower32
)
1449 >> 10) & 0x3fffff));
1450 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1451 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1452 output_insn (insn
, &the_insn
);
1457 the_insn
.opcode
= (OR_INSN
1458 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1461 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1462 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1463 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1464 output_insn (insn
, &the_insn
);
1469 /* FIXME: One nice optimization to do here is to OR the low part
1470 with the highpart if hi22 isn't needed and the low part is
1472 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1475 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1476 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1477 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1478 output_insn (insn
, &the_insn
);
1481 /* If we needed to build the upper part, shift it into place. */
1482 if (need_hh22_p
|| need_hm10_p
)
1484 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1486 the_insn
.reloc
= BFD_RELOC_NONE
;
1487 output_insn (insn
, &the_insn
);
1490 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1493 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1494 | 0x1c00 | (lower32
& 0x3ff));
1495 the_insn
.reloc
= BFD_RELOC_NONE
;
1496 output_insn (insn
, &the_insn
);
1499 /* If we needed to build both upper and lower parts, OR them together. */
1500 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1502 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1504 the_insn
.reloc
= BFD_RELOC_NONE
;
1505 output_insn (insn
, &the_insn
);
1509 /* Main entry point to assemble one instruction. */
1512 md_assemble (char *str
)
1514 const struct sparc_opcode
*insn
;
1518 special_case
= sparc_ip (str
, &insn
);
1522 /* Certain instructions may not appear on delay slots. Check for
1523 these situations. */
1524 if (last_insn
!= NULL
1525 && (last_insn
->flags
& F_DELAYED
) != 0)
1527 /* Before SPARC V9 the effect of having a delayed branch
1528 instruction in the delay slot of a conditional delayed branch
1531 In SPARC V9 DCTI couples are well defined.
1533 However, starting with the UltraSPARC Architecture 2005, DCTI
1534 couples (of all kind) are deprecated and should not be used,
1535 as they may be slow or behave differently to what the
1536 programmer expects. */
1537 if (dcti_couples_detect
1538 && (insn
->flags
& F_DELAYED
) != 0
1539 && ((max_architecture
< SPARC_OPCODE_ARCH_V9
1540 && (last_insn
->flags
& F_CONDBR
) != 0)
1541 || max_architecture
>= SPARC_OPCODE_ARCH_V9C
))
1542 as_warn (_("unpredictable DCTI couple"));
1545 /* We warn about attempts to put a floating point branch in a
1546 delay slot, unless the delay slot has been annulled. */
1547 if ((insn
->flags
& F_FBR
) != 0
1548 /* ??? This test isn't completely accurate. We assume anything with
1549 F_{UNBR,CONDBR,FBR} set is annullable. */
1550 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1551 || (last_opcode
& ANNUL
) == 0))
1552 as_warn (_("FP branch in delay slot"));
1555 /* SPARC before v9 does not allow a floating point compare
1556 directly before a floating point branch. Insert a nop
1557 instruction if needed, with a warning. */
1558 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1559 && last_insn
!= NULL
1560 && (insn
->flags
& F_FBR
) != 0
1561 && (last_insn
->flags
& F_FLOAT
) != 0
1562 && (last_insn
->match
& OP3 (0x35)) == OP3 (0x35))
1564 struct sparc_it nop_insn
;
1566 nop_insn
.opcode
= NOP_INSN
;
1567 nop_insn
.reloc
= BFD_RELOC_NONE
;
1568 output_insn (insn
, &nop_insn
);
1569 as_warn (_("FP branch preceded by FP compare; NOP inserted"));
1572 switch (special_case
)
1574 case SPECIAL_CASE_NONE
:
1576 output_insn (insn
, &the_insn
);
1579 case SPECIAL_CASE_SETSW
:
1580 synthetize_setsw (insn
);
1583 case SPECIAL_CASE_SET
:
1584 synthetize_setuw (insn
);
1587 case SPECIAL_CASE_SETX
:
1588 synthetize_setx (insn
);
1591 case SPECIAL_CASE_FDIV
:
1593 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1595 output_insn (insn
, &the_insn
);
1597 /* According to information leaked from Sun, the "fdiv" instructions
1598 on early SPARC machines would produce incorrect results sometimes.
1599 The workaround is to add an fmovs of the destination register to
1600 itself just after the instruction. This was true on machines
1601 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1602 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1603 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1604 output_insn (insn
, &the_insn
);
1609 as_fatal (_("failed special case insn sanity check"));
1614 get_hwcap_name (uint64_t mask
)
1616 if (mask
& HWCAP_MUL32
)
1618 if (mask
& HWCAP_DIV32
)
1620 if (mask
& HWCAP_FSMULD
)
1622 if (mask
& HWCAP_V8PLUS
)
1624 if (mask
& HWCAP_POPC
)
1626 if (mask
& HWCAP_VIS
)
1628 if (mask
& HWCAP_VIS2
)
1630 if (mask
& HWCAP_ASI_BLK_INIT
)
1631 return "ASIBlkInit";
1632 if (mask
& HWCAP_FMAF
)
1634 if (mask
& HWCAP_VIS3
)
1636 if (mask
& HWCAP_HPC
)
1638 if (mask
& HWCAP_RANDOM
)
1640 if (mask
& HWCAP_TRANS
)
1642 if (mask
& HWCAP_FJFMAU
)
1644 if (mask
& HWCAP_IMA
)
1646 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1648 if (mask
& HWCAP_AES
)
1650 if (mask
& HWCAP_DES
)
1652 if (mask
& HWCAP_KASUMI
)
1654 if (mask
& HWCAP_CAMELLIA
)
1656 if (mask
& HWCAP_MD5
)
1658 if (mask
& HWCAP_SHA1
)
1660 if (mask
& HWCAP_SHA256
)
1662 if (mask
& HWCAP_SHA512
)
1664 if (mask
& HWCAP_MPMUL
)
1666 if (mask
& HWCAP_MONT
)
1668 if (mask
& HWCAP_PAUSE
)
1670 if (mask
& HWCAP_CBCOND
)
1672 if (mask
& HWCAP_CRC32C
)
1676 if (mask
& HWCAP2_FJATHPLUS
)
1678 if (mask
& HWCAP2_VIS3B
)
1680 if (mask
& HWCAP2_ADP
)
1682 if (mask
& HWCAP2_SPARC5
)
1684 if (mask
& HWCAP2_MWAIT
)
1686 if (mask
& HWCAP2_XMPMUL
)
1688 if (mask
& HWCAP2_XMONT
)
1690 if (mask
& HWCAP2_NSEC
)
1692 if (mask
& HWCAP2_SPARC6
)
1694 if (mask
& HWCAP2_ONADDSUB
)
1696 if (mask
& HWCAP2_ONMUL
)
1698 if (mask
& HWCAP2_ONDIV
)
1700 if (mask
& HWCAP2_DICTUNP
)
1702 if (mask
& HWCAP2_FPCMPSHL
)
1704 if (mask
& HWCAP2_RLE
)
1706 if (mask
& HWCAP2_SHA3
)
1712 /* Subroutine of md_assemble to do the actual parsing. */
1715 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1717 const char *error_message
= "";
1721 const struct sparc_opcode
*insn
;
1723 unsigned long opcode
;
1724 unsigned int mask
= 0;
1728 int special_case
= SPECIAL_CASE_NONE
;
1729 const sparc_asi
*sasi
= NULL
;
1736 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1753 as_bad (_("Unknown opcode: `%s'"), str
);
1755 return special_case
;
1757 insn
= (struct sparc_opcode
*) str_hash_find (op_hash
, str
);
1761 as_bad (_("Unknown opcode: `%s'"), str
);
1762 return special_case
;
1772 opcode
= insn
->match
;
1773 memset (&the_insn
, '\0', sizeof (the_insn
));
1774 the_insn
.reloc
= BFD_RELOC_NONE
;
1777 /* Build the opcode, checking as we go to make sure that the
1779 for (args
= insn
->args
;; ++args
)
1787 /* Parse a series of masks. */
1794 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1797 error_message
= _(": invalid membar mask name");
1803 if (*s
== '|' || *s
== '+')
1811 if (! parse_const_expr_arg (&s
, &kmask
))
1813 error_message
= _(": invalid membar mask expression");
1816 if (kmask
< 0 || kmask
> 127)
1818 error_message
= _(": invalid membar mask number");
1823 opcode
|= MEMBAR (kmask
);
1831 if (! parse_const_expr_arg (&s
, &smask
))
1833 error_message
= _(": invalid siam mode expression");
1836 if (smask
< 0 || smask
> 7)
1838 error_message
= _(": invalid siam mode number");
1849 /* Parse a prefetch function. */
1852 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1854 error_message
= _(": invalid prefetch function name");
1860 if (! parse_const_expr_arg (&s
, &fcn
))
1862 error_message
= _(": invalid prefetch function expression");
1865 if (fcn
< 0 || fcn
> 31)
1867 error_message
= _(": invalid prefetch function number");
1877 /* Parse a sparc64 privileged register. */
1880 struct priv_reg_entry
*p
;
1881 unsigned int len
= 9999999; /* Init to make gcc happy. */
1884 for (p
= priv_reg_table
; p
->name
; p
++)
1885 if (p
->name
[0] == s
[0])
1887 len
= strlen (p
->name
);
1888 if (strncmp (p
->name
, s
, len
) == 0)
1894 error_message
= _(": unrecognizable privileged register");
1898 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1900 error_message
= _(": unrecognizable privileged register");
1909 error_message
= _(": unrecognizable privileged register");
1915 /* Parse a sparc64 hyperprivileged register. */
1918 struct priv_reg_entry
*p
;
1919 unsigned int len
= 9999999; /* Init to make gcc happy. */
1922 for (p
= hpriv_reg_table
; p
->name
; p
++)
1923 if (p
->name
[0] == s
[0])
1925 len
= strlen (p
->name
);
1926 if (strncmp (p
->name
, s
, len
) == 0)
1932 error_message
= _(": unrecognizable hyperprivileged register");
1936 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1938 error_message
= _(": unrecognizable hyperprivileged register");
1947 error_message
= _(": unrecognizable hyperprivileged register");
1953 /* Parse a v9a or later ancillary state register. */
1956 struct priv_reg_entry
*p
;
1957 unsigned int len
= 9999999; /* Init to make gcc happy. */
1960 for (p
= v9a_asr_table
; p
->name
; p
++)
1961 if (p
->name
[0] == s
[0])
1963 len
= strlen (p
->name
);
1964 if (strncmp (p
->name
, s
, len
) == 0)
1970 error_message
= _(": unrecognizable ancillary state register");
1974 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1976 error_message
= _(": unrecognizable ancillary state register");
1985 error_message
= _(": unrecognizable ancillary state register");
1991 if (startswith (s
, "%asr"))
1999 while (ISDIGIT (*s
))
2001 num
= num
* 10 + *s
- '0';
2005 /* We used to check here for the asr number to
2006 be between 16 and 31 in V9 and later, as
2007 mandated by the section C.1.1 "Register
2008 Names" in the SPARC spec. However, we
2009 decided to remove this restriction as a) it
2010 introduces problems when new V9 asr registers
2011 are introduced, b) the Solaris assembler
2012 doesn't implement this restriction and c) the
2013 restriction will go away in future revisions
2014 of the Oracle SPARC Architecture. */
2016 if (num
< 0 || 31 < num
)
2018 error_message
= _(": asr number must be between 0 and 31");
2022 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2027 error_message
= _(": expecting %asrN");
2034 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2038 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2044 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2049 if (s
[0] == '0' && s
[1] == 'x')
2052 while (ISXDIGIT (*s
))
2055 num
|= hex_value (*s
);
2061 while (ISDIGIT (*s
))
2063 num
= num
* 10 + *s
- '0';
2067 if (num
< 0 || num
> 31)
2069 error_message
= _(": crypto immediate must be between 0 and 31");
2073 opcode
|= RS3 (num
);
2078 error_message
= _(": expecting crypto immediate");
2083 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2084 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2085 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2087 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2088 /* These fields are unsigned, but for upward compatibility,
2089 allow negative values as well. */
2093 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2094 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2095 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2097 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2098 /* These fields are unsigned, but for upward compatibility,
2099 allow negative values as well. */
2103 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2108 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2113 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2118 if (*s
== 'p' && s
[1] == 'n')
2126 if (*s
== 'p' && s
[1] == 't')
2138 if ((startswith (s
, "%icc"))
2139 || (sparc_arch_size
== 32 && startswith (s
, "%ncc")))
2151 if ((startswith (s
, "%xcc"))
2152 || (sparc_arch_size
== 64 && startswith (s
, "%ncc")))
2164 if (startswith (s
, "%fcc0"))
2176 if (startswith (s
, "%fcc1"))
2188 if (startswith (s
, "%fcc2"))
2200 if (startswith (s
, "%fcc3"))
2208 if (startswith (s
, "%pc"))
2216 if (startswith (s
, "%tick"))
2223 case '\0': /* End of args. */
2224 if (s
[0] == ',' && s
[1] == '%')
2228 const struct perc_entry
*p
;
2230 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2231 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2232 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2234 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2237 if (s
[p
->len
+ 2] != '(')
2239 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2240 return special_case
;
2243 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2244 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2246 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2248 return special_case
;
2251 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2252 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2253 || the_insn
.exp
.X_add_number
!= 0
2254 || the_insn
.exp
.X_add_symbol
2255 != symbol_find_or_make ("__tls_get_addr")))
2257 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2259 return special_case
;
2262 the_insn
.reloc
= p
->pop
->reloc
;
2263 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2266 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2269 else if (*s1
== ')')
2278 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2279 return special_case
;
2283 (void) get_expression (s
);
2303 case '[': /* These must match exactly. */
2311 case '#': /* Must be at least one digit. */
2314 while (ISDIGIT (*s
))
2322 case 'C': /* Coprocessor state register. */
2323 if (startswith (s
, "%csr"))
2330 case 'b': /* Next operand is a coprocessor register. */
2333 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2338 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2352 opcode
|= mask
<< 14;
2360 opcode
|= mask
<< 25;
2366 case 'r': /* next operand must be a register */
2376 case 'f': /* frame pointer */
2384 case 'g': /* global register */
2393 case 'i': /* in register */
2397 mask
= c
- '0' + 24;
2402 case 'l': /* local register */
2406 mask
= (c
- '0' + 16);
2411 case 'o': /* out register */
2415 mask
= (c
- '0' + 8);
2420 case 's': /* stack pointer */
2428 case 'r': /* any register */
2429 if (!ISDIGIT ((c
= *s
++)))
2446 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2462 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2463 && no_undeclared_regs
&& ! globals
[mask
])
2464 as_bad (_("detected global register use not covered by .register pseudo-op"));
2466 /* Got the register, now figure out where
2467 it goes in the opcode. */
2471 opcode
|= mask
<< 14;
2479 opcode
|= mask
<< 25;
2483 opcode
|= (mask
<< 25) | (mask
<< 14);
2487 opcode
|= (mask
<< 25) | (mask
<< 0);
2493 case 'e': /* next operand is a floating point register */
2516 && ((format
= *s
) == 'f'
2521 for (mask
= 0; ISDIGIT (*s
); ++s
)
2523 mask
= 10 * mask
+ (*s
- '0');
2524 } /* read the number */
2534 /* register must be even numbered */
2544 /* register must be multiple of 4 */
2553 /* register must be multiple of 8 */
2557 if (*args
== '\'' && mask
< 48)
2559 /* register must be higher or equal than %f48 */
2565 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2566 error_message
= _(": There are only 64 f registers; [0-63]");
2568 error_message
= _(": There are only 32 f registers; [0-31]");
2571 else if (mask
>= 32)
2573 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2575 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2578 = _(": There are only 32 single precision f registers; [0-31]");
2582 mask
-= 31; /* wrap high bit */
2586 error_message
= _(": There are only 32 f registers; [0-31]");
2594 } /* if not an 'f' register. */
2596 if (*args
== '}' && mask
!= RS2 (opcode
))
2599 = _(": Instruction requires frs2 and frsd must be the same register");
2609 opcode
|= RS1 (mask
);
2616 opcode
|= RS2 (mask
);
2620 opcode
|= RS2 (mask
& 0xe);
2625 opcode
|= RS3 (mask
);
2633 opcode
|= RD (mask
);
2642 if (startswith (s
, "%fsr"))
2650 if (startswith (s
, "%efsr"))
2657 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2658 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2661 case 'l': /* 22 bit PC relative immediate */
2662 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2666 case 'L': /* 30 bit immediate */
2667 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2672 case 'n': /* 22 bit immediate */
2673 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2676 case 'i': /* 13 bit immediate */
2677 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2687 const char *op_arg
= NULL
;
2688 static expressionS op_exp
;
2689 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2691 /* Check for %hi, etc. */
2694 const struct perc_entry
*p
;
2696 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2697 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2698 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2700 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2703 if (s
[p
->len
+ 1] != '(')
2705 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2706 return special_case
;
2710 the_insn
.reloc
= p
->pop
->reloc
;
2712 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2715 /* Note that if the get_expression() fails, we will still
2716 have created U entries in the symbol table for the
2717 'symbols' in the input string. Try not to create U
2718 symbols for registers, etc. */
2720 /* This stuff checks to see if the expression ends in
2721 +%reg. If it does, it removes the register from
2722 the expression, and re-sets 's' to point to the
2729 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2732 else if (*s1
== ')')
2741 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2742 return special_case
;
2746 (void) get_expression (s
);
2748 if (expr_parse_end
!= s1
)
2750 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2751 return special_case
;
2754 if (*s
== ',' || *s
== ']' || !*s
)
2756 if (*s
!= '+' && *s
!= '-')
2758 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2759 return special_case
;
2763 op_exp
= the_insn
.exp
;
2764 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2767 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2770 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2772 if (s1
[-2] == '%' && s1
[-3] == '+')
2774 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2776 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2783 if (op_arg
&& s1
== s
+ 1)
2784 the_insn
.exp
.X_op
= O_absent
;
2786 (void) get_expression (s
);
2798 (void) get_expression (s
);
2806 the_insn
.exp2
= the_insn
.exp
;
2807 the_insn
.exp
= op_exp
;
2808 if (the_insn
.exp2
.X_op
== O_absent
)
2809 the_insn
.exp2
.X_op
= O_illegal
;
2810 else if (the_insn
.exp
.X_op
== O_absent
)
2812 the_insn
.exp
= the_insn
.exp2
;
2813 the_insn
.exp2
.X_op
= O_illegal
;
2815 else if (the_insn
.exp
.X_op
== O_constant
)
2817 valueT val
= the_insn
.exp
.X_add_number
;
2818 switch (the_insn
.reloc
)
2823 case BFD_RELOC_SPARC_HH22
:
2824 val
= BSR (val
, 32);
2827 case BFD_RELOC_SPARC_LM22
:
2828 case BFD_RELOC_HI22
:
2829 val
= (val
>> 10) & 0x3fffff;
2832 case BFD_RELOC_SPARC_HM10
:
2833 val
= BSR (val
, 32);
2836 case BFD_RELOC_LO10
:
2840 case BFD_RELOC_SPARC_H34
:
2845 case BFD_RELOC_SPARC_H44
:
2850 case BFD_RELOC_SPARC_M44
:
2855 case BFD_RELOC_SPARC_L44
:
2859 case BFD_RELOC_SPARC_HIX22
:
2861 val
= (val
>> 10) & 0x3fffff;
2864 case BFD_RELOC_SPARC_LOX10
:
2865 val
= (val
& 0x3ff) | 0x1c00;
2868 the_insn
.exp
= the_insn
.exp2
;
2869 the_insn
.exp
.X_add_number
+= val
;
2870 the_insn
.exp2
.X_op
= O_illegal
;
2871 the_insn
.reloc
= old_reloc
;
2873 else if (the_insn
.exp2
.X_op
!= O_constant
)
2875 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2876 return special_case
;
2880 if (old_reloc
!= BFD_RELOC_SPARC13
2881 || the_insn
.reloc
!= BFD_RELOC_LO10
2882 || sparc_arch_size
!= 64
2885 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2886 return special_case
;
2888 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2892 /* Check for constants that don't require emitting a reloc. */
2893 if (the_insn
.exp
.X_op
== O_constant
2894 && the_insn
.exp
.X_add_symbol
== 0
2895 && the_insn
.exp
.X_op_symbol
== 0)
2897 /* For pc-relative call instructions, we reject
2898 constants to get better code. */
2900 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2901 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2903 error_message
= _(": PC-relative operand can't be a constant");
2907 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2908 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2910 error_message
= _(": TLS operand can't be a constant");
2914 /* Constants that won't fit are checked in md_apply_fix
2915 and bfd_install_relocation.
2916 ??? It would be preferable to install the constants
2917 into the insn here and save having to create a fixS
2918 for each one. There already exists code to handle
2919 all the various cases (e.g. in md_apply_fix and
2920 bfd_install_relocation) so duplicating all that code
2921 here isn't right. */
2923 /* This is a special case to handle cbcond instructions
2924 properly, which can need two relocations. The first
2925 one is for the 5-bit immediate field and the latter
2926 is going to be for the WDISP10 branch part. We
2927 handle the R_SPARC_5 immediate directly here so that
2928 we don't need to add support for multiple relocations
2929 in one instruction just yet. */
2930 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
2931 && ((insn
->match
& OP(0x3)) == 0))
2933 valueT val
= the_insn
.exp
.X_add_number
;
2935 the_insn
.reloc
= BFD_RELOC_NONE
;
2936 if (! in_bitfield_range (val
, 0x1f))
2938 error_message
= _(": Immediate value in cbcond is out of range.");
2941 opcode
|= val
& 0x1f;
2962 if (! parse_sparc_asi (&s
, &sasi
))
2964 error_message
= _(": invalid ASI name");
2971 if (! parse_const_expr_arg (&s
, &asi
))
2973 error_message
= _(": invalid ASI expression");
2976 if (asi
< 0 || asi
> 255)
2978 error_message
= _(": invalid ASI number");
2982 opcode
|= ASI (asi
);
2984 } /* Alternate space. */
2987 if (startswith (s
, "%psr"))
2994 case 'q': /* Floating point queue. */
2995 if (startswith (s
, "%fq"))
3002 case 'Q': /* Coprocessor queue. */
3003 if (startswith (s
, "%cq"))
3011 if (strcmp (str
, "set") == 0
3012 || strcmp (str
, "setuw") == 0)
3014 special_case
= SPECIAL_CASE_SET
;
3017 else if (strcmp (str
, "setsw") == 0)
3019 special_case
= SPECIAL_CASE_SETSW
;
3022 else if (strcmp (str
, "setx") == 0)
3024 special_case
= SPECIAL_CASE_SETX
;
3027 else if (startswith (str
, "fdiv"))
3029 special_case
= SPECIAL_CASE_FDIV
;
3035 if (!startswith (s
, "%asi"))
3041 if (!startswith (s
, "%fprs"))
3047 if (!startswith (s
, "%mcdper"))
3053 if (!startswith (s
, "%entropy"))
3059 if (!startswith (s
, "%ccr"))
3065 if (!startswith (s
, "%tbr"))
3071 if (!startswith (s
, "%wim"))
3080 /* Parse a 2-bit immediate. */
3081 if (! parse_const_expr_arg (&s
, &imm2
))
3083 error_message
= _(": non-immdiate imm2 operand");
3086 if ((imm2
& ~0x3) != 0)
3088 error_message
= _(": imm2 immediate operand out of range (0-3)");
3092 opcode
|= ((imm2
& 0x2) << 3) | (imm2
& 0x1);
3098 char *push
= input_line_pointer
;
3101 input_line_pointer
= s
;
3103 if (e
.X_op
== O_constant
)
3105 int n
= e
.X_add_number
;
3106 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3107 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3109 opcode
|= e
.X_add_number
<< 5;
3112 as_bad (_("non-immediate OPF operand, ignored"));
3113 s
= input_line_pointer
;
3114 input_line_pointer
= push
;
3119 if (!startswith (s
, "%y"))
3127 /* Parse a sparclet cpreg. */
3129 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3131 error_message
= _(": invalid cpreg name");
3134 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3139 as_fatal (_("failed sanity check."));
3140 } /* switch on arg code. */
3142 /* Break out of for() loop. */
3144 } /* For each arg that we expect. */
3149 /* Args don't match. */
3150 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3151 && (insn
->name
== insn
[1].name
3152 || !strcmp (insn
->name
, insn
[1].name
)))
3160 as_bad (_("Illegal operands%s"), error_message
);
3161 return special_case
;
3166 /* We have a match. Now see if the architecture is OK. */
3167 /* String to use in case of architecture warning. */
3168 const char *msg_str
= str
;
3169 int needed_arch_mask
= insn
->architecture
;
3171 /* Include the ASI architecture needed as well */
3172 if (sasi
&& needed_arch_mask
> sasi
->architecture
)
3174 needed_arch_mask
= sasi
->architecture
;
3175 msg_str
= sasi
->name
;
3178 uint64_t hwcaps
= ((uint64_t) insn
->hwcaps2
<< 32) | insn
->hwcaps
;
3182 hwcap_seen
|= hwcaps
;
3187 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3188 if (! needed_arch_mask
)
3190 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3193 if (needed_arch_mask
3194 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3197 /* Can we bump up the architecture? */
3198 else if (needed_arch_mask
3199 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3201 enum sparc_opcode_arch_val needed_architecture
=
3202 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3203 & needed_arch_mask
);
3205 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3207 && needed_architecture
> warn_after_architecture
)
3209 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3210 sparc_opcode_archs
[current_architecture
].name
,
3211 sparc_opcode_archs
[needed_architecture
].name
,
3213 warn_after_architecture
= needed_architecture
;
3215 current_architecture
= needed_architecture
;
3219 | ((uint64_t) sparc_opcode_archs
[current_architecture
].hwcaps2
<< 32)
3220 | sparc_opcode_archs
[current_architecture
].hwcaps
);
3223 /* ??? This seems to be a bit fragile. What if the next entry in
3224 the opcode table is the one we want and it is supported?
3225 It is possible to arrange the table today so that this can't
3226 happen but what about tomorrow? */
3229 int arch
, printed_one_p
= 0;
3231 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3233 /* Create a list of the architectures that support the insn. */
3234 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3236 arch
= sparc_ffs (needed_arch_mask
);
3237 while ((1 << arch
) <= needed_arch_mask
)
3239 if ((1 << arch
) & needed_arch_mask
)
3243 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3250 as_bad (_("Architecture mismatch on \"%s %s\"."), str
, argsStart
);
3251 as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
3253 sparc_opcode_archs
[max_architecture
].name
);
3254 return special_case
;
3257 /* Make sure the hwcaps used by the instruction are
3258 currently enabled. */
3259 if (hwcaps
& ~hwcap_allowed
)
3261 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3263 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3265 return special_case
;
3267 } /* If no match. */
3270 } /* Forever looking for a match. */
3272 the_insn
.opcode
= opcode
;
3273 return special_case
;
3277 skip_over_keyword (char *q
)
3279 for (q
= q
+ (*q
== '#' || *q
== '%');
3280 ISALNUM (*q
) || *q
== '_';
3287 parse_sparc_asi (char **input_pointer_p
, const sparc_asi
**value_p
)
3289 const sparc_asi
*value
;
3292 p
= *input_pointer_p
;
3293 q
= skip_over_keyword(p
);
3296 value
= sparc_encode_asi (p
);
3301 *input_pointer_p
= q
;
3305 /* Parse an argument that can be expressed as a keyword.
3306 (eg: #StoreStore or %ccfr).
3307 The result is a boolean indicating success.
3308 If successful, INPUT_POINTER is updated. */
3311 parse_keyword_arg (int (*lookup_fn
) (const char *),
3312 char **input_pointerP
,
3318 p
= *input_pointerP
;
3319 q
= skip_over_keyword(p
);
3322 value
= (*lookup_fn
) (p
);
3327 *input_pointerP
= q
;
3331 /* Parse an argument that is a constant expression.
3332 The result is a boolean indicating success. */
3335 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3337 char *save
= input_line_pointer
;
3340 input_line_pointer
= *input_pointerP
;
3341 /* The next expression may be something other than a constant
3342 (say if we're not processing the right variant of the insn).
3343 Don't call expression unless we're sure it will succeed as it will
3344 signal an error (which we want to defer until later). */
3345 /* FIXME: It might be better to define md_operand and have it recognize
3346 things like %asi, etc. but continuing that route through to the end
3347 is a lot of work. */
3348 if (*input_line_pointer
== '%')
3350 input_line_pointer
= save
;
3354 *input_pointerP
= input_line_pointer
;
3355 input_line_pointer
= save
;
3356 if (exp
.X_op
!= O_constant
)
3358 *valueP
= exp
.X_add_number
;
3362 /* Subroutine of sparc_ip to parse an expression. */
3365 get_expression (char *str
)
3370 save_in
= input_line_pointer
;
3371 input_line_pointer
= str
;
3372 seg
= expression (&the_insn
.exp
);
3373 if (seg
!= absolute_section
3374 && seg
!= text_section
3375 && seg
!= data_section
3376 && seg
!= bss_section
3377 && seg
!= undefined_section
)
3379 the_insn
.error
= _("bad segment");
3380 expr_parse_end
= input_line_pointer
;
3381 input_line_pointer
= save_in
;
3384 expr_parse_end
= input_line_pointer
;
3385 input_line_pointer
= save_in
;
3389 /* Subroutine of md_assemble to output one insn. */
3392 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3394 char *toP
= frag_more (4);
3396 /* Put out the opcode. */
3397 if (INSN_BIG_ENDIAN
)
3398 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3400 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3402 /* Put out the symbol-dependent stuff. */
3403 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3405 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3406 (toP
- frag_now
->fr_literal
), /* Where. */
3411 /* Turn off overflow checking in fixup_segment. We'll do our
3412 own overflow checking in md_apply_fix. This is necessary because
3413 the insn size is 4 and fixup_segment will signal an overflow for
3414 large 8 byte quantities. */
3415 fixP
->fx_no_overflow
= 1;
3416 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3417 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3421 last_opcode
= theinsn
->opcode
;
3423 dwarf2_emit_insn (4);
3427 md_atof (int type
, char *litP
, int *sizeP
)
3429 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3432 /* Write a value out to the object file, using the appropriate
3436 md_number_to_chars (char *buf
, valueT val
, int n
)
3438 if (target_big_endian
)
3439 number_to_chars_bigendian (buf
, val
, n
);
3440 else if (target_little_endian_data
3441 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3442 /* Output debug words, which are not in allocated sections, as big
3444 number_to_chars_bigendian (buf
, val
, n
);
3445 else if (target_little_endian_data
|| ! target_big_endian
)
3446 number_to_chars_littleendian (buf
, val
, n
);
3449 /* Apply a fixS to the frags, now that we know the value it ought to
3453 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3455 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3456 offsetT val
= * (offsetT
*) valP
;
3459 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3461 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3463 /* SPARC ELF relocations don't use an addend in the data field. */
3464 if (fixP
->fx_addsy
!= NULL
)
3466 switch (fixP
->fx_r_type
)
3468 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3469 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3470 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3471 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3472 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3473 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3474 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3475 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3476 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3477 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3478 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3479 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3480 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3481 case BFD_RELOC_SPARC_TLS_IE_LD
:
3482 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3483 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3484 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3485 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3486 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3487 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3488 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3489 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3490 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3491 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3492 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3501 /* This is a hack. There should be a better way to
3502 handle this. Probably in terms of howto fields, once
3503 we can look at these fixups in terms of howtos. */
3504 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3505 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3507 /* If this is a data relocation, just output VAL. */
3509 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3511 md_number_to_chars (buf
, val
, 1);
3513 else if (fixP
->fx_r_type
== BFD_RELOC_16
3514 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3516 md_number_to_chars (buf
, val
, 2);
3518 else if (fixP
->fx_r_type
== BFD_RELOC_32
3519 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3520 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3522 md_number_to_chars (buf
, val
, 4);
3524 else if (fixP
->fx_r_type
== BFD_RELOC_64
3525 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3527 md_number_to_chars (buf
, val
, 8);
3529 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3530 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3537 /* It's a relocation against an instruction. */
3539 if (INSN_BIG_ENDIAN
)
3540 insn
= bfd_getb32 ((unsigned char *) buf
);
3542 insn
= bfd_getl32 ((unsigned char *) buf
);
3544 switch (fixP
->fx_r_type
)
3546 case BFD_RELOC_32_PCREL_S2
:
3548 /* FIXME: This increment-by-one deserves a comment of why it's
3550 if (! sparc_pic_code
3551 || fixP
->fx_addsy
== NULL
3552 || symbol_section_p (fixP
->fx_addsy
))
3555 insn
|= val
& 0x3fffffff;
3557 /* See if we have a delay slot. In that case we attempt to
3558 optimize several cases transforming CALL instructions
3559 into branches. But we can only do that if the relocation
3560 can be completely resolved here, i.e. if no undefined
3561 symbol is associated with it. */
3562 if (sparc_relax
&& fixP
->fx_addsy
== NULL
3563 && fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3567 #define XCC (2 << 20)
3568 #define COND(x) (((x)&0xf)<<25)
3569 #define CONDA COND(0x8)
3570 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3571 #define INSN_BA (F2(0,2) | CONDA)
3572 #define INSN_OR F3(2, 0x2, 0)
3573 #define INSN_NOP F2(0,4)
3577 /* If the instruction is a call with either:
3579 arithmetic instruction with rd == %o7
3580 where rs1 != %o7 and rs2 if it is register != %o7
3581 then we can optimize if the call destination is near
3582 by changing the call into a branch always. */
3583 if (INSN_BIG_ENDIAN
)
3584 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3586 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3587 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3589 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3590 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3591 || ((delay
& RD (~0)) != RD (O7
))))
3593 if ((delay
& RS1 (~0)) == RS1 (O7
)
3594 || ((delay
& F3I (~0)) == 0
3595 && (delay
& RS2 (~0)) == RS2 (O7
)))
3597 /* Ensure the branch will fit into simm22. */
3598 if ((val
& 0x3fe00000)
3599 && (val
& 0x3fe00000) != 0x3fe00000)
3601 /* Check if the arch is v9 and branch will fit
3603 if (((val
& 0x3c0000) == 0
3604 || (val
& 0x3c0000) == 0x3c0000)
3605 && (sparc_arch_size
== 64
3606 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3608 insn
= INSN_BPA
| (val
& 0x7ffff);
3611 insn
= INSN_BA
| (val
& 0x3fffff);
3612 if (fixP
->fx_where
>= 4
3613 && ((delay
& (0xffffffff ^ RS1 (~0)))
3614 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3619 if (INSN_BIG_ENDIAN
)
3620 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3622 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3623 if ((setter
& (0xffffffff ^ RD (~0)))
3624 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3631 If call foo was replaced with ba, replace
3632 or %rN, %g0, %o7 with nop. */
3633 reg
= (delay
& RS1 (~0)) >> 14;
3634 if (reg
!= ((setter
& RD (~0)) >> 25)
3635 || reg
== G0
|| reg
== O7
)
3638 if (INSN_BIG_ENDIAN
)
3639 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3641 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3646 case BFD_RELOC_SPARC_11
:
3647 if (! in_signed_range (val
, 0x7ff))
3648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3649 _("relocation overflow"));
3650 insn
|= val
& 0x7ff;
3653 case BFD_RELOC_SPARC_10
:
3654 if (! in_signed_range (val
, 0x3ff))
3655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3656 _("relocation overflow"));
3657 insn
|= val
& 0x3ff;
3660 case BFD_RELOC_SPARC_7
:
3661 if (! in_bitfield_range (val
, 0x7f))
3662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3663 _("relocation overflow"));
3667 case BFD_RELOC_SPARC_6
:
3668 if (! in_bitfield_range (val
, 0x3f))
3669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3670 _("relocation overflow"));
3674 case BFD_RELOC_SPARC_5
:
3675 if (! in_bitfield_range (val
, 0x1f))
3676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3677 _("relocation overflow"));
3681 case BFD_RELOC_SPARC_WDISP10
:
3684 || val
<= -(offsetT
) 0x808)
3685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3686 _("relocation overflow"));
3687 /* FIXME: The +1 deserves a comment. */
3688 val
= (val
>> 2) + 1;
3689 insn
|= ((val
& 0x300) << 11)
3690 | ((val
& 0xff) << 5);
3693 case BFD_RELOC_SPARC_WDISP16
:
3696 || val
<= -(offsetT
) 0x20008)
3697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3698 _("relocation overflow"));
3699 /* FIXME: The +1 deserves a comment. */
3700 val
= (val
>> 2) + 1;
3701 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3704 case BFD_RELOC_SPARC_WDISP19
:
3707 || val
<= -(offsetT
) 0x100008)
3708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3709 _("relocation overflow"));
3710 /* FIXME: The +1 deserves a comment. */
3711 val
= (val
>> 2) + 1;
3712 insn
|= val
& 0x7ffff;
3715 case BFD_RELOC_SPARC_HH22
:
3716 val
= BSR (val
, 32);
3719 case BFD_RELOC_SPARC_LM22
:
3720 case BFD_RELOC_HI22
:
3721 if (!fixP
->fx_addsy
)
3722 insn
|= (val
>> 10) & 0x3fffff;
3724 /* FIXME: Need comment explaining why we do this. */
3728 case BFD_RELOC_SPARC22
:
3729 if (val
& ~0x003fffff)
3730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3731 _("relocation overflow"));
3732 insn
|= (val
& 0x3fffff);
3735 case BFD_RELOC_SPARC_HM10
:
3736 val
= BSR (val
, 32);
3739 case BFD_RELOC_LO10
:
3740 if (!fixP
->fx_addsy
)
3741 insn
|= val
& 0x3ff;
3743 /* FIXME: Need comment explaining why we do this. */
3747 case BFD_RELOC_SPARC_OLO10
:
3749 val
+= fixP
->tc_fix_data
;
3752 case BFD_RELOC_SPARC13
:
3753 if (! in_signed_range (val
, 0x1fff))
3754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3755 _("relocation overflow"));
3756 insn
|= val
& 0x1fff;
3759 case BFD_RELOC_SPARC_WDISP22
:
3760 val
= (val
>> 2) + 1;
3762 case BFD_RELOC_SPARC_BASE22
:
3763 insn
|= val
& 0x3fffff;
3766 case BFD_RELOC_SPARC_H34
:
3767 if (!fixP
->fx_addsy
)
3771 insn
|= tval
& 0x3fffff;
3775 case BFD_RELOC_SPARC_H44
:
3776 if (!fixP
->fx_addsy
)
3780 insn
|= tval
& 0x3fffff;
3784 case BFD_RELOC_SPARC_M44
:
3785 if (!fixP
->fx_addsy
)
3786 insn
|= (val
>> 12) & 0x3ff;
3789 case BFD_RELOC_SPARC_L44
:
3790 if (!fixP
->fx_addsy
)
3791 insn
|= val
& 0xfff;
3794 case BFD_RELOC_SPARC_HIX22
:
3795 if (!fixP
->fx_addsy
)
3797 val
^= ~(offsetT
) 0;
3798 insn
|= (val
>> 10) & 0x3fffff;
3802 case BFD_RELOC_SPARC_LOX10
:
3803 if (!fixP
->fx_addsy
)
3804 insn
|= 0x1c00 | (val
& 0x3ff);
3807 case BFD_RELOC_NONE
:
3809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3810 _("bad or unhandled relocation type: 0x%02x"),
3815 if (INSN_BIG_ENDIAN
)
3816 bfd_putb32 (insn
, (unsigned char *) buf
);
3818 bfd_putl32 (insn
, (unsigned char *) buf
);
3821 /* Are we finished with this relocation now? */
3822 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3826 /* Translate internal representation of relocation info to BFD target
3830 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3832 static arelent
*relocs
[3];
3834 bfd_reloc_code_real_type code
;
3836 relocs
[0] = reloc
= XNEW (arelent
);
3839 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3840 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3841 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3843 switch (fixp
->fx_r_type
)
3851 switch (fixp
->fx_size
)
3854 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3855 _("can not do %d byte pc-relative relocation"),
3857 code
= fixp
->fx_r_type
;
3860 case 1: code
= BFD_RELOC_8_PCREL
; break;
3861 case 2: code
= BFD_RELOC_16_PCREL
; break;
3862 case 4: code
= BFD_RELOC_32_PCREL
; break;
3864 case 8: code
= BFD_RELOC_64_PCREL
; break;
3868 fixp
->fx_addnumber
= fixp
->fx_offset
;
3872 case BFD_RELOC_HI22
:
3873 case BFD_RELOC_LO10
:
3874 case BFD_RELOC_32_PCREL_S2
:
3875 case BFD_RELOC_SPARC13
:
3876 case BFD_RELOC_SPARC22
:
3877 case BFD_RELOC_SPARC_PC22
:
3878 case BFD_RELOC_SPARC_PC10
:
3879 case BFD_RELOC_SPARC_BASE13
:
3880 case BFD_RELOC_SPARC_WDISP10
:
3881 case BFD_RELOC_SPARC_WDISP16
:
3882 case BFD_RELOC_SPARC_WDISP19
:
3883 case BFD_RELOC_SPARC_WDISP22
:
3884 case BFD_RELOC_SPARC_5
:
3885 case BFD_RELOC_SPARC_6
:
3886 case BFD_RELOC_SPARC_7
:
3887 case BFD_RELOC_SPARC_10
:
3888 case BFD_RELOC_SPARC_11
:
3889 case BFD_RELOC_SPARC_HH22
:
3890 case BFD_RELOC_SPARC_HM10
:
3891 case BFD_RELOC_SPARC_LM22
:
3892 case BFD_RELOC_SPARC_PC_HH22
:
3893 case BFD_RELOC_SPARC_PC_HM10
:
3894 case BFD_RELOC_SPARC_PC_LM22
:
3895 case BFD_RELOC_SPARC_H34
:
3896 case BFD_RELOC_SPARC_H44
:
3897 case BFD_RELOC_SPARC_M44
:
3898 case BFD_RELOC_SPARC_L44
:
3899 case BFD_RELOC_SPARC_HIX22
:
3900 case BFD_RELOC_SPARC_LOX10
:
3901 case BFD_RELOC_SPARC_REV32
:
3902 case BFD_RELOC_SPARC_OLO10
:
3903 case BFD_RELOC_SPARC_UA16
:
3904 case BFD_RELOC_SPARC_UA32
:
3905 case BFD_RELOC_SPARC_UA64
:
3906 case BFD_RELOC_8_PCREL
:
3907 case BFD_RELOC_16_PCREL
:
3908 case BFD_RELOC_32_PCREL
:
3909 case BFD_RELOC_64_PCREL
:
3910 case BFD_RELOC_SPARC_PLT32
:
3911 case BFD_RELOC_SPARC_PLT64
:
3912 case BFD_RELOC_VTABLE_ENTRY
:
3913 case BFD_RELOC_VTABLE_INHERIT
:
3914 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3915 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3916 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3917 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3918 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3919 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3920 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3921 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3922 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3923 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3924 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3925 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3926 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3927 case BFD_RELOC_SPARC_TLS_IE_LD
:
3928 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3929 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3930 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3931 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3932 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3933 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3934 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3935 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3936 case BFD_RELOC_SPARC_GOTDATA_OP
:
3937 code
= fixp
->fx_r_type
;
3944 /* If we are generating PIC code, we need to generate a different
3947 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3949 #define GOTT_BASE "__GOTT_BASE__"
3950 #define GOTT_INDEX "__GOTT_INDEX__"
3953 /* This code must be parallel to tc_fix_adjustable. */
3959 case BFD_RELOC_32_PCREL_S2
:
3960 if (generic_force_reloc (fixp
))
3961 code
= BFD_RELOC_SPARC_WPLT30
;
3963 case BFD_RELOC_HI22
:
3964 code
= BFD_RELOC_SPARC_GOT22
;
3965 if (fixp
->fx_addsy
!= NULL
)
3967 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3968 code
= BFD_RELOC_SPARC_PC22
;
3970 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3971 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3972 code
= BFD_RELOC_HI22
; /* Unchanged. */
3976 case BFD_RELOC_LO10
:
3977 code
= BFD_RELOC_SPARC_GOT10
;
3978 if (fixp
->fx_addsy
!= NULL
)
3980 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3981 code
= BFD_RELOC_SPARC_PC10
;
3983 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3984 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3985 code
= BFD_RELOC_LO10
; /* Unchanged. */
3989 case BFD_RELOC_SPARC13
:
3990 code
= BFD_RELOC_SPARC_GOT13
;
3997 /* Nothing is aligned in DWARF debugging sections. */
3998 if (bfd_section_flags (section
) & SEC_DEBUGGING
)
4001 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
4002 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
4003 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
4007 if (code
== BFD_RELOC_SPARC_OLO10
)
4008 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
4010 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4011 if (reloc
->howto
== 0)
4013 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4014 _("internal error: can't export reloc type %d (`%s')"),
4015 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
4021 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
4022 if (code
!= BFD_RELOC_32_PCREL_S2
4023 && code
!= BFD_RELOC_SPARC_WDISP22
4024 && code
!= BFD_RELOC_SPARC_WDISP16
4025 && code
!= BFD_RELOC_SPARC_WDISP19
4026 && code
!= BFD_RELOC_SPARC_WDISP10
4027 && code
!= BFD_RELOC_SPARC_WPLT30
4028 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
4029 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
4030 reloc
->addend
= fixp
->fx_addnumber
;
4031 else if (symbol_section_p (fixp
->fx_addsy
))
4032 reloc
->addend
= (section
->vma
4033 + fixp
->fx_addnumber
4034 + md_pcrel_from (fixp
));
4036 reloc
->addend
= fixp
->fx_offset
;
4038 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4039 on the same location. */
4040 if (code
== BFD_RELOC_SPARC_OLO10
)
4042 relocs
[1] = reloc
= XNEW (arelent
);
4045 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4047 = symbol_get_bfdsym (section_symbol (absolute_section
));
4048 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4049 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4050 reloc
->addend
= fixp
->tc_fix_data
;
4056 /* We have no need to default values of symbols. */
4059 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4064 /* Round up a section size to the appropriate boundary. */
4067 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4072 /* Exactly what point is a PC-relative offset relative TO?
4073 On the sparc, they're relative to the address of the offset, plus
4074 its size. This gets us to the following instruction.
4075 (??? Is this right? FIXME-SOON) */
4077 md_pcrel_from (fixS
*fixP
)
4081 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4082 if (! sparc_pic_code
4083 || fixP
->fx_addsy
== NULL
4084 || symbol_section_p (fixP
->fx_addsy
))
4085 ret
+= fixP
->fx_size
;
4089 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4100 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4103 return (value
== 1) ? shift
: -1;
4106 /* Sort of like s_lcomm. */
4109 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4119 c
= get_symbol_name (&name
);
4120 p
= input_line_pointer
;
4122 SKIP_WHITESPACE_AFTER_NAME ();
4124 if (*input_line_pointer
!= ',')
4126 as_bad (_("Expected comma after name"));
4127 ignore_rest_of_line ();
4131 ++input_line_pointer
;
4133 if ((size
= get_absolute_expression ()) < 0)
4135 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4136 ignore_rest_of_line ();
4141 symbolP
= symbol_find_or_make (name
);
4144 if (!startswith (input_line_pointer
, ",\"bss\"")
4145 && !startswith (input_line_pointer
, ",\".bss\""))
4147 as_bad (_("bad .reserve segment -- expected BSS segment"));
4151 if (input_line_pointer
[2] == '.')
4152 input_line_pointer
+= 7;
4154 input_line_pointer
+= 6;
4157 if (*input_line_pointer
== ',')
4159 ++input_line_pointer
;
4162 if (*input_line_pointer
== '\n')
4164 as_bad (_("missing alignment"));
4165 ignore_rest_of_line ();
4169 align
= (int) get_absolute_expression ();
4173 as_bad (_("negative alignment"));
4174 ignore_rest_of_line ();
4180 temp
= mylog2 (align
);
4183 as_bad (_("alignment not a power of 2"));
4184 ignore_rest_of_line ();
4191 record_alignment (bss_section
, align
);
4196 if (!S_IS_DEFINED (symbolP
))
4201 segT current_seg
= now_seg
;
4202 subsegT current_subseg
= now_subseg
;
4204 /* Switch to bss. */
4205 subseg_set (bss_section
, 1);
4209 frag_align (align
, 0, 0);
4211 /* Detach from old frag. */
4212 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4213 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4215 symbol_set_frag (symbolP
, frag_now
);
4216 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4217 (offsetT
) size
, (char *) 0);
4220 S_SET_SEGMENT (symbolP
, bss_section
);
4222 subseg_set (current_seg
, current_subseg
);
4224 S_SET_SIZE (symbolP
, size
);
4229 as_warn (_("Ignoring attempt to re-define symbol %s"),
4230 S_GET_NAME (symbolP
));
4233 demand_empty_rest_of_line ();
4237 s_common (int ignore ATTRIBUTE_UNUSED
)
4245 c
= get_symbol_name (&name
);
4246 /* Just after name is now '\0'. */
4247 p
= input_line_pointer
;
4249 SKIP_WHITESPACE_AFTER_NAME ();
4250 if (*input_line_pointer
!= ',')
4252 as_bad (_("Expected comma after symbol-name"));
4253 ignore_rest_of_line ();
4258 input_line_pointer
++;
4260 if ((temp
= get_absolute_expression ()) < 0)
4262 as_bad (_(".COMMon length (%lu) out of range ignored"),
4263 (unsigned long) temp
);
4264 ignore_rest_of_line ();
4269 symbolP
= symbol_find_or_make (name
);
4271 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4273 as_bad (_("Ignoring attempt to re-define symbol"));
4274 ignore_rest_of_line ();
4277 if (S_GET_VALUE (symbolP
) != 0)
4279 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4281 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4282 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4285 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4286 if (*input_line_pointer
!= ',')
4288 as_bad (_("Expected comma after common length"));
4289 ignore_rest_of_line ();
4292 input_line_pointer
++;
4294 if (*input_line_pointer
!= '"')
4296 temp
= get_absolute_expression ();
4300 as_bad (_("negative alignment"));
4301 ignore_rest_of_line ();
4305 if (symbol_get_obj (symbolP
)->local
)
4312 old_subsec
= now_subseg
;
4317 align
= mylog2 (temp
);
4321 as_bad (_("alignment not a power of 2"));
4322 ignore_rest_of_line ();
4326 record_alignment (bss_section
, align
);
4327 subseg_set (bss_section
, 0);
4329 frag_align (align
, 0, 0);
4330 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4331 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4332 symbol_set_frag (symbolP
, frag_now
);
4333 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4334 (offsetT
) size
, (char *) 0);
4336 S_SET_SEGMENT (symbolP
, bss_section
);
4337 S_CLEAR_EXTERNAL (symbolP
);
4338 S_SET_SIZE (symbolP
, size
);
4339 subseg_set (old_sec
, old_subsec
);
4344 S_SET_VALUE (symbolP
, (valueT
) size
);
4345 S_SET_ALIGN (symbolP
, temp
);
4346 S_SET_SIZE (symbolP
, size
);
4347 S_SET_EXTERNAL (symbolP
);
4348 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4353 input_line_pointer
++;
4354 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4355 if (*input_line_pointer
== '.')
4356 input_line_pointer
++;
4357 /* @@ Some say data, some say bss. */
4358 if (!startswith (input_line_pointer
, "bss\"")
4359 && !startswith (input_line_pointer
, "data\""))
4361 while (*--input_line_pointer
!= '"')
4363 input_line_pointer
--;
4364 goto bad_common_segment
;
4366 while (*input_line_pointer
++ != '"')
4368 goto allocate_common
;
4371 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4373 demand_empty_rest_of_line ();
4378 p
= input_line_pointer
;
4379 while (*p
&& *p
!= '\n')
4383 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4385 input_line_pointer
= p
;
4386 ignore_rest_of_line ();
4391 /* Handle the .empty pseudo-op. This suppresses the warnings about
4392 invalid delay slot usage. */
4395 s_empty (int ignore ATTRIBUTE_UNUSED
)
4397 /* The easy way to implement is to just forget about the last
4403 s_seg (int ignore ATTRIBUTE_UNUSED
)
4406 if (startswith (input_line_pointer
, "\"text\""))
4408 input_line_pointer
+= 6;
4412 if (startswith (input_line_pointer
, "\"data\""))
4414 input_line_pointer
+= 6;
4418 if (startswith (input_line_pointer
, "\"data1\""))
4420 input_line_pointer
+= 7;
4424 if (startswith (input_line_pointer
, "\"bss\""))
4426 input_line_pointer
+= 5;
4427 /* We only support 2 segments -- text and data -- for now, so
4428 things in the "bss segment" will have to go into data for now.
4429 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4430 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4433 as_bad (_("Unknown segment type"));
4434 demand_empty_rest_of_line ();
4440 subseg_set (data_section
, 1);
4441 demand_empty_rest_of_line ();
4445 s_proc (int ignore ATTRIBUTE_UNUSED
)
4447 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4449 ++input_line_pointer
;
4451 ++input_line_pointer
;
4454 /* This static variable is set by s_uacons to tell sparc_cons_align
4455 that the expression does not need to be aligned. */
4457 static int sparc_no_align_cons
= 0;
4459 /* This handles the unaligned space allocation pseudo-ops, such as
4460 .uaword. .uaword is just like .word, but the value does not need
4464 s_uacons (int bytes
)
4466 /* Tell sparc_cons_align not to align this value. */
4467 sparc_no_align_cons
= 1;
4469 sparc_no_align_cons
= 0;
4472 /* This handles the native word allocation pseudo-op .nword.
4473 For sparc_arch_size 32 it is equivalent to .word, for
4474 sparc_arch_size 64 it is equivalent to .xword. */
4477 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4479 cons (sparc_arch_size
== 32 ? 4 : 8);
4482 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4486 .register %g[2367],{#scratch|symbolname|#ignore}
4490 s_register (int ignore ATTRIBUTE_UNUSED
)
4497 if (input_line_pointer
[0] != '%'
4498 || input_line_pointer
[1] != 'g'
4499 || ((input_line_pointer
[2] & ~1) != '2'
4500 && (input_line_pointer
[2] & ~1) != '6')
4501 || input_line_pointer
[3] != ',')
4502 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4503 reg
= input_line_pointer
[2] - '0';
4504 input_line_pointer
+= 4;
4506 if (*input_line_pointer
== '#')
4508 ++input_line_pointer
;
4509 c
= get_symbol_name (®name
);
4510 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4511 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4512 if (regname
[0] == 'i')
4515 regname
= (char *) "";
4519 c
= get_symbol_name (®name
);
4522 if (sparc_arch_size
== 64)
4526 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4527 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4528 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4529 as_bad (_("redefinition of global register"));
4533 if (regname
== NULL
)
4534 globals
[reg
] = (symbolS
*) 1;
4539 if (symbol_find (regname
))
4540 as_bad (_("Register symbol %s already defined."),
4543 globals
[reg
] = symbol_make (regname
);
4544 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4546 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4547 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4548 flags
|= BSF_GLOBAL
;
4549 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4550 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4551 S_SET_ALIGN (globals
[reg
], reg
);
4552 S_SET_SIZE (globals
[reg
], 0);
4553 /* Although we actually want undefined_section here,
4554 we have to use absolute_section, because otherwise
4555 generic as code will make it a COM section.
4556 We fix this up in sparc_adjust_symtab. */
4557 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4558 S_SET_OTHER (globals
[reg
], 0);
4559 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4560 ->internal_elf_sym
.st_info
=
4561 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4562 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4563 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4568 (void) restore_line_pointer (c
);
4570 demand_empty_rest_of_line ();
4573 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4574 symbols which need it. */
4577 sparc_adjust_symtab (void)
4581 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4583 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4584 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4587 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4588 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4591 S_SET_SEGMENT (sym
, undefined_section
);
4595 /* If the --enforce-aligned-data option is used, we require .word,
4596 et. al., to be aligned correctly. We do it by setting up an
4597 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4598 no unexpected alignment was introduced.
4600 The SunOS and Solaris native assemblers enforce aligned data by
4601 default. We don't want to do that, because gcc can deliberately
4602 generate misaligned data if the packed attribute is used. Instead,
4603 we permit misaligned data by default, and permit the user to set an
4604 option to check for it. */
4607 sparc_cons_align (int nbytes
)
4611 /* Only do this if we are enforcing aligned data. */
4612 if (! enforce_aligned_data
)
4615 /* Don't align if this is an unaligned pseudo-op. */
4616 if (sparc_no_align_cons
)
4619 nalign
= mylog2 (nbytes
);
4623 gas_assert (nalign
> 0);
4625 if (now_seg
== absolute_section
)
4627 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4628 as_bad (_("misaligned data"));
4632 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4633 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4635 record_alignment (now_seg
, nalign
);
4638 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4641 sparc_handle_align (fragS
*fragp
)
4646 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4648 switch (fragp
->fr_type
)
4652 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4656 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4667 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4669 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4670 if (INSN_BIG_ENDIAN
)
4671 number_to_chars_bigendian (p
, wval
, 4);
4673 number_to_chars_littleendian (p
, wval
, 4);
4679 if (INSN_BIG_ENDIAN
)
4680 number_to_chars_bigendian (p
, 0x01000000, 4);
4682 number_to_chars_littleendian (p
, 0x01000000, 4);
4684 fragp
->fr_fix
+= fix
;
4693 /* Some special processing for a Sparc ELF file. */
4696 sparc_elf_final_processing (void)
4698 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4699 sort of BFD interface for this. */
4700 if (sparc_arch_size
== 64)
4702 switch (sparc_memory_model
)
4705 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4708 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4714 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4715 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4716 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4717 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4718 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4719 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4723 sparc_cons (expressionS
*exp
, int size
)
4726 const char *sparc_cons_special_reloc
= NULL
;
4729 save
= input_line_pointer
;
4730 if (input_line_pointer
[0] == '%'
4731 && input_line_pointer
[1] == 'r'
4732 && input_line_pointer
[2] == '_')
4734 if (startswith (input_line_pointer
+ 3, "disp"))
4736 input_line_pointer
+= 7;
4737 sparc_cons_special_reloc
= "disp";
4739 else if (startswith (input_line_pointer
+ 3, "plt"))
4741 if (size
!= 4 && size
!= 8)
4742 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4745 input_line_pointer
+= 6;
4746 sparc_cons_special_reloc
= "plt";
4749 else if (startswith (input_line_pointer
+ 3, "tls_dtpoff"))
4751 if (size
!= 4 && size
!= 8)
4752 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4755 input_line_pointer
+= 13;
4756 sparc_cons_special_reloc
= "tls_dtpoff";
4759 if (sparc_cons_special_reloc
)
4766 if (*input_line_pointer
!= '8')
4768 input_line_pointer
--;
4771 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4775 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4779 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4789 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4790 sparc_cons_special_reloc
, size
* 8, size
);
4794 input_line_pointer
+= 2;
4795 if (*input_line_pointer
!= '(')
4797 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4798 sparc_cons_special_reloc
, size
* 8);
4805 input_line_pointer
= save
;
4806 sparc_cons_special_reloc
= NULL
;
4811 char *end
= ++input_line_pointer
;
4814 while (! is_end_of_line
[(c
= *end
)])
4828 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4829 sparc_cons_special_reloc
, size
* 8);
4835 if (input_line_pointer
!= end
)
4837 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4838 sparc_cons_special_reloc
, size
* 8);
4842 input_line_pointer
++;
4844 c
= *input_line_pointer
;
4845 if (! is_end_of_line
[c
] && c
!= ',')
4846 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4847 sparc_cons_special_reloc
, size
* 8);
4853 if (sparc_cons_special_reloc
== NULL
)
4855 return sparc_cons_special_reloc
;
4858 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4859 reloc for a cons. We could use the definition there, except that
4860 we want to handle little endian relocs specially. */
4863 cons_fix_new_sparc (fragS
*frag
,
4865 unsigned int nbytes
,
4867 const char *sparc_cons_special_reloc
)
4869 bfd_reloc_code_real_type r
;
4871 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4872 (nbytes
== 2 ? BFD_RELOC_16
:
4873 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4875 if (target_little_endian_data
4877 && now_seg
->flags
& SEC_ALLOC
)
4878 r
= BFD_RELOC_SPARC_REV32
;
4881 /* The Solaris linker does not allow R_SPARC_UA64
4882 relocations for 32-bit executables. */
4883 if (!target_little_endian_data
4884 && sparc_arch_size
!= 64
4885 && r
== BFD_RELOC_64
)
4889 if (sparc_cons_special_reloc
)
4891 if (*sparc_cons_special_reloc
== 'd')
4894 case 1: r
= BFD_RELOC_8_PCREL
; break;
4895 case 2: r
= BFD_RELOC_16_PCREL
; break;
4896 case 4: r
= BFD_RELOC_32_PCREL
; break;
4897 case 8: r
= BFD_RELOC_64_PCREL
; break;
4900 else if (*sparc_cons_special_reloc
== 'p')
4903 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4904 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4909 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4910 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4913 else if (sparc_no_align_cons
4914 || /* PR 20803 - relocs in the .eh_frame section
4915 need to support unaligned access. */
4916 strcmp (now_seg
->name
, ".eh_frame") == 0)
4920 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4921 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4923 /* The Solaris linker does not allow R_SPARC_UA64
4924 relocations for 32-bit executables. */
4925 case 8: r
= sparc_arch_size
== 64 ?
4926 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
4928 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4934 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4938 sparc_cfi_frame_initial_instructions (void)
4940 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4944 sparc_regname_to_dw2regnum (char *regname
)
4954 case 'g': i
= 0; break;
4955 case 'o': i
= 1; break;
4956 case 'l': i
= 2; break;
4957 case 'i': i
= 3; break;
4958 default: i
= -1; break;
4962 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4964 return i
* 8 + regname
[1] - '0';
4966 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4968 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4970 if (regname
[0] == 'f' || regname
[0] == 'r')
4972 unsigned int regnum
;
4974 regnum
= strtoul (regname
+ 1, &q
, 10);
4975 if (q
== NULL
|| *q
)
4977 if (regnum
>= ((regname
[0] == 'f'
4978 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4981 if (regname
[0] == 'f')
4984 if (regnum
>= 64 && (regnum
& 1))
4993 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4995 sparc_no_align_cons
= 1;
4996 emit_expr_with_reloc (exp
, nbytes
, "disp");
4997 sparc_no_align_cons
= 0;