1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 97, 98, 1999 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
26 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
32 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
33 static void init_default_arch
PARAMS ((void));
34 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
35 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
36 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
37 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
38 static int sparc_ffs
PARAMS ((unsigned int));
39 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
40 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
41 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
42 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
43 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
44 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
45 static int parse_const_expr_arg
PARAMS ((char **, int *));
46 static int get_expression
PARAMS ((char *str
));
48 /* Default architecture. */
49 /* ??? The default value should be V8, but sparclite support was added
50 by making it the default. GCC now passes -Asparclite, so maybe sometime in
51 the future we can set this to V8. */
53 #define DEFAULT_ARCH "sparclite"
55 static char *default_arch
= DEFAULT_ARCH
;
57 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
59 static int default_init_p
;
61 /* Current architecture. We don't bump up unless necessary. */
62 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
64 /* The maximum architecture level we can bump up to.
65 In a 32 bit environment, don't allow bumping up to v9 by default.
66 The native assembler works this way. The user is required to pass
67 an explicit argument before we'll create v9 object files. However, if
68 we don't see any v9 insns, a v8plus object file is not created. */
69 static enum sparc_opcode_arch_val max_architecture
;
71 /* Either 32 or 64, selects file format. */
72 static int sparc_arch_size
;
73 /* Initial (default) value, recorded separately in case a user option
74 changes the value before md_show_usage is called. */
75 static int default_arch_size
;
78 /* The currently selected v9 memory model. Currently only used for
80 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
83 static int architecture_requested
;
84 static int warn_on_bump
;
86 /* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88 static enum sparc_opcode_arch_val warn_after_architecture
;
90 /* Non-zero if we are generating PIC code. */
93 /* Non-zero if we should give an error when misaligned data is seen. */
94 static int enforce_aligned_data
;
96 extern int target_big_endian
;
98 static int target_little_endian_data
;
100 /* V9 and 86x have big and little endian data, but instructions are always big
101 endian. The sparclet has bi-endian support but both data and insns have
102 the same endianness. Global `target_big_endian' is used for data.
103 The following macro is used for instructions. */
104 #ifndef INSN_BIG_ENDIAN
105 #define INSN_BIG_ENDIAN (target_big_endian \
106 || default_arch_type == sparc86x \
107 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
110 /* handle of the OPCODE hash table */
111 static struct hash_control
*op_hash
;
113 static int log2
PARAMS ((int));
114 static void s_data1
PARAMS ((void));
115 static void s_seg
PARAMS ((int));
116 static void s_proc
PARAMS ((int));
117 static void s_reserve
PARAMS ((int));
118 static void s_common
PARAMS ((int));
119 static void s_empty
PARAMS ((int));
120 static void s_uacons
PARAMS ((int));
121 static void s_ncons
PARAMS ((int));
123 const pseudo_typeS md_pseudo_table
[] =
125 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
126 {"common", s_common
, 0},
127 {"empty", s_empty
, 0},
128 {"global", s_globl
, 0},
130 {"nword", s_ncons
, 0},
131 {"optim", s_ignore
, 0},
133 {"reserve", s_reserve
, 0},
135 {"skip", s_space
, 0},
138 {"uahalf", s_uacons
, 2},
139 {"uaword", s_uacons
, 4},
140 {"uaxword", s_uacons
, 8},
142 /* these are specific to sparc/svr4 */
143 {"2byte", s_uacons
, 2},
144 {"4byte", s_uacons
, 4},
145 {"8byte", s_uacons
, 8},
150 const int md_reloc_size
= 12; /* Size of relocation record */
152 /* This array holds the chars that always start a comment. If the
153 pre-processor is disabled, these aren't very useful */
154 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
156 /* This array holds the chars that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output */
159 /* Note that input_file.c hand checks for '#' at the beginning of the
160 first line of the input file. This is because the compiler outputs
161 #NO_APP at the beginning of its output. */
162 /* Also note that comments started like this one will always
163 work if '/' isn't otherwise defined. */
164 const char line_comment_chars
[] = "#";
166 const char line_separator_chars
[] = "";
168 /* Chars that can be used to separate mant from exp in floating point nums */
169 const char EXP_CHARS
[] = "eE";
171 /* Chars that mean this number is a floating point constant */
174 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
176 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
177 changed in read.c. Ideally it shouldn't have to know about it at all,
178 but nothing is ideal around here. */
180 #define isoctal(c) ((unsigned)((c) - '0') < '8')
185 unsigned long opcode
;
186 struct nlist
*nlistp
;
190 bfd_reloc_code_real_type reloc
;
193 struct sparc_it the_insn
, set_insn
;
195 static void output_insn
196 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
198 /* Table of arguments to -A.
199 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
200 for this use. That table is for opcodes only. This table is for opcodes
203 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
204 v8plusa
, v9
, v9a
, v9_64
};
206 static struct sparc_arch
{
209 enum sparc_arch_types arch_type
;
210 /* Default word size, as specified during configuration.
211 A value of zero means can't be used to specify default architecture. */
212 int default_arch_size
;
213 /* Allowable arg to -A? */
215 } sparc_arch_table
[] = {
216 { "v6", "v6", v6
, 0, 1 },
217 { "v7", "v7", v7
, 0, 1 },
218 { "v8", "v8", v8
, 32, 1 },
219 { "sparclet", "sparclet", sparclet
, 32, 1 },
220 { "sparclite", "sparclite", sparclite
, 32, 1 },
221 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
222 { "v8plus", "v9", v9
, 0, 1 },
223 { "v8plusa", "v9a", v9
, 0, 1 },
224 { "v9", "v9", v9
, 0, 1 },
225 { "v9a", "v9a", v9
, 0, 1 },
226 /* This exists to allow configure.in/Makefile.in to pass one
227 value to specify both the default machine and default word size. */
228 { "v9-64", "v9", v9
, 64, 0 },
229 { NULL
, NULL
, v8
, 0, 0 }
232 /* Variant of default_arch */
233 static enum sparc_arch_types default_arch_type
;
235 static struct sparc_arch
*
239 struct sparc_arch
*sa
;
241 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
242 if (strcmp (sa
->name
, name
) == 0)
244 if (sa
->name
== NULL
)
249 /* Initialize the default opcode arch and word size from the default
250 architecture name. */
255 struct sparc_arch
*sa
= lookup_arch (default_arch
);
258 || sa
->default_arch_size
== 0)
259 as_fatal (_("Invalid default architecture, broken assembler."));
261 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
262 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
263 as_fatal (_("Bad opcode table, broken assembler."));
264 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
266 default_arch_type
= sa
->arch_type
;
269 /* Called by TARGET_FORMAT. */
272 sparc_target_format ()
274 /* We don't get a chance to initialize anything before we're called,
275 so handle that now. */
276 if (! default_init_p
)
277 init_default_arch ();
281 return "a.out-sparc-netbsd";
284 if (target_big_endian
)
285 return "a.out-sunos-big";
286 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
287 return "a.out-sunos-big";
288 else return "a.out-sparc-little";
290 return "a.out-sunos-big";
301 return "coff-sparc-lynx";
308 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
316 * Invocation line includes a switch not recognized by the base assembler.
317 * See if it's a processor-specific option. These are:
320 * Warn on architecture bumps. See also -A.
322 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
323 * Standard 32 bit architectures.
324 * -Av8plus, -Av8plusa
325 * Sparc64 in a 32 bit world.
327 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
328 * This used to only mean 64 bits, but properly specifying it
329 * complicated gcc's ASM_SPECs, so now opcode selection is
330 * specified orthogonally to word size (except when specifying
331 * the default, but that is an internal implementation detail).
332 * -xarch=v8plus, -xarch=v8plusa
333 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
335 * Select the architecture and possibly the file format.
336 * Instructions or features not supported by the selected
337 * architecture cause fatal errors.
339 * The default is to start at v6, and bump the architecture up
340 * whenever an instruction is seen at a higher level. In 32 bit
341 * environments, v9 is not bumped up to, the user must pass
344 * If -bump is specified, a warning is printing when bumping to
347 * If an architecture is specified, all instructions must match
348 * that architecture. Any higher level instructions are flagged
349 * as errors. Note that in the 32 bit environment specifying
350 * -Av8plus does not automatically create a v8plus object file, a
351 * v9 insn must be seen.
353 * If both an architecture and -bump are specified, the
354 * architecture starts at the specified level, but bumps are
355 * warnings. Note that we can't set `current_architecture' to
356 * the requested level in this case: in the 32 bit environment,
357 * we still must avoid creating v8plus object files unless v9
361 * Bumping between incompatible architectures is always an
362 * error. For example, from sparclite to v9.
366 CONST
char *md_shortopts
= "A:K:VQ:sq";
369 CONST
char *md_shortopts
= "A:k";
371 CONST
char *md_shortopts
= "A:";
374 struct option md_longopts
[] = {
375 #define OPTION_BUMP (OPTION_MD_BASE)
376 {"bump", no_argument
, NULL
, OPTION_BUMP
},
377 #define OPTION_SPARC (OPTION_MD_BASE + 1)
378 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
379 #define OPTION_XARCH (OPTION_MD_BASE + 2)
380 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
382 #define OPTION_32 (OPTION_MD_BASE + 3)
383 {"32", no_argument
, NULL
, OPTION_32
},
384 #define OPTION_64 (OPTION_MD_BASE + 4)
385 {"64", no_argument
, NULL
, OPTION_64
},
386 #define OPTION_TSO (OPTION_MD_BASE + 5)
387 {"TSO", no_argument
, NULL
, OPTION_TSO
},
388 #define OPTION_PSO (OPTION_MD_BASE + 6)
389 {"PSO", no_argument
, NULL
, OPTION_PSO
},
390 #define OPTION_RMO (OPTION_MD_BASE + 7)
391 {"RMO", no_argument
, NULL
, OPTION_RMO
},
393 #ifdef SPARC_BIENDIAN
394 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
395 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
396 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
397 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
399 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
400 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
401 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
402 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
403 {NULL
, no_argument
, NULL
, 0}
405 size_t md_longopts_size
= sizeof(md_longopts
);
408 md_parse_option (c
, arg
)
412 /* We don't get a chance to initialize anything before we're called,
413 so handle that now. */
414 if (! default_init_p
)
415 init_default_arch ();
421 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
425 /* This is for compatibility with Sun's assembler. */
426 if (strcmp (arg
, "v8plus") != 0
427 && strcmp (arg
, "v8plusa") != 0)
429 as_bad (_("invalid architecture -xarch=%s"), arg
);
437 struct sparc_arch
*sa
;
438 enum sparc_opcode_arch_val opcode_arch
;
440 sa
= lookup_arch (arg
);
442 || ! sa
->user_option_p
)
444 as_bad (_("invalid architecture -A%s"), arg
);
448 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
449 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
450 as_fatal (_("Bad opcode table, broken assembler."));
452 max_architecture
= opcode_arch
;
453 architecture_requested
= 1;
458 /* Ignore -sparc, used by SunOS make default .s.o rule. */
461 case OPTION_ENFORCE_ALIGNED_DATA
:
462 enforce_aligned_data
= 1;
465 #ifdef SPARC_BIENDIAN
466 case OPTION_LITTLE_ENDIAN
:
467 target_big_endian
= 0;
468 if (default_arch_type
!= sparclet
)
469 as_fatal ("This target does not support -EL");
471 case OPTION_LITTLE_ENDIAN_DATA
:
472 target_little_endian_data
= 1;
473 target_big_endian
= 0;
474 if (default_arch_type
!= sparc86x
475 && default_arch_type
!= v9
)
476 as_fatal ("This target does not support --little-endian-data");
478 case OPTION_BIG_ENDIAN
:
479 target_big_endian
= 1;
493 const char **list
, **l
;
495 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
496 list
= bfd_target_list ();
497 for (l
= list
; *l
!= NULL
; l
++)
499 if (sparc_arch_size
== 32)
501 if (strcmp (*l
, "elf32-sparc") == 0)
506 if (strcmp (*l
, "elf64-sparc") == 0)
511 as_fatal (_("No compiled in support for %d bit object file format"),
518 sparc_memory_model
= MM_TSO
;
522 sparc_memory_model
= MM_PSO
;
526 sparc_memory_model
= MM_RMO
;
534 /* Qy - do emit .comment
535 Qn - do not emit .comment */
539 /* use .stab instead of .stab.excl */
543 /* quick -- native assembler does fewer checks */
547 if (strcmp (arg
, "PIC") != 0)
548 as_warn (_("Unrecognized option following -K"));
562 md_show_usage (stream
)
565 const struct sparc_arch
*arch
;
567 /* We don't get a chance to initialize anything before we're called,
568 so handle that now. */
569 if (! default_init_p
)
570 init_default_arch ();
572 fprintf(stream
, _("SPARC options:\n"));
573 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
575 if (arch
!= &sparc_arch_table
[0])
576 fprintf (stream
, " | ");
577 if (arch
->user_option_p
)
578 fprintf (stream
, "-A%s", arch
->name
);
580 fprintf (stream
, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
581 fprintf (stream
, _("\
582 specify variant of SPARC architecture\n\
583 -bump warn when assembler switches architectures\n\
585 --enforce-aligned-data force .long, etc., to be aligned correctly\n"));
587 fprintf (stream
, _("\
588 -k generate PIC\n"));
591 fprintf (stream
, _("\
592 -32 create 32 bit object file\n\
593 -64 create 64 bit object file\n"));
594 fprintf (stream
, _("\
595 [default is %d]\n"), default_arch_size
);
596 fprintf (stream
, _("\
597 -TSO use Total Store Ordering\n\
598 -PSO use Partial Store Ordering\n\
599 -RMO use Relaxed Memory Ordering\n"));
600 fprintf (stream
, _("\
601 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
602 fprintf (stream
, _("\
603 -KPIC generate PIC\n\
604 -V print assembler version number\n\
609 #ifdef SPARC_BIENDIAN
610 fprintf (stream
, _("\
611 -EL generate code for a little endian machine\n\
612 -EB generate code for a big endian machine\n\
613 --little-endian-data generate code for a machine having big endian\n\
614 instructions and little endian data."));
618 /* native operand size opcode translation */
624 } native_op_table
[] =
626 {"ldn", "ld", "ldx"},
627 {"ldna", "lda", "ldxa"},
628 {"stn", "st", "stx"},
629 {"stna", "sta", "stxa"},
630 {"slln", "sll", "sllx"},
631 {"srln", "srl", "srlx"},
632 {"sran", "sra", "srax"},
633 {"casn", "cas", "casx"},
634 {"casna", "casa", "casxa"},
635 {"clrn", "clr", "clrx"},
639 /* sparc64 priviledged registers */
641 struct priv_reg_entry
647 struct priv_reg_entry priv_reg_table
[] =
666 {"", -1}, /* end marker */
669 /* v9a specific asrs */
671 struct priv_reg_entry v9a_asr_table
[] =
680 {"clear_softint", 21},
681 {"", -1}, /* end marker */
685 cmp_reg_entry (parg
, qarg
)
689 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
690 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
692 return strcmp (q
->name
, p
->name
);
695 /* This function is called once, at assembler startup time. It should
696 set up all the tables, etc. that the MD part of the assembler will need. */
701 register const char *retval
= NULL
;
703 register unsigned int i
= 0;
705 /* We don't get a chance to initialize anything before md_parse_option
706 is called, and it may not be called, so handle default initialization
707 now if not already done. */
708 if (! default_init_p
)
709 init_default_arch ();
711 op_hash
= hash_new ();
713 while (i
< (unsigned int) sparc_num_opcodes
)
715 const char *name
= sparc_opcodes
[i
].name
;
716 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
719 as_bad (_("Internal error: can't hash `%s': %s\n"),
720 sparc_opcodes
[i
].name
, retval
);
725 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
727 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
728 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
733 while (i
< (unsigned int) sparc_num_opcodes
734 && !strcmp (sparc_opcodes
[i
].name
, name
));
737 for (i
= 0; native_op_table
[i
].name
; i
++)
739 const struct sparc_opcode
*insn
;
740 char *name
= sparc_arch_size
== 32 ? native_op_table
[i
].name32
:
741 native_op_table
[i
].name64
;
742 insn
= (struct sparc_opcode
*)hash_find (op_hash
, name
);
745 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
746 name
, native_op_table
[i
].name
);
751 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
754 as_bad (_("Internal error: can't hash `%s': %s\n"),
755 sparc_opcodes
[i
].name
, retval
);
762 as_fatal (_("Broken assembler. No assembly attempted."));
764 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
765 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
767 /* If -bump, record the architecture level at which we start issuing
768 warnings. The behaviour is different depending upon whether an
769 architecture was explicitly specified. If it wasn't, we issue warnings
770 for all upwards bumps. If it was, we don't start issuing warnings until
771 we need to bump beyond the requested architecture or when we bump between
772 conflicting architectures. */
775 && architecture_requested
)
777 /* `max_architecture' records the requested architecture.
778 Issue warnings if we go above it. */
779 warn_after_architecture
= max_architecture
;
781 /* Find the highest architecture level that doesn't conflict with
782 the requested one. */
783 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
784 max_architecture
> warn_after_architecture
;
786 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
787 warn_after_architecture
))
792 /* Called after all assembly has been done. */
797 if (sparc_arch_size
== 64)
799 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
800 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
802 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
806 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
807 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
808 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
809 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
810 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
811 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
812 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
813 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclite_le
);
816 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
817 be but for now it is (since that's the way it's always been
819 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
824 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
827 in_signed_range (val
, max
)
828 bfd_signed_vma val
, max
;
832 /* Sign-extend the value from the architecture word size, so that
833 0xffffffff is always considered -1 on sparc32. */
834 if (sparc_arch_size
== 32)
836 bfd_signed_vma sign
= (bfd_signed_vma
)1 << 31;
837 val
= ((val
& 0xffffffff) ^ sign
) - sign
;
846 /* Return non-zero if VAL is in the range 0 to MAX. */
849 in_unsigned_range (val
, max
)
857 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
858 (e.g. -15 to +31). */
861 in_bitfield_range (val
, max
)
862 bfd_signed_vma val
, max
;
868 if (val
< ~(max
>> 1))
882 for (i
= 0; (mask
& 1) == 0; ++i
)
887 /* Implement big shift right. */
893 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
894 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
895 return val
>> amount
;
898 /* For communication between sparc_ip and get_expression. */
899 static char *expr_end
;
901 /* Values for `special_case'.
902 Instructions that require wierd handling because they're longer than
904 #define SPECIAL_CASE_NONE 0
905 #define SPECIAL_CASE_SET 1
906 #define SPECIAL_CASE_SETSW 2
907 #define SPECIAL_CASE_SETX 3
908 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
909 #define SPECIAL_CASE_FDIV 4
911 /* Bit masks of various insns. */
912 #define NOP_INSN 0x01000000
913 #define OR_INSN 0x80100000
914 #define XOR_INSN 0x80180000
915 #define FMOVS_INSN 0x81A00020
916 #define SETHI_INSN 0x01000000
917 #define SLLX_INSN 0x81281000
918 #define SRA_INSN 0x81380000
920 /* The last instruction to be assembled. */
921 static const struct sparc_opcode
*last_insn
;
922 /* The assembled opcode of `last_insn'. */
923 static unsigned long last_opcode
;
925 /* Handle the set and setuw synthetic instructions. */
927 synthetize_setuw (insn
)
928 const struct sparc_opcode
*insn
;
931 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
933 if (the_insn
.exp
.X_op
== O_constant
)
935 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
937 if (sizeof(offsetT
) > 4
938 && (the_insn
.exp
.X_add_number
< 0
939 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
940 as_warn (_("set: number not in 0..4294967295 range"));
944 if (sizeof(offsetT
) > 4
945 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
946 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
947 as_warn (_("set: number not in -2147483648..4294967295 range"));
948 the_insn
.exp
.X_add_number
= (int)the_insn
.exp
.X_add_number
;
952 /* See if operand is absolute and small; skip sethi if so. */
953 if (the_insn
.exp
.X_op
!= O_constant
954 || the_insn
.exp
.X_add_number
>= (1 << 12)
955 || the_insn
.exp
.X_add_number
< -(1 << 12))
957 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
958 | ((the_insn
.exp
.X_add_number
>> 10)
959 & (the_insn
.exp
.X_op
== O_constant
? 0x3fffff : 0)));
960 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
963 output_insn (insn
, &the_insn
);
967 /* See if operand has no low-order bits; skip OR if so. */
968 if (the_insn
.exp
.X_op
!= O_constant
969 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
972 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
974 | (the_insn
.exp
.X_add_number
975 & (the_insn
.exp
.X_op
!= O_constant
? 0 :
976 need_hi22_p
? 0x3ff : 0x1fff)));
977 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
980 output_insn (insn
, &the_insn
);
984 /* Handle the setsw synthetic instruction. */
986 synthetize_setsw (insn
)
987 const struct sparc_opcode
*insn
;
991 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
993 if (the_insn
.exp
.X_op
!= O_constant
)
995 synthetize_setuw (insn
);
997 /* Need to sign extend it. */
998 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
999 the_insn
.reloc
= BFD_RELOC_NONE
;
1000 output_insn (insn
, &the_insn
);
1004 if (sizeof(offsetT
) > 4
1005 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
1006 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
1007 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1009 low32
= the_insn
.exp
.X_add_number
;
1013 synthetize_setuw (insn
);
1019 the_insn
.reloc
= BFD_RELOC_NONE
;
1020 /* See if operand is absolute and small; skip sethi if so. */
1021 if (low32
< -(1 << 12))
1023 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1024 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1025 output_insn (insn
, &the_insn
);
1026 low32
= 0x1c00 | (low32
& 0x3ff);
1027 opc
= RS1 (rd
) | XOR_INSN
;
1030 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1031 | (low32
& 0x1fff));
1032 output_insn (insn
, &the_insn
);
1035 /* Handle the setsw synthetic instruction. */
1037 synthetize_setx (insn
)
1038 const struct sparc_opcode
*insn
;
1040 int upper32
, lower32
;
1041 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1042 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1044 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1045 int need_xor10_p
= 0;
1047 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1048 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1049 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1052 upper_dstreg
= tmpreg
;
1053 /* The tmp reg should not be the dst reg. */
1054 if (tmpreg
== dstreg
)
1055 as_warn (_("setx: temporary register same as destination register"));
1057 /* ??? Obviously there are other optimizations we can do
1058 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1059 doing some of these. Later. If you do change things, try to
1060 change all of this to be table driven as well. */
1061 /* What to output depends on the number if it's constant.
1062 Compute that first, then output what we've decided upon. */
1063 if (the_insn
.exp
.X_op
!= O_constant
)
1065 if (sparc_arch_size
== 32)
1067 /* When arch size is 32, we want setx to be equivalent
1068 to setuw for anything but constants. */
1069 the_insn
.exp
.X_add_number
&= 0xffffffff;
1070 synthetize_setuw (insn
);
1073 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1074 lower32
= 0; upper32
= 0;
1078 /* Reset X_add_number, we've extracted it as upper32/lower32.
1079 Otherwise fixup_segment will complain about not being able to
1080 write an 8 byte number in a 4 byte field. */
1081 the_insn
.exp
.X_add_number
= 0;
1083 /* Only need hh22 if `or' insn can't handle constant. */
1084 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1087 /* Does bottom part (after sethi) have bits? */
1088 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1089 /* No hh22, but does upper32 still have bits we can't set
1091 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1094 /* If the lower half is all zero, we build the upper half directly
1095 into the dst reg. */
1097 /* Need lower half if number is zero or 0xffffffff00000000. */
1098 || (! need_hh22_p
&& ! need_hm10_p
))
1100 /* No need for sethi if `or' insn can handle constant. */
1101 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1102 /* Note that we can't use a negative constant in the `or'
1103 insn unless the upper 32 bits are all ones. */
1104 || (lower32
< 0 && upper32
!= -1)
1105 || (lower32
>= 0 && upper32
== -1))
1108 if (need_hi22_p
&& upper32
== -1)
1111 /* Does bottom part (after sethi) have bits? */
1112 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1114 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1115 /* Need `or' if we didn't set anything else. */
1116 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1120 /* Output directly to dst reg if lower 32 bits are all zero. */
1121 upper_dstreg
= dstreg
;
1124 if (!upper_dstreg
&& dstreg
)
1125 as_warn (_("setx: illegal temporary register g0"));
1129 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1130 | ((upper32
>> 10) & 0x3fffff));
1131 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1132 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1133 output_insn (insn
, &the_insn
);
1138 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1139 | (((need_xor10_p
? ~lower32
: lower32
)
1140 >> 10) & 0x3fffff));
1141 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1142 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1143 output_insn (insn
, &the_insn
);
1148 the_insn
.opcode
= (OR_INSN
1149 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1152 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1153 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1154 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1155 output_insn (insn
, &the_insn
);
1160 /* FIXME: One nice optimization to do here is to OR the low part
1161 with the highpart if hi22 isn't needed and the low part is
1163 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1166 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1167 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1168 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1169 output_insn (insn
, &the_insn
);
1172 /* If we needed to build the upper part, shift it into place. */
1173 if (need_hh22_p
|| need_hm10_p
)
1175 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1177 the_insn
.reloc
= BFD_RELOC_NONE
;
1178 output_insn (insn
, &the_insn
);
1181 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1184 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1185 | 0x1c00 | (lower32
& 0x3ff));
1186 the_insn
.reloc
= BFD_RELOC_NONE
;
1187 output_insn (insn
, &the_insn
);
1190 /* If we needed to build both upper and lower parts, OR them together. */
1191 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1193 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1195 the_insn
.reloc
= BFD_RELOC_NONE
;
1196 output_insn (insn
, &the_insn
);
1200 /* Main entry point to assemble one instruction. */
1206 const struct sparc_opcode
*insn
;
1210 special_case
= sparc_ip (str
, &insn
);
1212 /* We warn about attempts to put a floating point branch in a delay slot,
1213 unless the delay slot has been annulled. */
1215 && last_insn
!= NULL
1216 && (insn
->flags
& F_FBR
) != 0
1217 && (last_insn
->flags
& F_DELAYED
) != 0
1218 /* ??? This test isn't completely accurate. We assume anything with
1219 F_{UNBR,CONDBR,FBR} set is annullable. */
1220 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1221 || (last_opcode
& ANNUL
) == 0))
1222 as_warn (_("FP branch in delay slot"));
1224 /* SPARC before v9 requires a nop instruction between a floating
1225 point instruction and a floating point branch. We insert one
1226 automatically, with a warning. */
1227 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1229 && last_insn
!= NULL
1230 && (insn
->flags
& F_FBR
) != 0
1231 && (last_insn
->flags
& F_FLOAT
) != 0)
1233 struct sparc_it nop_insn
;
1235 nop_insn
.opcode
= NOP_INSN
;
1236 nop_insn
.reloc
= BFD_RELOC_NONE
;
1237 output_insn (insn
, &nop_insn
);
1238 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1241 switch (special_case
)
1243 case SPECIAL_CASE_NONE
:
1245 output_insn (insn
, &the_insn
);
1248 case SPECIAL_CASE_SETSW
:
1249 synthetize_setsw (insn
);
1252 case SPECIAL_CASE_SET
:
1253 synthetize_setuw (insn
);
1256 case SPECIAL_CASE_SETX
:
1257 synthetize_setx (insn
);
1260 case SPECIAL_CASE_FDIV
:
1262 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1264 output_insn (insn
, &the_insn
);
1266 /* According to information leaked from Sun, the "fdiv" instructions
1267 on early SPARC machines would produce incorrect results sometimes.
1268 The workaround is to add an fmovs of the destination register to
1269 itself just after the instruction. This was true on machines
1270 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1271 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1272 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1273 output_insn (insn
, &the_insn
);
1278 as_fatal (_("failed special case insn sanity check"));
1282 /* Subroutine of md_assemble to do the actual parsing. */
1285 sparc_ip (str
, pinsn
)
1287 const struct sparc_opcode
**pinsn
;
1289 char *error_message
= "";
1293 const struct sparc_opcode
*insn
;
1295 unsigned long opcode
;
1296 unsigned int mask
= 0;
1300 int special_case
= SPECIAL_CASE_NONE
;
1303 if (islower ((unsigned char) *s
))
1307 while (islower ((unsigned char) *s
) || isdigit ((unsigned char) *s
));
1325 as_fatal (_("Unknown opcode: `%s'"), str
);
1327 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1331 as_bad (_("Unknown opcode: `%s'"), str
);
1332 return special_case
;
1342 opcode
= insn
->match
;
1343 memset (&the_insn
, '\0', sizeof (the_insn
));
1344 the_insn
.reloc
= BFD_RELOC_NONE
;
1348 * Build the opcode, checking as we go to make
1349 * sure that the operands match
1351 for (args
= insn
->args
;; ++args
)
1359 /* Parse a series of masks. */
1366 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1369 error_message
= _(": invalid membar mask name");
1373 while (*s
== ' ') { ++s
; continue; }
1374 if (*s
== '|' || *s
== '+')
1376 while (*s
== ' ') { ++s
; continue; }
1381 if (! parse_const_expr_arg (&s
, &kmask
))
1383 error_message
= _(": invalid membar mask expression");
1386 if (kmask
< 0 || kmask
> 127)
1388 error_message
= _(": invalid membar mask number");
1393 opcode
|= MEMBAR (kmask
);
1401 /* Parse a prefetch function. */
1404 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1406 error_message
= _(": invalid prefetch function name");
1412 if (! parse_const_expr_arg (&s
, &fcn
))
1414 error_message
= _(": invalid prefetch function expression");
1417 if (fcn
< 0 || fcn
> 31)
1419 error_message
= _(": invalid prefetch function number");
1429 /* Parse a sparc64 privileged register. */
1432 struct priv_reg_entry
*p
= priv_reg_table
;
1433 unsigned int len
= 9999999; /* init to make gcc happy */
1436 while (p
->name
[0] > s
[0])
1438 while (p
->name
[0] == s
[0])
1440 len
= strlen (p
->name
);
1441 if (strncmp (p
->name
, s
, len
) == 0)
1445 if (p
->name
[0] != s
[0])
1447 error_message
= _(": unrecognizable privileged register");
1451 opcode
|= (p
->regnum
<< 14);
1453 opcode
|= (p
->regnum
<< 25);
1459 error_message
= _(": unrecognizable privileged register");
1465 /* Parse a v9a ancillary state register. */
1468 struct priv_reg_entry
*p
= v9a_asr_table
;
1469 unsigned int len
= 9999999; /* init to make gcc happy */
1472 while (p
->name
[0] > s
[0])
1474 while (p
->name
[0] == s
[0])
1476 len
= strlen (p
->name
);
1477 if (strncmp (p
->name
, s
, len
) == 0)
1481 if (p
->name
[0] != s
[0])
1483 error_message
= _(": unrecognizable v9a ancillary state register");
1486 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1488 error_message
= _(": rd on write only ancillary state register");
1492 opcode
|= (p
->regnum
<< 14);
1494 opcode
|= (p
->regnum
<< 25);
1500 error_message
= _(": unrecognizable v9a ancillary state register");
1506 if (strncmp (s
, "%asr", 4) == 0)
1510 if (isdigit ((unsigned char) *s
))
1514 while (isdigit ((unsigned char) *s
))
1516 num
= num
* 10 + *s
- '0';
1520 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1522 if (num
< 16 || 31 < num
)
1524 error_message
= _(": asr number must be between 16 and 31");
1530 if (num
< 0 || 31 < num
)
1532 error_message
= _(": asr number must be between 0 and 31");
1537 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1542 error_message
= _(": expecting %asrN");
1549 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1553 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1557 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1558 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1559 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1561 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1562 /* These fields are unsigned, but for upward compatibility,
1563 allow negative values as well. */
1567 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1568 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1569 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1571 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1572 /* These fields are unsigned, but for upward compatibility,
1573 allow negative values as well. */
1577 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1582 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1587 if (*s
== 'p' && s
[1] == 'n')
1595 if (*s
== 'p' && s
[1] == 't')
1607 if (strncmp (s
, "%icc", 4) == 0)
1619 if (strncmp (s
, "%xcc", 4) == 0)
1631 if (strncmp (s
, "%fcc0", 5) == 0)
1643 if (strncmp (s
, "%fcc1", 5) == 0)
1655 if (strncmp (s
, "%fcc2", 5) == 0)
1667 if (strncmp (s
, "%fcc3", 5) == 0)
1675 if (strncmp (s
, "%pc", 3) == 0)
1683 if (strncmp (s
, "%tick", 5) == 0)
1690 case '\0': /* end of args */
1709 case '[': /* these must match exactly */
1717 case '#': /* must be at least one digit */
1718 if (isdigit ((unsigned char) *s
++))
1720 while (isdigit ((unsigned char) *s
))
1728 case 'C': /* coprocessor state register */
1729 if (strncmp (s
, "%csr", 4) == 0)
1736 case 'b': /* next operand is a coprocessor register */
1739 if (*s
++ == '%' && *s
++ == 'c' && isdigit ((unsigned char) *s
))
1742 if (isdigit ((unsigned char) *s
))
1744 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1758 opcode
|= mask
<< 14;
1766 opcode
|= mask
<< 25;
1772 case 'r': /* next operand must be a register */
1782 case 'f': /* frame pointer */
1790 case 'g': /* global register */
1799 case 'i': /* in register */
1803 mask
= c
- '0' + 24;
1808 case 'l': /* local register */
1812 mask
= (c
- '0' + 16);
1817 case 'o': /* out register */
1821 mask
= (c
- '0' + 8);
1826 case 's': /* stack pointer */
1834 case 'r': /* any register */
1835 if (!isdigit ((unsigned char) (c
= *s
++)))
1850 if (isdigit ((unsigned char) *s
))
1852 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1868 /* Got the register, now figure out where
1869 it goes in the opcode. */
1873 opcode
|= mask
<< 14;
1881 opcode
|= mask
<< 25;
1885 opcode
|= (mask
<< 25) | (mask
<< 14);
1889 opcode
|= (mask
<< 25) | (mask
<< 0);
1895 case 'e': /* next operand is a floating point register */
1910 && ((format
= *s
) == 'f')
1911 && isdigit ((unsigned char) *++s
))
1913 for (mask
= 0; isdigit ((unsigned char) *s
); ++s
)
1915 mask
= 10 * mask
+ (*s
- '0');
1916 } /* read the number */
1924 } /* register must be even numbered */
1932 } /* register must be multiple of 4 */
1936 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1937 error_message
= _(": There are only 64 f registers; [0-63]");
1939 error_message
= _(": There are only 32 f registers; [0-31]");
1942 else if (mask
>= 32)
1944 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1947 mask
-= 31; /* wrap high bit */
1951 error_message
= _(": There are only 32 f registers; [0-31]");
1959 } /* if not an 'f' register. */
1966 opcode
|= RS1 (mask
);
1973 opcode
|= RS2 (mask
);
1979 opcode
|= RD (mask
);
1988 if (strncmp (s
, "%fsr", 4) == 0)
1995 case '0': /* 64 bit immediate (set, setsw, setx insn) */
1996 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
1999 case 'l': /* 22 bit PC relative immediate */
2000 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2004 case 'L': /* 30 bit immediate */
2005 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2010 case 'n': /* 22 bit immediate */
2011 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2014 case 'i': /* 13 bit immediate */
2015 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2025 char *op_arg
= NULL
;
2027 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2029 /* Check for %hi, etc. */
2032 static const struct ops
{
2033 /* The name as it appears in assembler. */
2035 /* strlen (name), precomputed for speed */
2037 /* The reloc this pseudo-op translates to. */
2039 /* Non-zero if for v9 only. */
2041 /* Non-zero if can be used in pc-relative contexts. */
2042 int pcrel_p
;/*FIXME:wip*/
2044 /* hix/lox must appear before hi/lo so %hix won't be
2045 mistaken for %hi. */
2046 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2047 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2048 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2049 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2050 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2051 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2052 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2053 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2054 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2055 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2056 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2057 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2060 const struct ops
*o
;
2062 for (o
= ops
; o
->name
; o
++)
2063 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2065 if (o
->name
== NULL
)
2068 if (s
[o
->len
+ 1] != '(')
2070 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2071 return special_case
;
2075 the_insn
.reloc
= o
->reloc
;
2080 /* Note that if the get_expression() fails, we will still
2081 have created U entries in the symbol table for the
2082 'symbols' in the input string. Try not to create U
2083 symbols for registers, etc. */
2085 /* This stuff checks to see if the expression ends in
2086 +%reg. If it does, it removes the register from
2087 the expression, and re-sets 's' to point to the
2094 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2097 else if (*s1
== ')')
2106 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2107 return special_case
;
2111 (void) get_expression (s
);
2114 if (*s
== ',' || *s
== ']' || !*s
)
2116 if (*s
!= '+' && *s
!= '-')
2118 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2119 return special_case
;
2123 op_exp
= the_insn
.exp
;
2124 memset (&the_insn
.exp
, 0, sizeof(the_insn
.exp
));
2127 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
2129 if (s1
!= s
&& isdigit ((unsigned char) s1
[-1]))
2131 if (s1
[-2] == '%' && s1
[-3] == '+')
2133 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2140 (void) get_expression (s
);
2152 (void) get_expression (s
);
2160 the_insn
.exp2
= the_insn
.exp
;
2161 the_insn
.exp
= op_exp
;
2162 if (the_insn
.exp2
.X_op
== O_absent
)
2163 the_insn
.exp2
.X_op
= O_illegal
;
2164 else if (the_insn
.exp
.X_op
== O_absent
)
2166 the_insn
.exp
= the_insn
.exp2
;
2167 the_insn
.exp2
.X_op
= O_illegal
;
2169 else if (the_insn
.exp
.X_op
== O_constant
)
2171 valueT val
= the_insn
.exp
.X_add_number
;
2172 switch (the_insn
.reloc
)
2177 case BFD_RELOC_SPARC_HH22
:
2178 val
= BSR (val
, 32);
2179 /* intentional fallthrough */
2181 case BFD_RELOC_SPARC_LM22
:
2182 case BFD_RELOC_HI22
:
2183 val
= (val
>> 10) & 0x3fffff;
2186 case BFD_RELOC_SPARC_HM10
:
2187 val
= BSR (val
, 32);
2188 /* intentional fallthrough */
2190 case BFD_RELOC_LO10
:
2194 case BFD_RELOC_SPARC_H44
:
2199 case BFD_RELOC_SPARC_M44
:
2204 case BFD_RELOC_SPARC_L44
:
2208 case BFD_RELOC_SPARC_HIX22
:
2210 val
= (val
>> 10) & 0x3fffff;
2213 case BFD_RELOC_SPARC_LOX10
:
2214 val
= (val
& 0x3ff) | 0x1c00;
2217 the_insn
.exp
= the_insn
.exp2
;
2218 the_insn
.exp
.X_add_number
+= val
;
2219 the_insn
.exp2
.X_op
= O_illegal
;
2220 the_insn
.reloc
= old_reloc
;
2222 else if (the_insn
.exp2
.X_op
!= O_constant
)
2224 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2225 return special_case
;
2229 if (old_reloc
!= BFD_RELOC_SPARC13
2230 || the_insn
.reloc
!= BFD_RELOC_LO10
2231 || sparc_arch_size
!= 64
2234 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2235 return special_case
;
2237 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2241 /* Check for constants that don't require emitting a reloc. */
2242 if (the_insn
.exp
.X_op
== O_constant
2243 && the_insn
.exp
.X_add_symbol
== 0
2244 && the_insn
.exp
.X_op_symbol
== 0)
2246 /* For pc-relative call instructions, we reject
2247 constants to get better code. */
2249 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2250 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2252 error_message
= _(": PC-relative operand can't be a constant");
2256 /* Constants that won't fit are checked in md_apply_fix3
2257 and bfd_install_relocation.
2258 ??? It would be preferable to install the constants
2259 into the insn here and save having to create a fixS
2260 for each one. There already exists code to handle
2261 all the various cases (e.g. in md_apply_fix3 and
2262 bfd_install_relocation) so duplicating all that code
2263 here isn't right. */
2283 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2285 error_message
= _(": invalid ASI name");
2291 if (! parse_const_expr_arg (&s
, &asi
))
2293 error_message
= _(": invalid ASI expression");
2296 if (asi
< 0 || asi
> 255)
2298 error_message
= _(": invalid ASI number");
2302 opcode
|= ASI (asi
);
2304 } /* alternate space */
2307 if (strncmp (s
, "%psr", 4) == 0)
2314 case 'q': /* floating point queue */
2315 if (strncmp (s
, "%fq", 3) == 0)
2322 case 'Q': /* coprocessor queue */
2323 if (strncmp (s
, "%cq", 3) == 0)
2331 if (strcmp (str
, "set") == 0
2332 || strcmp (str
, "setuw") == 0)
2334 special_case
= SPECIAL_CASE_SET
;
2337 else if (strcmp (str
, "setsw") == 0)
2339 special_case
= SPECIAL_CASE_SETSW
;
2342 else if (strcmp (str
, "setx") == 0)
2344 special_case
= SPECIAL_CASE_SETX
;
2347 else if (strncmp (str
, "fdiv", 4) == 0)
2349 special_case
= SPECIAL_CASE_FDIV
;
2355 if (strncmp (s
, "%asi", 4) != 0)
2361 if (strncmp (s
, "%fprs", 5) != 0)
2367 if (strncmp (s
, "%ccr", 4) != 0)
2373 if (strncmp (s
, "%tbr", 4) != 0)
2379 if (strncmp (s
, "%wim", 4) != 0)
2386 char *push
= input_line_pointer
;
2389 input_line_pointer
= s
;
2391 if (e
.X_op
== O_constant
)
2393 int n
= e
.X_add_number
;
2394 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2395 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2397 opcode
|= e
.X_add_number
<< 5;
2400 as_bad (_("non-immediate OPF operand, ignored"));
2401 s
= input_line_pointer
;
2402 input_line_pointer
= push
;
2407 if (strncmp (s
, "%y", 2) != 0)
2415 /* Parse a sparclet cpreg. */
2417 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2419 error_message
= _(": invalid cpreg name");
2422 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2427 as_fatal (_("failed sanity check."));
2428 } /* switch on arg code */
2430 /* Break out of for() loop. */
2432 } /* for each arg that we expect */
2437 /* Args don't match. */
2438 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2439 && (insn
->name
== insn
[1].name
2440 || !strcmp (insn
->name
, insn
[1].name
)))
2448 as_bad (_("Illegal operands%s"), error_message
);
2449 return special_case
;
2454 /* We have a match. Now see if the architecture is ok. */
2455 int needed_arch_mask
= insn
->architecture
;
2459 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
2460 | (1 << SPARC_OPCODE_ARCH_V9A
));
2461 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2464 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
2466 /* Can we bump up the architecture? */
2467 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
2469 enum sparc_opcode_arch_val needed_architecture
=
2470 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2471 & needed_arch_mask
);
2473 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2475 && needed_architecture
> warn_after_architecture
)
2477 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2478 sparc_opcode_archs
[current_architecture
].name
,
2479 sparc_opcode_archs
[needed_architecture
].name
,
2481 warn_after_architecture
= needed_architecture
;
2483 current_architecture
= needed_architecture
;
2486 /* ??? This seems to be a bit fragile. What if the next entry in
2487 the opcode table is the one we want and it is supported?
2488 It is possible to arrange the table today so that this can't
2489 happen but what about tomorrow? */
2492 int arch
,printed_one_p
= 0;
2494 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2496 /* Create a list of the architectures that support the insn. */
2497 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
2499 arch
= sparc_ffs (needed_arch_mask
);
2500 while ((1 << arch
) <= needed_arch_mask
)
2502 if ((1 << arch
) & needed_arch_mask
)
2506 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2513 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2514 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2516 sparc_opcode_archs
[max_architecture
].name
);
2517 return special_case
;
2522 } /* forever looking for a match */
2524 the_insn
.opcode
= opcode
;
2525 return special_case
;
2528 /* Parse an argument that can be expressed as a keyword.
2529 (eg: #StoreStore or %ccfr).
2530 The result is a boolean indicating success.
2531 If successful, INPUT_POINTER is updated. */
2534 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2535 int (*lookup_fn
) PARAMS ((const char *));
2536 char **input_pointerP
;
2542 p
= *input_pointerP
;
2543 for (q
= p
+ (*p
== '#' || *p
== '%');
2544 isalnum ((unsigned char) *q
) || *q
== '_';
2549 value
= (*lookup_fn
) (p
);
2554 *input_pointerP
= q
;
2558 /* Parse an argument that is a constant expression.
2559 The result is a boolean indicating success. */
2562 parse_const_expr_arg (input_pointerP
, valueP
)
2563 char **input_pointerP
;
2566 char *save
= input_line_pointer
;
2569 input_line_pointer
= *input_pointerP
;
2570 /* The next expression may be something other than a constant
2571 (say if we're not processing the right variant of the insn).
2572 Don't call expression unless we're sure it will succeed as it will
2573 signal an error (which we want to defer until later). */
2574 /* FIXME: It might be better to define md_operand and have it recognize
2575 things like %asi, etc. but continuing that route through to the end
2576 is a lot of work. */
2577 if (*input_line_pointer
== '%')
2579 input_line_pointer
= save
;
2583 *input_pointerP
= input_line_pointer
;
2584 input_line_pointer
= save
;
2585 if (exp
.X_op
!= O_constant
)
2587 *valueP
= exp
.X_add_number
;
2591 /* Subroutine of sparc_ip to parse an expression. */
2594 get_expression (str
)
2600 save_in
= input_line_pointer
;
2601 input_line_pointer
= str
;
2602 seg
= expression (&the_insn
.exp
);
2603 if (seg
!= absolute_section
2604 && seg
!= text_section
2605 && seg
!= data_section
2606 && seg
!= bss_section
2607 && seg
!= undefined_section
)
2609 the_insn
.error
= _("bad segment");
2610 expr_end
= input_line_pointer
;
2611 input_line_pointer
= save_in
;
2614 expr_end
= input_line_pointer
;
2615 input_line_pointer
= save_in
;
2619 /* Subroutine of md_assemble to output one insn. */
2622 output_insn (insn
, the_insn
)
2623 const struct sparc_opcode
*insn
;
2624 struct sparc_it
*the_insn
;
2626 char *toP
= frag_more (4);
2628 /* put out the opcode */
2629 if (INSN_BIG_ENDIAN
)
2630 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2632 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2634 /* put out the symbol-dependent stuff */
2635 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2637 fixS
*fixP
= fix_new_exp (frag_now
, /* which frag */
2638 (toP
- frag_now
->fr_literal
), /* where */
2643 /* Turn off overflow checking in fixup_segment. We'll do our
2644 own overflow checking in md_apply_fix3. This is necessary because
2645 the insn size is 4 and fixup_segment will signal an overflow for
2646 large 8 byte quantities. */
2647 fixP
->fx_no_overflow
= 1;
2648 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2649 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2653 last_opcode
= the_insn
->opcode
;
2657 This is identical to the md_atof in m68k.c. I think this is right,
2660 Turn a string in input_line_pointer into a floating point constant of type
2661 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2662 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2665 /* Equal to MAX_PRECISION in atof-ieee.c */
2666 #define MAX_LITTLENUMS 6
2669 md_atof (type
, litP
, sizeP
)
2675 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2706 return _("Bad call to MD_ATOF()");
2709 t
= atof_ieee (input_line_pointer
, type
, words
);
2711 input_line_pointer
= t
;
2712 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2714 if (target_big_endian
)
2716 for (i
= 0; i
< prec
; i
++)
2718 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2719 litP
+= sizeof (LITTLENUM_TYPE
);
2724 for (i
= prec
- 1; i
>= 0; i
--)
2726 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2727 litP
+= sizeof (LITTLENUM_TYPE
);
2734 /* Write a value out to the object file, using the appropriate
2738 md_number_to_chars (buf
, val
, n
)
2743 if (target_big_endian
)
2744 number_to_chars_bigendian (buf
, val
, n
);
2745 else if (target_little_endian_data
2746 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2747 /* Output debug words, which are not in allocated sections, as big endian */
2748 number_to_chars_bigendian (buf
, val
, n
);
2749 else if (target_little_endian_data
|| ! target_big_endian
)
2750 number_to_chars_littleendian (buf
, val
, n
);
2753 /* Apply a fixS to the frags, now that we know the value it ought to
2757 md_apply_fix3 (fixP
, value
, segment
)
2762 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2768 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2770 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2773 /* FIXME: SPARC ELF relocations don't use an addend in the data
2774 field itself. This whole approach should be somehow combined
2775 with the calls to bfd_install_relocation. Also, the value passed
2776 in by fixup_segment includes the value of a defined symbol. We
2777 don't want to include the value of an externally visible symbol. */
2778 if (fixP
->fx_addsy
!= NULL
)
2780 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
2781 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2782 || S_IS_WEAK (fixP
->fx_addsy
)
2783 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2784 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2785 && ((bfd_get_section_flags (stdoutput
,
2786 S_GET_SEGMENT (fixP
->fx_addsy
))
2787 & SEC_LINK_ONCE
) != 0
2788 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2790 sizeof ".gnu.linkonce" - 1) == 0)))
2791 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2792 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2793 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2794 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2799 /* This is a hack. There should be a better way to
2800 handle this. Probably in terms of howto fields, once
2801 we can look at these fixups in terms of howtos. */
2802 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2803 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2806 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2807 generate a reloc, then we just want to let the reloc addend set
2808 the value. We do not want to also stuff the addend into the
2809 object file. Including the addend in the object file works when
2810 doing a static link, because the linker will ignore the object
2811 file contents. However, the dynamic linker does not ignore the
2812 object file contents. */
2813 if (fixP
->fx_addsy
!= NULL
2814 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2817 /* When generating PIC code, we do not want an addend for a reloc
2818 against a local symbol. We adjust fx_addnumber to cancel out the
2819 value already included in val, and to also cancel out the
2820 adjustment which bfd_install_relocation will create. */
2822 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2823 && fixP
->fx_addsy
!= NULL
2824 && ! S_IS_COMMON (fixP
->fx_addsy
)
2825 && symbol_section_p (fixP
->fx_addsy
))
2826 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2828 /* When generating PIC code, we need to fiddle to get
2829 bfd_install_relocation to do the right thing for a PC relative
2830 reloc against a local symbol which we are going to keep. */
2832 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
2833 && fixP
->fx_addsy
!= NULL
2834 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2835 || S_IS_WEAK (fixP
->fx_addsy
))
2836 && S_IS_DEFINED (fixP
->fx_addsy
)
2837 && ! S_IS_COMMON (fixP
->fx_addsy
))
2840 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2844 /* If this is a data relocation, just output VAL. */
2846 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2848 md_number_to_chars (buf
, val
, 2);
2850 else if (fixP
->fx_r_type
== BFD_RELOC_32
2851 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
2853 md_number_to_chars (buf
, val
, 4);
2855 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2857 md_number_to_chars (buf
, val
, 8);
2859 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2860 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2867 /* It's a relocation against an instruction. */
2869 if (INSN_BIG_ENDIAN
)
2870 insn
= bfd_getb32 ((unsigned char *) buf
);
2872 insn
= bfd_getl32 ((unsigned char *) buf
);
2874 switch (fixP
->fx_r_type
)
2876 case BFD_RELOC_32_PCREL_S2
:
2878 /* FIXME: This increment-by-one deserves a comment of why it's
2880 if (! sparc_pic_code
2881 || fixP
->fx_addsy
== NULL
2882 || symbol_section_p (fixP
->fx_addsy
))
2884 insn
|= val
& 0x3fffffff;
2887 case BFD_RELOC_SPARC_11
:
2888 if (! in_signed_range (val
, 0x7ff))
2889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2890 _("relocation overflow"));
2891 insn
|= val
& 0x7ff;
2894 case BFD_RELOC_SPARC_10
:
2895 if (! in_signed_range (val
, 0x3ff))
2896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2897 _("relocation overflow"));
2898 insn
|= val
& 0x3ff;
2901 case BFD_RELOC_SPARC_7
:
2902 if (! in_bitfield_range (val
, 0x7f))
2903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2904 _("relocation overflow"));
2908 case BFD_RELOC_SPARC_6
:
2909 if (! in_bitfield_range (val
, 0x3f))
2910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2911 _("relocation overflow"));
2915 case BFD_RELOC_SPARC_5
:
2916 if (! in_bitfield_range (val
, 0x1f))
2917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2918 _("relocation overflow"));
2922 case BFD_RELOC_SPARC_WDISP16
:
2923 /* FIXME: simplify */
2924 if (((val
> 0) && (val
& ~0x3fffc))
2925 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2927 _("relocation overflow"));
2928 /* FIXME: The +1 deserves a comment. */
2929 val
= (val
>> 2) + 1;
2930 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2933 case BFD_RELOC_SPARC_WDISP19
:
2934 /* FIXME: simplify */
2935 if (((val
> 0) && (val
& ~0x1ffffc))
2936 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2938 _("relocation overflow"));
2939 /* FIXME: The +1 deserves a comment. */
2940 val
= (val
>> 2) + 1;
2941 insn
|= val
& 0x7ffff;
2944 case BFD_RELOC_SPARC_HH22
:
2945 val
= BSR (val
, 32);
2946 /* intentional fallthrough */
2948 case BFD_RELOC_SPARC_LM22
:
2949 case BFD_RELOC_HI22
:
2950 if (!fixP
->fx_addsy
)
2952 insn
|= (val
>> 10) & 0x3fffff;
2956 /* FIXME: Need comment explaining why we do this. */
2961 case BFD_RELOC_SPARC22
:
2962 if (val
& ~0x003fffff)
2963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2964 _("relocation overflow"));
2965 insn
|= (val
& 0x3fffff);
2968 case BFD_RELOC_SPARC_HM10
:
2969 val
= BSR (val
, 32);
2970 /* intentional fallthrough */
2972 case BFD_RELOC_LO10
:
2973 if (!fixP
->fx_addsy
)
2975 insn
|= val
& 0x3ff;
2979 /* FIXME: Need comment explaining why we do this. */
2984 case BFD_RELOC_SPARC_OLO10
:
2986 val
+= fixP
->tc_fix_data
;
2987 /* intentional fallthrough */
2989 case BFD_RELOC_SPARC13
:
2990 if (! in_signed_range (val
, 0x1fff))
2991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2992 _("relocation overflow"));
2993 insn
|= val
& 0x1fff;
2996 case BFD_RELOC_SPARC_WDISP22
:
2997 val
= (val
>> 2) + 1;
2999 case BFD_RELOC_SPARC_BASE22
:
3000 insn
|= val
& 0x3fffff;
3003 case BFD_RELOC_SPARC_H44
:
3004 if (!fixP
->fx_addsy
)
3008 insn
|= tval
& 0x3fffff;
3012 case BFD_RELOC_SPARC_M44
:
3013 if (!fixP
->fx_addsy
)
3014 insn
|= (val
>> 12) & 0x3ff;
3017 case BFD_RELOC_SPARC_L44
:
3018 if (!fixP
->fx_addsy
)
3019 insn
|= val
& 0xfff;
3022 case BFD_RELOC_SPARC_HIX22
:
3023 if (!fixP
->fx_addsy
)
3025 val
^= ~ (offsetT
) 0;
3026 insn
|= (val
>> 10) & 0x3fffff;
3030 case BFD_RELOC_SPARC_LOX10
:
3031 if (!fixP
->fx_addsy
)
3032 insn
|= 0x1c00 | (val
& 0x3ff);
3035 case BFD_RELOC_NONE
:
3037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3038 _("bad or unhandled relocation type: 0x%02x"),
3043 if (INSN_BIG_ENDIAN
)
3044 bfd_putb32 (insn
, (unsigned char *) buf
);
3046 bfd_putl32 (insn
, (unsigned char *) buf
);
3049 /* Are we finished with this relocation now? */
3050 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3056 /* Translate internal representation of relocation info to BFD target
3059 tc_gen_reloc (section
, fixp
)
3063 static arelent
*relocs
[3];
3065 bfd_reloc_code_real_type code
;
3067 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3070 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3071 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3072 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3074 switch (fixp
->fx_r_type
)
3078 case BFD_RELOC_HI22
:
3079 case BFD_RELOC_LO10
:
3080 case BFD_RELOC_32_PCREL_S2
:
3081 case BFD_RELOC_SPARC13
:
3082 case BFD_RELOC_SPARC22
:
3083 case BFD_RELOC_SPARC_BASE13
:
3084 case BFD_RELOC_SPARC_WDISP16
:
3085 case BFD_RELOC_SPARC_WDISP19
:
3086 case BFD_RELOC_SPARC_WDISP22
:
3088 case BFD_RELOC_SPARC_5
:
3089 case BFD_RELOC_SPARC_6
:
3090 case BFD_RELOC_SPARC_7
:
3091 case BFD_RELOC_SPARC_10
:
3092 case BFD_RELOC_SPARC_11
:
3093 case BFD_RELOC_SPARC_HH22
:
3094 case BFD_RELOC_SPARC_HM10
:
3095 case BFD_RELOC_SPARC_LM22
:
3096 case BFD_RELOC_SPARC_PC_HH22
:
3097 case BFD_RELOC_SPARC_PC_HM10
:
3098 case BFD_RELOC_SPARC_PC_LM22
:
3099 case BFD_RELOC_SPARC_H44
:
3100 case BFD_RELOC_SPARC_M44
:
3101 case BFD_RELOC_SPARC_L44
:
3102 case BFD_RELOC_SPARC_HIX22
:
3103 case BFD_RELOC_SPARC_LOX10
:
3104 case BFD_RELOC_SPARC_REV32
:
3105 case BFD_RELOC_SPARC_OLO10
:
3106 case BFD_RELOC_VTABLE_ENTRY
:
3107 case BFD_RELOC_VTABLE_INHERIT
:
3108 code
= fixp
->fx_r_type
;
3115 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3116 /* If we are generating PIC code, we need to generate a different
3120 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3122 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3129 case BFD_RELOC_32_PCREL_S2
:
3130 if (! S_IS_DEFINED (fixp
->fx_addsy
)
3131 || S_IS_COMMON (fixp
->fx_addsy
)
3132 || S_IS_EXTERNAL (fixp
->fx_addsy
)
3133 || S_IS_WEAK (fixp
->fx_addsy
))
3134 code
= BFD_RELOC_SPARC_WPLT30
;
3136 case BFD_RELOC_HI22
:
3137 if (fixp
->fx_addsy
!= NULL
3138 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3139 code
= BFD_RELOC_SPARC_PC22
;
3141 code
= BFD_RELOC_SPARC_GOT22
;
3143 case BFD_RELOC_LO10
:
3144 if (fixp
->fx_addsy
!= NULL
3145 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3146 code
= BFD_RELOC_SPARC_PC10
;
3148 code
= BFD_RELOC_SPARC_GOT10
;
3150 case BFD_RELOC_SPARC13
:
3151 code
= BFD_RELOC_SPARC_GOT13
;
3157 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3159 if (code
== BFD_RELOC_SPARC_OLO10
)
3160 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3162 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3163 if (reloc
->howto
== 0)
3165 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3166 _("internal error: can't export reloc type %d (`%s')"),
3167 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3173 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3176 if (reloc
->howto
->pc_relative
== 0
3177 || code
== BFD_RELOC_SPARC_PC10
3178 || code
== BFD_RELOC_SPARC_PC22
)
3179 reloc
->addend
= fixp
->fx_addnumber
;
3180 else if (sparc_pic_code
3181 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3182 && fixp
->fx_addsy
!= NULL
3183 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3184 || S_IS_WEAK (fixp
->fx_addsy
))
3185 && S_IS_DEFINED (fixp
->fx_addsy
)
3186 && ! S_IS_COMMON (fixp
->fx_addsy
))
3187 reloc
->addend
= fixp
->fx_addnumber
;
3189 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3191 #else /* elf or coff */
3193 if (reloc
->howto
->pc_relative
== 0
3194 || code
== BFD_RELOC_SPARC_PC10
3195 || code
== BFD_RELOC_SPARC_PC22
)
3196 reloc
->addend
= fixp
->fx_addnumber
;
3197 else if (symbol_section_p (fixp
->fx_addsy
))
3198 reloc
->addend
= (section
->vma
3199 + fixp
->fx_addnumber
3200 + md_pcrel_from (fixp
));
3202 reloc
->addend
= fixp
->fx_offset
;
3205 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3206 on the same location. */
3207 if (code
== BFD_RELOC_SPARC_OLO10
)
3209 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3212 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3213 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (section_symbol (absolute_section
));
3214 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3215 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3216 reloc
->addend
= fixp
->tc_fix_data
;
3222 /* We have no need to default values of symbols. */
3226 md_undefined_symbol (name
)
3230 } /* md_undefined_symbol() */
3232 /* Round up a section size to the appropriate boundary. */
3234 md_section_align (segment
, size
)
3239 /* This is not right for ELF; a.out wants it, and COFF will force
3240 the alignment anyways. */
3241 valueT align
= ((valueT
) 1
3242 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3244 /* turn alignment value into a mask */
3246 newsize
= (size
+ align
) & ~align
;
3253 /* Exactly what point is a PC-relative offset relative TO?
3254 On the sparc, they're relative to the address of the offset, plus
3255 its size. This gets us to the following instruction.
3256 (??? Is this right? FIXME-SOON) */
3258 md_pcrel_from (fixP
)
3263 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3264 if (! sparc_pic_code
3265 || fixP
->fx_addsy
== NULL
3266 || symbol_section_p (fixP
->fx_addsy
))
3267 ret
+= fixP
->fx_size
;
3271 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3283 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3286 return (value
== 1) ? shift
: -1;
3290 * sort of like s_lcomm
3294 static int max_alignment
= 15;
3309 name
= input_line_pointer
;
3310 c
= get_symbol_end ();
3311 p
= input_line_pointer
;
3315 if (*input_line_pointer
!= ',')
3317 as_bad (_("Expected comma after name"));
3318 ignore_rest_of_line ();
3322 ++input_line_pointer
;
3324 if ((size
= get_absolute_expression ()) < 0)
3326 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3327 ignore_rest_of_line ();
3332 symbolP
= symbol_find_or_make (name
);
3335 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3336 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3338 as_bad (_("bad .reserve segment -- expected BSS segment"));
3342 if (input_line_pointer
[2] == '.')
3343 input_line_pointer
+= 7;
3345 input_line_pointer
+= 6;
3348 if (*input_line_pointer
== ',')
3350 ++input_line_pointer
;
3353 if (*input_line_pointer
== '\n')
3355 as_bad (_("missing alignment"));
3356 ignore_rest_of_line ();
3360 align
= (int) get_absolute_expression ();
3363 if (align
> max_alignment
)
3365 align
= max_alignment
;
3366 as_warn (_("alignment too large; assuming %d"), align
);
3372 as_bad (_("negative alignment"));
3373 ignore_rest_of_line ();
3379 temp
= log2 (align
);
3382 as_bad (_("alignment not a power of 2"));
3383 ignore_rest_of_line ();
3390 record_alignment (bss_section
, align
);
3395 if (!S_IS_DEFINED (symbolP
)
3397 && S_GET_OTHER (symbolP
) == 0
3398 && S_GET_DESC (symbolP
) == 0
3405 segT current_seg
= now_seg
;
3406 subsegT current_subseg
= now_subseg
;
3408 subseg_set (bss_section
, 1); /* switch to bss */
3411 frag_align (align
, 0, 0); /* do alignment */
3413 /* detach from old frag */
3414 if (S_GET_SEGMENT(symbolP
) == bss_section
)
3415 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3417 symbol_set_frag (symbolP
, frag_now
);
3418 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
3419 (offsetT
) size
, (char *)0);
3422 S_SET_SEGMENT (symbolP
, bss_section
);
3424 subseg_set (current_seg
, current_subseg
);
3427 S_SET_SIZE (symbolP
, size
);
3433 as_warn("Ignoring attempt to re-define symbol %s",
3434 S_GET_NAME (symbolP
));
3435 } /* if not redefining */
3437 demand_empty_rest_of_line ();
3450 name
= input_line_pointer
;
3451 c
= get_symbol_end ();
3452 /* just after name is now '\0' */
3453 p
= input_line_pointer
;
3456 if (*input_line_pointer
!= ',')
3458 as_bad (_("Expected comma after symbol-name"));
3459 ignore_rest_of_line ();
3462 input_line_pointer
++; /* skip ',' */
3463 if ((temp
= get_absolute_expression ()) < 0)
3465 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp
);
3466 ignore_rest_of_line ();
3471 symbolP
= symbol_find_or_make (name
);
3473 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3475 as_bad (_("Ignoring attempt to re-define symbol"));
3476 ignore_rest_of_line ();
3479 if (S_GET_VALUE (symbolP
) != 0)
3481 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3483 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3484 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3490 S_SET_VALUE (symbolP
, (valueT
) size
);
3491 S_SET_EXTERNAL (symbolP
);
3494 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3495 if (*input_line_pointer
!= ',')
3497 as_bad (_("Expected comma after common length"));
3498 ignore_rest_of_line ();
3501 input_line_pointer
++;
3503 if (*input_line_pointer
!= '"')
3505 temp
= get_absolute_expression ();
3508 if (temp
> max_alignment
)
3510 temp
= max_alignment
;
3511 as_warn (_("alignment too large; assuming %d"), temp
);
3517 as_bad (_("negative alignment"));
3518 ignore_rest_of_line ();
3523 if (symbol_get_obj (symbolP
)->local
)
3531 old_subsec
= now_subseg
;
3536 align
= log2 (temp
);
3540 as_bad (_("alignment not a power of 2"));
3541 ignore_rest_of_line ();
3545 record_alignment (bss_section
, align
);
3546 subseg_set (bss_section
, 0);
3548 frag_align (align
, 0, 0);
3549 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3550 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3551 symbol_set_frag (symbolP
, frag_now
);
3552 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3553 (offsetT
) size
, (char *) 0);
3555 S_SET_SEGMENT (symbolP
, bss_section
);
3556 S_CLEAR_EXTERNAL (symbolP
);
3557 S_SET_SIZE (symbolP
, size
);
3558 subseg_set (old_sec
, old_subsec
);
3561 #endif /* OBJ_ELF */
3564 S_SET_VALUE (symbolP
, (valueT
) size
);
3566 S_SET_ALIGN (symbolP
, temp
);
3567 S_SET_SIZE (symbolP
, size
);
3569 S_SET_EXTERNAL (symbolP
);
3570 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3575 input_line_pointer
++;
3576 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3577 if (*input_line_pointer
== '.')
3578 input_line_pointer
++;
3579 /* @@ Some say data, some say bss. */
3580 if (strncmp (input_line_pointer
, "bss\"", 4)
3581 && strncmp (input_line_pointer
, "data\"", 5))
3583 while (*--input_line_pointer
!= '"')
3585 input_line_pointer
--;
3586 goto bad_common_segment
;
3588 while (*input_line_pointer
++ != '"')
3590 goto allocate_common
;
3593 #ifdef BFD_ASSEMBLER
3594 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3597 demand_empty_rest_of_line ();
3602 p
= input_line_pointer
;
3603 while (*p
&& *p
!= '\n')
3607 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3609 input_line_pointer
= p
;
3610 ignore_rest_of_line ();
3615 /* Handle the .empty pseudo-op. This supresses the warnings about
3616 invalid delay slot usage. */
3622 /* The easy way to implement is to just forget about the last
3632 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3634 input_line_pointer
+= 6;
3638 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3640 input_line_pointer
+= 6;
3644 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3646 input_line_pointer
+= 7;
3650 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3652 input_line_pointer
+= 5;
3653 /* We only support 2 segments -- text and data -- for now, so
3654 things in the "bss segment" will have to go into data for now.
3655 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3656 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
3659 as_bad (_("Unknown segment type"));
3660 demand_empty_rest_of_line ();
3666 subseg_set (data_section
, 1);
3667 demand_empty_rest_of_line ();
3674 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3676 ++input_line_pointer
;
3678 ++input_line_pointer
;
3681 /* This static variable is set by s_uacons to tell sparc_cons_align
3682 that the expession does not need to be aligned. */
3684 static int sparc_no_align_cons
= 0;
3686 /* This handles the unaligned space allocation pseudo-ops, such as
3687 .uaword. .uaword is just like .word, but the value does not need
3694 /* Tell sparc_cons_align not to align this value. */
3695 sparc_no_align_cons
= 1;
3699 /* This handles the native word allocation pseudo-op .nword.
3700 For sparc_arch_size 32 it is equivalent to .word, for
3701 sparc_arch_size 64 it is equivalent to .xword. */
3707 cons (sparc_arch_size
== 32 ? 4 : 8);
3710 /* If the --enforce-aligned-data option is used, we require .word,
3711 et. al., to be aligned correctly. We do it by setting up an
3712 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3713 no unexpected alignment was introduced.
3715 The SunOS and Solaris native assemblers enforce aligned data by
3716 default. We don't want to do that, because gcc can deliberately
3717 generate misaligned data if the packed attribute is used. Instead,
3718 we permit misaligned data by default, and permit the user to set an
3719 option to check for it. */
3722 sparc_cons_align (nbytes
)
3728 /* Only do this if we are enforcing aligned data. */
3729 if (! enforce_aligned_data
)
3732 if (sparc_no_align_cons
)
3734 /* This is an unaligned pseudo-op. */
3735 sparc_no_align_cons
= 0;
3739 nalign
= log2 (nbytes
);
3743 assert (nalign
> 0);
3745 if (now_seg
== absolute_section
)
3747 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
3748 as_bad (_("misaligned data"));
3752 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
3753 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
3755 record_alignment (now_seg
, nalign
);
3758 /* This is where we do the unexpected alignment check.
3759 This is called from HANDLE_ALIGN in tc-sparc.h. */
3762 sparc_handle_align (fragp
)
3765 if (fragp
->fr_type
== rs_align_code
&& !fragp
->fr_subtype
3766 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
3767 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
3768 if (fragp
->fr_type
== rs_align_code
&& fragp
->fr_subtype
== 1024)
3770 int count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
3775 && !((long)(fragp
->fr_literal
+ fragp
->fr_fix
) & 3))
3777 unsigned *p
= (unsigned *)(fragp
->fr_literal
+ fragp
->fr_fix
);
3780 for (i
= 0; i
< count
; i
+= 4, p
++)
3781 if (INSN_BIG_ENDIAN
)
3782 number_to_chars_bigendian ((char *)p
, 0x01000000, 4); /* emit nops */
3784 number_to_chars_littleendian ((char *)p
, 0x10000000, 4);
3786 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
3788 char *waddr
= &fragp
->fr_literal
[fragp
->fr_fix
];
3789 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
3790 if (INSN_BIG_ENDIAN
)
3791 number_to_chars_bigendian (waddr
, wval
, 4);
3793 number_to_chars_littleendian (waddr
, wval
, 4);
3795 fragp
->fr_var
= count
;
3801 /* Some special processing for a Sparc ELF file. */
3804 sparc_elf_final_processing ()
3806 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3807 sort of BFD interface for this. */
3808 if (sparc_arch_size
== 64)
3810 switch (sparc_memory_model
)
3813 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
3816 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
3822 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
3823 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
3824 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
3825 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
3829 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3830 reloc for a cons. We could use the definition there, except that
3831 we want to handle little endian relocs specially. */
3834 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
3837 unsigned int nbytes
;
3840 bfd_reloc_code_real_type r
;
3842 r
= (nbytes
== 1 ? BFD_RELOC_8
:
3843 (nbytes
== 2 ? BFD_RELOC_16
:
3844 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
3846 if (target_little_endian_data
&& nbytes
== 4
3847 && now_seg
->flags
& SEC_ALLOC
)
3848 r
= BFD_RELOC_SPARC_REV32
;
3849 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
3854 elf32_sparc_force_relocation (fixp
)
3857 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3858 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)