1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
28 #include "xtensa-relax.h"
29 #include "dwarf2dbg.h"
30 #include "xtensa-istack.h"
31 #include "struc-symbol.h"
32 #include "xtensa-config.h"
34 /* Provide default values for new configuration settings. */
40 #define uint32 unsigned int
43 #define int32 signed int
48 Naming conventions (used somewhat inconsistently):
49 The xtensa_ functions are exported
50 The xg_ functions are internal
52 We also have a couple of different extensibility mechanisms.
53 1) The idiom replacement:
54 This is used when a line is first parsed to
55 replace an instruction pattern with another instruction
56 It is currently limited to replacements of instructions
57 with constant operands.
58 2) The xtensa-relax.c mechanism that has stronger instruction
59 replacement patterns. When an instruction's immediate field
60 does not fit the next instruction sequence is attempted.
61 In addition, "narrow" opcodes are supported this way. */
64 /* Define characters with special meanings to GAS. */
65 const char comment_chars
[] = "#";
66 const char line_comment_chars
[] = "#";
67 const char line_separator_chars
[] = ";";
68 const char EXP_CHARS
[] = "eE";
69 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
72 /* Flags to indicate whether the hardware supports the density and
73 absolute literals options. */
75 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
76 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
78 static vliw_insn cur_vinsn
;
80 unsigned xtensa_num_pipe_stages
;
81 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
83 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
85 /* Some functions are only valid in the front end. This variable
86 allows us to assert that we haven't crossed over into the
88 static bfd_boolean past_xtensa_end
= FALSE
;
90 /* Flags for properties of the last instruction in a segment. */
91 #define FLAG_IS_A0_WRITER 0x1
92 #define FLAG_IS_BAD_LOOPEND 0x2
95 /* We define a special segment names ".literal" to place literals
96 into. The .fini and .init sections are special because they
97 contain code that is moved together by the linker. We give them
98 their own special .fini.literal and .init.literal sections. */
100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. If lit_prefix is set, it is
108 used to determine the literal section names; otherwise, the literal
109 sections are determined based on the current text section. The
110 lit_seg and lit4_seg fields cache these literal sections, with the
111 current_text_seg field used a tag to indicate whether the cached
114 typedef struct lit_state_struct
117 segT current_text_seg
;
122 static lit_state default_lit_sections
;
125 /* We keep a list of literal segments. The seg_list type is the node
126 for this list. The literal_head pointer is the head of the list,
127 with the literal_head_h dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
139 /* Lists of symbols. We keep a list of symbols that label the current
140 instruction, so that we can adjust the symbols when inserting alignment
141 for various instructions. We also keep a list of all the symbols on
142 literals, so that we can fix up those symbols when the literals are
143 later moved into the text sections. */
145 typedef struct sym_list_struct
147 struct sym_list_struct
*next
;
151 static sym_list
*insn_labels
= NULL
;
152 static sym_list
*free_insn_labels
= NULL
;
153 static sym_list
*saved_insn_labels
= NULL
;
155 static sym_list
*literal_syms
;
158 /* Flags to determine whether to prefer const16 or l32r
159 if both options are available. */
160 int prefer_const16
= 0;
163 /* Global flag to indicate when we are emitting literals. */
164 int generating_literals
= 0;
166 /* The following PROPERTY table definitions are copied from
167 <elf/xtensa.h> and must be kept in sync with the code there. */
169 /* Flags in the property tables to specify whether blocks of memory
170 are literals, instructions, data, or unreachable. For
171 instructions, blocks that begin loop targets and branch targets are
172 designated. Blocks that do not allow density, instruction
173 reordering or transformation are also specified. Finally, for
174 branch targets, branch target alignment priority is included.
175 Alignment of the next block is specified in the current block
176 and the size of the current block does not include any fill required
177 to align to the next block. */
179 #define XTENSA_PROP_LITERAL 0x00000001
180 #define XTENSA_PROP_INSN 0x00000002
181 #define XTENSA_PROP_DATA 0x00000004
182 #define XTENSA_PROP_UNREACHABLE 0x00000008
183 /* Instruction only properties at beginning of code. */
184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
186 /* Instruction only properties about code. */
187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190 but it should apply to literals under certain circumstances. */
191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
193 /* Branch target alignment information. This transmits information
194 to the linker optimization about the priority of aligning a
195 particular block for branch target alignment: None, low priority,
196 high priority, or required. These only need to be checked in
197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201 case XTENSA_PROP_BT_ALIGN_NONE:
202 case XTENSA_PROP_BT_ALIGN_LOW:
203 case XTENSA_PROP_BT_ALIGN_HIGH:
204 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208 /* No branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
210 /* Low priority branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
212 /* High priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
214 /* Required branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
218 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
219 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
220 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
221 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
224 /* Alignment is specified in the block BEFORE the one that needs
225 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
226 get the required alignment specified as a power of 2. Use
227 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
228 alignment. Be careful of side effects since the SET will evaluate
229 flags twice. Also, note that the SIZE of a block in the property
230 table does not include the alignment size, so the alignment fill
231 must be calculated to determine if two blocks are contiguous.
232 TEXT_ALIGN is not currently implemented but is a placeholder for a
233 possible future implementation. */
235 #define XTENSA_PROP_ALIGN 0x00000800
237 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
239 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
240 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
241 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
242 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
243 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
245 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
248 /* Structure for saving instruction and alignment per-fragment data
249 that will be written to the object file. This structure is
250 equivalent to the actual data that will be written out to the file
251 but is easier to use. We provide a conversion to file flags
252 in frag_flags_to_number. */
254 typedef struct frag_flags_struct frag_flags
;
256 struct frag_flags_struct
258 /* is_literal should only be used after xtensa_move_literals.
259 If you need to check if you are generating a literal fragment,
260 then use the generating_literals global. */
262 unsigned is_literal
: 1;
263 unsigned is_insn
: 1;
264 unsigned is_data
: 1;
265 unsigned is_unreachable
: 1;
267 /* is_specific_opcode implies no_transform. */
268 unsigned is_no_transform
: 1;
272 unsigned is_loop_target
: 1;
273 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
274 unsigned bt_align_priority
: 2;
276 unsigned is_no_density
: 1;
277 /* no_longcalls flag does not need to be placed in the object file. */
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 xtensa_format narrowest
;
334 /* formats is a bitfield with the Nth bit set
335 if the opcode fits in the Nth xtensa_format. */
338 /* slots[N]'s Mth bit is set if the op fits in the
339 Mth slot of the Nth xtensa_format. */
340 bitfield slots
[MAX_FORMATS
];
342 /* A count of the number of slots in a given format
343 an op can fit (i.e., the bitcount of the slot field above). */
344 char slots_in_format
[MAX_FORMATS
];
346 } op_placement_info
, *op_placement_info_table
;
348 op_placement_info_table op_placement_table
;
351 /* Extra expression types. */
353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
356 #define O_pcrel O_md4 /* value is a PC-relative offset */
357 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
358 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
359 #define O_tlscall O_md7 /* TLS_CALL relocation */
360 #define O_tpoff O_md8 /* TPOFF relocation */
361 #define O_dtpoff O_md9 /* DTPOFF relocation */
363 struct suffix_reloc_map
367 bfd_reloc_code_real_type reloc
;
368 unsigned char operator;
371 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
373 static struct suffix_reloc_map suffix_relocs
[] =
375 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
376 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
377 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
378 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
379 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
380 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
381 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
382 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
383 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
384 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
398 directive_literal_prefix
,
400 directive_absolute_literals
,
401 directive_last_directive
407 bfd_boolean can_be_negated
;
410 const directive_infoS directive_info
[] =
413 { "literal", FALSE
},
415 { "transform", TRUE
},
416 { "freeregs", FALSE
},
417 { "longcalls", TRUE
},
418 { "literal_prefix", FALSE
},
419 { "schedule", TRUE
},
420 { "absolute-literals", TRUE
}
423 bfd_boolean directive_state
[] =
427 #if !XCHAL_HAVE_DENSITY
432 TRUE
, /* transform */
433 FALSE
, /* freeregs */
434 FALSE
, /* longcalls */
435 FALSE
, /* literal_prefix */
436 FALSE
, /* schedule */
437 #if XSHAL_USE_ABSOLUTE_LITERALS
438 TRUE
/* absolute_literals */
440 FALSE
/* absolute_literals */
445 /* Directive functions. */
447 static void xtensa_begin_directive (int);
448 static void xtensa_end_directive (int);
449 static void xtensa_literal_prefix (void);
450 static void xtensa_literal_position (int);
451 static void xtensa_literal_pseudo (int);
452 static void xtensa_frequency_pseudo (int);
453 static void xtensa_elf_cons (int);
454 static void xtensa_leb128 (int);
456 /* Parsing and Idiom Translation. */
458 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
460 /* Various Other Internal Functions. */
462 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
463 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
464 static void xtensa_mark_literal_pool_location (void);
465 static addressT
get_expanded_loop_offset (xtensa_opcode
);
466 static fragS
*get_literal_pool_location (segT
);
467 static void set_literal_pool_location (segT
, fragS
*);
468 static void xtensa_set_frag_assembly_state (fragS
*);
469 static void finish_vinsn (vliw_insn
*);
470 static bfd_boolean
emit_single_op (TInsn
*);
471 static int total_frag_text_expansion (fragS
*);
473 /* Alignment Functions. */
475 static int get_text_align_power (unsigned);
476 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
477 static int branch_align_power (segT
);
479 /* Helpers for xtensa_relax_frag(). */
481 static long relax_frag_add_nop (fragS
*);
483 /* Accessors for additional per-subsegment information. */
485 static unsigned get_last_insn_flags (segT
, subsegT
);
486 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
487 static float get_subseg_total_freq (segT
, subsegT
);
488 static float get_subseg_target_freq (segT
, subsegT
);
489 static void set_subseg_freq (segT
, subsegT
, float, float);
491 /* Segment list functions. */
493 static void xtensa_move_literals (void);
494 static void xtensa_reorder_segments (void);
495 static void xtensa_switch_to_literal_fragment (emit_state
*);
496 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
497 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
498 static void xtensa_restore_emit_state (emit_state
*);
499 static segT
cache_literal_section (bfd_boolean
);
501 /* Import from elf32-xtensa.c in BFD library. */
503 extern asection
*xtensa_make_property_section (asection
*, const char *);
505 /* op_placement_info functions. */
507 static void init_op_placement_info_table (void);
508 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
509 static int xg_get_single_size (xtensa_opcode
);
510 static xtensa_format
xg_get_single_format (xtensa_opcode
);
511 static int xg_get_single_slot (xtensa_opcode
);
513 /* TInsn and IStack functions. */
515 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
516 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
517 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
518 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
519 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
520 static void tinsn_from_chars (TInsn
*, char *, int);
521 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
522 static int get_num_stack_text_bytes (IStack
*);
523 static int get_num_stack_literal_bytes (IStack
*);
525 /* vliw_insn functions. */
527 static void xg_init_vinsn (vliw_insn
*);
528 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
529 static void xg_clear_vinsn (vliw_insn
*);
530 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
531 static void xg_free_vinsn (vliw_insn
*);
532 static bfd_boolean vinsn_to_insnbuf
533 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
534 static void vinsn_from_chars (vliw_insn
*, char *);
536 /* Expression Utilities. */
538 bfd_boolean
expr_is_const (const expressionS
*);
539 offsetT
get_expr_const (const expressionS
*);
540 void set_expr_const (expressionS
*, offsetT
);
541 bfd_boolean
expr_is_register (const expressionS
*);
542 offsetT
get_expr_register (const expressionS
*);
543 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
544 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
545 static void copy_expr (expressionS
*, const expressionS
*);
547 /* Section renaming. */
549 static void build_section_rename (const char *);
552 /* ISA imported from bfd. */
553 extern xtensa_isa xtensa_default_isa
;
555 extern int target_big_endian
;
557 static xtensa_opcode xtensa_addi_opcode
;
558 static xtensa_opcode xtensa_addmi_opcode
;
559 static xtensa_opcode xtensa_call0_opcode
;
560 static xtensa_opcode xtensa_call4_opcode
;
561 static xtensa_opcode xtensa_call8_opcode
;
562 static xtensa_opcode xtensa_call12_opcode
;
563 static xtensa_opcode xtensa_callx0_opcode
;
564 static xtensa_opcode xtensa_callx4_opcode
;
565 static xtensa_opcode xtensa_callx8_opcode
;
566 static xtensa_opcode xtensa_callx12_opcode
;
567 static xtensa_opcode xtensa_const16_opcode
;
568 static xtensa_opcode xtensa_entry_opcode
;
569 static xtensa_opcode xtensa_extui_opcode
;
570 static xtensa_opcode xtensa_movi_opcode
;
571 static xtensa_opcode xtensa_movi_n_opcode
;
572 static xtensa_opcode xtensa_isync_opcode
;
573 static xtensa_opcode xtensa_j_opcode
;
574 static xtensa_opcode xtensa_jx_opcode
;
575 static xtensa_opcode xtensa_l32r_opcode
;
576 static xtensa_opcode xtensa_loop_opcode
;
577 static xtensa_opcode xtensa_loopnez_opcode
;
578 static xtensa_opcode xtensa_loopgtz_opcode
;
579 static xtensa_opcode xtensa_nop_opcode
;
580 static xtensa_opcode xtensa_nop_n_opcode
;
581 static xtensa_opcode xtensa_or_opcode
;
582 static xtensa_opcode xtensa_ret_opcode
;
583 static xtensa_opcode xtensa_ret_n_opcode
;
584 static xtensa_opcode xtensa_retw_opcode
;
585 static xtensa_opcode xtensa_retw_n_opcode
;
586 static xtensa_opcode xtensa_rsr_lcount_opcode
;
587 static xtensa_opcode xtensa_waiti_opcode
;
588 static int config_max_slots
= 0;
591 /* Command-line Options. */
593 bfd_boolean use_literal_section
= TRUE
;
594 enum flix_level produce_flix
= FLIX_ALL
;
595 static bfd_boolean align_targets
= TRUE
;
596 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
597 static bfd_boolean has_a0_b_retw
= FALSE
;
598 static bfd_boolean workaround_a0_b_retw
= FALSE
;
599 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
600 static bfd_boolean workaround_short_loop
= FALSE
;
601 static bfd_boolean maybe_has_short_loop
= FALSE
;
602 static bfd_boolean workaround_close_loop_end
= FALSE
;
603 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
604 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
606 /* When workaround_short_loops is TRUE, all loops with early exits must
607 have at least 3 instructions. workaround_all_short_loops is a modifier
608 to the workaround_short_loop flag. In addition to the
609 workaround_short_loop actions, all straightline loopgtz and loopnez
610 must have at least 3 instructions. */
612 static bfd_boolean workaround_all_short_loops
= FALSE
;
616 xtensa_setup_hw_workarounds (int earliest
, int latest
)
618 if (earliest
> latest
)
619 as_fatal (_("illegal range of target hardware versions"));
621 /* Enable all workarounds for pre-T1050.0 hardware. */
622 if (earliest
< 105000 || latest
< 105000)
624 workaround_a0_b_retw
|= TRUE
;
625 workaround_b_j_loop_end
|= TRUE
;
626 workaround_short_loop
|= TRUE
;
627 workaround_close_loop_end
|= TRUE
;
628 workaround_all_short_loops
|= TRUE
;
629 enforce_three_byte_loop_align
= TRUE
;
636 option_density
= OPTION_MD_BASE
,
640 option_no_generate_flix
,
647 option_no_link_relax
,
655 option_text_section_literals
,
656 option_no_text_section_literals
,
658 option_absolute_literals
,
659 option_no_absolute_literals
,
661 option_align_targets
,
662 option_no_align_targets
,
664 option_warn_unaligned_targets
,
669 option_workaround_a0_b_retw
,
670 option_no_workaround_a0_b_retw
,
672 option_workaround_b_j_loop_end
,
673 option_no_workaround_b_j_loop_end
,
675 option_workaround_short_loop
,
676 option_no_workaround_short_loop
,
678 option_workaround_all_short_loops
,
679 option_no_workaround_all_short_loops
,
681 option_workaround_close_loop_end
,
682 option_no_workaround_close_loop_end
,
684 option_no_workarounds
,
686 option_rename_section_name
,
689 option_prefer_const16
,
691 option_target_hardware
694 const char *md_shortopts
= "";
696 struct option md_longopts
[] =
698 { "density", no_argument
, NULL
, option_density
},
699 { "no-density", no_argument
, NULL
, option_no_density
},
701 { "flix", no_argument
, NULL
, option_flix
},
702 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
703 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
705 /* Both "relax" and "generics" are deprecated and treated as equivalent
706 to the "transform" option. */
707 { "relax", no_argument
, NULL
, option_relax
},
708 { "no-relax", no_argument
, NULL
, option_no_relax
},
709 { "generics", no_argument
, NULL
, option_generics
},
710 { "no-generics", no_argument
, NULL
, option_no_generics
},
712 { "transform", no_argument
, NULL
, option_transform
},
713 { "no-transform", no_argument
, NULL
, option_no_transform
},
714 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
715 { "no-text-section-literals", no_argument
, NULL
,
716 option_no_text_section_literals
},
717 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
718 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
719 /* This option was changed from -align-target to -target-align
720 because it conflicted with the "-al" option. */
721 { "target-align", no_argument
, NULL
, option_align_targets
},
722 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
723 { "warn-unaligned-targets", no_argument
, NULL
,
724 option_warn_unaligned_targets
},
725 { "longcalls", no_argument
, NULL
, option_longcalls
},
726 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
728 { "no-workaround-a0-b-retw", no_argument
, NULL
,
729 option_no_workaround_a0_b_retw
},
730 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
732 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
733 option_no_workaround_b_j_loop_end
},
734 { "workaround-b-j-loop-end", no_argument
, NULL
,
735 option_workaround_b_j_loop_end
},
737 { "no-workaround-short-loops", no_argument
, NULL
,
738 option_no_workaround_short_loop
},
739 { "workaround-short-loops", no_argument
, NULL
,
740 option_workaround_short_loop
},
742 { "no-workaround-all-short-loops", no_argument
, NULL
,
743 option_no_workaround_all_short_loops
},
744 { "workaround-all-short-loop", no_argument
, NULL
,
745 option_workaround_all_short_loops
},
747 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
748 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
750 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
752 { "no-workaround-close-loop-end", no_argument
, NULL
,
753 option_no_workaround_close_loop_end
},
754 { "workaround-close-loop-end", no_argument
, NULL
,
755 option_workaround_close_loop_end
},
757 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
759 { "link-relax", no_argument
, NULL
, option_link_relax
},
760 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
762 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
764 { NULL
, no_argument
, NULL
, 0 }
767 size_t md_longopts_size
= sizeof md_longopts
;
771 md_parse_option (int c
, char *arg
)
776 as_warn (_("--density option is ignored"));
778 case option_no_density
:
779 as_warn (_("--no-density option is ignored"));
781 case option_link_relax
:
784 case option_no_link_relax
:
788 produce_flix
= FLIX_ALL
;
790 case option_no_generate_flix
:
791 produce_flix
= FLIX_NO_GENERATE
;
794 produce_flix
= FLIX_NONE
;
796 case option_generics
:
797 as_warn (_("--generics is deprecated; use --transform instead"));
798 return md_parse_option (option_transform
, arg
);
799 case option_no_generics
:
800 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
801 return md_parse_option (option_no_transform
, arg
);
803 as_warn (_("--relax is deprecated; use --transform instead"));
804 return md_parse_option (option_transform
, arg
);
805 case option_no_relax
:
806 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
807 return md_parse_option (option_no_transform
, arg
);
808 case option_longcalls
:
809 directive_state
[directive_longcalls
] = TRUE
;
811 case option_no_longcalls
:
812 directive_state
[directive_longcalls
] = FALSE
;
814 case option_text_section_literals
:
815 use_literal_section
= FALSE
;
817 case option_no_text_section_literals
:
818 use_literal_section
= TRUE
;
820 case option_absolute_literals
:
821 if (!absolute_literals_supported
)
823 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
826 directive_state
[directive_absolute_literals
] = TRUE
;
828 case option_no_absolute_literals
:
829 directive_state
[directive_absolute_literals
] = FALSE
;
832 case option_workaround_a0_b_retw
:
833 workaround_a0_b_retw
= TRUE
;
835 case option_no_workaround_a0_b_retw
:
836 workaround_a0_b_retw
= FALSE
;
838 case option_workaround_b_j_loop_end
:
839 workaround_b_j_loop_end
= TRUE
;
841 case option_no_workaround_b_j_loop_end
:
842 workaround_b_j_loop_end
= FALSE
;
845 case option_workaround_short_loop
:
846 workaround_short_loop
= TRUE
;
848 case option_no_workaround_short_loop
:
849 workaround_short_loop
= FALSE
;
852 case option_workaround_all_short_loops
:
853 workaround_all_short_loops
= TRUE
;
855 case option_no_workaround_all_short_loops
:
856 workaround_all_short_loops
= FALSE
;
859 case option_workaround_close_loop_end
:
860 workaround_close_loop_end
= TRUE
;
862 case option_no_workaround_close_loop_end
:
863 workaround_close_loop_end
= FALSE
;
866 case option_no_workarounds
:
867 workaround_a0_b_retw
= FALSE
;
868 workaround_b_j_loop_end
= FALSE
;
869 workaround_short_loop
= FALSE
;
870 workaround_all_short_loops
= FALSE
;
871 workaround_close_loop_end
= FALSE
;
874 case option_align_targets
:
875 align_targets
= TRUE
;
877 case option_no_align_targets
:
878 align_targets
= FALSE
;
881 case option_warn_unaligned_targets
:
882 warn_unaligned_branch_targets
= TRUE
;
885 case option_rename_section_name
:
886 build_section_rename (arg
);
890 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
891 should be emitted or not. FIXME: Not implemented. */
894 case option_prefer_l32r
:
896 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
900 case option_prefer_const16
:
902 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
906 case option_target_hardware
:
908 int earliest
, latest
= 0;
909 if (*arg
== 0 || *arg
== '-')
910 as_fatal (_("invalid target hardware version"));
912 earliest
= strtol (arg
, &arg
, 0);
916 else if (*arg
== '-')
919 as_fatal (_("invalid target hardware version"));
920 latest
= strtol (arg
, &arg
, 0);
923 as_fatal (_("invalid target hardware version"));
925 xtensa_setup_hw_workarounds (earliest
, latest
);
929 case option_transform
:
930 /* This option has no affect other than to use the defaults,
931 which are already set. */
934 case option_no_transform
:
935 /* This option turns off all transformations of any kind.
936 However, because we want to preserve the state of other
937 directives, we only change its own field. Thus, before
938 you perform any transformation, always check if transform
939 is available. If you use the functions we provide for this
940 purpose, you will be ok. */
941 directive_state
[directive_transform
] = FALSE
;
951 md_show_usage (FILE *stream
)
955 --[no-]text-section-literals\n\
956 [Do not] put literals in the text section\n\
957 --[no-]absolute-literals\n\
958 [Do not] default to use non-PC-relative literals\n\
959 --[no-]target-align [Do not] try to align branch targets\n\
960 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
961 --[no-]transform [Do not] transform instructions\n\
962 --flix both allow hand-written and generate flix bundles\n\
963 --no-generate-flix allow hand-written but do not generate\n\
965 --no-allow-flix neither allow hand-written nor generate\n\
967 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
971 /* Functions related to the list of current label symbols. */
974 xtensa_add_insn_label (symbolS
*sym
)
978 if (!free_insn_labels
)
979 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
982 l
= free_insn_labels
;
983 free_insn_labels
= l
->next
;
987 l
->next
= insn_labels
;
993 xtensa_clear_insn_labels (void)
997 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1005 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1009 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1011 symbolS
*lit_sym
= lit
->sym
;
1012 S_SET_VALUE (lit_sym
, new_offset
);
1013 symbol_set_frag (lit_sym
, new_frag
);
1018 /* Directive data and functions. */
1020 typedef struct state_stackS_struct
1022 directiveE directive
;
1023 bfd_boolean negated
;
1024 bfd_boolean old_state
;
1028 struct state_stackS_struct
*prev
;
1031 state_stackS
*directive_state_stack
;
1033 const pseudo_typeS md_pseudo_table
[] =
1035 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1036 { "literal_position", xtensa_literal_position
, 0 },
1037 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1038 { "long", xtensa_elf_cons
, 4 },
1039 { "word", xtensa_elf_cons
, 4 },
1040 { "4byte", xtensa_elf_cons
, 4 },
1041 { "short", xtensa_elf_cons
, 2 },
1042 { "2byte", xtensa_elf_cons
, 2 },
1043 { "sleb128", xtensa_leb128
, 1},
1044 { "uleb128", xtensa_leb128
, 0},
1045 { "begin", xtensa_begin_directive
, 0 },
1046 { "end", xtensa_end_directive
, 0 },
1047 { "literal", xtensa_literal_pseudo
, 0 },
1048 { "frequency", xtensa_frequency_pseudo
, 0 },
1054 use_transform (void)
1056 /* After md_end, you should be checking frag by frag, rather
1057 than state directives. */
1058 gas_assert (!past_xtensa_end
);
1059 return directive_state
[directive_transform
];
1064 do_align_targets (void)
1066 /* Do not use this function after md_end; just look at align_targets
1067 instead. There is no target-align directive, so alignment is either
1068 enabled for all frags or not done at all. */
1069 gas_assert (!past_xtensa_end
);
1070 return align_targets
&& use_transform ();
1075 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1079 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1081 as_where (&file
, &line
);
1083 stack
->directive
= directive
;
1084 stack
->negated
= negated
;
1085 stack
->old_state
= directive_state
[directive
];
1088 stack
->datum
= datum
;
1089 stack
->prev
= directive_state_stack
;
1090 directive_state_stack
= stack
;
1092 directive_state
[directive
] = !negated
;
1097 directive_pop (directiveE
*directive
,
1098 bfd_boolean
*negated
,
1103 state_stackS
*top
= directive_state_stack
;
1105 if (!directive_state_stack
)
1107 as_bad (_("unmatched end directive"));
1108 *directive
= directive_none
;
1112 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1113 *directive
= top
->directive
;
1114 *negated
= top
->negated
;
1117 *datum
= top
->datum
;
1118 directive_state_stack
= top
->prev
;
1124 directive_balance (void)
1126 while (directive_state_stack
)
1128 directiveE directive
;
1129 bfd_boolean negated
;
1134 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1135 as_warn_where ((char *) file
, line
,
1136 _(".begin directive with no matching .end directive"));
1142 inside_directive (directiveE dir
)
1144 state_stackS
*top
= directive_state_stack
;
1146 while (top
&& top
->directive
!= dir
)
1149 return (top
!= NULL
);
1154 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1158 char *directive_string
;
1160 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1165 input_line_pointer
+= 3;
1168 len
= strspn (input_line_pointer
,
1169 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1171 /* This code is a hack to make .begin [no-][generics|relax] exactly
1172 equivalent to .begin [no-]transform. We should remove it when
1173 we stop accepting those options. */
1175 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1177 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1178 directive_string
= "transform";
1180 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1182 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1183 directive_string
= "transform";
1186 directive_string
= input_line_pointer
;
1188 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1190 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1192 input_line_pointer
+= len
;
1193 *directive
= (directiveE
) i
;
1194 if (*negated
&& !directive_info
[i
].can_be_negated
)
1195 as_bad (_("directive %s cannot be negated"),
1196 directive_info
[i
].name
);
1201 as_bad (_("unknown directive"));
1202 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1207 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1209 directiveE directive
;
1210 bfd_boolean negated
;
1214 get_directive (&directive
, &negated
);
1215 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1217 discard_rest_of_line ();
1221 if (cur_vinsn
.inside_bundle
)
1222 as_bad (_("directives are not valid inside bundles"));
1226 case directive_literal
:
1227 if (!inside_directive (directive_literal
))
1229 /* Previous labels go with whatever follows this directive, not with
1230 the literal, so save them now. */
1231 saved_insn_labels
= insn_labels
;
1234 as_warn (_(".begin literal is deprecated; use .literal instead"));
1235 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1236 xtensa_switch_to_literal_fragment (state
);
1237 directive_push (directive_literal
, negated
, state
);
1240 case directive_literal_prefix
:
1241 /* Have to flush pending output because a movi relaxed to an l32r
1242 might produce a literal. */
1243 md_flush_pending_output ();
1244 /* Check to see if the current fragment is a literal
1245 fragment. If it is, then this operation is not allowed. */
1246 if (generating_literals
)
1248 as_bad (_("cannot set literal_prefix inside literal fragment"));
1252 /* Allocate the literal state for this section and push
1253 onto the directive stack. */
1254 ls
= xmalloc (sizeof (lit_state
));
1257 *ls
= default_lit_sections
;
1258 directive_push (directive_literal_prefix
, negated
, ls
);
1260 /* Process the new prefix. */
1261 xtensa_literal_prefix ();
1264 case directive_freeregs
:
1265 /* This information is currently unused, but we'll accept the statement
1266 and just discard the rest of the line. This won't check the syntax,
1267 but it will accept every correct freeregs directive. */
1268 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1269 directive_push (directive_freeregs
, negated
, 0);
1272 case directive_schedule
:
1273 md_flush_pending_output ();
1274 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1275 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1276 directive_push (directive_schedule
, negated
, 0);
1277 xtensa_set_frag_assembly_state (frag_now
);
1280 case directive_density
:
1281 as_warn (_(".begin [no-]density is ignored"));
1284 case directive_absolute_literals
:
1285 md_flush_pending_output ();
1286 if (!absolute_literals_supported
&& !negated
)
1288 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1291 xtensa_set_frag_assembly_state (frag_now
);
1292 directive_push (directive
, negated
, 0);
1296 md_flush_pending_output ();
1297 xtensa_set_frag_assembly_state (frag_now
);
1298 directive_push (directive
, negated
, 0);
1302 demand_empty_rest_of_line ();
1307 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1309 directiveE begin_directive
, end_directive
;
1310 bfd_boolean begin_negated
, end_negated
;
1314 emit_state
**state_ptr
;
1317 if (cur_vinsn
.inside_bundle
)
1318 as_bad (_("directives are not valid inside bundles"));
1320 get_directive (&end_directive
, &end_negated
);
1322 md_flush_pending_output ();
1324 switch (end_directive
)
1326 case (directiveE
) XTENSA_UNDEFINED
:
1327 discard_rest_of_line ();
1330 case directive_density
:
1331 as_warn (_(".end [no-]density is ignored"));
1332 demand_empty_rest_of_line ();
1335 case directive_absolute_literals
:
1336 if (!absolute_literals_supported
&& !end_negated
)
1338 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1339 demand_empty_rest_of_line ();
1348 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1349 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1350 (const void **) state_ptr
);
1352 if (begin_directive
!= directive_none
)
1354 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1356 as_bad (_("does not match begin %s%s at %s:%d"),
1357 begin_negated
? "no-" : "",
1358 directive_info
[begin_directive
].name
, file
, line
);
1362 switch (end_directive
)
1364 case directive_literal
:
1365 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1366 xtensa_restore_emit_state (state
);
1367 xtensa_set_frag_assembly_state (frag_now
);
1369 if (!inside_directive (directive_literal
))
1371 /* Restore the list of current labels. */
1372 xtensa_clear_insn_labels ();
1373 insn_labels
= saved_insn_labels
;
1377 case directive_literal_prefix
:
1378 /* Restore the default collection sections from saved state. */
1379 s
= (lit_state
*) state
;
1381 default_lit_sections
= *s
;
1383 /* Free the state storage. */
1384 free (s
->lit_prefix
);
1388 case directive_schedule
:
1389 case directive_freeregs
:
1393 xtensa_set_frag_assembly_state (frag_now
);
1399 demand_empty_rest_of_line ();
1403 /* Place an aligned literal fragment at the current location. */
1406 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1408 md_flush_pending_output ();
1410 if (inside_directive (directive_literal
))
1411 as_warn (_(".literal_position inside literal directive; ignoring"));
1412 xtensa_mark_literal_pool_location ();
1414 demand_empty_rest_of_line ();
1415 xtensa_clear_insn_labels ();
1419 /* Support .literal label, expr, ... */
1422 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1425 char *p
, *base_name
;
1429 if (inside_directive (directive_literal
))
1431 as_bad (_(".literal not allowed inside .begin literal region"));
1432 ignore_rest_of_line ();
1436 md_flush_pending_output ();
1438 /* Previous labels go with whatever follows this directive, not with
1439 the literal, so save them now. */
1440 saved_insn_labels
= insn_labels
;
1443 /* If we are using text-section literals, then this is the right value... */
1446 base_name
= input_line_pointer
;
1448 xtensa_switch_to_literal_fragment (&state
);
1450 /* ...but if we aren't using text-section-literals, then we
1451 need to put them in the section we just switched to. */
1452 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1455 /* All literals are aligned to four-byte boundaries. */
1456 frag_align (2, 0, 0);
1457 record_alignment (now_seg
, 2);
1459 c
= get_symbol_end ();
1460 /* Just after name is now '\0'. */
1461 p
= input_line_pointer
;
1465 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1467 as_bad (_("expected comma or colon after symbol name; "
1468 "rest of line ignored"));
1469 ignore_rest_of_line ();
1470 xtensa_restore_emit_state (&state
);
1478 input_line_pointer
++; /* skip ',' or ':' */
1480 xtensa_elf_cons (4);
1482 xtensa_restore_emit_state (&state
);
1484 /* Restore the list of current labels. */
1485 xtensa_clear_insn_labels ();
1486 insn_labels
= saved_insn_labels
;
1491 xtensa_literal_prefix (void)
1496 /* Parse the new prefix from the input_line_pointer. */
1498 len
= strspn (input_line_pointer
,
1499 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1500 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1502 /* Get a null-terminated copy of the name. */
1503 name
= xmalloc (len
+ 1);
1505 strncpy (name
, input_line_pointer
, len
);
1508 /* Skip the name in the input line. */
1509 input_line_pointer
+= len
;
1511 default_lit_sections
.lit_prefix
= name
;
1513 /* Clear cached literal sections, since the prefix has changed. */
1514 default_lit_sections
.lit_seg
= NULL
;
1515 default_lit_sections
.lit4_seg
= NULL
;
1519 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1522 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1524 float fall_through_f
, target_f
;
1526 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1527 if (fall_through_f
< 0)
1529 as_bad (_("fall through frequency must be greater than 0"));
1530 ignore_rest_of_line ();
1534 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1537 as_bad (_("branch target frequency must be greater than 0"));
1538 ignore_rest_of_line ();
1542 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1544 demand_empty_rest_of_line ();
1548 /* Like normal .long/.short/.word, except support @plt, etc.
1549 Clobbers input_line_pointer, checks end-of-line. */
1552 xtensa_elf_cons (int nbytes
)
1555 bfd_reloc_code_real_type reloc
;
1557 md_flush_pending_output ();
1559 if (cur_vinsn
.inside_bundle
)
1560 as_bad (_("directives are not valid inside bundles"));
1562 if (is_it_end_of_statement ())
1564 demand_empty_rest_of_line ();
1571 if (exp
.X_op
== O_symbol
1572 && *input_line_pointer
== '@'
1573 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1576 reloc_howto_type
*reloc_howto
=
1577 bfd_reloc_type_lookup (stdoutput
, reloc
);
1579 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1580 as_bad (_("unsupported relocation"));
1581 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1582 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1583 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1584 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1585 as_bad (_("opcode-specific %s relocation used outside "
1586 "an instruction"), reloc_howto
->name
);
1587 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1588 as_bad (_("%s relocations do not fit in %d bytes"),
1589 reloc_howto
->name
, nbytes
);
1590 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1591 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1592 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1593 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1596 char *p
= frag_more ((int) nbytes
);
1597 xtensa_set_frag_assembly_state (frag_now
);
1598 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1599 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1604 xtensa_set_frag_assembly_state (frag_now
);
1605 emit_expr (&exp
, (unsigned int) nbytes
);
1608 while (*input_line_pointer
++ == ',');
1610 input_line_pointer
--; /* Put terminator back into stream. */
1611 demand_empty_rest_of_line ();
1614 static bfd_boolean is_leb128_expr
;
1617 xtensa_leb128 (int sign
)
1619 is_leb128_expr
= TRUE
;
1621 is_leb128_expr
= FALSE
;
1625 /* Parsing and Idiom Translation. */
1627 /* Parse @plt, etc. and return the desired relocation. */
1628 static bfd_reloc_code_real_type
1629 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1636 struct suffix_reloc_map
*ptr
;
1639 return BFD_RELOC_NONE
;
1641 for (ch
= *str
, str2
= ident
;
1642 (str2
< ident
+ sizeof (ident
) - 1
1643 && (ISALNUM (ch
) || ch
== '@'));
1646 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1653 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1654 if (ch
== ptr
->suffix
[0]
1655 && len
== ptr
->length
1656 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1658 /* Now check for "identifier@suffix+constant". */
1659 if (*str
== '-' || *str
== '+')
1661 char *orig_line
= input_line_pointer
;
1662 expressionS new_exp
;
1664 input_line_pointer
= str
;
1665 expression (&new_exp
);
1666 if (new_exp
.X_op
== O_constant
)
1668 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1669 str
= input_line_pointer
;
1672 if (&input_line_pointer
!= str_p
)
1673 input_line_pointer
= orig_line
;
1680 return BFD_RELOC_UNUSED
;
1684 /* Find the matching operator type. */
1685 static unsigned char
1686 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1688 struct suffix_reloc_map
*sfx
;
1689 unsigned char operator = (unsigned char) -1;
1691 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1693 if (sfx
->reloc
== reloc
)
1695 operator = sfx
->operator;
1699 gas_assert (operator != (unsigned char) -1);
1704 /* Find the matching reloc type. */
1705 static bfd_reloc_code_real_type
1706 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1708 struct suffix_reloc_map
*sfx
;
1709 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1711 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1713 if (sfx
->operator == operator)
1722 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1723 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1724 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1725 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1728 if (reloc
== BFD_RELOC_UNUSED
)
1729 return BFD_RELOC_32
;
1736 expression_end (const char *name
)
1759 #define ERROR_REG_NUM ((unsigned) -1)
1762 tc_get_register (const char *prefix
)
1765 const char *next_expr
;
1766 const char *old_line_pointer
;
1769 old_line_pointer
= input_line_pointer
;
1771 if (*input_line_pointer
== '$')
1772 ++input_line_pointer
;
1774 /* Accept "sp" as a synonym for "a1". */
1775 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1776 && expression_end (input_line_pointer
+ 2))
1778 input_line_pointer
+= 2;
1779 return 1; /* AR[1] */
1782 while (*input_line_pointer
++ == *prefix
++)
1784 --input_line_pointer
;
1789 as_bad (_("bad register name: %s"), old_line_pointer
);
1790 return ERROR_REG_NUM
;
1793 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1795 as_bad (_("bad register number: %s"), input_line_pointer
);
1796 return ERROR_REG_NUM
;
1801 while (ISDIGIT ((int) *input_line_pointer
))
1802 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1804 if (!(next_expr
= expression_end (input_line_pointer
)))
1806 as_bad (_("bad register name: %s"), old_line_pointer
);
1807 return ERROR_REG_NUM
;
1810 input_line_pointer
= (char *) next_expr
;
1817 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1819 xtensa_isa isa
= xtensa_default_isa
;
1821 /* Check if this is an immediate operand. */
1822 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1824 bfd_reloc_code_real_type reloc
;
1825 segT t
= expression (tok
);
1827 if (t
== absolute_section
1828 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1830 gas_assert (tok
->X_op
== O_constant
);
1831 tok
->X_op
= O_symbol
;
1832 tok
->X_add_symbol
= &abs_symbol
;
1835 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1836 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1841 case BFD_RELOC_LO16
:
1842 if (tok
->X_op
== O_constant
)
1844 tok
->X_add_number
&= 0xffff;
1848 case BFD_RELOC_HI16
:
1849 if (tok
->X_op
== O_constant
)
1851 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1855 case BFD_RELOC_UNUSED
:
1856 as_bad (_("unsupported relocation"));
1858 case BFD_RELOC_32_PCREL
:
1859 as_bad (_("pcrel relocation not allowed in an instruction"));
1864 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1869 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1870 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1872 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1875 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1876 as_bad (_("register number out of range"));
1879 tok
->X_op
= O_register
;
1880 tok
->X_add_symbol
= 0;
1881 tok
->X_add_number
= reg
;
1886 /* Split up the arguments for an opcode or pseudo-op. */
1889 tokenize_arguments (char **args
, char *str
)
1891 char *old_input_line_pointer
;
1892 bfd_boolean saw_comma
= FALSE
;
1893 bfd_boolean saw_arg
= FALSE
;
1894 bfd_boolean saw_colon
= FALSE
;
1896 char *arg_end
, *arg
;
1899 /* Save and restore input_line_pointer around this function. */
1900 old_input_line_pointer
= input_line_pointer
;
1901 input_line_pointer
= str
;
1903 while (*input_line_pointer
)
1906 switch (*input_line_pointer
)
1913 input_line_pointer
++;
1914 if (saw_comma
|| saw_colon
|| !saw_arg
)
1920 input_line_pointer
++;
1921 if (saw_comma
|| saw_colon
|| !saw_arg
)
1927 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1930 arg_end
= input_line_pointer
+ 1;
1931 while (!expression_end (arg_end
))
1934 arg_len
= arg_end
- input_line_pointer
;
1935 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1936 args
[num_args
] = arg
;
1940 strncpy (arg
, input_line_pointer
, arg_len
);
1941 arg
[arg_len
] = '\0';
1943 input_line_pointer
= arg_end
;
1953 if (saw_comma
|| saw_colon
)
1955 input_line_pointer
= old_input_line_pointer
;
1960 as_bad (_("extra comma"));
1962 as_bad (_("extra colon"));
1964 as_bad (_("missing argument"));
1966 as_bad (_("missing comma or colon"));
1967 input_line_pointer
= old_input_line_pointer
;
1972 /* Parse the arguments to an opcode. Return TRUE on error. */
1975 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1977 expressionS
*tok
, *last_tok
;
1978 xtensa_opcode opcode
= insn
->opcode
;
1979 bfd_boolean had_error
= TRUE
;
1980 xtensa_isa isa
= xtensa_default_isa
;
1981 int n
, num_regs
= 0;
1982 int opcode_operand_count
;
1983 int opnd_cnt
, last_opnd_cnt
;
1984 unsigned int next_reg
= 0;
1985 char *old_input_line_pointer
;
1987 if (insn
->insn_type
== ITYPE_LITERAL
)
1988 opcode_operand_count
= 1;
1990 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1993 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1995 /* Save and restore input_line_pointer around this function. */
1996 old_input_line_pointer
= input_line_pointer
;
2002 /* Skip invisible operands. */
2003 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2009 for (n
= 0; n
< num_args
; n
++)
2011 input_line_pointer
= arg_strings
[n
];
2012 if (*input_line_pointer
== ':')
2014 xtensa_regfile opnd_rf
;
2015 input_line_pointer
++;
2018 gas_assert (opnd_cnt
> 0);
2020 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2022 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2023 as_warn (_("incorrect register number, ignoring"));
2028 if (opnd_cnt
>= opcode_operand_count
)
2030 as_warn (_("too many arguments"));
2033 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2035 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2036 next_reg
= tok
->X_add_number
+ 1;
2038 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2040 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2042 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2043 /* minus 1 because we are seeing one right now */
2049 last_opnd_cnt
= opnd_cnt
;
2050 demand_empty_rest_of_line ();
2057 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2061 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2064 insn
->ntok
= tok
- insn
->tok
;
2068 input_line_pointer
= old_input_line_pointer
;
2074 get_invisible_operands (TInsn
*insn
)
2076 xtensa_isa isa
= xtensa_default_isa
;
2077 static xtensa_insnbuf slotbuf
= NULL
;
2079 xtensa_opcode opc
= insn
->opcode
;
2080 int slot
, opnd
, fmt_found
;
2084 slotbuf
= xtensa_insnbuf_alloc (isa
);
2086 /* Find format/slot where this can be encoded. */
2089 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2091 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2093 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2099 if (fmt_found
) break;
2104 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2108 /* First encode all the visible operands
2109 (to deal with shared field operands). */
2110 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2112 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2113 && (insn
->tok
[opnd
].X_op
== O_register
2114 || insn
->tok
[opnd
].X_op
== O_constant
))
2116 val
= insn
->tok
[opnd
].X_add_number
;
2117 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2118 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2122 /* Then pull out the values for the invisible ones. */
2123 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2125 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2127 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2128 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2129 insn
->tok
[opnd
].X_add_number
= val
;
2130 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2131 insn
->tok
[opnd
].X_op
= O_register
;
2133 insn
->tok
[opnd
].X_op
= O_constant
;
2142 xg_reverse_shift_count (char **cnt_argp
)
2144 char *cnt_arg
, *new_arg
;
2145 cnt_arg
= *cnt_argp
;
2147 /* replace the argument with "31-(argument)" */
2148 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2149 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2152 *cnt_argp
= new_arg
;
2156 /* If "arg" is a constant expression, return non-zero with the value
2160 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2163 char *save_ptr
= input_line_pointer
;
2165 input_line_pointer
= arg
;
2167 input_line_pointer
= save_ptr
;
2169 if (exp
.X_op
== O_constant
)
2171 *valp
= exp
.X_add_number
;
2180 xg_replace_opname (char **popname
, char *newop
)
2183 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2184 strcpy (*popname
, newop
);
2189 xg_check_num_args (int *pnum_args
,
2194 int num_args
= *pnum_args
;
2196 if (num_args
< expected_num
)
2198 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2199 num_args
, opname
, expected_num
);
2203 if (num_args
> expected_num
)
2205 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2206 num_args
, opname
, expected_num
);
2207 while (num_args
-- > expected_num
)
2209 free (arg_strings
[num_args
]);
2210 arg_strings
[num_args
] = 0;
2212 *pnum_args
= expected_num
;
2220 /* If the register is not specified as part of the opcode,
2221 then get it from the operand and move it to the opcode. */
2224 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 int is_user
, is_write
;
2235 is_user
= (opname
[1] == 'u');
2236 is_write
= (opname
[0] == 'w');
2238 /* Opname == [rw]ur or [rwx]sr... */
2240 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2243 /* Check if the argument is a symbolic register name. */
2244 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2245 /* Handle WSR to "INTSET" as a special case. */
2246 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2247 && !strcasecmp (arg_strings
[1], "intset"))
2248 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2249 if (sr
== XTENSA_UNDEFINED
2250 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2252 /* Maybe it's a register number.... */
2254 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2256 as_bad (_("invalid register '%s' for '%s' instruction"),
2257 arg_strings
[1], opname
);
2260 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2261 if (sr
== XTENSA_UNDEFINED
)
2263 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2264 (long) val
, opname
);
2269 /* Remove the last argument, which is now part of the opcode. */
2270 free (arg_strings
[1]);
2274 /* Translate the opcode. */
2275 sr_name
= xtensa_sysreg_name (isa
, sr
);
2276 /* Another special case for "WSR.INTSET".... */
2277 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2279 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2280 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2282 *popname
= new_opname
;
2289 xtensa_translate_old_userreg_ops (char **popname
)
2291 xtensa_isa isa
= xtensa_default_isa
;
2293 char *opname
, *new_opname
;
2294 const char *sr_name
;
2295 bfd_boolean has_underbar
= FALSE
;
2298 if (opname
[0] == '_')
2300 has_underbar
= TRUE
;
2304 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2305 if (sr
!= XTENSA_UNDEFINED
)
2307 /* The new default name ("nnn") is different from the old default
2308 name ("URnnn"). The old default is handled below, and we don't
2309 want to recognize [RW]nnn, so do nothing if the name is the (new)
2311 static char namebuf
[10];
2312 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2313 if (strcmp (namebuf
, opname
+ 1) == 0)
2321 /* Only continue if the reg name is "URnnn". */
2322 if (opname
[1] != 'u' || opname
[2] != 'r')
2324 val
= strtoul (opname
+ 3, &end
, 10);
2328 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2329 if (sr
== XTENSA_UNDEFINED
)
2331 as_bad (_("invalid register number (%ld) for '%s'"),
2332 (long) val
, opname
);
2337 /* Translate the opcode. */
2338 sr_name
= xtensa_sysreg_name (isa
, sr
);
2339 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2340 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2341 opname
[0], sr_name
);
2343 *popname
= new_opname
;
2350 xtensa_translate_zero_immed (char *old_op
,
2360 gas_assert (opname
[0] != '_');
2362 if (strcmp (opname
, old_op
) != 0)
2365 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2367 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2369 xg_replace_opname (popname
, new_op
);
2370 free (arg_strings
[1]);
2371 arg_strings
[1] = arg_strings
[2];
2380 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2381 Returns non-zero if an error was found. */
2384 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2386 char *opname
= *popname
;
2387 bfd_boolean has_underbar
= FALSE
;
2391 has_underbar
= TRUE
;
2395 if (strcmp (opname
, "mov") == 0)
2397 if (use_transform () && !has_underbar
&& density_supported
)
2398 xg_replace_opname (popname
, "mov.n");
2401 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2403 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2404 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2405 strcpy (arg_strings
[2], arg_strings
[1]);
2411 if (strcmp (opname
, "bbsi.l") == 0)
2413 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2415 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2416 if (target_big_endian
)
2417 xg_reverse_shift_count (&arg_strings
[1]);
2421 if (strcmp (opname
, "bbci.l") == 0)
2423 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2425 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2426 if (target_big_endian
)
2427 xg_reverse_shift_count (&arg_strings
[1]);
2431 /* Don't do anything special with NOPs inside FLIX instructions. They
2432 are handled elsewhere. Real NOP instructions are always available
2433 in configurations with FLIX, so this should never be an issue but
2434 check for it anyway. */
2435 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2436 && strcmp (opname
, "nop") == 0)
2438 if (use_transform () && !has_underbar
&& density_supported
)
2439 xg_replace_opname (popname
, "nop.n");
2442 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2444 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2445 arg_strings
[0] = (char *) xmalloc (3);
2446 arg_strings
[1] = (char *) xmalloc (3);
2447 arg_strings
[2] = (char *) xmalloc (3);
2448 strcpy (arg_strings
[0], "a1");
2449 strcpy (arg_strings
[1], "a1");
2450 strcpy (arg_strings
[2], "a1");
2456 /* Recognize [RW]UR and [RWX]SR. */
2457 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2458 && (opname
[1] == 'u' || opname
[1] == 's'))
2459 || (opname
[0] == 'x' && opname
[1] == 's'))
2461 && opname
[3] == '\0')
2462 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2464 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2465 [RW]<name> if <name> is the non-default name of a user register. */
2466 if ((opname
[0] == 'r' || opname
[0] == 'w')
2467 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2468 return xtensa_translate_old_userreg_ops (popname
);
2470 /* Relax branches that don't allow comparisons against an immediate value
2471 of zero to the corresponding branches with implicit zero immediates. */
2472 if (!has_underbar
&& use_transform ())
2474 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2475 pnum_args
, arg_strings
))
2478 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2479 pnum_args
, arg_strings
))
2482 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2483 pnum_args
, arg_strings
))
2486 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2487 pnum_args
, arg_strings
))
2495 /* Functions for dealing with the Xtensa ISA. */
2497 /* Currently the assembler only allows us to use a single target per
2498 fragment. Because of this, only one operand for a given
2499 instruction may be symbolic. If there is a PC-relative operand,
2500 the last one is chosen. Otherwise, the result is the number of the
2501 last immediate operand, and if there are none of those, we fail and
2505 get_relaxable_immed (xtensa_opcode opcode
)
2507 int last_immed
= -1;
2510 if (opcode
== XTENSA_UNDEFINED
)
2513 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2514 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2516 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2518 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2520 if (last_immed
== -1
2521 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2528 static xtensa_opcode
2529 get_opcode_from_buf (const char *buf
, int slot
)
2531 static xtensa_insnbuf insnbuf
= NULL
;
2532 static xtensa_insnbuf slotbuf
= NULL
;
2533 xtensa_isa isa
= xtensa_default_isa
;
2538 insnbuf
= xtensa_insnbuf_alloc (isa
);
2539 slotbuf
= xtensa_insnbuf_alloc (isa
);
2542 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2543 fmt
= xtensa_format_decode (isa
, insnbuf
);
2544 if (fmt
== XTENSA_UNDEFINED
)
2545 return XTENSA_UNDEFINED
;
2547 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2548 return XTENSA_UNDEFINED
;
2550 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2551 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2555 #ifdef TENSILICA_DEBUG
2557 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2560 xtensa_print_insn_table (void)
2562 int num_opcodes
, num_operands
;
2563 xtensa_opcode opcode
;
2564 xtensa_isa isa
= xtensa_default_isa
;
2566 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2567 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2570 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2571 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2572 for (opn
= 0; opn
< num_operands
; opn
++)
2574 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2576 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2578 xtensa_regfile opnd_rf
=
2579 xtensa_operand_regfile (isa
, opcode
, opn
);
2580 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2582 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2583 fputs ("[lLr] ", stderr
);
2585 fputs ("i ", stderr
);
2587 fprintf (stderr
, "\n");
2593 print_vliw_insn (xtensa_insnbuf vbuf
)
2595 xtensa_isa isa
= xtensa_default_isa
;
2596 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2597 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2600 fprintf (stderr
, "format = %d\n", f
);
2602 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2604 xtensa_opcode opcode
;
2608 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2609 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2610 opname
= xtensa_opcode_name (isa
, opcode
);
2612 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2613 fprintf (stderr
, " operands = ");
2615 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2619 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2621 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2622 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2623 fprintf (stderr
, "%d ", val
);
2625 fprintf (stderr
, "\n");
2627 xtensa_insnbuf_free (isa
, sbuf
);
2630 #endif /* TENSILICA_DEBUG */
2634 is_direct_call_opcode (xtensa_opcode opcode
)
2636 xtensa_isa isa
= xtensa_default_isa
;
2637 int n
, num_operands
;
2639 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2642 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2643 for (n
= 0; n
< num_operands
; n
++)
2645 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2646 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2653 /* Convert from BFD relocation type code to slot and operand number.
2654 Returns non-zero on failure. */
2657 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2659 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2660 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2662 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2665 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2666 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2668 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2678 /* Convert from slot number to BFD relocation type code for the
2679 standard PC-relative relocations. Return BFD_RELOC_NONE on
2682 static bfd_reloc_code_real_type
2683 encode_reloc (int slot
)
2685 if (slot
< 0 || slot
> 14)
2686 return BFD_RELOC_NONE
;
2688 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2692 /* Convert from slot numbers to BFD relocation type code for the
2693 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2695 static bfd_reloc_code_real_type
2696 encode_alt_reloc (int slot
)
2698 if (slot
< 0 || slot
> 14)
2699 return BFD_RELOC_NONE
;
2701 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2706 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2709 xtensa_opcode opcode
,
2715 uint32 valbuf
= value
;
2717 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2719 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2721 as_bad_where ((char *) file
, line
,
2722 _("operand %d of '%s' has out of range value '%u'"),
2724 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2727 as_bad_where ((char *) file
, line
,
2728 _("operand %d of '%s' has invalid value '%u'"),
2730 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2735 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2741 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2744 xtensa_opcode opcode
,
2748 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2749 fmt
, slot
, slotbuf
, &val
);
2750 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2755 /* Checks for rules from xtensa-relax tables. */
2757 /* The routine xg_instruction_matches_option_term must return TRUE
2758 when a given option term is true. The meaning of all of the option
2759 terms is given interpretation by this function. */
2762 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2764 if (strcmp (option
->option_name
, "realnop") == 0
2765 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2767 /* These conditions were evaluated statically when building the
2768 relaxation table. There's no need to reevaluate them now. */
2771 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2772 return insn
->extra_arg
.X_op
== O_register
;
2775 as_fatal (_("internal error: unknown option name '%s'"),
2776 option
->option_name
);
2782 xg_instruction_matches_or_options (TInsn
*insn
,
2783 const ReqOrOptionList
*or_option
)
2785 const ReqOrOption
*option
;
2786 /* Must match each of the AND terms. */
2787 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2789 if (xg_instruction_matches_option_term (insn
, option
))
2797 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2799 const ReqOption
*req_options
;
2800 /* Must match each of the AND terms. */
2801 for (req_options
= options
;
2802 req_options
!= NULL
;
2803 req_options
= req_options
->next
)
2805 /* Must match one of the OR clauses. */
2806 if (!xg_instruction_matches_or_options (insn
,
2807 req_options
->or_option_terms
))
2814 /* Return the transition rule that matches or NULL if none matches. */
2817 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2819 PreconditionList
*condition_l
;
2821 if (rule
->opcode
!= insn
->opcode
)
2824 for (condition_l
= rule
->conditions
;
2825 condition_l
!= NULL
;
2826 condition_l
= condition_l
->next
)
2830 Precondition
*cond
= condition_l
->precond
;
2835 /* The expression must be the constant. */
2836 gas_assert (cond
->op_num
< insn
->ntok
);
2837 exp1
= &insn
->tok
[cond
->op_num
];
2838 if (expr_is_const (exp1
))
2843 if (get_expr_const (exp1
) != cond
->op_data
)
2847 if (get_expr_const (exp1
) == cond
->op_data
)
2854 else if (expr_is_register (exp1
))
2859 if (get_expr_register (exp1
) != cond
->op_data
)
2863 if (get_expr_register (exp1
) == cond
->op_data
)
2875 gas_assert (cond
->op_num
< insn
->ntok
);
2876 gas_assert (cond
->op_data
< insn
->ntok
);
2877 exp1
= &insn
->tok
[cond
->op_num
];
2878 exp2
= &insn
->tok
[cond
->op_data
];
2883 if (!expr_is_equal (exp1
, exp2
))
2887 if (expr_is_equal (exp1
, exp2
))
2899 if (!xg_instruction_matches_options (insn
, rule
->options
))
2907 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2909 bfd_boolean a_greater
= FALSE
;
2910 bfd_boolean b_greater
= FALSE
;
2912 ReqOptionList
*l_a
= a
->options
;
2913 ReqOptionList
*l_b
= b
->options
;
2915 /* We only care if they both are the same except for
2916 a const16 vs. an l32r. */
2918 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2920 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2921 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2922 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2924 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2926 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2928 /* This is the case we care about. */
2929 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2930 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2937 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2938 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2948 l_or_a
= l_or_a
->next
;
2949 l_or_b
= l_or_b
->next
;
2951 if (l_or_a
|| l_or_b
)
2960 /* Incomparable if the substitution was used differently in two cases. */
2961 if (a_greater
&& b_greater
)
2973 static TransitionRule
*
2974 xg_instruction_match (TInsn
*insn
)
2976 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2978 gas_assert (insn
->opcode
< table
->num_opcodes
);
2980 /* Walk through all of the possible transitions. */
2981 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2983 TransitionRule
*rule
= l
->rule
;
2984 if (xg_instruction_matches_rule (insn
, rule
))
2991 /* Various Other Internal Functions. */
2994 is_unique_insn_expansion (TransitionRule
*r
)
2996 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2998 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3004 /* Check if there is exactly one relaxation for INSN that converts it to
3005 another instruction of equal or larger size. If so, and if TARG is
3006 non-null, go ahead and generate the relaxed instruction into TARG. If
3007 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3008 instruction, i.e., ignore relaxations that convert to an instruction of
3009 equal size. In some contexts where this function is used, only
3010 a single widening is allowed and the NARROW_ONLY argument is used to
3011 exclude cases like ADDI being "widened" to an ADDMI, which may
3012 later be relaxed to an ADDMI/ADDI pair. */
3015 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3017 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3019 TransitionRule
*match
= 0;
3021 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3022 gas_assert (insn
->opcode
< table
->num_opcodes
);
3024 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3026 TransitionRule
*rule
= l
->rule
;
3028 if (xg_instruction_matches_rule (insn
, rule
)
3029 && is_unique_insn_expansion (rule
)
3030 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3031 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3042 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3047 /* Return the maximum number of bytes this opcode can expand to. */
3050 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3052 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3054 int max_size
= xg_get_single_size (opcode
);
3056 gas_assert (opcode
< table
->num_opcodes
);
3058 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3060 TransitionRule
*rule
= l
->rule
;
3061 BuildInstr
*build_list
;
3066 build_list
= rule
->to_instr
;
3067 if (is_unique_insn_expansion (rule
))
3069 gas_assert (build_list
->typ
== INSTR_INSTR
);
3070 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3073 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3075 switch (build_list
->typ
)
3078 this_size
+= xg_get_single_size (build_list
->opcode
);
3080 case INSTR_LITERAL_DEF
:
3081 case INSTR_LABEL_DEF
:
3086 if (this_size
> max_size
)
3087 max_size
= this_size
;
3093 /* Return the maximum number of literal bytes this opcode can generate. */
3096 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3098 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3102 gas_assert (opcode
< table
->num_opcodes
);
3104 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3106 TransitionRule
*rule
= l
->rule
;
3107 BuildInstr
*build_list
;
3112 build_list
= rule
->to_instr
;
3113 if (is_unique_insn_expansion (rule
))
3115 gas_assert (build_list
->typ
== INSTR_INSTR
);
3116 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3119 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3121 switch (build_list
->typ
)
3123 case INSTR_LITERAL_DEF
:
3124 /* Hard-coded 4-byte literal. */
3128 case INSTR_LABEL_DEF
:
3133 if (this_size
> max_size
)
3134 max_size
= this_size
;
3141 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3143 int steps_taken
= 0;
3144 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3147 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3148 gas_assert (insn
->opcode
< table
->num_opcodes
);
3150 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3152 TransitionRule
*rule
= l
->rule
;
3154 if (xg_instruction_matches_rule (insn
, rule
))
3156 if (steps_taken
== lateral_steps
)
3166 get_special_literal_symbol (void)
3168 static symbolS
*sym
= NULL
;
3171 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3177 get_special_label_symbol (void)
3179 static symbolS
*sym
= NULL
;
3182 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3188 xg_valid_literal_expression (const expressionS
*exp
)
3210 /* This will check to see if the value can be converted into the
3211 operand type. It will return TRUE if it does not fit. */
3214 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3216 uint32 valbuf
= value
;
3217 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3223 /* Assumes: All immeds are constants. Check that all constants fit
3224 into their immeds; return FALSE if not. */
3227 xg_immeds_fit (const TInsn
*insn
)
3229 xtensa_isa isa
= xtensa_default_isa
;
3233 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3234 for (i
= 0; i
< n
; ++i
)
3236 const expressionS
*exp
= &insn
->tok
[i
];
3238 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3245 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3250 /* The symbol should have a fixup associated with it. */
3259 /* This should only be called after we have an initial
3260 estimate of the addresses. */
3263 xg_symbolic_immeds_fit (const TInsn
*insn
,
3269 xtensa_isa isa
= xtensa_default_isa
;
3277 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3279 for (i
= 0; i
< n
; ++i
)
3281 const expressionS
*exp
= &insn
->tok
[i
];
3283 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3290 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3296 /* Check for the worst case. */
3297 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3302 /* We only allow symbols for PC-relative references.
3303 If pc_frag == 0, then we don't have frag locations yet. */
3305 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3308 /* If it is a weak symbol or a symbol in a different section,
3309 it cannot be known to fit at assembly time. */
3310 if (S_IS_WEAK (exp
->X_add_symbol
)
3311 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3313 /* For a direct call with --no-longcalls, be optimistic and
3314 assume it will be in range. If the symbol is weak and
3315 undefined, it may remain undefined at link-time, in which
3316 case it will have a zero value and almost certainly be out
3317 of range for a direct call; thus, relax for undefined weak
3318 symbols even if longcalls is not enabled. */
3319 if (is_direct_call_opcode (insn
->opcode
)
3320 && ! pc_frag
->tc_frag_data
.use_longcalls
3321 && (! S_IS_WEAK (exp
->X_add_symbol
)
3322 || S_IS_DEFINED (exp
->X_add_symbol
)))
3328 symbolP
= exp
->X_add_symbol
;
3329 sym_frag
= symbol_get_frag (symbolP
);
3330 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3331 pc
= pc_frag
->fr_address
+ pc_offset
;
3333 /* If frag has yet to be reached on this pass, assume it
3334 will move by STRETCH just as we did. If this is not so,
3335 it will be because some frag between grows, and that will
3336 force another pass. Beware zero-length frags. There
3337 should be a faster way to do this. */
3340 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3341 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3346 new_offset
= target
;
3347 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3348 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3353 /* The symbol should have a fixup associated with it. */
3362 /* Return TRUE on success. */
3365 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3371 targ
->debug_line
= insn
->debug_line
;
3372 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3377 targ
->opcode
= bi
->opcode
;
3378 targ
->insn_type
= ITYPE_INSN
;
3379 targ
->is_specific_opcode
= FALSE
;
3381 for (; op
!= NULL
; op
= op
->next
)
3383 int op_num
= op
->op_num
;
3384 int op_data
= op
->op_data
;
3386 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3388 if (targ
->ntok
<= op_num
)
3389 targ
->ntok
= op_num
+ 1;
3394 set_expr_const (&targ
->tok
[op_num
], op_data
);
3397 gas_assert (op_data
< insn
->ntok
);
3398 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3401 if (insn
->extra_arg
.X_op
!= O_register
)
3403 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3406 sym
= get_special_literal_symbol ();
3407 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3408 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3409 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3410 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3413 sym
= get_special_label_symbol ();
3414 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3416 case OP_OPERAND_HI16U
:
3417 case OP_OPERAND_LOW16U
:
3418 gas_assert (op_data
< insn
->ntok
);
3419 if (expr_is_const (&insn
->tok
[op_data
]))
3422 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3423 val
= xg_apply_userdef_op_fn (op
->typ
,
3426 targ
->tok
[op_num
].X_add_number
= val
;
3430 /* For const16 we can create relocations for these. */
3431 if (targ
->opcode
== XTENSA_UNDEFINED
3432 || (targ
->opcode
!= xtensa_const16_opcode
))
3434 gas_assert (op_data
< insn
->ntok
);
3435 /* Need to build a O_lo16 or O_hi16. */
3436 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3437 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3439 if (op
->typ
== OP_OPERAND_HI16U
)
3440 targ
->tok
[op_num
].X_op
= O_hi16
;
3441 else if (op
->typ
== OP_OPERAND_LOW16U
)
3442 targ
->tok
[op_num
].X_op
= O_lo16
;
3449 /* currently handles:
3452 OP_OPERAND_F32MINUS */
3453 if (xg_has_userdef_op_fn (op
->typ
))
3455 gas_assert (op_data
< insn
->ntok
);
3456 if (expr_is_const (&insn
->tok
[op_data
]))
3459 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3460 val
= xg_apply_userdef_op_fn (op
->typ
,
3463 targ
->tok
[op_num
].X_add_number
= val
;
3466 return FALSE
; /* We cannot use a relocation for this. */
3475 case INSTR_LITERAL_DEF
:
3477 targ
->opcode
= XTENSA_UNDEFINED
;
3478 targ
->insn_type
= ITYPE_LITERAL
;
3479 targ
->is_specific_opcode
= FALSE
;
3480 for (; op
!= NULL
; op
= op
->next
)
3482 int op_num
= op
->op_num
;
3483 int op_data
= op
->op_data
;
3484 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3486 if (targ
->ntok
<= op_num
)
3487 targ
->ntok
= op_num
+ 1;
3492 gas_assert (op_data
< insn
->ntok
);
3493 /* We can only pass resolvable literals through. */
3494 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3496 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3508 case INSTR_LABEL_DEF
:
3510 targ
->opcode
= XTENSA_UNDEFINED
;
3511 targ
->insn_type
= ITYPE_LABEL
;
3512 targ
->is_specific_opcode
= FALSE
;
3513 /* Literal with no ops is a label? */
3514 gas_assert (op
== NULL
);
3525 /* Return TRUE on success. */
3528 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3530 for (; bi
!= NULL
; bi
= bi
->next
)
3532 TInsn
*next_insn
= istack_push_space (istack
);
3534 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3541 /* Return TRUE on valid expansion. */
3544 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3546 int stack_size
= istack
->ninsn
;
3547 int steps_taken
= 0;
3548 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3551 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3552 gas_assert (insn
->opcode
< table
->num_opcodes
);
3554 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3556 TransitionRule
*rule
= l
->rule
;
3558 if (xg_instruction_matches_rule (insn
, rule
))
3560 if (lateral_steps
== steps_taken
)
3564 /* This is it. Expand the rule to the stack. */
3565 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3568 /* Check to see if it fits. */
3569 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3571 TInsn
*tinsn
= &istack
->insn
[i
];
3573 if (tinsn
->insn_type
== ITYPE_INSN
3574 && !tinsn_has_symbolic_operands (tinsn
)
3575 && !xg_immeds_fit (tinsn
))
3577 istack
->ninsn
= stack_size
;
3590 /* Relax the assembly instruction at least "min_steps".
3591 Return the number of steps taken.
3593 For relaxation to correctly terminate, every relaxation chain must
3594 terminate in one of two ways:
3596 1. If the chain from one instruction to the next consists entirely of
3597 single instructions, then the chain *must* handle all possible
3598 immediates without failing. It must not ever fail because an
3599 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3600 chain is one example. L32R loads 32 bits, and there cannot be an
3601 immediate larger than 32 bits, so it satisfies this condition.
3602 Single instruction relaxation chains are as defined by
3603 xg_is_single_relaxable_instruction.
3605 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3606 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3608 Strictly speaking, in most cases you can violate condition 1 and be OK
3609 -- in particular when the last two instructions have the same single
3610 size. But nevertheless, you should guarantee the above two conditions.
3612 We could fix this so that single-instruction expansions correctly
3613 terminate when they can't handle the range, but the error messages are
3614 worse, and it actually turns out that in every case but one (18-bit wide
3615 branches), you need a multi-instruction expansion to get the full range
3616 anyway. And because 18-bit branches are handled identically to 15-bit
3617 branches, there isn't any point in changing it. */
3620 xg_assembly_relax (IStack
*istack
,
3623 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3624 offsetT pc_offset
, /* offset in fragment */
3625 int min_steps
, /* minimum conversion steps */
3626 long stretch
) /* number of bytes stretched so far */
3628 int steps_taken
= 0;
3630 /* Some of its immeds don't fit. Try to build a relaxed version.
3631 This may go through a couple of stages of single instruction
3632 transformations before we get there. */
3634 TInsn single_target
;
3636 int lateral_steps
= 0;
3637 int istack_size
= istack
->ninsn
;
3639 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3640 && steps_taken
>= min_steps
)
3642 istack_push (istack
, insn
);
3645 current_insn
= *insn
;
3647 /* Walk through all of the single instruction expansions. */
3648 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3651 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3654 if (steps_taken
>= min_steps
)
3656 istack_push (istack
, &single_target
);
3660 current_insn
= single_target
;
3663 /* Now check for a multi-instruction expansion. */
3664 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3666 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3669 if (steps_taken
>= min_steps
)
3671 istack_push (istack
, ¤t_insn
);
3676 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3678 if (steps_taken
>= min_steps
)
3682 istack
->ninsn
= istack_size
;
3685 /* It's not going to work -- use the original. */
3686 istack_push (istack
, insn
);
3692 xg_finish_frag (char *last_insn
,
3693 enum xtensa_relax_statesE frag_state
,
3694 enum xtensa_relax_statesE slot0_state
,
3696 bfd_boolean is_insn
)
3698 /* Finish off this fragment so that it has at LEAST the desired
3699 max_growth. If it doesn't fit in this fragment, close this one
3700 and start a new one. In either case, return a pointer to the
3701 beginning of the growth area. */
3705 frag_grow (max_growth
);
3706 old_frag
= frag_now
;
3708 frag_now
->fr_opcode
= last_insn
;
3710 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3712 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3713 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3715 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3716 xtensa_set_frag_assembly_state (frag_now
);
3718 /* Just to make sure that we did not split it up. */
3719 gas_assert (old_frag
->fr_next
== frag_now
);
3723 /* Return TRUE if the target frag is one of the next non-empty frags. */
3726 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3731 for (; fragP
; fragP
= fragP
->fr_next
)
3733 if (fragP
== target
)
3735 if (fragP
->fr_fix
!= 0)
3737 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3739 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3740 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3742 if (fragP
->fr_type
== rs_space
)
3750 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3752 xtensa_isa isa
= xtensa_default_isa
;
3754 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3759 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3760 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3763 for (i
= 0; i
< num_ops
; i
++)
3765 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3771 if (target_op
== -1)
3774 if (insn
->ntok
<= target_op
)
3777 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3780 sym
= insn
->tok
[target_op
].X_add_symbol
;
3784 if (insn
->tok
[target_op
].X_add_number
!= 0)
3787 target_frag
= symbol_get_frag (sym
);
3788 if (target_frag
== NULL
)
3791 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3792 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3800 xg_add_branch_and_loop_targets (TInsn
*insn
)
3802 xtensa_isa isa
= xtensa_default_isa
;
3803 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3805 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3808 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3809 && insn
->tok
[i
].X_op
== O_symbol
)
3810 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3814 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3815 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3819 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3821 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3822 && insn
->tok
[i
].X_op
== O_symbol
)
3824 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3825 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3826 if (S_IS_DEFINED (sym
))
3827 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3834 /* Return FALSE if no error. */
3837 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3842 switch (instr_spec
->typ
)
3845 new_insn
->insn_type
= ITYPE_INSN
;
3846 new_insn
->opcode
= instr_spec
->opcode
;
3848 case INSTR_LITERAL_DEF
:
3849 new_insn
->insn_type
= ITYPE_LITERAL
;
3850 new_insn
->opcode
= XTENSA_UNDEFINED
;
3852 case INSTR_LABEL_DEF
:
3855 new_insn
->is_specific_opcode
= FALSE
;
3856 new_insn
->debug_line
= old_insn
->debug_line
;
3857 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3859 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3862 const expressionS
*src_exp
;
3868 /* The expression must be the constant. */
3869 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3870 exp
= &new_insn
->tok
[b_op
->op_num
];
3871 set_expr_const (exp
, b_op
->op_data
);
3875 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3876 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3877 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3878 exp
= &new_insn
->tok
[b_op
->op_num
];
3879 copy_expr (exp
, src_exp
);
3884 as_bad (_("can't handle generation of literal/labels yet"));
3888 as_bad (_("can't handle undefined OP TYPE"));
3893 new_insn
->ntok
= num_ops
;
3898 /* Return TRUE if it was simplified. */
3901 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3903 TransitionRule
*rule
;
3904 BuildInstr
*insn_spec
;
3906 if (old_insn
->is_specific_opcode
|| !density_supported
)
3909 rule
= xg_instruction_match (old_insn
);
3913 insn_spec
= rule
->to_instr
;
3914 /* There should only be one. */
3915 gas_assert (insn_spec
!= NULL
);
3916 gas_assert (insn_spec
->next
== NULL
);
3917 if (insn_spec
->next
!= NULL
)
3920 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3926 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3927 l32i.n. (2) Check the number of operands. (3) Place the instruction
3928 tokens into the stack or relax it and place multiple
3929 instructions/literals onto the stack. Return FALSE if no error. */
3932 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3936 bfd_boolean do_expand
;
3938 tinsn_init (&new_insn
);
3940 /* Narrow it if we can. xg_simplify_insn now does all the
3941 appropriate checking (e.g., for the density option). */
3942 if (xg_simplify_insn (orig_insn
, &new_insn
))
3943 orig_insn
= &new_insn
;
3945 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3947 if (orig_insn
->ntok
< noperands
)
3949 as_bad (_("found %d operands for '%s': Expected %d"),
3951 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3955 if (orig_insn
->ntok
> noperands
)
3956 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3958 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3961 /* If there are not enough operands, we will assert above. If there
3962 are too many, just cut out the extras here. */
3963 orig_insn
->ntok
= noperands
;
3965 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3968 /* Special case for extui opcode which has constraints not handled
3969 by the ordinary operand encoding checks. The number of operands
3970 and related syntax issues have already been checked. */
3971 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3973 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3974 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3975 if (shiftimm
+ maskimm
> 32)
3977 as_bad (_("immediate operands sum to greater than 32"));
3982 /* If the instruction will definitely need to be relaxed, it is better
3983 to expand it now for better scheduling. Decide whether to expand
3985 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3987 /* Calls should be expanded to longcalls only in the backend relaxation
3988 so that the assembly scheduler will keep the L32R/CALLX instructions
3990 if (is_direct_call_opcode (orig_insn
->opcode
))
3993 if (tinsn_has_symbolic_operands (orig_insn
))
3995 /* The values of symbolic operands are not known yet, so only expand
3996 now if an operand is "complex" (e.g., difference of symbols) and
3997 will have to be stored as a literal regardless of the value. */
3998 if (!tinsn_has_complex_operands (orig_insn
))
4001 else if (xg_immeds_fit (orig_insn
))
4005 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4007 istack_push (istack
, orig_insn
);
4013 /* Return TRUE if the section flags are marked linkonce
4014 or the name is .gnu.linkonce.*. */
4016 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4019 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4021 flagword flags
, link_once_flags
;
4023 flags
= bfd_get_section_flags (abfd
, sec
);
4024 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4026 /* Flags might not be set yet. */
4027 if (!link_once_flags
4028 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4029 link_once_flags
= SEC_LINK_ONCE
;
4031 return (link_once_flags
!= 0);
4036 xtensa_add_literal_sym (symbolS
*sym
)
4040 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4042 l
->next
= literal_syms
;
4048 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4050 static int lit_num
= 0;
4051 static char name
[256];
4054 sprintf (name
, ".L_lit_sym%d", lit_num
);
4056 /* Create a local symbol. If it is in a linkonce section, we have to
4057 be careful to make sure that if it is used in a relocation that the
4058 symbol will be in the output file. */
4059 if (get_is_linkonce_section (stdoutput
, sec
))
4061 symbolP
= symbol_new (name
, sec
, 0, frag
);
4062 S_CLEAR_EXTERNAL (symbolP
);
4063 /* symbolP->local = 1; */
4066 symbolP
= symbol_new (name
, sec
, 0, frag
);
4068 xtensa_add_literal_sym (symbolP
);
4075 /* Currently all literals that are generated here are 32-bit L32R targets. */
4078 xg_assemble_literal (/* const */ TInsn
*insn
)
4081 symbolS
*lit_sym
= NULL
;
4082 bfd_reloc_code_real_type reloc
;
4083 bfd_boolean pcrel
= FALSE
;
4086 /* size = 4 for L32R. It could easily be larger when we move to
4087 larger constants. Add a parameter later. */
4088 offsetT litsize
= 4;
4089 offsetT litalign
= 2; /* 2^2 = 4 */
4090 expressionS saved_loc
;
4091 expressionS
* emit_val
;
4093 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4095 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4096 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4098 xtensa_switch_to_literal_fragment (&state
);
4100 emit_val
= &insn
->tok
[0];
4101 if (emit_val
->X_op
== O_big
)
4103 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4106 /* This happens when someone writes a "movi a2, big_number". */
4107 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4108 _("invalid immediate"));
4109 xtensa_restore_emit_state (&state
);
4114 /* Force a 4-byte align here. Note that this opens a new frag, so all
4115 literals done with this function have a frag to themselves. That's
4116 important for the way text section literals work. */
4117 frag_align (litalign
, 0, 0);
4118 record_alignment (now_seg
, litalign
);
4120 switch (emit_val
->X_op
)
4130 p
= frag_more (litsize
);
4131 xtensa_set_frag_assembly_state (frag_now
);
4132 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4133 if (emit_val
->X_add_symbol
)
4134 emit_val
->X_op
= O_symbol
;
4136 emit_val
->X_op
= O_constant
;
4137 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4138 litsize
, emit_val
, pcrel
, reloc
);
4142 emit_expr (emit_val
, litsize
);
4146 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4147 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4148 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4149 lit_sym
= frag_now
->fr_symbol
;
4152 xtensa_restore_emit_state (&state
);
4158 xg_assemble_literal_space (/* const */ int size
, int slot
)
4161 /* We might have to do something about this alignment. It only
4162 takes effect if something is placed here. */
4163 offsetT litalign
= 2; /* 2^2 = 4 */
4164 fragS
*lit_saved_frag
;
4166 gas_assert (size
% 4 == 0);
4168 xtensa_switch_to_literal_fragment (&state
);
4170 /* Force a 4-byte align here. */
4171 frag_align (litalign
, 0, 0);
4172 record_alignment (now_seg
, litalign
);
4176 lit_saved_frag
= frag_now
;
4177 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4178 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4179 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4182 xtensa_restore_emit_state (&state
);
4183 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4187 /* Put in a fixup record based on the opcode.
4188 Return TRUE on success. */
4191 xg_add_opcode_fix (TInsn
*tinsn
,
4199 xtensa_opcode opcode
= tinsn
->opcode
;
4200 bfd_reloc_code_real_type reloc
;
4201 reloc_howto_type
*howto
;
4205 reloc
= BFD_RELOC_NONE
;
4207 /* First try the special cases for "alternate" relocs. */
4208 if (opcode
== xtensa_l32r_opcode
)
4210 if (fragP
->tc_frag_data
.use_absolute_literals
)
4211 reloc
= encode_alt_reloc (slot
);
4213 else if (opcode
== xtensa_const16_opcode
)
4215 if (exp
->X_op
== O_lo16
)
4217 reloc
= encode_reloc (slot
);
4218 exp
->X_op
= O_symbol
;
4220 else if (exp
->X_op
== O_hi16
)
4222 reloc
= encode_alt_reloc (slot
);
4223 exp
->X_op
= O_symbol
;
4227 if (opnum
!= get_relaxable_immed (opcode
))
4229 as_bad (_("invalid relocation for operand %i of '%s'"),
4230 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4234 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4235 into the symbol table where the generic portions of the assembler
4236 won't know what to do with them. */
4237 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4239 as_bad (_("invalid expression for operand %i of '%s'"),
4240 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4244 /* Next try the generic relocs. */
4245 if (reloc
== BFD_RELOC_NONE
)
4246 reloc
= encode_reloc (slot
);
4247 if (reloc
== BFD_RELOC_NONE
)
4249 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4253 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4256 as_bad (_("undefined symbol for opcode \"%s\""),
4257 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4261 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4262 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4263 howto
->pc_relative
, reloc
);
4264 the_fix
->fx_no_overflow
= 1;
4265 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4266 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4267 the_fix
->tc_fix_data
.slot
= slot
;
4274 xg_emit_insn_to_buf (TInsn
*tinsn
,
4278 bfd_boolean build_fix
)
4280 static xtensa_insnbuf insnbuf
= NULL
;
4281 bfd_boolean has_symbolic_immed
= FALSE
;
4282 bfd_boolean ok
= TRUE
;
4285 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4287 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4288 if (has_symbolic_immed
&& build_fix
)
4291 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4292 int slot
= xg_get_single_slot (tinsn
->opcode
);
4293 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4294 expressionS
*exp
= &tinsn
->tok
[opnum
];
4296 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4299 fragP
->tc_frag_data
.is_insn
= TRUE
;
4300 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4301 (unsigned char *) buf
, 0);
4307 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4309 symbolS
*sym
= get_special_literal_symbol ();
4313 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4314 for (i
= 0; i
< insn
->ntok
; i
++)
4315 if (insn
->tok
[i
].X_add_symbol
== sym
)
4316 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4322 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4324 symbolS
*sym
= get_special_label_symbol ();
4326 for (i
= 0; i
< insn
->ntok
; i
++)
4327 if (insn
->tok
[i
].X_add_symbol
== sym
)
4328 insn
->tok
[i
].X_add_symbol
= label_sym
;
4333 /* Return TRUE if the instruction can write to the specified
4334 integer register. */
4337 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4341 xtensa_isa isa
= xtensa_default_isa
;
4343 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4345 for (i
= 0; i
< num_ops
; i
++)
4348 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4349 if ((inout
== 'o' || inout
== 'm')
4350 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4352 xtensa_regfile opnd_rf
=
4353 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4354 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4356 if ((insn
->tok
[i
].X_op
== O_register
)
4357 && (insn
->tok
[i
].X_add_number
== regnum
))
4367 is_bad_loopend_opcode (const TInsn
*tinsn
)
4369 xtensa_opcode opcode
= tinsn
->opcode
;
4371 if (opcode
== XTENSA_UNDEFINED
)
4374 if (opcode
== xtensa_call0_opcode
4375 || opcode
== xtensa_callx0_opcode
4376 || opcode
== xtensa_call4_opcode
4377 || opcode
== xtensa_callx4_opcode
4378 || opcode
== xtensa_call8_opcode
4379 || opcode
== xtensa_callx8_opcode
4380 || opcode
== xtensa_call12_opcode
4381 || opcode
== xtensa_callx12_opcode
4382 || opcode
== xtensa_isync_opcode
4383 || opcode
== xtensa_ret_opcode
4384 || opcode
== xtensa_ret_n_opcode
4385 || opcode
== xtensa_retw_opcode
4386 || opcode
== xtensa_retw_n_opcode
4387 || opcode
== xtensa_waiti_opcode
4388 || opcode
== xtensa_rsr_lcount_opcode
)
4395 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4396 This allows the debugger to add unaligned labels.
4397 Also, the assembler generates stabs labels that need
4398 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4401 is_unaligned_label (symbolS
*sym
)
4403 const char *name
= S_GET_NAME (sym
);
4404 static size_t fake_size
= 0;
4408 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4411 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4413 fake_size
= strlen (FAKE_LABEL_NAME
);
4416 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4417 && (name
[fake_size
] == 'F'
4418 || name
[fake_size
] == 'L'
4419 || (name
[fake_size
] == 'e'
4420 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4428 next_non_empty_frag (const fragS
*fragP
)
4430 fragS
*next_fragP
= fragP
->fr_next
;
4432 /* Sometimes an empty will end up here due storage allocation issues.
4433 So we have to skip until we find something legit. */
4434 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4435 next_fragP
= next_fragP
->fr_next
;
4437 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4445 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4447 xtensa_opcode out_opcode
;
4448 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4450 if (next_fragP
== NULL
)
4453 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4454 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4456 *opcode
= out_opcode
;
4464 frag_format_size (const fragS
*fragP
)
4466 static xtensa_insnbuf insnbuf
= NULL
;
4467 xtensa_isa isa
= xtensa_default_isa
;
4472 insnbuf
= xtensa_insnbuf_alloc (isa
);
4475 return XTENSA_UNDEFINED
;
4477 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4478 (unsigned char *) fragP
->fr_literal
, 0);
4480 fmt
= xtensa_format_decode (isa
, insnbuf
);
4481 if (fmt
== XTENSA_UNDEFINED
)
4482 return XTENSA_UNDEFINED
;
4483 fmt_size
= xtensa_format_length (isa
, fmt
);
4485 /* If the next format won't be changing due to relaxation, just
4486 return the length of the first format. */
4487 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4490 /* If during relaxation we have to pull an instruction out of a
4491 multi-slot instruction, we will return the more conservative
4492 number. This works because alignment on bigger instructions
4493 is more restrictive than alignment on smaller instructions.
4494 This is more conservative than we would like, but it happens
4497 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4500 /* If we aren't doing one of our own relaxations or it isn't
4501 slot-based, then the insn size won't change. */
4502 if (fragP
->fr_type
!= rs_machine_dependent
)
4504 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4507 /* If an instruction is about to grow, return the longer size. */
4508 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4509 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4510 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4512 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4513 instruction in the relaxed version is of length 3. (The case
4514 where we have to pull the instruction out of a FLIX bundle
4515 is handled conservatively above.) However, frags with opcodes
4516 that are expanding to wide branches end up having formats that
4517 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4518 we can't tell directly what format the relaxer picked. This
4519 is a wart in the design of the relaxer that should someday be
4520 fixed, but would require major changes, or at least should
4521 be accompanied by major changes to make use of that data.
4523 In any event, we can tell that we are expanding from a single-slot
4524 format to a wider one with the logic below. */
4527 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4529 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4531 if (relaxed_size
== xtensa_format_length (isa
, i
))
4532 return relaxed_size
;
4538 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4539 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4546 next_frag_format_size (const fragS
*fragP
)
4548 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4549 return frag_format_size (next_fragP
);
4553 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4554 required two-byte instructions to be treated as three-byte instructions
4555 for loop instruction alignment. This restriction was removed beginning
4556 with Xtensa LX. Now the only requirement on loop instruction alignment
4557 is that the first instruction of the loop must appear at an address that
4558 does not cross a fetch boundary. */
4561 get_loop_align_size (int insn_size
)
4563 if (insn_size
== XTENSA_UNDEFINED
)
4564 return xtensa_fetch_width
;
4566 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4573 /* If the next legit fragment is an end-of-loop marker,
4574 switch its state so it will instantiate a NOP. */
4577 update_next_frag_state (fragS
*fragP
)
4579 fragS
*next_fragP
= fragP
->fr_next
;
4580 fragS
*new_target
= NULL
;
4584 /* We are guaranteed there will be one of these... */
4585 while (!(next_fragP
->fr_type
== rs_machine_dependent
4586 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4587 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4588 next_fragP
= next_fragP
->fr_next
;
4590 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4591 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4592 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4594 /* ...and one of these. */
4595 new_target
= next_fragP
->fr_next
;
4596 while (!(new_target
->fr_type
== rs_machine_dependent
4597 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4598 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4599 new_target
= new_target
->fr_next
;
4601 gas_assert (new_target
->fr_type
== rs_machine_dependent
4602 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4603 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4606 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4608 if (next_fragP
->fr_type
== rs_machine_dependent
4609 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4611 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4615 next_fragP
= next_fragP
->fr_next
;
4621 next_frag_is_branch_target (const fragS
*fragP
)
4623 /* Sometimes an empty will end up here due to storage allocation issues,
4624 so we have to skip until we find something legit. */
4625 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4627 if (fragP
->tc_frag_data
.is_branch_target
)
4629 if (fragP
->fr_fix
!= 0)
4637 next_frag_is_loop_target (const fragS
*fragP
)
4639 /* Sometimes an empty will end up here due storage allocation issues.
4640 So we have to skip until we find something legit. */
4641 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4643 if (fragP
->tc_frag_data
.is_loop_target
)
4645 if (fragP
->fr_fix
!= 0)
4653 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4655 const fragS
*next_fragp
= fragp
->fr_next
;
4656 xtensa_opcode next_opcode
;
4658 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4661 /* Sometimes an empty will end up here due to storage allocation issues,
4662 so we have to skip until we find something legit. */
4663 while (next_fragp
->fr_fix
== 0)
4664 next_fragp
= next_fragp
->fr_next
;
4666 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4669 /* There is some implicit knowledge encoded in here.
4670 The LOOP instructions that are NOT RELAX_IMMED have
4671 been relaxed. Note that we can assume that the LOOP
4672 instruction is in slot 0 because loops aren't bundleable. */
4673 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4674 return get_expanded_loop_offset (next_opcode
);
4680 /* Mark a location where we can later insert literal frags. Update
4681 the section's literal_pool_loc, so subsequent literals can be
4682 placed nearest to their use. */
4685 xtensa_mark_literal_pool_location (void)
4687 /* Any labels pointing to the current location need
4688 to be adjusted to after the literal pool. */
4690 fragS
*pool_location
;
4692 if (use_literal_section
)
4695 /* We stash info in these frags so we can later move the literal's
4696 fixes into this frchain's fix list. */
4697 pool_location
= frag_now
;
4698 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4699 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4700 frag_variant (rs_machine_dependent
, 0, 0,
4701 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4702 xtensa_set_frag_assembly_state (frag_now
);
4703 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4704 frag_variant (rs_machine_dependent
, 0, 0,
4705 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4706 xtensa_set_frag_assembly_state (frag_now
);
4708 /* Now put a frag into the literal pool that points to this location. */
4709 set_literal_pool_location (now_seg
, pool_location
);
4710 xtensa_switch_to_non_abs_literal_fragment (&s
);
4711 frag_align (2, 0, 0);
4712 record_alignment (now_seg
, 2);
4714 /* Close whatever frag is there. */
4715 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4716 xtensa_set_frag_assembly_state (frag_now
);
4717 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4718 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4719 xtensa_restore_emit_state (&s
);
4720 xtensa_set_frag_assembly_state (frag_now
);
4724 /* Build a nop of the correct size into tinsn. */
4727 build_nop (TInsn
*tinsn
, int size
)
4733 tinsn
->opcode
= xtensa_nop_n_opcode
;
4735 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4736 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4740 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4742 tinsn
->opcode
= xtensa_or_opcode
;
4743 set_expr_const (&tinsn
->tok
[0], 1);
4744 set_expr_const (&tinsn
->tok
[1], 1);
4745 set_expr_const (&tinsn
->tok
[2], 1);
4749 tinsn
->opcode
= xtensa_nop_opcode
;
4751 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4756 /* Assemble a NOP of the requested size in the buffer. User must have
4757 allocated "buf" with at least "size" bytes. */
4760 assemble_nop (int size
, char *buf
)
4762 static xtensa_insnbuf insnbuf
= NULL
;
4765 build_nop (&tinsn
, size
);
4768 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4770 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4771 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4772 (unsigned char *) buf
, 0);
4776 /* Return the number of bytes for the offset of the expanded loop
4777 instruction. This should be incorporated into the relaxation
4778 specification but is hard-coded here. This is used to auto-align
4779 the loop instruction. It is invalid to call this function if the
4780 configuration does not have loops or if the opcode is not a loop
4784 get_expanded_loop_offset (xtensa_opcode opcode
)
4786 /* This is the OFFSET of the loop instruction in the expanded loop.
4787 This MUST correspond directly to the specification of the loop
4788 expansion. It will be validated on fragment conversion. */
4789 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4790 if (opcode
== xtensa_loop_opcode
)
4792 if (opcode
== xtensa_loopnez_opcode
)
4794 if (opcode
== xtensa_loopgtz_opcode
)
4796 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4802 get_literal_pool_location (segT seg
)
4804 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4809 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4811 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4815 /* Set frag assembly state should be called when a new frag is
4816 opened and after a frag has been closed. */
4819 xtensa_set_frag_assembly_state (fragS
*fragP
)
4821 if (!density_supported
)
4822 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4824 /* This function is called from subsegs_finish, which is called
4825 after xtensa_end, so we can't use "use_transform" or
4826 "use_schedule" here. */
4827 if (!directive_state
[directive_transform
])
4828 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4829 if (directive_state
[directive_longcalls
])
4830 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4831 fragP
->tc_frag_data
.use_absolute_literals
=
4832 directive_state
[directive_absolute_literals
];
4833 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4838 relaxable_section (asection
*sec
)
4840 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4841 && strcmp (sec
->name
, ".eh_frame") != 0);
4846 xtensa_mark_frags_for_org (void)
4850 /* Walk over each fragment of all of the current segments. If we find
4851 a .org frag in any of the segments, mark all frags prior to it as
4852 "no transform", which will prevent linker optimizations from messing
4853 up the .org distance. This should be done after
4854 xtensa_find_unmarked_state_frags, because we don't want to worry here
4855 about that function trashing the data we save here. */
4857 for (seclist
= &stdoutput
->sections
;
4858 seclist
&& *seclist
;
4859 seclist
= &(*seclist
)->next
)
4861 segT sec
= *seclist
;
4862 segment_info_type
*seginfo
;
4865 flags
= bfd_get_section_flags (stdoutput
, sec
);
4866 if (flags
& SEC_DEBUGGING
)
4868 if (!(flags
& SEC_ALLOC
))
4871 seginfo
= seg_info (sec
);
4872 if (seginfo
&& seginfo
->frchainP
)
4874 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4875 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4876 fragP
= fragP
->fr_next
)
4878 /* cvt_frag_to_fill has changed the fr_type of org frags to
4879 rs_fill, so use the value as cached in rs_subtype here. */
4880 if (fragP
->fr_subtype
== RELAX_ORG
)
4882 while (last_fragP
!= fragP
->fr_next
)
4884 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4885 last_fragP
= last_fragP
->fr_next
;
4895 xtensa_find_unmarked_state_frags (void)
4899 /* Walk over each fragment of all of the current segments. For each
4900 unmarked fragment, mark it with the same info as the previous
4902 for (seclist
= &stdoutput
->sections
;
4903 seclist
&& *seclist
;
4904 seclist
= &(*seclist
)->next
)
4906 segT sec
= *seclist
;
4907 segment_info_type
*seginfo
;
4910 flags
= bfd_get_section_flags (stdoutput
, sec
);
4911 if (flags
& SEC_DEBUGGING
)
4913 if (!(flags
& SEC_ALLOC
))
4916 seginfo
= seg_info (sec
);
4917 if (seginfo
&& seginfo
->frchainP
)
4919 fragS
*last_fragP
= 0;
4920 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4921 fragP
= fragP
->fr_next
)
4923 if (fragP
->fr_fix
!= 0
4924 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4926 if (last_fragP
== 0)
4928 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4929 _("assembly state not set for first frag in section %s"),
4934 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4935 fragP
->tc_frag_data
.is_no_density
=
4936 last_fragP
->tc_frag_data
.is_no_density
;
4937 fragP
->tc_frag_data
.is_no_transform
=
4938 last_fragP
->tc_frag_data
.is_no_transform
;
4939 fragP
->tc_frag_data
.use_longcalls
=
4940 last_fragP
->tc_frag_data
.use_longcalls
;
4941 fragP
->tc_frag_data
.use_absolute_literals
=
4942 last_fragP
->tc_frag_data
.use_absolute_literals
;
4945 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4954 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4956 void *unused ATTRIBUTE_UNUSED
)
4958 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4959 segment_info_type
*seginfo
= seg_info (sec
);
4960 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4962 if (flags
& SEC_CODE
)
4964 xtensa_isa isa
= xtensa_default_isa
;
4965 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4966 while (frag
!= NULL
)
4968 if (frag
->tc_frag_data
.is_branch_target
)
4971 addressT branch_align
, frag_addr
;
4974 xtensa_insnbuf_from_chars
4975 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4976 fmt
= xtensa_format_decode (isa
, insnbuf
);
4977 op_size
= xtensa_format_length (isa
, fmt
);
4978 branch_align
= 1 << branch_align_power (sec
);
4979 frag_addr
= frag
->fr_address
% branch_align
;
4980 if (frag_addr
+ op_size
> branch_align
)
4981 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4982 _("unaligned branch target: %d bytes at 0x%lx"),
4983 op_size
, (long) frag
->fr_address
);
4985 frag
= frag
->fr_next
;
4987 xtensa_insnbuf_free (isa
, insnbuf
);
4993 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4995 void *unused ATTRIBUTE_UNUSED
)
4997 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4998 segment_info_type
*seginfo
= seg_info (sec
);
4999 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5000 xtensa_isa isa
= xtensa_default_isa
;
5002 if (flags
& SEC_CODE
)
5004 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5005 while (frag
!= NULL
)
5007 if (frag
->tc_frag_data
.is_first_loop_insn
)
5013 xtensa_insnbuf_from_chars
5014 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5015 fmt
= xtensa_format_decode (isa
, insnbuf
);
5016 op_size
= xtensa_format_length (isa
, fmt
);
5017 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5019 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5020 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5021 _("unaligned loop: %d bytes at 0x%lx"),
5022 op_size
, (long) frag
->fr_address
);
5024 frag
= frag
->fr_next
;
5026 xtensa_insnbuf_free (isa
, insnbuf
);
5032 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5034 xtensa_isa isa
= xtensa_default_isa
;
5035 static xtensa_insnbuf insnbuf
= NULL
;
5036 static xtensa_insnbuf slotbuf
= NULL
;
5039 bfd_boolean alt_reloc
;
5040 xtensa_opcode opcode
;
5041 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5043 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5045 as_fatal (_("unexpected fix"));
5049 insnbuf
= xtensa_insnbuf_alloc (isa
);
5050 slotbuf
= xtensa_insnbuf_alloc (isa
);
5053 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5054 fmt
= xtensa_format_decode (isa
, insnbuf
);
5055 if (fmt
== XTENSA_UNDEFINED
)
5056 as_fatal (_("undecodable fix"));
5057 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5058 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5059 if (opcode
== XTENSA_UNDEFINED
)
5060 as_fatal (_("undecodable fix"));
5062 /* CONST16 immediates are not PC-relative, despite the fact that we
5063 reuse the normal PC-relative operand relocations for the low part
5064 of a CONST16 operand. */
5065 if (opcode
== xtensa_const16_opcode
)
5068 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5069 get_relaxable_immed (opcode
), val
,
5070 fixP
->fx_file
, fixP
->fx_line
);
5072 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5073 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5079 /* External Functions and Other GAS Hooks. */
5082 xtensa_target_format (void)
5084 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5089 xtensa_file_arch_init (bfd
*abfd
)
5091 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5096 md_number_to_chars (char *buf
, valueT val
, int n
)
5098 if (target_big_endian
)
5099 number_to_chars_bigendian (buf
, val
, n
);
5101 number_to_chars_littleendian (buf
, val
, n
);
5105 /* This function is called once, at assembler startup time. It should
5106 set up all the tables, etc. that the MD part of the assembler will
5112 segT current_section
= now_seg
;
5113 int current_subsec
= now_subseg
;
5117 xtensa_default_isa
= xtensa_isa_init (0, 0);
5118 isa
= xtensa_default_isa
;
5122 /* Set up the literal sections. */
5123 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5125 subseg_set (current_section
, current_subsec
);
5127 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5128 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5129 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5130 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5131 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5132 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5133 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5134 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5135 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5136 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5137 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5138 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5139 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5140 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5141 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5142 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5143 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5144 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5145 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5146 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5147 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5148 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5149 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5150 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5151 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5152 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5153 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5154 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5155 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5156 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5157 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5159 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5161 int format_slots
= xtensa_format_num_slots (isa
, i
);
5162 if (format_slots
> config_max_slots
)
5163 config_max_slots
= format_slots
;
5166 xg_init_vinsn (&cur_vinsn
);
5168 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5170 init_op_placement_info_table ();
5172 /* Set up the assembly state. */
5173 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5174 xtensa_set_frag_assembly_state (frag_now
);
5178 /* TC_INIT_FIX_DATA hook */
5181 xtensa_init_fix_data (fixS
*x
)
5183 x
->tc_fix_data
.slot
= 0;
5184 x
->tc_fix_data
.X_add_symbol
= NULL
;
5185 x
->tc_fix_data
.X_add_number
= 0;
5189 /* tc_frob_label hook */
5192 xtensa_frob_label (symbolS
*sym
)
5196 if (cur_vinsn
.inside_bundle
)
5198 as_bad (_("labels are not valid inside bundles"));
5202 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5204 /* Since the label was already attached to a frag associated with the
5205 previous basic block, it now needs to be reset to the current frag. */
5206 symbol_set_frag (sym
, frag_now
);
5207 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5209 if (generating_literals
)
5210 xtensa_add_literal_sym (sym
);
5212 xtensa_add_insn_label (sym
);
5214 if (symbol_get_tc (sym
)->is_loop_target
)
5216 if ((get_last_insn_flags (now_seg
, now_subseg
)
5217 & FLAG_IS_BAD_LOOPEND
) != 0)
5218 as_bad (_("invalid last instruction for a zero-overhead loop"));
5220 xtensa_set_frag_assembly_state (frag_now
);
5221 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5222 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5224 xtensa_set_frag_assembly_state (frag_now
);
5225 xtensa_move_labels (frag_now
, 0);
5228 /* No target aligning in the absolute section. */
5229 if (now_seg
!= absolute_section
5230 && !is_unaligned_label (sym
)
5231 && !generating_literals
)
5233 xtensa_set_frag_assembly_state (frag_now
);
5235 if (do_align_targets ())
5236 frag_var (rs_machine_dependent
, 0, (int) freq
,
5237 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5238 frag_now
->fr_offset
, NULL
);
5240 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5241 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5242 xtensa_set_frag_assembly_state (frag_now
);
5243 xtensa_move_labels (frag_now
, 0);
5246 /* We need to mark the following properties even if we aren't aligning. */
5248 /* If the label is already known to be a branch target, i.e., a
5249 forward branch, mark the frag accordingly. Backward branches
5250 are handled by xg_add_branch_and_loop_targets. */
5251 if (symbol_get_tc (sym
)->is_branch_target
)
5252 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5254 /* Loops only go forward, so they can be identified here. */
5255 if (symbol_get_tc (sym
)->is_loop_target
)
5256 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5258 dwarf2_emit_label (sym
);
5262 /* tc_unrecognized_line hook */
5265 xtensa_unrecognized_line (int ch
)
5270 if (cur_vinsn
.inside_bundle
== 0)
5272 /* PR8110: Cannot emit line number info inside a FLIX bundle
5273 when using --gstabs. Temporarily disable debug info. */
5274 generate_lineno_debug ();
5275 if (debug_type
== DEBUG_STABS
)
5277 xt_saved_debug_type
= debug_type
;
5278 debug_type
= DEBUG_NONE
;
5281 cur_vinsn
.inside_bundle
= 1;
5285 as_bad (_("extra opening brace"));
5291 if (cur_vinsn
.inside_bundle
)
5292 finish_vinsn (&cur_vinsn
);
5295 as_bad (_("extra closing brace"));
5300 as_bad (_("syntax error"));
5307 /* md_flush_pending_output hook */
5310 xtensa_flush_pending_output (void)
5312 /* This line fixes a bug where automatically generated gstabs info
5313 separates a function label from its entry instruction, ending up
5314 with the literal position between the function label and the entry
5315 instruction and crashing code. It only happens with --gstabs and
5316 --text-section-literals, and when several other obscure relaxation
5317 conditions are met. */
5318 if (outputting_stabs_line_debug
)
5321 if (cur_vinsn
.inside_bundle
)
5322 as_bad (_("missing closing brace"));
5324 /* If there is a non-zero instruction fragment, close it. */
5325 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5327 frag_wane (frag_now
);
5329 xtensa_set_frag_assembly_state (frag_now
);
5331 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5333 xtensa_clear_insn_labels ();
5337 /* We had an error while parsing an instruction. The string might look
5338 like this: "insn arg1, arg2 }". If so, we need to see the closing
5339 brace and reset some fields. Otherwise, the vinsn never gets closed
5340 and the num_slots field will grow past the end of the array of slots,
5341 and bad things happen. */
5344 error_reset_cur_vinsn (void)
5346 if (cur_vinsn
.inside_bundle
)
5348 if (*input_line_pointer
== '}'
5349 || *(input_line_pointer
- 1) == '}'
5350 || *(input_line_pointer
- 2) == '}')
5351 xg_clear_vinsn (&cur_vinsn
);
5357 md_assemble (char *str
)
5359 xtensa_isa isa
= xtensa_default_isa
;
5362 bfd_boolean has_underbar
= FALSE
;
5363 char *arg_strings
[MAX_INSN_ARGS
];
5365 TInsn orig_insn
; /* Original instruction from the input. */
5367 tinsn_init (&orig_insn
);
5369 /* Split off the opcode. */
5370 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5371 opname
= xmalloc (opnamelen
+ 1);
5372 memcpy (opname
, str
, opnamelen
);
5373 opname
[opnamelen
] = '\0';
5375 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5378 as_bad (_("syntax error"));
5382 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5385 /* Check for an underbar prefix. */
5388 has_underbar
= TRUE
;
5392 orig_insn
.insn_type
= ITYPE_INSN
;
5394 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5395 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5397 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5398 extra argument and set the opcode to "CALLXn". */
5399 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5400 && strncasecmp (opname
, "callx", 5) == 0)
5402 unsigned long window_size
;
5405 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5406 if (suffix
!= opname
+ 5
5407 && (window_size
== 0
5410 || window_size
== 12)
5411 && strcasecmp (suffix
, ".tls") == 0)
5413 switch (window_size
)
5415 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5416 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5417 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5418 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5422 as_bad (_("wrong number of operands for '%s'"), opname
);
5425 bfd_reloc_code_real_type reloc
;
5426 char *old_input_line_pointer
;
5427 expressionS
*tok
= &orig_insn
.extra_arg
;
5430 old_input_line_pointer
= input_line_pointer
;
5431 input_line_pointer
= arg_strings
[num_args
- 1];
5433 t
= expression (tok
);
5434 if (tok
->X_op
== O_symbol
5435 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5436 == BFD_RELOC_XTENSA_TLS_CALL
))
5437 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5439 as_bad (_("bad relocation expression for '%s'"), opname
);
5441 input_line_pointer
= old_input_line_pointer
;
5447 /* Special case: Check for "j.l" psuedo op. */
5448 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5449 && strncasecmp (opname
, "j.l", 3) == 0)
5452 as_bad (_("wrong number of operands for '%s'"), opname
);
5455 char *old_input_line_pointer
;
5456 expressionS
*tok
= &orig_insn
.extra_arg
;
5458 old_input_line_pointer
= input_line_pointer
;
5459 input_line_pointer
= arg_strings
[num_args
- 1];
5461 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5462 input_line_pointer
= old_input_line_pointer
;
5465 orig_insn
.opcode
= xtensa_j_opcode
;
5469 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5471 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5472 if (fmt
== XTENSA_UNDEFINED
)
5474 as_bad (_("unknown opcode or format name '%s'"), opname
);
5475 error_reset_cur_vinsn ();
5478 if (!cur_vinsn
.inside_bundle
)
5480 as_bad (_("format names only valid inside bundles"));
5481 error_reset_cur_vinsn ();
5484 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5485 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5487 cur_vinsn
.format
= fmt
;
5488 free (has_underbar
? opname
- 1 : opname
);
5489 error_reset_cur_vinsn ();
5493 /* Parse the arguments. */
5494 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5496 as_bad (_("syntax error"));
5497 error_reset_cur_vinsn ();
5501 /* Free the opcode and argument strings, now that they've been parsed. */
5502 free (has_underbar
? opname
- 1 : opname
);
5504 while (num_args
-- > 0)
5505 free (arg_strings
[num_args
]);
5507 /* Get expressions for invisible operands. */
5508 if (get_invisible_operands (&orig_insn
))
5510 error_reset_cur_vinsn ();
5514 /* Check for the right number and type of arguments. */
5515 if (tinsn_check_arguments (&orig_insn
))
5517 error_reset_cur_vinsn ();
5521 /* Record the line number for each TInsn, because a FLIX bundle may be
5522 spread across multiple input lines and individual instructions may be
5523 moved around in some cases. */
5524 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5525 dwarf2_where (&orig_insn
.debug_line
);
5526 dwarf2_consume_line_info ();
5528 xg_add_branch_and_loop_targets (&orig_insn
);
5530 /* Check that immediate value for ENTRY is >= 16. */
5531 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5533 expressionS
*exp
= &orig_insn
.tok
[2];
5534 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5535 as_warn (_("entry instruction with stack decrement < 16"));
5539 assemble_tokens (opcode, tok, ntok);
5540 expand the tokens from the orig_insn into the
5541 stack of instructions that will not expand
5542 unless required at relaxation time. */
5544 if (!cur_vinsn
.inside_bundle
)
5545 emit_single_op (&orig_insn
);
5546 else /* We are inside a bundle. */
5548 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5549 cur_vinsn
.num_slots
++;
5550 if (*input_line_pointer
== '}'
5551 || *(input_line_pointer
- 1) == '}'
5552 || *(input_line_pointer
- 2) == '}')
5553 finish_vinsn (&cur_vinsn
);
5556 /* We've just emitted a new instruction so clear the list of labels. */
5557 xtensa_clear_insn_labels ();
5561 /* HANDLE_ALIGN hook */
5563 /* For a .align directive, we mark the previous block with the alignment
5564 information. This will be placed in the object file in the
5565 property section corresponding to this section. */
5568 xtensa_handle_align (fragS
*fragP
)
5571 && ! fragP
->tc_frag_data
.is_literal
5572 && (fragP
->fr_type
== rs_align
5573 || fragP
->fr_type
== rs_align_code
)
5574 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5575 && fragP
->fr_offset
> 0
5576 && now_seg
!= bss_section
)
5578 fragP
->tc_frag_data
.is_align
= TRUE
;
5579 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5582 if (fragP
->fr_type
== rs_align_test
)
5585 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5587 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5588 _("unaligned entry instruction"));
5591 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5592 fragP
->fr_subtype
= RELAX_ORG
;
5596 /* TC_FRAG_INIT hook */
5599 xtensa_frag_init (fragS
*frag
)
5601 xtensa_set_frag_assembly_state (frag
);
5606 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5612 /* Round up a section size to the appropriate boundary. */
5615 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5617 return size
; /* Byte alignment is fine. */
5622 md_pcrel_from (fixS
*fixP
)
5625 static xtensa_insnbuf insnbuf
= NULL
;
5626 static xtensa_insnbuf slotbuf
= NULL
;
5629 xtensa_opcode opcode
;
5632 xtensa_isa isa
= xtensa_default_isa
;
5633 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5634 bfd_boolean alt_reloc
;
5636 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5639 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5644 insnbuf
= xtensa_insnbuf_alloc (isa
);
5645 slotbuf
= xtensa_insnbuf_alloc (isa
);
5648 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5649 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5650 fmt
= xtensa_format_decode (isa
, insnbuf
);
5652 if (fmt
== XTENSA_UNDEFINED
)
5653 as_fatal (_("bad instruction format"));
5655 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5656 as_fatal (_("invalid relocation"));
5658 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5659 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5661 /* Check for "alternate" relocations (operand not specified). None
5662 of the current uses for these are really PC-relative. */
5663 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5665 if (opcode
!= xtensa_l32r_opcode
5666 && opcode
!= xtensa_const16_opcode
)
5667 as_fatal (_("invalid relocation for '%s' instruction"),
5668 xtensa_opcode_name (isa
, opcode
));
5672 opnum
= get_relaxable_immed (opcode
);
5674 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5675 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5677 as_bad_where (fixP
->fx_file
,
5679 _("invalid relocation for operand %d of '%s'"),
5680 opnum
, xtensa_opcode_name (isa
, opcode
));
5683 return 0 - opnd_value
;
5687 /* TC_FORCE_RELOCATION hook */
5690 xtensa_force_relocation (fixS
*fix
)
5692 switch (fix
->fx_r_type
)
5694 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5695 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5696 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5697 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5698 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5699 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5700 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5701 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5702 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5704 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5705 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5706 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5707 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5708 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5715 if (linkrelax
&& fix
->fx_addsy
5716 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5719 return generic_force_reloc (fix
);
5723 /* TC_VALIDATE_FIX_SUB hook */
5726 xtensa_validate_fix_sub (fixS
*fix
)
5728 segT add_symbol_segment
, sub_symbol_segment
;
5730 /* The difference of two symbols should be resolved by the assembler when
5731 linkrelax is not set. If the linker may relax the section containing
5732 the symbols, then an Xtensa DIFF relocation must be generated so that
5733 the linker knows to adjust the difference value. */
5734 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5737 /* Make sure both symbols are in the same segment, and that segment is
5738 "normal" and relaxable. If the segment is not "normal", then the
5739 fix is not valid. If the segment is not "relaxable", then the fix
5740 should have been handled earlier. */
5741 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5742 if (! SEG_NORMAL (add_symbol_segment
) ||
5743 ! relaxable_section (add_symbol_segment
))
5745 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5746 return (sub_symbol_segment
== add_symbol_segment
);
5750 /* NO_PSEUDO_DOT hook */
5752 /* This function has nothing to do with pseudo dots, but this is the
5753 nearest macro to where the check needs to take place. FIXME: This
5757 xtensa_check_inside_bundle (void)
5759 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5760 as_bad (_("directives are not valid inside bundles"));
5762 /* This function must always return FALSE because it is called via a
5763 macro that has nothing to do with bundling. */
5768 /* md_elf_section_change_hook */
5771 xtensa_elf_section_change_hook (void)
5773 /* Set up the assembly state. */
5774 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5775 xtensa_set_frag_assembly_state (frag_now
);
5779 /* tc_fix_adjustable hook */
5782 xtensa_fix_adjustable (fixS
*fixP
)
5784 /* We need the symbol name for the VTABLE entries. */
5785 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5786 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5793 /* tc_symbol_new_hook */
5795 symbolS
*expr_symbols
= NULL
;
5798 xtensa_symbol_new_hook (symbolS
*sym
)
5800 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5802 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5809 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5811 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5814 /* Subtracted symbols are only allowed for a few relocation types, and
5815 unless linkrelax is enabled, they should not make it to this point. */
5816 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5817 || fixP
->fx_r_type
== BFD_RELOC_16
5818 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5821 switch (fixP
->fx_r_type
)
5823 case BFD_RELOC_32_PCREL
:
5829 switch (fixP
->fx_r_type
)
5832 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5835 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5838 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5844 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5845 - S_GET_VALUE (fixP
->fx_subsy
));
5847 /* The difference value gets written out, and the DIFF reloc
5848 identifies the address of the subtracted symbol (i.e., the one
5849 with the lowest address). */
5851 fixP
->fx_offset
-= val
;
5852 fixP
->fx_subsy
= NULL
;
5854 else if (! fixP
->fx_addsy
)
5861 case BFD_RELOC_XTENSA_PLT
:
5862 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5863 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5866 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5867 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5868 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5869 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5870 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5871 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5872 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5875 case BFD_RELOC_XTENSA_SLOT0_OP
:
5876 case BFD_RELOC_XTENSA_SLOT1_OP
:
5877 case BFD_RELOC_XTENSA_SLOT2_OP
:
5878 case BFD_RELOC_XTENSA_SLOT3_OP
:
5879 case BFD_RELOC_XTENSA_SLOT4_OP
:
5880 case BFD_RELOC_XTENSA_SLOT5_OP
:
5881 case BFD_RELOC_XTENSA_SLOT6_OP
:
5882 case BFD_RELOC_XTENSA_SLOT7_OP
:
5883 case BFD_RELOC_XTENSA_SLOT8_OP
:
5884 case BFD_RELOC_XTENSA_SLOT9_OP
:
5885 case BFD_RELOC_XTENSA_SLOT10_OP
:
5886 case BFD_RELOC_XTENSA_SLOT11_OP
:
5887 case BFD_RELOC_XTENSA_SLOT12_OP
:
5888 case BFD_RELOC_XTENSA_SLOT13_OP
:
5889 case BFD_RELOC_XTENSA_SLOT14_OP
:
5892 /* Write the tentative value of a PC-relative relocation to a
5893 local symbol into the instruction. The value will be ignored
5894 by the linker, and it makes the object file disassembly
5895 readable when all branch targets are encoded in relocations. */
5897 gas_assert (fixP
->fx_addsy
);
5898 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5899 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5901 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5902 - md_pcrel_from (fixP
));
5903 (void) xg_apply_fix_value (fixP
, val
);
5906 else if (! fixP
->fx_addsy
)
5909 if (xg_apply_fix_value (fixP
, val
))
5914 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5915 case BFD_RELOC_XTENSA_TLS_FUNC
:
5916 case BFD_RELOC_XTENSA_TLS_ARG
:
5917 case BFD_RELOC_XTENSA_TLS_CALL
:
5918 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5919 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5920 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5921 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5922 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5923 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5924 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5925 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5926 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5927 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5928 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5929 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5930 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5931 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5932 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5933 /* These all need to be resolved at link-time. Do nothing now. */
5936 case BFD_RELOC_VTABLE_INHERIT
:
5937 case BFD_RELOC_VTABLE_ENTRY
:
5942 as_bad (_("unhandled local relocation fix %s"),
5943 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5949 md_atof (int type
, char *litP
, int *sizeP
)
5951 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5956 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5958 return total_frag_text_expansion (fragP
);
5962 /* Translate internal representation of relocation info to BFD target
5966 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5970 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5971 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5972 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5973 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5975 /* Make sure none of our internal relocations make it this far.
5976 They'd better have been fully resolved by this point. */
5977 gas_assert ((int) fixp
->fx_r_type
> 0);
5979 reloc
->addend
= fixp
->fx_offset
;
5981 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5982 if (reloc
->howto
== NULL
)
5984 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5985 _("cannot represent `%s' relocation in object file"),
5986 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5987 free (reloc
->sym_ptr_ptr
);
5992 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5993 as_fatal (_("internal error; cannot generate `%s' relocation"),
5994 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6000 /* Checks for resource conflicts between instructions. */
6002 /* The func unit stuff could be implemented as bit-vectors rather
6003 than the iterative approach here. If it ends up being too
6004 slow, we will switch it. */
6007 new_resource_table (void *data
,
6010 unit_num_copies_func uncf
,
6011 opcode_num_units_func onuf
,
6012 opcode_funcUnit_use_unit_func ouuf
,
6013 opcode_funcUnit_use_stage_func ousf
)
6016 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6018 rt
->cycles
= cycles
;
6019 rt
->allocated_cycles
= cycles
;
6021 rt
->unit_num_copies
= uncf
;
6022 rt
->opcode_num_units
= onuf
;
6023 rt
->opcode_unit_use
= ouuf
;
6024 rt
->opcode_unit_stage
= ousf
;
6026 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6027 for (i
= 0; i
< cycles
; i
++)
6028 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6035 clear_resource_table (resource_table
*rt
)
6038 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6039 for (j
= 0; j
< rt
->num_units
; j
++)
6040 rt
->units
[i
][j
] = 0;
6044 /* We never shrink it, just fake it into thinking so. */
6047 resize_resource_table (resource_table
*rt
, int cycles
)
6051 rt
->cycles
= cycles
;
6052 if (cycles
<= rt
->allocated_cycles
)
6055 old_cycles
= rt
->allocated_cycles
;
6056 rt
->allocated_cycles
= cycles
;
6058 rt
->units
= xrealloc (rt
->units
,
6059 rt
->allocated_cycles
* sizeof (unsigned char *));
6060 for (i
= 0; i
< old_cycles
; i
++)
6061 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6062 rt
->num_units
* sizeof (unsigned char));
6063 for (i
= old_cycles
; i
< cycles
; i
++)
6064 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6069 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6072 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6074 for (i
= 0; i
< uses
; i
++)
6076 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6077 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6078 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6079 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6080 if (copies_in_use
>= copies
)
6088 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6091 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6093 for (i
= 0; i
< uses
; i
++)
6095 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6096 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6097 /* Note that this allows resources to be oversubscribed. That's
6098 essential to the way the optional scheduler works.
6099 resources_available reports when a resource is over-subscribed,
6100 so it's easy to tell. */
6101 rt
->units
[stage
+ cycle
][unit
]++;
6107 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6110 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6112 for (i
= 0; i
< uses
; i
++)
6114 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6115 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6116 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6117 rt
->units
[stage
+ cycle
][unit
]--;
6122 /* Wrapper functions make parameterized resource reservation
6126 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6128 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6134 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6136 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6141 /* Note that this function does not check issue constraints, but
6142 solely whether the hardware is available to execute the given
6143 instructions together. It also doesn't check if the tinsns
6144 write the same state, or access the same tieports. That is
6145 checked by check_t1_t2_reads_and_writes. */
6148 resources_conflict (vliw_insn
*vinsn
)
6151 static resource_table
*rt
= NULL
;
6153 /* This is the most common case by far. Optimize it. */
6154 if (vinsn
->num_slots
== 1)
6159 xtensa_isa isa
= xtensa_default_isa
;
6160 rt
= new_resource_table
6161 (isa
, xtensa_num_pipe_stages
,
6162 xtensa_isa_num_funcUnits (isa
),
6163 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6164 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6165 opcode_funcUnit_use_unit
,
6166 opcode_funcUnit_use_stage
);
6169 clear_resource_table (rt
);
6171 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6173 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6175 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6182 /* finish_vinsn, emit_single_op and helper functions. */
6184 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6185 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6186 static void xg_assemble_vliw_tokens (vliw_insn
*);
6189 /* We have reached the end of a bundle; emit into the frag. */
6192 finish_vinsn (vliw_insn
*vinsn
)
6199 if (find_vinsn_conflicts (vinsn
))
6201 xg_clear_vinsn (vinsn
);
6205 /* First, find a format that works. */
6206 if (vinsn
->format
== XTENSA_UNDEFINED
)
6207 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6209 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6210 && produce_flix
== FLIX_NONE
)
6212 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6213 xg_clear_vinsn (vinsn
);
6217 if (vinsn
->format
== XTENSA_UNDEFINED
)
6219 as_where (&file_name
, &line
);
6220 as_bad_where (file_name
, line
,
6221 _("couldn't find a valid instruction format"));
6222 fprintf (stderr
, _(" ops were: "));
6223 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6224 fprintf (stderr
, _(" %s;"),
6225 xtensa_opcode_name (xtensa_default_isa
,
6226 vinsn
->slots
[i
].opcode
));
6227 fprintf (stderr
, _("\n"));
6228 xg_clear_vinsn (vinsn
);
6232 if (vinsn
->num_slots
6233 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6235 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6236 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6237 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6239 xg_clear_vinsn (vinsn
);
6243 if (resources_conflict (vinsn
))
6245 as_where (&file_name
, &line
);
6246 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6247 fprintf (stderr
, " ops were: ");
6248 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6249 fprintf (stderr
, " %s;",
6250 xtensa_opcode_name (xtensa_default_isa
,
6251 vinsn
->slots
[i
].opcode
));
6252 fprintf (stderr
, "\n");
6253 xg_clear_vinsn (vinsn
);
6257 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6259 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6261 symbolS
*lit_sym
= NULL
;
6263 bfd_boolean e
= FALSE
;
6264 bfd_boolean saved_density
= density_supported
;
6266 /* We don't want to narrow ops inside multi-slot bundles. */
6267 if (vinsn
->num_slots
> 1)
6268 density_supported
= FALSE
;
6270 istack_init (&slotstack
);
6271 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6273 vinsn
->slots
[i
].opcode
=
6274 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6276 vinsn
->slots
[i
].ntok
= 0;
6279 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6285 density_supported
= saved_density
;
6289 xg_clear_vinsn (vinsn
);
6293 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6295 TInsn
*insn
= &slotstack
.insn
[j
];
6296 if (insn
->insn_type
== ITYPE_LITERAL
)
6298 gas_assert (lit_sym
== NULL
);
6299 lit_sym
= xg_assemble_literal (insn
);
6303 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6305 xg_resolve_literals (insn
, lit_sym
);
6306 if (j
!= slotstack
.ninsn
- 1)
6307 emit_single_op (insn
);
6311 if (vinsn
->num_slots
> 1)
6313 if (opcode_fits_format_slot
6314 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6317 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6321 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6322 if (vinsn
->format
== XTENSA_UNDEFINED
)
6323 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6325 vinsn
->slots
[i
].opcode
6326 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6329 vinsn
->slots
[i
].ntok
= 0;
6334 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6335 vinsn
->format
= XTENSA_UNDEFINED
;
6340 /* Now check resource conflicts on the modified bundle. */
6341 if (resources_conflict (vinsn
))
6343 as_where (&file_name
, &line
);
6344 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6345 fprintf (stderr
, " ops were: ");
6346 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6347 fprintf (stderr
, " %s;",
6348 xtensa_opcode_name (xtensa_default_isa
,
6349 vinsn
->slots
[i
].opcode
));
6350 fprintf (stderr
, "\n");
6351 xg_clear_vinsn (vinsn
);
6355 /* First, find a format that works. */
6356 if (vinsn
->format
== XTENSA_UNDEFINED
)
6357 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6359 xg_assemble_vliw_tokens (vinsn
);
6361 xg_clear_vinsn (vinsn
);
6365 /* Given an vliw instruction, what conflicts are there in register
6366 usage and in writes to states and queues?
6368 This function does two things:
6369 1. Reports an error when a vinsn contains illegal combinations
6370 of writes to registers states or queues.
6371 2. Marks individual tinsns as not relaxable if the combination
6372 contains antidependencies.
6374 Job 2 handles things like swap semantics in instructions that need
6375 to be relaxed. For example,
6379 normally would be relaxed to
6384 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6386 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6388 then we can't relax it into
6391 { add a0, a1, a0 ; add a2, a0, a4 ; }
6393 because the value of a0 is trashed before the second add can read it. */
6395 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6398 find_vinsn_conflicts (vliw_insn
*vinsn
)
6402 xtensa_isa isa
= xtensa_default_isa
;
6404 gas_assert (!past_xtensa_end
);
6406 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6408 TInsn
*op1
= &vinsn
->slots
[i
];
6409 if (op1
->is_specific_opcode
)
6410 op1
->keep_wide
= TRUE
;
6412 op1
->keep_wide
= FALSE
;
6415 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6417 TInsn
*op1
= &vinsn
->slots
[i
];
6419 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6422 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6426 TInsn
*op2
= &vinsn
->slots
[j
];
6427 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6428 switch (conflict_type
)
6431 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6432 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6433 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6436 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6437 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6438 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6441 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6442 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6443 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6446 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6447 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6448 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6451 /* Everything is OK. */
6454 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6455 || conflict_type
== 'a');
6462 as_bad (_("multiple branches or jumps in the same bundle"));
6470 /* Check how the state used by t1 and t2 relate.
6473 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6474 case B: no relationship between what is read and written (both could
6475 read the same reg though)
6476 case C: t1 writes a register t2 writes (a register conflict within a
6478 case D: t1 writes a state that t2 also writes
6479 case E: t1 writes a tie queue that t2 also writes
6480 case F: two volatile queue accesses
6484 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6486 xtensa_isa isa
= xtensa_default_isa
;
6487 xtensa_regfile t1_regfile
, t2_regfile
;
6489 int t1_base_reg
, t1_last_reg
;
6490 int t2_base_reg
, t2_last_reg
;
6491 char t1_inout
, t2_inout
;
6493 char conflict
= 'b';
6498 bfd_boolean t1_volatile
= FALSE
;
6499 bfd_boolean t2_volatile
= FALSE
;
6501 /* Check registers. */
6502 for (j
= 0; j
< t2
->ntok
; j
++)
6504 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6507 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6508 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6509 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6511 for (i
= 0; i
< t1
->ntok
; i
++)
6513 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6516 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6518 if (t1_regfile
!= t2_regfile
)
6521 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6522 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6524 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6525 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6527 if (t1_inout
== 'm' || t1_inout
== 'o'
6528 || t2_inout
== 'm' || t2_inout
== 'o')
6535 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6536 t1_last_reg
= (t1_base_reg
6537 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6539 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6541 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6543 if (t1_reg
!= t2_reg
)
6546 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6552 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6558 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6566 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6567 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6568 for (j
= 0; j
< t2_states
; j
++)
6570 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6571 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6572 for (i
= 0; i
< t1_states
; i
++)
6574 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6575 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6576 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6579 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6585 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6591 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6596 /* Check tieports. */
6597 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6598 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6599 for (j
= 0; j
< t2_interfaces
; j
++)
6601 xtensa_interface t2_int
6602 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6603 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6605 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6606 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6609 for (i
= 0; i
< t1_interfaces
; i
++)
6611 xtensa_interface t1_int
6612 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6613 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6615 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6616 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6619 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6622 if (t1_int
!= t2_int
)
6625 if (t2_inout
== 'i' && t1_inout
== 'o')
6631 if (t1_inout
== 'i' && t2_inout
== 'o')
6637 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6646 static xtensa_format
6647 xg_find_narrowest_format (vliw_insn
*vinsn
)
6649 /* Right now we assume that the ops within the vinsn are properly
6650 ordered for the slots that the programmer wanted them in. In
6651 other words, we don't rearrange the ops in hopes of finding a
6652 better format. The scheduler handles that. */
6654 xtensa_isa isa
= xtensa_default_isa
;
6655 xtensa_format format
;
6656 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6658 if (vinsn
->num_slots
== 1)
6659 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6661 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6664 xg_copy_vinsn (&v_copy
, vinsn
);
6665 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6669 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6671 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6673 v_copy
.slots
[slot
].opcode
=
6674 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6675 v_copy
.slots
[slot
].ntok
= 0;
6678 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6681 else if (v_copy
.num_slots
> 1)
6684 /* Try the widened version. */
6685 if (!v_copy
.slots
[slot
].keep_wide
6686 && !v_copy
.slots
[slot
].is_specific_opcode
6687 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6689 && opcode_fits_format_slot (widened
.opcode
,
6692 v_copy
.slots
[slot
] = widened
;
6697 if (fit
== v_copy
.num_slots
)
6699 xg_copy_vinsn (vinsn
, &v_copy
);
6700 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6701 vinsn
->format
= format
;
6707 if (format
== xtensa_isa_num_formats (isa
))
6708 return XTENSA_UNDEFINED
;
6714 /* Return the additional space needed in a frag
6715 for possible relaxations of any ops in a VLIW insn.
6716 Also fill out the relaxations that might be required of
6717 each tinsn in the vinsn. */
6720 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6722 bfd_boolean finish_frag
= FALSE
;
6723 int extra_space
= 0;
6726 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6728 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6729 if (!tinsn_has_symbolic_operands (tinsn
))
6731 /* A narrow instruction could be widened later to help
6732 alignment issues. */
6733 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6734 && !tinsn
->is_specific_opcode
6735 && vinsn
->num_slots
== 1)
6737 /* Difference in bytes between narrow and wide insns... */
6739 tinsn
->subtype
= RELAX_NARROW
;
6744 if (workaround_b_j_loop_end
6745 && tinsn
->opcode
== xtensa_jx_opcode
6746 && use_transform ())
6748 /* Add 2 of these. */
6749 extra_space
+= 3; /* for the nop size */
6750 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6753 /* Need to assemble it with space for the relocation. */
6754 if (xg_is_relaxable_insn (tinsn
, 0)
6755 && !tinsn
->is_specific_opcode
)
6757 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6758 int max_literal_size
=
6759 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6761 tinsn
->literal_space
= max_literal_size
;
6763 tinsn
->subtype
= RELAX_IMMED
;
6764 extra_space
+= max_size
;
6768 /* A fix record will be added for this instruction prior
6769 to relaxation, so make it end the frag. */
6774 *pfinish_frag
= finish_frag
;
6780 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6782 xtensa_isa isa
= xtensa_default_isa
;
6783 int slot
, chosen_slot
;
6785 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6786 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6787 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6789 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6790 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6792 if (slot
== chosen_slot
)
6793 vinsn
->slots
[slot
] = *tinsn
;
6796 vinsn
->slots
[slot
].opcode
=
6797 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6798 vinsn
->slots
[slot
].ntok
= 0;
6799 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6806 emit_single_op (TInsn
*orig_insn
)
6809 IStack istack
; /* put instructions into here */
6810 symbolS
*lit_sym
= NULL
;
6811 symbolS
*label_sym
= NULL
;
6813 istack_init (&istack
);
6815 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6816 Because the scheduling and bundling characteristics of movi and
6817 l32r or const16 are so different, we can do much better if we relax
6818 it prior to scheduling and bundling, rather than after. */
6819 if ((orig_insn
->opcode
== xtensa_movi_opcode
6820 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6821 && !cur_vinsn
.inside_bundle
6822 && (orig_insn
->tok
[1].X_op
== O_symbol
6823 || orig_insn
->tok
[1].X_op
== O_pltrel
6824 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6825 || orig_insn
->tok
[1].X_op
== O_tlsarg
6826 || orig_insn
->tok
[1].X_op
== O_tpoff
6827 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6828 && !orig_insn
->is_specific_opcode
&& use_transform ())
6829 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6831 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6834 for (i
= 0; i
< istack
.ninsn
; i
++)
6836 TInsn
*insn
= &istack
.insn
[i
];
6837 switch (insn
->insn_type
)
6840 gas_assert (lit_sym
== NULL
);
6841 lit_sym
= xg_assemble_literal (insn
);
6845 static int relaxed_sym_idx
= 0;
6846 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6847 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6849 gas_assert (label_sym
== NULL
);
6850 label_sym
= symbol_find_or_make (label
);
6851 gas_assert (label_sym
);
6859 xg_resolve_literals (insn
, lit_sym
);
6861 xg_resolve_labels (insn
, label_sym
);
6863 bundle_tinsn (insn
, &v
);
6878 total_frag_text_expansion (fragS
*fragP
)
6881 int total_expansion
= 0;
6883 for (slot
= 0; slot
< config_max_slots
; slot
++)
6884 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6886 return total_expansion
;
6890 /* Emit a vliw instruction to the current fragment. */
6893 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6895 bfd_boolean finish_frag
;
6896 bfd_boolean is_jump
= FALSE
;
6897 bfd_boolean is_branch
= FALSE
;
6898 xtensa_isa isa
= xtensa_default_isa
;
6903 struct dwarf2_line_info debug_line
;
6904 bfd_boolean loc_directive_seen
= FALSE
;
6907 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6909 if (generating_literals
)
6911 static int reported
= 0;
6913 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6914 _("cannot assemble into a literal fragment"));
6921 if (frag_now_fix () != 0
6922 && (! frag_now
->tc_frag_data
.is_insn
6923 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6924 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6925 || (directive_state
[directive_longcalls
]
6926 != frag_now
->tc_frag_data
.use_longcalls
)
6927 || (directive_state
[directive_absolute_literals
]
6928 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6930 frag_wane (frag_now
);
6932 xtensa_set_frag_assembly_state (frag_now
);
6935 if (workaround_a0_b_retw
6936 && vinsn
->num_slots
== 1
6937 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6938 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6939 && use_transform ())
6941 has_a0_b_retw
= TRUE
;
6943 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6944 After the first assembly pass we will check all of them and
6945 add a nop if needed. */
6946 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6947 frag_var (rs_machine_dependent
, 4, 4,
6948 RELAX_ADD_NOP_IF_A0_B_RETW
,
6949 frag_now
->fr_symbol
,
6950 frag_now
->fr_offset
,
6952 xtensa_set_frag_assembly_state (frag_now
);
6953 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6954 frag_var (rs_machine_dependent
, 4, 4,
6955 RELAX_ADD_NOP_IF_A0_B_RETW
,
6956 frag_now
->fr_symbol
,
6957 frag_now
->fr_offset
,
6959 xtensa_set_frag_assembly_state (frag_now
);
6962 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6964 tinsn
= &vinsn
->slots
[slot
];
6966 /* See if the instruction implies an aligned section. */
6967 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6968 record_alignment (now_seg
, 2);
6970 /* Determine the best line number for debug info. */
6971 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6972 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6973 || tinsn
->debug_line
.line
< debug_line
.line
6974 || tinsn
->debug_line
.column
< debug_line
.column
))
6975 debug_line
= tinsn
->debug_line
;
6976 if (tinsn
->loc_directive_seen
)
6977 loc_directive_seen
= TRUE
;
6980 /* Special cases for instructions that force an alignment... */
6981 /* None of these opcodes are bundle-able. */
6982 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6986 /* Remember the symbol that marks the end of the loop in the frag
6987 that marks the start of the loop. This way we can easily find
6988 the end of the loop at the beginning, without adding special code
6989 to mark the loop instructions themselves. */
6990 symbolS
*target_sym
= NULL
;
6991 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6992 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6994 xtensa_set_frag_assembly_state (frag_now
);
6995 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6997 max_fill
= get_text_align_max_fill_size
6998 (get_text_align_power (xtensa_fetch_width
),
6999 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7001 if (use_transform ())
7002 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7003 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7005 frag_var (rs_machine_dependent
, 0, 0,
7006 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7007 xtensa_set_frag_assembly_state (frag_now
);
7010 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7011 && !vinsn
->slots
[0].is_specific_opcode
)
7013 xtensa_mark_literal_pool_location ();
7014 xtensa_move_labels (frag_now
, 0);
7015 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7018 if (vinsn
->num_slots
== 1)
7020 if (workaround_a0_b_retw
&& use_transform ())
7021 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7022 is_register_writer (&vinsn
->slots
[0], "a", 0));
7024 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7025 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7028 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7030 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7032 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7034 /* vinsn_to_insnbuf will produce the error. */
7035 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7037 f
= frag_more (insn_size
+ extra_space
);
7038 xtensa_set_frag_assembly_state (frag_now
);
7039 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7042 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7043 if (vinsn
->format
== XTENSA_UNDEFINED
)
7046 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7048 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7049 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7052 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7054 tinsn
= &vinsn
->slots
[slot
];
7055 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7056 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7057 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7058 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7059 if (tinsn
->literal_space
!= 0)
7060 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7061 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7063 if (tinsn
->subtype
== RELAX_NARROW
)
7064 gas_assert (vinsn
->num_slots
== 1);
7065 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7067 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7070 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7071 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7075 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7076 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7080 frag_variant (rs_machine_dependent
,
7081 extra_space
, extra_space
, RELAX_SLOTS
,
7082 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7083 xtensa_set_frag_assembly_state (frag_now
);
7086 /* Special cases for loops:
7087 close_loop_end should be inserted AFTER short_loop.
7088 Make sure that CLOSE loops are processed BEFORE short_loops
7089 when converting them. */
7091 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7092 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7093 && !vinsn
->slots
[0].is_specific_opcode
)
7095 if (workaround_short_loop
&& use_transform ())
7097 maybe_has_short_loop
= TRUE
;
7098 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7099 frag_var (rs_machine_dependent
, 4, 4,
7100 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7101 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7102 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7103 frag_var (rs_machine_dependent
, 4, 4,
7104 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7105 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7108 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7109 loop at least 12 bytes away from another loop's end. */
7110 if (workaround_close_loop_end
&& use_transform ())
7112 maybe_has_close_loop_end
= TRUE
;
7113 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7114 frag_var (rs_machine_dependent
, 12, 12,
7115 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7116 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7120 if (use_transform ())
7124 gas_assert (finish_frag
);
7125 frag_var (rs_machine_dependent
,
7126 xtensa_fetch_width
, xtensa_fetch_width
,
7128 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7129 xtensa_set_frag_assembly_state (frag_now
);
7131 else if (is_branch
&& do_align_targets ())
7133 gas_assert (finish_frag
);
7134 frag_var (rs_machine_dependent
,
7135 xtensa_fetch_width
, xtensa_fetch_width
,
7136 RELAX_MAYBE_UNREACHABLE
,
7137 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7138 xtensa_set_frag_assembly_state (frag_now
);
7139 frag_var (rs_machine_dependent
,
7141 RELAX_MAYBE_DESIRE_ALIGN
,
7142 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7143 xtensa_set_frag_assembly_state (frag_now
);
7147 /* Now, if the original opcode was a call... */
7148 if (do_align_targets ()
7149 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7151 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7152 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7153 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7154 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7155 xtensa_set_frag_assembly_state (frag_now
);
7158 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7160 frag_wane (frag_now
);
7162 xtensa_set_frag_assembly_state (frag_now
);
7167 /* xtensa_end and helper functions. */
7169 static void xtensa_cleanup_align_frags (void);
7170 static void xtensa_fix_target_frags (void);
7171 static void xtensa_mark_narrow_branches (void);
7172 static void xtensa_mark_zcl_first_insns (void);
7173 static void xtensa_mark_difference_of_two_symbols (void);
7174 static void xtensa_fix_a0_b_retw_frags (void);
7175 static void xtensa_fix_b_j_loop_end_frags (void);
7176 static void xtensa_fix_close_loop_end_frags (void);
7177 static void xtensa_fix_short_loop_frags (void);
7178 static void xtensa_sanity_check (void);
7179 static void xtensa_add_config_info (void);
7184 directive_balance ();
7185 xtensa_flush_pending_output ();
7187 past_xtensa_end
= TRUE
;
7189 xtensa_move_literals ();
7191 xtensa_reorder_segments ();
7192 xtensa_cleanup_align_frags ();
7193 xtensa_fix_target_frags ();
7194 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7195 xtensa_fix_a0_b_retw_frags ();
7196 if (workaround_b_j_loop_end
)
7197 xtensa_fix_b_j_loop_end_frags ();
7199 /* "close_loop_end" should be processed BEFORE "short_loop". */
7200 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7201 xtensa_fix_close_loop_end_frags ();
7203 if (workaround_short_loop
&& maybe_has_short_loop
)
7204 xtensa_fix_short_loop_frags ();
7206 xtensa_mark_narrow_branches ();
7207 xtensa_mark_zcl_first_insns ();
7209 xtensa_sanity_check ();
7211 xtensa_add_config_info ();
7216 xtensa_cleanup_align_frags (void)
7221 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7222 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7225 /* Walk over all of the fragments in a subsection. */
7226 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7228 if ((fragP
->fr_type
== rs_align
7229 || fragP
->fr_type
== rs_align_code
7230 || (fragP
->fr_type
== rs_machine_dependent
7231 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7232 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7233 && fragP
->fr_fix
== 0)
7235 fragS
*next
= fragP
->fr_next
;
7238 && next
->fr_fix
== 0
7239 && next
->fr_type
== rs_machine_dependent
7240 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7243 next
= next
->fr_next
;
7246 /* If we don't widen branch targets, then they
7247 will be easier to align. */
7248 if (fragP
->tc_frag_data
.is_branch_target
7249 && fragP
->fr_opcode
== fragP
->fr_literal
7250 && fragP
->fr_type
== rs_machine_dependent
7251 && fragP
->fr_subtype
== RELAX_SLOTS
7252 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7254 if (fragP
->fr_type
== rs_machine_dependent
7255 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7256 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7262 /* Re-process all of the fragments looking to convert all of the
7263 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7264 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7265 Otherwise, convert to a .fill 0. */
7268 xtensa_fix_target_frags (void)
7273 /* When this routine is called, all of the subsections are still intact
7274 so we walk over subsections instead of sections. */
7275 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7276 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7280 /* Walk over all of the fragments in a subsection. */
7281 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7283 if (fragP
->fr_type
== rs_machine_dependent
7284 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7286 if (next_frag_is_branch_target (fragP
))
7287 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7296 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7299 xtensa_mark_narrow_branches (void)
7304 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7305 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7308 /* Walk over all of the fragments in a subsection. */
7309 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7311 if (fragP
->fr_type
== rs_machine_dependent
7312 && fragP
->fr_subtype
== RELAX_SLOTS
7313 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7317 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7318 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7320 if (vinsn
.num_slots
== 1
7321 && xtensa_opcode_is_branch (xtensa_default_isa
,
7322 vinsn
.slots
[0].opcode
) == 1
7323 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7324 && is_narrow_branch_guaranteed_in_range (fragP
,
7327 fragP
->fr_subtype
= RELAX_SLOTS
;
7328 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7329 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7337 /* A branch is typically widened only when its target is out of
7338 range. However, we would like to widen them to align a subsequent
7339 branch target when possible.
7341 Because the branch relaxation code is so convoluted, the optimal solution
7342 (combining the two cases) is difficult to get right in all circumstances.
7343 We therefore go with an "almost as good" solution, where we only
7344 use for alignment narrow branches that definitely will not expand to a
7345 jump and a branch. These functions find and mark these cases. */
7347 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7348 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7349 We start counting beginning with the frag after the 2-byte branch, so the
7350 maximum offset is (4 - 2) + 63 = 65. */
7351 #define MAX_IMMED6 65
7353 static offsetT
unrelaxed_frag_max_size (fragS
*);
7356 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7358 const expressionS
*exp
= &tinsn
->tok
[1];
7359 symbolS
*symbolP
= exp
->X_add_symbol
;
7360 offsetT max_distance
= exp
->X_add_number
;
7363 if (exp
->X_op
!= O_symbol
)
7366 target_frag
= symbol_get_frag (symbolP
);
7368 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7369 if (is_branch_jmp_to_next (tinsn
, fragP
))
7372 /* The branch doesn't branch over it's own frag,
7373 but over the subsequent ones. */
7374 fragP
= fragP
->fr_next
;
7375 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7377 max_distance
+= unrelaxed_frag_max_size (fragP
);
7378 fragP
= fragP
->fr_next
;
7380 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7387 xtensa_mark_zcl_first_insns (void)
7392 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7393 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7396 /* Walk over all of the fragments in a subsection. */
7397 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7399 if (fragP
->fr_type
== rs_machine_dependent
7400 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7401 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7403 /* Find the loop frag. */
7404 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7405 /* Find the first insn frag. */
7406 targ_frag
= next_non_empty_frag (targ_frag
);
7408 /* Of course, sometimes (mostly for toy test cases) a
7409 zero-cost loop instruction is the last in a section. */
7412 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7413 /* Do not widen a frag that is the first instruction of a
7414 zero-cost loop. It makes that loop harder to align. */
7415 if (targ_frag
->fr_type
== rs_machine_dependent
7416 && targ_frag
->fr_subtype
== RELAX_SLOTS
7417 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7420 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7421 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7424 frag_wane (targ_frag
);
7425 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7429 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7437 /* When a difference-of-symbols expression is encoded as a uleb128 or
7438 sleb128 value, the linker is unable to adjust that value to account for
7439 link-time relaxation. Mark all the code between such symbols so that
7440 its size cannot be changed by linker relaxation. */
7443 xtensa_mark_difference_of_two_symbols (void)
7447 for (expr_sym
= expr_symbols
; expr_sym
;
7448 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7450 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7452 if (exp
->X_op
== O_subtract
)
7454 symbolS
*left
= exp
->X_add_symbol
;
7455 symbolS
*right
= exp
->X_op_symbol
;
7457 /* Difference of two symbols not in the same section
7458 are handled with relocations in the linker. */
7459 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7465 if (symbol_get_frag (left
)->fr_address
7466 <= symbol_get_frag (right
)->fr_address
)
7468 start
= symbol_get_frag (left
);
7469 end
= symbol_get_frag (right
);
7473 start
= symbol_get_frag (right
);
7474 end
= symbol_get_frag (left
);
7477 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7478 walk
= start
->tc_frag_data
.no_transform_end
;
7483 walk
->tc_frag_data
.is_no_transform
= 1;
7484 walk
= walk
->fr_next
;
7486 while (walk
&& walk
->fr_address
< end
->fr_address
);
7488 start
->tc_frag_data
.no_transform_end
= walk
;
7495 /* Re-process all of the fragments looking to convert all of the
7496 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7497 conditional branch or a retw/retw.n, convert this frag to one that
7498 will generate a NOP. In any case close it off with a .fill 0. */
7500 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7503 xtensa_fix_a0_b_retw_frags (void)
7508 /* When this routine is called, all of the subsections are still intact
7509 so we walk over subsections instead of sections. */
7510 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7511 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7515 /* Walk over all of the fragments in a subsection. */
7516 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7518 if (fragP
->fr_type
== rs_machine_dependent
7519 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7521 if (next_instrs_are_b_retw (fragP
))
7523 if (fragP
->tc_frag_data
.is_no_transform
)
7524 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7526 relax_frag_add_nop (fragP
);
7536 next_instrs_are_b_retw (fragS
*fragP
)
7538 xtensa_opcode opcode
;
7540 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7541 static xtensa_insnbuf insnbuf
= NULL
;
7542 static xtensa_insnbuf slotbuf
= NULL
;
7543 xtensa_isa isa
= xtensa_default_isa
;
7546 bfd_boolean branch_seen
= FALSE
;
7550 insnbuf
= xtensa_insnbuf_alloc (isa
);
7551 slotbuf
= xtensa_insnbuf_alloc (isa
);
7554 if (next_fragP
== NULL
)
7557 /* Check for the conditional branch. */
7558 xtensa_insnbuf_from_chars
7559 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7560 fmt
= xtensa_format_decode (isa
, insnbuf
);
7561 if (fmt
== XTENSA_UNDEFINED
)
7564 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7566 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7567 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7569 branch_seen
= (branch_seen
7570 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7576 offset
+= xtensa_format_length (isa
, fmt
);
7577 if (offset
== next_fragP
->fr_fix
)
7579 next_fragP
= next_non_empty_frag (next_fragP
);
7583 if (next_fragP
== NULL
)
7586 /* Check for the retw/retw.n. */
7587 xtensa_insnbuf_from_chars
7588 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7589 fmt
= xtensa_format_decode (isa
, insnbuf
);
7591 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7592 have no problems. */
7593 if (fmt
== XTENSA_UNDEFINED
7594 || xtensa_format_num_slots (isa
, fmt
) != 1)
7597 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7598 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7600 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7607 /* Re-process all of the fragments looking to convert all of the
7608 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7609 loop end label, convert this frag to one that will generate a NOP.
7610 In any case close it off with a .fill 0. */
7612 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7615 xtensa_fix_b_j_loop_end_frags (void)
7620 /* When this routine is called, all of the subsections are still intact
7621 so we walk over subsections instead of sections. */
7622 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7623 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7627 /* Walk over all of the fragments in a subsection. */
7628 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7630 if (fragP
->fr_type
== rs_machine_dependent
7631 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7633 if (next_instr_is_loop_end (fragP
))
7635 if (fragP
->tc_frag_data
.is_no_transform
)
7636 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7638 relax_frag_add_nop (fragP
);
7648 next_instr_is_loop_end (fragS
*fragP
)
7650 const fragS
*next_fragP
;
7652 if (next_frag_is_loop_target (fragP
))
7655 next_fragP
= next_non_empty_frag (fragP
);
7656 if (next_fragP
== NULL
)
7659 if (!next_frag_is_loop_target (next_fragP
))
7662 /* If the size is >= 3 then there is more than one instruction here.
7663 The hardware bug will not fire. */
7664 if (next_fragP
->fr_fix
> 3)
7671 /* Re-process all of the fragments looking to convert all of the
7672 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7673 not MY loop's loop end within 12 bytes, add enough nops here to
7674 make it at least 12 bytes away. In any case close it off with a
7677 static offsetT min_bytes_to_other_loop_end
7678 (fragS
*, fragS
*, offsetT
);
7681 xtensa_fix_close_loop_end_frags (void)
7686 /* When this routine is called, all of the subsections are still intact
7687 so we walk over subsections instead of sections. */
7688 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7689 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7693 fragS
*current_target
= NULL
;
7695 /* Walk over all of the fragments in a subsection. */
7696 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7698 if (fragP
->fr_type
== rs_machine_dependent
7699 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7700 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7701 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7704 && fragP
->fr_type
== rs_machine_dependent
7705 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7708 int bytes_added
= 0;
7710 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7711 /* Max out at 12. */
7712 min_bytes
= min_bytes_to_other_loop_end
7713 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7715 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7717 if (fragP
->tc_frag_data
.is_no_transform
)
7718 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7721 while (min_bytes
+ bytes_added
7722 < REQUIRED_LOOP_DIVIDING_BYTES
)
7726 if (fragP
->fr_var
< length
)
7727 as_fatal (_("fr_var %lu < length %d"),
7728 (long) fragP
->fr_var
, length
);
7731 assemble_nop (length
,
7732 fragP
->fr_literal
+ fragP
->fr_fix
);
7733 fragP
->fr_fix
+= length
;
7734 fragP
->fr_var
-= length
;
7736 bytes_added
+= length
;
7742 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7743 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7749 static offsetT
unrelaxed_frag_min_size (fragS
*);
7752 min_bytes_to_other_loop_end (fragS
*fragP
,
7753 fragS
*current_target
,
7757 fragS
*current_fragP
;
7759 for (current_fragP
= fragP
;
7761 current_fragP
= current_fragP
->fr_next
)
7763 if (current_fragP
->tc_frag_data
.is_loop_target
7764 && current_fragP
!= current_target
)
7767 offset
+= unrelaxed_frag_min_size (current_fragP
);
7769 if (offset
>= max_size
)
7777 unrelaxed_frag_min_size (fragS
*fragP
)
7779 offsetT size
= fragP
->fr_fix
;
7781 /* Add fill size. */
7782 if (fragP
->fr_type
== rs_fill
)
7783 size
+= fragP
->fr_offset
;
7790 unrelaxed_frag_max_size (fragS
*fragP
)
7792 offsetT size
= fragP
->fr_fix
;
7793 switch (fragP
->fr_type
)
7796 /* Empty frags created by the obstack allocation scheme
7797 end up with type 0. */
7802 size
+= fragP
->fr_offset
;
7810 /* No further adjustments needed. */
7812 case rs_machine_dependent
:
7813 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7814 size
+= fragP
->fr_var
;
7817 /* We had darn well better know how big it is. */
7826 /* Re-process all of the fragments looking to convert all
7827 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7830 1) the instruction size count to the loop end label
7831 is too short (<= 2 instructions),
7832 2) loop has a jump or branch in it
7835 1) workaround_all_short_loops is TRUE
7836 2) The generating loop was a 'loopgtz' or 'loopnez'
7837 3) the instruction size count to the loop end label is too short
7839 then convert this frag (and maybe the next one) to generate a NOP.
7840 In any case close it off with a .fill 0. */
7842 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7843 static bfd_boolean
branch_before_loop_end (fragS
*);
7846 xtensa_fix_short_loop_frags (void)
7851 /* When this routine is called, all of the subsections are still intact
7852 so we walk over subsections instead of sections. */
7853 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7854 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7857 fragS
*current_target
= NULL
;
7858 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7860 /* Walk over all of the fragments in a subsection. */
7861 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7863 if (fragP
->fr_type
== rs_machine_dependent
7864 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7865 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7868 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7869 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7870 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7871 current_opcode
= t_insn
.opcode
;
7872 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7873 current_opcode
) == 1);
7876 if (fragP
->fr_type
== rs_machine_dependent
7877 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7879 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7880 && (branch_before_loop_end (fragP
->fr_next
)
7881 || (workaround_all_short_loops
7882 && current_opcode
!= XTENSA_UNDEFINED
7883 && current_opcode
!= xtensa_loop_opcode
)))
7885 if (fragP
->tc_frag_data
.is_no_transform
)
7886 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7888 relax_frag_add_nop (fragP
);
7897 static int unrelaxed_frag_min_insn_count (fragS
*);
7900 count_insns_to_loop_end (fragS
*base_fragP
,
7901 bfd_boolean count_relax_add
,
7904 fragS
*fragP
= NULL
;
7909 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7911 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7912 if (insn_count
>= max_count
)
7915 if (count_relax_add
)
7917 if (fragP
->fr_type
== rs_machine_dependent
7918 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7920 /* In order to add the appropriate number of
7921 NOPs, we count an instruction for downstream
7924 if (insn_count
>= max_count
)
7934 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7936 xtensa_isa isa
= xtensa_default_isa
;
7937 static xtensa_insnbuf insnbuf
= NULL
;
7941 if (!fragP
->tc_frag_data
.is_insn
)
7945 insnbuf
= xtensa_insnbuf_alloc (isa
);
7947 /* Decode the fixed instructions. */
7948 while (offset
< fragP
->fr_fix
)
7952 xtensa_insnbuf_from_chars
7953 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7954 fmt
= xtensa_format_decode (isa
, insnbuf
);
7956 if (fmt
== XTENSA_UNDEFINED
)
7958 as_fatal (_("undecodable instruction in instruction frag"));
7961 offset
+= xtensa_format_length (isa
, fmt
);
7969 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7972 branch_before_loop_end (fragS
*base_fragP
)
7976 for (fragP
= base_fragP
;
7977 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7978 fragP
= fragP
->fr_next
)
7980 if (unrelaxed_frag_has_b_j (fragP
))
7988 unrelaxed_frag_has_b_j (fragS
*fragP
)
7990 static xtensa_insnbuf insnbuf
= NULL
;
7991 xtensa_isa isa
= xtensa_default_isa
;
7994 if (!fragP
->tc_frag_data
.is_insn
)
7998 insnbuf
= xtensa_insnbuf_alloc (isa
);
8000 /* Decode the fixed instructions. */
8001 while (offset
< fragP
->fr_fix
)
8006 xtensa_insnbuf_from_chars
8007 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8008 fmt
= xtensa_format_decode (isa
, insnbuf
);
8009 if (fmt
== XTENSA_UNDEFINED
)
8012 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8014 xtensa_opcode opcode
=
8015 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8016 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8017 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8020 offset
+= xtensa_format_length (isa
, fmt
);
8026 /* Checks to be made after initial assembly but before relaxation. */
8028 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8029 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8032 xtensa_sanity_check (void)
8039 as_where (&file_name
, &line
);
8040 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8041 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8045 /* Walk over all of the fragments in a subsection. */
8046 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8048 if (fragP
->fr_type
== rs_machine_dependent
8049 && fragP
->fr_subtype
== RELAX_SLOTS
8050 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8052 static xtensa_insnbuf insnbuf
= NULL
;
8055 if (fragP
->fr_opcode
!= NULL
)
8058 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8059 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8060 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8062 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8063 t_insn
.opcode
) == 1)
8065 if (is_empty_loop (&t_insn
, fragP
))
8067 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8068 as_bad (_("invalid empty loop"));
8070 if (!is_local_forward_loop (&t_insn
, fragP
))
8072 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8073 as_bad (_("loop target does not follow "
8074 "loop instruction in section"));
8081 new_logical_line (file_name
, line
);
8085 #define LOOP_IMMED_OPN 1
8087 /* Return TRUE if the loop target is the next non-zero fragment. */
8090 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8092 const expressionS
*exp
;
8096 if (insn
->insn_type
!= ITYPE_INSN
)
8099 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8102 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8105 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8107 if (exp
->X_op
!= O_symbol
)
8110 symbolP
= exp
->X_add_symbol
;
8114 if (symbol_get_frag (symbolP
) == NULL
)
8117 if (S_GET_VALUE (symbolP
) != 0)
8120 /* Walk through the zero-size fragments from this one. If we find
8121 the target fragment, then this is a zero-size loop. */
8123 for (next_fragP
= fragP
->fr_next
;
8125 next_fragP
= next_fragP
->fr_next
)
8127 if (next_fragP
== symbol_get_frag (symbolP
))
8129 if (next_fragP
->fr_fix
!= 0)
8137 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8139 const expressionS
*exp
;
8143 if (insn
->insn_type
!= ITYPE_INSN
)
8146 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8149 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8152 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8154 if (exp
->X_op
!= O_symbol
)
8157 symbolP
= exp
->X_add_symbol
;
8161 if (symbol_get_frag (symbolP
) == NULL
)
8164 /* Walk through fragments until we find the target.
8165 If we do not find the target, then this is an invalid loop. */
8167 for (next_fragP
= fragP
->fr_next
;
8169 next_fragP
= next_fragP
->fr_next
)
8171 if (next_fragP
== symbol_get_frag (symbolP
))
8179 #define XTINFO_NAME "Xtensa_Info"
8180 #define XTINFO_NAMESZ 12
8181 #define XTINFO_TYPE 1
8184 xtensa_add_config_info (void)
8190 info_sec
= subseg_new (".xtensa.info", 0);
8191 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8193 data
= xmalloc (100);
8194 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8195 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8196 sz
= strlen (data
) + 1;
8198 /* Add enough null terminators to pad to a word boundary. */
8201 while ((sz
& 3) != 0);
8203 /* Follow the standard note section layout:
8204 First write the length of the name string. */
8206 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8208 /* Next comes the length of the "descriptor", i.e., the actual data. */
8210 md_number_to_chars (p
, (valueT
) sz
, 4);
8212 /* Write the note type. */
8214 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8216 /* Write the name field. */
8217 p
= frag_more (XTINFO_NAMESZ
);
8218 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8220 /* Finally, write the descriptor. */
8222 memcpy (p
, data
, sz
);
8228 /* Alignment Functions. */
8231 get_text_align_power (unsigned target_size
)
8233 if (target_size
<= 4)
8236 if (target_size
<= 8)
8239 if (target_size
<= 16)
8242 if (target_size
<= 32)
8245 if (target_size
<= 64)
8248 if (target_size
<= 128)
8251 if (target_size
<= 256)
8254 if (target_size
<= 512)
8257 if (target_size
<= 1024)
8266 get_text_align_max_fill_size (int align_pow
,
8267 bfd_boolean use_nops
,
8268 bfd_boolean use_no_density
)
8271 return (1 << align_pow
);
8273 return 3 * (1 << align_pow
);
8275 return 1 + (1 << align_pow
);
8279 /* Calculate the minimum bytes of fill needed at "address" to align a
8280 target instruction of size "target_size" so that it does not cross a
8281 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8282 the fill can be an arbitrary number of bytes. Otherwise, the space must
8283 be filled by NOP instructions. */
8286 get_text_align_fill_size (addressT address
,
8289 bfd_boolean use_nops
,
8290 bfd_boolean use_no_density
)
8292 addressT alignment
, fill
, fill_limit
, fill_step
;
8293 bfd_boolean skip_one
= FALSE
;
8295 alignment
= (1 << align_pow
);
8296 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8300 fill_limit
= alignment
;
8303 else if (!use_no_density
)
8305 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8306 fill_limit
= alignment
* 2;
8312 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8313 fill_limit
= alignment
* 3;
8317 /* Try all fill sizes until finding one that works. */
8318 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8320 if (skip_one
&& fill
== 1)
8322 if ((address
+ fill
) >> align_pow
8323 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8332 branch_align_power (segT sec
)
8334 /* If the Xtensa processor has a fetch width of X, and
8335 the section is aligned to at least that boundary, then a branch
8336 target need only fit within that aligned block of memory to avoid
8337 a stall. Otherwise, try to fit branch targets within 4-byte
8338 aligned blocks (which may be insufficient, e.g., if the section
8339 has no alignment, but it's good enough). */
8340 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8341 int sec_align
= get_recorded_alignment (sec
);
8343 if (sec_align
>= fetch_align
)
8350 /* This will assert if it is not possible. */
8353 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8359 gas_assert (fill_size
% 3 == 0);
8360 return (fill_size
/ 3);
8363 gas_assert (fill_size
!= 1); /* Bad argument. */
8365 while (fill_size
> 1)
8368 if (fill_size
== 2 || fill_size
== 4)
8370 fill_size
-= insn_size
;
8373 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8379 get_text_align_nth_nop_size (offsetT fill_size
,
8381 bfd_boolean use_no_density
)
8388 gas_assert (fill_size
!= 1); /* Bad argument. */
8390 while (fill_size
> 1)
8393 if (fill_size
== 2 || fill_size
== 4)
8395 fill_size
-= insn_size
;
8405 /* For the given fragment, find the appropriate address
8406 for it to begin at if we are using NOPs to align it. */
8409 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8411 /* The rule is: get next fragment's FIRST instruction. Find
8412 the smallest number of bytes that need to be added to
8413 ensure that the next fragment's FIRST instruction will fit
8416 E.G., 2 bytes : 0, 1, 2 mod 4
8419 If the FIRST instruction MIGHT be relaxed,
8420 assume that it will become a 3-byte instruction.
8422 Note again here that LOOP instructions are not bundleable,
8423 and this relaxation only applies to LOOP opcodes. */
8426 int first_insn_size
;
8428 addressT pre_opcode_bytes
;
8431 xtensa_opcode opcode
;
8432 bfd_boolean is_loop
;
8434 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8435 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8437 /* Find the loop frag. */
8438 first_insn
= next_non_empty_frag (fragP
);
8439 /* Now find the first insn frag. */
8440 first_insn
= next_non_empty_frag (first_insn
);
8442 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8443 gas_assert (is_loop
);
8444 loop_insn_size
= xg_get_single_size (opcode
);
8446 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8447 pre_opcode_bytes
+= loop_insn_size
;
8449 /* For loops, the alignment depends on the size of the
8450 instruction following the loop, not the LOOP instruction. */
8452 if (first_insn
== NULL
)
8453 first_insn_size
= xtensa_fetch_width
;
8455 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8457 /* If it was 8, then we'll need a larger alignment for the section. */
8458 align_power
= get_text_align_power (first_insn_size
);
8459 record_alignment (now_seg
, align_power
);
8461 fill_size
= get_text_align_fill_size
8462 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8463 fragP
->tc_frag_data
.is_no_density
);
8465 return address
+ fill_size
;
8469 /* 3 mechanisms for relaxing an alignment:
8471 Align to a power of 2.
8472 Align so the next fragment's instruction does not cross a word boundary.
8473 Align the current instruction so that if the next instruction
8474 were 3 bytes, it would not cross a word boundary.
8478 zeros - This is easy; always insert zeros.
8479 nops - 3-byte and 2-byte instructions
8483 >=5 : 3-byte instruction + fn (n-3)
8484 widening - widen previous instructions. */
8487 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8489 addressT target_address
, loop_insn_offset
;
8491 xtensa_opcode loop_opcode
;
8492 bfd_boolean is_loop
;
8495 offsetT branch_align
;
8498 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8499 switch (fragP
->fr_subtype
)
8501 case RELAX_DESIRE_ALIGN
:
8502 target_size
= next_frag_format_size (fragP
);
8503 if (target_size
== XTENSA_UNDEFINED
)
8505 align_power
= branch_align_power (now_seg
);
8506 branch_align
= 1 << align_power
;
8507 /* Don't count on the section alignment being as large as the target. */
8508 if (target_size
> branch_align
)
8509 target_size
= branch_align
;
8510 opt_diff
= get_text_align_fill_size (address
, align_power
,
8511 target_size
, FALSE
, FALSE
);
8513 *max_diff
= (opt_diff
+ branch_align
8514 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8515 gas_assert (*max_diff
>= opt_diff
);
8518 case RELAX_ALIGN_NEXT_OPCODE
:
8519 /* The next non-empty frag after this one holds the LOOP instruction
8520 that needs to be aligned. The required alignment depends on the
8521 size of the next non-empty frag after the loop frag, i.e., the
8522 first instruction in the loop. */
8523 loop_frag
= next_non_empty_frag (fragP
);
8524 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8525 loop_insn_offset
= 0;
8526 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8527 gas_assert (is_loop
);
8529 /* If the loop has been expanded then the LOOP instruction
8530 could be at an offset from this fragment. */
8531 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8532 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8534 /* In an ideal world, which is what we are shooting for here,
8535 we wouldn't need to use any NOPs immediately prior to the
8536 LOOP instruction. If this approach fails, relax_frag_loop_align
8537 will call get_noop_aligned_address. */
8539 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8540 align_power
= get_text_align_power (target_size
);
8541 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8542 target_size
, FALSE
, FALSE
);
8544 *max_diff
= xtensa_fetch_width
8545 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8546 - target_size
+ opt_diff
;
8547 gas_assert (*max_diff
>= opt_diff
);
8558 /* md_relax_frag Hook and Helper Functions. */
8560 static long relax_frag_loop_align (fragS
*, long);
8561 static long relax_frag_for_align (fragS
*, long);
8562 static long relax_frag_immed
8563 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8566 /* Return the number of bytes added to this fragment, given that the
8567 input has been stretched already by "stretch". */
8570 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8572 xtensa_isa isa
= xtensa_default_isa
;
8573 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8574 long new_stretch
= 0;
8578 static xtensa_insnbuf vbuf
= NULL
;
8579 int slot
, num_slots
;
8582 as_where (&file_name
, &line
);
8583 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8585 fragP
->tc_frag_data
.unreported_expansion
= 0;
8587 switch (fragP
->fr_subtype
)
8589 case RELAX_ALIGN_NEXT_OPCODE
:
8590 /* Always convert. */
8591 if (fragP
->tc_frag_data
.relax_seen
)
8592 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8595 case RELAX_LOOP_END
:
8599 case RELAX_LOOP_END_ADD_NOP
:
8600 /* Add a NOP and switch to .fill 0. */
8601 new_stretch
= relax_frag_add_nop (fragP
);
8605 case RELAX_DESIRE_ALIGN
:
8606 /* Do nothing. The narrowing before this frag will either align
8611 case RELAX_LITERAL_FINAL
:
8614 case RELAX_LITERAL_NR
:
8616 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8617 gas_assert (unreported
== lit_size
);
8618 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8619 fragP
->fr_var
-= lit_size
;
8620 fragP
->fr_fix
+= lit_size
;
8626 vbuf
= xtensa_insnbuf_alloc (isa
);
8628 xtensa_insnbuf_from_chars
8629 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8630 fmt
= xtensa_format_decode (isa
, vbuf
);
8631 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8633 for (slot
= 0; slot
< num_slots
; slot
++)
8635 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8638 if (fragP
->tc_frag_data
.relax_seen
)
8639 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8643 case RELAX_IMMED_STEP1
:
8644 case RELAX_IMMED_STEP2
:
8645 case RELAX_IMMED_STEP3
:
8646 /* Place the immediate. */
8647 new_stretch
+= relax_frag_immed
8648 (now_seg
, fragP
, stretch
,
8649 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8650 fmt
, slot
, stretched_p
, FALSE
);
8654 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8660 case RELAX_LITERAL_POOL_BEGIN
:
8661 case RELAX_LITERAL_POOL_END
:
8662 case RELAX_MAYBE_UNREACHABLE
:
8663 case RELAX_MAYBE_DESIRE_ALIGN
:
8664 /* No relaxation required. */
8667 case RELAX_FILL_NOP
:
8668 case RELAX_UNREACHABLE
:
8669 if (fragP
->tc_frag_data
.relax_seen
)
8670 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8674 as_bad (_("bad relaxation state"));
8677 /* Tell gas we need another relaxation pass. */
8678 if (! fragP
->tc_frag_data
.relax_seen
)
8680 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8684 new_logical_line (file_name
, line
);
8690 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8692 addressT old_address
, old_next_address
, old_size
;
8693 addressT new_address
, new_next_address
, new_size
;
8696 /* All the frags with relax_frag_for_alignment prior to this one in the
8697 section have been done, hopefully eliminating the need for a NOP here.
8698 But, this will put it in if necessary. */
8700 /* Calculate the old address of this fragment and the next fragment. */
8701 old_address
= fragP
->fr_address
- stretch
;
8702 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8703 fragP
->tc_frag_data
.text_expansion
[0]);
8704 old_size
= old_next_address
- old_address
;
8706 /* Calculate the new address of this fragment and the next fragment. */
8707 new_address
= fragP
->fr_address
;
8709 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8710 new_size
= new_next_address
- new_address
;
8712 growth
= new_size
- old_size
;
8714 /* Fix up the text_expansion field and return the new growth. */
8715 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8720 /* Add a NOP instruction. */
8723 relax_frag_add_nop (fragS
*fragP
)
8725 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8726 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8727 assemble_nop (length
, nop_buf
);
8728 fragP
->tc_frag_data
.is_insn
= TRUE
;
8730 if (fragP
->fr_var
< length
)
8732 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8736 fragP
->fr_fix
+= length
;
8737 fragP
->fr_var
-= length
;
8742 static long future_alignment_required (fragS
*, long);
8745 relax_frag_for_align (fragS
*fragP
, long stretch
)
8747 /* Overview of the relaxation procedure for alignment:
8748 We can widen with NOPs or by widening instructions or by filling
8749 bytes after jump instructions. Find the opportune places and widen
8750 them if necessary. */
8755 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8756 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8757 || (fragP
->fr_subtype
== RELAX_SLOTS
8758 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8760 stretch_me
= future_alignment_required (fragP
, stretch
);
8761 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8767 /* We expanded on a previous pass. Can we shrink now? */
8768 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8769 if (shrink
<= stretch
&& stretch
> 0)
8771 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8777 /* Below here, diff > 0. */
8778 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8784 /* Return the address of the next frag that should be aligned.
8786 By "address" we mean the address it _would_ be at if there
8787 is no action taken to align it between here and the target frag.
8788 In other words, if no narrows and no fill nops are used between
8789 here and the frag to align, _even_if_ some of the frags we use
8790 to align targets have already expanded on a previous relaxation
8793 Also, count each frag that may be used to help align the target.
8795 Return 0 if there are no frags left in the chain that need to be
8799 find_address_of_next_align_frag (fragS
**fragPP
,
8803 bfd_boolean
*paddable
)
8805 fragS
*fragP
= *fragPP
;
8806 addressT address
= fragP
->fr_address
;
8808 /* Do not reset the counts to 0. */
8812 /* Limit this to a small search. */
8813 if (*widens
>= (int) xtensa_fetch_width
)
8818 address
+= fragP
->fr_fix
;
8820 if (fragP
->fr_type
== rs_fill
)
8821 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8822 else if (fragP
->fr_type
== rs_machine_dependent
)
8824 switch (fragP
->fr_subtype
)
8826 case RELAX_UNREACHABLE
:
8830 case RELAX_FILL_NOP
:
8832 if (!fragP
->tc_frag_data
.is_no_density
)
8837 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8842 address
+= total_frag_text_expansion (fragP
);;
8846 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8849 case RELAX_ALIGN_NEXT_OPCODE
:
8850 case RELAX_DESIRE_ALIGN
:
8854 case RELAX_MAYBE_UNREACHABLE
:
8855 case RELAX_MAYBE_DESIRE_ALIGN
:
8860 /* Just punt if we don't know the type. */
8867 /* Just punt if we don't know the type. */
8871 fragP
= fragP
->fr_next
;
8879 static long bytes_to_stretch (fragS
*, int, int, int, int);
8882 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8884 fragS
*this_frag
= fragP
;
8888 int narrow_nops
= 0;
8889 bfd_boolean paddable
= FALSE
;
8890 offsetT local_opt_diff
;
8893 int stretch_amount
= 0;
8894 int local_stretch_amount
;
8895 int global_stretch_amount
;
8897 address
= find_address_of_next_align_frag
8898 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8902 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8903 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8905 frag_wane (this_frag
);
8909 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8910 opt_diff
= local_opt_diff
;
8911 gas_assert (opt_diff
>= 0);
8912 gas_assert (max_diff
>= opt_diff
);
8917 fragP
= fragP
->fr_next
;
8919 while (fragP
&& opt_diff
< max_diff
&& address
)
8921 /* We only use these to determine if we can exit early
8922 because there will be plenty of ways to align future
8924 int glob_widens
= 0;
8927 bfd_boolean glob_pad
= 0;
8928 address
= find_address_of_next_align_frag
8929 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8930 /* If there is a padable portion, then skip. */
8931 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8936 offsetT next_m_diff
;
8937 offsetT next_o_diff
;
8939 /* Downrange frags haven't had stretch added to them yet. */
8942 /* The address also includes any text expansion from this
8943 frag in a previous pass, but we don't want that. */
8944 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8946 /* Assume we are going to move at least opt_diff. In
8947 reality, we might not be able to, but assuming that
8948 we will helps catch cases where moving opt_diff pushes
8949 the next target from aligned to unaligned. */
8950 address
+= opt_diff
;
8952 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8954 /* Now cleanup for the adjustments to address. */
8955 next_o_diff
+= opt_diff
;
8956 next_m_diff
+= opt_diff
;
8957 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8958 opt_diff
= next_o_diff
;
8959 if (next_m_diff
< max_diff
)
8960 max_diff
= next_m_diff
;
8961 fragP
= fragP
->fr_next
;
8965 /* If there are enough wideners in between, do it. */
8968 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8970 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
8975 local_stretch_amount
8976 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8977 num_widens
, local_opt_diff
);
8978 global_stretch_amount
8979 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8980 num_widens
, opt_diff
);
8981 /* If the condition below is true, then the frag couldn't
8982 stretch the correct amount for the global case, so we just
8983 optimize locally. We'll rely on the subsequent frags to get
8984 the correct alignment in the global case. */
8985 if (global_stretch_amount
< local_stretch_amount
)
8986 stretch_amount
= local_stretch_amount
;
8988 stretch_amount
= global_stretch_amount
;
8990 if (this_frag
->fr_subtype
== RELAX_SLOTS
8991 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8992 gas_assert (stretch_amount
<= 1);
8993 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8995 if (this_frag
->tc_frag_data
.is_no_density
)
8996 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
8998 gas_assert (stretch_amount
<= 3);
9001 return stretch_amount
;
9005 /* The idea: widen everything you can to get a target or loop aligned,
9006 then start using NOPs.
9008 wide_nops = the number of wide NOPs available for aligning
9009 narrow_nops = the number of narrow NOPs available for aligning
9010 (a subset of wide_nops)
9011 widens = the number of narrow instructions that should be widened
9016 bytes_to_stretch (fragS
*this_frag
,
9025 int bytes_short
= desired_diff
- num_widens
;
9027 gas_assert (desired_diff
>= 0
9028 && desired_diff
< (signed) xtensa_fetch_width
);
9029 if (desired_diff
== 0)
9032 gas_assert (wide_nops
> 0 || num_widens
> 0);
9034 /* Always prefer widening to NOP-filling. */
9035 if (bytes_short
< 0)
9037 /* There are enough RELAX_NARROW frags after this one
9038 to align the target without widening this frag in any way. */
9042 if (bytes_short
== 0)
9044 /* Widen every narrow between here and the align target
9045 and the align target will be properly aligned. */
9046 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9052 /* From here we will need at least one NOP to get an alignment.
9053 However, we may not be able to align at all, in which case,
9055 nops_needed
= desired_diff
/ 3;
9057 /* If there aren't enough nops, don't widen. */
9058 if (nops_needed
> wide_nops
)
9061 /* First try it with all wide nops. */
9062 nop_bytes
= nops_needed
* 3;
9063 extra_bytes
= desired_diff
- nop_bytes
;
9065 if (nop_bytes
+ num_widens
>= desired_diff
)
9067 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9069 else if (num_widens
== extra_bytes
)
9074 /* Add a narrow nop. */
9078 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9081 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9083 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9084 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9085 else if (num_widens
== extra_bytes
)
9090 /* Replace a wide nop with a narrow nop--we can get here if
9091 extra_bytes was negative in the previous conditional. */
9092 if (narrow_nops
== 1)
9096 if (nop_bytes
+ num_widens
>= desired_diff
)
9098 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9099 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9100 else if (num_widens
== extra_bytes
)
9105 /* If we can't satisfy any of the above cases, then we can't align
9106 using padding or fill nops. */
9112 relax_frag_immed (segT segP
,
9119 bfd_boolean estimate_only
)
9123 bfd_boolean negatable_branch
= FALSE
;
9124 bfd_boolean branch_jmp_to_next
= FALSE
;
9125 bfd_boolean from_wide_insn
= FALSE
;
9126 xtensa_isa isa
= xtensa_default_isa
;
9128 offsetT frag_offset
;
9130 int num_text_bytes
, num_literal_bytes
;
9131 int literal_diff
, total_text_diff
, this_text_diff
;
9133 gas_assert (fragP
->fr_opcode
!= NULL
);
9135 xg_clear_vinsn (&cur_vinsn
);
9136 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9137 if (cur_vinsn
.num_slots
> 1)
9138 from_wide_insn
= TRUE
;
9140 tinsn
= cur_vinsn
.slots
[slot
];
9141 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9143 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9146 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9147 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9149 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9151 old_size
= xtensa_format_length (isa
, fmt
);
9153 /* Special case: replace a branch to the next instruction with a NOP.
9154 This is required to work around a hardware bug in T1040.0 and also
9155 serves as an optimization. */
9157 if (branch_jmp_to_next
9158 && ((old_size
== 2) || (old_size
== 3))
9159 && !next_frag_is_loop_target (fragP
))
9162 /* Here is the fun stuff: Get the immediate field from this
9163 instruction. If it fits, we are done. If not, find the next
9164 instruction sequence that fits. */
9166 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9167 istack_init (&istack
);
9168 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9169 min_steps
, stretch
);
9170 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9172 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9174 /* Figure out the number of bytes needed. */
9175 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9177 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9178 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9183 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9186 num_text_bytes
+= old_size
;
9187 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9188 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9191 /* The first instruction in the relaxed sequence will go after
9192 the current wide instruction, and thus its symbolic immediates
9195 istack_init (&istack
);
9196 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9197 frag_offset
+ old_size
,
9198 min_steps
, stretch
+ old_size
);
9199 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9201 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9202 = (int) RELAX_IMMED
+ num_steps
;
9204 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9206 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9208 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9212 total_text_diff
= num_text_bytes
- old_size
;
9213 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9215 /* It MUST get larger. If not, we could get an infinite loop. */
9216 gas_assert (num_text_bytes
>= 0);
9217 gas_assert (literal_diff
>= 0);
9218 gas_assert (total_text_diff
>= 0);
9220 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9221 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9222 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9223 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9225 /* Find the associated expandable literal for this. */
9226 if (literal_diff
!= 0)
9228 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9231 gas_assert (literal_diff
== 4);
9232 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9234 /* We expect that the literal section state has NOT been
9236 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9237 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9238 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9240 /* We need to mark this section for another iteration
9246 if (negatable_branch
&& istack
.ninsn
> 1)
9247 update_next_frag_state (fragP
);
9249 return this_text_diff
;
9253 /* md_convert_frag Hook and Helper Functions. */
9255 static void convert_frag_align_next_opcode (fragS
*);
9256 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9257 static void convert_frag_fill_nop (fragS
*);
9258 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9261 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9263 static xtensa_insnbuf vbuf
= NULL
;
9264 xtensa_isa isa
= xtensa_default_isa
;
9271 as_where (&file_name
, &line
);
9272 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9274 switch (fragp
->fr_subtype
)
9276 case RELAX_ALIGN_NEXT_OPCODE
:
9277 /* Always convert. */
9278 convert_frag_align_next_opcode (fragp
);
9281 case RELAX_DESIRE_ALIGN
:
9282 /* Do nothing. If not aligned already, too bad. */
9286 case RELAX_LITERAL_FINAL
:
9291 vbuf
= xtensa_insnbuf_alloc (isa
);
9293 xtensa_insnbuf_from_chars
9294 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9295 fmt
= xtensa_format_decode (isa
, vbuf
);
9296 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9298 for (slot
= 0; slot
< num_slots
; slot
++)
9300 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9303 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9307 case RELAX_IMMED_STEP1
:
9308 case RELAX_IMMED_STEP2
:
9309 case RELAX_IMMED_STEP3
:
9310 /* Place the immediate. */
9313 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9318 /* This is OK because some slots could have
9319 relaxations and others have none. */
9325 case RELAX_UNREACHABLE
:
9326 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9327 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9328 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9332 case RELAX_MAYBE_UNREACHABLE
:
9333 case RELAX_MAYBE_DESIRE_ALIGN
:
9337 case RELAX_FILL_NOP
:
9338 convert_frag_fill_nop (fragp
);
9341 case RELAX_LITERAL_NR
:
9342 if (use_literal_section
)
9344 /* This should have been handled during relaxation. When
9345 relaxing a code segment, literals sometimes need to be
9346 added to the corresponding literal segment. If that
9347 literal segment has already been relaxed, then we end up
9348 in this situation. Marking the literal segments as data
9349 would make this happen less often (since GAS always relaxes
9350 code before data), but we could still get into trouble if
9351 there are instructions in a segment that is not marked as
9352 containing code. Until we can implement a better solution,
9353 cheat and adjust the addresses of all the following frags.
9354 This could break subsequent alignments, but the linker's
9355 literal coalescing will do that anyway. */
9358 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9359 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9360 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9363 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9367 as_bad (_("invalid relaxation fragment result"));
9372 new_logical_line (file_name
, line
);
9377 convert_frag_align_next_opcode (fragS
*fragp
)
9379 char *nop_buf
; /* Location for Writing. */
9380 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9381 addressT aligned_address
;
9385 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9387 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9388 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9389 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9391 for (nop
= 0; nop
< nop_count
; nop
++)
9394 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9396 assemble_nop (nop_size
, nop_buf
);
9397 nop_buf
+= nop_size
;
9400 fragp
->fr_fix
+= fill_size
;
9401 fragp
->fr_var
-= fill_size
;
9406 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9408 TInsn tinsn
, single_target
;
9409 int size
, old_size
, diff
;
9410 offsetT frag_offset
;
9412 gas_assert (slot
== 0);
9413 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9415 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9417 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9418 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9419 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9424 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9426 /* No conversion. */
9431 gas_assert (fragP
->fr_opcode
!= NULL
);
9433 /* Frags in this relaxation state should only contain
9434 single instruction bundles. */
9435 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9437 /* Just convert it to a wide form.... */
9439 old_size
= xg_get_single_size (tinsn
.opcode
);
9441 tinsn_init (&single_target
);
9442 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9444 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9446 as_bad (_("unable to widen instruction"));
9450 size
= xg_get_single_size (single_target
.opcode
);
9451 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9454 diff
= size
- old_size
;
9455 gas_assert (diff
>= 0);
9456 gas_assert (diff
<= fragP
->fr_var
);
9457 fragP
->fr_var
-= diff
;
9458 fragP
->fr_fix
+= diff
;
9466 convert_frag_fill_nop (fragS
*fragP
)
9468 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9469 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9470 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9471 - fragP
->fr_address
- fragP
->fr_fix
));
9474 /* No conversion. */
9478 assemble_nop (size
, loc
);
9479 fragP
->tc_frag_data
.is_insn
= TRUE
;
9480 fragP
->fr_var
-= size
;
9481 fragP
->fr_fix
+= size
;
9486 static fixS
*fix_new_exp_in_seg
9487 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9488 bfd_reloc_code_real_type
);
9489 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9492 convert_frag_immed (segT segP
,
9498 char *immed_instr
= fragP
->fr_opcode
;
9500 bfd_boolean expanded
= FALSE
;
9501 bfd_boolean branch_jmp_to_next
= FALSE
;
9502 char *fr_opcode
= fragP
->fr_opcode
;
9503 xtensa_isa isa
= xtensa_default_isa
;
9504 bfd_boolean from_wide_insn
= FALSE
;
9506 bfd_boolean is_loop
;
9508 gas_assert (fr_opcode
!= NULL
);
9510 xg_clear_vinsn (&cur_vinsn
);
9512 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9513 if (cur_vinsn
.num_slots
> 1)
9514 from_wide_insn
= TRUE
;
9516 orig_tinsn
= cur_vinsn
.slots
[slot
];
9517 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9519 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9521 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9522 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9524 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9526 /* Conversion just inserts a NOP and marks the fix as completed. */
9527 bytes
= xtensa_format_length (isa
, fmt
);
9530 cur_vinsn
.slots
[slot
].opcode
=
9531 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9532 cur_vinsn
.slots
[slot
].ntok
= 0;
9536 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9537 gas_assert (bytes
== 2 || bytes
== 3);
9538 build_nop (&cur_vinsn
.slots
[0], bytes
);
9539 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9541 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9542 xtensa_insnbuf_to_chars
9543 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9548 /* Here is the fun stuff: Get the immediate field from this
9549 instruction. If it fits, we're done. If not, find the next
9550 instruction sequence that fits. */
9554 symbolS
*lit_sym
= NULL
;
9556 int target_offset
= 0;
9559 symbolS
*gen_label
= NULL
;
9560 offsetT frag_offset
;
9561 bfd_boolean first
= TRUE
;
9562 bfd_boolean last_is_jump
;
9564 /* It does not fit. Find something that does and
9565 convert immediately. */
9566 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9567 istack_init (&istack
);
9568 xg_assembly_relax (&istack
, &orig_tinsn
,
9569 segP
, fragP
, frag_offset
, min_steps
, 0);
9571 old_size
= xtensa_format_length (isa
, fmt
);
9573 /* Assemble this right inline. */
9575 /* First, create the mapping from a label name to the REAL label. */
9577 for (i
= 0; i
< istack
.ninsn
; i
++)
9579 TInsn
*tinsn
= &istack
.insn
[i
];
9582 switch (tinsn
->insn_type
)
9585 if (lit_sym
!= NULL
)
9586 as_bad (_("multiple literals in expansion"));
9587 /* First find the appropriate space in the literal pool. */
9588 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9589 if (lit_frag
== NULL
)
9590 as_bad (_("no registered fragment for literal"));
9591 if (tinsn
->ntok
!= 1)
9592 as_bad (_("number of literal tokens != 1"));
9594 /* Set the literal symbol and add a fixup. */
9595 lit_sym
= lit_frag
->fr_symbol
;
9599 if (align_targets
&& !is_loop
)
9601 fragS
*unreach
= fragP
->fr_next
;
9602 while (!(unreach
->fr_type
== rs_machine_dependent
9603 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9604 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9606 unreach
= unreach
->fr_next
;
9609 gas_assert (unreach
->fr_type
== rs_machine_dependent
9610 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9611 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9613 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9615 gas_assert (gen_label
== NULL
);
9616 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9617 fr_opcode
- fragP
->fr_literal
9618 + target_offset
, fragP
);
9622 if (first
&& from_wide_insn
)
9624 target_offset
+= xtensa_format_length (isa
, fmt
);
9626 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9627 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9630 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9637 last_is_jump
= FALSE
;
9638 for (i
= 0; i
< istack
.ninsn
; i
++)
9640 TInsn
*tinsn
= &istack
.insn
[i
];
9644 bfd_reloc_code_real_type reloc_type
;
9646 switch (tinsn
->insn_type
)
9649 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9650 /* Already checked. */
9651 gas_assert (lit_frag
!= NULL
);
9652 gas_assert (lit_sym
!= NULL
);
9653 gas_assert (tinsn
->ntok
== 1);
9655 target_seg
= S_GET_SEGMENT (lit_sym
);
9656 gas_assert (target_seg
);
9657 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
9658 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9659 &tinsn
->tok
[0], FALSE
, reloc_type
);
9666 xg_resolve_labels (tinsn
, gen_label
);
9667 xg_resolve_literals (tinsn
, lit_sym
);
9668 if (from_wide_insn
&& first
)
9671 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9673 cur_vinsn
.slots
[slot
] = *tinsn
;
9677 cur_vinsn
.slots
[slot
].opcode
=
9678 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9679 cur_vinsn
.slots
[slot
].ntok
= 0;
9681 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9682 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9683 (unsigned char *) immed_instr
, 0);
9684 fragP
->tc_frag_data
.is_insn
= TRUE
;
9685 size
= xtensa_format_length (isa
, fmt
);
9686 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9689 (tinsn
, immed_instr
+ size
, fragP
,
9690 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9691 size
+= xg_get_single_size (tinsn
->opcode
);
9696 size
= xg_get_single_size (tinsn
->opcode
);
9697 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9698 immed_instr
- fragP
->fr_literal
, TRUE
);
9700 immed_instr
+= size
;
9706 diff
= total_size
- old_size
;
9707 gas_assert (diff
>= 0);
9710 gas_assert (diff
<= fragP
->fr_var
);
9711 fragP
->fr_var
-= diff
;
9712 fragP
->fr_fix
+= diff
;
9715 /* Check for undefined immediates in LOOP instructions. */
9719 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9720 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9722 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9725 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9726 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9728 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9733 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9734 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9736 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9738 /* Add an expansion note on the expanded instruction. */
9739 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9740 &orig_tinsn
.tok
[0], TRUE
,
9741 BFD_RELOC_XTENSA_ASM_EXPAND
);
9746 /* Add a new fix expression into the desired segment. We have to
9747 switch to that segment to do this. */
9750 fix_new_exp_in_seg (segT new_seg
,
9757 bfd_reloc_code_real_type r_type
)
9761 subsegT subseg
= now_subseg
;
9763 gas_assert (new_seg
!= 0);
9764 subseg_set (new_seg
, new_subseg
);
9766 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9767 subseg_set (seg
, subseg
);
9772 /* Relax a loop instruction so that it can span loop >256 bytes.
9778 addi as, as, lo8 (label-.L1)
9779 addmi as, as, mid8 (label-.L1)
9790 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9795 unsigned long target
;
9796 static xtensa_insnbuf insnbuf
= NULL
;
9797 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9798 xtensa_isa isa
= xtensa_default_isa
;
9799 addressT loop_offset
;
9800 addressT addi_offset
= 9;
9801 addressT addmi_offset
= 12;
9806 insnbuf
= xtensa_insnbuf_alloc (isa
);
9808 /* Get the loop offset. */
9809 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9811 /* Validate that there really is a LOOP at the loop_offset. Because
9812 loops are not bundleable, we can assume that the instruction will be
9814 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9815 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9817 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9818 addi_offset
+= loop_offset
;
9819 addmi_offset
+= loop_offset
;
9821 gas_assert (tinsn
->ntok
== 2);
9822 if (tinsn
->tok
[1].X_op
== O_constant
)
9823 target
= tinsn
->tok
[1].X_add_number
;
9824 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9826 /* Find the fragment. */
9827 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9828 gas_assert (S_GET_SEGMENT (sym
) == segP
9829 || S_GET_SEGMENT (sym
) == absolute_section
);
9830 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9834 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9838 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9839 loop_length_hi
= loop_length
& ~0x0ff;
9840 loop_length_lo
= loop_length
& 0x0ff;
9841 if (loop_length_lo
>= 128)
9843 loop_length_lo
-= 256;
9844 loop_length_hi
+= 256;
9847 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9848 32512. If the loop is larger than that, then we just fail. */
9849 if (loop_length_hi
> 32512)
9850 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9851 _("loop too long for LOOP instruction"));
9853 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9854 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9856 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9857 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9859 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9860 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9862 fragP
->tc_frag_data
.is_insn
= TRUE
;
9863 xtensa_insnbuf_to_chars
9864 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9866 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9867 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9868 xtensa_insnbuf_to_chars
9869 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9871 /* Walk through all of the frags from here to the loop end
9872 and mark them as no_transform to keep them from being modified
9873 by the linker. If we ever have a relocation for the
9874 addi/addmi of the difference of two symbols we can remove this. */
9877 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9878 next_fragP
= next_fragP
->fr_next
)
9880 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9881 if (next_fragP
->tc_frag_data
.is_loop_target
)
9883 if (target_count
== 2)
9889 /* A map that keeps information on a per-subsegment basis. This is
9890 maintained during initial assembly, but is invalid once the
9891 subsegments are smashed together. I.E., it cannot be used during
9894 typedef struct subseg_map_struct
9902 float total_freq
; /* fall-through + branch target frequency */
9903 float target_freq
; /* branch target frequency alone */
9905 struct subseg_map_struct
*next
;
9909 static subseg_map
*sseg_map
= NULL
;
9912 get_subseg_info (segT seg
, subsegT subseg
)
9914 subseg_map
*subseg_e
;
9916 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9918 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9926 add_subseg_info (segT seg
, subsegT subseg
)
9928 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9929 memset (subseg_e
, 0, sizeof (subseg_map
));
9930 subseg_e
->seg
= seg
;
9931 subseg_e
->subseg
= subseg
;
9932 subseg_e
->flags
= 0;
9933 /* Start off considering every branch target very important. */
9934 subseg_e
->target_freq
= 1.0;
9935 subseg_e
->total_freq
= 1.0;
9936 subseg_e
->next
= sseg_map
;
9937 sseg_map
= subseg_e
;
9943 get_last_insn_flags (segT seg
, subsegT subseg
)
9945 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9947 return subseg_e
->flags
;
9953 set_last_insn_flags (segT seg
,
9958 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9960 subseg_e
= add_subseg_info (seg
, subseg
);
9962 subseg_e
->flags
|= fl
;
9964 subseg_e
->flags
&= ~fl
;
9969 get_subseg_total_freq (segT seg
, subsegT subseg
)
9971 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9973 return subseg_e
->total_freq
;
9979 get_subseg_target_freq (segT seg
, subsegT subseg
)
9981 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9983 return subseg_e
->target_freq
;
9989 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9991 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9993 subseg_e
= add_subseg_info (seg
, subseg
);
9994 subseg_e
->total_freq
= total_f
;
9995 subseg_e
->target_freq
= target_f
;
9999 /* Segment Lists and emit_state Stuff. */
10002 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10007 segT literal_section
= head
->seg
;
10009 /* Move the literal section to the front of the section list. */
10010 gas_assert (literal_section
);
10011 if (literal_section
!= stdoutput
->sections
)
10013 bfd_section_list_remove (stdoutput
, literal_section
);
10014 bfd_section_list_prepend (stdoutput
, literal_section
);
10021 static void mark_literal_frags (seg_list
*);
10024 xtensa_move_literals (void)
10027 frchainS
*frchain_from
, *frchain_to
;
10028 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
10029 fragS
**frag_splice
;
10032 fixS
*fix
, *next_fix
, **fix_splice
;
10035 mark_literal_frags (literal_head
->next
);
10037 if (use_literal_section
)
10040 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10042 /* Keep the literals for .init and .fini in separate sections. */
10043 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10044 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10047 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10048 search_frag
= frchain_from
->frch_root
;
10049 literal_pool
= NULL
;
10051 frag_splice
= &(frchain_from
->frch_root
);
10053 while (!search_frag
->tc_frag_data
.literal_frag
)
10055 gas_assert (search_frag
->fr_fix
== 0
10056 || search_frag
->fr_type
== rs_align
);
10057 search_frag
= search_frag
->fr_next
;
10060 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10061 == RELAX_LITERAL_POOL_BEGIN
);
10062 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10064 /* Make sure that all the frags in this series are closed, and
10065 that there is at least one left over of zero-size. This
10066 prevents us from making a segment with an frchain without any
10068 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10069 xtensa_set_frag_assembly_state (frag_now
);
10070 last_frag
= frag_now
;
10071 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10072 xtensa_set_frag_assembly_state (frag_now
);
10074 while (search_frag
!= frag_now
)
10076 next_frag
= search_frag
->fr_next
;
10078 /* First, move the frag out of the literal section and
10079 to the appropriate place. */
10080 if (search_frag
->tc_frag_data
.literal_frag
)
10082 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10083 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10084 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10085 gas_assert (frchain_to
);
10087 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10088 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10090 *frag_splice
= next_frag
;
10091 search_frag
->fr_next
= insert_after
->fr_next
;
10092 insert_after
->fr_next
= search_frag
;
10093 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10094 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10096 /* Now move any fixups associated with this frag to the
10098 fix
= frchain_from
->fix_root
;
10099 fix_splice
= &(frchain_from
->fix_root
);
10102 next_fix
= fix
->fx_next
;
10103 if (fix
->fx_frag
== search_frag
)
10105 *fix_splice
= next_fix
;
10106 fix
->fx_next
= frchain_to
->fix_root
;
10107 frchain_to
->fix_root
= fix
;
10108 if (frchain_to
->fix_tail
== NULL
)
10109 frchain_to
->fix_tail
= fix
;
10112 fix_splice
= &(fix
->fx_next
);
10115 search_frag
= next_frag
;
10118 if (frchain_from
->fix_root
!= NULL
)
10120 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10121 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10123 gas_assert (frchain_from
->fix_root
== NULL
);
10125 frchain_from
->fix_tail
= NULL
;
10126 xtensa_restore_emit_state (&state
);
10129 /* Now fix up the SEGMENT value for all the literal symbols. */
10130 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10132 symbolS
*lit_sym
= lit
->sym
;
10133 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10135 S_SET_SEGMENT (lit_sym
, dseg
);
10140 /* Walk over all the frags for segments in a list and mark them as
10141 containing literals. As clunky as this is, we can't rely on frag_var
10142 and frag_variant to get called in all situations. */
10145 mark_literal_frags (seg_list
*segment
)
10147 frchainS
*frchain_from
;
10148 fragS
*search_frag
;
10152 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10153 search_frag
= frchain_from
->frch_root
;
10154 while (search_frag
)
10156 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10157 search_frag
= search_frag
->fr_next
;
10159 segment
= segment
->next
;
10165 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10167 /* Move all of the sections in the section list to come
10168 after "after" in the gnu segment list. */
10173 segT literal_section
= head
->seg
;
10175 /* Move the literal section after "after". */
10176 gas_assert (literal_section
);
10177 if (literal_section
!= after
)
10179 bfd_section_list_remove (stdoutput
, literal_section
);
10180 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10188 /* Push all the literal segments to the end of the gnu list. */
10191 xtensa_reorder_segments (void)
10198 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10204 /* Now that we have the last section, push all the literal
10205 sections to the end. */
10206 xtensa_reorder_seg_list (literal_head
, last_sec
);
10208 /* Now perform the final error check. */
10209 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10211 gas_assert (new_count
== old_count
);
10215 /* Change the emit state (seg, subseg, and frag related stuff) to the
10216 correct location. Return a emit_state which can be passed to
10217 xtensa_restore_emit_state to return to current fragment. */
10220 xtensa_switch_to_literal_fragment (emit_state
*result
)
10222 if (directive_state
[directive_absolute_literals
])
10224 segT lit4_seg
= cache_literal_section (TRUE
);
10225 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10228 xtensa_switch_to_non_abs_literal_fragment (result
);
10230 /* Do a 4-byte align here. */
10231 frag_align (2, 0, 0);
10232 record_alignment (now_seg
, 2);
10237 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10239 static bfd_boolean recursive
= FALSE
;
10240 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10242 bfd_boolean is_init
=
10243 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10244 bfd_boolean is_fini
=
10245 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10247 if (pool_location
== NULL
10248 && !use_literal_section
10250 && !is_init
&& ! is_fini
)
10252 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10254 /* When we mark a literal pool location, we want to put a frag in
10255 the literal pool that points to it. But to do that, we want to
10256 switch_to_literal_fragment. But literal sections don't have
10257 literal pools, so their location is always null, so we would
10258 recurse forever. This is kind of hacky, but it works. */
10261 xtensa_mark_literal_pool_location ();
10265 lit_seg
= cache_literal_section (FALSE
);
10266 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10268 if (!use_literal_section
10269 && !is_init
&& !is_fini
10270 && get_literal_pool_location (now_seg
) != pool_location
)
10272 /* Close whatever frag is there. */
10273 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10274 xtensa_set_frag_assembly_state (frag_now
);
10275 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10276 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10277 xtensa_set_frag_assembly_state (frag_now
);
10282 /* Call this function before emitting data into the literal section.
10283 This is a helper function for xtensa_switch_to_literal_fragment.
10284 This is similar to a .section new_now_seg subseg. */
10287 xtensa_switch_section_emit_state (emit_state
*state
,
10289 subsegT new_now_subseg
)
10291 state
->name
= now_seg
->name
;
10292 state
->now_seg
= now_seg
;
10293 state
->now_subseg
= now_subseg
;
10294 state
->generating_literals
= generating_literals
;
10295 generating_literals
++;
10296 subseg_set (new_now_seg
, new_now_subseg
);
10300 /* Use to restore the emitting into the normal place. */
10303 xtensa_restore_emit_state (emit_state
*state
)
10305 generating_literals
= state
->generating_literals
;
10306 subseg_set (state
->now_seg
, state
->now_subseg
);
10310 /* Predicate function used to look up a section in a particular group. */
10313 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10315 const char *gname
= inf
;
10316 const char *group_name
= elf_group_name (sec
);
10318 return (group_name
== gname
10319 || (group_name
!= NULL
10321 && strcmp (group_name
, gname
) == 0));
10325 /* Get the literal section to be used for the current text section.
10326 The result may be cached in the default_lit_sections structure. */
10329 cache_literal_section (bfd_boolean use_abs_literals
)
10331 const char *text_name
, *group_name
= 0;
10332 char *base_name
, *name
, *suffix
;
10334 segT seg
, current_section
;
10335 int current_subsec
;
10336 bfd_boolean linkonce
= FALSE
;
10338 /* Save the current section/subsection. */
10339 current_section
= now_seg
;
10340 current_subsec
= now_subseg
;
10342 /* Clear the cached values if they are no longer valid. */
10343 if (now_seg
!= default_lit_sections
.current_text_seg
)
10345 default_lit_sections
.current_text_seg
= now_seg
;
10346 default_lit_sections
.lit_seg
= NULL
;
10347 default_lit_sections
.lit4_seg
= NULL
;
10350 /* Check if the literal section is already cached. */
10351 if (use_abs_literals
)
10352 pcached
= &default_lit_sections
.lit4_seg
;
10354 pcached
= &default_lit_sections
.lit_seg
;
10359 text_name
= default_lit_sections
.lit_prefix
;
10360 if (! text_name
|| ! *text_name
)
10362 text_name
= segment_name (current_section
);
10363 group_name
= elf_group_name (current_section
);
10364 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10367 base_name
= use_abs_literals
? ".lit4" : ".literal";
10370 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10371 sprintf (name
, "%s.%s", base_name
, group_name
);
10373 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10375 suffix
= strchr (text_name
+ linkonce_len
, '.');
10377 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10378 + (suffix
? strlen (suffix
) : 0));
10379 strcpy (name
, ".gnu.linkonce");
10380 strcat (name
, base_name
);
10382 strcat (name
, suffix
);
10387 /* If the section name ends with ".text", then replace that suffix
10388 instead of appending an additional suffix. */
10389 size_t len
= strlen (text_name
);
10390 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10393 name
= xmalloc (len
+ strlen (base_name
) + 1);
10394 strcpy (name
, text_name
);
10395 strcpy (name
+ len
, base_name
);
10398 /* Canonicalize section names to allow renaming literal sections.
10399 The group name, if any, came from the current text section and
10400 has already been canonicalized. */
10401 name
= tc_canonicalize_symbol_name (name
);
10403 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10404 (void *) group_name
);
10409 seg
= subseg_force_new (name
, 0);
10411 if (! use_abs_literals
)
10413 /* Add the newly created literal segment to the list. */
10414 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10416 n
->next
= literal_head
->next
;
10417 literal_head
->next
= n
;
10420 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10421 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10422 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10424 elf_group_name (seg
) = group_name
;
10426 bfd_set_section_flags (stdoutput
, seg
, flags
);
10427 bfd_set_section_alignment (stdoutput
, seg
, 2);
10431 subseg_set (current_section
, current_subsec
);
10436 /* Property Tables Stuff. */
10438 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10439 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10440 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10442 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10443 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10445 static bfd_boolean
get_frag_is_literal (const fragS
*);
10446 static void xtensa_create_property_segments
10447 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10448 static void xtensa_create_xproperty_segments
10449 (frag_flags_fn
, const char *, xt_section_type
);
10450 static bfd_boolean
exclude_section_from_property_tables (segT
);
10451 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10452 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10453 static void add_xt_block_frags
10454 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10455 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10456 static void xtensa_frag_flags_init (frag_flags
*);
10457 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10458 static flagword
frag_flags_to_number (const frag_flags
*);
10459 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10461 /* Set up property tables after relaxation. */
10464 xtensa_post_relax_hook (void)
10466 xtensa_move_seg_list_to_beginning (literal_head
);
10468 xtensa_find_unmarked_state_frags ();
10469 xtensa_mark_frags_for_org ();
10470 xtensa_mark_difference_of_two_symbols ();
10472 xtensa_create_property_segments (get_frag_is_literal
,
10474 XTENSA_LIT_SEC_NAME
,
10476 xtensa_create_xproperty_segments (get_frag_property_flags
,
10477 XTENSA_PROP_SEC_NAME
,
10480 if (warn_unaligned_branch_targets
)
10481 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10482 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10486 /* This function is only meaningful after xtensa_move_literals. */
10489 get_frag_is_literal (const fragS
*fragP
)
10491 gas_assert (fragP
!= NULL
);
10492 return fragP
->tc_frag_data
.is_literal
;
10497 xtensa_create_property_segments (frag_predicate property_function
,
10498 frag_predicate end_property_function
,
10499 const char *section_name_base
,
10500 xt_section_type sec_type
)
10504 /* Walk over all of the current segments.
10505 Walk over each fragment
10506 For each non-empty fragment,
10507 Build a property record (append where possible). */
10509 for (seclist
= &stdoutput
->sections
;
10510 seclist
&& *seclist
;
10511 seclist
= &(*seclist
)->next
)
10513 segT sec
= *seclist
;
10515 if (exclude_section_from_property_tables (sec
))
10518 if (section_has_property (sec
, property_function
))
10520 segment_info_type
*xt_seg_info
;
10521 xtensa_block_info
**xt_blocks
;
10522 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10524 prop_sec
->output_section
= prop_sec
;
10525 subseg_set (prop_sec
, 0);
10526 xt_seg_info
= seg_info (prop_sec
);
10527 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10529 /* Walk over all of the frchains here and add new sections. */
10530 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10531 end_property_function
);
10535 /* Now we fill them out.... */
10537 for (seclist
= &stdoutput
->sections
;
10538 seclist
&& *seclist
;
10539 seclist
= &(*seclist
)->next
)
10541 segment_info_type
*seginfo
;
10542 xtensa_block_info
*block
;
10543 segT sec
= *seclist
;
10545 seginfo
= seg_info (sec
);
10546 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10550 xtensa_block_info
*cur_block
;
10552 bfd_size_type rec_size
;
10554 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10557 rec_size
= num_recs
* 8;
10558 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10565 subseg_set (sec
, 0);
10566 frag_data
= frag_more (rec_size
);
10568 for (i
= 0; i
< num_recs
; i
++)
10572 /* Write the fixup. */
10573 gas_assert (cur_block
);
10574 fix
= fix_new (frag_now
, i
* 8, 4,
10575 section_symbol (cur_block
->sec
),
10577 FALSE
, BFD_RELOC_32
);
10578 fix
->fx_file
= "<internal>";
10581 /* Write the length. */
10582 md_number_to_chars (&frag_data
[4 + i
* 8],
10583 cur_block
->size
, 4);
10584 cur_block
= cur_block
->next
;
10586 frag_wane (frag_now
);
10588 frag_wane (frag_now
);
10596 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10597 const char *section_name_base
,
10598 xt_section_type sec_type
)
10602 /* Walk over all of the current segments.
10603 Walk over each fragment.
10604 For each fragment that has instructions,
10605 build an instruction record (append where possible). */
10607 for (seclist
= &stdoutput
->sections
;
10608 seclist
&& *seclist
;
10609 seclist
= &(*seclist
)->next
)
10611 segT sec
= *seclist
;
10613 if (exclude_section_from_property_tables (sec
))
10616 if (section_has_xproperty (sec
, flag_fn
))
10618 segment_info_type
*xt_seg_info
;
10619 xtensa_block_info
**xt_blocks
;
10620 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10622 prop_sec
->output_section
= prop_sec
;
10623 subseg_set (prop_sec
, 0);
10624 xt_seg_info
= seg_info (prop_sec
);
10625 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10627 /* Walk over all of the frchains here and add new sections. */
10628 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10632 /* Now we fill them out.... */
10634 for (seclist
= &stdoutput
->sections
;
10635 seclist
&& *seclist
;
10636 seclist
= &(*seclist
)->next
)
10638 segment_info_type
*seginfo
;
10639 xtensa_block_info
*block
;
10640 segT sec
= *seclist
;
10642 seginfo
= seg_info (sec
);
10643 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10647 xtensa_block_info
*cur_block
;
10649 bfd_size_type rec_size
;
10651 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10654 rec_size
= num_recs
* (8 + 4);
10655 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10656 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10663 subseg_set (sec
, 0);
10664 frag_data
= frag_more (rec_size
);
10666 for (i
= 0; i
< num_recs
; i
++)
10670 /* Write the fixup. */
10671 gas_assert (cur_block
);
10672 fix
= fix_new (frag_now
, i
* 12, 4,
10673 section_symbol (cur_block
->sec
),
10675 FALSE
, BFD_RELOC_32
);
10676 fix
->fx_file
= "<internal>";
10679 /* Write the length. */
10680 md_number_to_chars (&frag_data
[4 + i
* 12],
10681 cur_block
->size
, 4);
10682 md_number_to_chars (&frag_data
[8 + i
* 12],
10683 frag_flags_to_number (&cur_block
->flags
),
10684 sizeof (flagword
));
10685 cur_block
= cur_block
->next
;
10687 frag_wane (frag_now
);
10689 frag_wane (frag_now
);
10697 exclude_section_from_property_tables (segT sec
)
10699 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
10701 /* Sections that don't contribute to the memory footprint are excluded. */
10702 if ((flags
& SEC_DEBUGGING
)
10703 || !(flags
& SEC_ALLOC
)
10704 || (flags
& SEC_MERGE
))
10707 /* Linker cie and fde optimizations mess up property entries for
10708 eh_frame sections, but there is nothing inside them relevant to
10709 property tables anyway. */
10710 if (strcmp (sec
->name
, ".eh_frame") == 0)
10718 section_has_property (segT sec
, frag_predicate property_function
)
10720 segment_info_type
*seginfo
= seg_info (sec
);
10723 if (seginfo
&& seginfo
->frchainP
)
10725 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10727 if (property_function (fragP
)
10728 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10737 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10739 segment_info_type
*seginfo
= seg_info (sec
);
10742 if (seginfo
&& seginfo
->frchainP
)
10744 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10746 frag_flags prop_flags
;
10747 property_function (fragP
, &prop_flags
);
10748 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10756 /* Two types of block sections exist right now: literal and insns. */
10759 add_xt_block_frags (segT sec
,
10760 xtensa_block_info
**xt_block
,
10761 frag_predicate property_function
,
10762 frag_predicate end_property_function
)
10766 /* Build it if needed. */
10767 while (*xt_block
!= NULL
)
10768 xt_block
= &(*xt_block
)->next
;
10769 /* We are either at NULL at the beginning or at the end. */
10771 /* Walk through the frags. */
10772 if (seg_info (sec
)->frchainP
)
10774 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10776 fragP
= fragP
->fr_next
)
10778 if (property_function (fragP
)
10779 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10781 if (*xt_block
!= NULL
)
10783 if ((*xt_block
)->offset
+ (*xt_block
)->size
10784 == fragP
->fr_address
)
10785 (*xt_block
)->size
+= fragP
->fr_fix
;
10787 xt_block
= &((*xt_block
)->next
);
10789 if (*xt_block
== NULL
)
10791 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10792 xmalloc (sizeof (xtensa_block_info
));
10793 new_block
->sec
= sec
;
10794 new_block
->offset
= fragP
->fr_address
;
10795 new_block
->size
= fragP
->fr_fix
;
10796 new_block
->next
= NULL
;
10797 xtensa_frag_flags_init (&new_block
->flags
);
10798 *xt_block
= new_block
;
10800 if (end_property_function
10801 && end_property_function (fragP
))
10803 xt_block
= &((*xt_block
)->next
);
10811 /* Break the encapsulation of add_xt_prop_frags here. */
10814 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10816 if (prop_flags
->is_literal
10817 || prop_flags
->is_insn
10818 || prop_flags
->is_data
10819 || prop_flags
->is_unreachable
)
10826 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10828 memset (prop_flags
, 0, sizeof (frag_flags
));
10833 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10835 xtensa_frag_flags_init (prop_flags
);
10836 if (fragP
->tc_frag_data
.is_literal
)
10837 prop_flags
->is_literal
= TRUE
;
10838 if (fragP
->tc_frag_data
.is_specific_opcode
10839 || fragP
->tc_frag_data
.is_no_transform
)
10841 prop_flags
->is_no_transform
= TRUE
;
10842 if (xtensa_frag_flags_is_empty (prop_flags
))
10843 prop_flags
->is_data
= TRUE
;
10845 if (fragP
->tc_frag_data
.is_unreachable
)
10846 prop_flags
->is_unreachable
= TRUE
;
10847 else if (fragP
->tc_frag_data
.is_insn
)
10849 prop_flags
->is_insn
= TRUE
;
10850 if (fragP
->tc_frag_data
.is_loop_target
)
10851 prop_flags
->insn
.is_loop_target
= TRUE
;
10852 if (fragP
->tc_frag_data
.is_branch_target
)
10853 prop_flags
->insn
.is_branch_target
= TRUE
;
10854 if (fragP
->tc_frag_data
.is_no_density
)
10855 prop_flags
->insn
.is_no_density
= TRUE
;
10856 if (fragP
->tc_frag_data
.use_absolute_literals
)
10857 prop_flags
->insn
.is_abslit
= TRUE
;
10859 if (fragP
->tc_frag_data
.is_align
)
10861 prop_flags
->is_align
= TRUE
;
10862 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10863 if (xtensa_frag_flags_is_empty (prop_flags
))
10864 prop_flags
->is_data
= TRUE
;
10870 frag_flags_to_number (const frag_flags
*prop_flags
)
10873 if (prop_flags
->is_literal
)
10874 num
|= XTENSA_PROP_LITERAL
;
10875 if (prop_flags
->is_insn
)
10876 num
|= XTENSA_PROP_INSN
;
10877 if (prop_flags
->is_data
)
10878 num
|= XTENSA_PROP_DATA
;
10879 if (prop_flags
->is_unreachable
)
10880 num
|= XTENSA_PROP_UNREACHABLE
;
10881 if (prop_flags
->insn
.is_loop_target
)
10882 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10883 if (prop_flags
->insn
.is_branch_target
)
10885 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10886 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10889 if (prop_flags
->insn
.is_no_density
)
10890 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10891 if (prop_flags
->is_no_transform
)
10892 num
|= XTENSA_PROP_NO_TRANSFORM
;
10893 if (prop_flags
->insn
.is_no_reorder
)
10894 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10895 if (prop_flags
->insn
.is_abslit
)
10896 num
|= XTENSA_PROP_INSN_ABSLIT
;
10898 if (prop_flags
->is_align
)
10900 num
|= XTENSA_PROP_ALIGN
;
10901 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10909 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10910 const frag_flags
*prop_flags_2
)
10912 /* Cannot combine with an end marker. */
10914 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10916 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10918 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10921 if (prop_flags_1
->is_insn
)
10923 /* Properties of the beginning of the frag. */
10924 if (prop_flags_2
->insn
.is_loop_target
)
10926 if (prop_flags_2
->insn
.is_branch_target
)
10928 if (prop_flags_1
->insn
.is_no_density
!=
10929 prop_flags_2
->insn
.is_no_density
)
10931 if (prop_flags_1
->is_no_transform
!=
10932 prop_flags_2
->is_no_transform
)
10934 if (prop_flags_1
->insn
.is_no_reorder
!=
10935 prop_flags_2
->insn
.is_no_reorder
)
10937 if (prop_flags_1
->insn
.is_abslit
!=
10938 prop_flags_2
->insn
.is_abslit
)
10942 if (prop_flags_1
->is_align
)
10950 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10953 unsigned align_bits
;
10955 if (!xt_block
->flags
.is_align
)
10956 return xt_block
->size
;
10958 end_addr
= xt_block
->offset
+ xt_block
->size
;
10959 align_bits
= xt_block
->flags
.alignment
;
10960 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10961 return end_addr
- xt_block
->offset
;
10966 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10967 const xtensa_block_info
*xt_block_2
)
10969 if (xt_block
->sec
!= xt_block_2
->sec
)
10971 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10972 != xt_block_2
->offset
)
10975 if (xt_block_2
->size
== 0
10976 && (!xt_block_2
->flags
.is_unreachable
10977 || xt_block
->flags
.is_unreachable
))
10979 if (xt_block_2
->flags
.is_align
10980 && xt_block
->flags
.is_align
)
10982 /* Nothing needed. */
10983 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10988 if (xt_block_2
->flags
.is_align
)
10990 /* Push alignment to previous entry. */
10991 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10992 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10997 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10998 &xt_block_2
->flags
))
11001 xt_block
->size
+= xt_block_2
->size
;
11003 if (xt_block_2
->flags
.is_align
)
11005 xt_block
->flags
.is_align
= TRUE
;
11006 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11014 add_xt_prop_frags (segT sec
,
11015 xtensa_block_info
**xt_block
,
11016 frag_flags_fn property_function
)
11020 /* Build it if needed. */
11021 while (*xt_block
!= NULL
)
11023 xt_block
= &(*xt_block
)->next
;
11025 /* We are either at NULL at the beginning or at the end. */
11027 /* Walk through the frags. */
11028 if (seg_info (sec
)->frchainP
)
11030 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11031 fragP
= fragP
->fr_next
)
11033 xtensa_block_info tmp_block
;
11034 tmp_block
.sec
= sec
;
11035 tmp_block
.offset
= fragP
->fr_address
;
11036 tmp_block
.size
= fragP
->fr_fix
;
11037 tmp_block
.next
= NULL
;
11038 property_function (fragP
, &tmp_block
.flags
);
11040 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11041 /* && fragP->fr_fix != 0) */
11043 if ((*xt_block
) == NULL
11044 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11046 xtensa_block_info
*new_block
;
11047 if ((*xt_block
) != NULL
)
11048 xt_block
= &(*xt_block
)->next
;
11049 new_block
= (xtensa_block_info
*)
11050 xmalloc (sizeof (xtensa_block_info
));
11051 *new_block
= tmp_block
;
11052 *xt_block
= new_block
;
11060 /* op_placement_info_table */
11062 /* op_placement_info makes it easier to determine which
11063 ops can go in which slots. */
11066 init_op_placement_info_table (void)
11068 xtensa_isa isa
= xtensa_default_isa
;
11069 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11070 xtensa_opcode opcode
;
11073 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11075 op_placement_table
= (op_placement_info_table
)
11076 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11077 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11079 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11081 op_placement_info
*opi
= &op_placement_table
[opcode
];
11082 /* FIXME: Make tinsn allocation dynamic. */
11083 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11084 as_fatal (_("too many operands in instruction"));
11085 opi
->narrowest
= XTENSA_UNDEFINED
;
11086 opi
->narrowest_size
= 0x7F;
11087 opi
->narrowest_slot
= 0;
11089 opi
->num_formats
= 0;
11091 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11093 opi
->slots
[fmt
] = 0;
11094 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11096 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11098 int fmt_length
= xtensa_format_length (isa
, fmt
);
11100 set_bit (fmt
, opi
->formats
);
11101 set_bit (slot
, opi
->slots
[fmt
]);
11102 if (fmt_length
< opi
->narrowest_size
11103 || (fmt_length
== opi
->narrowest_size
11104 && (xtensa_format_num_slots (isa
, fmt
)
11105 < xtensa_format_num_slots (isa
,
11108 opi
->narrowest
= fmt
;
11109 opi
->narrowest_size
= fmt_length
;
11110 opi
->narrowest_slot
= slot
;
11115 opi
->num_formats
++;
11118 xtensa_insnbuf_free (isa
, ibuf
);
11123 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11125 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11129 /* If the opcode is available in a single slot format, return its size. */
11132 xg_get_single_size (xtensa_opcode opcode
)
11134 return op_placement_table
[opcode
].narrowest_size
;
11138 static xtensa_format
11139 xg_get_single_format (xtensa_opcode opcode
)
11141 return op_placement_table
[opcode
].narrowest
;
11146 xg_get_single_slot (xtensa_opcode opcode
)
11148 return op_placement_table
[opcode
].narrowest_slot
;
11152 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11155 istack_init (IStack
*stack
)
11157 memset (stack
, 0, sizeof (IStack
));
11163 istack_empty (IStack
*stack
)
11165 return (stack
->ninsn
== 0);
11170 istack_full (IStack
*stack
)
11172 return (stack
->ninsn
== MAX_ISTACK
);
11176 /* Return a pointer to the top IStack entry.
11177 It is an error to call this if istack_empty () is TRUE. */
11180 istack_top (IStack
*stack
)
11182 int rec
= stack
->ninsn
- 1;
11183 gas_assert (!istack_empty (stack
));
11184 return &stack
->insn
[rec
];
11188 /* Add a new TInsn to an IStack.
11189 It is an error to call this if istack_full () is TRUE. */
11192 istack_push (IStack
*stack
, TInsn
*insn
)
11194 int rec
= stack
->ninsn
;
11195 gas_assert (!istack_full (stack
));
11196 stack
->insn
[rec
] = *insn
;
11201 /* Clear space for the next TInsn on the IStack and return a pointer
11202 to it. It is an error to call this if istack_full () is TRUE. */
11205 istack_push_space (IStack
*stack
)
11207 int rec
= stack
->ninsn
;
11209 gas_assert (!istack_full (stack
));
11210 insn
= &stack
->insn
[rec
];
11217 /* Remove the last pushed instruction. It is an error to call this if
11218 istack_empty () returns TRUE. */
11221 istack_pop (IStack
*stack
)
11223 int rec
= stack
->ninsn
- 1;
11224 gas_assert (!istack_empty (stack
));
11226 tinsn_init (&stack
->insn
[rec
]);
11230 /* TInsn functions. */
11233 tinsn_init (TInsn
*dst
)
11235 memset (dst
, 0, sizeof (TInsn
));
11239 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11242 tinsn_has_symbolic_operands (const TInsn
*insn
)
11245 int n
= insn
->ntok
;
11247 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11249 for (i
= 0; i
< n
; ++i
)
11251 switch (insn
->tok
[i
].X_op
)
11265 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11267 xtensa_isa isa
= xtensa_default_isa
;
11269 int n
= insn
->ntok
;
11271 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11273 for (i
= 0; i
< n
; ++i
)
11275 switch (insn
->tok
[i
].X_op
)
11283 /* Errors for these types are caught later. */
11288 /* Symbolic immediates are only allowed on the last immediate
11289 operand. At this time, CONST16 is the only opcode where we
11290 support non-PC-relative relocations. */
11291 if (i
!= get_relaxable_immed (insn
->opcode
)
11292 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11293 && insn
->opcode
!= xtensa_const16_opcode
))
11295 as_bad (_("invalid symbolic operand"));
11304 /* For assembly code with complex expressions (e.g. subtraction),
11305 we have to build them in the literal pool so that
11306 their results are calculated correctly after relaxation.
11307 The relaxation only handles expressions that
11308 boil down to SYMBOL + OFFSET. */
11311 tinsn_has_complex_operands (const TInsn
*insn
)
11314 int n
= insn
->ntok
;
11315 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11316 for (i
= 0; i
< n
; ++i
)
11318 switch (insn
->tok
[i
].X_op
)
11334 /* Encode a TInsn opcode and its constant operands into slotbuf.
11335 Return TRUE if there is a symbol in the immediate field. This
11336 function assumes that:
11337 1) The number of operands are correct.
11338 2) The insn_type is ITYPE_INSN.
11339 3) The opcode can be encoded in the specified format and slot.
11340 4) Operands are either O_constant or O_symbol, and all constants fit. */
11343 tinsn_to_slotbuf (xtensa_format fmt
,
11346 xtensa_insnbuf slotbuf
)
11348 xtensa_isa isa
= xtensa_default_isa
;
11349 xtensa_opcode opcode
= tinsn
->opcode
;
11350 bfd_boolean has_fixup
= FALSE
;
11351 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11354 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11355 if (noperands
!= tinsn
->ntok
)
11356 as_fatal (_("operand number mismatch"));
11358 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11360 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11361 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11365 for (i
= 0; i
< noperands
; i
++)
11367 expressionS
*exp
= &tinsn
->tok
[i
];
11376 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11378 /* The register number has already been checked in
11379 expression_maybe_register, so we don't need to check here. */
11380 opnd_value
= exp
->X_add_number
;
11381 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11382 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11385 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11389 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11391 as_where (&file_name
, &line
);
11392 /* It is a constant and we called this function
11393 then we have to try to fit it. */
11394 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11395 exp
->X_add_number
, file_name
, line
);
11408 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11409 into a multi-slot instruction, fill the other slots with NOPs.
11410 Return TRUE if there is a symbol in the immediate field. See also the
11411 assumptions listed for tinsn_to_slotbuf. */
11414 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11416 static xtensa_insnbuf slotbuf
= 0;
11417 static vliw_insn vinsn
;
11418 xtensa_isa isa
= xtensa_default_isa
;
11419 bfd_boolean has_fixup
= FALSE
;
11424 slotbuf
= xtensa_insnbuf_alloc (isa
);
11425 xg_init_vinsn (&vinsn
);
11428 xg_clear_vinsn (&vinsn
);
11430 bundle_tinsn (tinsn
, &vinsn
);
11432 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11434 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11436 /* Only one slot may have a fix-up because the rest contains NOPs. */
11438 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11439 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11446 /* Check the instruction arguments. Return TRUE on failure. */
11449 tinsn_check_arguments (const TInsn
*insn
)
11451 xtensa_isa isa
= xtensa_default_isa
;
11452 xtensa_opcode opcode
= insn
->opcode
;
11453 xtensa_regfile t1_regfile
, t2_regfile
;
11454 int t1_reg
, t2_reg
;
11455 int t1_base_reg
, t1_last_reg
;
11456 int t2_base_reg
, t2_last_reg
;
11457 char t1_inout
, t2_inout
;
11460 if (opcode
== XTENSA_UNDEFINED
)
11462 as_bad (_("invalid opcode"));
11466 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11468 as_bad (_("too few operands"));
11472 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11474 as_bad (_("too many operands"));
11478 /* Check registers. */
11479 for (j
= 0; j
< insn
->ntok
; j
++)
11481 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
11484 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
11485 t2_base_reg
= insn
->tok
[j
].X_add_number
;
11487 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
11489 for (i
= 0; i
< insn
->ntok
; i
++)
11494 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
11497 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
11499 if (t1_regfile
!= t2_regfile
)
11502 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
11503 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
11505 t1_base_reg
= insn
->tok
[i
].X_add_number
;
11506 t1_last_reg
= (t1_base_reg
11507 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
11509 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
11511 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
11513 if (t1_reg
!= t2_reg
)
11516 if (t1_inout
!= 'i' && t2_inout
!= 'i')
11518 as_bad (_("multiple writes to the same register"));
11529 /* Load an instruction from its encoded form. */
11532 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11536 xg_init_vinsn (&vinsn
);
11537 vinsn_from_chars (&vinsn
, f
);
11539 *tinsn
= vinsn
.slots
[slot
];
11540 xg_free_vinsn (&vinsn
);
11545 tinsn_from_insnbuf (TInsn
*tinsn
,
11546 xtensa_insnbuf slotbuf
,
11551 xtensa_isa isa
= xtensa_default_isa
;
11553 /* Find the immed. */
11554 tinsn_init (tinsn
);
11555 tinsn
->insn_type
= ITYPE_INSN
;
11556 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11557 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11558 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11559 for (i
= 0; i
< tinsn
->ntok
; i
++)
11561 set_expr_const (&tinsn
->tok
[i
],
11562 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11563 tinsn
->opcode
, i
));
11568 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11571 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11573 xtensa_opcode opcode
= tinsn
->opcode
;
11576 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11578 opnum
= get_relaxable_immed (opcode
);
11579 gas_assert (opnum
>= 0);
11580 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11581 fragP
->tc_frag_data
.slot_symbols
[slot
],
11582 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11584 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
11589 get_num_stack_text_bytes (IStack
*istack
)
11592 int text_bytes
= 0;
11594 for (i
= 0; i
< istack
->ninsn
; i
++)
11596 TInsn
*tinsn
= &istack
->insn
[i
];
11597 if (tinsn
->insn_type
== ITYPE_INSN
)
11598 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11605 get_num_stack_literal_bytes (IStack
*istack
)
11610 for (i
= 0; i
< istack
->ninsn
; i
++)
11612 TInsn
*tinsn
= &istack
->insn
[i
];
11613 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11620 /* vliw_insn functions. */
11623 xg_init_vinsn (vliw_insn
*v
)
11626 xtensa_isa isa
= xtensa_default_isa
;
11628 xg_clear_vinsn (v
);
11630 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11631 if (v
->insnbuf
== NULL
)
11632 as_fatal (_("out of memory"));
11634 for (i
= 0; i
< config_max_slots
; i
++)
11636 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11637 if (v
->slotbuf
[i
] == NULL
)
11638 as_fatal (_("out of memory"));
11644 xg_clear_vinsn (vliw_insn
*v
)
11648 memset (v
, 0, offsetof (vliw_insn
, slots
)
11649 + sizeof(TInsn
) * config_max_slots
);
11651 v
->format
= XTENSA_UNDEFINED
;
11653 v
->inside_bundle
= FALSE
;
11655 if (xt_saved_debug_type
!= DEBUG_NONE
)
11656 debug_type
= xt_saved_debug_type
;
11658 for (i
= 0; i
< config_max_slots
; i
++)
11659 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11664 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
11667 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
11668 dst
->insnbuf
= src
->insnbuf
;
11669 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
11674 vinsn_has_specific_opcodes (vliw_insn
*v
)
11678 for (i
= 0; i
< v
->num_slots
; i
++)
11680 if (v
->slots
[i
].is_specific_opcode
)
11688 xg_free_vinsn (vliw_insn
*v
)
11691 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11692 for (i
= 0; i
< config_max_slots
; i
++)
11693 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11697 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11698 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11701 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11704 bfd_boolean record_fixup
)
11706 xtensa_isa isa
= xtensa_default_isa
;
11707 xtensa_format fmt
= vinsn
->format
;
11708 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11710 bfd_boolean has_fixup
= FALSE
;
11712 xtensa_format_encode (isa
, fmt
, insnbuf
);
11714 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11716 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11717 expressionS
*extra_arg
= &tinsn
->extra_arg
;
11718 bfd_boolean tinsn_has_fixup
=
11719 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11720 vinsn
->slotbuf
[slot
]);
11722 xtensa_format_set_slot (isa
, fmt
, slot
,
11723 insnbuf
, vinsn
->slotbuf
[slot
]);
11724 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
11726 if (vinsn
->num_slots
!= 1)
11727 as_bad (_("TLS relocation not allowed in FLIX bundle"));
11728 else if (record_fixup
)
11729 /* Instructions that generate TLS relocations should always be
11730 relaxed in the front-end. If "record_fixup" is set, then this
11731 function is being called during back-end relaxation, so flag
11732 the unexpected behavior as an error. */
11733 as_bad (_("unexpected TLS relocation"));
11735 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
11736 xtensa_format_length (isa
, fmt
),
11737 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
11738 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
11740 if (tinsn_has_fixup
)
11743 xtensa_opcode opcode
= tinsn
->opcode
;
11744 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11747 for (i
= 0; i
< noperands
; i
++)
11749 expressionS
* exp
= &tinsn
->tok
[i
];
11755 if (get_relaxable_immed (opcode
) == i
)
11757 /* Add a fix record for the instruction, except if this
11758 function is being called prior to relaxation, i.e.,
11759 if record_fixup is false, and the instruction might
11760 be relaxed later. */
11762 || tinsn
->is_specific_opcode
11763 || !xg_is_relaxable_insn (tinsn
, 0))
11765 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
11766 frag_offset
- fragP
->fr_literal
);
11770 if (exp
->X_op
!= O_symbol
)
11771 as_bad (_("invalid operand"));
11772 tinsn
->symbol
= exp
->X_add_symbol
;
11773 tinsn
->offset
= exp
->X_add_number
;
11777 as_bad (_("symbolic operand not allowed"));
11785 as_bad (_("expression too complex"));
11797 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11799 static xtensa_insnbuf insnbuf
= NULL
;
11800 static xtensa_insnbuf slotbuf
= NULL
;
11803 xtensa_isa isa
= xtensa_default_isa
;
11807 insnbuf
= xtensa_insnbuf_alloc (isa
);
11808 slotbuf
= xtensa_insnbuf_alloc (isa
);
11811 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11812 fmt
= xtensa_format_decode (isa
, insnbuf
);
11813 if (fmt
== XTENSA_UNDEFINED
)
11814 as_fatal (_("cannot decode instruction format"));
11815 vinsn
->format
= fmt
;
11816 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11818 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11820 TInsn
*tinsn
= &vinsn
->slots
[i
];
11821 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11822 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11827 /* Expression utilities. */
11829 /* Return TRUE if the expression is an integer constant. */
11832 expr_is_const (const expressionS
*s
)
11834 return (s
->X_op
== O_constant
);
11838 /* Get the expression constant.
11839 Calling this is illegal if expr_is_const () returns TRUE. */
11842 get_expr_const (const expressionS
*s
)
11844 gas_assert (expr_is_const (s
));
11845 return s
->X_add_number
;
11849 /* Set the expression to a constant value. */
11852 set_expr_const (expressionS
*s
, offsetT val
)
11854 s
->X_op
= O_constant
;
11855 s
->X_add_number
= val
;
11856 s
->X_add_symbol
= NULL
;
11857 s
->X_op_symbol
= NULL
;
11862 expr_is_register (const expressionS
*s
)
11864 return (s
->X_op
== O_register
);
11868 /* Get the expression constant.
11869 Calling this is illegal if expr_is_const () returns TRUE. */
11872 get_expr_register (const expressionS
*s
)
11874 gas_assert (expr_is_register (s
));
11875 return s
->X_add_number
;
11879 /* Set the expression to a symbol + constant offset. */
11882 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11884 s
->X_op
= O_symbol
;
11885 s
->X_add_symbol
= sym
;
11886 s
->X_op_symbol
= NULL
; /* unused */
11887 s
->X_add_number
= offset
;
11891 /* Return TRUE if the two expressions are equal. */
11894 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11896 if (s1
->X_op
!= s2
->X_op
)
11898 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11900 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11902 if (s1
->X_add_number
!= s2
->X_add_number
)
11909 copy_expr (expressionS
*dst
, const expressionS
*src
)
11911 memcpy (dst
, src
, sizeof (expressionS
));
11915 /* Support for the "--rename-section" option. */
11917 struct rename_section_struct
11921 struct rename_section_struct
*next
;
11924 static struct rename_section_struct
*section_rename
;
11927 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11928 entries to the section_rename list. Note: Specifying multiple
11929 renamings separated by colons is not documented and is retained only
11930 for backward compatibility. */
11933 build_section_rename (const char *arg
)
11935 struct rename_section_struct
*r
;
11936 char *this_arg
= NULL
;
11937 char *next_arg
= NULL
;
11939 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11941 char *old_name
, *new_name
;
11945 next_arg
= strchr (this_arg
, ':');
11953 old_name
= this_arg
;
11954 new_name
= strchr (this_arg
, '=');
11956 if (*old_name
== '\0')
11958 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11961 if (!new_name
|| new_name
[1] == '\0')
11963 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11970 /* Check for invalid section renaming. */
11971 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11973 if (strcmp (r
->old_name
, old_name
) == 0)
11974 as_bad (_("section %s renamed multiple times"), old_name
);
11975 if (strcmp (r
->new_name
, new_name
) == 0)
11976 as_bad (_("multiple sections remapped to output section %s"),
11981 r
= (struct rename_section_struct
*)
11982 xmalloc (sizeof (struct rename_section_struct
));
11983 r
->old_name
= xstrdup (old_name
);
11984 r
->new_name
= xstrdup (new_name
);
11985 r
->next
= section_rename
;
11986 section_rename
= r
;
11992 xtensa_section_rename (char *name
)
11994 struct rename_section_struct
*r
= section_rename
;
11996 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11998 if (strcmp (r
->old_name
, name
) == 0)
11999 return r
->new_name
;