gas/config/tc-xtensa.c

   1 /* tc-xtensa.c -- Assemble Xtensa instructions.
   2    Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include <limits.h>
  23 #include "as.h"
  24 #include "sb.h"
  25 #include "safe-ctype.h"
  26 #include "tc-xtensa.h"
  27 #include "subsegs.h"
  28 #include "xtensa-relax.h"
  29 #include "dwarf2dbg.h"
  30 #include "xtensa-istack.h"
  31 #include "struc-symbol.h"
  32 #include "xtensa-config.h"
  33
  34 /* Provide default values for new configuration settings.  */
  35 #ifndef XSHAL_ABI
  36 #define XSHAL_ABI 0
  37 #endif
  38
  39 #ifndef uint32
  40 #define uint32 unsigned int
  41 #endif
  42 #ifndef int32
  43 #define int32 signed int
  44 #endif
  45
  46 /* Notes:
  47
  48    Naming conventions (used somewhat inconsistently):
  49       The xtensa_ functions are exported
  50       The xg_ functions are internal
  51
  52    We also have a couple of different extensibility mechanisms.
  53    1) The idiom replacement:
  54       This is used when a line is first parsed to
  55       replace an instruction pattern with another instruction
  56       It is currently limited to replacements of instructions
  57       with constant operands.
  58    2) The xtensa-relax.c mechanism that has stronger instruction
  59       replacement patterns.  When an instruction's immediate field
  60       does not fit the next instruction sequence is attempted.
  61       In addition, "narrow" opcodes are supported this way.  */
  62
  63
  64 /* Define characters with special meanings to GAS.  */
  65 const char comment_chars[] = "#";
  66 const char line_comment_chars[] = "#";
  67 const char line_separator_chars[] = ";";
  68 const char EXP_CHARS[] = "eE";
  69 const char FLT_CHARS[] = "rRsSfFdDxXpP";
  70
  71
  72 /* Flags to indicate whether the hardware supports the density and
  73    absolute literals options.  */
  74
  75 bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
  76 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
  77
  78 /* Maximum width we would pad an unreachable frag to get alignment.  */
  79 #define UNREACHABLE_MAX_WIDTH  8
  80
  81 static vliw_insn cur_vinsn;
  82
  83 unsigned xtensa_num_pipe_stages;
  84 unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
  85
  86 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
  87
  88 /* Some functions are only valid in the front end.  This variable
  89    allows us to assert that we haven't crossed over into the
  90    back end.  */
  91 static bfd_boolean past_xtensa_end = FALSE;
  92
  93 /* Flags for properties of the last instruction in a segment.  */
  94 #define FLAG_IS_A0_WRITER       0x1
  95 #define FLAG_IS_BAD_LOOPEND     0x2
  96
  97
  98 /* We define a special segment names ".literal" to place literals
  99    into.  The .fini and .init sections are special because they
 100    contain code that is moved together by the linker.  We give them
 101    their own special .fini.literal and .init.literal sections.  */
 102
 103 #define LITERAL_SECTION_NAME            xtensa_section_rename (".literal")
 104 #define LIT4_SECTION_NAME               xtensa_section_rename (".lit4")
 105 #define INIT_SECTION_NAME               xtensa_section_rename (".init")
 106 #define FINI_SECTION_NAME               xtensa_section_rename (".fini")
 107
 108
 109 /* This type is used for the directive_stack to keep track of the
 110    state of the literal collection pools.  If lit_prefix is set, it is
 111    used to determine the literal section names; otherwise, the literal
 112    sections are determined based on the current text section.  The
 113    lit_seg and lit4_seg fields cache these literal sections, with the
 114    current_text_seg field used a tag to indicate whether the cached
 115    values are valid.  */
 116
 117 typedef struct lit_state_struct
 118 {
 119   char *lit_prefix;
 120   segT current_text_seg;
 121   segT lit_seg;
 122   segT lit4_seg;
 123 } lit_state;
 124
 125 static lit_state default_lit_sections;
 126
 127
 128 /* We keep a list of literal segments.  The seg_list type is the node
 129    for this list.  The literal_head pointer is the head of the list,
 130    with the literal_head_h dummy node at the start.  */
 131
 132 typedef struct seg_list_struct
 133 {
 134   struct seg_list_struct *next;
 135   segT seg;
 136 } seg_list;
 137
 138 static seg_list literal_head_h;
 139 static seg_list *literal_head = &literal_head_h;
 140
 141
 142 /* Lists of symbols.  We keep a list of symbols that label the current
 143    instruction, so that we can adjust the symbols when inserting alignment
 144    for various instructions.  We also keep a list of all the symbols on
 145    literals, so that we can fix up those symbols when the literals are
 146    later moved into the text sections.  */
 147
 148 typedef struct sym_list_struct
 149 {
 150   struct sym_list_struct *next;
 151   symbolS *sym;
 152 } sym_list;
 153
 154 static sym_list *insn_labels = NULL;
 155 static sym_list *free_insn_labels = NULL;
 156 static sym_list *saved_insn_labels = NULL;
 157
 158 static sym_list *literal_syms;
 159
 160
 161 /* Flags to determine whether to prefer const16 or l32r
 162    if both options are available.  */
 163 int prefer_const16 = 0;
 164 int prefer_l32r = 0;
 165
 166 /* Global flag to indicate when we are emitting literals.  */
 167 int generating_literals = 0;
 168
 169 /* The following PROPERTY table definitions are copied from
 170    <elf/xtensa.h> and must be kept in sync with the code there.  */
 171
 172 /* Flags in the property tables to specify whether blocks of memory
 173    are literals, instructions, data, or unreachable.  For
 174    instructions, blocks that begin loop targets and branch targets are
 175    designated.  Blocks that do not allow density, instruction
 176    reordering or transformation are also specified.  Finally, for
 177    branch targets, branch target alignment priority is included.
 178    Alignment of the next block is specified in the current block
 179    and the size of the current block does not include any fill required
 180    to align to the next block.  */
 181
 182 #define XTENSA_PROP_LITERAL             0x00000001
 183 #define XTENSA_PROP_INSN                0x00000002
 184 #define XTENSA_PROP_DATA                0x00000004
 185 #define XTENSA_PROP_UNREACHABLE         0x00000008
 186 /* Instruction only properties at beginning of code.  */
 187 #define XTENSA_PROP_INSN_LOOP_TARGET    0x00000010
 188 #define XTENSA_PROP_INSN_BRANCH_TARGET  0x00000020
 189 /* Instruction only properties about code.  */
 190 #define XTENSA_PROP_INSN_NO_DENSITY     0x00000040
 191 #define XTENSA_PROP_INSN_NO_REORDER     0x00000080
 192 /* Historically, NO_TRANSFORM was a property of instructions,
 193    but it should apply to literals under certain circumstances.  */
 194 #define XTENSA_PROP_NO_TRANSFORM        0x00000100
 195
 196 /*  Branch target alignment information.  This transmits information
 197     to the linker optimization about the priority of aligning a
 198     particular block for branch target alignment: None, low priority,
 199     high priority, or required.  These only need to be checked in
 200     instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
 201     Common usage is
 202
 203     switch (GET_XTENSA_PROP_BT_ALIGN (flags))
 204     case XTENSA_PROP_BT_ALIGN_NONE:
 205     case XTENSA_PROP_BT_ALIGN_LOW:
 206     case XTENSA_PROP_BT_ALIGN_HIGH:
 207     case XTENSA_PROP_BT_ALIGN_REQUIRE:
 208 */
 209 #define XTENSA_PROP_BT_ALIGN_MASK       0x00000600
 210
 211 /* No branch target alignment.  */
 212 #define XTENSA_PROP_BT_ALIGN_NONE       0x0
 213 /* Low priority branch target alignment.  */
 214 #define XTENSA_PROP_BT_ALIGN_LOW        0x1
 215 /* High priority branch target alignment.  */
 216 #define XTENSA_PROP_BT_ALIGN_HIGH       0x2
 217 /* Required branch target alignment.  */
 218 #define XTENSA_PROP_BT_ALIGN_REQUIRE    0x3
 219
 220 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
 221   (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
 222 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
 223   (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
 224     (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
 225
 226
 227 /* Alignment is specified in the block BEFORE the one that needs
 228    alignment.  Up to 5 bits.  Use GET_XTENSA_PROP_ALIGNMENT(flags) to
 229    get the required alignment specified as a power of 2.  Use
 230    SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
 231    alignment.  Be careful of side effects since the SET will evaluate
 232    flags twice.  Also, note that the SIZE of a block in the property
 233    table does not include the alignment size, so the alignment fill
 234    must be calculated to determine if two blocks are contiguous.
 235    TEXT_ALIGN is not currently implemented but is a placeholder for a
 236    possible future implementation.  */
 237
 238 #define XTENSA_PROP_ALIGN               0x00000800
 239
 240 #define XTENSA_PROP_ALIGNMENT_MASK      0x0001f000
 241
 242 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
 243   (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
 244 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
 245   (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
 246     (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
 247
 248 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
 249
 250
 251 /* Structure for saving instruction and alignment per-fragment data
 252    that will be written to the object file.  This structure is
 253    equivalent to the actual data that will be written out to the file
 254    but is easier to use.   We provide a conversion to file flags
 255    in frag_flags_to_number.  */
 256
 257 typedef struct frag_flags_struct frag_flags;
 258
 259 struct frag_flags_struct
 260 {
 261   /* is_literal should only be used after xtensa_move_literals.
 262      If you need to check if you are generating a literal fragment,
 263      then use the generating_literals global.  */
 264
 265   unsigned is_literal : 1;
 266   unsigned is_insn : 1;
 267   unsigned is_data : 1;
 268   unsigned is_unreachable : 1;
 269
 270   /* is_specific_opcode implies no_transform.  */
 271   unsigned is_no_transform : 1;
 272
 273   struct
 274   {
 275     unsigned is_loop_target : 1;
 276     unsigned is_branch_target : 1; /* Branch targets have a priority.  */
 277     unsigned bt_align_priority : 2;
 278
 279     unsigned is_no_density : 1;
 280     /* no_longcalls flag does not need to be placed in the object file.  */
 281
 282     unsigned is_no_reorder : 1;
 283
 284     /* Uses absolute literal addressing for l32r.  */
 285     unsigned is_abslit : 1;
 286   } insn;
 287   unsigned is_align : 1;
 288   unsigned alignment : 5;
 289 };
 290
 291
 292 /* Structure for saving information about a block of property data
 293    for frags that have the same flags.  */
 294 struct xtensa_block_info_struct
 295 {
 296   segT sec;
 297   bfd_vma offset;
 298   size_t size;
 299   frag_flags flags;
 300   struct xtensa_block_info_struct *next;
 301 };
 302
 303
 304 /* Structure for saving the current state before emitting literals.  */
 305 typedef struct emit_state_struct
 306 {
 307   const char *name;
 308   segT now_seg;
 309   subsegT now_subseg;
 310   int generating_literals;
 311 } emit_state;
 312
 313
 314 /* Opcode placement information */
 315
 316 typedef unsigned long long bitfield;
 317 #define bit_is_set(bit, bf)     ((bf) & (0x01ll << (bit)))
 318 #define set_bit(bit, bf)        ((bf) |= (0x01ll << (bit)))
 319 #define clear_bit(bit, bf)      ((bf) &= ~(0x01ll << (bit)))
 320
 321 #define MAX_FORMATS 32
 322
 323 typedef struct op_placement_info_struct
 324 {
 325   int num_formats;
 326   /* A number describing how restrictive the issue is for this
 327      opcode.  For example, an opcode that fits lots of different
 328      formats has a high freedom, as does an opcode that fits
 329      only one format but many slots in that format.  The most
 330      restrictive is the opcode that fits only one slot in one
 331      format.  */
 332   int issuef;
 333   xtensa_format narrowest;
 334   char narrowest_size;
 335   char narrowest_slot;
 336
 337   /* formats is a bitfield with the Nth bit set
 338      if the opcode fits in the Nth xtensa_format.  */
 339   bitfield formats;
 340
 341   /* slots[N]'s Mth bit is set if the op fits in the
 342      Mth slot of the Nth xtensa_format.  */
 343   bitfield slots[MAX_FORMATS];
 344
 345   /* A count of the number of slots in a given format
 346      an op can fit (i.e., the bitcount of the slot field above).  */
 347   char slots_in_format[MAX_FORMATS];
 348
 349 } op_placement_info, *op_placement_info_table;
 350
 351 op_placement_info_table op_placement_table;
 352
 353
 354 /* Extra expression types.  */
 355
 356 #define O_pltrel        O_md1   /* like O_symbol but use a PLT reloc */
 357 #define O_hi16          O_md2   /* use high 16 bits of symbolic value */
 358 #define O_lo16          O_md3   /* use low 16 bits of symbolic value */
 359 #define O_pcrel         O_md4   /* value is a PC-relative offset */
 360 #define O_tlsfunc       O_md5   /* TLS_FUNC/TLSDESC_FN relocation */
 361 #define O_tlsarg        O_md6   /* TLS_ARG/TLSDESC_ARG relocation */
 362 #define O_tlscall       O_md7   /* TLS_CALL relocation */
 363 #define O_tpoff         O_md8   /* TPOFF relocation */
 364 #define O_dtpoff        O_md9   /* DTPOFF relocation */
 365
 366 struct suffix_reloc_map
 367 {
 368   char *suffix;
 369   int length;
 370   bfd_reloc_code_real_type reloc;
 371   unsigned char operator;
 372 };
 373
 374 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
 375
 376 static struct suffix_reloc_map suffix_relocs[] =
 377 {
 378   SUFFIX_MAP ("l",      BFD_RELOC_LO16,                 O_lo16),
 379   SUFFIX_MAP ("h",      BFD_RELOC_HI16,                 O_hi16),
 380   SUFFIX_MAP ("plt",    BFD_RELOC_XTENSA_PLT,           O_pltrel),
 381   SUFFIX_MAP ("pcrel",  BFD_RELOC_32_PCREL,             O_pcrel),
 382   SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC,     O_tlsfunc),
 383   SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG,       O_tlsarg),
 384   SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL,     O_tlscall),
 385   SUFFIX_MAP ("tpoff",  BFD_RELOC_XTENSA_TLS_TPOFF,     O_tpoff),
 386   SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF,    O_dtpoff),
 387   { (char *) 0, 0,      BFD_RELOC_UNUSED,               0 }
 388 };
 389
 390
 391 /* Directives.  */
 392
 393 typedef enum
 394 {
 395   directive_none = 0,
 396   directive_literal,
 397   directive_density,
 398   directive_transform,
 399   directive_freeregs,
 400   directive_longcalls,
 401   directive_literal_prefix,
 402   directive_schedule,
 403   directive_absolute_literals,
 404   directive_last_directive
 405 } directiveE;
 406
 407 typedef struct
 408 {
 409   const char *name;
 410   bfd_boolean can_be_negated;
 411 } directive_infoS;
 412
 413 const directive_infoS directive_info[] =
 414 {
 415   { "none",             FALSE },
 416   { "literal",          FALSE },
 417   { "density",          TRUE },
 418   { "transform",        TRUE },
 419   { "freeregs",         FALSE },
 420   { "longcalls",        TRUE },
 421   { "literal_prefix",   FALSE },
 422   { "schedule",         TRUE },
 423   { "absolute-literals", TRUE }
 424 };
 425
 426 bfd_boolean directive_state[] =
 427 {
 428   FALSE,                        /* none */
 429   FALSE,                        /* literal */
 430 #if !XCHAL_HAVE_DENSITY
 431   FALSE,                        /* density */
 432 #else
 433   TRUE,                         /* density */
 434 #endif
 435   TRUE,                         /* transform */
 436   FALSE,                        /* freeregs */
 437   FALSE,                        /* longcalls */
 438   FALSE,                        /* literal_prefix */
 439   FALSE,                        /* schedule */
 440 #if XSHAL_USE_ABSOLUTE_LITERALS
 441   TRUE                          /* absolute_literals */
 442 #else
 443   FALSE                         /* absolute_literals */
 444 #endif
 445 };
 446
 447
 448 /* Directive functions.  */
 449
 450 static void xtensa_begin_directive (int);
 451 static void xtensa_end_directive (int);
 452 static void xtensa_literal_prefix (void);
 453 static void xtensa_literal_position (int);
 454 static void xtensa_literal_pseudo (int);
 455 static void xtensa_frequency_pseudo (int);
 456 static void xtensa_elf_cons (int);
 457 static void xtensa_leb128 (int);
 458
 459 /* Parsing and Idiom Translation.  */
 460
 461 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
 462
 463 /* Various Other Internal Functions.  */
 464
 465 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
 466 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
 467 static void xtensa_mark_literal_pool_location (void);
 468 static addressT get_expanded_loop_offset (xtensa_opcode);
 469 static fragS *get_literal_pool_location (segT);
 470 static void set_literal_pool_location (segT, fragS *);
 471 static void xtensa_set_frag_assembly_state (fragS *);
 472 static void finish_vinsn (vliw_insn *);
 473 static bfd_boolean emit_single_op (TInsn *);
 474 static int total_frag_text_expansion (fragS *);
 475
 476 /* Alignment Functions.  */
 477
 478 static int get_text_align_power (unsigned);
 479 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
 480 static int branch_align_power (segT);
 481
 482 /* Helpers for xtensa_relax_frag().  */
 483
 484 static long relax_frag_add_nop (fragS *);
 485
 486 /* Accessors for additional per-subsegment information.  */
 487
 488 static unsigned get_last_insn_flags (segT, subsegT);
 489 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
 490 static float get_subseg_total_freq (segT, subsegT);
 491 static float get_subseg_target_freq (segT, subsegT);
 492 static void set_subseg_freq (segT, subsegT, float, float);
 493
 494 /* Segment list functions.  */
 495
 496 static void xtensa_move_literals (void);
 497 static void xtensa_reorder_segments (void);
 498 static void xtensa_switch_to_literal_fragment (emit_state *);
 499 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
 500 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
 501 static void xtensa_restore_emit_state (emit_state *);
 502 static segT cache_literal_section (bfd_boolean);
 503
 504 /* Import from elf32-xtensa.c in BFD library.  */
 505
 506 extern asection *xtensa_make_property_section (asection *, const char *);
 507
 508 /* op_placement_info functions.  */
 509
 510 static void init_op_placement_info_table (void);
 511 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
 512 static int xg_get_single_size (xtensa_opcode);
 513 static xtensa_format xg_get_single_format (xtensa_opcode);
 514 static int xg_get_single_slot (xtensa_opcode);
 515
 516 /* TInsn and IStack functions.  */
 517
 518 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
 519 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
 520 static bfd_boolean tinsn_has_complex_operands (const TInsn *);
 521 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
 522 static bfd_boolean tinsn_check_arguments (const TInsn *);
 523 static void tinsn_from_chars (TInsn *, char *, int);
 524 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
 525 static int get_num_stack_text_bytes (IStack *);
 526 static int get_num_stack_literal_bytes (IStack *);
 527
 528 /* vliw_insn functions.  */
 529
 530 static void xg_init_vinsn (vliw_insn *);
 531 static void xg_copy_vinsn (vliw_insn *, vliw_insn *);
 532 static void xg_clear_vinsn (vliw_insn *);
 533 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
 534 static void xg_free_vinsn (vliw_insn *);
 535 static bfd_boolean vinsn_to_insnbuf
 536   (vliw_insn *, char *, fragS *, bfd_boolean);
 537 static void vinsn_from_chars (vliw_insn *, char *);
 538
 539 /* Expression Utilities.  */
 540
 541 bfd_boolean expr_is_const (const expressionS *);
 542 offsetT get_expr_const (const expressionS *);
 543 void set_expr_const (expressionS *, offsetT);
 544 bfd_boolean expr_is_register (const expressionS *);
 545 offsetT get_expr_register (const expressionS *);
 546 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
 547 bfd_boolean expr_is_equal (expressionS *, expressionS *);
 548 static void copy_expr (expressionS *, const expressionS *);
 549
 550 /* Section renaming.  */
 551
 552 static void build_section_rename (const char *);
 553
 554
 555 /* ISA imported from bfd.  */
 556 extern xtensa_isa xtensa_default_isa;
 557
 558 extern int target_big_endian;
 559
 560 static xtensa_opcode xtensa_addi_opcode;
 561 static xtensa_opcode xtensa_addmi_opcode;
 562 static xtensa_opcode xtensa_call0_opcode;
 563 static xtensa_opcode xtensa_call4_opcode;
 564 static xtensa_opcode xtensa_call8_opcode;
 565 static xtensa_opcode xtensa_call12_opcode;
 566 static xtensa_opcode xtensa_callx0_opcode;
 567 static xtensa_opcode xtensa_callx4_opcode;
 568 static xtensa_opcode xtensa_callx8_opcode;
 569 static xtensa_opcode xtensa_callx12_opcode;
 570 static xtensa_opcode xtensa_const16_opcode;
 571 static xtensa_opcode xtensa_entry_opcode;
 572 static xtensa_opcode xtensa_extui_opcode;
 573 static xtensa_opcode xtensa_movi_opcode;
 574 static xtensa_opcode xtensa_movi_n_opcode;
 575 static xtensa_opcode xtensa_isync_opcode;
 576 static xtensa_opcode xtensa_j_opcode;
 577 static xtensa_opcode xtensa_jx_opcode;
 578 static xtensa_opcode xtensa_l32r_opcode;
 579 static xtensa_opcode xtensa_loop_opcode;
 580 static xtensa_opcode xtensa_loopnez_opcode;
 581 static xtensa_opcode xtensa_loopgtz_opcode;
 582 static xtensa_opcode xtensa_nop_opcode;
 583 static xtensa_opcode xtensa_nop_n_opcode;
 584 static xtensa_opcode xtensa_or_opcode;
 585 static xtensa_opcode xtensa_ret_opcode;
 586 static xtensa_opcode xtensa_ret_n_opcode;
 587 static xtensa_opcode xtensa_retw_opcode;
 588 static xtensa_opcode xtensa_retw_n_opcode;
 589 static xtensa_opcode xtensa_rsr_lcount_opcode;
 590 static xtensa_opcode xtensa_waiti_opcode;
 591 static int config_max_slots = 0;
 592
 593 \f
 594 /* Command-line Options.  */
 595
 596 bfd_boolean use_literal_section = TRUE;
 597 enum flix_level produce_flix = FLIX_ALL;
 598 static bfd_boolean align_targets = TRUE;
 599 static bfd_boolean warn_unaligned_branch_targets = FALSE;
 600 static bfd_boolean has_a0_b_retw = FALSE;
 601 static bfd_boolean workaround_a0_b_retw = FALSE;
 602 static bfd_boolean workaround_b_j_loop_end = FALSE;
 603 static bfd_boolean workaround_short_loop = FALSE;
 604 static bfd_boolean maybe_has_short_loop = FALSE;
 605 static bfd_boolean workaround_close_loop_end = FALSE;
 606 static bfd_boolean maybe_has_close_loop_end = FALSE;
 607 static bfd_boolean enforce_three_byte_loop_align = FALSE;
 608
 609 /* When workaround_short_loops is TRUE, all loops with early exits must
 610    have at least 3 instructions.  workaround_all_short_loops is a modifier
 611    to the workaround_short_loop flag.  In addition to the
 612    workaround_short_loop actions, all straightline loopgtz and loopnez
 613    must have at least 3 instructions.  */
 614
 615 static bfd_boolean workaround_all_short_loops = FALSE;
 616
 617
 618 static void
 619 xtensa_setup_hw_workarounds (int earliest, int latest)
 620 {
 621   if (earliest > latest)
 622     as_fatal (_("illegal range of target hardware versions"));
 623
 624   /* Enable all workarounds for pre-T1050.0 hardware.  */
 625   if (earliest < 105000 || latest < 105000)
 626     {
 627       workaround_a0_b_retw |= TRUE;
 628       workaround_b_j_loop_end |= TRUE;
 629       workaround_short_loop |= TRUE;
 630       workaround_close_loop_end |= TRUE;
 631       workaround_all_short_loops |= TRUE;
 632       enforce_three_byte_loop_align = TRUE;
 633     }
 634 }
 635
 636
 637 enum
 638 {
 639   option_density = OPTION_MD_BASE,
 640   option_no_density,
 641
 642   option_flix,
 643   option_no_generate_flix,
 644   option_no_flix,
 645
 646   option_relax,
 647   option_no_relax,
 648
 649   option_link_relax,
 650   option_no_link_relax,
 651
 652   option_generics,
 653   option_no_generics,
 654
 655   option_transform,
 656   option_no_transform,
 657
 658   option_text_section_literals,
 659   option_no_text_section_literals,
 660
 661   option_absolute_literals,
 662   option_no_absolute_literals,
 663
 664   option_align_targets,
 665   option_no_align_targets,
 666
 667   option_warn_unaligned_targets,
 668
 669   option_longcalls,
 670   option_no_longcalls,
 671
 672   option_workaround_a0_b_retw,
 673   option_no_workaround_a0_b_retw,
 674
 675   option_workaround_b_j_loop_end,
 676   option_no_workaround_b_j_loop_end,
 677
 678   option_workaround_short_loop,
 679   option_no_workaround_short_loop,
 680
 681   option_workaround_all_short_loops,
 682   option_no_workaround_all_short_loops,
 683
 684   option_workaround_close_loop_end,
 685   option_no_workaround_close_loop_end,
 686
 687   option_no_workarounds,
 688
 689   option_rename_section_name,
 690
 691   option_prefer_l32r,
 692   option_prefer_const16,
 693
 694   option_target_hardware
 695 };
 696
 697 const char *md_shortopts = "";
 698
 699 struct option md_longopts[] =
 700 {
 701   { "density", no_argument, NULL, option_density },
 702   { "no-density", no_argument, NULL, option_no_density },
 703
 704   { "flix", no_argument, NULL, option_flix },
 705   { "no-generate-flix", no_argument, NULL, option_no_generate_flix },
 706   { "no-allow-flix", no_argument, NULL, option_no_flix },
 707
 708   /* Both "relax" and "generics" are deprecated and treated as equivalent
 709      to the "transform" option.  */
 710   { "relax", no_argument, NULL, option_relax },
 711   { "no-relax", no_argument, NULL, option_no_relax },
 712   { "generics", no_argument, NULL, option_generics },
 713   { "no-generics", no_argument, NULL, option_no_generics },
 714
 715   { "transform", no_argument, NULL, option_transform },
 716   { "no-transform", no_argument, NULL, option_no_transform },
 717   { "text-section-literals", no_argument, NULL, option_text_section_literals },
 718   { "no-text-section-literals", no_argument, NULL,
 719     option_no_text_section_literals },
 720   { "absolute-literals", no_argument, NULL, option_absolute_literals },
 721   { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
 722   /* This option was changed from -align-target to -target-align
 723      because it conflicted with the "-al" option.  */
 724   { "target-align", no_argument, NULL, option_align_targets },
 725   { "no-target-align", no_argument, NULL, option_no_align_targets },
 726   { "warn-unaligned-targets", no_argument, NULL,
 727     option_warn_unaligned_targets },
 728   { "longcalls", no_argument, NULL, option_longcalls },
 729   { "no-longcalls", no_argument, NULL, option_no_longcalls },
 730
 731   { "no-workaround-a0-b-retw", no_argument, NULL,
 732     option_no_workaround_a0_b_retw },
 733   { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
 734
 735   { "no-workaround-b-j-loop-end", no_argument, NULL,
 736     option_no_workaround_b_j_loop_end },
 737   { "workaround-b-j-loop-end", no_argument, NULL,
 738     option_workaround_b_j_loop_end },
 739
 740   { "no-workaround-short-loops", no_argument, NULL,
 741     option_no_workaround_short_loop },
 742   { "workaround-short-loops", no_argument, NULL,
 743     option_workaround_short_loop },
 744
 745   { "no-workaround-all-short-loops", no_argument, NULL,
 746     option_no_workaround_all_short_loops },
 747   { "workaround-all-short-loop", no_argument, NULL,
 748     option_workaround_all_short_loops },
 749
 750   { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
 751   { "prefer-const16", no_argument, NULL, option_prefer_const16 },
 752
 753   { "no-workarounds", no_argument, NULL, option_no_workarounds },
 754
 755   { "no-workaround-close-loop-end", no_argument, NULL,
 756     option_no_workaround_close_loop_end },
 757   { "workaround-close-loop-end", no_argument, NULL,
 758     option_workaround_close_loop_end },
 759
 760   { "rename-section", required_argument, NULL, option_rename_section_name },
 761
 762   { "link-relax", no_argument, NULL, option_link_relax },
 763   { "no-link-relax", no_argument, NULL, option_no_link_relax },
 764
 765   { "target-hardware", required_argument, NULL, option_target_hardware },
 766
 767   { NULL, no_argument, NULL, 0 }
 768 };
 769
 770 size_t md_longopts_size = sizeof md_longopts;
 771
 772
 773 int
 774 md_parse_option (int c, char *arg)
 775 {
 776   switch (c)
 777     {
 778     case option_density:
 779       as_warn (_("--density option is ignored"));
 780       return 1;
 781     case option_no_density:
 782       as_warn (_("--no-density option is ignored"));
 783       return 1;
 784     case option_link_relax:
 785       linkrelax = 1;
 786       return 1;
 787     case option_no_link_relax:
 788       linkrelax = 0;
 789       return 1;
 790     case option_flix:
 791       produce_flix = FLIX_ALL;
 792       return 1;
 793     case option_no_generate_flix:
 794       produce_flix = FLIX_NO_GENERATE;
 795       return 1;
 796     case option_no_flix:
 797       produce_flix = FLIX_NONE;
 798       return 1;
 799     case option_generics:
 800       as_warn (_("--generics is deprecated; use --transform instead"));
 801       return md_parse_option (option_transform, arg);
 802     case option_no_generics:
 803       as_warn (_("--no-generics is deprecated; use --no-transform instead"));
 804       return md_parse_option (option_no_transform, arg);
 805     case option_relax:
 806       as_warn (_("--relax is deprecated; use --transform instead"));
 807       return md_parse_option (option_transform, arg);
 808     case option_no_relax:
 809       as_warn (_("--no-relax is deprecated; use --no-transform instead"));
 810       return md_parse_option (option_no_transform, arg);
 811     case option_longcalls:
 812       directive_state[directive_longcalls] = TRUE;
 813       return 1;
 814     case option_no_longcalls:
 815       directive_state[directive_longcalls] = FALSE;
 816       return 1;
 817     case option_text_section_literals:
 818       use_literal_section = FALSE;
 819       return 1;
 820     case option_no_text_section_literals:
 821       use_literal_section = TRUE;
 822       return 1;
 823     case option_absolute_literals:
 824       if (!absolute_literals_supported)
 825         {
 826           as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
 827           return 0;
 828         }
 829       directive_state[directive_absolute_literals] = TRUE;
 830       return 1;
 831     case option_no_absolute_literals:
 832       directive_state[directive_absolute_literals] = FALSE;
 833       return 1;
 834
 835     case option_workaround_a0_b_retw:
 836       workaround_a0_b_retw = TRUE;
 837       return 1;
 838     case option_no_workaround_a0_b_retw:
 839       workaround_a0_b_retw = FALSE;
 840       return 1;
 841     case option_workaround_b_j_loop_end:
 842       workaround_b_j_loop_end = TRUE;
 843       return 1;
 844     case option_no_workaround_b_j_loop_end:
 845       workaround_b_j_loop_end = FALSE;
 846       return 1;
 847
 848     case option_workaround_short_loop:
 849       workaround_short_loop = TRUE;
 850       return 1;
 851     case option_no_workaround_short_loop:
 852       workaround_short_loop = FALSE;
 853       return 1;
 854
 855     case option_workaround_all_short_loops:
 856       workaround_all_short_loops = TRUE;
 857       return 1;
 858     case option_no_workaround_all_short_loops:
 859       workaround_all_short_loops = FALSE;
 860       return 1;
 861
 862     case option_workaround_close_loop_end:
 863       workaround_close_loop_end = TRUE;
 864       return 1;
 865     case option_no_workaround_close_loop_end:
 866       workaround_close_loop_end = FALSE;
 867       return 1;
 868
 869     case option_no_workarounds:
 870       workaround_a0_b_retw = FALSE;
 871       workaround_b_j_loop_end = FALSE;
 872       workaround_short_loop = FALSE;
 873       workaround_all_short_loops = FALSE;
 874       workaround_close_loop_end = FALSE;
 875       return 1;
 876
 877     case option_align_targets:
 878       align_targets = TRUE;
 879       return 1;
 880     case option_no_align_targets:
 881       align_targets = FALSE;
 882       return 1;
 883
 884     case option_warn_unaligned_targets:
 885       warn_unaligned_branch_targets = TRUE;
 886       return 1;
 887
 888     case option_rename_section_name:
 889       build_section_rename (arg);
 890       return 1;
 891
 892     case 'Q':
 893       /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
 894          should be emitted or not.  FIXME: Not implemented.  */
 895       return 1;
 896
 897     case option_prefer_l32r:
 898       if (prefer_const16)
 899         as_fatal (_("prefer-l32r conflicts with prefer-const16"));
 900       prefer_l32r = 1;
 901       return 1;
 902
 903     case option_prefer_const16:
 904       if (prefer_l32r)
 905         as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
 906       prefer_const16 = 1;
 907       return 1;
 908
 909     case option_target_hardware:
 910       {
 911         int earliest, latest = 0;
 912         if (*arg == 0 || *arg == '-')
 913           as_fatal (_("invalid target hardware version"));
 914
 915         earliest = strtol (arg, &arg, 0);
 916
 917         if (*arg == 0)
 918           latest = earliest;
 919         else if (*arg == '-')
 920           {
 921             if (*++arg == 0)
 922               as_fatal (_("invalid target hardware version"));
 923             latest = strtol (arg, &arg, 0);
 924           }
 925         if (*arg != 0)
 926           as_fatal (_("invalid target hardware version"));
 927
 928         xtensa_setup_hw_workarounds (earliest, latest);
 929         return 1;
 930       }
 931
 932     case option_transform:
 933       /* This option has no affect other than to use the defaults,
 934          which are already set.  */
 935       return 1;
 936
 937     case option_no_transform:
 938       /* This option turns off all transformations of any kind.
 939          However, because we want to preserve the state of other
 940          directives, we only change its own field.  Thus, before
 941          you perform any transformation, always check if transform
 942          is available.  If you use the functions we provide for this
 943          purpose, you will be ok.  */
 944       directive_state[directive_transform] = FALSE;
 945       return 1;
 946
 947     default:
 948       return 0;
 949     }
 950 }
 951
 952
 953 void
 954 md_show_usage (FILE *stream)
 955 {
 956   fputs ("\n\
 957 Xtensa options:\n\
 958   --[no-]text-section-literals\n\
 959                           [Do not] put literals in the text section\n\
 960   --[no-]absolute-literals\n\
 961                           [Do not] default to use non-PC-relative literals\n\
 962   --[no-]target-align     [Do not] try to align branch targets\n\
 963   --[no-]longcalls        [Do not] emit 32-bit call sequences\n\
 964   --[no-]transform        [Do not] transform instructions\n\
 965   --flix                  both allow hand-written and generate flix bundles\n\
 966   --no-generate-flix      allow hand-written but do not generate\n\
 967                           flix bundles\n\
 968   --no-allow-flix         neither allow hand-written nor generate\n\
 969                           flix bundles\n\
 970   --rename-section old=new Rename section 'old' to 'new'\n", stream);
 971 }
 972
 973 \f
 974 /* Functions related to the list of current label symbols.  */
 975
 976 static void
 977 xtensa_add_insn_label (symbolS *sym)
 978 {
 979   sym_list *l;
 980
 981   if (!free_insn_labels)
 982     l = (sym_list *) xmalloc (sizeof (sym_list));
 983   else
 984     {
 985       l = free_insn_labels;
 986       free_insn_labels = l->next;
 987     }
 988
 989   l->sym = sym;
 990   l->next = insn_labels;
 991   insn_labels = l;
 992 }
 993
 994
 995 static void
 996 xtensa_clear_insn_labels (void)
 997 {
 998   sym_list **pl;
 999
1000   for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1001     ;
1002   *pl = insn_labels;
1003   insn_labels = NULL;
1004 }
1005
1006
1007 static void
1008 xtensa_move_labels (fragS *new_frag, valueT new_offset)
1009 {
1010   sym_list *lit;
1011
1012   for (lit = insn_labels; lit; lit = lit->next)
1013     {
1014       symbolS *lit_sym = lit->sym;
1015       S_SET_VALUE (lit_sym, new_offset);
1016       symbol_set_frag (lit_sym, new_frag);
1017     }
1018 }
1019
1020 \f
1021 /* Directive data and functions.  */
1022
1023 typedef struct state_stackS_struct
1024 {
1025   directiveE directive;
1026   bfd_boolean negated;
1027   bfd_boolean old_state;
1028   const char *file;
1029   unsigned int line;
1030   const void *datum;
1031   struct state_stackS_struct *prev;
1032 } state_stackS;
1033
1034 state_stackS *directive_state_stack;
1035
1036 const pseudo_typeS md_pseudo_table[] =
1037 {
1038   { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
1039   { "literal_position", xtensa_literal_position, 0 },
1040   { "frame", s_ignore, 0 },     /* Formerly used for STABS debugging.  */
1041   { "long", xtensa_elf_cons, 4 },
1042   { "word", xtensa_elf_cons, 4 },
1043   { "4byte", xtensa_elf_cons, 4 },
1044   { "short", xtensa_elf_cons, 2 },
1045   { "2byte", xtensa_elf_cons, 2 },
1046   { "sleb128", xtensa_leb128, 1},
1047   { "uleb128", xtensa_leb128, 0},
1048   { "begin", xtensa_begin_directive, 0 },
1049   { "end", xtensa_end_directive, 0 },
1050   { "literal", xtensa_literal_pseudo, 0 },
1051   { "frequency", xtensa_frequency_pseudo, 0 },
1052   { NULL, 0, 0 },
1053 };
1054
1055
1056 static bfd_boolean
1057 use_transform (void)
1058 {
1059   /* After md_end, you should be checking frag by frag, rather
1060      than state directives.  */
1061   gas_assert (!past_xtensa_end);
1062   return directive_state[directive_transform];
1063 }
1064
1065
1066 static bfd_boolean
1067 do_align_targets (void)
1068 {
1069   /* Do not use this function after md_end; just look at align_targets
1070      instead.  There is no target-align directive, so alignment is either
1071      enabled for all frags or not done at all.  */
1072   gas_assert (!past_xtensa_end);
1073   return align_targets && use_transform ();
1074 }
1075
1076
1077 static void
1078 directive_push (directiveE directive, bfd_boolean negated, const void *datum)
1079 {
1080   char *file;
1081   unsigned int line;
1082   state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1083
1084   as_where (&file, &line);
1085
1086   stack->directive = directive;
1087   stack->negated = negated;
1088   stack->old_state = directive_state[directive];
1089   stack->file = file;
1090   stack->line = line;
1091   stack->datum = datum;
1092   stack->prev = directive_state_stack;
1093   directive_state_stack = stack;
1094
1095   directive_state[directive] = !negated;
1096 }
1097
1098
1099 static void
1100 directive_pop (directiveE *directive,
1101                bfd_boolean *negated,
1102                const char **file,
1103                unsigned int *line,
1104                const void **datum)
1105 {
1106   state_stackS *top = directive_state_stack;
1107
1108   if (!directive_state_stack)
1109     {
1110       as_bad (_("unmatched end directive"));
1111       *directive = directive_none;
1112       return;
1113     }
1114
1115   directive_state[directive_state_stack->directive] = top->old_state;
1116   *directive = top->directive;
1117   *negated = top->negated;
1118   *file = top->file;
1119   *line = top->line;
1120   *datum = top->datum;
1121   directive_state_stack = top->prev;
1122   free (top);
1123 }
1124
1125
1126 static void
1127 directive_balance (void)
1128 {
1129   while (directive_state_stack)
1130     {
1131       directiveE directive;
1132       bfd_boolean negated;
1133       const char *file;
1134       unsigned int line;
1135       const void *datum;
1136
1137       directive_pop (&directive, &negated, &file, &line, &datum);
1138       as_warn_where ((char *) file, line,
1139                      _(".begin directive with no matching .end directive"));
1140     }
1141 }
1142
1143
1144 static bfd_boolean
1145 inside_directive (directiveE dir)
1146 {
1147   state_stackS *top = directive_state_stack;
1148
1149   while (top && top->directive != dir)
1150     top = top->prev;
1151
1152   return (top != NULL);
1153 }
1154
1155
1156 static void
1157 get_directive (directiveE *directive, bfd_boolean *negated)
1158 {
1159   int len;
1160   unsigned i;
1161   char *directive_string;
1162
1163   if (strncmp (input_line_pointer, "no-", 3) != 0)
1164     *negated = FALSE;
1165   else
1166     {
1167       *negated = TRUE;
1168       input_line_pointer += 3;
1169     }
1170
1171   len = strspn (input_line_pointer,
1172                 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1173
1174   /* This code is a hack to make .begin [no-][generics|relax] exactly
1175      equivalent to .begin [no-]transform.  We should remove it when
1176      we stop accepting those options.  */
1177
1178   if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1179     {
1180       as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1181       directive_string = "transform";
1182     }
1183   else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1184     {
1185       as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1186       directive_string = "transform";
1187     }
1188   else
1189     directive_string = input_line_pointer;
1190
1191   for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1192     {
1193       if (strncmp (directive_string, directive_info[i].name, len) == 0)
1194         {
1195           input_line_pointer += len;
1196           *directive = (directiveE) i;
1197           if (*negated && !directive_info[i].can_be_negated)
1198             as_bad (_("directive %s cannot be negated"),
1199                     directive_info[i].name);
1200           return;
1201         }
1202     }
1203
1204   as_bad (_("unknown directive"));
1205   *directive = (directiveE) XTENSA_UNDEFINED;
1206 }
1207
1208
1209 static void
1210 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1211 {
1212   directiveE directive;
1213   bfd_boolean negated;
1214   emit_state *state;
1215   lit_state *ls;
1216
1217   get_directive (&directive, &negated);
1218   if (directive == (directiveE) XTENSA_UNDEFINED)
1219     {
1220       discard_rest_of_line ();
1221       return;
1222     }
1223
1224   if (cur_vinsn.inside_bundle)
1225     as_bad (_("directives are not valid inside bundles"));
1226
1227   switch (directive)
1228     {
1229     case directive_literal:
1230       if (!inside_directive (directive_literal))
1231         {
1232           /* Previous labels go with whatever follows this directive, not with
1233              the literal, so save them now.  */
1234           saved_insn_labels = insn_labels;
1235           insn_labels = NULL;
1236         }
1237       as_warn (_(".begin literal is deprecated; use .literal instead"));
1238       state = (emit_state *) xmalloc (sizeof (emit_state));
1239       xtensa_switch_to_literal_fragment (state);
1240       directive_push (directive_literal, negated, state);
1241       break;
1242
1243     case directive_literal_prefix:
1244       /* Have to flush pending output because a movi relaxed to an l32r
1245          might produce a literal.  */
1246       md_flush_pending_output ();
1247       /* Check to see if the current fragment is a literal
1248          fragment.  If it is, then this operation is not allowed.  */
1249       if (generating_literals)
1250         {
1251           as_bad (_("cannot set literal_prefix inside literal fragment"));
1252           return;
1253         }
1254
1255       /* Allocate the literal state for this section and push
1256          onto the directive stack.  */
1257       ls = xmalloc (sizeof (lit_state));
1258       gas_assert (ls);
1259
1260       *ls = default_lit_sections;
1261       directive_push (directive_literal_prefix, negated, ls);
1262
1263       /* Process the new prefix.  */
1264       xtensa_literal_prefix ();
1265       break;
1266
1267     case directive_freeregs:
1268       /* This information is currently unused, but we'll accept the statement
1269          and just discard the rest of the line.  This won't check the syntax,
1270          but it will accept every correct freeregs directive.  */
1271       input_line_pointer += strcspn (input_line_pointer, "\n");
1272       directive_push (directive_freeregs, negated, 0);
1273       break;
1274
1275     case directive_schedule:
1276       md_flush_pending_output ();
1277       frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1278                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1279       directive_push (directive_schedule, negated, 0);
1280       xtensa_set_frag_assembly_state (frag_now);
1281       break;
1282
1283     case directive_density:
1284       as_warn (_(".begin [no-]density is ignored"));
1285       break;
1286
1287     case directive_absolute_literals:
1288       md_flush_pending_output ();
1289       if (!absolute_literals_supported && !negated)
1290         {
1291           as_warn (_("Xtensa absolute literals option not supported; ignored"));
1292           break;
1293         }
1294       xtensa_set_frag_assembly_state (frag_now);
1295       directive_push (directive, negated, 0);
1296       break;
1297
1298     default:
1299       md_flush_pending_output ();
1300       xtensa_set_frag_assembly_state (frag_now);
1301       directive_push (directive, negated, 0);
1302       break;
1303     }
1304
1305   demand_empty_rest_of_line ();
1306 }
1307
1308
1309 static void
1310 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1311 {
1312   directiveE begin_directive, end_directive;
1313   bfd_boolean begin_negated, end_negated;
1314   const char *file;
1315   unsigned int line;
1316   emit_state *state;
1317   emit_state **state_ptr;
1318   lit_state *s;
1319
1320   if (cur_vinsn.inside_bundle)
1321     as_bad (_("directives are not valid inside bundles"));
1322
1323   get_directive (&end_directive, &end_negated);
1324
1325   md_flush_pending_output ();
1326
1327   switch (end_directive)
1328     {
1329     case (directiveE) XTENSA_UNDEFINED:
1330       discard_rest_of_line ();
1331       return;
1332
1333     case directive_density:
1334       as_warn (_(".end [no-]density is ignored"));
1335       demand_empty_rest_of_line ();
1336       break;
1337
1338     case directive_absolute_literals:
1339       if (!absolute_literals_supported && !end_negated)
1340         {
1341           as_warn (_("Xtensa absolute literals option not supported; ignored"));
1342           demand_empty_rest_of_line ();
1343           return;
1344         }
1345       break;
1346
1347     default:
1348       break;
1349     }
1350
1351   state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1352   directive_pop (&begin_directive, &begin_negated, &file, &line,
1353                  (const void **) state_ptr);
1354
1355   if (begin_directive != directive_none)
1356     {
1357       if (begin_directive != end_directive || begin_negated != end_negated)
1358         {
1359           as_bad (_("does not match begin %s%s at %s:%d"),
1360                   begin_negated ? "no-" : "",
1361                   directive_info[begin_directive].name, file, line);
1362         }
1363       else
1364         {
1365           switch (end_directive)
1366             {
1367             case directive_literal:
1368               frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1369               xtensa_restore_emit_state (state);
1370               xtensa_set_frag_assembly_state (frag_now);
1371               free (state);
1372               if (!inside_directive (directive_literal))
1373                 {
1374                   /* Restore the list of current labels.  */
1375                   xtensa_clear_insn_labels ();
1376                   insn_labels = saved_insn_labels;
1377                 }
1378               break;
1379
1380             case directive_literal_prefix:
1381               /* Restore the default collection sections from saved state.  */
1382               s = (lit_state *) state;
1383               gas_assert (s);
1384               default_lit_sections = *s;
1385
1386               /* Free the state storage.  */
1387               free (s->lit_prefix);
1388               free (s);
1389               break;
1390
1391             case directive_schedule:
1392             case directive_freeregs:
1393               break;
1394
1395             default:
1396               xtensa_set_frag_assembly_state (frag_now);
1397               break;
1398             }
1399         }
1400     }
1401
1402   demand_empty_rest_of_line ();
1403 }
1404
1405
1406 /* Place an aligned literal fragment at the current location.  */
1407
1408 static void
1409 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1410 {
1411   md_flush_pending_output ();
1412
1413   if (inside_directive (directive_literal))
1414     as_warn (_(".literal_position inside literal directive; ignoring"));
1415   xtensa_mark_literal_pool_location ();
1416
1417   demand_empty_rest_of_line ();
1418   xtensa_clear_insn_labels ();
1419 }
1420
1421
1422 /* Support .literal label, expr, ...  */
1423
1424 static void
1425 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1426 {
1427   emit_state state;
1428   char *p, *base_name;
1429   char c;
1430   segT dest_seg;
1431
1432   if (inside_directive (directive_literal))
1433     {
1434       as_bad (_(".literal not allowed inside .begin literal region"));
1435       ignore_rest_of_line ();
1436       return;
1437     }
1438
1439   md_flush_pending_output ();
1440
1441   /* Previous labels go with whatever follows this directive, not with
1442      the literal, so save them now.  */
1443   saved_insn_labels = insn_labels;
1444   insn_labels = NULL;
1445
1446   /* If we are using text-section literals, then this is the right value... */
1447   dest_seg = now_seg;
1448
1449   base_name = input_line_pointer;
1450
1451   xtensa_switch_to_literal_fragment (&state);
1452
1453   /* ...but if we aren't using text-section-literals, then we
1454      need to put them in the section we just switched to.  */
1455   if (use_literal_section || directive_state[directive_absolute_literals])
1456     dest_seg = now_seg;
1457
1458   /* All literals are aligned to four-byte boundaries.  */
1459   frag_align (2, 0, 0);
1460   record_alignment (now_seg, 2);
1461
1462   c = get_symbol_end ();
1463   /* Just after name is now '\0'.  */
1464   p = input_line_pointer;
1465   *p = c;
1466   SKIP_WHITESPACE ();
1467
1468   if (*input_line_pointer != ',' && *input_line_pointer != ':')
1469     {
1470       as_bad (_("expected comma or colon after symbol name; "
1471                 "rest of line ignored"));
1472       ignore_rest_of_line ();
1473       xtensa_restore_emit_state (&state);
1474       return;
1475     }
1476   *p = 0;
1477
1478   colon (base_name);
1479
1480   *p = c;
1481   input_line_pointer++;         /* skip ',' or ':' */
1482
1483   xtensa_elf_cons (4);
1484
1485   xtensa_restore_emit_state (&state);
1486
1487   /* Restore the list of current labels.  */
1488   xtensa_clear_insn_labels ();
1489   insn_labels = saved_insn_labels;
1490 }
1491
1492
1493 static void
1494 xtensa_literal_prefix (void)
1495 {
1496   char *name;
1497   int len;
1498
1499   /* Parse the new prefix from the input_line_pointer.  */
1500   SKIP_WHITESPACE ();
1501   len = strspn (input_line_pointer,
1502                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1503                 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1504
1505   /* Get a null-terminated copy of the name.  */
1506   name = xmalloc (len + 1);
1507   gas_assert (name);
1508   strncpy (name, input_line_pointer, len);
1509   name[len] = 0;
1510
1511   /* Skip the name in the input line.  */
1512   input_line_pointer += len;
1513
1514   default_lit_sections.lit_prefix = name;
1515
1516   /* Clear cached literal sections, since the prefix has changed.  */
1517   default_lit_sections.lit_seg = NULL;
1518   default_lit_sections.lit4_seg = NULL;
1519 }
1520
1521
1522 /* Support ".frequency branch_target_frequency fall_through_frequency".  */
1523
1524 static void
1525 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1526 {
1527   float fall_through_f, target_f;
1528
1529   fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1530   if (fall_through_f < 0)
1531     {
1532       as_bad (_("fall through frequency must be greater than 0"));
1533       ignore_rest_of_line ();
1534       return;
1535     }
1536
1537   target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1538   if (target_f < 0)
1539     {
1540       as_bad (_("branch target frequency must be greater than 0"));
1541       ignore_rest_of_line ();
1542       return;
1543     }
1544
1545   set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
1546
1547   demand_empty_rest_of_line ();
1548 }
1549
1550
1551 /* Like normal .long/.short/.word, except support @plt, etc.
1552    Clobbers input_line_pointer, checks end-of-line.  */
1553
1554 static void
1555 xtensa_elf_cons (int nbytes)
1556 {
1557   expressionS exp;
1558   bfd_reloc_code_real_type reloc;
1559
1560   md_flush_pending_output ();
1561
1562   if (cur_vinsn.inside_bundle)
1563     as_bad (_("directives are not valid inside bundles"));
1564
1565   if (is_it_end_of_statement ())
1566     {
1567       demand_empty_rest_of_line ();
1568       return;
1569     }
1570
1571   do
1572     {
1573       expression (&exp);
1574       if (exp.X_op == O_symbol
1575           && *input_line_pointer == '@'
1576           && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1577               != BFD_RELOC_NONE))
1578         {
1579           reloc_howto_type *reloc_howto =
1580             bfd_reloc_type_lookup (stdoutput, reloc);
1581
1582           if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1583             as_bad (_("unsupported relocation"));
1584           else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1585                     && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1586                    || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1587                        && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1588             as_bad (_("opcode-specific %s relocation used outside "
1589                       "an instruction"), reloc_howto->name);
1590           else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1591             as_bad (_("%s relocations do not fit in %d bytes"),
1592                     reloc_howto->name, nbytes);
1593           else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC
1594                    || reloc == BFD_RELOC_XTENSA_TLS_ARG
1595                    || reloc == BFD_RELOC_XTENSA_TLS_CALL)
1596             as_bad (_("invalid use of %s relocation"), reloc_howto->name);
1597           else
1598             {
1599               char *p = frag_more ((int) nbytes);
1600               xtensa_set_frag_assembly_state (frag_now);
1601               fix_new_exp (frag_now, p - frag_now->fr_literal,
1602                            nbytes, &exp, reloc_howto->pc_relative, reloc);
1603             }
1604         }
1605       else
1606         {
1607           xtensa_set_frag_assembly_state (frag_now);
1608           emit_expr (&exp, (unsigned int) nbytes);
1609         }
1610     }
1611   while (*input_line_pointer++ == ',');
1612
1613   input_line_pointer--;         /* Put terminator back into stream.  */
1614   demand_empty_rest_of_line ();
1615 }
1616
1617 static bfd_boolean is_leb128_expr;
1618
1619 static void
1620 xtensa_leb128 (int sign)
1621 {
1622   is_leb128_expr = TRUE;
1623   s_leb128 (sign);
1624   is_leb128_expr = FALSE;
1625 }
1626
1627 \f
1628 /* Parsing and Idiom Translation.  */
1629
1630 /* Parse @plt, etc. and return the desired relocation.  */
1631 static bfd_reloc_code_real_type
1632 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1633 {
1634   char ident[20];
1635   char *str = *str_p;
1636   char *str2;
1637   int ch;
1638   int len;
1639   struct suffix_reloc_map *ptr;
1640
1641   if (*str++ != '@')
1642     return BFD_RELOC_NONE;
1643
1644   for (ch = *str, str2 = ident;
1645        (str2 < ident + sizeof (ident) - 1
1646         && (ISALNUM (ch) || ch == '@'));
1647        ch = *++str)
1648     {
1649       *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1650     }
1651
1652   *str2 = '\0';
1653   len = str2 - ident;
1654
1655   ch = ident[0];
1656   for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++)
1657     if (ch == ptr->suffix[0]
1658         && len == ptr->length
1659         && memcmp (ident, ptr->suffix, ptr->length) == 0)
1660       {
1661         /* Now check for "identifier@suffix+constant".  */
1662         if (*str == '-' || *str == '+')
1663           {
1664             char *orig_line = input_line_pointer;
1665             expressionS new_exp;
1666
1667             input_line_pointer = str;
1668             expression (&new_exp);
1669             if (new_exp.X_op == O_constant)
1670               {
1671                 exp_p->X_add_number += new_exp.X_add_number;
1672                 str = input_line_pointer;
1673               }
1674
1675             if (&input_line_pointer != str_p)
1676               input_line_pointer = orig_line;
1677           }
1678
1679         *str_p = str;
1680         return ptr->reloc;
1681       }
1682
1683   return BFD_RELOC_UNUSED;
1684 }
1685
1686
1687 /* Find the matching operator type.  */
1688 static unsigned char
1689 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc)
1690 {
1691   struct suffix_reloc_map *sfx;
1692   unsigned char operator = (unsigned char) -1;
1693
1694   for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++)
1695     {
1696       if (sfx->reloc == reloc)
1697         {
1698           operator = sfx->operator;
1699           break;
1700         }
1701     }
1702   gas_assert (operator != (unsigned char) -1);
1703   return operator;
1704 }
1705
1706
1707 /* Find the matching reloc type.  */
1708 static bfd_reloc_code_real_type
1709 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal)
1710 {
1711   struct suffix_reloc_map *sfx;
1712   bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
1713
1714   for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++)
1715     {
1716       if (sfx->operator == operator)
1717         {
1718           reloc = sfx->reloc;
1719           break;
1720         }
1721     }
1722
1723   if (is_literal)
1724     {
1725       if (reloc == BFD_RELOC_XTENSA_TLS_FUNC)
1726         return BFD_RELOC_XTENSA_TLSDESC_FN;
1727       else if (reloc == BFD_RELOC_XTENSA_TLS_ARG)
1728         return BFD_RELOC_XTENSA_TLSDESC_ARG;
1729     }
1730
1731   if (reloc == BFD_RELOC_UNUSED)
1732     return BFD_RELOC_32;
1733
1734   return reloc;
1735 }
1736
1737
1738 static const char *
1739 expression_end (const char *name)
1740 {
1741   while (1)
1742     {
1743       switch (*name)
1744         {
1745         case '}':
1746         case ';':
1747         case '\0':
1748         case ',':
1749         case ':':
1750           return name;
1751         case ' ':
1752         case '\t':
1753           ++name;
1754           continue;
1755         default:
1756           return 0;
1757         }
1758     }
1759 }
1760
1761
1762 #define ERROR_REG_NUM ((unsigned) -1)
1763
1764 static unsigned
1765 tc_get_register (const char *prefix)
1766 {
1767   unsigned reg;
1768   const char *next_expr;
1769   const char *old_line_pointer;
1770
1771   SKIP_WHITESPACE ();
1772   old_line_pointer = input_line_pointer;
1773
1774   if (*input_line_pointer == '$')
1775     ++input_line_pointer;
1776
1777   /* Accept "sp" as a synonym for "a1".  */
1778   if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1779       && expression_end (input_line_pointer + 2))
1780     {
1781       input_line_pointer += 2;
1782       return 1;  /* AR[1] */
1783     }
1784
1785   while (*input_line_pointer++ == *prefix++)
1786     ;
1787   --input_line_pointer;
1788   --prefix;
1789
1790   if (*prefix)
1791     {
1792       as_bad (_("bad register name: %s"), old_line_pointer);
1793       return ERROR_REG_NUM;
1794     }
1795
1796   if (!ISDIGIT ((unsigned char) *input_line_pointer))
1797     {
1798       as_bad (_("bad register number: %s"), input_line_pointer);
1799       return ERROR_REG_NUM;
1800     }
1801
1802   reg = 0;
1803
1804   while (ISDIGIT ((int) *input_line_pointer))
1805     reg = reg * 10 + *input_line_pointer++ - '0';
1806
1807   if (!(next_expr = expression_end (input_line_pointer)))
1808     {
1809       as_bad (_("bad register name: %s"), old_line_pointer);
1810       return ERROR_REG_NUM;
1811     }
1812
1813   input_line_pointer = (char *) next_expr;
1814
1815   return reg;
1816 }
1817
1818
1819 static void
1820 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1821 {
1822   xtensa_isa isa = xtensa_default_isa;
1823
1824   /* Check if this is an immediate operand.  */
1825   if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1826     {
1827       bfd_reloc_code_real_type reloc;
1828       segT t = expression (tok);
1829       if (t == absolute_section
1830           && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1831         {
1832           gas_assert (tok->X_op == O_constant);
1833           tok->X_op = O_symbol;
1834           tok->X_add_symbol = &abs_symbol;
1835         }
1836
1837       if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1838           && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1839               != BFD_RELOC_NONE))
1840         {
1841           switch (reloc)
1842             {
1843             case BFD_RELOC_LO16:
1844               if (tok->X_op == O_constant)
1845                 {
1846                   tok->X_add_number &= 0xffff;
1847                   return;
1848                 }
1849               break;
1850             case BFD_RELOC_HI16:
1851               if (tok->X_op == O_constant)
1852                 {
1853                   tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1854                   return;
1855                 }
1856               break;
1857             case BFD_RELOC_UNUSED:
1858               as_bad (_("unsupported relocation"));
1859               return;
1860             case BFD_RELOC_32_PCREL:
1861               as_bad (_("pcrel relocation not allowed in an instruction"));
1862               return;
1863             default:
1864               break;
1865             }
1866           tok->X_op = map_suffix_reloc_to_operator (reloc);
1867         }
1868     }
1869   else
1870     {
1871       xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1872       unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1873
1874       if (reg != ERROR_REG_NUM) /* Already errored */
1875         {
1876           uint32 buf = reg;
1877           if (xtensa_operand_encode (isa, opc, opnd, &buf))
1878             as_bad (_("register number out of range"));
1879         }
1880
1881       tok->X_op = O_register;
1882       tok->X_add_symbol = 0;
1883       tok->X_add_number = reg;
1884     }
1885 }
1886
1887
1888 /* Split up the arguments for an opcode or pseudo-op.  */
1889
1890 static int
1891 tokenize_arguments (char **args, char *str)
1892 {
1893   char *old_input_line_pointer;
1894   bfd_boolean saw_comma = FALSE;
1895   bfd_boolean saw_arg = FALSE;
1896   bfd_boolean saw_colon = FALSE;
1897   int num_args = 0;
1898   char *arg_end, *arg;
1899   int arg_len;
1900
1901   /* Save and restore input_line_pointer around this function.  */
1902   old_input_line_pointer = input_line_pointer;
1903   input_line_pointer = str;
1904
1905   while (*input_line_pointer)
1906     {
1907       SKIP_WHITESPACE ();
1908       switch (*input_line_pointer)
1909         {
1910         case '\0':
1911         case '}':
1912           goto fini;
1913
1914         case ':':
1915           input_line_pointer++;
1916           if (saw_comma || saw_colon || !saw_arg)
1917             goto err;
1918           saw_colon = TRUE;
1919           break;
1920
1921         case ',':
1922           input_line_pointer++;
1923           if (saw_comma || saw_colon || !saw_arg)
1924             goto err;
1925           saw_comma = TRUE;
1926           break;
1927
1928         default:
1929           if (!saw_comma && !saw_colon && saw_arg)
1930             goto err;
1931
1932           arg_end = input_line_pointer + 1;
1933           while (!expression_end (arg_end))
1934             arg_end += 1;
1935
1936           arg_len = arg_end - input_line_pointer;
1937           arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
1938           args[num_args] = arg;
1939
1940           if (saw_colon)
1941             *arg++ = ':';
1942           strncpy (arg, input_line_pointer, arg_len);
1943           arg[arg_len] = '\0';
1944
1945           input_line_pointer = arg_end;
1946           num_args += 1;
1947           saw_comma = FALSE;
1948           saw_colon = FALSE;
1949           saw_arg = TRUE;
1950           break;
1951         }
1952     }
1953
1954 fini:
1955   if (saw_comma || saw_colon)
1956     goto err;
1957   input_line_pointer = old_input_line_pointer;
1958   return num_args;
1959
1960 err:
1961   if (saw_comma)
1962     as_bad (_("extra comma"));
1963   else if (saw_colon)
1964     as_bad (_("extra colon"));
1965   else if (!saw_arg)
1966     as_bad (_("missing argument"));
1967   else
1968     as_bad (_("missing comma or colon"));
1969   input_line_pointer = old_input_line_pointer;
1970   return -1;
1971 }
1972
1973
1974 /* Parse the arguments to an opcode.  Return TRUE on error.  */
1975
1976 static bfd_boolean
1977 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
1978 {
1979   expressionS *tok, *last_tok;
1980   xtensa_opcode opcode = insn->opcode;
1981   bfd_boolean had_error = TRUE;
1982   xtensa_isa isa = xtensa_default_isa;
1983   int n, num_regs = 0;
1984   int opcode_operand_count;
1985   int opnd_cnt, last_opnd_cnt;
1986   unsigned int next_reg = 0;
1987   char *old_input_line_pointer;
1988
1989   if (insn->insn_type == ITYPE_LITERAL)
1990     opcode_operand_count = 1;
1991   else
1992     opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
1993
1994   tok = insn->tok;
1995   memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
1996
1997   /* Save and restore input_line_pointer around this function.  */
1998   old_input_line_pointer = input_line_pointer;
1999
2000   last_tok = 0;
2001   last_opnd_cnt = -1;
2002   opnd_cnt = 0;
2003
2004   /* Skip invisible operands.  */
2005   while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2006     {
2007       opnd_cnt += 1;
2008       tok++;
2009     }
2010
2011   for (n = 0; n < num_args; n++)
2012     {
2013       input_line_pointer = arg_strings[n];
2014       if (*input_line_pointer == ':')
2015         {
2016           xtensa_regfile opnd_rf;
2017           input_line_pointer++;
2018           if (num_regs == 0)
2019             goto err;
2020           gas_assert (opnd_cnt > 0);
2021           num_regs--;
2022           opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2023           if (next_reg
2024               != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2025             as_warn (_("incorrect register number, ignoring"));
2026           next_reg++;
2027         }
2028       else
2029         {
2030           if (opnd_cnt >= opcode_operand_count)
2031             {
2032               as_warn (_("too many arguments"));
2033               goto err;
2034             }
2035           gas_assert (opnd_cnt < MAX_INSN_ARGS);
2036
2037           expression_maybe_register (opcode, opnd_cnt, tok);
2038           next_reg = tok->X_add_number + 1;
2039
2040           if (tok->X_op == O_illegal || tok->X_op == O_absent)
2041             goto err;
2042           if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2043             {
2044               num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2045               /* minus 1 because we are seeing one right now */
2046             }
2047           else
2048             num_regs = 0;
2049
2050           last_tok = tok;
2051           last_opnd_cnt = opnd_cnt;
2052           demand_empty_rest_of_line ();
2053
2054           do
2055             {
2056               opnd_cnt += 1;
2057               tok++;
2058             }
2059           while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2060         }
2061     }
2062
2063   if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2064     goto err;
2065
2066   insn->ntok = tok - insn->tok;
2067   had_error = FALSE;
2068
2069  err:
2070   input_line_pointer = old_input_line_pointer;
2071   return had_error;
2072 }
2073
2074
2075 static int
2076 get_invisible_operands (TInsn *insn)
2077 {
2078   xtensa_isa isa = xtensa_default_isa;
2079   static xtensa_insnbuf slotbuf = NULL;
2080   xtensa_format fmt;
2081   xtensa_opcode opc = insn->opcode;
2082   int slot, opnd, fmt_found;
2083   unsigned val;
2084
2085   if (!slotbuf)
2086     slotbuf = xtensa_insnbuf_alloc (isa);
2087
2088   /* Find format/slot where this can be encoded.  */
2089   fmt_found = 0;
2090   slot = 0;
2091   for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2092     {
2093       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2094         {
2095           if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2096             {
2097               fmt_found = 1;
2098               break;
2099             }
2100         }
2101       if (fmt_found) break;
2102     }
2103
2104   if (!fmt_found)
2105     {
2106       as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2107       return -1;
2108     }
2109
2110   /* First encode all the visible operands
2111      (to deal with shared field operands).  */
2112   for (opnd = 0; opnd < insn->ntok; opnd++)
2113     {
2114       if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2115           && (insn->tok[opnd].X_op == O_register
2116               || insn->tok[opnd].X_op == O_constant))
2117         {
2118           val = insn->tok[opnd].X_add_number;
2119           xtensa_operand_encode (isa, opc, opnd, &val);
2120           xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2121         }
2122     }
2123
2124   /* Then pull out the values for the invisible ones.  */
2125   for (opnd = 0; opnd < insn->ntok; opnd++)
2126     {
2127       if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2128         {
2129           xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2130           xtensa_operand_decode (isa, opc, opnd, &val);
2131           insn->tok[opnd].X_add_number = val;
2132           if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2133             insn->tok[opnd].X_op = O_register;
2134           else
2135             insn->tok[opnd].X_op = O_constant;
2136         }
2137     }
2138
2139   return 0;
2140 }
2141
2142
2143 static void
2144 xg_reverse_shift_count (char **cnt_argp)
2145 {
2146   char *cnt_arg, *new_arg;
2147   cnt_arg = *cnt_argp;
2148
2149   /* replace the argument with "31-(argument)" */
2150   new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2151   sprintf (new_arg, "31-(%s)", cnt_arg);
2152
2153   free (cnt_arg);
2154   *cnt_argp = new_arg;
2155 }
2156
2157
2158 /* If "arg" is a constant expression, return non-zero with the value
2159    in *valp.  */
2160
2161 static int
2162 xg_arg_is_constant (char *arg, offsetT *valp)
2163 {
2164   expressionS exp;
2165   char *save_ptr = input_line_pointer;
2166
2167   input_line_pointer = arg;
2168   expression (&exp);
2169   input_line_pointer = save_ptr;
2170
2171   if (exp.X_op == O_constant)
2172     {
2173       *valp = exp.X_add_number;
2174       return 1;
2175     }
2176
2177   return 0;
2178 }
2179
2180
2181 static void
2182 xg_replace_opname (char **popname, char *newop)
2183 {
2184   free (*popname);
2185   *popname = (char *) xmalloc (strlen (newop) + 1);
2186   strcpy (*popname, newop);
2187 }
2188
2189
2190 static int
2191 xg_check_num_args (int *pnum_args,
2192                    int expected_num,
2193                    char *opname,
2194                    char **arg_strings)
2195 {
2196   int num_args = *pnum_args;
2197
2198   if (num_args < expected_num)
2199     {
2200       as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2201               num_args, opname, expected_num);
2202       return -1;
2203     }
2204
2205   if (num_args > expected_num)
2206     {
2207       as_warn (_("too many operands (%d) for '%s'; expected %d"),
2208                num_args, opname, expected_num);
2209       while (num_args-- > expected_num)
2210         {
2211           free (arg_strings[num_args]);
2212           arg_strings[num_args] = 0;
2213         }
2214       *pnum_args = expected_num;
2215       return -1;
2216     }
2217
2218   return 0;
2219 }
2220
2221
2222 /* If the register is not specified as part of the opcode,
2223    then get it from the operand and move it to the opcode.  */
2224
2225 static int
2226 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2227 {
2228   xtensa_isa isa = xtensa_default_isa;
2229   xtensa_sysreg sr;
2230   char *opname, *new_opname;
2231   const char *sr_name;
2232   int is_user, is_write;
2233
2234   opname = *popname;
2235   if (*opname == '_')
2236     opname += 1;
2237   is_user = (opname[1] == 'u');
2238   is_write = (opname[0] == 'w');
2239
2240   /* Opname == [rw]ur or [rwx]sr... */
2241
2242   if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2243     return -1;
2244
2245   /* Check if the argument is a symbolic register name.  */
2246   sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2247   /* Handle WSR to "INTSET" as a special case.  */
2248   if (sr == XTENSA_UNDEFINED && is_write && !is_user
2249       && !strcasecmp (arg_strings[1], "intset"))
2250     sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2251   if (sr == XTENSA_UNDEFINED
2252       || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2253     {
2254       /* Maybe it's a register number.... */
2255       offsetT val;
2256       if (!xg_arg_is_constant (arg_strings[1], &val))
2257         {
2258           as_bad (_("invalid register '%s' for '%s' instruction"),
2259                   arg_strings[1], opname);
2260           return -1;
2261         }
2262       sr = xtensa_sysreg_lookup (isa, val, is_user);
2263       if (sr == XTENSA_UNDEFINED)
2264         {
2265           as_bad (_("invalid register number (%ld) for '%s' instruction"),
2266                   (long) val, opname);
2267           return -1;
2268         }
2269     }
2270
2271   /* Remove the last argument, which is now part of the opcode.  */
2272   free (arg_strings[1]);
2273   arg_strings[1] = 0;
2274   *pnum_args = 1;
2275
2276   /* Translate the opcode.  */
2277   sr_name = xtensa_sysreg_name (isa, sr);
2278   /* Another special case for "WSR.INTSET"....  */
2279   if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2280     sr_name = "intset";
2281   new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2282   sprintf (new_opname, "%s.%s", *popname, sr_name);
2283   free (*popname);
2284   *popname = new_opname;
2285
2286   return 0;
2287 }
2288
2289
2290 static int
2291 xtensa_translate_old_userreg_ops (char **popname)
2292 {
2293   xtensa_isa isa = xtensa_default_isa;
2294   xtensa_sysreg sr;
2295   char *opname, *new_opname;
2296   const char *sr_name;
2297   bfd_boolean has_underbar = FALSE;
2298
2299   opname = *popname;
2300   if (opname[0] == '_')
2301     {
2302       has_underbar = TRUE;
2303       opname += 1;
2304     }
2305
2306   sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2307   if (sr != XTENSA_UNDEFINED)
2308     {
2309       /* The new default name ("nnn") is different from the old default
2310          name ("URnnn").  The old default is handled below, and we don't
2311          want to recognize [RW]nnn, so do nothing if the name is the (new)
2312          default.  */
2313       static char namebuf[10];
2314       sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2315       if (strcmp (namebuf, opname + 1) == 0)
2316         return 0;
2317     }
2318   else
2319     {
2320       offsetT val;
2321       char *end;
2322
2323       /* Only continue if the reg name is "URnnn".  */
2324       if (opname[1] != 'u' || opname[2] != 'r')
2325         return 0;
2326       val = strtoul (opname + 3, &end, 10);
2327       if (*end != '\0')
2328         return 0;
2329
2330       sr = xtensa_sysreg_lookup (isa, val, 1);
2331       if (sr == XTENSA_UNDEFINED)
2332         {
2333           as_bad (_("invalid register number (%ld) for '%s'"),
2334                   (long) val, opname);
2335           return -1;
2336         }
2337     }
2338
2339   /* Translate the opcode.  */
2340   sr_name = xtensa_sysreg_name (isa, sr);
2341   new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2342   sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2343            opname[0], sr_name);
2344   free (*popname);
2345   *popname = new_opname;
2346
2347   return 0;
2348 }
2349
2350
2351 static int
2352 xtensa_translate_zero_immed (char *old_op,
2353                              char *new_op,
2354                              char **popname,
2355                              int *pnum_args,
2356                              char **arg_strings)
2357 {
2358   char *opname;
2359   offsetT val;
2360
2361   opname = *popname;
2362   gas_assert (opname[0] != '_');
2363
2364   if (strcmp (opname, old_op) != 0)
2365     return 0;
2366
2367   if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2368     return -1;
2369   if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2370     {
2371       xg_replace_opname (popname, new_op);
2372       free (arg_strings[1]);
2373       arg_strings[1] = arg_strings[2];
2374       arg_strings[2] = 0;
2375       *pnum_args = 2;
2376     }
2377
2378   return 0;
2379 }
2380
2381
2382 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2383    Returns non-zero if an error was found.  */
2384
2385 static int
2386 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2387 {
2388   char *opname = *popname;
2389   bfd_boolean has_underbar = FALSE;
2390
2391   if (*opname == '_')
2392     {
2393       has_underbar = TRUE;
2394       opname += 1;
2395     }
2396
2397   if (strcmp (opname, "mov") == 0)
2398     {
2399       if (use_transform () && !has_underbar && density_supported)
2400         xg_replace_opname (popname, "mov.n");
2401       else
2402         {
2403           if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2404             return -1;
2405           xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2406           arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2407           strcpy (arg_strings[2], arg_strings[1]);
2408           *pnum_args = 3;
2409         }
2410       return 0;
2411     }
2412
2413   if (strcmp (opname, "bbsi.l") == 0)
2414     {
2415       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2416         return -1;
2417       xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2418       if (target_big_endian)
2419         xg_reverse_shift_count (&arg_strings[1]);
2420       return 0;
2421     }
2422
2423   if (strcmp (opname, "bbci.l") == 0)
2424     {
2425       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2426         return -1;
2427       xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2428       if (target_big_endian)
2429         xg_reverse_shift_count (&arg_strings[1]);
2430       return 0;
2431     }
2432
2433   /* Don't do anything special with NOPs inside FLIX instructions.  They
2434      are handled elsewhere.  Real NOP instructions are always available
2435      in configurations with FLIX, so this should never be an issue but
2436      check for it anyway.  */
2437   if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
2438       && strcmp (opname, "nop") == 0)
2439     {
2440       if (use_transform () && !has_underbar && density_supported)
2441         xg_replace_opname (popname, "nop.n");
2442       else
2443         {
2444           if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2445             return -1;
2446           xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2447           arg_strings[0] = (char *) xmalloc (3);
2448           arg_strings[1] = (char *) xmalloc (3);
2449           arg_strings[2] = (char *) xmalloc (3);
2450           strcpy (arg_strings[0], "a1");
2451           strcpy (arg_strings[1], "a1");
2452           strcpy (arg_strings[2], "a1");
2453           *pnum_args = 3;
2454         }
2455       return 0;
2456     }
2457
2458   /* Recognize [RW]UR and [RWX]SR.  */
2459   if ((((opname[0] == 'r' || opname[0] == 'w')
2460         && (opname[1] == 'u' || opname[1] == 's'))
2461        || (opname[0] == 'x' && opname[1] == 's'))
2462       && opname[2] == 'r'
2463       && opname[3] == '\0')
2464     return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2465
2466   /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2467      [RW]<name> if <name> is the non-default name of a user register.  */
2468   if ((opname[0] == 'r' || opname[0] == 'w')
2469       && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2470     return xtensa_translate_old_userreg_ops (popname);
2471
2472   /* Relax branches that don't allow comparisons against an immediate value
2473      of zero to the corresponding branches with implicit zero immediates.  */
2474   if (!has_underbar && use_transform ())
2475     {
2476       if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2477                                        pnum_args, arg_strings))
2478         return -1;
2479
2480       if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2481                                        pnum_args, arg_strings))
2482         return -1;
2483
2484       if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2485                                        pnum_args, arg_strings))
2486         return -1;
2487
2488       if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2489                                        pnum_args, arg_strings))
2490         return -1;
2491     }
2492
2493   return 0;
2494 }
2495
2496 \f
2497 /* Functions for dealing with the Xtensa ISA.  */
2498
2499 /* Currently the assembler only allows us to use a single target per
2500    fragment.  Because of this, only one operand for a given
2501    instruction may be symbolic.  If there is a PC-relative operand,
2502    the last one is chosen.  Otherwise, the result is the number of the
2503    last immediate operand, and if there are none of those, we fail and
2504    return -1.  */
2505
2506 static int
2507 get_relaxable_immed (xtensa_opcode opcode)
2508 {
2509   int last_immed = -1;
2510   int noperands, opi;
2511
2512   if (opcode == XTENSA_UNDEFINED)
2513     return -1;
2514
2515   noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2516   for (opi = noperands - 1; opi >= 0; opi--)
2517     {
2518       if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2519         continue;
2520       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2521         return opi;
2522       if (last_immed == -1
2523           && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2524         last_immed = opi;
2525     }
2526   return last_immed;
2527 }
2528
2529
2530 static xtensa_opcode
2531 get_opcode_from_buf (const char *buf, int slot)
2532 {
2533   static xtensa_insnbuf insnbuf = NULL;
2534   static xtensa_insnbuf slotbuf = NULL;
2535   xtensa_isa isa = xtensa_default_isa;
2536   xtensa_format fmt;
2537
2538   if (!insnbuf)
2539     {
2540       insnbuf = xtensa_insnbuf_alloc (isa);
2541       slotbuf = xtensa_insnbuf_alloc (isa);
2542     }
2543
2544   xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
2545   fmt = xtensa_format_decode (isa, insnbuf);
2546   if (fmt == XTENSA_UNDEFINED)
2547     return XTENSA_UNDEFINED;
2548
2549   if (slot >= xtensa_format_num_slots (isa, fmt))
2550     return XTENSA_UNDEFINED;
2551
2552   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2553   return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2554 }
2555
2556
2557 #ifdef TENSILICA_DEBUG
2558
2559 /* For debugging, print out the mapping of opcode numbers to opcodes.  */
2560
2561 static void
2562 xtensa_print_insn_table (void)
2563 {
2564   int num_opcodes, num_operands;
2565   xtensa_opcode opcode;
2566   xtensa_isa isa = xtensa_default_isa;
2567
2568   num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2569   for (opcode = 0; opcode < num_opcodes; opcode++)
2570     {
2571       int opn;
2572       fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2573       num_operands = xtensa_opcode_num_operands (isa, opcode);
2574       for (opn = 0; opn < num_operands; opn++)
2575         {
2576           if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2577             continue;
2578           if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2579             {
2580               xtensa_regfile opnd_rf =
2581                 xtensa_operand_regfile (isa, opcode, opn);
2582               fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2583             }
2584           else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2585             fputs ("[lLr] ", stderr);
2586           else
2587             fputs ("i ", stderr);
2588         }
2589       fprintf (stderr, "\n");
2590     }
2591 }
2592
2593
2594 static void
2595 print_vliw_insn (xtensa_insnbuf vbuf)
2596 {
2597   xtensa_isa isa = xtensa_default_isa;
2598   xtensa_format f = xtensa_format_decode (isa, vbuf);
2599   xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2600   int op;
2601
2602   fprintf (stderr, "format = %d\n", f);
2603
2604   for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2605     {
2606       xtensa_opcode opcode;
2607       const char *opname;
2608       int operands;
2609
2610       xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2611       opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2612       opname = xtensa_opcode_name (isa, opcode);
2613
2614       fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2615       fprintf (stderr, "   operands = ");
2616       for (operands = 0;
2617            operands < xtensa_opcode_num_operands (isa, opcode);
2618            operands++)
2619         {
2620           unsigned int val;
2621           if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2622             continue;
2623           xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2624           xtensa_operand_decode (isa, opcode, operands, &val);
2625           fprintf (stderr, "%d ", val);
2626         }
2627       fprintf (stderr, "\n");
2628     }
2629   xtensa_insnbuf_free (isa, sbuf);
2630 }
2631
2632 #endif /* TENSILICA_DEBUG */
2633
2634
2635 static bfd_boolean
2636 is_direct_call_opcode (xtensa_opcode opcode)
2637 {
2638   xtensa_isa isa = xtensa_default_isa;
2639   int n, num_operands;
2640
2641   if (xtensa_opcode_is_call (isa, opcode) != 1)
2642     return FALSE;
2643
2644   num_operands = xtensa_opcode_num_operands (isa, opcode);
2645   for (n = 0; n < num_operands; n++)
2646     {
2647       if (xtensa_operand_is_register (isa, opcode, n) == 0
2648           && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2649         return TRUE;
2650     }
2651   return FALSE;
2652 }
2653
2654
2655 /* Convert from BFD relocation type code to slot and operand number.
2656    Returns non-zero on failure.  */
2657
2658 static int
2659 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
2660 {
2661   if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2662       && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2663     {
2664       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2665       *is_alt = FALSE;
2666     }
2667   else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2668       && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2669     {
2670       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2671       *is_alt = TRUE;
2672     }
2673   else
2674     return -1;
2675
2676   return 0;
2677 }
2678
2679
2680 /* Convert from slot number to BFD relocation type code for the
2681    standard PC-relative relocations.  Return BFD_RELOC_NONE on
2682    failure.  */
2683
2684 static bfd_reloc_code_real_type
2685 encode_reloc (int slot)
2686 {
2687   if (slot < 0 || slot > 14)
2688     return BFD_RELOC_NONE;
2689
2690   return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2691 }
2692
2693
2694 /* Convert from slot numbers to BFD relocation type code for the
2695    "alternate" relocations.  Return BFD_RELOC_NONE on failure.  */
2696
2697 static bfd_reloc_code_real_type
2698 encode_alt_reloc (int slot)
2699 {
2700   if (slot < 0 || slot > 14)
2701     return BFD_RELOC_NONE;
2702
2703   return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2704 }
2705
2706
2707 static void
2708 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2709                             xtensa_format fmt,
2710                             int slot,
2711                             xtensa_opcode opcode,
2712                             int operand,
2713                             uint32 value,
2714                             const char *file,
2715                             unsigned int line)
2716 {
2717   uint32 valbuf = value;
2718
2719   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2720     {
2721       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2722           == 1)
2723         as_bad_where ((char *) file, line,
2724                       _("operand %d of '%s' has out of range value '%u'"),
2725                       operand + 1,
2726                       xtensa_opcode_name (xtensa_default_isa, opcode),
2727                       value);
2728       else
2729         as_bad_where ((char *) file, line,
2730                       _("operand %d of '%s' has invalid value '%u'"),
2731                       operand + 1,
2732                       xtensa_opcode_name (xtensa_default_isa, opcode),
2733                       value);
2734       return;
2735     }
2736
2737   xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2738                             slotbuf, valbuf);
2739 }
2740
2741
2742 static uint32
2743 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2744                             xtensa_format fmt,
2745                             int slot,
2746                             xtensa_opcode opcode,
2747                             int opnum)
2748 {
2749   uint32 val = 0;
2750   (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2751                                    fmt, slot, slotbuf, &val);
2752   (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2753   return val;
2754 }
2755
2756 \f
2757 /* Checks for rules from xtensa-relax tables.  */
2758
2759 /* The routine xg_instruction_matches_option_term must return TRUE
2760    when a given option term is true.  The meaning of all of the option
2761    terms is given interpretation by this function.  */
2762
2763 static bfd_boolean
2764 xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option)
2765 {
2766   if (strcmp (option->option_name, "realnop") == 0
2767       || strncmp (option->option_name, "IsaUse", 6) == 0)
2768     {
2769       /* These conditions were evaluated statically when building the
2770          relaxation table.  There's no need to reevaluate them now.  */
2771       return TRUE;
2772     }
2773   else if (strcmp (option->option_name, "FREEREG") == 0)
2774     return insn->extra_arg.X_op == O_register;
2775   else
2776     {
2777       as_fatal (_("internal error: unknown option name '%s'"),
2778                 option->option_name);
2779     }
2780 }
2781
2782
2783 static bfd_boolean
2784 xg_instruction_matches_or_options (TInsn *insn,
2785                                    const ReqOrOptionList *or_option)
2786 {
2787   const ReqOrOption *option;
2788   /* Must match each of the AND terms.  */
2789   for (option = or_option; option != NULL; option = option->next)
2790     {
2791       if (xg_instruction_matches_option_term (insn, option))
2792         return TRUE;
2793     }
2794   return FALSE;
2795 }
2796
2797
2798 static bfd_boolean
2799 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2800 {
2801   const ReqOption *req_options;
2802   /* Must match each of the AND terms.  */
2803   for (req_options = options;
2804        req_options != NULL;
2805        req_options = req_options->next)
2806     {
2807       /* Must match one of the OR clauses.  */
2808       if (!xg_instruction_matches_or_options (insn,
2809                                               req_options->or_option_terms))
2810         return FALSE;
2811     }
2812   return TRUE;
2813 }
2814
2815
2816 /* Return the transition rule that matches or NULL if none matches.  */
2817
2818 static bfd_boolean
2819 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2820 {
2821   PreconditionList *condition_l;
2822
2823   if (rule->opcode != insn->opcode)
2824     return FALSE;
2825
2826   for (condition_l = rule->conditions;
2827        condition_l != NULL;
2828        condition_l = condition_l->next)
2829     {
2830       expressionS *exp1;
2831       expressionS *exp2;
2832       Precondition *cond = condition_l->precond;
2833
2834       switch (cond->typ)
2835         {
2836         case OP_CONSTANT:
2837           /* The expression must be the constant.  */
2838           gas_assert (cond->op_num < insn->ntok);
2839           exp1 = &insn->tok[cond->op_num];
2840           if (expr_is_const (exp1))
2841             {
2842               switch (cond->cmp)
2843                 {
2844                 case OP_EQUAL:
2845                   if (get_expr_const (exp1) != cond->op_data)
2846                     return FALSE;
2847                   break;
2848                 case OP_NOTEQUAL:
2849                   if (get_expr_const (exp1) == cond->op_data)
2850                     return FALSE;
2851                   break;
2852                 default:
2853                   return FALSE;
2854                 }
2855             }
2856           else if (expr_is_register (exp1))
2857             {
2858               switch (cond->cmp)
2859                 {
2860                 case OP_EQUAL:
2861                   if (get_expr_register (exp1) != cond->op_data)
2862                     return FALSE;
2863                   break;
2864                 case OP_NOTEQUAL:
2865                   if (get_expr_register (exp1) == cond->op_data)
2866                     return FALSE;
2867                   break;
2868                 default:
2869                   return FALSE;
2870                 }
2871             }
2872           else
2873             return FALSE;
2874           break;
2875
2876         case OP_OPERAND:
2877           gas_assert (cond->op_num < insn->ntok);
2878           gas_assert (cond->op_data < insn->ntok);
2879           exp1 = &insn->tok[cond->op_num];
2880           exp2 = &insn->tok[cond->op_data];
2881
2882           switch (cond->cmp)
2883             {
2884             case OP_EQUAL:
2885               if (!expr_is_equal (exp1, exp2))
2886                 return FALSE;
2887               break;
2888             case OP_NOTEQUAL:
2889               if (expr_is_equal (exp1, exp2))
2890                 return FALSE;
2891               break;
2892             }
2893           break;
2894
2895         case OP_LITERAL:
2896         case OP_LABEL:
2897         default:
2898           return FALSE;
2899         }
2900     }
2901   if (!xg_instruction_matches_options (insn, rule->options))
2902     return FALSE;
2903
2904   return TRUE;
2905 }
2906
2907
2908 static int
2909 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2910 {
2911   bfd_boolean a_greater = FALSE;
2912   bfd_boolean b_greater = FALSE;
2913
2914   ReqOptionList *l_a = a->options;
2915   ReqOptionList *l_b = b->options;
2916
2917   /* We only care if they both are the same except for
2918      a const16 vs. an l32r.  */
2919
2920   while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2921     {
2922       ReqOrOptionList *l_or_a = l_a->or_option_terms;
2923       ReqOrOptionList *l_or_b = l_b->or_option_terms;
2924       while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2925         {
2926           if (l_or_a->is_true != l_or_b->is_true)
2927             return 0;
2928           if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
2929             {
2930               /* This is the case we care about.  */
2931               if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
2932                   && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
2933                 {
2934                   if (prefer_const16)
2935                     a_greater = TRUE;
2936                   else
2937                     b_greater = TRUE;
2938                 }
2939               else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
2940                        && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
2941                 {
2942                   if (prefer_const16)
2943                     b_greater = TRUE;
2944                   else
2945                     a_greater = TRUE;
2946                 }
2947               else
2948                 return 0;
2949             }
2950           l_or_a = l_or_a->next;
2951           l_or_b = l_or_b->next;
2952         }
2953       if (l_or_a || l_or_b)
2954         return 0;
2955
2956       l_a = l_a->next;
2957       l_b = l_b->next;
2958     }
2959   if (l_a || l_b)
2960     return 0;
2961
2962   /* Incomparable if the substitution was used differently in two cases.  */
2963   if (a_greater && b_greater)
2964     return 0;
2965
2966   if (b_greater)
2967     return 1;
2968   if (a_greater)
2969     return -1;
2970
2971   return 0;
2972 }
2973
2974
2975 static TransitionRule *
2976 xg_instruction_match (TInsn *insn)
2977 {
2978   TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
2979   TransitionList *l;
2980   gas_assert (insn->opcode < table->num_opcodes);
2981
2982   /* Walk through all of the possible transitions.  */
2983   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
2984     {
2985       TransitionRule *rule = l->rule;
2986       if (xg_instruction_matches_rule (insn, rule))
2987         return rule;
2988     }
2989   return NULL;
2990 }
2991
2992 \f
2993 /* Various Other Internal Functions.  */
2994
2995 static bfd_boolean
2996 is_unique_insn_expansion (TransitionRule *r)
2997 {
2998   if (!r->to_instr || r->to_instr->next != NULL)
2999     return FALSE;
3000   if (r->to_instr->typ != INSTR_INSTR)
3001     return FALSE;
3002   return TRUE;
3003 }
3004
3005
3006 /* Check if there is exactly one relaxation for INSN that converts it to
3007    another instruction of equal or larger size.  If so, and if TARG is
3008    non-null, go ahead and generate the relaxed instruction into TARG.  If
3009    NARROW_ONLY is true, then only consider relaxations that widen a narrow
3010    instruction, i.e., ignore relaxations that convert to an instruction of
3011    equal size.  In some contexts where this function is used, only
3012    a single widening is allowed and the NARROW_ONLY argument is used to
3013    exclude cases like ADDI being "widened" to an ADDMI, which may
3014    later be relaxed to an ADDMI/ADDI pair.  */
3015
3016 bfd_boolean
3017 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
3018 {
3019   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3020   TransitionList *l;
3021   TransitionRule *match = 0;
3022
3023   gas_assert (insn->insn_type == ITYPE_INSN);
3024   gas_assert (insn->opcode < table->num_opcodes);
3025
3026   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3027     {
3028       TransitionRule *rule = l->rule;
3029
3030       if (xg_instruction_matches_rule (insn, rule)
3031           && is_unique_insn_expansion (rule)
3032           && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
3033               <= xg_get_single_size (rule->to_instr->opcode)))
3034         {
3035           if (match)
3036             return FALSE;
3037           match = rule;
3038         }
3039     }
3040   if (!match)
3041     return FALSE;
3042
3043   if (targ)
3044     xg_build_to_insn (targ, insn, match->to_instr);
3045   return TRUE;
3046 }
3047
3048
3049 /* Return the maximum number of bytes this opcode can expand to.  */
3050
3051 static int
3052 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3053 {
3054   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3055   TransitionList *l;
3056   int max_size = xg_get_single_size (opcode);
3057
3058   gas_assert (opcode < table->num_opcodes);
3059
3060   for (l = table->table[opcode]; l != NULL; l = l->next)
3061     {
3062       TransitionRule *rule = l->rule;
3063       BuildInstr *build_list;
3064       int this_size = 0;
3065
3066       if (!rule)
3067         continue;
3068       build_list = rule->to_instr;
3069       if (is_unique_insn_expansion (rule))
3070         {
3071           gas_assert (build_list->typ == INSTR_INSTR);
3072           this_size = xg_get_max_insn_widen_size (build_list->opcode);
3073         }
3074       else
3075         for (; build_list != NULL; build_list = build_list->next)
3076           {
3077             switch (build_list->typ)
3078               {
3079               case INSTR_INSTR:
3080                 this_size += xg_get_single_size (build_list->opcode);
3081                 break;
3082               case INSTR_LITERAL_DEF:
3083               case INSTR_LABEL_DEF:
3084               default:
3085                 break;
3086               }
3087           }
3088       if (this_size > max_size)
3089         max_size = this_size;
3090     }
3091   return max_size;
3092 }
3093
3094
3095 /* Return the maximum number of literal bytes this opcode can generate.  */
3096
3097 static int
3098 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3099 {
3100   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3101   TransitionList *l;
3102   int max_size = 0;
3103
3104   gas_assert (opcode < table->num_opcodes);
3105
3106   for (l = table->table[opcode]; l != NULL; l = l->next)
3107     {
3108       TransitionRule *rule = l->rule;
3109       BuildInstr *build_list;
3110       int this_size = 0;
3111
3112       if (!rule)
3113         continue;
3114       build_list = rule->to_instr;
3115       if (is_unique_insn_expansion (rule))
3116         {
3117           gas_assert (build_list->typ == INSTR_INSTR);
3118           this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3119         }
3120       else
3121         for (; build_list != NULL; build_list = build_list->next)
3122           {
3123             switch (build_list->typ)
3124               {
3125               case INSTR_LITERAL_DEF:
3126                 /* Hard-coded 4-byte literal.  */
3127                 this_size += 4;
3128                 break;
3129               case INSTR_INSTR:
3130               case INSTR_LABEL_DEF:
3131               default:
3132                 break;
3133               }
3134           }
3135       if (this_size > max_size)
3136         max_size = this_size;
3137     }
3138   return max_size;
3139 }
3140
3141
3142 static bfd_boolean
3143 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3144 {
3145   int steps_taken = 0;
3146   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3147   TransitionList *l;
3148
3149   gas_assert (insn->insn_type == ITYPE_INSN);
3150   gas_assert (insn->opcode < table->num_opcodes);
3151
3152   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3153     {
3154       TransitionRule *rule = l->rule;
3155
3156       if (xg_instruction_matches_rule (insn, rule))
3157         {
3158           if (steps_taken == lateral_steps)
3159             return TRUE;
3160           steps_taken++;
3161         }
3162     }
3163   return FALSE;
3164 }
3165
3166
3167 static symbolS *
3168 get_special_literal_symbol (void)
3169 {
3170   static symbolS *sym = NULL;
3171
3172   if (sym == NULL)
3173     sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3174   return sym;
3175 }
3176
3177
3178 static symbolS *
3179 get_special_label_symbol (void)
3180 {
3181   static symbolS *sym = NULL;
3182
3183   if (sym == NULL)
3184     sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3185   return sym;
3186 }
3187
3188
3189 static bfd_boolean
3190 xg_valid_literal_expression (const expressionS *exp)
3191 {
3192   switch (exp->X_op)
3193     {
3194     case O_constant:
3195     case O_symbol:
3196     case O_big:
3197     case O_uminus:
3198     case O_subtract:
3199     case O_pltrel:
3200     case O_pcrel:
3201     case O_tlsfunc:
3202     case O_tlsarg:
3203     case O_tpoff:
3204     case O_dtpoff:
3205       return TRUE;
3206     default:
3207       return FALSE;
3208     }
3209 }
3210
3211
3212 /* This will check to see if the value can be converted into the
3213    operand type.  It will return TRUE if it does not fit.  */
3214
3215 static bfd_boolean
3216 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3217 {
3218   uint32 valbuf = value;
3219   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3220     return TRUE;
3221   return FALSE;
3222 }
3223
3224
3225 /* Assumes: All immeds are constants.  Check that all constants fit
3226    into their immeds; return FALSE if not.  */
3227
3228 static bfd_boolean
3229 xg_immeds_fit (const TInsn *insn)
3230 {
3231   xtensa_isa isa = xtensa_default_isa;
3232   int i;
3233
3234   int n = insn->ntok;
3235   gas_assert (insn->insn_type == ITYPE_INSN);
3236   for (i = 0; i < n; ++i)
3237     {
3238       const expressionS *expr = &insn->tok[i];
3239       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3240         continue;
3241
3242       switch (expr->X_op)
3243         {
3244         case O_register:
3245         case O_constant:
3246           if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3247             return FALSE;
3248           break;
3249
3250         default:
3251           /* The symbol should have a fixup associated with it.  */
3252           gas_assert (FALSE);
3253           break;
3254         }
3255     }
3256   return TRUE;
3257 }
3258
3259
3260 /* This should only be called after we have an initial
3261    estimate of the addresses.  */
3262
3263 static bfd_boolean
3264 xg_symbolic_immeds_fit (const TInsn *insn,
3265                         segT pc_seg,
3266                         fragS *pc_frag,
3267                         offsetT pc_offset,
3268                         long stretch)
3269 {
3270   xtensa_isa isa = xtensa_default_isa;
3271   symbolS *symbolP;
3272   fragS *sym_frag;
3273   offsetT target, pc;
3274   uint32 new_offset;
3275   int i;
3276   int n = insn->ntok;
3277
3278   gas_assert (insn->insn_type == ITYPE_INSN);
3279
3280   for (i = 0; i < n; ++i)
3281     {
3282       const expressionS *expr = &insn->tok[i];
3283       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3284         continue;
3285
3286       switch (expr->X_op)
3287         {
3288         case O_register:
3289         case O_constant:
3290           if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3291             return FALSE;
3292           break;
3293
3294         case O_lo16:
3295         case O_hi16:
3296           /* Check for the worst case.  */
3297           if (xg_check_operand (0xffff, insn->opcode, i))
3298             return FALSE;
3299           break;
3300
3301         case O_symbol:
3302           /* We only allow symbols for PC-relative references.
3303              If pc_frag == 0, then we don't have frag locations yet.  */
3304           if (pc_frag == 0
3305               || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
3306             return FALSE;
3307
3308           /* If it is a weak symbol or a symbol in a different section,
3309              it cannot be known to fit at assembly time.  */
3310           if (S_IS_WEAK (expr->X_add_symbol)
3311               || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3312             {
3313               /* For a direct call with --no-longcalls, be optimistic and
3314                  assume it will be in range.  If the symbol is weak and
3315                  undefined, it may remain undefined at link-time, in which
3316                  case it will have a zero value and almost certainly be out
3317                  of range for a direct call; thus, relax for undefined weak
3318                  symbols even if longcalls is not enabled.  */
3319               if (is_direct_call_opcode (insn->opcode)
3320                   && ! pc_frag->tc_frag_data.use_longcalls
3321                   && (! S_IS_WEAK (expr->X_add_symbol)
3322                       || S_IS_DEFINED (expr->X_add_symbol)))
3323                 return TRUE;
3324
3325               return FALSE;
3326             }
3327
3328           symbolP = expr->X_add_symbol;
3329           sym_frag = symbol_get_frag (symbolP);
3330           target = S_GET_VALUE (symbolP) + expr->X_add_number;
3331           pc = pc_frag->fr_address + pc_offset;
3332
3333           /* If frag has yet to be reached on this pass, assume it
3334              will move by STRETCH just as we did.  If this is not so,
3335              it will be because some frag between grows, and that will
3336              force another pass.  Beware zero-length frags.  There
3337              should be a faster way to do this.  */
3338
3339           if (stretch != 0
3340               && sym_frag->relax_marker != pc_frag->relax_marker
3341               && S_GET_SEGMENT (symbolP) == pc_seg)
3342             {
3343               target += stretch;
3344             }
3345
3346           new_offset = target;
3347           xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3348           if (xg_check_operand (new_offset, insn->opcode, i))
3349             return FALSE;
3350           break;
3351
3352         default:
3353           /* The symbol should have a fixup associated with it.  */
3354           return FALSE;
3355         }
3356     }
3357
3358   return TRUE;
3359 }
3360
3361
3362 /* Return TRUE on success.  */
3363
3364 static bfd_boolean
3365 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3366 {
3367   BuildOp *op;
3368   symbolS *sym;
3369
3370   tinsn_init (targ);
3371   targ->debug_line = insn->debug_line;
3372   targ->loc_directive_seen = insn->loc_directive_seen;
3373   switch (bi->typ)
3374     {
3375     case INSTR_INSTR:
3376       op = bi->ops;
3377       targ->opcode = bi->opcode;
3378       targ->insn_type = ITYPE_INSN;
3379       targ->is_specific_opcode = FALSE;
3380
3381       for (; op != NULL; op = op->next)
3382         {
3383           int op_num = op->op_num;
3384           int op_data = op->op_data;
3385
3386           gas_assert (op->op_num < MAX_INSN_ARGS);
3387
3388           if (targ->ntok <= op_num)
3389             targ->ntok = op_num + 1;
3390
3391           switch (op->typ)
3392             {
3393             case OP_CONSTANT:
3394               set_expr_const (&targ->tok[op_num], op_data);
3395               break;
3396             case OP_OPERAND:
3397               gas_assert (op_data < insn->ntok);
3398               copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3399               break;
3400             case OP_FREEREG:
3401               if (insn->extra_arg.X_op != O_register)
3402                 return FALSE;
3403               copy_expr (&targ->tok[op_num], &insn->extra_arg);
3404               break;
3405             case OP_LITERAL:
3406               sym = get_special_literal_symbol ();
3407               set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3408               if (insn->tok[op_data].X_op == O_tlsfunc
3409                   || insn->tok[op_data].X_op == O_tlsarg)
3410                 copy_expr (&targ->extra_arg, &insn->tok[op_data]);
3411               break;
3412             case OP_LABEL:
3413               sym = get_special_label_symbol ();
3414               set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3415               break;
3416             case OP_OPERAND_HI16U:
3417             case OP_OPERAND_LOW16U:
3418               gas_assert (op_data < insn->ntok);
3419               if (expr_is_const (&insn->tok[op_data]))
3420                 {
3421                   long val;
3422                   copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3423                   val = xg_apply_userdef_op_fn (op->typ,
3424                                                 targ->tok[op_num].
3425                                                 X_add_number);
3426                   targ->tok[op_num].X_add_number = val;
3427                 }
3428               else
3429                 {
3430                   /* For const16 we can create relocations for these.  */
3431                   if (targ->opcode == XTENSA_UNDEFINED
3432                       || (targ->opcode != xtensa_const16_opcode))
3433                     return FALSE;
3434                   gas_assert (op_data < insn->ntok);
3435                   /* Need to build a O_lo16 or O_hi16.  */
3436                   copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3437                   if (targ->tok[op_num].X_op == O_symbol)
3438                     {
3439                       if (op->typ == OP_OPERAND_HI16U)
3440                         targ->tok[op_num].X_op = O_hi16;
3441                       else if (op->typ == OP_OPERAND_LOW16U)
3442                         targ->tok[op_num].X_op = O_lo16;
3443                       else
3444                         return FALSE;
3445                     }
3446                 }
3447               break;
3448             default:
3449               /* currently handles:
3450                  OP_OPERAND_LOW8
3451                  OP_OPERAND_HI24S
3452                  OP_OPERAND_F32MINUS */
3453               if (xg_has_userdef_op_fn (op->typ))
3454                 {
3455                   gas_assert (op_data < insn->ntok);
3456                   if (expr_is_const (&insn->tok[op_data]))
3457                     {
3458                       long val;
3459                       copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3460                       val = xg_apply_userdef_op_fn (op->typ,
3461                                                     targ->tok[op_num].
3462                                                     X_add_number);
3463                       targ->tok[op_num].X_add_number = val;
3464                     }
3465                   else
3466                     return FALSE; /* We cannot use a relocation for this.  */
3467                   break;
3468                 }
3469               gas_assert (0);
3470               break;
3471             }
3472         }
3473       break;
3474
3475     case INSTR_LITERAL_DEF:
3476       op = bi->ops;
3477       targ->opcode = XTENSA_UNDEFINED;
3478       targ->insn_type = ITYPE_LITERAL;
3479       targ->is_specific_opcode = FALSE;
3480       for (; op != NULL; op = op->next)
3481         {
3482           int op_num = op->op_num;
3483           int op_data = op->op_data;
3484           gas_assert (op->op_num < MAX_INSN_ARGS);
3485
3486           if (targ->ntok <= op_num)
3487             targ->ntok = op_num + 1;
3488
3489           switch (op->typ)
3490             {
3491             case OP_OPERAND:
3492               gas_assert (op_data < insn->ntok);
3493               /* We can only pass resolvable literals through.  */
3494               if (!xg_valid_literal_expression (&insn->tok[op_data]))
3495                 return FALSE;
3496               copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3497               break;
3498             case OP_LITERAL:
3499             case OP_CONSTANT:
3500             case OP_LABEL:
3501             default:
3502               gas_assert (0);
3503               break;
3504             }
3505         }
3506       break;
3507
3508     case INSTR_LABEL_DEF:
3509       op = bi->ops;
3510       targ->opcode = XTENSA_UNDEFINED;
3511       targ->insn_type = ITYPE_LABEL;
3512       targ->is_specific_opcode = FALSE;
3513       /* Literal with no ops is a label?  */
3514       gas_assert (op == NULL);
3515       break;
3516
3517     default:
3518       gas_assert (0);
3519     }
3520
3521   return TRUE;
3522 }
3523
3524
3525 /* Return TRUE on success.  */
3526
3527 static bfd_boolean
3528 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3529 {
3530   for (; bi != NULL; bi = bi->next)
3531     {
3532       TInsn *next_insn = istack_push_space (istack);
3533
3534       if (!xg_build_to_insn (next_insn, insn, bi))
3535         return FALSE;
3536     }
3537   return TRUE;
3538 }
3539
3540
3541 /* Return TRUE on valid expansion.  */
3542
3543 static bfd_boolean
3544 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3545 {
3546   int stack_size = istack->ninsn;
3547   int steps_taken = 0;
3548   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3549   TransitionList *l;
3550
3551   gas_assert (insn->insn_type == ITYPE_INSN);
3552   gas_assert (insn->opcode < table->num_opcodes);
3553
3554   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3555     {
3556       TransitionRule *rule = l->rule;
3557
3558       if (xg_instruction_matches_rule (insn, rule))
3559         {
3560           if (lateral_steps == steps_taken)
3561             {
3562               int i;
3563
3564               /* This is it.  Expand the rule to the stack.  */
3565               if (!xg_build_to_stack (istack, insn, rule->to_instr))
3566                 return FALSE;
3567
3568               /* Check to see if it fits.  */
3569               for (i = stack_size; i < istack->ninsn; i++)
3570                 {
3571                   TInsn *insn = &istack->insn[i];
3572
3573                   if (insn->insn_type == ITYPE_INSN
3574                       && !tinsn_has_symbolic_operands (insn)
3575                       && !xg_immeds_fit (insn))
3576                     {
3577                       istack->ninsn = stack_size;
3578                       return FALSE;
3579                     }
3580                 }
3581               return TRUE;
3582             }
3583           steps_taken++;
3584         }
3585     }
3586   return FALSE;
3587 }
3588
3589 \f
3590 /* Relax the assembly instruction at least "min_steps".
3591    Return the number of steps taken.
3592
3593    For relaxation to correctly terminate, every relaxation chain must
3594    terminate in one of two ways:
3595
3596    1.  If the chain from one instruction to the next consists entirely of
3597        single instructions, then the chain *must* handle all possible
3598        immediates without failing.  It must not ever fail because an
3599        immediate is out of range.  The MOVI.N -> MOVI -> L32R relaxation
3600        chain is one example.  L32R loads 32 bits, and there cannot be an
3601        immediate larger than 32 bits, so it satisfies this condition.
3602        Single instruction relaxation chains are as defined by
3603        xg_is_single_relaxable_instruction.
3604
3605    2.  Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3606        BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3607
3608    Strictly speaking, in most cases you can violate condition 1 and be OK
3609    -- in particular when the last two instructions have the same single
3610    size.  But nevertheless, you should guarantee the above two conditions.
3611
3612    We could fix this so that single-instruction expansions correctly
3613    terminate when they can't handle the range, but the error messages are
3614    worse, and it actually turns out that in every case but one (18-bit wide
3615    branches), you need a multi-instruction expansion to get the full range
3616    anyway.  And because 18-bit branches are handled identically to 15-bit
3617    branches, there isn't any point in changing it.  */
3618
3619 static int
3620 xg_assembly_relax (IStack *istack,
3621                    TInsn *insn,
3622                    segT pc_seg,
3623                    fragS *pc_frag,      /* if pc_frag == 0, not pc-relative */
3624                    offsetT pc_offset,   /* offset in fragment */
3625                    int min_steps,       /* minimum conversion steps */
3626                    long stretch)        /* number of bytes stretched so far */
3627 {
3628   int steps_taken = 0;
3629
3630   /* Some of its immeds don't fit.  Try to build a relaxed version.
3631      This may go through a couple of stages of single instruction
3632      transformations before we get there.  */
3633
3634   TInsn single_target;
3635   TInsn current_insn;
3636   int lateral_steps = 0;
3637   int istack_size = istack->ninsn;
3638
3639   if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3640       && steps_taken >= min_steps)
3641     {
3642       istack_push (istack, insn);
3643       return steps_taken;
3644     }
3645   current_insn = *insn;
3646
3647   /* Walk through all of the single instruction expansions.  */
3648   while (xg_is_single_relaxable_insn (&current_insn, &single_target, FALSE))
3649     {
3650       steps_taken++;
3651       if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3652                                   stretch))
3653         {
3654           if (steps_taken >= min_steps)
3655             {
3656               istack_push (istack, &single_target);
3657               return steps_taken;
3658             }
3659         }
3660       current_insn = single_target;
3661     }
3662
3663   /* Now check for a multi-instruction expansion.  */
3664   while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3665     {
3666       if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3667                                   stretch))
3668         {
3669           if (steps_taken >= min_steps)
3670             {
3671               istack_push (istack, &current_insn);
3672               return steps_taken;
3673             }
3674         }
3675       steps_taken++;
3676       if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3677         {
3678           if (steps_taken >= min_steps)
3679             return steps_taken;
3680         }
3681       lateral_steps++;
3682       istack->ninsn = istack_size;
3683     }
3684
3685   /* It's not going to work -- use the original.  */
3686   istack_push (istack, insn);
3687   return steps_taken;
3688 }
3689
3690
3691 static void
3692 xg_finish_frag (char *last_insn,
3693                 enum xtensa_relax_statesE frag_state,
3694                 enum xtensa_relax_statesE slot0_state,
3695                 int max_growth,
3696                 bfd_boolean is_insn)
3697 {
3698   /* Finish off this fragment so that it has at LEAST the desired
3699      max_growth.  If it doesn't fit in this fragment, close this one
3700      and start a new one.  In either case, return a pointer to the
3701      beginning of the growth area.  */
3702
3703   fragS *old_frag;
3704
3705   frag_grow (max_growth);
3706   old_frag = frag_now;
3707
3708   frag_now->fr_opcode = last_insn;
3709   if (is_insn)
3710     frag_now->tc_frag_data.is_insn = TRUE;
3711
3712   frag_var (rs_machine_dependent, max_growth, max_growth,
3713             frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3714
3715   old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3716   xtensa_set_frag_assembly_state (frag_now);
3717
3718   /* Just to make sure that we did not split it up.  */
3719   gas_assert (old_frag->fr_next == frag_now);
3720 }
3721
3722
3723 /* Return TRUE if the target frag is one of the next non-empty frags.  */
3724
3725 static bfd_boolean
3726 is_next_frag_target (const fragS *fragP, const fragS *target)
3727 {
3728   if (fragP == NULL)
3729     return FALSE;
3730
3731   for (; fragP; fragP = fragP->fr_next)
3732     {
3733       if (fragP == target)
3734         return TRUE;
3735       if (fragP->fr_fix != 0)
3736         return FALSE;
3737       if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3738         return FALSE;
3739       if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3740           && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3741         return FALSE;
3742       if (fragP->fr_type == rs_space)
3743         return FALSE;
3744     }
3745   return FALSE;
3746 }
3747
3748
3749 static bfd_boolean
3750 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3751 {
3752   xtensa_isa isa = xtensa_default_isa;
3753   int i;
3754   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3755   int target_op = -1;
3756   symbolS *sym;
3757   fragS *target_frag;
3758
3759   if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
3760       && xtensa_opcode_is_jump (isa, insn->opcode) != 1)
3761     return FALSE;
3762
3763   for (i = 0; i < num_ops; i++)
3764     {
3765       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3766         {
3767           target_op = i;
3768           break;
3769         }
3770     }
3771   if (target_op == -1)
3772     return FALSE;
3773
3774   if (insn->ntok <= target_op)
3775     return FALSE;
3776
3777   if (insn->tok[target_op].X_op != O_symbol)
3778     return FALSE;
3779
3780   sym = insn->tok[target_op].X_add_symbol;
3781   if (sym == NULL)
3782     return FALSE;
3783
3784   if (insn->tok[target_op].X_add_number != 0)
3785     return FALSE;
3786
3787   target_frag = symbol_get_frag (sym);
3788   if (target_frag == NULL)
3789     return FALSE;
3790
3791   if (is_next_frag_target (fragP->fr_next, target_frag)
3792       && S_GET_VALUE (sym) == target_frag->fr_address)
3793     return TRUE;
3794
3795   return FALSE;
3796 }
3797
3798
3799 static void
3800 xg_add_branch_and_loop_targets (TInsn *insn)
3801 {
3802   xtensa_isa isa = xtensa_default_isa;
3803   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3804
3805   if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3806     {
3807       int i = 1;
3808       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3809           && insn->tok[i].X_op == O_symbol)
3810         symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3811       return;
3812     }
3813
3814   if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3815       || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3816     {
3817       int i;
3818
3819       for (i = 0; i < insn->ntok && i < num_ops; i++)
3820         {
3821           if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3822               && insn->tok[i].X_op == O_symbol)
3823             {
3824               symbolS *sym = insn->tok[i].X_add_symbol;
3825               symbol_get_tc (sym)->is_branch_target = TRUE;
3826               if (S_IS_DEFINED (sym))
3827                 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3828             }
3829         }
3830     }
3831 }
3832
3833
3834 /* Return FALSE if no error.  */
3835
3836 static bfd_boolean
3837 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3838 {
3839   int num_ops = 0;
3840   BuildOp *b_op;
3841
3842   switch (instr_spec->typ)
3843     {
3844     case INSTR_INSTR:
3845       new_insn->insn_type = ITYPE_INSN;
3846       new_insn->opcode = instr_spec->opcode;
3847       break;
3848     case INSTR_LITERAL_DEF:
3849       new_insn->insn_type = ITYPE_LITERAL;
3850       new_insn->opcode = XTENSA_UNDEFINED;
3851       break;
3852     case INSTR_LABEL_DEF:
3853       abort ();
3854     }
3855   new_insn->is_specific_opcode = FALSE;
3856   new_insn->debug_line = old_insn->debug_line;
3857   new_insn->loc_directive_seen = old_insn->loc_directive_seen;
3858
3859   for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3860     {
3861       expressionS *exp;
3862       const expressionS *src_exp;
3863
3864       num_ops++;
3865       switch (b_op->typ)
3866         {
3867         case OP_CONSTANT:
3868           /* The expression must be the constant.  */
3869           gas_assert (b_op->op_num < MAX_INSN_ARGS);
3870           exp = &new_insn->tok[b_op->op_num];
3871           set_expr_const (exp, b_op->op_data);
3872           break;
3873
3874         case OP_OPERAND:
3875           gas_assert (b_op->op_num < MAX_INSN_ARGS);
3876           gas_assert (b_op->op_data < (unsigned) old_insn->ntok);
3877           src_exp = &old_insn->tok[b_op->op_data];
3878           exp = &new_insn->tok[b_op->op_num];
3879           copy_expr (exp, src_exp);
3880           break;
3881
3882         case OP_LITERAL:
3883         case OP_LABEL:
3884           as_bad (_("can't handle generation of literal/labels yet"));
3885           gas_assert (0);
3886
3887         default:
3888           as_bad (_("can't handle undefined OP TYPE"));
3889           gas_assert (0);
3890         }
3891     }
3892
3893   new_insn->ntok = num_ops;
3894   return FALSE;
3895 }
3896
3897
3898 /* Return TRUE if it was simplified.  */
3899
3900 static bfd_boolean
3901 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
3902 {
3903   TransitionRule *rule;
3904   BuildInstr *insn_spec;
3905
3906   if (old_insn->is_specific_opcode || !density_supported)
3907     return FALSE;
3908
3909   rule = xg_instruction_match (old_insn);
3910   if (rule == NULL)
3911     return FALSE;
3912
3913   insn_spec = rule->to_instr;
3914   /* There should only be one.  */
3915   gas_assert (insn_spec != NULL);
3916   gas_assert (insn_spec->next == NULL);
3917   if (insn_spec->next != NULL)
3918     return FALSE;
3919
3920   xg_build_token_insn (insn_spec, old_insn, new_insn);
3921
3922   return TRUE;
3923 }
3924
3925
3926 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3927    l32i.n. (2) Check the number of operands.  (3) Place the instruction
3928    tokens into the stack or relax it and place multiple
3929    instructions/literals onto the stack.  Return FALSE if no error.  */
3930
3931 static bfd_boolean
3932 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
3933 {
3934   int noperands;
3935   TInsn new_insn;
3936   bfd_boolean do_expand;
3937
3938   tinsn_init (&new_insn);
3939
3940   /* Narrow it if we can.  xg_simplify_insn now does all the
3941      appropriate checking (e.g., for the density option).  */
3942   if (xg_simplify_insn (orig_insn, &new_insn))
3943     orig_insn = &new_insn;
3944
3945   noperands = xtensa_opcode_num_operands (xtensa_default_isa,
3946                                           orig_insn->opcode);
3947   if (orig_insn->ntok < noperands)
3948     {
3949       as_bad (_("found %d operands for '%s':  Expected %d"),
3950               orig_insn->ntok,
3951               xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3952               noperands);
3953       return TRUE;
3954     }
3955   if (orig_insn->ntok > noperands)
3956     as_warn (_("found too many (%d) operands for '%s':  Expected %d"),
3957              orig_insn->ntok,
3958              xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3959              noperands);
3960
3961   /* If there are not enough operands, we will assert above.  If there
3962      are too many, just cut out the extras here.  */
3963   orig_insn->ntok = noperands;
3964
3965   if (tinsn_has_invalid_symbolic_operands (orig_insn))
3966     return TRUE;
3967
3968   /* Special case for extui opcode which has constraints not handled
3969      by the ordinary operand encoding checks.  The number of operands
3970      and related syntax issues have already been checked.  */
3971   if (orig_insn->opcode == xtensa_extui_opcode)
3972     {
3973       int shiftimm = orig_insn->tok[2].X_add_number;
3974       int maskimm = orig_insn->tok[3].X_add_number;
3975       if (shiftimm + maskimm > 32)
3976         {
3977           as_bad (_("immediate operands sum to greater than 32"));
3978           return TRUE;
3979         }
3980     }
3981
3982   /* If the instruction will definitely need to be relaxed, it is better
3983      to expand it now for better scheduling.  Decide whether to expand
3984      now....  */
3985   do_expand = (!orig_insn->is_specific_opcode && use_transform ());
3986
3987   /* Calls should be expanded to longcalls only in the backend relaxation
3988      so that the assembly scheduler will keep the L32R/CALLX instructions
3989      adjacent.  */
3990   if (is_direct_call_opcode (orig_insn->opcode))
3991     do_expand = FALSE;
3992
3993   if (tinsn_has_symbolic_operands (orig_insn))
3994     {
3995       /* The values of symbolic operands are not known yet, so only expand
3996          now if an operand is "complex" (e.g., difference of symbols) and
3997          will have to be stored as a literal regardless of the value.  */
3998       if (!tinsn_has_complex_operands (orig_insn))
3999         do_expand = FALSE;
4000     }
4001   else if (xg_immeds_fit (orig_insn))
4002     do_expand = FALSE;
4003
4004   if (do_expand)
4005     xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4006   else
4007     istack_push (istack, orig_insn);
4008
4009   return FALSE;
4010 }
4011
4012
4013 /* Return TRUE if the section flags are marked linkonce
4014    or the name is .gnu.linkonce.*.  */
4015
4016 static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
4017
4018 static bfd_boolean
4019 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4020 {
4021   flagword flags, link_once_flags;
4022
4023   flags = bfd_get_section_flags (abfd, sec);
4024   link_once_flags = (flags & SEC_LINK_ONCE);
4025
4026   /* Flags might not be set yet.  */
4027   if (!link_once_flags
4028       && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0)
4029     link_once_flags = SEC_LINK_ONCE;
4030
4031   return (link_once_flags != 0);
4032 }
4033
4034
4035 static void
4036 xtensa_add_literal_sym (symbolS *sym)
4037 {
4038   sym_list *l;
4039
4040   l = (sym_list *) xmalloc (sizeof (sym_list));
4041   l->sym = sym;
4042   l->next = literal_syms;
4043   literal_syms = l;
4044 }
4045
4046
4047 static symbolS *
4048 xtensa_create_literal_symbol (segT sec, fragS *frag)
4049 {
4050   static int lit_num = 0;
4051   static char name[256];
4052   symbolS *symbolP;
4053
4054   sprintf (name, ".L_lit_sym%d", lit_num);
4055
4056   /* Create a local symbol.  If it is in a linkonce section, we have to
4057      be careful to make sure that if it is used in a relocation that the
4058      symbol will be in the output file.  */
4059   if (get_is_linkonce_section (stdoutput, sec))
4060     {
4061       symbolP = symbol_new (name, sec, 0, frag);
4062       S_CLEAR_EXTERNAL (symbolP);
4063       /* symbolP->local = 1; */
4064     }
4065   else
4066     symbolP = symbol_new (name, sec, 0, frag);
4067
4068   xtensa_add_literal_sym (symbolP);
4069
4070   lit_num++;
4071   return symbolP;
4072 }
4073
4074
4075 /* Currently all literals that are generated here are 32-bit L32R targets.  */
4076
4077 static symbolS *
4078 xg_assemble_literal (/* const */ TInsn *insn)
4079 {
4080   emit_state state;
4081   symbolS *lit_sym = NULL;
4082   bfd_reloc_code_real_type reloc;
4083   bfd_boolean pcrel = FALSE;
4084   char *p;
4085
4086   /* size = 4 for L32R.  It could easily be larger when we move to
4087      larger constants.  Add a parameter later.  */
4088   offsetT litsize = 4;
4089   offsetT litalign = 2;         /* 2^2 = 4 */
4090   expressionS saved_loc;
4091   expressionS * emit_val;
4092
4093   set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4094
4095   gas_assert (insn->insn_type == ITYPE_LITERAL);
4096   gas_assert (insn->ntok == 1); /* must be only one token here */
4097
4098   xtensa_switch_to_literal_fragment (&state);
4099
4100   emit_val = &insn->tok[0];
4101   if (emit_val->X_op == O_big)
4102     {
4103       int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4104       if (size > litsize)
4105         {
4106           /* This happens when someone writes a "movi a2, big_number".  */
4107           as_bad_where (frag_now->fr_file, frag_now->fr_line,
4108                         _("invalid immediate"));
4109           xtensa_restore_emit_state (&state);
4110           return NULL;
4111         }
4112     }
4113
4114   /* Force a 4-byte align here.  Note that this opens a new frag, so all
4115      literals done with this function have a frag to themselves.  That's
4116      important for the way text section literals work.  */
4117   frag_align (litalign, 0, 0);
4118   record_alignment (now_seg, litalign);
4119
4120   switch (emit_val->X_op)
4121     {
4122     case O_pcrel:
4123       pcrel = TRUE;
4124       /* fall through */
4125     case O_pltrel:
4126     case O_tlsfunc:
4127     case O_tlsarg:
4128     case O_tpoff:
4129     case O_dtpoff:
4130       p = frag_more (litsize);
4131       xtensa_set_frag_assembly_state (frag_now);
4132       reloc = map_operator_to_reloc (emit_val->X_op, TRUE);
4133       if (emit_val->X_add_symbol)
4134         emit_val->X_op = O_symbol;
4135       else
4136         emit_val->X_op = O_constant;
4137       fix_new_exp (frag_now, p - frag_now->fr_literal,
4138                    litsize, emit_val, pcrel, reloc);
4139       break;
4140
4141     default:
4142       emit_expr (emit_val, litsize);
4143       break;
4144     }
4145
4146   gas_assert (frag_now->tc_frag_data.literal_frag == NULL);
4147   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4148   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4149   lit_sym = frag_now->fr_symbol;
4150
4151   /* Go back.  */
4152   xtensa_restore_emit_state (&state);
4153   return lit_sym;
4154 }
4155
4156
4157 static void
4158 xg_assemble_literal_space (/* const */ int size, int slot)
4159 {
4160   emit_state state;
4161   /* We might have to do something about this alignment.  It only
4162      takes effect if something is placed here.  */
4163   offsetT litalign = 2;         /* 2^2 = 4 */
4164   fragS *lit_saved_frag;
4165
4166   gas_assert (size % 4 == 0);
4167
4168   xtensa_switch_to_literal_fragment (&state);
4169
4170   /* Force a 4-byte align here.  */
4171   frag_align (litalign, 0, 0);
4172   record_alignment (now_seg, litalign);
4173
4174   frag_grow (size);
4175
4176   lit_saved_frag = frag_now;
4177   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4178   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4179   xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
4180
4181   /* Go back.  */
4182   xtensa_restore_emit_state (&state);
4183   frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4184 }
4185
4186
4187 /* Put in a fixup record based on the opcode.
4188    Return TRUE on success.  */
4189
4190 static bfd_boolean
4191 xg_add_opcode_fix (TInsn *tinsn,
4192                    int opnum,
4193                    xtensa_format fmt,
4194                    int slot,
4195                    expressionS *expr,
4196                    fragS *fragP,
4197                    offsetT offset)
4198 {
4199   xtensa_opcode opcode = tinsn->opcode;
4200   bfd_reloc_code_real_type reloc;
4201   reloc_howto_type *howto;
4202   int fmt_length;
4203   fixS *the_fix;
4204
4205   reloc = BFD_RELOC_NONE;
4206
4207   /* First try the special cases for "alternate" relocs.  */
4208   if (opcode == xtensa_l32r_opcode)
4209     {
4210       if (fragP->tc_frag_data.use_absolute_literals)
4211         reloc = encode_alt_reloc (slot);
4212     }
4213   else if (opcode == xtensa_const16_opcode)
4214     {
4215       if (expr->X_op == O_lo16)
4216         {
4217           reloc = encode_reloc (slot);
4218           expr->X_op = O_symbol;
4219         }
4220       else if (expr->X_op == O_hi16)
4221         {
4222           reloc = encode_alt_reloc (slot);
4223           expr->X_op = O_symbol;
4224         }
4225     }
4226
4227   if (opnum != get_relaxable_immed (opcode))
4228     {
4229       as_bad (_("invalid relocation for operand %i of '%s'"),
4230               opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4231       return FALSE;
4232     }
4233
4234   /* Handle erroneous "@h" and "@l" expressions here before they propagate
4235      into the symbol table where the generic portions of the assembler
4236      won't know what to do with them.  */
4237   if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4238     {
4239       as_bad (_("invalid expression for operand %i of '%s'"),
4240               opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4241       return FALSE;
4242     }
4243
4244   /* Next try the generic relocs.  */
4245   if (reloc == BFD_RELOC_NONE)
4246     reloc = encode_reloc (slot);
4247   if (reloc == BFD_RELOC_NONE)
4248     {
4249       as_bad (_("invalid relocation in instruction slot %i"), slot);
4250       return FALSE;
4251     }
4252
4253   howto = bfd_reloc_type_lookup (stdoutput, reloc);
4254   if (!howto)
4255     {
4256       as_bad (_("undefined symbol for opcode \"%s\""),
4257               xtensa_opcode_name (xtensa_default_isa, opcode));
4258       return FALSE;
4259     }
4260
4261   fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4262   the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
4263                          howto->pc_relative, reloc);
4264   the_fix->fx_no_overflow = 1;
4265   the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4266   the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4267   the_fix->tc_fix_data.slot = slot;
4268
4269   return TRUE;
4270 }
4271
4272
4273 static bfd_boolean
4274 xg_emit_insn_to_buf (TInsn *tinsn,
4275                      char *buf,
4276                      fragS *fragP,
4277                      offsetT offset,
4278                      bfd_boolean build_fix)
4279 {
4280   static xtensa_insnbuf insnbuf = NULL;
4281   bfd_boolean has_symbolic_immed = FALSE;
4282   bfd_boolean ok = TRUE;
4283
4284   if (!insnbuf)
4285     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4286
4287   has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4288   if (has_symbolic_immed && build_fix)
4289     {
4290       /* Add a fixup.  */
4291       xtensa_format fmt = xg_get_single_format (tinsn->opcode);
4292       int slot = xg_get_single_slot (tinsn->opcode);
4293       int opnum = get_relaxable_immed (tinsn->opcode);
4294       expressionS *exp = &tinsn->tok[opnum];
4295
4296       if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
4297         ok = FALSE;
4298     }
4299   fragP->tc_frag_data.is_insn = TRUE;
4300   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4301                            (unsigned char *) buf, 0);
4302   return ok;
4303 }
4304
4305
4306 static void
4307 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4308 {
4309   symbolS *sym = get_special_literal_symbol ();
4310   int i;
4311   if (lit_sym == 0)
4312     return;
4313   gas_assert (insn->insn_type == ITYPE_INSN);
4314   for (i = 0; i < insn->ntok; i++)
4315     if (insn->tok[i].X_add_symbol == sym)
4316       insn->tok[i].X_add_symbol = lit_sym;
4317
4318 }
4319
4320
4321 static void
4322 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4323 {
4324   symbolS *sym = get_special_label_symbol ();
4325   int i;
4326   for (i = 0; i < insn->ntok; i++)
4327     if (insn->tok[i].X_add_symbol == sym)
4328       insn->tok[i].X_add_symbol = label_sym;
4329
4330 }
4331
4332
4333 /* Return TRUE if the instruction can write to the specified
4334    integer register.  */
4335
4336 static bfd_boolean
4337 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4338 {
4339   int i;
4340   int num_ops;
4341   xtensa_isa isa = xtensa_default_isa;
4342
4343   num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4344
4345   for (i = 0; i < num_ops; i++)
4346     {
4347       char inout;
4348       inout = xtensa_operand_inout (isa, insn->opcode, i);
4349       if ((inout == 'o' || inout == 'm')
4350           && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4351         {
4352           xtensa_regfile opnd_rf =
4353             xtensa_operand_regfile (isa, insn->opcode, i);
4354           if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4355             {
4356               if ((insn->tok[i].X_op == O_register)
4357                   && (insn->tok[i].X_add_number == regnum))
4358                 return TRUE;
4359             }
4360         }
4361     }
4362   return FALSE;
4363 }
4364
4365
4366 static bfd_boolean
4367 is_bad_loopend_opcode (const TInsn *tinsn)
4368 {
4369   xtensa_opcode opcode = tinsn->opcode;
4370
4371   if (opcode == XTENSA_UNDEFINED)
4372     return FALSE;
4373
4374   if (opcode == xtensa_call0_opcode
4375       || opcode == xtensa_callx0_opcode
4376       || opcode == xtensa_call4_opcode
4377       || opcode == xtensa_callx4_opcode
4378       || opcode == xtensa_call8_opcode
4379       || opcode == xtensa_callx8_opcode
4380       || opcode == xtensa_call12_opcode
4381       || opcode == xtensa_callx12_opcode
4382       || opcode == xtensa_isync_opcode
4383       || opcode == xtensa_ret_opcode
4384       || opcode == xtensa_ret_n_opcode
4385       || opcode == xtensa_retw_opcode
4386       || opcode == xtensa_retw_n_opcode
4387       || opcode == xtensa_waiti_opcode
4388       || opcode == xtensa_rsr_lcount_opcode)
4389     return TRUE;
4390
4391   return FALSE;
4392 }
4393
4394
4395 /* Labels that begin with ".Ln" or ".LM"  are unaligned.
4396    This allows the debugger to add unaligned labels.
4397    Also, the assembler generates stabs labels that need
4398    not be aligned:  FAKE_LABEL_NAME . {"F", "L", "endfunc"}.  */
4399
4400 static bfd_boolean
4401 is_unaligned_label (symbolS *sym)
4402 {
4403   const char *name = S_GET_NAME (sym);
4404   static size_t fake_size = 0;
4405
4406   if (name
4407       && name[0] == '.'
4408       && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4409     return TRUE;
4410
4411   /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4412   if (fake_size == 0)
4413     fake_size = strlen (FAKE_LABEL_NAME);
4414
4415   if (name
4416       && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4417       && (name[fake_size] == 'F'
4418           || name[fake_size] == 'L'
4419           || (name[fake_size] == 'e'
4420               && strncmp ("endfunc", name+fake_size, 7) == 0)))
4421     return TRUE;
4422
4423   return FALSE;
4424 }
4425
4426
4427 static fragS *
4428 next_non_empty_frag (const fragS *fragP)
4429 {
4430   fragS *next_fragP = fragP->fr_next;
4431
4432   /* Sometimes an empty will end up here due storage allocation issues.
4433      So we have to skip until we find something legit.  */
4434   while (next_fragP && next_fragP->fr_fix == 0)
4435     next_fragP = next_fragP->fr_next;
4436
4437   if (next_fragP == NULL || next_fragP->fr_fix == 0)
4438     return NULL;
4439
4440   return next_fragP;
4441 }
4442
4443
4444 static bfd_boolean
4445 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4446 {
4447   xtensa_opcode out_opcode;
4448   const fragS *next_fragP = next_non_empty_frag (fragP);
4449
4450   if (next_fragP == NULL)
4451     return FALSE;
4452
4453   out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4454   if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4455     {
4456       *opcode = out_opcode;
4457       return TRUE;
4458     }
4459   return FALSE;
4460 }
4461
4462
4463 static int
4464 frag_format_size (const fragS *fragP)
4465 {
4466   static xtensa_insnbuf insnbuf = NULL;
4467   xtensa_isa isa = xtensa_default_isa;
4468   xtensa_format fmt;
4469   int fmt_size;
4470
4471   if (!insnbuf)
4472     insnbuf = xtensa_insnbuf_alloc (isa);
4473
4474   if (fragP == NULL)
4475     return XTENSA_UNDEFINED;
4476
4477   xtensa_insnbuf_from_chars (isa, insnbuf,
4478                              (unsigned char *) fragP->fr_literal, 0);
4479
4480   fmt = xtensa_format_decode (isa, insnbuf);
4481   if (fmt == XTENSA_UNDEFINED)
4482     return XTENSA_UNDEFINED;
4483   fmt_size = xtensa_format_length (isa, fmt);
4484
4485   /* If the next format won't be changing due to relaxation, just
4486      return the length of the first format.  */
4487   if (fragP->fr_opcode != fragP->fr_literal)
4488     return fmt_size;
4489
4490   /* If during relaxation we have to pull an instruction out of a
4491      multi-slot instruction, we will return the more conservative
4492      number.  This works because alignment on bigger instructions
4493      is more restrictive than alignment on smaller instructions.
4494      This is more conservative than we would like, but it happens
4495      infrequently.  */
4496
4497   if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4498     return fmt_size;
4499
4500   /* If we aren't doing one of our own relaxations or it isn't
4501      slot-based, then the insn size won't change.  */
4502   if (fragP->fr_type != rs_machine_dependent)
4503     return fmt_size;
4504   if (fragP->fr_subtype != RELAX_SLOTS)
4505     return fmt_size;
4506
4507   /* If an instruction is about to grow, return the longer size.  */
4508   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4509       || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
4510       || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
4511     {
4512       /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4513          instruction in the relaxed version is of length 3.  (The case
4514          where we have to pull the instruction out of a FLIX bundle
4515          is handled conservatively above.)  However, frags with opcodes
4516          that are expanding to wide branches end up having formats that
4517          are not determinable by the RELAX_IMMED_STEPX enumeration, and
4518          we can't tell directly what format the relaxer picked.  This
4519          is a wart in the design of the relaxer that should someday be
4520          fixed, but would require major changes, or at least should
4521          be accompanied by major changes to make use of that data.
4522
4523          In any event, we can tell that we are expanding from a single-slot
4524          three-byte format to a wider one with the logic below.  */
4525
4526       if (fmt_size <= 3 && fragP->tc_frag_data.text_expansion[0] != 3)
4527         return 3 + fragP->tc_frag_data.text_expansion[0];
4528       else
4529         return 3;
4530     }
4531
4532   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4533     return 2 + fragP->tc_frag_data.text_expansion[0];
4534
4535   return fmt_size;
4536 }
4537
4538
4539 static int
4540 next_frag_format_size (const fragS *fragP)
4541 {
4542   const fragS *next_fragP = next_non_empty_frag (fragP);
4543   return frag_format_size (next_fragP);
4544 }
4545
4546
4547 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4548    required two-byte instructions to be treated as three-byte instructions
4549    for loop instruction alignment.  This restriction was removed beginning
4550    with Xtensa LX.  Now the only requirement on loop instruction alignment
4551    is that the first instruction of the loop must appear at an address that
4552    does not cross a fetch boundary.  */
4553
4554 static int
4555 get_loop_align_size (int insn_size)
4556 {
4557   if (insn_size == XTENSA_UNDEFINED)
4558     return xtensa_fetch_width;
4559
4560   if (enforce_three_byte_loop_align && insn_size == 2)
4561     return 3;
4562
4563   return insn_size;
4564 }
4565
4566
4567 /* If the next legit fragment is an end-of-loop marker,
4568    switch its state so it will instantiate a NOP.  */
4569
4570 static void
4571 update_next_frag_state (fragS *fragP)
4572 {
4573   fragS *next_fragP = fragP->fr_next;
4574   fragS *new_target = NULL;
4575
4576   if (align_targets)
4577     {
4578       /* We are guaranteed there will be one of these...   */
4579       while (!(next_fragP->fr_type == rs_machine_dependent
4580                && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4581                    || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4582         next_fragP = next_fragP->fr_next;
4583
4584       gas_assert (next_fragP->fr_type == rs_machine_dependent
4585               && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4586                   || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4587
4588       /* ...and one of these.  */
4589       new_target = next_fragP->fr_next;
4590       while (!(new_target->fr_type == rs_machine_dependent
4591                && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4592                    || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4593         new_target = new_target->fr_next;
4594
4595       gas_assert (new_target->fr_type == rs_machine_dependent
4596               && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4597                   || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4598     }
4599
4600   while (next_fragP && next_fragP->fr_fix == 0)
4601     {
4602       if (next_fragP->fr_type == rs_machine_dependent
4603           && next_fragP->fr_subtype == RELAX_LOOP_END)
4604         {
4605           next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4606           return;
4607         }
4608
4609       next_fragP = next_fragP->fr_next;
4610     }
4611 }
4612
4613
4614 static bfd_boolean
4615 next_frag_is_branch_target (const fragS *fragP)
4616 {
4617   /* Sometimes an empty will end up here due to storage allocation issues,
4618      so we have to skip until we find something legit.  */
4619   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4620     {
4621       if (fragP->tc_frag_data.is_branch_target)
4622         return TRUE;
4623       if (fragP->fr_fix != 0)
4624         break;
4625     }
4626   return FALSE;
4627 }
4628
4629
4630 static bfd_boolean
4631 next_frag_is_loop_target (const fragS *fragP)
4632 {
4633   /* Sometimes an empty will end up here due storage allocation issues.
4634      So we have to skip until we find something legit. */
4635   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4636     {
4637       if (fragP->tc_frag_data.is_loop_target)
4638         return TRUE;
4639       if (fragP->fr_fix != 0)
4640         break;
4641     }
4642   return FALSE;
4643 }
4644
4645
4646 static addressT
4647 next_frag_pre_opcode_bytes (const fragS *fragp)
4648 {
4649   const fragS *next_fragp = fragp->fr_next;
4650   xtensa_opcode next_opcode;
4651
4652   if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4653     return 0;
4654
4655   /* Sometimes an empty will end up here due to storage allocation issues,
4656      so we have to skip until we find something legit.  */
4657   while (next_fragp->fr_fix == 0)
4658     next_fragp = next_fragp->fr_next;
4659
4660   if (next_fragp->fr_type != rs_machine_dependent)
4661     return 0;
4662
4663   /* There is some implicit knowledge encoded in here.
4664      The LOOP instructions that are NOT RELAX_IMMED have
4665      been relaxed.  Note that we can assume that the LOOP
4666      instruction is in slot 0 because loops aren't bundleable.  */
4667   if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4668       return get_expanded_loop_offset (next_opcode);
4669
4670   return 0;
4671 }
4672
4673
4674 /* Mark a location where we can later insert literal frags.  Update
4675    the section's literal_pool_loc, so subsequent literals can be
4676    placed nearest to their use.  */
4677
4678 static void
4679 xtensa_mark_literal_pool_location (void)
4680 {
4681   /* Any labels pointing to the current location need
4682      to be adjusted to after the literal pool.  */
4683   emit_state s;
4684   fragS *pool_location;
4685
4686   if (use_literal_section)
4687     return;
4688
4689   /* We stash info in these frags so we can later move the literal's
4690      fixes into this frchain's fix list.  */
4691   pool_location = frag_now;
4692   frag_now->tc_frag_data.lit_frchain = frchain_now;
4693   frag_now->tc_frag_data.literal_frag = frag_now;
4694   frag_variant (rs_machine_dependent, 0, 0,
4695                 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4696   xtensa_set_frag_assembly_state (frag_now);
4697   frag_now->tc_frag_data.lit_seg = now_seg;
4698   frag_variant (rs_machine_dependent, 0, 0,
4699                 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4700   xtensa_set_frag_assembly_state (frag_now);
4701
4702   /* Now put a frag into the literal pool that points to this location.  */
4703   set_literal_pool_location (now_seg, pool_location);
4704   xtensa_switch_to_non_abs_literal_fragment (&s);
4705   frag_align (2, 0, 0);
4706   record_alignment (now_seg, 2);
4707
4708   /* Close whatever frag is there.  */
4709   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4710   xtensa_set_frag_assembly_state (frag_now);
4711   frag_now->tc_frag_data.literal_frag = pool_location;
4712   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4713   xtensa_restore_emit_state (&s);
4714   xtensa_set_frag_assembly_state (frag_now);
4715 }
4716
4717
4718 /* Build a nop of the correct size into tinsn.  */
4719
4720 static void
4721 build_nop (TInsn *tinsn, int size)
4722 {
4723   tinsn_init (tinsn);
4724   switch (size)
4725     {
4726     case 2:
4727       tinsn->opcode = xtensa_nop_n_opcode;
4728       tinsn->ntok = 0;
4729       if (tinsn->opcode == XTENSA_UNDEFINED)
4730         as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4731       break;
4732
4733     case 3:
4734       if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4735         {
4736           tinsn->opcode = xtensa_or_opcode;
4737           set_expr_const (&tinsn->tok[0], 1);
4738           set_expr_const (&tinsn->tok[1], 1);
4739           set_expr_const (&tinsn->tok[2], 1);
4740           tinsn->ntok = 3;
4741         }
4742       else
4743         tinsn->opcode = xtensa_nop_opcode;
4744
4745       gas_assert (tinsn->opcode != XTENSA_UNDEFINED);
4746     }
4747 }
4748
4749
4750 /* Assemble a NOP of the requested size in the buffer.  User must have
4751    allocated "buf" with at least "size" bytes.  */
4752
4753 static void
4754 assemble_nop (int size, char *buf)
4755 {
4756   static xtensa_insnbuf insnbuf = NULL;
4757   TInsn tinsn;
4758
4759   build_nop (&tinsn, size);
4760
4761   if (!insnbuf)
4762     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4763
4764   tinsn_to_insnbuf (&tinsn, insnbuf);
4765   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4766                            (unsigned char *) buf, 0);
4767 }
4768
4769
4770 /* Return the number of bytes for the offset of the expanded loop
4771    instruction.  This should be incorporated into the relaxation
4772    specification but is hard-coded here.  This is used to auto-align
4773    the loop instruction.  It is invalid to call this function if the
4774    configuration does not have loops or if the opcode is not a loop
4775    opcode.  */
4776
4777 static addressT
4778 get_expanded_loop_offset (xtensa_opcode opcode)
4779 {
4780   /* This is the OFFSET of the loop instruction in the expanded loop.
4781      This MUST correspond directly to the specification of the loop
4782      expansion.  It will be validated on fragment conversion.  */
4783   gas_assert (opcode != XTENSA_UNDEFINED);
4784   if (opcode == xtensa_loop_opcode)
4785     return 0;
4786   if (opcode == xtensa_loopnez_opcode)
4787     return 3;
4788   if (opcode == xtensa_loopgtz_opcode)
4789     return 6;
4790   as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4791   return 0;
4792 }
4793
4794
4795 static fragS *
4796 get_literal_pool_location (segT seg)
4797 {
4798   return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4799 }
4800
4801
4802 static void
4803 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4804 {
4805   seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4806 }
4807
4808
4809 /* Set frag assembly state should be called when a new frag is
4810    opened and after a frag has been closed.  */
4811
4812 static void
4813 xtensa_set_frag_assembly_state (fragS *fragP)
4814 {
4815   if (!density_supported)
4816     fragP->tc_frag_data.is_no_density = TRUE;
4817
4818   /* This function is called from subsegs_finish, which is called
4819      after xtensa_end, so we can't use "use_transform" or
4820      "use_schedule" here.  */
4821   if (!directive_state[directive_transform])
4822     fragP->tc_frag_data.is_no_transform = TRUE;
4823   if (directive_state[directive_longcalls])
4824     fragP->tc_frag_data.use_longcalls = TRUE;
4825   fragP->tc_frag_data.use_absolute_literals =
4826     directive_state[directive_absolute_literals];
4827   fragP->tc_frag_data.is_assembly_state_set = TRUE;
4828 }
4829
4830
4831 static bfd_boolean
4832 relaxable_section (asection *sec)
4833 {
4834   return ((sec->flags & SEC_DEBUGGING) == 0
4835           && strcmp (sec->name, ".eh_frame") != 0);
4836 }
4837
4838
4839 static void
4840 xtensa_mark_frags_for_org (void)
4841 {
4842   segT *seclist;
4843
4844   /* Walk over each fragment of all of the current segments.  If we find
4845      a .org frag in any of the segments, mark all frags prior to it as
4846      "no transform", which will prevent linker optimizations from messing
4847      up the .org distance.  This should be done after
4848      xtensa_find_unmarked_state_frags, because we don't want to worry here
4849      about that function trashing the data we save here.  */
4850
4851   for (seclist = &stdoutput->sections;
4852        seclist && *seclist;
4853        seclist = &(*seclist)->next)
4854     {
4855       segT sec = *seclist;
4856       segment_info_type *seginfo;
4857       fragS *fragP;
4858       flagword flags;
4859       flags = bfd_get_section_flags (stdoutput, sec);
4860       if (flags & SEC_DEBUGGING)
4861         continue;
4862       if (!(flags & SEC_ALLOC))
4863         continue;
4864
4865       seginfo = seg_info (sec);
4866       if (seginfo && seginfo->frchainP)
4867         {
4868           fragS *last_fragP = seginfo->frchainP->frch_root;
4869           for (fragP = seginfo->frchainP->frch_root; fragP;
4870                fragP = fragP->fr_next)
4871             {
4872               /* cvt_frag_to_fill has changed the fr_type of org frags to
4873                  rs_fill, so use the value as cached in rs_subtype here.  */
4874               if (fragP->fr_subtype == RELAX_ORG)
4875                 {
4876                   while (last_fragP != fragP->fr_next)
4877                     {
4878                       last_fragP->tc_frag_data.is_no_transform = TRUE;
4879                       last_fragP = last_fragP->fr_next;
4880                     }
4881                 }
4882             }
4883         }
4884     }
4885 }
4886
4887
4888 static void
4889 xtensa_find_unmarked_state_frags (void)
4890 {
4891   segT *seclist;
4892
4893   /* Walk over each fragment of all of the current segments.  For each
4894      unmarked fragment, mark it with the same info as the previous
4895      fragment.  */
4896   for (seclist = &stdoutput->sections;
4897        seclist && *seclist;
4898        seclist = &(*seclist)->next)
4899     {
4900       segT sec = *seclist;
4901       segment_info_type *seginfo;
4902       fragS *fragP;
4903       flagword flags;
4904       flags = bfd_get_section_flags (stdoutput, sec);
4905       if (flags & SEC_DEBUGGING)
4906         continue;
4907       if (!(flags & SEC_ALLOC))
4908         continue;
4909
4910       seginfo = seg_info (sec);
4911       if (seginfo && seginfo->frchainP)
4912         {
4913           fragS *last_fragP = 0;
4914           for (fragP = seginfo->frchainP->frch_root; fragP;
4915                fragP = fragP->fr_next)
4916             {
4917               if (fragP->fr_fix != 0
4918                   && !fragP->tc_frag_data.is_assembly_state_set)
4919                 {
4920                   if (last_fragP == 0)
4921                     {
4922                       as_warn_where (fragP->fr_file, fragP->fr_line,
4923                                      _("assembly state not set for first frag in section %s"),
4924                                      sec->name);
4925                     }
4926                   else
4927                     {
4928                       fragP->tc_frag_data.is_assembly_state_set = TRUE;
4929                       fragP->tc_frag_data.is_no_density =
4930                         last_fragP->tc_frag_data.is_no_density;
4931                       fragP->tc_frag_data.is_no_transform =
4932                         last_fragP->tc_frag_data.is_no_transform;
4933                       fragP->tc_frag_data.use_longcalls =
4934                         last_fragP->tc_frag_data.use_longcalls;
4935                       fragP->tc_frag_data.use_absolute_literals =
4936                         last_fragP->tc_frag_data.use_absolute_literals;
4937                     }
4938                 }
4939               if (fragP->tc_frag_data.is_assembly_state_set)
4940                 last_fragP = fragP;
4941             }
4942         }
4943     }
4944 }
4945
4946
4947 static void
4948 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
4949                                       asection *sec,
4950                                       void *unused ATTRIBUTE_UNUSED)
4951 {
4952   flagword flags = bfd_get_section_flags (abfd, sec);
4953   segment_info_type *seginfo = seg_info (sec);
4954   fragS *frag = seginfo->frchainP->frch_root;
4955
4956   if (flags & SEC_CODE)
4957     {
4958       xtensa_isa isa = xtensa_default_isa;
4959       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4960       while (frag != NULL)
4961         {
4962           if (frag->tc_frag_data.is_branch_target)
4963             {
4964               int op_size;
4965               addressT branch_align, frag_addr;
4966               xtensa_format fmt;
4967
4968               xtensa_insnbuf_from_chars
4969                 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
4970               fmt = xtensa_format_decode (isa, insnbuf);
4971               op_size = xtensa_format_length (isa, fmt);
4972               branch_align = 1 << branch_align_power (sec);
4973               frag_addr = frag->fr_address % branch_align;
4974               if (frag_addr + op_size > branch_align)
4975                 as_warn_where (frag->fr_file, frag->fr_line,
4976                                _("unaligned branch target: %d bytes at 0x%lx"),
4977                                op_size, (long) frag->fr_address);
4978             }
4979           frag = frag->fr_next;
4980         }
4981       xtensa_insnbuf_free (isa, insnbuf);
4982     }
4983 }
4984
4985
4986 static void
4987 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
4988                              asection *sec,
4989                              void *unused ATTRIBUTE_UNUSED)
4990 {
4991   flagword flags = bfd_get_section_flags (abfd, sec);
4992   segment_info_type *seginfo = seg_info (sec);
4993   fragS *frag = seginfo->frchainP->frch_root;
4994   xtensa_isa isa = xtensa_default_isa;
4995
4996   if (flags & SEC_CODE)
4997     {
4998       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4999       while (frag != NULL)
5000         {
5001           if (frag->tc_frag_data.is_first_loop_insn)
5002             {
5003               int op_size;
5004               addressT frag_addr;
5005               xtensa_format fmt;
5006
5007               xtensa_insnbuf_from_chars
5008                 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5009               fmt = xtensa_format_decode (isa, insnbuf);
5010               op_size = xtensa_format_length (isa, fmt);
5011               frag_addr = frag->fr_address % xtensa_fetch_width;
5012
5013               if (frag_addr + op_size > xtensa_fetch_width)
5014                 as_warn_where (frag->fr_file, frag->fr_line,
5015                                _("unaligned loop: %d bytes at 0x%lx"),
5016                                op_size, (long) frag->fr_address);
5017             }
5018           frag = frag->fr_next;
5019         }
5020       xtensa_insnbuf_free (isa, insnbuf);
5021     }
5022 }
5023
5024
5025 static int
5026 xg_apply_fix_value (fixS *fixP, valueT val)
5027 {
5028   xtensa_isa isa = xtensa_default_isa;
5029   static xtensa_insnbuf insnbuf = NULL;
5030   static xtensa_insnbuf slotbuf = NULL;
5031   xtensa_format fmt;
5032   int slot;
5033   bfd_boolean alt_reloc;
5034   xtensa_opcode opcode;
5035   char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5036
5037   if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc)
5038       || alt_reloc)
5039     as_fatal (_("unexpected fix"));
5040
5041   if (!insnbuf)
5042     {
5043       insnbuf = xtensa_insnbuf_alloc (isa);
5044       slotbuf = xtensa_insnbuf_alloc (isa);
5045     }
5046
5047   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5048   fmt = xtensa_format_decode (isa, insnbuf);
5049   if (fmt == XTENSA_UNDEFINED)
5050     as_fatal (_("undecodable fix"));
5051   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5052   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5053   if (opcode == XTENSA_UNDEFINED)
5054     as_fatal (_("undecodable fix"));
5055
5056   /* CONST16 immediates are not PC-relative, despite the fact that we
5057      reuse the normal PC-relative operand relocations for the low part
5058      of a CONST16 operand.  */
5059   if (opcode == xtensa_const16_opcode)
5060     return 0;
5061
5062   xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5063                               get_relaxable_immed (opcode), val,
5064                               fixP->fx_file, fixP->fx_line);
5065
5066   xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5067   xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5068
5069   return 1;
5070 }
5071
5072 \f
5073 /* External Functions and Other GAS Hooks.  */
5074
5075 const char *
5076 xtensa_target_format (void)
5077 {
5078   return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5079 }
5080
5081
5082 void
5083 xtensa_file_arch_init (bfd *abfd)
5084 {
5085   bfd_set_private_flags (abfd, 0x100 | 0x200);
5086 }
5087
5088
5089 void
5090 md_number_to_chars (char *buf, valueT val, int n)
5091 {
5092   if (target_big_endian)
5093     number_to_chars_bigendian (buf, val, n);
5094   else
5095     number_to_chars_littleendian (buf, val, n);
5096 }
5097
5098
5099 /* This function is called once, at assembler startup time.  It should
5100    set up all the tables, etc. that the MD part of the assembler will
5101    need.  */
5102
5103 void
5104 md_begin (void)
5105 {
5106   segT current_section = now_seg;
5107   int current_subsec = now_subseg;
5108   xtensa_isa isa;
5109   int i;
5110
5111   xtensa_default_isa = xtensa_isa_init (0, 0);
5112   isa = xtensa_default_isa;
5113
5114   linkrelax = 1;
5115
5116   /* Set up the literal sections.  */
5117   memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5118
5119   subseg_set (current_section, current_subsec);
5120
5121   xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5122   xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5123   xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5124   xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5125   xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5126   xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5127   xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5128   xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5129   xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5130   xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
5131   xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
5132   xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
5133   xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui");
5134   xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5135   xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
5136   xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
5137   xtensa_j_opcode = xtensa_opcode_lookup (isa, "j");
5138   xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
5139   xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
5140   xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5141   xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5142   xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
5143   xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5144   xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5145   xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5146   xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5147   xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5148   xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5149   xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5150   xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5151   xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5152
5153   for (i = 0; i < xtensa_isa_num_formats (isa); i++)
5154     {
5155       int format_slots = xtensa_format_num_slots (isa, i);
5156       if (format_slots > config_max_slots)
5157         config_max_slots = format_slots;
5158     }
5159
5160   xg_init_vinsn (&cur_vinsn);
5161
5162   xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa);
5163
5164   init_op_placement_info_table ();
5165
5166   /* Set up the assembly state.  */
5167   if (!frag_now->tc_frag_data.is_assembly_state_set)
5168     xtensa_set_frag_assembly_state (frag_now);
5169 }
5170
5171
5172 /* TC_INIT_FIX_DATA hook */
5173
5174 void
5175 xtensa_init_fix_data (fixS *x)
5176 {
5177   x->tc_fix_data.slot = 0;
5178   x->tc_fix_data.X_add_symbol = NULL;
5179   x->tc_fix_data.X_add_number = 0;
5180 }
5181
5182
5183 /* tc_frob_label hook */
5184
5185 void
5186 xtensa_frob_label (symbolS *sym)
5187 {
5188   float freq;
5189
5190   if (cur_vinsn.inside_bundle)
5191     {
5192       as_bad (_("labels are not valid inside bundles"));
5193       return;
5194     }
5195
5196   freq = get_subseg_target_freq (now_seg, now_subseg);
5197
5198   /* Since the label was already attached to a frag associated with the
5199      previous basic block, it now needs to be reset to the current frag.  */
5200   symbol_set_frag (sym, frag_now);
5201   S_SET_VALUE (sym, (valueT) frag_now_fix ());
5202
5203   if (generating_literals)
5204     xtensa_add_literal_sym (sym);
5205   else
5206     xtensa_add_insn_label (sym);
5207
5208   if (symbol_get_tc (sym)->is_loop_target)
5209     {
5210       if ((get_last_insn_flags (now_seg, now_subseg)
5211           & FLAG_IS_BAD_LOOPEND) != 0)
5212         as_bad (_("invalid last instruction for a zero-overhead loop"));
5213
5214       xtensa_set_frag_assembly_state (frag_now);
5215       frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
5216                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5217
5218       xtensa_set_frag_assembly_state (frag_now);
5219       xtensa_move_labels (frag_now, 0);
5220     }
5221
5222   /* No target aligning in the absolute section.  */
5223   if (now_seg != absolute_section
5224       && !is_unaligned_label (sym)
5225       && !generating_literals)
5226     {
5227       xtensa_set_frag_assembly_state (frag_now);
5228
5229       if (do_align_targets ())
5230         frag_var (rs_machine_dependent, 0, (int) freq,
5231                   RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol,
5232                   frag_now->fr_offset, NULL);
5233       else
5234         frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
5235                   frag_now->fr_symbol, frag_now->fr_offset, NULL);
5236       xtensa_set_frag_assembly_state (frag_now);
5237       xtensa_move_labels (frag_now, 0);
5238     }
5239
5240   /* We need to mark the following properties even if we aren't aligning.  */
5241
5242   /* If the label is already known to be a branch target, i.e., a
5243      forward branch, mark the frag accordingly.  Backward branches
5244      are handled by xg_add_branch_and_loop_targets.  */
5245   if (symbol_get_tc (sym)->is_branch_target)
5246     symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5247
5248   /* Loops only go forward, so they can be identified here.  */
5249   if (symbol_get_tc (sym)->is_loop_target)
5250     symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5251
5252   dwarf2_emit_label (sym);
5253 }
5254
5255
5256 /* tc_unrecognized_line hook */
5257
5258 int
5259 xtensa_unrecognized_line (int ch)
5260 {
5261   switch (ch)
5262     {
5263     case '{' :
5264       if (cur_vinsn.inside_bundle == 0)
5265         {
5266           /* PR8110: Cannot emit line number info inside a FLIX bundle
5267              when using --gstabs.  Temporarily disable debug info.  */
5268           generate_lineno_debug ();
5269           if (debug_type == DEBUG_STABS)
5270             {
5271               xt_saved_debug_type = debug_type;
5272               debug_type = DEBUG_NONE;
5273             }
5274
5275           cur_vinsn.inside_bundle = 1;
5276         }
5277       else
5278         {
5279           as_bad (_("extra opening brace"));
5280           return 0;
5281         }
5282       break;
5283
5284     case '}' :
5285       if (cur_vinsn.inside_bundle)
5286         finish_vinsn (&cur_vinsn);
5287       else
5288         {
5289           as_bad (_("extra closing brace"));
5290           return 0;
5291         }
5292       break;
5293     default:
5294       as_bad (_("syntax error"));
5295       return 0;
5296     }
5297   return 1;
5298 }
5299
5300
5301 /* md_flush_pending_output hook */
5302
5303 void
5304 xtensa_flush_pending_output (void)
5305 {
5306   /* This line fixes a bug where automatically generated gstabs info
5307      separates a function label from its entry instruction, ending up
5308      with the literal position between the function label and the entry
5309      instruction and crashing code.  It only happens with --gstabs and
5310      --text-section-literals, and when several other obscure relaxation
5311      conditions are met.  */
5312   if (outputting_stabs_line_debug)
5313     return;
5314
5315   if (cur_vinsn.inside_bundle)
5316     as_bad (_("missing closing brace"));
5317
5318   /* If there is a non-zero instruction fragment, close it.  */
5319   if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5320     {
5321       frag_wane (frag_now);
5322       frag_new (0);
5323       xtensa_set_frag_assembly_state (frag_now);
5324     }
5325   frag_now->tc_frag_data.is_insn = FALSE;
5326
5327   xtensa_clear_insn_labels ();
5328 }
5329
5330
5331 /* We had an error while parsing an instruction.  The string might look
5332    like this: "insn arg1, arg2 }".  If so, we need to see the closing
5333    brace and reset some fields.  Otherwise, the vinsn never gets closed
5334    and the num_slots field will grow past the end of the array of slots,
5335    and bad things happen.  */
5336
5337 static void
5338 error_reset_cur_vinsn (void)
5339 {
5340   if (cur_vinsn.inside_bundle)
5341     {
5342       if (*input_line_pointer == '}'
5343           || *(input_line_pointer - 1) == '}'
5344           || *(input_line_pointer - 2) == '}')
5345         xg_clear_vinsn (&cur_vinsn);
5346     }
5347 }
5348
5349
5350 void
5351 md_assemble (char *str)
5352 {
5353   xtensa_isa isa = xtensa_default_isa;
5354   char *opname;
5355   unsigned opnamelen;
5356   bfd_boolean has_underbar = FALSE;
5357   char *arg_strings[MAX_INSN_ARGS];
5358   int num_args;
5359   TInsn orig_insn;              /* Original instruction from the input.  */
5360
5361   tinsn_init (&orig_insn);
5362
5363   /* Split off the opcode.  */
5364   opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5365   opname = xmalloc (opnamelen + 1);
5366   memcpy (opname, str, opnamelen);
5367   opname[opnamelen] = '\0';
5368
5369   num_args = tokenize_arguments (arg_strings, str + opnamelen);
5370   if (num_args == -1)
5371     {
5372       as_bad (_("syntax error"));
5373       return;
5374     }
5375
5376   if (xg_translate_idioms (&opname, &num_args, arg_strings))
5377     return;
5378
5379   /* Check for an underbar prefix.  */
5380   if (*opname == '_')
5381     {
5382       has_underbar = TRUE;
5383       opname += 1;
5384     }
5385
5386   orig_insn.insn_type = ITYPE_INSN;
5387   orig_insn.ntok = 0;
5388   orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5389   orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5390
5391   /* Special case: Check for "CALLXn.TLS" psuedo op.  If found, grab its
5392      extra argument and set the opcode to "CALLXn".  */
5393   if (orig_insn.opcode == XTENSA_UNDEFINED
5394       && strncasecmp (opname, "callx", 5) == 0)
5395     {
5396       unsigned long window_size;
5397       char *suffix;
5398
5399       window_size = strtoul (opname + 5, &suffix, 10);
5400       if (suffix != opname + 5
5401           && (window_size == 0
5402               || window_size == 4
5403               || window_size == 8
5404               || window_size == 12)
5405           && strcasecmp (suffix, ".tls") == 0)
5406         {
5407           switch (window_size)
5408             {
5409             case 0: orig_insn.opcode = xtensa_callx0_opcode; break;
5410             case 4: orig_insn.opcode = xtensa_callx4_opcode; break;
5411             case 8: orig_insn.opcode = xtensa_callx8_opcode; break;
5412             case 12: orig_insn.opcode = xtensa_callx12_opcode; break;
5413             }
5414
5415           if (num_args != 2)
5416             as_bad (_("wrong number of operands for '%s'"), opname);
5417           else
5418             {
5419               bfd_reloc_code_real_type reloc;
5420               char *old_input_line_pointer;
5421               expressionS *tok = &orig_insn.extra_arg;
5422               segT t;
5423
5424               old_input_line_pointer = input_line_pointer;
5425               input_line_pointer = arg_strings[num_args - 1];
5426
5427               t = expression (tok);
5428               if (tok->X_op == O_symbol
5429                   && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
5430                       == BFD_RELOC_XTENSA_TLS_CALL))
5431                 tok->X_op = map_suffix_reloc_to_operator (reloc);
5432               else
5433                 as_bad (_("bad relocation expression for '%s'"), opname);
5434
5435               input_line_pointer = old_input_line_pointer;
5436               num_args -= 1;
5437             }
5438         }
5439     }
5440
5441   /* Special case: Check for "j.l" psuedo op.  */
5442   if (orig_insn.opcode == XTENSA_UNDEFINED
5443       && strncasecmp (opname, "j.l", 3) == 0)
5444     {
5445       if (num_args != 2)
5446         as_bad (_("wrong number of operands for '%s'"), opname);
5447       else
5448         {
5449           char *old_input_line_pointer;
5450           expressionS *tok = &orig_insn.extra_arg;
5451
5452           old_input_line_pointer = input_line_pointer;
5453           input_line_pointer = arg_strings[num_args - 1];
5454
5455           expression_maybe_register (xtensa_jx_opcode, 0, tok);
5456           input_line_pointer = old_input_line_pointer;
5457
5458           num_args -= 1;
5459           orig_insn.opcode = xtensa_j_opcode;
5460         }
5461     }
5462
5463   if (orig_insn.opcode == XTENSA_UNDEFINED)
5464     {
5465       xtensa_format fmt = xtensa_format_lookup (isa, opname);
5466       if (fmt == XTENSA_UNDEFINED)
5467         {
5468           as_bad (_("unknown opcode or format name '%s'"), opname);
5469           error_reset_cur_vinsn ();
5470           return;
5471         }
5472       if (!cur_vinsn.inside_bundle)
5473         {
5474           as_bad (_("format names only valid inside bundles"));
5475           error_reset_cur_vinsn ();
5476           return;
5477         }
5478       if (cur_vinsn.format != XTENSA_UNDEFINED)
5479         as_warn (_("multiple formats specified for one bundle; using '%s'"),
5480                  opname);
5481       cur_vinsn.format = fmt;
5482       free (has_underbar ? opname - 1 : opname);
5483       error_reset_cur_vinsn ();
5484       return;
5485     }
5486
5487   /* Parse the arguments.  */
5488   if (parse_arguments (&orig_insn, num_args, arg_strings))
5489     {
5490       as_bad (_("syntax error"));
5491       error_reset_cur_vinsn ();
5492       return;
5493     }
5494
5495   /* Free the opcode and argument strings, now that they've been parsed.  */
5496   free (has_underbar ? opname - 1 : opname);
5497   opname = 0;
5498   while (num_args-- > 0)
5499     free (arg_strings[num_args]);
5500
5501   /* Get expressions for invisible operands.  */
5502   if (get_invisible_operands (&orig_insn))
5503     {
5504       error_reset_cur_vinsn ();
5505       return;
5506     }
5507
5508   /* Check for the right number and type of arguments.  */
5509   if (tinsn_check_arguments (&orig_insn))
5510     {
5511       error_reset_cur_vinsn ();
5512       return;
5513     }
5514
5515   /* Record the line number for each TInsn, because a FLIX bundle may be
5516      spread across multiple input lines and individual instructions may be
5517      moved around in some cases.  */
5518   orig_insn.loc_directive_seen = dwarf2_loc_directive_seen;
5519   dwarf2_where (&orig_insn.debug_line);
5520   dwarf2_consume_line_info ();
5521
5522   xg_add_branch_and_loop_targets (&orig_insn);
5523
5524   /* Check that immediate value for ENTRY is >= 16.  */
5525   if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3)
5526     {
5527       expressionS *exp = &orig_insn.tok[2];
5528       if (exp->X_op == O_constant && exp->X_add_number < 16)
5529         as_warn (_("entry instruction with stack decrement < 16"));
5530     }
5531
5532   /* Finish it off:
5533      assemble_tokens (opcode, tok, ntok);
5534      expand the tokens from the orig_insn into the
5535      stack of instructions that will not expand
5536      unless required at relaxation time.  */
5537
5538   if (!cur_vinsn.inside_bundle)
5539     emit_single_op (&orig_insn);
5540   else /* We are inside a bundle.  */
5541     {
5542       cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5543       cur_vinsn.num_slots++;
5544       if (*input_line_pointer == '}'
5545           || *(input_line_pointer - 1) == '}'
5546           || *(input_line_pointer - 2) == '}')
5547         finish_vinsn (&cur_vinsn);
5548     }
5549
5550   /* We've just emitted a new instruction so clear the list of labels.  */
5551   xtensa_clear_insn_labels ();
5552 }
5553
5554
5555 /* HANDLE_ALIGN hook */
5556
5557 /* For a .align directive, we mark the previous block with the alignment
5558    information.  This will be placed in the object file in the
5559    property section corresponding to this section.  */
5560
5561 void
5562 xtensa_handle_align (fragS *fragP)
5563 {
5564   if (linkrelax
5565       && ! fragP->tc_frag_data.is_literal
5566       && (fragP->fr_type == rs_align
5567           || fragP->fr_type == rs_align_code)
5568       && fragP->fr_address + fragP->fr_fix > 0
5569       && fragP->fr_offset > 0
5570       && now_seg != bss_section)
5571     {
5572       fragP->tc_frag_data.is_align = TRUE;
5573       fragP->tc_frag_data.alignment = fragP->fr_offset;
5574     }
5575
5576   if (fragP->fr_type == rs_align_test)
5577     {
5578       int count;
5579       count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5580       if (count != 0)
5581         as_bad_where (fragP->fr_file, fragP->fr_line,
5582                       _("unaligned entry instruction"));
5583     }
5584
5585   if (linkrelax && fragP->fr_type == rs_org)
5586     fragP->fr_subtype = RELAX_ORG;
5587 }
5588
5589
5590 /* TC_FRAG_INIT hook */
5591
5592 void
5593 xtensa_frag_init (fragS *frag)
5594 {
5595   xtensa_set_frag_assembly_state (frag);
5596 }
5597
5598
5599 symbolS *
5600 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5601 {
5602   return NULL;
5603 }
5604
5605
5606 /* Round up a section size to the appropriate boundary.  */
5607
5608 valueT
5609 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5610 {
5611   return size;                  /* Byte alignment is fine.  */
5612 }
5613
5614
5615 long
5616 md_pcrel_from (fixS *fixP)
5617 {
5618   char *insn_p;
5619   static xtensa_insnbuf insnbuf = NULL;
5620   static xtensa_insnbuf slotbuf = NULL;
5621   int opnum;
5622   uint32 opnd_value;
5623   xtensa_opcode opcode;
5624   xtensa_format fmt;
5625   int slot;
5626   xtensa_isa isa = xtensa_default_isa;
5627   valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5628   bfd_boolean alt_reloc;
5629
5630   if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5631     return 0;
5632
5633   if (fixP->fx_r_type == BFD_RELOC_32_PCREL)
5634     return addr;
5635
5636   if (!insnbuf)
5637     {
5638       insnbuf = xtensa_insnbuf_alloc (isa);
5639       slotbuf = xtensa_insnbuf_alloc (isa);
5640     }
5641
5642   insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5643   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
5644   fmt = xtensa_format_decode (isa, insnbuf);
5645
5646   if (fmt == XTENSA_UNDEFINED)
5647     as_fatal (_("bad instruction format"));
5648
5649   if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5650     as_fatal (_("invalid relocation"));
5651
5652   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5653   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5654
5655   /* Check for "alternate" relocations (operand not specified).  None
5656      of the current uses for these are really PC-relative.  */
5657   if (alt_reloc || opcode == xtensa_const16_opcode)
5658     {
5659       if (opcode != xtensa_l32r_opcode
5660           && opcode != xtensa_const16_opcode)
5661         as_fatal (_("invalid relocation for '%s' instruction"),
5662                   xtensa_opcode_name (isa, opcode));
5663       return 0;
5664     }
5665
5666   opnum = get_relaxable_immed (opcode);
5667   opnd_value = 0;
5668   if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5669       || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5670     {
5671       as_bad_where (fixP->fx_file,
5672                     fixP->fx_line,
5673                     _("invalid relocation for operand %d of '%s'"),
5674                     opnum, xtensa_opcode_name (isa, opcode));
5675       return 0;
5676     }
5677   return 0 - opnd_value;
5678 }
5679
5680
5681 /* TC_FORCE_RELOCATION hook */
5682
5683 int
5684 xtensa_force_relocation (fixS *fix)
5685 {
5686   switch (fix->fx_r_type)
5687     {
5688     case BFD_RELOC_XTENSA_ASM_EXPAND:
5689     case BFD_RELOC_XTENSA_SLOT0_ALT:
5690     case BFD_RELOC_XTENSA_SLOT1_ALT:
5691     case BFD_RELOC_XTENSA_SLOT2_ALT:
5692     case BFD_RELOC_XTENSA_SLOT3_ALT:
5693     case BFD_RELOC_XTENSA_SLOT4_ALT:
5694     case BFD_RELOC_XTENSA_SLOT5_ALT:
5695     case BFD_RELOC_XTENSA_SLOT6_ALT:
5696     case BFD_RELOC_XTENSA_SLOT7_ALT:
5697     case BFD_RELOC_XTENSA_SLOT8_ALT:
5698     case BFD_RELOC_XTENSA_SLOT9_ALT:
5699     case BFD_RELOC_XTENSA_SLOT10_ALT:
5700     case BFD_RELOC_XTENSA_SLOT11_ALT:
5701     case BFD_RELOC_XTENSA_SLOT12_ALT:
5702     case BFD_RELOC_XTENSA_SLOT13_ALT:
5703     case BFD_RELOC_XTENSA_SLOT14_ALT:
5704       return 1;
5705     default:
5706       break;
5707     }
5708
5709   if (linkrelax && fix->fx_addsy
5710       && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5711     return 1;
5712
5713   return generic_force_reloc (fix);
5714 }
5715
5716
5717 /* TC_VALIDATE_FIX_SUB hook */
5718
5719 int
5720 xtensa_validate_fix_sub (fixS *fix)
5721 {
5722   segT add_symbol_segment, sub_symbol_segment;
5723
5724   /* The difference of two symbols should be resolved by the assembler when
5725      linkrelax is not set.  If the linker may relax the section containing
5726      the symbols, then an Xtensa DIFF relocation must be generated so that
5727      the linker knows to adjust the difference value.  */
5728   if (!linkrelax || fix->fx_addsy == NULL)
5729     return 0;
5730
5731   /* Make sure both symbols are in the same segment, and that segment is
5732      "normal" and relaxable.  If the segment is not "normal", then the
5733      fix is not valid.  If the segment is not "relaxable", then the fix
5734      should have been handled earlier.  */
5735   add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5736   if (! SEG_NORMAL (add_symbol_segment) ||
5737       ! relaxable_section (add_symbol_segment))
5738     return 0;
5739   sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5740   return (sub_symbol_segment == add_symbol_segment);
5741 }
5742
5743
5744 /* NO_PSEUDO_DOT hook */
5745
5746 /* This function has nothing to do with pseudo dots, but this is the
5747    nearest macro to where the check needs to take place.  FIXME: This
5748    seems wrong.  */
5749
5750 bfd_boolean
5751 xtensa_check_inside_bundle (void)
5752 {
5753   if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5754     as_bad (_("directives are not valid inside bundles"));
5755
5756   /* This function must always return FALSE because it is called via a
5757      macro that has nothing to do with bundling.  */
5758   return FALSE;
5759 }
5760
5761
5762 /* md_elf_section_change_hook */
5763
5764 void
5765 xtensa_elf_section_change_hook (void)
5766 {
5767   /* Set up the assembly state.  */
5768   if (!frag_now->tc_frag_data.is_assembly_state_set)
5769     xtensa_set_frag_assembly_state (frag_now);
5770 }
5771
5772
5773 /* tc_fix_adjustable hook */
5774
5775 bfd_boolean
5776 xtensa_fix_adjustable (fixS *fixP)
5777 {
5778   /* We need the symbol name for the VTABLE entries.  */
5779   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5780       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5781     return 0;
5782
5783   return 1;
5784 }
5785
5786
5787 /* tc_symbol_new_hook */
5788
5789 symbolS *expr_symbols = NULL;
5790
5791 void
5792 xtensa_symbol_new_hook (symbolS *sym)
5793 {
5794   if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section)
5795     {
5796       symbol_get_tc (sym)->next_expr_symbol = expr_symbols;
5797       expr_symbols = sym;
5798     }
5799 }
5800
5801
5802 void
5803 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
5804 {
5805   char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5806   valueT val = 0;
5807
5808   /* Subtracted symbols are only allowed for a few relocation types, and
5809      unless linkrelax is enabled, they should not make it to this point.  */
5810   if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32
5811                                         || fixP->fx_r_type == BFD_RELOC_16
5812                                         || fixP->fx_r_type == BFD_RELOC_8)))
5813     as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
5814
5815   switch (fixP->fx_r_type)
5816     {
5817     case BFD_RELOC_32_PCREL:
5818     case BFD_RELOC_32:
5819     case BFD_RELOC_16:
5820     case BFD_RELOC_8:
5821       if (fixP->fx_subsy)
5822         {
5823           switch (fixP->fx_r_type)
5824             {
5825             case BFD_RELOC_8:
5826               fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5827               break;
5828             case BFD_RELOC_16:
5829               fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5830               break;
5831             case BFD_RELOC_32:
5832               fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5833               break;
5834             default:
5835               break;
5836             }
5837
5838           val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5839                  - S_GET_VALUE (fixP->fx_subsy));
5840
5841           /* The difference value gets written out, and the DIFF reloc
5842              identifies the address of the subtracted symbol (i.e., the one
5843              with the lowest address).  */
5844           *valP = val;
5845           fixP->fx_offset -= val;
5846           fixP->fx_subsy = NULL;
5847         }
5848       else if (! fixP->fx_addsy)
5849         {
5850           val = *valP;
5851           fixP->fx_done = 1;
5852         }
5853       /* fall through */
5854
5855     case BFD_RELOC_XTENSA_PLT:
5856       md_number_to_chars (fixpos, val, fixP->fx_size);
5857       fixP->fx_no_overflow = 0; /* Use the standard overflow check.  */
5858       break;
5859
5860     case BFD_RELOC_XTENSA_TLSDESC_FN:
5861     case BFD_RELOC_XTENSA_TLSDESC_ARG:
5862     case BFD_RELOC_XTENSA_TLS_TPOFF:
5863     case BFD_RELOC_XTENSA_TLS_DTPOFF:
5864       S_SET_THREAD_LOCAL (fixP->fx_addsy);
5865       md_number_to_chars (fixpos, 0, fixP->fx_size);
5866       fixP->fx_no_overflow = 0; /* Use the standard overflow check.  */
5867       break;
5868
5869     case BFD_RELOC_XTENSA_SLOT0_OP:
5870     case BFD_RELOC_XTENSA_SLOT1_OP:
5871     case BFD_RELOC_XTENSA_SLOT2_OP:
5872     case BFD_RELOC_XTENSA_SLOT3_OP:
5873     case BFD_RELOC_XTENSA_SLOT4_OP:
5874     case BFD_RELOC_XTENSA_SLOT5_OP:
5875     case BFD_RELOC_XTENSA_SLOT6_OP:
5876     case BFD_RELOC_XTENSA_SLOT7_OP:
5877     case BFD_RELOC_XTENSA_SLOT8_OP:
5878     case BFD_RELOC_XTENSA_SLOT9_OP:
5879     case BFD_RELOC_XTENSA_SLOT10_OP:
5880     case BFD_RELOC_XTENSA_SLOT11_OP:
5881     case BFD_RELOC_XTENSA_SLOT12_OP:
5882     case BFD_RELOC_XTENSA_SLOT13_OP:
5883     case BFD_RELOC_XTENSA_SLOT14_OP:
5884       if (linkrelax)
5885         {
5886           /* Write the tentative value of a PC-relative relocation to a
5887              local symbol into the instruction.  The value will be ignored
5888              by the linker, and it makes the object file disassembly
5889              readable when all branch targets are encoded in relocations.  */
5890
5891           gas_assert (fixP->fx_addsy);
5892           if (S_GET_SEGMENT (fixP->fx_addsy) == seg
5893               && !S_FORCE_RELOC (fixP->fx_addsy, 1))
5894             {
5895               val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5896                      - md_pcrel_from (fixP));
5897               (void) xg_apply_fix_value (fixP, val);
5898             }
5899         }
5900       else if (! fixP->fx_addsy)
5901         {
5902           val = *valP;
5903           if (xg_apply_fix_value (fixP, val))
5904             fixP->fx_done = 1;
5905         }
5906       break;
5907
5908     case BFD_RELOC_XTENSA_ASM_EXPAND:
5909     case BFD_RELOC_XTENSA_TLS_FUNC:
5910     case BFD_RELOC_XTENSA_TLS_ARG:
5911     case BFD_RELOC_XTENSA_TLS_CALL:
5912     case BFD_RELOC_XTENSA_SLOT0_ALT:
5913     case BFD_RELOC_XTENSA_SLOT1_ALT:
5914     case BFD_RELOC_XTENSA_SLOT2_ALT:
5915     case BFD_RELOC_XTENSA_SLOT3_ALT:
5916     case BFD_RELOC_XTENSA_SLOT4_ALT:
5917     case BFD_RELOC_XTENSA_SLOT5_ALT:
5918     case BFD_RELOC_XTENSA_SLOT6_ALT:
5919     case BFD_RELOC_XTENSA_SLOT7_ALT:
5920     case BFD_RELOC_XTENSA_SLOT8_ALT:
5921     case BFD_RELOC_XTENSA_SLOT9_ALT:
5922     case BFD_RELOC_XTENSA_SLOT10_ALT:
5923     case BFD_RELOC_XTENSA_SLOT11_ALT:
5924     case BFD_RELOC_XTENSA_SLOT12_ALT:
5925     case BFD_RELOC_XTENSA_SLOT13_ALT:
5926     case BFD_RELOC_XTENSA_SLOT14_ALT:
5927       /* These all need to be resolved at link-time.  Do nothing now.  */
5928       break;
5929
5930     case BFD_RELOC_VTABLE_INHERIT:
5931     case BFD_RELOC_VTABLE_ENTRY:
5932       fixP->fx_done = 0;
5933       break;
5934
5935     default:
5936       as_bad (_("unhandled local relocation fix %s"),
5937               bfd_get_reloc_code_name (fixP->fx_r_type));
5938     }
5939 }
5940
5941
5942 char *
5943 md_atof (int type, char *litP, int *sizeP)
5944 {
5945   return ieee_md_atof (type, litP, sizeP, target_big_endian);
5946 }
5947
5948
5949 int
5950 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
5951 {
5952   return total_frag_text_expansion (fragP);
5953 }
5954
5955
5956 /* Translate internal representation of relocation info to BFD target
5957    format.  */
5958
5959 arelent *
5960 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
5961 {
5962   arelent *reloc;
5963
5964   reloc = (arelent *) xmalloc (sizeof (arelent));
5965   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5966   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5967   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5968
5969   /* Make sure none of our internal relocations make it this far.
5970      They'd better have been fully resolved by this point.  */
5971   gas_assert ((int) fixp->fx_r_type > 0);
5972
5973   reloc->addend = fixp->fx_offset;
5974
5975   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
5976   if (reloc->howto == NULL)
5977     {
5978       as_bad_where (fixp->fx_file, fixp->fx_line,
5979                     _("cannot represent `%s' relocation in object file"),
5980                     bfd_get_reloc_code_name (fixp->fx_r_type));
5981       free (reloc->sym_ptr_ptr);
5982       free (reloc);
5983       return NULL;
5984     }
5985
5986   if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
5987     as_fatal (_("internal error; cannot generate `%s' relocation"),
5988               bfd_get_reloc_code_name (fixp->fx_r_type));
5989
5990   return reloc;
5991 }
5992
5993 \f
5994 /* Checks for resource conflicts between instructions.  */
5995
5996 /* The func unit stuff could be implemented as bit-vectors rather
5997    than the iterative approach here.  If it ends up being too
5998    slow, we will switch it.  */
5999
6000 resource_table *
6001 new_resource_table (void *data,
6002                     int cycles,
6003                     int nu,
6004                     unit_num_copies_func uncf,
6005                     opcode_num_units_func onuf,
6006                     opcode_funcUnit_use_unit_func ouuf,
6007                     opcode_funcUnit_use_stage_func ousf)
6008 {
6009   int i;
6010   resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
6011   rt->data = data;
6012   rt->cycles = cycles;
6013   rt->allocated_cycles = cycles;
6014   rt->num_units = nu;
6015   rt->unit_num_copies = uncf;
6016   rt->opcode_num_units = onuf;
6017   rt->opcode_unit_use = ouuf;
6018   rt->opcode_unit_stage = ousf;
6019
6020   rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *));
6021   for (i = 0; i < cycles; i++)
6022     rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char));
6023
6024   return rt;
6025 }
6026
6027
6028 void
6029 clear_resource_table (resource_table *rt)
6030 {
6031   int i, j;
6032   for (i = 0; i < rt->allocated_cycles; i++)
6033     for (j = 0; j < rt->num_units; j++)
6034       rt->units[i][j] = 0;
6035 }
6036
6037
6038 /* We never shrink it, just fake it into thinking so.  */
6039
6040 void
6041 resize_resource_table (resource_table *rt, int cycles)
6042 {
6043   int i, old_cycles;
6044
6045   rt->cycles = cycles;
6046   if (cycles <= rt->allocated_cycles)
6047     return;
6048
6049   old_cycles = rt->allocated_cycles;
6050   rt->allocated_cycles = cycles;
6051
6052   rt->units = xrealloc (rt->units,
6053                         rt->allocated_cycles * sizeof (unsigned char *));
6054   for (i = 0; i < old_cycles; i++)
6055     rt->units[i] = xrealloc (rt->units[i],
6056                              rt->num_units * sizeof (unsigned char));
6057   for (i = old_cycles; i < cycles; i++)
6058     rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char));
6059 }
6060
6061
6062 bfd_boolean
6063 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
6064 {
6065   int i;
6066   int uses = (rt->opcode_num_units) (rt->data, opcode);
6067
6068   for (i = 0; i < uses; i++)
6069     {
6070       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6071       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6072       int copies_in_use = rt->units[stage + cycle][unit];
6073       int copies = (rt->unit_num_copies) (rt->data, unit);
6074       if (copies_in_use >= copies)
6075         return FALSE;
6076     }
6077   return TRUE;
6078 }
6079
6080
6081 void
6082 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6083 {
6084   int i;
6085   int uses = (rt->opcode_num_units) (rt->data, opcode);
6086
6087   for (i = 0; i < uses; i++)
6088     {
6089       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6090       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6091       /* Note that this allows resources to be oversubscribed.  That's
6092          essential to the way the optional scheduler works.
6093          resources_available reports when a resource is over-subscribed,
6094          so it's easy to tell.  */
6095       rt->units[stage + cycle][unit]++;
6096     }
6097 }
6098
6099
6100 void
6101 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6102 {
6103   int i;
6104   int uses = (rt->opcode_num_units) (rt->data, opcode);
6105
6106   for (i = 0; i < uses; i++)
6107     {
6108       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6109       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6110       gas_assert (rt->units[stage + cycle][unit] > 0);
6111       rt->units[stage + cycle][unit]--;
6112     }
6113 }
6114
6115
6116 /* Wrapper functions make parameterized resource reservation
6117    more convenient.  */
6118
6119 int
6120 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
6121 {
6122   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6123   return use->unit;
6124 }
6125
6126
6127 int
6128 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
6129 {
6130   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6131   return use->stage;
6132 }
6133
6134
6135 /* Note that this function does not check issue constraints, but
6136    solely whether the hardware is available to execute the given
6137    instructions together.  It also doesn't check if the tinsns
6138    write the same state, or access the same tieports.  That is
6139    checked by check_t1_t2_reads_and_writes.  */
6140
6141 static bfd_boolean
6142 resources_conflict (vliw_insn *vinsn)
6143 {
6144   int i;
6145   static resource_table *rt = NULL;
6146
6147   /* This is the most common case by far.  Optimize it.  */
6148   if (vinsn->num_slots == 1)
6149     return FALSE;
6150
6151   if (rt == NULL)
6152     {
6153       xtensa_isa isa = xtensa_default_isa;
6154       rt = new_resource_table
6155         (isa, xtensa_num_pipe_stages,
6156          xtensa_isa_num_funcUnits (isa),
6157          (unit_num_copies_func) xtensa_funcUnit_num_copies,
6158          (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6159          opcode_funcUnit_use_unit,
6160          opcode_funcUnit_use_stage);
6161     }
6162
6163   clear_resource_table (rt);
6164
6165   for (i = 0; i < vinsn->num_slots; i++)
6166     {
6167       if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6168         return TRUE;
6169       reserve_resources (rt, vinsn->slots[i].opcode, 0);
6170     }
6171
6172   return FALSE;
6173 }
6174
6175 \f
6176 /* finish_vinsn, emit_single_op and helper functions.  */
6177
6178 static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6179 static xtensa_format xg_find_narrowest_format (vliw_insn *);
6180 static void xg_assemble_vliw_tokens (vliw_insn *);
6181
6182
6183 /* We have reached the end of a bundle; emit into the frag.  */
6184
6185 static void
6186 finish_vinsn (vliw_insn *vinsn)
6187 {
6188   IStack slotstack;
6189   int i;
6190   char *file_name;
6191   unsigned line;
6192
6193   if (find_vinsn_conflicts (vinsn))
6194     {
6195       xg_clear_vinsn (vinsn);
6196       return;
6197     }
6198
6199   /* First, find a format that works.  */
6200   if (vinsn->format == XTENSA_UNDEFINED)
6201     vinsn->format = xg_find_narrowest_format (vinsn);
6202
6203   if (xtensa_format_num_slots (xtensa_default_isa, vinsn->format) > 1
6204       && produce_flix == FLIX_NONE)
6205     {
6206       as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6207       xg_clear_vinsn (vinsn);
6208       return;
6209     }
6210
6211   if (vinsn->format == XTENSA_UNDEFINED)
6212     {
6213       as_where (&file_name, &line);
6214       as_bad_where (file_name, line,
6215                     _("couldn't find a valid instruction format"));
6216       fprintf (stderr, _("    ops were: "));
6217       for (i = 0; i < vinsn->num_slots; i++)
6218         fprintf (stderr, _(" %s;"),
6219                  xtensa_opcode_name (xtensa_default_isa,
6220                                      vinsn->slots[i].opcode));
6221       fprintf (stderr, _("\n"));
6222       xg_clear_vinsn (vinsn);
6223       return;
6224     }
6225
6226   if (vinsn->num_slots
6227       != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
6228     {
6229       as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6230               xtensa_format_name (xtensa_default_isa, vinsn->format),
6231               xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6232               vinsn->num_slots);
6233       xg_clear_vinsn (vinsn);
6234       return;
6235     }
6236
6237   if (resources_conflict (vinsn))
6238     {
6239       as_where (&file_name, &line);
6240       as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6241       fprintf (stderr, "    ops were: ");
6242       for (i = 0; i < vinsn->num_slots; i++)
6243         fprintf (stderr, " %s;",
6244                  xtensa_opcode_name (xtensa_default_isa,
6245                                      vinsn->slots[i].opcode));
6246       fprintf (stderr, "\n");
6247       xg_clear_vinsn (vinsn);
6248       return;
6249     }
6250
6251   for (i = 0; i < vinsn->num_slots; i++)
6252     {
6253       if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6254         {
6255           symbolS *lit_sym = NULL;
6256           int j;
6257           bfd_boolean e = FALSE;
6258           bfd_boolean saved_density = density_supported;
6259
6260           /* We don't want to narrow ops inside multi-slot bundles.  */
6261           if (vinsn->num_slots > 1)
6262             density_supported = FALSE;
6263
6264           istack_init (&slotstack);
6265           if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6266             {
6267               vinsn->slots[i].opcode =
6268                 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6269                                                vinsn->format, i);
6270               vinsn->slots[i].ntok = 0;
6271             }
6272
6273           if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6274             {
6275               e = TRUE;
6276               continue;
6277             }
6278
6279           density_supported = saved_density;
6280
6281           if (e)
6282             {
6283               xg_clear_vinsn (vinsn);
6284               return;
6285             }
6286
6287           for (j = 0; j < slotstack.ninsn; j++)
6288             {
6289               TInsn *insn = &slotstack.insn[j];
6290               if (insn->insn_type == ITYPE_LITERAL)
6291                 {
6292                   gas_assert (lit_sym == NULL);
6293                   lit_sym = xg_assemble_literal (insn);
6294                 }
6295               else
6296                 {
6297                   gas_assert (insn->insn_type == ITYPE_INSN);
6298                   if (lit_sym)
6299                     xg_resolve_literals (insn, lit_sym);
6300                   if (j != slotstack.ninsn - 1)
6301                     emit_single_op (insn);
6302                 }
6303             }
6304
6305           if (vinsn->num_slots > 1)
6306             {
6307               if (opcode_fits_format_slot
6308                   (slotstack.insn[slotstack.ninsn - 1].opcode,
6309                    vinsn->format, i))
6310                 {
6311                   vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6312                 }
6313               else
6314                 {
6315                   emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6316                   if (vinsn->format == XTENSA_UNDEFINED)
6317                     vinsn->slots[i].opcode = xtensa_nop_opcode;
6318                   else
6319                     vinsn->slots[i].opcode
6320                       = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6321                                                        vinsn->format, i);
6322
6323                   vinsn->slots[i].ntok = 0;
6324                 }
6325             }
6326           else
6327             {
6328               vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6329               vinsn->format = XTENSA_UNDEFINED;
6330             }
6331         }
6332     }
6333
6334   /* Now check resource conflicts on the modified bundle.  */
6335   if (resources_conflict (vinsn))
6336     {
6337       as_where (&file_name, &line);
6338       as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6339       fprintf (stderr, "    ops were: ");
6340       for (i = 0; i < vinsn->num_slots; i++)
6341         fprintf (stderr, " %s;",
6342                  xtensa_opcode_name (xtensa_default_isa,
6343                                      vinsn->slots[i].opcode));
6344       fprintf (stderr, "\n");
6345       xg_clear_vinsn (vinsn);
6346       return;
6347     }
6348
6349   /* First, find a format that works.  */
6350   if (vinsn->format == XTENSA_UNDEFINED)
6351       vinsn->format = xg_find_narrowest_format (vinsn);
6352
6353   xg_assemble_vliw_tokens (vinsn);
6354
6355   xg_clear_vinsn (vinsn);
6356 }
6357
6358
6359 /* Given an vliw instruction, what conflicts are there in register
6360    usage and in writes to states and queues?
6361
6362    This function does two things:
6363    1. Reports an error when a vinsn contains illegal combinations
6364       of writes to registers states or queues.
6365    2. Marks individual tinsns as not relaxable if the combination
6366       contains antidependencies.
6367
6368    Job 2 handles things like swap semantics in instructions that need
6369    to be relaxed.  For example,
6370
6371         addi a0, a1, 100000
6372
6373    normally would be relaxed to
6374
6375         l32r a0, some_label
6376         add a0, a1, a0
6377
6378    _but_, if the above instruction is bundled with an a0 reader, e.g.,
6379
6380         { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6381
6382    then we can't relax it into
6383
6384         l32r a0, some_label
6385         { add a0, a1, a0 ; add a2, a0, a4 ; }
6386
6387    because the value of a0 is trashed before the second add can read it.  */
6388
6389 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6390
6391 static bfd_boolean
6392 find_vinsn_conflicts (vliw_insn *vinsn)
6393 {
6394   int i, j;
6395   int branches = 0;
6396   xtensa_isa isa = xtensa_default_isa;
6397
6398   gas_assert (!past_xtensa_end);
6399
6400   for (i = 0 ; i < vinsn->num_slots; i++)
6401     {
6402       TInsn *op1 = &vinsn->slots[i];
6403       if (op1->is_specific_opcode)
6404         op1->keep_wide = TRUE;
6405       else
6406         op1->keep_wide = FALSE;
6407     }
6408
6409   for (i = 0 ; i < vinsn->num_slots; i++)
6410     {
6411       TInsn *op1 = &vinsn->slots[i];
6412
6413       if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6414         branches++;
6415
6416       for (j = 0; j < vinsn->num_slots; j++)
6417         {
6418           if (i != j)
6419             {
6420               TInsn *op2 = &vinsn->slots[j];
6421               char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6422               switch (conflict_type)
6423                 {
6424                 case 'c':
6425                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6426                           xtensa_opcode_name (isa, op1->opcode), i,
6427                           xtensa_opcode_name (isa, op2->opcode), j);
6428                   return TRUE;
6429                 case 'd':
6430                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6431                           xtensa_opcode_name (isa, op1->opcode), i,
6432                           xtensa_opcode_name (isa, op2->opcode), j);
6433                   return TRUE;
6434                 case 'e':
6435                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6436                           xtensa_opcode_name (isa, op1->opcode), i,
6437                           xtensa_opcode_name (isa, op2->opcode), j);
6438                   return TRUE;
6439                 case 'f':
6440                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6441                           xtensa_opcode_name (isa, op1->opcode), i,
6442                           xtensa_opcode_name (isa, op2->opcode), j);
6443                   return TRUE;
6444                 default:
6445                   /* Everything is OK.  */
6446                   break;
6447                 }
6448               op2->is_specific_opcode = (op2->is_specific_opcode
6449                                          || conflict_type == 'a');
6450             }
6451         }
6452     }
6453
6454   if (branches > 1)
6455     {
6456       as_bad (_("multiple branches or jumps in the same bundle"));
6457       return TRUE;
6458     }
6459
6460   return FALSE;
6461 }
6462
6463
6464 /* Check how the state used by t1 and t2 relate.
6465    Cases found are:
6466
6467    case A: t1 reads a register t2 writes (an antidependency within a bundle)
6468    case B: no relationship between what is read and written (both could
6469            read the same reg though)
6470    case C: t1 writes a register t2 writes (a register conflict within a
6471            bundle)
6472    case D: t1 writes a state that t2 also writes
6473    case E: t1 writes a tie queue that t2 also writes
6474    case F: two volatile queue accesses
6475 */
6476
6477 static char
6478 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6479 {
6480   xtensa_isa isa = xtensa_default_isa;
6481   xtensa_regfile t1_regfile, t2_regfile;
6482   int t1_reg, t2_reg;
6483   int t1_base_reg, t1_last_reg;
6484   int t2_base_reg, t2_last_reg;
6485   char t1_inout, t2_inout;
6486   int i, j;
6487   char conflict = 'b';
6488   int t1_states;
6489   int t2_states;
6490   int t1_interfaces;
6491   int t2_interfaces;
6492   bfd_boolean t1_volatile = FALSE;
6493   bfd_boolean t2_volatile = FALSE;
6494
6495   /* Check registers.  */
6496   for (j = 0; j < t2->ntok; j++)
6497     {
6498       if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6499         continue;
6500
6501       t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6502       t2_base_reg = t2->tok[j].X_add_number;
6503       t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6504
6505       for (i = 0; i < t1->ntok; i++)
6506         {
6507           if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6508             continue;
6509
6510           t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6511
6512           if (t1_regfile != t2_regfile)
6513             continue;
6514
6515           t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6516           t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6517
6518           if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6519               || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6520             {
6521               if (t1_inout == 'm' || t1_inout == 'o'
6522                   || t2_inout == 'm' || t2_inout == 'o')
6523                 {
6524                   conflict = 'a';
6525                   continue;
6526                 }
6527             }
6528
6529           t1_base_reg = t1->tok[i].X_add_number;
6530           t1_last_reg = (t1_base_reg
6531                          + xtensa_operand_num_regs (isa, t1->opcode, i));
6532
6533           for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6534             {
6535               for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6536                 {
6537                   if (t1_reg != t2_reg)
6538                     continue;
6539
6540                   if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6541                     {
6542                       conflict = 'a';
6543                       continue;
6544                     }
6545
6546                   if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6547                     {
6548                       conflict = 'a';
6549                       continue;
6550                     }
6551
6552                   if (t1_inout != 'i' && t2_inout != 'i')
6553                     return 'c';
6554                 }
6555             }
6556         }
6557     }
6558
6559   /* Check states.  */
6560   t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6561   t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6562   for (j = 0; j < t2_states; j++)
6563     {
6564       xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6565       t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6566       for (i = 0; i < t1_states; i++)
6567         {
6568           xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6569           t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6570           if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1)
6571             continue;
6572
6573           if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6574             {
6575               conflict = 'a';
6576               continue;
6577             }
6578
6579           if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6580             {
6581               conflict = 'a';
6582               continue;
6583             }
6584
6585           if (t1_inout != 'i' && t2_inout != 'i')
6586             return 'd';
6587         }
6588     }
6589
6590   /* Check tieports.  */
6591   t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6592   t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6593   for (j = 0; j < t2_interfaces; j++)
6594     {
6595       xtensa_interface t2_int
6596         = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6597       int t2_class = xtensa_interface_class_id (isa, t2_int);
6598
6599       t2_inout = xtensa_interface_inout (isa, t2_int);
6600       if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
6601         t2_volatile = TRUE;
6602
6603       for (i = 0; i < t1_interfaces; i++)
6604         {
6605           xtensa_interface t1_int
6606             = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6607           int t1_class = xtensa_interface_class_id (isa, t1_int);
6608
6609           t1_inout = xtensa_interface_inout (isa, t1_int);
6610           if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
6611             t1_volatile = TRUE;
6612
6613           if (t1_volatile && t2_volatile && (t1_class == t2_class))
6614             return 'f';
6615
6616           if (t1_int != t2_int)
6617             continue;
6618
6619           if (t2_inout == 'i' && t1_inout == 'o')
6620             {
6621               conflict = 'a';
6622               continue;
6623             }
6624
6625           if (t1_inout == 'i' && t2_inout == 'o')
6626             {
6627               conflict = 'a';
6628               continue;
6629             }
6630
6631           if (t1_inout != 'i' && t2_inout != 'i')
6632             return 'e';
6633         }
6634     }
6635
6636   return conflict;
6637 }
6638
6639
6640 static xtensa_format
6641 xg_find_narrowest_format (vliw_insn *vinsn)
6642 {
6643   /* Right now we assume that the ops within the vinsn are properly
6644      ordered for the slots that the programmer wanted them in.  In
6645      other words, we don't rearrange the ops in hopes of finding a
6646      better format.  The scheduler handles that.  */
6647
6648   xtensa_isa isa = xtensa_default_isa;
6649   xtensa_format format;
6650   xtensa_opcode nop_opcode = xtensa_nop_opcode;
6651
6652   if (vinsn->num_slots == 1)
6653     return xg_get_single_format (vinsn->slots[0].opcode);
6654
6655   for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6656     {
6657       vliw_insn v_copy;
6658       xg_copy_vinsn (&v_copy, vinsn);
6659       if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6660         {
6661           int slot;
6662           int fit = 0;
6663           for (slot = 0; slot < v_copy.num_slots; slot++)
6664             {
6665               if (v_copy.slots[slot].opcode == nop_opcode)
6666                 {
6667                   v_copy.slots[slot].opcode =
6668                     xtensa_format_slot_nop_opcode (isa, format, slot);
6669                   v_copy.slots[slot].ntok = 0;
6670                 }
6671
6672               if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6673                                            format, slot))
6674                 fit++;
6675               else if (v_copy.num_slots > 1)
6676                 {
6677                   TInsn widened;
6678                   /* Try the widened version.  */
6679                   if (!v_copy.slots[slot].keep_wide
6680                       && !v_copy.slots[slot].is_specific_opcode
6681                       && xg_is_single_relaxable_insn (&v_copy.slots[slot],
6682                                                       &widened, TRUE)
6683                       && opcode_fits_format_slot (widened.opcode,
6684                                                   format, slot))
6685                     {
6686                       v_copy.slots[slot] = widened;
6687                       fit++;
6688                     }
6689                 }
6690             }
6691           if (fit == v_copy.num_slots)
6692             {
6693               xg_copy_vinsn (vinsn, &v_copy);
6694               xtensa_format_encode (isa, format, vinsn->insnbuf);
6695               vinsn->format = format;
6696               break;
6697             }
6698         }
6699     }
6700
6701   if (format == xtensa_isa_num_formats (isa))
6702     return XTENSA_UNDEFINED;
6703
6704   return format;
6705 }
6706
6707
6708 /* Return the additional space needed in a frag
6709    for possible relaxations of any ops in a VLIW insn.
6710    Also fill out the relaxations that might be required of
6711    each tinsn in the vinsn.  */
6712
6713 static int
6714 relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
6715 {
6716   bfd_boolean finish_frag = FALSE;
6717   int extra_space = 0;
6718   int slot;
6719
6720   for (slot = 0; slot < vinsn->num_slots; slot++)
6721     {
6722       TInsn *tinsn = &vinsn->slots[slot];
6723       if (!tinsn_has_symbolic_operands (tinsn))
6724         {
6725           /* A narrow instruction could be widened later to help
6726              alignment issues.  */
6727           if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
6728               && !tinsn->is_specific_opcode
6729               && vinsn->num_slots == 1)
6730             {
6731               /* Difference in bytes between narrow and wide insns...  */
6732               extra_space += 1;
6733               tinsn->subtype = RELAX_NARROW;
6734             }
6735         }
6736       else
6737         {
6738           if (workaround_b_j_loop_end
6739               && tinsn->opcode == xtensa_jx_opcode
6740               && use_transform ())
6741             {
6742               /* Add 2 of these.  */
6743               extra_space += 3; /* for the nop size */
6744               tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6745             }
6746
6747           /* Need to assemble it with space for the relocation.  */
6748           if (xg_is_relaxable_insn (tinsn, 0)
6749               && !tinsn->is_specific_opcode)
6750             {
6751               int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6752               int max_literal_size =
6753                 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6754
6755               tinsn->literal_space = max_literal_size;
6756
6757               tinsn->subtype = RELAX_IMMED;
6758               extra_space += max_size;
6759             }
6760           else
6761             {
6762               /* A fix record will be added for this instruction prior
6763                  to relaxation, so make it end the frag.  */
6764               finish_frag = TRUE;
6765             }
6766         }
6767     }
6768   *pfinish_frag = finish_frag;
6769   return extra_space;
6770 }
6771
6772
6773 static void
6774 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
6775 {
6776   xtensa_isa isa = xtensa_default_isa;
6777   int slot, chosen_slot;
6778
6779   vinsn->format = xg_get_single_format (tinsn->opcode);
6780   gas_assert (vinsn->format != XTENSA_UNDEFINED);
6781   vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
6782
6783   chosen_slot = xg_get_single_slot (tinsn->opcode);
6784   for (slot = 0; slot < vinsn->num_slots; slot++)
6785     {
6786       if (slot == chosen_slot)
6787         vinsn->slots[slot] = *tinsn;
6788       else
6789         {
6790           vinsn->slots[slot].opcode =
6791             xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
6792           vinsn->slots[slot].ntok = 0;
6793           vinsn->slots[slot].insn_type = ITYPE_INSN;
6794         }
6795     }
6796 }
6797
6798
6799 static bfd_boolean
6800 emit_single_op (TInsn *orig_insn)
6801 {
6802   int i;
6803   IStack istack;                /* put instructions into here */
6804   symbolS *lit_sym = NULL;
6805   symbolS *label_sym = NULL;
6806
6807   istack_init (&istack);
6808
6809   /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6810      Because the scheduling and bundling characteristics of movi and
6811      l32r or const16 are so different, we can do much better if we relax
6812      it prior to scheduling and bundling, rather than after.  */
6813   if ((orig_insn->opcode == xtensa_movi_opcode
6814        || orig_insn->opcode == xtensa_movi_n_opcode)
6815       && !cur_vinsn.inside_bundle
6816       && (orig_insn->tok[1].X_op == O_symbol
6817           || orig_insn->tok[1].X_op == O_pltrel
6818           || orig_insn->tok[1].X_op == O_tlsfunc
6819           || orig_insn->tok[1].X_op == O_tlsarg
6820           || orig_insn->tok[1].X_op == O_tpoff
6821           || orig_insn->tok[1].X_op == O_dtpoff)
6822       && !orig_insn->is_specific_opcode && use_transform ())
6823     xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6824   else
6825     if (xg_expand_assembly_insn (&istack, orig_insn))
6826       return TRUE;
6827
6828   for (i = 0; i < istack.ninsn; i++)
6829     {
6830       TInsn *insn = &istack.insn[i];
6831       switch (insn->insn_type)
6832         {
6833         case ITYPE_LITERAL:
6834           gas_assert (lit_sym == NULL);
6835           lit_sym = xg_assemble_literal (insn);
6836           break;
6837         case ITYPE_LABEL:
6838           {
6839             static int relaxed_sym_idx = 0;
6840             char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
6841             sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6842             colon (label);
6843             gas_assert (label_sym == NULL);
6844             label_sym = symbol_find_or_make (label);
6845             gas_assert (label_sym);
6846             free (label);
6847           }
6848           break;
6849         case ITYPE_INSN:
6850           {
6851             vliw_insn v;
6852             if (lit_sym)
6853               xg_resolve_literals (insn, lit_sym);
6854             if (label_sym)
6855               xg_resolve_labels (insn, label_sym);
6856             xg_init_vinsn (&v);
6857             bundle_tinsn (insn, &v);
6858             finish_vinsn (&v);
6859             xg_free_vinsn (&v);
6860           }
6861           break;
6862         default:
6863           gas_assert (0);
6864           break;
6865         }
6866     }
6867   return FALSE;
6868 }
6869
6870
6871 static int
6872 total_frag_text_expansion (fragS *fragP)
6873 {
6874   int slot;
6875   int total_expansion = 0;
6876
6877   for (slot = 0; slot < config_max_slots; slot++)
6878     total_expansion += fragP->tc_frag_data.text_expansion[slot];
6879
6880   return total_expansion;
6881 }
6882
6883
6884 /* Emit a vliw instruction to the current fragment.  */
6885
6886 static void
6887 xg_assemble_vliw_tokens (vliw_insn *vinsn)
6888 {
6889   bfd_boolean finish_frag;
6890   bfd_boolean is_jump = FALSE;
6891   bfd_boolean is_branch = FALSE;
6892   xtensa_isa isa = xtensa_default_isa;
6893   int insn_size;
6894   int extra_space;
6895   char *f = NULL;
6896   int slot;
6897   struct dwarf2_line_info debug_line;
6898   bfd_boolean loc_directive_seen = FALSE;
6899   TInsn *tinsn;
6900
6901   memset (&debug_line, 0, sizeof (struct dwarf2_line_info));
6902
6903   if (generating_literals)
6904     {
6905       static int reported = 0;
6906       if (reported < 4)
6907         as_bad_where (frag_now->fr_file, frag_now->fr_line,
6908                       _("cannot assemble into a literal fragment"));
6909       if (reported == 3)
6910         as_bad (_("..."));
6911       reported++;
6912       return;
6913     }
6914
6915   if (frag_now_fix () != 0
6916       && (! frag_now->tc_frag_data.is_insn
6917           || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6918           || !use_transform () != frag_now->tc_frag_data.is_no_transform
6919           || (directive_state[directive_longcalls]
6920               != frag_now->tc_frag_data.use_longcalls)
6921           || (directive_state[directive_absolute_literals]
6922               != frag_now->tc_frag_data.use_absolute_literals)))
6923     {
6924       frag_wane (frag_now);
6925       frag_new (0);
6926       xtensa_set_frag_assembly_state (frag_now);
6927     }
6928
6929   if (workaround_a0_b_retw
6930       && vinsn->num_slots == 1
6931       && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
6932       && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
6933       && use_transform ())
6934     {
6935       has_a0_b_retw = TRUE;
6936
6937       /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6938          After the first assembly pass we will check all of them and
6939          add a nop if needed.  */
6940       frag_now->tc_frag_data.is_insn = TRUE;
6941       frag_var (rs_machine_dependent, 4, 4,
6942                 RELAX_ADD_NOP_IF_A0_B_RETW,
6943                 frag_now->fr_symbol,
6944                 frag_now->fr_offset,
6945                 NULL);
6946       xtensa_set_frag_assembly_state (frag_now);
6947       frag_now->tc_frag_data.is_insn = TRUE;
6948       frag_var (rs_machine_dependent, 4, 4,
6949                 RELAX_ADD_NOP_IF_A0_B_RETW,
6950                 frag_now->fr_symbol,
6951                 frag_now->fr_offset,
6952                 NULL);
6953       xtensa_set_frag_assembly_state (frag_now);
6954     }
6955
6956   for (slot = 0; slot < vinsn->num_slots; slot++)
6957     {
6958       tinsn = &vinsn->slots[slot];
6959
6960       /* See if the instruction implies an aligned section.  */
6961       if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1)
6962         record_alignment (now_seg, 2);
6963
6964       /* Determine the best line number for debug info.  */
6965       if ((tinsn->loc_directive_seen || !loc_directive_seen)
6966           && (tinsn->debug_line.filenum != debug_line.filenum
6967               || tinsn->debug_line.line < debug_line.line
6968               || tinsn->debug_line.column < debug_line.column))
6969         debug_line = tinsn->debug_line;
6970       if (tinsn->loc_directive_seen)
6971         loc_directive_seen = TRUE;
6972     }
6973
6974   /* Special cases for instructions that force an alignment... */
6975   /* None of these opcodes are bundle-able.  */
6976   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
6977     {
6978       int max_fill;
6979
6980       /* Remember the symbol that marks the end of the loop in the frag
6981          that marks the start of the loop.  This way we can easily find
6982          the end of the loop at the beginning, without adding special code
6983          to mark the loop instructions themselves.  */
6984       symbolS *target_sym = NULL;
6985       if (vinsn->slots[0].tok[1].X_op == O_symbol)
6986         target_sym = vinsn->slots[0].tok[1].X_add_symbol;
6987
6988       xtensa_set_frag_assembly_state (frag_now);
6989       frag_now->tc_frag_data.is_insn = TRUE;
6990
6991       max_fill = get_text_align_max_fill_size
6992         (get_text_align_power (xtensa_fetch_width),
6993          TRUE, frag_now->tc_frag_data.is_no_density);
6994
6995       if (use_transform ())
6996         frag_var (rs_machine_dependent, max_fill, max_fill,
6997                   RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
6998       else
6999         frag_var (rs_machine_dependent, 0, 0,
7000                   RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7001       xtensa_set_frag_assembly_state (frag_now);
7002     }
7003
7004   if (vinsn->slots[0].opcode == xtensa_entry_opcode
7005       && !vinsn->slots[0].is_specific_opcode)
7006     {
7007       xtensa_mark_literal_pool_location ();
7008       xtensa_move_labels (frag_now, 0);
7009       frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
7010     }
7011
7012   if (vinsn->num_slots == 1)
7013     {
7014       if (workaround_a0_b_retw && use_transform ())
7015         set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
7016                              is_register_writer (&vinsn->slots[0], "a", 0));
7017
7018       set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
7019                            is_bad_loopend_opcode (&vinsn->slots[0]));
7020     }
7021   else
7022     set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
7023
7024   insn_size = xtensa_format_length (isa, vinsn->format);
7025
7026   extra_space = relaxation_requirements (vinsn, &finish_frag);
7027
7028   /* vinsn_to_insnbuf will produce the error.  */
7029   if (vinsn->format != XTENSA_UNDEFINED)
7030     {
7031       f = frag_more (insn_size + extra_space);
7032       xtensa_set_frag_assembly_state (frag_now);
7033       frag_now->tc_frag_data.is_insn = TRUE;
7034     }
7035
7036   vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
7037   if (vinsn->format == XTENSA_UNDEFINED)
7038     return;
7039
7040   xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
7041
7042   if (debug_type == DEBUG_DWARF2 || loc_directive_seen)
7043     dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space),
7044                           &debug_line);
7045
7046   for (slot = 0; slot < vinsn->num_slots; slot++)
7047     {
7048       tinsn = &vinsn->slots[slot];
7049       frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7050       frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
7051       frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
7052       frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
7053       if (tinsn->literal_space != 0)
7054         xg_assemble_literal_space (tinsn->literal_space, slot);
7055       frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg;
7056
7057       if (tinsn->subtype == RELAX_NARROW)
7058         gas_assert (vinsn->num_slots == 1);
7059       if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
7060         is_jump = TRUE;
7061       if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
7062         is_branch = TRUE;
7063
7064       if (tinsn->subtype || tinsn->symbol || tinsn->offset
7065           || tinsn->literal_frag || is_jump || is_branch)
7066         finish_frag = TRUE;
7067     }
7068
7069   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7070     frag_now->tc_frag_data.is_specific_opcode = TRUE;
7071
7072   if (finish_frag)
7073     {
7074       frag_variant (rs_machine_dependent,
7075                     extra_space, extra_space, RELAX_SLOTS,
7076                     frag_now->fr_symbol, frag_now->fr_offset, f);
7077       xtensa_set_frag_assembly_state (frag_now);
7078     }
7079
7080   /* Special cases for loops:
7081      close_loop_end should be inserted AFTER short_loop.
7082      Make sure that CLOSE loops are processed BEFORE short_loops
7083      when converting them.  */
7084
7085   /* "short_loop": Add a NOP if the loop is < 4 bytes.  */
7086   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1
7087       && !vinsn->slots[0].is_specific_opcode)
7088     {
7089       if (workaround_short_loop && use_transform ())
7090         {
7091           maybe_has_short_loop = TRUE;
7092           frag_now->tc_frag_data.is_insn = TRUE;
7093           frag_var (rs_machine_dependent, 4, 4,
7094                     RELAX_ADD_NOP_IF_SHORT_LOOP,
7095                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7096           frag_now->tc_frag_data.is_insn = TRUE;
7097           frag_var (rs_machine_dependent, 4, 4,
7098                     RELAX_ADD_NOP_IF_SHORT_LOOP,
7099                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7100         }
7101
7102       /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7103          loop at least 12 bytes away from another loop's end.  */
7104       if (workaround_close_loop_end && use_transform ())
7105         {
7106           maybe_has_close_loop_end = TRUE;
7107           frag_now->tc_frag_data.is_insn = TRUE;
7108           frag_var (rs_machine_dependent, 12, 12,
7109                     RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
7110                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7111         }
7112     }
7113
7114   if (use_transform ())
7115     {
7116       if (is_jump)
7117         {
7118           gas_assert (finish_frag);
7119           frag_var (rs_machine_dependent,
7120                     UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
7121                     RELAX_UNREACHABLE,
7122                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7123           xtensa_set_frag_assembly_state (frag_now);
7124         }
7125       else if (is_branch && do_align_targets ())
7126         {
7127           gas_assert (finish_frag);
7128           frag_var (rs_machine_dependent,
7129                     UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
7130                     RELAX_MAYBE_UNREACHABLE,
7131                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7132           xtensa_set_frag_assembly_state (frag_now);
7133           frag_var (rs_machine_dependent,
7134                     0, 0,
7135                     RELAX_MAYBE_DESIRE_ALIGN,
7136                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7137           xtensa_set_frag_assembly_state (frag_now);
7138         }
7139     }
7140
7141   /* Now, if the original opcode was a call...  */
7142   if (do_align_targets ()
7143       && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7144     {
7145       float freq = get_subseg_total_freq (now_seg, now_subseg);
7146       frag_now->tc_frag_data.is_insn = TRUE;
7147       frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7148                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7149       xtensa_set_frag_assembly_state (frag_now);
7150     }
7151
7152   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7153     {
7154       frag_wane (frag_now);
7155       frag_new (0);
7156       xtensa_set_frag_assembly_state (frag_now);
7157     }
7158 }
7159
7160 \f
7161 /* xtensa_end and helper functions.  */
7162
7163 static void xtensa_cleanup_align_frags (void);
7164 static void xtensa_fix_target_frags (void);
7165 static void xtensa_mark_narrow_branches (void);
7166 static void xtensa_mark_zcl_first_insns (void);
7167 static void xtensa_mark_difference_of_two_symbols (void);
7168 static void xtensa_fix_a0_b_retw_frags (void);
7169 static void xtensa_fix_b_j_loop_end_frags (void);
7170 static void xtensa_fix_close_loop_end_frags (void);
7171 static void xtensa_fix_short_loop_frags (void);
7172 static void xtensa_sanity_check (void);
7173 static void xtensa_add_config_info (void);
7174
7175 void
7176 xtensa_end (void)
7177 {
7178   directive_balance ();
7179   xtensa_flush_pending_output ();
7180
7181   past_xtensa_end = TRUE;
7182
7183   xtensa_move_literals ();
7184
7185   xtensa_reorder_segments ();
7186   xtensa_cleanup_align_frags ();
7187   xtensa_fix_target_frags ();
7188   if (workaround_a0_b_retw && has_a0_b_retw)
7189     xtensa_fix_a0_b_retw_frags ();
7190   if (workaround_b_j_loop_end)
7191     xtensa_fix_b_j_loop_end_frags ();
7192
7193   /* "close_loop_end" should be processed BEFORE "short_loop".  */
7194   if (workaround_close_loop_end && maybe_has_close_loop_end)
7195     xtensa_fix_close_loop_end_frags ();
7196
7197   if (workaround_short_loop && maybe_has_short_loop)
7198     xtensa_fix_short_loop_frags ();
7199   if (align_targets)
7200     xtensa_mark_narrow_branches ();
7201   xtensa_mark_zcl_first_insns ();
7202
7203   xtensa_sanity_check ();
7204
7205   xtensa_add_config_info ();
7206 }
7207
7208
7209 static void
7210 xtensa_cleanup_align_frags (void)
7211 {
7212   frchainS *frchP;
7213   asection *s;
7214
7215   for (s = stdoutput->sections; s; s = s->next)
7216     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7217       {
7218         fragS *fragP;
7219         /* Walk over all of the fragments in a subsection.  */
7220         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7221           {
7222             if ((fragP->fr_type == rs_align
7223                  || fragP->fr_type == rs_align_code
7224                  || (fragP->fr_type == rs_machine_dependent
7225                      && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7226                          || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7227                 && fragP->fr_fix == 0)
7228               {
7229                 fragS *next = fragP->fr_next;
7230
7231                 while (next
7232                        && next->fr_fix == 0
7233                        && next->fr_type == rs_machine_dependent
7234                        && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7235                   {
7236                     frag_wane (next);
7237                     next = next->fr_next;
7238                   }
7239               }
7240             /* If we don't widen branch targets, then they
7241                will be easier to align.  */
7242             if (fragP->tc_frag_data.is_branch_target
7243                 && fragP->fr_opcode == fragP->fr_literal
7244                 && fragP->fr_type == rs_machine_dependent
7245                 && fragP->fr_subtype == RELAX_SLOTS
7246                 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7247               frag_wane (fragP);
7248             if (fragP->fr_type == rs_machine_dependent
7249                 && fragP->fr_subtype == RELAX_UNREACHABLE)
7250               fragP->tc_frag_data.is_unreachable = TRUE;
7251           }
7252       }
7253 }
7254
7255
7256 /* Re-process all of the fragments looking to convert all of the
7257    RELAX_DESIRE_ALIGN_IF_TARGET fragments.  If there is a branch
7258    target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7259    Otherwise, convert to a .fill 0.  */
7260
7261 static void
7262 xtensa_fix_target_frags (void)
7263 {
7264   frchainS *frchP;
7265   asection *s;
7266
7267   /* When this routine is called, all of the subsections are still intact
7268      so we walk over subsections instead of sections.  */
7269   for (s = stdoutput->sections; s; s = s->next)
7270     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7271       {
7272         fragS *fragP;
7273
7274         /* Walk over all of the fragments in a subsection.  */
7275         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7276           {
7277             if (fragP->fr_type == rs_machine_dependent
7278                 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7279               {
7280                 if (next_frag_is_branch_target (fragP))
7281                   fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7282                 else
7283                   frag_wane (fragP);
7284               }
7285           }
7286       }
7287 }
7288
7289
7290 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7291
7292 static void
7293 xtensa_mark_narrow_branches (void)
7294 {
7295   frchainS *frchP;
7296   asection *s;
7297
7298   for (s = stdoutput->sections; s; s = s->next)
7299     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7300       {
7301         fragS *fragP;
7302         /* Walk over all of the fragments in a subsection.  */
7303         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7304           {
7305             if (fragP->fr_type == rs_machine_dependent
7306                 && fragP->fr_subtype == RELAX_SLOTS
7307                 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7308               {
7309                 vliw_insn vinsn;
7310
7311                 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7312                 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7313
7314                 if (vinsn.num_slots == 1
7315                     && xtensa_opcode_is_branch (xtensa_default_isa,
7316                                                 vinsn.slots[0].opcode) == 1
7317                     && xg_get_single_size (vinsn.slots[0].opcode) == 2
7318                     && is_narrow_branch_guaranteed_in_range (fragP,
7319                                                              &vinsn.slots[0]))
7320                   {
7321                     fragP->fr_subtype = RELAX_SLOTS;
7322                     fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7323                     fragP->tc_frag_data.is_aligning_branch = 1;
7324                   }
7325               }
7326           }
7327       }
7328 }
7329
7330
7331 /* A branch is typically widened only when its target is out of
7332    range.  However, we would like to widen them to align a subsequent
7333    branch target when possible.
7334
7335    Because the branch relaxation code is so convoluted, the optimal solution
7336    (combining the two cases) is difficult to get right in all circumstances.
7337    We therefore go with an "almost as good" solution, where we only
7338    use for alignment narrow branches that definitely will not expand to a
7339    jump and a branch.  These functions find and mark these cases.  */
7340
7341 /* The range in bytes of BNEZ.N and BEQZ.N.  The target operand is encoded
7342    as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7343    We start counting beginning with the frag after the 2-byte branch, so the
7344    maximum offset is (4 - 2) + 63 = 65.  */
7345 #define MAX_IMMED6 65
7346
7347 static offsetT unrelaxed_frag_max_size (fragS *);
7348
7349 static bfd_boolean
7350 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
7351 {
7352   const expressionS *expr = &tinsn->tok[1];
7353   symbolS *symbolP = expr->X_add_symbol;
7354   offsetT max_distance = expr->X_add_number;
7355   fragS *target_frag;
7356
7357   if (expr->X_op != O_symbol)
7358     return FALSE;
7359
7360   target_frag = symbol_get_frag (symbolP);
7361
7362   max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7363   if (is_branch_jmp_to_next (tinsn, fragP))
7364     return FALSE;
7365
7366   /* The branch doesn't branch over it's own frag,
7367      but over the subsequent ones.  */
7368   fragP = fragP->fr_next;
7369   while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7370     {
7371       max_distance += unrelaxed_frag_max_size (fragP);
7372       fragP = fragP->fr_next;
7373     }
7374   if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7375     return TRUE;
7376   return FALSE;
7377 }
7378
7379
7380 static void
7381 xtensa_mark_zcl_first_insns (void)
7382 {
7383   frchainS *frchP;
7384   asection *s;
7385
7386   for (s = stdoutput->sections; s; s = s->next)
7387     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7388       {
7389         fragS *fragP;
7390         /* Walk over all of the fragments in a subsection.  */
7391         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7392           {
7393             if (fragP->fr_type == rs_machine_dependent
7394                 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7395                     || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7396               {
7397                 /* Find the loop frag.  */
7398                 fragS *targ_frag = next_non_empty_frag (fragP);
7399                 /* Find the first insn frag.  */
7400                 targ_frag = next_non_empty_frag (targ_frag);
7401
7402                 /* Of course, sometimes (mostly for toy test cases) a
7403                    zero-cost loop instruction is the last in a section.  */
7404                 if (targ_frag)
7405                   {
7406                     targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7407                     /* Do not widen a frag that is the first instruction of a
7408                        zero-cost loop.  It makes that loop harder to align.  */
7409                     if (targ_frag->fr_type == rs_machine_dependent
7410                         && targ_frag->fr_subtype == RELAX_SLOTS
7411                         && (targ_frag->tc_frag_data.slot_subtypes[0]
7412                             == RELAX_NARROW))
7413                       {
7414                         if (targ_frag->tc_frag_data.is_aligning_branch)
7415                           targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
7416                         else
7417                           {
7418                             frag_wane (targ_frag);
7419                             targ_frag->tc_frag_data.slot_subtypes[0] = 0;
7420                           }
7421                       }
7422                   }
7423                 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7424                   frag_wane (fragP);
7425               }
7426           }
7427       }
7428 }
7429
7430
7431 /* When a difference-of-symbols expression is encoded as a uleb128 or
7432    sleb128 value, the linker is unable to adjust that value to account for
7433    link-time relaxation.  Mark all the code between such symbols so that
7434    its size cannot be changed by linker relaxation.  */
7435
7436 static void
7437 xtensa_mark_difference_of_two_symbols (void)
7438 {
7439   symbolS *expr_sym;
7440
7441   for (expr_sym = expr_symbols; expr_sym;
7442        expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol)
7443     {
7444       expressionS *expr = symbol_get_value_expression (expr_sym);
7445
7446       if (expr->X_op == O_subtract)
7447         {
7448           symbolS *left = expr->X_add_symbol;
7449           symbolS *right = expr->X_op_symbol;
7450
7451           /* Difference of two symbols not in the same section
7452              are handled with relocations in the linker.  */
7453           if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right))
7454             {
7455               fragS *start;
7456               fragS *end;
7457               fragS *walk;
7458
7459               if (symbol_get_frag (left)->fr_address
7460                   <= symbol_get_frag (right)->fr_address)
7461                 {
7462                   start = symbol_get_frag (left);
7463                   end = symbol_get_frag (right);
7464                 }
7465               else
7466                 {
7467                   start = symbol_get_frag (right);
7468                   end = symbol_get_frag (left);
7469                 }
7470
7471               if (start->tc_frag_data.no_transform_end != NULL)
7472                 walk = start->tc_frag_data.no_transform_end;
7473               else
7474                 walk = start;
7475               do
7476                 {
7477                   walk->tc_frag_data.is_no_transform = 1;
7478                   walk = walk->fr_next;
7479                 }
7480               while (walk && walk->fr_address < end->fr_address);
7481
7482               start->tc_frag_data.no_transform_end = walk;
7483             }
7484         }
7485     }
7486 }
7487
7488
7489 /* Re-process all of the fragments looking to convert all of the
7490    RELAX_ADD_NOP_IF_A0_B_RETW.  If the next instruction is a
7491    conditional branch or a retw/retw.n, convert this frag to one that
7492    will generate a NOP.  In any case close it off with a .fill 0.  */
7493
7494 static bfd_boolean next_instrs_are_b_retw (fragS *);
7495
7496 static void
7497 xtensa_fix_a0_b_retw_frags (void)
7498 {
7499   frchainS *frchP;
7500   asection *s;
7501
7502   /* When this routine is called, all of the subsections are still intact
7503      so we walk over subsections instead of sections.  */
7504   for (s = stdoutput->sections; s; s = s->next)
7505     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7506       {
7507         fragS *fragP;
7508
7509         /* Walk over all of the fragments in a subsection.  */
7510         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7511           {
7512             if (fragP->fr_type == rs_machine_dependent
7513                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7514               {
7515                 if (next_instrs_are_b_retw (fragP))
7516                   {
7517                     if (fragP->tc_frag_data.is_no_transform)
7518                       as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7519                     else
7520                       relax_frag_add_nop (fragP);
7521                   }
7522                 frag_wane (fragP);
7523               }
7524           }
7525       }
7526 }
7527
7528
7529 static bfd_boolean
7530 next_instrs_are_b_retw (fragS *fragP)
7531 {
7532   xtensa_opcode opcode;
7533   xtensa_format fmt;
7534   const fragS *next_fragP = next_non_empty_frag (fragP);
7535   static xtensa_insnbuf insnbuf = NULL;
7536   static xtensa_insnbuf slotbuf = NULL;
7537   xtensa_isa isa = xtensa_default_isa;
7538   int offset = 0;
7539   int slot;
7540   bfd_boolean branch_seen = FALSE;
7541
7542   if (!insnbuf)
7543     {
7544       insnbuf = xtensa_insnbuf_alloc (isa);
7545       slotbuf = xtensa_insnbuf_alloc (isa);
7546     }
7547
7548   if (next_fragP == NULL)
7549     return FALSE;
7550
7551   /* Check for the conditional branch.  */
7552   xtensa_insnbuf_from_chars
7553     (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
7554   fmt = xtensa_format_decode (isa, insnbuf);
7555   if (fmt == XTENSA_UNDEFINED)
7556     return FALSE;
7557
7558   for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7559     {
7560       xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
7561       opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
7562
7563       branch_seen = (branch_seen
7564                      || xtensa_opcode_is_branch (isa, opcode) == 1);
7565     }
7566
7567   if (!branch_seen)
7568     return FALSE;
7569
7570   offset += xtensa_format_length (isa, fmt);
7571   if (offset == next_fragP->fr_fix)
7572     {
7573       next_fragP = next_non_empty_frag (next_fragP);
7574       offset = 0;
7575     }
7576
7577   if (next_fragP == NULL)
7578     return FALSE;
7579
7580   /* Check for the retw/retw.n.  */
7581   xtensa_insnbuf_from_chars
7582     (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
7583   fmt = xtensa_format_decode (isa, insnbuf);
7584
7585   /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7586      have no problems.  */
7587   if (fmt == XTENSA_UNDEFINED
7588       || xtensa_format_num_slots (isa, fmt) != 1)
7589     return FALSE;
7590
7591   xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
7592   opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
7593
7594   if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
7595     return TRUE;
7596
7597   return FALSE;
7598 }
7599
7600
7601 /* Re-process all of the fragments looking to convert all of the
7602    RELAX_ADD_NOP_IF_PRE_LOOP_END.  If there is one instruction and a
7603    loop end label, convert this frag to one that will generate a NOP.
7604    In any case close it off with a .fill 0.  */
7605
7606 static bfd_boolean next_instr_is_loop_end (fragS *);
7607
7608 static void
7609 xtensa_fix_b_j_loop_end_frags (void)
7610 {
7611   frchainS *frchP;
7612   asection *s;
7613
7614   /* When this routine is called, all of the subsections are still intact
7615      so we walk over subsections instead of sections.  */
7616   for (s = stdoutput->sections; s; s = s->next)
7617     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7618       {
7619         fragS *fragP;
7620
7621         /* Walk over all of the fragments in a subsection.  */
7622         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7623           {
7624             if (fragP->fr_type == rs_machine_dependent
7625                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
7626               {
7627                 if (next_instr_is_loop_end (fragP))
7628                   {
7629                     if (fragP->tc_frag_data.is_no_transform)
7630                       as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7631                     else
7632                       relax_frag_add_nop (fragP);
7633                   }
7634                 frag_wane (fragP);
7635               }
7636           }
7637       }
7638 }
7639
7640
7641 static bfd_boolean
7642 next_instr_is_loop_end (fragS *fragP)
7643 {
7644   const fragS *next_fragP;
7645
7646   if (next_frag_is_loop_target (fragP))
7647     return FALSE;
7648
7649   next_fragP = next_non_empty_frag (fragP);
7650   if (next_fragP == NULL)
7651     return FALSE;
7652
7653   if (!next_frag_is_loop_target (next_fragP))
7654     return FALSE;
7655
7656   /* If the size is >= 3 then there is more than one instruction here.
7657      The hardware bug will not fire.  */
7658   if (next_fragP->fr_fix > 3)
7659     return FALSE;
7660
7661   return TRUE;
7662 }
7663
7664
7665 /* Re-process all of the fragments looking to convert all of the
7666    RELAX_ADD_NOP_IF_CLOSE_LOOP_END.  If there is an loop end that is
7667    not MY loop's loop end within 12 bytes, add enough nops here to
7668    make it at least 12 bytes away.  In any case close it off with a
7669    .fill 0.  */
7670
7671 static offsetT min_bytes_to_other_loop_end
7672   (fragS *, fragS *, offsetT);
7673
7674 static void
7675 xtensa_fix_close_loop_end_frags (void)
7676 {
7677   frchainS *frchP;
7678   asection *s;
7679
7680   /* When this routine is called, all of the subsections are still intact
7681      so we walk over subsections instead of sections.  */
7682   for (s = stdoutput->sections; s; s = s->next)
7683     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7684       {
7685         fragS *fragP;
7686
7687         fragS *current_target = NULL;
7688
7689         /* Walk over all of the fragments in a subsection.  */
7690         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7691           {
7692             if (fragP->fr_type == rs_machine_dependent
7693                 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
7694                     || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
7695               current_target = symbol_get_frag (fragP->fr_symbol);
7696
7697             if (current_target
7698                 && fragP->fr_type == rs_machine_dependent
7699                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
7700               {
7701                 offsetT min_bytes;
7702                 int bytes_added = 0;
7703
7704 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7705                 /* Max out at 12.  */
7706                 min_bytes = min_bytes_to_other_loop_end
7707                   (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
7708
7709                 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
7710                   {
7711                     if (fragP->tc_frag_data.is_no_transform)
7712                       as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7713                     else
7714                       {
7715                         while (min_bytes + bytes_added
7716                                < REQUIRED_LOOP_DIVIDING_BYTES)
7717                           {
7718                             int length = 3;
7719
7720                             if (fragP->fr_var < length)
7721                               as_fatal (_("fr_var %lu < length %d"),
7722                                         (long) fragP->fr_var, length);
7723                             else
7724                               {
7725                                 assemble_nop (length,
7726                                               fragP->fr_literal + fragP->fr_fix);
7727                                 fragP->fr_fix += length;
7728                                 fragP->fr_var -= length;
7729                               }
7730                             bytes_added += length;
7731                           }
7732                       }
7733                   }
7734                 frag_wane (fragP);
7735               }
7736             gas_assert (fragP->fr_type != rs_machine_dependent
7737                     || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
7738           }
7739       }
7740 }
7741
7742
7743 static offsetT unrelaxed_frag_min_size (fragS *);
7744
7745 static offsetT
7746 min_bytes_to_other_loop_end (fragS *fragP,
7747                              fragS *current_target,
7748                              offsetT max_size)
7749 {
7750   offsetT offset = 0;
7751   fragS *current_fragP;
7752
7753   for (current_fragP = fragP;
7754        current_fragP;
7755        current_fragP = current_fragP->fr_next)
7756     {
7757       if (current_fragP->tc_frag_data.is_loop_target
7758           && current_fragP != current_target)
7759         return offset;
7760
7761       offset += unrelaxed_frag_min_size (current_fragP);
7762
7763       if (offset >= max_size)
7764         return max_size;
7765     }
7766   return max_size;
7767 }
7768
7769
7770 static offsetT
7771 unrelaxed_frag_min_size (fragS *fragP)
7772 {
7773   offsetT size = fragP->fr_fix;
7774
7775   /* Add fill size.  */
7776   if (fragP->fr_type == rs_fill)
7777     size += fragP->fr_offset;
7778
7779   return size;
7780 }
7781
7782
7783 static offsetT
7784 unrelaxed_frag_max_size (fragS *fragP)
7785 {
7786   offsetT size = fragP->fr_fix;
7787   switch (fragP->fr_type)
7788     {
7789     case 0:
7790       /* Empty frags created by the obstack allocation scheme
7791          end up with type 0.  */
7792       break;
7793     case rs_fill:
7794     case rs_org:
7795     case rs_space:
7796       size += fragP->fr_offset;
7797       break;
7798     case rs_align:
7799     case rs_align_code:
7800     case rs_align_test:
7801     case rs_leb128:
7802     case rs_cfa:
7803     case rs_dwarf2dbg:
7804       /* No further adjustments needed.  */
7805       break;
7806     case rs_machine_dependent:
7807       if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
7808         size += fragP->fr_var;
7809       break;
7810     default:
7811       /* We had darn well better know how big it is.  */
7812       gas_assert (0);
7813       break;
7814     }
7815
7816   return size;
7817 }
7818
7819
7820 /* Re-process all of the fragments looking to convert all
7821    of the RELAX_ADD_NOP_IF_SHORT_LOOP.  If:
7822
7823    A)
7824      1) the instruction size count to the loop end label
7825         is too short (<= 2 instructions),
7826      2) loop has a jump or branch in it
7827
7828    or B)
7829      1) workaround_all_short_loops is TRUE
7830      2) The generating loop was a  'loopgtz' or 'loopnez'
7831      3) the instruction size count to the loop end label is too short
7832         (<= 2 instructions)
7833    then convert this frag (and maybe the next one) to generate a NOP.
7834    In any case close it off with a .fill 0.  */
7835
7836 static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
7837 static bfd_boolean branch_before_loop_end (fragS *);
7838
7839 static void
7840 xtensa_fix_short_loop_frags (void)
7841 {
7842   frchainS *frchP;
7843   asection *s;
7844
7845   /* When this routine is called, all of the subsections are still intact
7846      so we walk over subsections instead of sections.  */
7847   for (s = stdoutput->sections; s; s = s->next)
7848     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7849       {
7850         fragS *fragP;
7851         fragS *current_target = NULL;
7852         xtensa_opcode current_opcode = XTENSA_UNDEFINED;
7853
7854         /* Walk over all of the fragments in a subsection.  */
7855         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7856           {
7857             if (fragP->fr_type == rs_machine_dependent
7858                 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
7859                     || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
7860               {
7861                 TInsn t_insn;
7862                 fragS *loop_frag = next_non_empty_frag (fragP);
7863                 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
7864                 current_target = symbol_get_frag (fragP->fr_symbol);
7865                 current_opcode = t_insn.opcode;
7866                 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa,
7867                                                current_opcode) == 1);
7868               }
7869
7870             if (fragP->fr_type == rs_machine_dependent
7871                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7872               {
7873                 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
7874                     && (branch_before_loop_end (fragP->fr_next)
7875                         || (workaround_all_short_loops
7876                             && current_opcode != XTENSA_UNDEFINED
7877                             && current_opcode != xtensa_loop_opcode)))
7878                   {
7879                     if (fragP->tc_frag_data.is_no_transform)
7880                       as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7881                     else
7882                       relax_frag_add_nop (fragP);
7883                   }
7884                 frag_wane (fragP);
7885               }
7886           }
7887       }
7888 }
7889
7890
7891 static int unrelaxed_frag_min_insn_count (fragS *);
7892
7893 static int
7894 count_insns_to_loop_end (fragS *base_fragP,
7895                          bfd_boolean count_relax_add,
7896                          int max_count)
7897 {
7898   fragS *fragP = NULL;
7899   int insn_count = 0;
7900
7901   fragP = base_fragP;
7902
7903   for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
7904     {
7905       insn_count += unrelaxed_frag_min_insn_count (fragP);
7906       if (insn_count >= max_count)
7907         return max_count;
7908
7909       if (count_relax_add)
7910         {
7911           if (fragP->fr_type == rs_machine_dependent
7912               && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7913             {
7914               /* In order to add the appropriate number of
7915                  NOPs, we count an instruction for downstream
7916                  occurrences.  */
7917               insn_count++;
7918               if (insn_count >= max_count)
7919                 return max_count;
7920             }
7921         }
7922     }
7923   return insn_count;
7924 }
7925
7926
7927 static int
7928 unrelaxed_frag_min_insn_count (fragS *fragP)
7929 {
7930   xtensa_isa isa = xtensa_default_isa;
7931   static xtensa_insnbuf insnbuf = NULL;
7932   int insn_count = 0;
7933   int offset = 0;
7934
7935   if (!fragP->tc_frag_data.is_insn)
7936     return insn_count;
7937
7938   if (!insnbuf)
7939     insnbuf = xtensa_insnbuf_alloc (isa);
7940
7941   /* Decode the fixed instructions.  */
7942   while (offset < fragP->fr_fix)
7943     {
7944       xtensa_format fmt;
7945
7946       xtensa_insnbuf_from_chars
7947         (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
7948       fmt = xtensa_format_decode (isa, insnbuf);
7949
7950       if (fmt == XTENSA_UNDEFINED)
7951         {
7952           as_fatal (_("undecodable instruction in instruction frag"));
7953           return insn_count;
7954         }
7955       offset += xtensa_format_length (isa, fmt);
7956       insn_count++;
7957     }
7958
7959   return insn_count;
7960 }
7961
7962
7963 static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
7964
7965 static bfd_boolean
7966 branch_before_loop_end (fragS *base_fragP)
7967 {
7968   fragS *fragP;
7969
7970   for (fragP = base_fragP;
7971        fragP && !fragP->tc_frag_data.is_loop_target;
7972        fragP = fragP->fr_next)
7973     {
7974       if (unrelaxed_frag_has_b_j (fragP))
7975         return TRUE;
7976     }
7977   return FALSE;
7978 }
7979
7980
7981 static bfd_boolean
7982 unrelaxed_frag_has_b_j (fragS *fragP)
7983 {
7984   static xtensa_insnbuf insnbuf = NULL;
7985   xtensa_isa isa = xtensa_default_isa;
7986   int offset = 0;
7987
7988   if (!fragP->tc_frag_data.is_insn)
7989     return FALSE;
7990
7991   if (!insnbuf)
7992     insnbuf = xtensa_insnbuf_alloc (isa);
7993
7994   /* Decode the fixed instructions.  */
7995   while (offset < fragP->fr_fix)
7996     {
7997       xtensa_format fmt;
7998       int slot;
7999
8000       xtensa_insnbuf_from_chars
8001         (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8002       fmt = xtensa_format_decode (isa, insnbuf);
8003       if (fmt == XTENSA_UNDEFINED)
8004         return FALSE;
8005
8006       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8007         {
8008           xtensa_opcode opcode =
8009             get_opcode_from_buf (fragP->fr_literal + offset, slot);
8010           if (xtensa_opcode_is_branch (isa, opcode) == 1
8011               || xtensa_opcode_is_jump (isa, opcode) == 1)
8012             return TRUE;
8013         }
8014       offset += xtensa_format_length (isa, fmt);
8015     }
8016   return FALSE;
8017 }
8018
8019
8020 /* Checks to be made after initial assembly but before relaxation.  */
8021
8022 static bfd_boolean is_empty_loop (const TInsn *, fragS *);
8023 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
8024
8025 static void
8026 xtensa_sanity_check (void)
8027 {
8028   char *file_name;
8029   unsigned line;
8030   frchainS *frchP;
8031   asection *s;
8032
8033   as_where (&file_name, &line);
8034   for (s = stdoutput->sections; s; s = s->next)
8035     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8036       {
8037         fragS *fragP;
8038
8039         /* Walk over all of the fragments in a subsection.  */
8040         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8041           {
8042             if (fragP->fr_type == rs_machine_dependent
8043                 && fragP->fr_subtype == RELAX_SLOTS
8044                 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8045               {
8046                 static xtensa_insnbuf insnbuf = NULL;
8047                 TInsn t_insn;
8048
8049                 if (fragP->fr_opcode != NULL)
8050                   {
8051                     if (!insnbuf)
8052                       insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
8053                     tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8054                     tinsn_immed_from_frag (&t_insn, fragP, 0);
8055
8056                     if (xtensa_opcode_is_loop (xtensa_default_isa,
8057                                                t_insn.opcode) == 1)
8058                       {
8059                         if (is_empty_loop (&t_insn, fragP))
8060                           {
8061                             new_logical_line (fragP->fr_file, fragP->fr_line);
8062                             as_bad (_("invalid empty loop"));
8063                           }
8064                         if (!is_local_forward_loop (&t_insn, fragP))
8065                           {
8066                             new_logical_line (fragP->fr_file, fragP->fr_line);
8067                             as_bad (_("loop target does not follow "
8068                                       "loop instruction in section"));
8069                           }
8070                       }
8071                   }
8072               }
8073           }
8074       }
8075   new_logical_line (file_name, line);
8076 }
8077
8078
8079 #define LOOP_IMMED_OPN 1
8080
8081 /* Return TRUE if the loop target is the next non-zero fragment.  */
8082
8083 static bfd_boolean
8084 is_empty_loop (const TInsn *insn, fragS *fragP)
8085 {
8086   const expressionS *expr;
8087   symbolS *symbolP;
8088   fragS *next_fragP;
8089
8090   if (insn->insn_type != ITYPE_INSN)
8091     return FALSE;
8092
8093   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8094     return FALSE;
8095
8096   if (insn->ntok <= LOOP_IMMED_OPN)
8097     return FALSE;
8098
8099   expr = &insn->tok[LOOP_IMMED_OPN];
8100
8101   if (expr->X_op != O_symbol)
8102     return FALSE;
8103
8104   symbolP = expr->X_add_symbol;
8105   if (!symbolP)
8106     return FALSE;
8107
8108   if (symbol_get_frag (symbolP) == NULL)
8109     return FALSE;
8110
8111   if (S_GET_VALUE (symbolP) != 0)
8112     return FALSE;
8113
8114   /* Walk through the zero-size fragments from this one.  If we find
8115      the target fragment, then this is a zero-size loop.  */
8116
8117   for (next_fragP = fragP->fr_next;
8118        next_fragP != NULL;
8119        next_fragP = next_fragP->fr_next)
8120     {
8121       if (next_fragP == symbol_get_frag (symbolP))
8122         return TRUE;
8123       if (next_fragP->fr_fix != 0)
8124         return FALSE;
8125     }
8126   return FALSE;
8127 }
8128
8129
8130 static bfd_boolean
8131 is_local_forward_loop (const TInsn *insn, fragS *fragP)
8132 {
8133   const expressionS *expr;
8134   symbolS *symbolP;
8135   fragS *next_fragP;
8136
8137   if (insn->insn_type != ITYPE_INSN)
8138     return FALSE;
8139
8140   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8141     return FALSE;
8142
8143   if (insn->ntok <= LOOP_IMMED_OPN)
8144     return FALSE;
8145
8146   expr = &insn->tok[LOOP_IMMED_OPN];
8147
8148   if (expr->X_op != O_symbol)
8149     return FALSE;
8150
8151   symbolP = expr->X_add_symbol;
8152   if (!symbolP)
8153     return FALSE;
8154
8155   if (symbol_get_frag (symbolP) == NULL)
8156     return FALSE;
8157
8158   /* Walk through fragments until we find the target.
8159      If we do not find the target, then this is an invalid loop.  */
8160
8161   for (next_fragP = fragP->fr_next;
8162        next_fragP != NULL;
8163        next_fragP = next_fragP->fr_next)
8164     {
8165       if (next_fragP == symbol_get_frag (symbolP))
8166         return TRUE;
8167     }
8168
8169   return FALSE;
8170 }
8171
8172
8173 #define XTINFO_NAME "Xtensa_Info"
8174 #define XTINFO_NAMESZ 12
8175 #define XTINFO_TYPE 1
8176
8177 static void
8178 xtensa_add_config_info (void)
8179 {
8180   asection *info_sec;
8181   char *data, *p;
8182   int sz;
8183
8184   info_sec = subseg_new (".xtensa.info", 0);
8185   bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
8186
8187   data = xmalloc (100);
8188   sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8189            XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI);
8190   sz = strlen (data) + 1;
8191
8192   /* Add enough null terminators to pad to a word boundary.  */
8193   do
8194     data[sz++] = 0;
8195   while ((sz & 3) != 0);
8196
8197   /* Follow the standard note section layout:
8198      First write the length of the name string.  */
8199   p = frag_more (4);
8200   md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4);
8201
8202   /* Next comes the length of the "descriptor", i.e., the actual data.  */
8203   p = frag_more (4);
8204   md_number_to_chars (p, (valueT) sz, 4);
8205
8206   /* Write the note type.  */
8207   p = frag_more (4);
8208   md_number_to_chars (p, (valueT) XTINFO_TYPE, 4);
8209
8210   /* Write the name field.  */
8211   p = frag_more (XTINFO_NAMESZ);
8212   memcpy (p, XTINFO_NAME, XTINFO_NAMESZ);
8213
8214   /* Finally, write the descriptor.  */
8215   p = frag_more (sz);
8216   memcpy (p, data, sz);
8217
8218   free (data);
8219 }
8220
8221 \f
8222 /* Alignment Functions.  */
8223
8224 static int
8225 get_text_align_power (unsigned target_size)
8226 {
8227   if (target_size <= 4)
8228     return 2;
8229   gas_assert (target_size == 8);
8230   return 3;
8231 }
8232
8233
8234 static int
8235 get_text_align_max_fill_size (int align_pow,
8236                               bfd_boolean use_nops,
8237                               bfd_boolean use_no_density)
8238 {
8239   if (!use_nops)
8240     return (1 << align_pow);
8241   if (use_no_density)
8242     return 3 * (1 << align_pow);
8243
8244   return 1 + (1 << align_pow);
8245 }
8246
8247
8248 /* Calculate the minimum bytes of fill needed at "address" to align a
8249    target instruction of size "target_size" so that it does not cross a
8250    power-of-two boundary specified by "align_pow".  If "use_nops" is FALSE,
8251    the fill can be an arbitrary number of bytes.  Otherwise, the space must
8252    be filled by NOP instructions.  */
8253
8254 static int
8255 get_text_align_fill_size (addressT address,
8256                           int align_pow,
8257                           int target_size,
8258                           bfd_boolean use_nops,
8259                           bfd_boolean use_no_density)
8260 {
8261   addressT alignment, fill, fill_limit, fill_step;
8262   bfd_boolean skip_one = FALSE;
8263
8264   alignment = (1 << align_pow);
8265   gas_assert (target_size > 0 && alignment >= (addressT) target_size);
8266
8267   if (!use_nops)
8268     {
8269       fill_limit = alignment;
8270       fill_step = 1;
8271     }
8272   else if (!use_no_density)
8273     {
8274       /* Combine 2- and 3-byte NOPs to fill anything larger than one.  */
8275       fill_limit = alignment * 2;
8276       fill_step = 1;
8277       skip_one = TRUE;
8278     }
8279   else
8280     {
8281       /* Fill with 3-byte NOPs -- can only fill multiples of 3.  */
8282       fill_limit = alignment * 3;
8283       fill_step = 3;
8284     }
8285
8286   /* Try all fill sizes until finding one that works.  */
8287   for (fill = 0; fill < fill_limit; fill += fill_step)
8288     {
8289       if (skip_one && fill == 1)
8290         continue;
8291       if ((address + fill) >> align_pow
8292           == (address + fill + target_size - 1) >> align_pow)
8293         return fill;
8294     }
8295   gas_assert (0);
8296   return 0;
8297 }
8298
8299
8300 static int
8301 branch_align_power (segT sec)
8302 {
8303   /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8304      is aligned to at least an 8-byte boundary, then a branch target need
8305      only fit within an 8-byte aligned block of memory to avoid a stall.
8306      Otherwise, try to fit branch targets within 4-byte aligned blocks
8307      (which may be insufficient, e.g., if the section has no alignment, but
8308      it's good enough).  */
8309   if (xtensa_fetch_width == 8)
8310     {
8311       if (get_recorded_alignment (sec) >= 3)
8312         return 3;
8313     }
8314   else
8315     gas_assert (xtensa_fetch_width == 4);
8316
8317   return 2;
8318 }
8319
8320
8321 /* This will assert if it is not possible.  */
8322
8323 static int
8324 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
8325 {
8326   int count = 0;
8327
8328   if (use_no_density)
8329     {
8330       gas_assert (fill_size % 3 == 0);
8331       return (fill_size / 3);
8332     }
8333
8334   gas_assert (fill_size != 1);  /* Bad argument.  */
8335
8336   while (fill_size > 1)
8337     {
8338       int insn_size = 3;
8339       if (fill_size == 2 || fill_size == 4)
8340         insn_size = 2;
8341       fill_size -= insn_size;
8342       count++;
8343     }
8344   gas_assert (fill_size != 1);  /* Bad algorithm.  */
8345   return count;
8346 }
8347
8348
8349 static int
8350 get_text_align_nth_nop_size (offsetT fill_size,
8351                              int n,
8352                              bfd_boolean use_no_density)
8353 {
8354   int count = 0;
8355
8356   if (use_no_density)
8357     return 3;
8358
8359   gas_assert (fill_size != 1);  /* Bad argument.  */
8360
8361   while (fill_size > 1)
8362     {
8363       int insn_size = 3;
8364       if (fill_size == 2 || fill_size == 4)
8365         insn_size = 2;
8366       fill_size -= insn_size;
8367       count++;
8368       if (n + 1 == count)
8369         return insn_size;
8370     }
8371   gas_assert (0);
8372   return 0;
8373 }
8374
8375
8376 /* For the given fragment, find the appropriate address
8377    for it to begin at if we are using NOPs to align it.  */
8378
8379 static addressT
8380 get_noop_aligned_address (fragS *fragP, addressT address)
8381 {
8382   /* The rule is: get next fragment's FIRST instruction.  Find
8383      the smallest number of bytes that need to be added to
8384      ensure that the next fragment's FIRST instruction will fit
8385      in a single word.
8386
8387      E.G.,   2 bytes : 0, 1, 2 mod 4
8388              3 bytes: 0, 1 mod 4
8389
8390      If the FIRST instruction MIGHT be relaxed,
8391      assume that it will become a 3-byte instruction.
8392
8393      Note again here that LOOP instructions are not bundleable,
8394      and this relaxation only applies to LOOP opcodes.  */
8395
8396   int fill_size = 0;
8397   int first_insn_size;
8398   int loop_insn_size;
8399   addressT pre_opcode_bytes;
8400   int align_power;
8401   fragS *first_insn;
8402   xtensa_opcode opcode;
8403   bfd_boolean is_loop;
8404
8405   gas_assert (fragP->fr_type == rs_machine_dependent);
8406   gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
8407
8408   /* Find the loop frag.  */
8409   first_insn = next_non_empty_frag (fragP);
8410   /* Now find the first insn frag.  */
8411   first_insn = next_non_empty_frag (first_insn);
8412
8413   is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8414   gas_assert (is_loop);
8415   loop_insn_size = xg_get_single_size (opcode);
8416
8417   pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8418   pre_opcode_bytes += loop_insn_size;
8419
8420   /* For loops, the alignment depends on the size of the
8421      instruction following the loop, not the LOOP instruction.  */
8422
8423   if (first_insn == NULL)
8424     first_insn_size = xtensa_fetch_width;
8425   else
8426     first_insn_size = get_loop_align_size (frag_format_size (first_insn));
8427
8428   /* If it was 8, then we'll need a larger alignment for the section.  */
8429   align_power = get_text_align_power (first_insn_size);
8430   record_alignment (now_seg, align_power);
8431
8432   fill_size = get_text_align_fill_size
8433     (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
8434      fragP->tc_frag_data.is_no_density);
8435
8436   return address + fill_size;
8437 }
8438
8439
8440 /* 3 mechanisms for relaxing an alignment:
8441
8442    Align to a power of 2.
8443    Align so the next fragment's instruction does not cross a word boundary.
8444    Align the current instruction so that if the next instruction
8445        were 3 bytes, it would not cross a word boundary.
8446
8447    We can align with:
8448
8449    zeros    - This is easy; always insert zeros.
8450    nops     - 3-byte and 2-byte instructions
8451               2 - 2-byte nop
8452               3 - 3-byte nop
8453               4 - 2 2-byte nops
8454               >=5 : 3-byte instruction + fn (n-3)
8455    widening - widen previous instructions.  */
8456
8457 static offsetT
8458 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
8459 {
8460   addressT target_address, loop_insn_offset;
8461   int target_size;
8462   xtensa_opcode loop_opcode;
8463   bfd_boolean is_loop;
8464   int align_power;
8465   offsetT opt_diff;
8466   offsetT branch_align;
8467   fragS *loop_frag;
8468
8469   gas_assert (fragP->fr_type == rs_machine_dependent);
8470   switch (fragP->fr_subtype)
8471     {
8472     case RELAX_DESIRE_ALIGN:
8473       target_size = next_frag_format_size (fragP);
8474       if (target_size == XTENSA_UNDEFINED)
8475         target_size = 3;
8476       align_power = branch_align_power (now_seg);
8477       branch_align = 1 << align_power;
8478       /* Don't count on the section alignment being as large as the target.  */
8479       if (target_size > branch_align)
8480         target_size = branch_align;
8481       opt_diff = get_text_align_fill_size (address, align_power,
8482                                            target_size, FALSE, FALSE);
8483
8484       *max_diff = (opt_diff + branch_align
8485                    - (target_size + ((address + opt_diff) % branch_align)));
8486       gas_assert (*max_diff >= opt_diff);
8487       return opt_diff;
8488
8489     case RELAX_ALIGN_NEXT_OPCODE:
8490       /* The next non-empty frag after this one holds the LOOP instruction
8491          that needs to be aligned.  The required alignment depends on the
8492          size of the next non-empty frag after the loop frag, i.e., the
8493          first instruction in the loop.  */
8494       loop_frag = next_non_empty_frag (fragP);
8495       target_size = get_loop_align_size (next_frag_format_size (loop_frag));
8496       loop_insn_offset = 0;
8497       is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8498       gas_assert (is_loop);
8499
8500       /* If the loop has been expanded then the LOOP instruction
8501          could be at an offset from this fragment.  */
8502       if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED)
8503         loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8504
8505       /* In an ideal world, which is what we are shooting for here,
8506          we wouldn't need to use any NOPs immediately prior to the
8507          LOOP instruction.  If this approach fails, relax_frag_loop_align
8508          will call get_noop_aligned_address.  */
8509       target_address =
8510         address + loop_insn_offset + xg_get_single_size (loop_opcode);
8511       align_power = get_text_align_power (target_size);
8512       opt_diff = get_text_align_fill_size (target_address, align_power,
8513                                            target_size, FALSE, FALSE);
8514
8515       *max_diff = xtensa_fetch_width
8516         - ((target_address + opt_diff) % xtensa_fetch_width)
8517         - target_size + opt_diff;
8518       gas_assert (*max_diff >= opt_diff);
8519       return opt_diff;
8520
8521     default:
8522       break;
8523     }
8524   gas_assert (0);
8525   return 0;
8526 }
8527
8528 \f
8529 /* md_relax_frag Hook and Helper Functions.  */
8530
8531 static long relax_frag_loop_align (fragS *, long);
8532 static long relax_frag_for_align (fragS *, long);
8533 static long relax_frag_immed
8534   (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8535
8536
8537 /* Return the number of bytes added to this fragment, given that the
8538    input has been stretched already by "stretch".  */
8539
8540 long
8541 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
8542 {
8543   xtensa_isa isa = xtensa_default_isa;
8544   int unreported = fragP->tc_frag_data.unreported_expansion;
8545   long new_stretch = 0;
8546   char *file_name;
8547   unsigned line;
8548   int lit_size;
8549   static xtensa_insnbuf vbuf = NULL;
8550   int slot, num_slots;
8551   xtensa_format fmt;
8552
8553   as_where (&file_name, &line);
8554   new_logical_line (fragP->fr_file, fragP->fr_line);
8555
8556   fragP->tc_frag_data.unreported_expansion = 0;
8557
8558   switch (fragP->fr_subtype)
8559     {
8560     case RELAX_ALIGN_NEXT_OPCODE:
8561       /* Always convert.  */
8562       if (fragP->tc_frag_data.relax_seen)
8563         new_stretch = relax_frag_loop_align (fragP, stretch);
8564       break;
8565
8566     case RELAX_LOOP_END:
8567       /* Do nothing.  */
8568       break;
8569
8570     case RELAX_LOOP_END_ADD_NOP:
8571       /* Add a NOP and switch to .fill 0.  */
8572       new_stretch = relax_frag_add_nop (fragP);
8573       frag_wane (fragP);
8574       break;
8575
8576     case RELAX_DESIRE_ALIGN:
8577       /* Do nothing. The narrowing before this frag will either align
8578          it or not.  */
8579       break;
8580
8581     case RELAX_LITERAL:
8582     case RELAX_LITERAL_FINAL:
8583       return 0;
8584
8585     case RELAX_LITERAL_NR:
8586       lit_size = 4;
8587       fragP->fr_subtype = RELAX_LITERAL_FINAL;
8588       gas_assert (unreported == lit_size);
8589       memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
8590       fragP->fr_var -= lit_size;
8591       fragP->fr_fix += lit_size;
8592       new_stretch = 4;
8593       break;
8594
8595     case RELAX_SLOTS:
8596       if (vbuf == NULL)
8597         vbuf = xtensa_insnbuf_alloc (isa);
8598
8599       xtensa_insnbuf_from_chars
8600         (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
8601       fmt = xtensa_format_decode (isa, vbuf);
8602       num_slots = xtensa_format_num_slots (isa, fmt);
8603
8604       for (slot = 0; slot < num_slots; slot++)
8605         {
8606           switch (fragP->tc_frag_data.slot_subtypes[slot])
8607             {
8608             case RELAX_NARROW:
8609               if (fragP->tc_frag_data.relax_seen)
8610                 new_stretch += relax_frag_for_align (fragP, stretch);
8611               break;
8612
8613             case RELAX_IMMED:
8614             case RELAX_IMMED_STEP1:
8615             case RELAX_IMMED_STEP2:
8616             case RELAX_IMMED_STEP3:
8617               /* Place the immediate.  */
8618               new_stretch += relax_frag_immed
8619                 (now_seg, fragP, stretch,
8620                  fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8621                  fmt, slot, stretched_p, FALSE);
8622               break;
8623
8624             default:
8625               /* This is OK; see the note in xg_assemble_vliw_tokens.  */
8626               break;
8627             }
8628         }
8629       break;
8630
8631     case RELAX_LITERAL_POOL_BEGIN:
8632     case RELAX_LITERAL_POOL_END:
8633     case RELAX_MAYBE_UNREACHABLE:
8634     case RELAX_MAYBE_DESIRE_ALIGN:
8635       /* No relaxation required.  */
8636       break;
8637
8638     case RELAX_FILL_NOP:
8639     case RELAX_UNREACHABLE:
8640       if (fragP->tc_frag_data.relax_seen)
8641         new_stretch += relax_frag_for_align (fragP, stretch);
8642       break;
8643
8644     default:
8645       as_bad (_("bad relaxation state"));
8646     }
8647
8648   /* Tell gas we need another relaxation pass.  */
8649   if (! fragP->tc_frag_data.relax_seen)
8650     {
8651       fragP->tc_frag_data.relax_seen = TRUE;
8652       *stretched_p = 1;
8653     }
8654
8655   new_logical_line (file_name, line);
8656   return new_stretch;
8657 }
8658
8659
8660 static long
8661 relax_frag_loop_align (fragS *fragP, long stretch)
8662 {
8663   addressT old_address, old_next_address, old_size;
8664   addressT new_address, new_next_address, new_size;
8665   addressT growth;
8666
8667   /* All the frags with relax_frag_for_alignment prior to this one in the
8668      section have been done, hopefully eliminating the need for a NOP here.
8669      But, this will put it in if necessary.  */
8670
8671   /* Calculate the old address of this fragment and the next fragment.  */
8672   old_address = fragP->fr_address - stretch;
8673   old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
8674                       fragP->tc_frag_data.text_expansion[0]);
8675   old_size = old_next_address - old_address;
8676
8677   /* Calculate the new address of this fragment and the next fragment.  */
8678   new_address = fragP->fr_address;
8679   new_next_address =
8680     get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
8681   new_size = new_next_address - new_address;
8682
8683   growth = new_size - old_size;
8684
8685   /* Fix up the text_expansion field and return the new growth.  */
8686   fragP->tc_frag_data.text_expansion[0] += growth;
8687   return growth;
8688 }
8689
8690
8691 /* Add a NOP instruction.  */
8692
8693 static long
8694 relax_frag_add_nop (fragS *fragP)
8695 {
8696   char *nop_buf = fragP->fr_literal + fragP->fr_fix;
8697   int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
8698   assemble_nop (length, nop_buf);
8699   fragP->tc_frag_data.is_insn = TRUE;
8700
8701   if (fragP->fr_var < length)
8702     {
8703       as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
8704       return 0;
8705     }
8706
8707   fragP->fr_fix += length;
8708   fragP->fr_var -= length;
8709   return length;
8710 }
8711
8712
8713 static long future_alignment_required (fragS *, long);
8714
8715 static long
8716 relax_frag_for_align (fragS *fragP, long stretch)
8717 {
8718   /* Overview of the relaxation procedure for alignment:
8719      We can widen with NOPs or by widening instructions or by filling
8720      bytes after jump instructions.  Find the opportune places and widen
8721      them if necessary.  */
8722
8723   long stretch_me;
8724   long diff;
8725
8726   gas_assert (fragP->fr_subtype == RELAX_FILL_NOP
8727           || fragP->fr_subtype == RELAX_UNREACHABLE
8728           || (fragP->fr_subtype == RELAX_SLOTS
8729               && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
8730
8731   stretch_me = future_alignment_required (fragP, stretch);
8732   diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
8733   if (diff == 0)
8734     return 0;
8735
8736   if (diff < 0)
8737     {
8738       /* We expanded on a previous pass.  Can we shrink now?  */
8739       long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
8740       if (shrink <= stretch && stretch > 0)
8741         {
8742           fragP->tc_frag_data.text_expansion[0] = stretch_me;
8743           return -shrink;
8744         }
8745       return 0;
8746     }
8747
8748   /* Below here, diff > 0.  */
8749   fragP->tc_frag_data.text_expansion[0] = stretch_me;
8750
8751   return diff;
8752 }
8753
8754
8755 /* Return the address of the next frag that should be aligned.
8756
8757    By "address" we mean the address it _would_ be at if there
8758    is no action taken to align it between here and the target frag.
8759    In other words, if no narrows and no fill nops are used between
8760    here and the frag to align, _even_if_ some of the frags we use
8761    to align targets have already expanded on a previous relaxation
8762    pass.
8763
8764    Also, count each frag that may be used to help align the target.
8765
8766    Return 0 if there are no frags left in the chain that need to be
8767    aligned.  */
8768
8769 static addressT
8770 find_address_of_next_align_frag (fragS **fragPP,
8771                                  int *wide_nops,
8772                                  int *narrow_nops,
8773                                  int *widens,
8774                                  bfd_boolean *paddable)
8775 {
8776   fragS *fragP = *fragPP;
8777   addressT address = fragP->fr_address;
8778
8779   /* Do not reset the counts to 0.  */
8780
8781   while (fragP)
8782     {
8783       /* Limit this to a small search.  */
8784       if (*widens >= (int) xtensa_fetch_width)
8785         {
8786           *fragPP = fragP;
8787           return 0;
8788         }
8789       address += fragP->fr_fix;
8790
8791       if (fragP->fr_type == rs_fill)
8792         address += fragP->fr_offset * fragP->fr_var;
8793       else if (fragP->fr_type == rs_machine_dependent)
8794         {
8795           switch (fragP->fr_subtype)
8796             {
8797             case RELAX_UNREACHABLE:
8798               *paddable = TRUE;
8799               break;
8800
8801             case RELAX_FILL_NOP:
8802               (*wide_nops)++;
8803               if (!fragP->tc_frag_data.is_no_density)
8804                 (*narrow_nops)++;
8805               break;
8806
8807             case RELAX_SLOTS:
8808               if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8809                 {
8810                   (*widens)++;
8811                   break;
8812                 }
8813               address += total_frag_text_expansion (fragP);;
8814               break;
8815
8816             case RELAX_IMMED:
8817               address += fragP->tc_frag_data.text_expansion[0];
8818               break;
8819
8820             case RELAX_ALIGN_NEXT_OPCODE:
8821             case RELAX_DESIRE_ALIGN:
8822               *fragPP = fragP;
8823               return address;
8824
8825             case RELAX_MAYBE_UNREACHABLE:
8826             case RELAX_MAYBE_DESIRE_ALIGN:
8827               /* Do nothing.  */
8828               break;
8829
8830             default:
8831               /* Just punt if we don't know the type.  */
8832               *fragPP = fragP;
8833               return 0;
8834             }
8835         }
8836       else
8837         {
8838           /* Just punt if we don't know the type.  */
8839           *fragPP = fragP;
8840           return 0;
8841         }
8842       fragP = fragP->fr_next;
8843     }
8844
8845   *fragPP = fragP;
8846   return 0;
8847 }
8848
8849
8850 static long bytes_to_stretch (fragS *, int, int, int, int);
8851
8852 static long
8853 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
8854 {
8855   fragS *this_frag = fragP;
8856   long address;
8857   int num_widens = 0;
8858   int wide_nops = 0;
8859   int narrow_nops = 0;
8860   bfd_boolean paddable = FALSE;
8861   offsetT local_opt_diff;
8862   offsetT opt_diff;
8863   offsetT max_diff;
8864   int stretch_amount = 0;
8865   int local_stretch_amount;
8866   int global_stretch_amount;
8867
8868   address = find_address_of_next_align_frag
8869     (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
8870
8871   if (!address)
8872     {
8873       if (this_frag->tc_frag_data.is_aligning_branch)
8874         this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
8875       else
8876         frag_wane (this_frag);
8877     }
8878   else
8879     {
8880       local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
8881       opt_diff = local_opt_diff;
8882       gas_assert (opt_diff >= 0);
8883       gas_assert (max_diff >= opt_diff);
8884       if (max_diff == 0)
8885         return 0;
8886
8887       if (fragP)
8888         fragP = fragP->fr_next;
8889
8890       while (fragP && opt_diff < max_diff && address)
8891         {
8892           /* We only use these to determine if we can exit early
8893              because there will be plenty of ways to align future
8894              align frags.  */
8895           int glob_widens = 0;
8896           int dnn = 0;
8897           int dw = 0;
8898           bfd_boolean glob_pad = 0;
8899           address = find_address_of_next_align_frag
8900             (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
8901           /* If there is a padable portion, then skip.  */
8902           if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
8903             address = 0;
8904
8905           if (address)
8906             {
8907               offsetT next_m_diff;
8908               offsetT next_o_diff;
8909
8910               /* Downrange frags haven't had stretch added to them yet.  */
8911               address += stretch;
8912
8913               /* The address also includes any text expansion from this
8914                  frag in a previous pass, but we don't want that.  */
8915               address -= this_frag->tc_frag_data.text_expansion[0];
8916
8917               /* Assume we are going to move at least opt_diff.  In
8918                  reality, we might not be able to, but assuming that
8919                  we will helps catch cases where moving opt_diff pushes
8920                  the next target from aligned to unaligned.  */
8921               address += opt_diff;
8922
8923               next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
8924
8925               /* Now cleanup for the adjustments to address.  */
8926               next_o_diff += opt_diff;
8927               next_m_diff += opt_diff;
8928               if (next_o_diff <= max_diff && next_o_diff > opt_diff)
8929                 opt_diff = next_o_diff;
8930               if (next_m_diff < max_diff)
8931                 max_diff = next_m_diff;
8932               fragP = fragP->fr_next;
8933             }
8934         }
8935
8936       /* If there are enough wideners in between, do it.  */
8937       if (paddable)
8938         {
8939           if (this_frag->fr_subtype == RELAX_UNREACHABLE)
8940             {
8941               gas_assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
8942               return opt_diff;
8943             }
8944           return 0;
8945         }
8946       local_stretch_amount
8947         = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8948                             num_widens, local_opt_diff);
8949       global_stretch_amount
8950         = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8951                             num_widens, opt_diff);
8952       /* If the condition below is true, then the frag couldn't
8953          stretch the correct amount for the global case, so we just
8954          optimize locally.  We'll rely on the subsequent frags to get
8955          the correct alignment in the global case.  */
8956       if (global_stretch_amount < local_stretch_amount)
8957         stretch_amount = local_stretch_amount;
8958       else
8959         stretch_amount = global_stretch_amount;
8960
8961       if (this_frag->fr_subtype == RELAX_SLOTS
8962           && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8963         gas_assert (stretch_amount <= 1);
8964       else if (this_frag->fr_subtype == RELAX_FILL_NOP)
8965         {
8966           if (this_frag->tc_frag_data.is_no_density)
8967             gas_assert (stretch_amount == 3 || stretch_amount == 0);
8968           else
8969             gas_assert (stretch_amount <= 3);
8970         }
8971     }
8972   return stretch_amount;
8973 }
8974
8975
8976 /* The idea: widen everything you can to get a target or loop aligned,
8977    then start using NOPs.
8978
8979    When we must have a NOP, here is a table of how we decide
8980    (so you don't have to fight through the control flow below):
8981
8982    wide_nops   = the number of wide NOPs available for aligning
8983    narrow_nops = the number of narrow NOPs available for aligning
8984                  (a subset of wide_nops)
8985    widens      = the number of narrow instructions that should be widened
8986
8987    Desired   wide   narrow
8988    Diff      nop    nop      widens
8989    1           0      0         1
8990    2           0      1         0
8991    3a          1      0         0
8992     b          0      1         1 (case 3a makes this case unnecessary)
8993    4a          1      0         1
8994     b          0      2         0
8995     c          0      1         2 (case 4a makes this case unnecessary)
8996    5a          1      0         2
8997     b          1      1         0
8998     c          0      2         1 (case 5b makes this case unnecessary)
8999    6a          2      0         0
9000     b          1      0         3
9001     c          0      1         4 (case 6b makes this case unnecessary)
9002     d          1      1         1 (case 6a makes this case unnecessary)
9003     e          0      2         2 (case 6a makes this case unnecessary)
9004     f          0      3         0 (case 6a makes this case unnecessary)
9005    7a          1      0         4
9006     b          2      0         1
9007     c          1      1         2 (case 7b makes this case unnecessary)
9008     d          0      1         5 (case 7a makes this case unnecessary)
9009     e          0      2         3 (case 7b makes this case unnecessary)
9010     f          0      3         1 (case 7b makes this case unnecessary)
9011     g          1      2         1 (case 7b makes this case unnecessary)
9012 */
9013
9014 static long
9015 bytes_to_stretch (fragS *this_frag,
9016                   int wide_nops,
9017                   int narrow_nops,
9018                   int num_widens,
9019                   int desired_diff)
9020 {
9021   int bytes_short = desired_diff - num_widens;
9022
9023   gas_assert (desired_diff >= 0 && desired_diff < 8);
9024   if (desired_diff == 0)
9025     return 0;
9026
9027   gas_assert (wide_nops > 0 || num_widens > 0);
9028
9029   /* Always prefer widening to NOP-filling.  */
9030   if (bytes_short < 0)
9031     {
9032       /* There are enough RELAX_NARROW frags after this one
9033          to align the target without widening this frag in any way.  */
9034       return 0;
9035     }
9036
9037   if (bytes_short == 0)
9038     {
9039       /* Widen every narrow between here and the align target
9040          and the align target will be properly aligned.  */
9041       if (this_frag->fr_subtype == RELAX_FILL_NOP)
9042         return 0;
9043       else
9044         return 1;
9045     }
9046
9047   /* From here we will need at least one NOP to get an alignment.
9048      However, we may not be able to align at all, in which case,
9049      don't widen.  */
9050   if (this_frag->fr_subtype == RELAX_FILL_NOP)
9051     {
9052       switch (desired_diff)
9053         {
9054         case 1:
9055           return 0;
9056         case 2:
9057           if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
9058             return 2; /* case 2 */
9059           return 0;
9060         case 3:
9061           if (wide_nops > 1)
9062             return 0;
9063           else
9064             return 3; /* case 3a */
9065         case 4:
9066           if (num_widens >= 1 && wide_nops == 1)
9067             return 3; /* case 4a */
9068           if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
9069             return 2; /* case 4b */
9070           return 0;
9071         case 5:
9072           if (num_widens >= 2 && wide_nops == 1)
9073             return 3; /* case 5a */
9074           /* We will need two nops.  Are there enough nops
9075              between here and the align target?  */
9076           if (wide_nops < 2 || narrow_nops == 0)
9077             return 0;
9078           /* Are there other nops closer that can serve instead?  */
9079           if (wide_nops > 2 && narrow_nops > 1)
9080             return 0;
9081           /* Take the density one first, because there might not be
9082              another density one available.  */
9083           if (!this_frag->tc_frag_data.is_no_density)
9084             return 2; /* case 5b narrow */
9085           else
9086             return 3; /* case 5b wide */
9087           return 0;
9088         case 6:
9089           if (wide_nops == 2)
9090             return 3; /* case 6a */
9091           else if (num_widens >= 3 && wide_nops == 1)
9092             return 3; /* case 6b */
9093           return 0;
9094         case 7:
9095           if (wide_nops == 1 && num_widens >= 4)
9096             return 3; /* case 7a */
9097           else if (wide_nops == 2 && num_widens >= 1)
9098             return 3; /* case 7b */
9099           return 0;
9100         default:
9101           gas_assert (0);
9102         }
9103     }
9104   else
9105     {
9106       /* We will need a NOP no matter what, but should we widen
9107          this instruction to help?
9108
9109          This is a RELAX_NARROW frag.  */
9110       switch (desired_diff)
9111         {
9112         case 1:
9113           gas_assert (0);
9114           return 0;
9115         case 2:
9116         case 3:
9117           return 0;
9118         case 4:
9119           if (wide_nops >= 1 && num_widens == 1)
9120             return 1; /* case 4a */
9121           return 0;
9122         case 5:
9123           if (wide_nops >= 1 && num_widens == 2)
9124             return 1; /* case 5a */
9125           return 0;
9126         case 6:
9127           if (wide_nops >= 2)
9128             return 0; /* case 6a */
9129           else if (wide_nops >= 1 && num_widens == 3)
9130             return 1; /* case 6b */
9131           return 0;
9132         case 7:
9133           if (wide_nops >= 1 && num_widens == 4)
9134             return 1; /* case 7a */
9135           else if (wide_nops >= 2 && num_widens == 1)
9136             return 1; /* case 7b */
9137           return 0;
9138         default:
9139           gas_assert (0);
9140           return 0;
9141         }
9142     }
9143   gas_assert (0);
9144   return 0;
9145 }
9146
9147
9148 static long
9149 relax_frag_immed (segT segP,
9150                   fragS *fragP,
9151                   long stretch,
9152                   int min_steps,
9153                   xtensa_format fmt,
9154                   int slot,
9155                   int *stretched_p,
9156                   bfd_boolean estimate_only)
9157 {
9158   TInsn tinsn;
9159   int old_size;
9160   bfd_boolean negatable_branch = FALSE;
9161   bfd_boolean branch_jmp_to_next = FALSE;
9162   bfd_boolean from_wide_insn = FALSE;
9163   xtensa_isa isa = xtensa_default_isa;
9164   IStack istack;
9165   offsetT frag_offset;
9166   int num_steps;
9167   int num_text_bytes, num_literal_bytes;
9168   int literal_diff, total_text_diff, this_text_diff;
9169
9170   gas_assert (fragP->fr_opcode != NULL);
9171
9172   xg_clear_vinsn (&cur_vinsn);
9173   vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
9174   if (cur_vinsn.num_slots > 1)
9175     from_wide_insn = TRUE;
9176
9177   tinsn = cur_vinsn.slots[slot];
9178   tinsn_immed_from_frag (&tinsn, fragP, slot);
9179
9180   if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1)
9181     return 0;
9182
9183   if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
9184     branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
9185
9186   negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
9187
9188   old_size = xtensa_format_length (isa, fmt);
9189
9190   /* Special case: replace a branch to the next instruction with a NOP.
9191      This is required to work around a hardware bug in T1040.0 and also
9192      serves as an optimization.  */
9193
9194   if (branch_jmp_to_next
9195       && ((old_size == 2) || (old_size == 3))
9196       && !next_frag_is_loop_target (fragP))
9197     return 0;
9198
9199   /* Here is the fun stuff: Get the immediate field from this
9200      instruction.  If it fits, we are done.  If not, find the next
9201      instruction sequence that fits.  */
9202
9203   frag_offset = fragP->fr_opcode - fragP->fr_literal;
9204   istack_init (&istack);
9205   num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
9206                                  min_steps, stretch);
9207   gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
9208
9209   fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
9210
9211   /* Figure out the number of bytes needed.  */
9212   num_literal_bytes = get_num_stack_literal_bytes (&istack);
9213   literal_diff
9214     = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9215   num_text_bytes = get_num_stack_text_bytes (&istack);
9216
9217   if (from_wide_insn)
9218     {
9219       int first = 0;
9220       while (istack.insn[first].opcode == XTENSA_UNDEFINED)
9221         first++;
9222
9223       num_text_bytes += old_size;
9224       if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
9225         num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
9226       else
9227         {
9228           /* The first instruction in the relaxed sequence will go after
9229              the current wide instruction, and thus its symbolic immediates
9230              might not fit.  */
9231
9232           istack_init (&istack);
9233           num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP,
9234                                          frag_offset + old_size,
9235                                          min_steps, stretch + old_size);
9236           gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
9237
9238           fragP->tc_frag_data.slot_subtypes[slot]
9239             = (int) RELAX_IMMED + num_steps;
9240
9241           num_literal_bytes = get_num_stack_literal_bytes (&istack);
9242           literal_diff
9243             = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9244
9245           num_text_bytes = get_num_stack_text_bytes (&istack) + old_size;
9246         }
9247     }
9248
9249   total_text_diff = num_text_bytes - old_size;
9250   this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
9251
9252   /* It MUST get larger.  If not, we could get an infinite loop.  */
9253   gas_assert (num_text_bytes >= 0);
9254   gas_assert (literal_diff >= 0);
9255   gas_assert (total_text_diff >= 0);
9256
9257   fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
9258   fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
9259   gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
9260   gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
9261
9262   /* Find the associated expandable literal for this.  */
9263   if (literal_diff != 0)
9264     {
9265       fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot];
9266       if (lit_fragP)
9267         {
9268           gas_assert (literal_diff == 4);
9269           lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
9270
9271           /* We expect that the literal section state has NOT been
9272              modified yet.  */
9273           gas_assert (lit_fragP->fr_type == rs_machine_dependent
9274                   && lit_fragP->fr_subtype == RELAX_LITERAL);
9275           lit_fragP->fr_subtype = RELAX_LITERAL_NR;
9276
9277           /* We need to mark this section for another iteration
9278              of relaxation.  */
9279           (*stretched_p)++;
9280         }
9281     }
9282
9283   if (negatable_branch && istack.ninsn > 1)
9284     update_next_frag_state (fragP);
9285
9286   return this_text_diff;
9287 }
9288
9289 \f
9290 /* md_convert_frag Hook and Helper Functions.  */
9291
9292 static void convert_frag_align_next_opcode (fragS *);
9293 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
9294 static void convert_frag_fill_nop (fragS *);
9295 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
9296
9297 void
9298 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
9299 {
9300   static xtensa_insnbuf vbuf = NULL;
9301   xtensa_isa isa = xtensa_default_isa;
9302   int slot;
9303   int num_slots;
9304   xtensa_format fmt;
9305   char *file_name;
9306   unsigned line;
9307
9308   as_where (&file_name, &line);
9309   new_logical_line (fragp->fr_file, fragp->fr_line);
9310
9311   switch (fragp->fr_subtype)
9312     {
9313     case RELAX_ALIGN_NEXT_OPCODE:
9314       /* Always convert.  */
9315       convert_frag_align_next_opcode (fragp);
9316       break;
9317
9318     case RELAX_DESIRE_ALIGN:
9319       /* Do nothing.  If not aligned already, too bad.  */
9320       break;
9321
9322     case RELAX_LITERAL:
9323     case RELAX_LITERAL_FINAL:
9324       break;
9325
9326     case RELAX_SLOTS:
9327       if (vbuf == NULL)
9328         vbuf = xtensa_insnbuf_alloc (isa);
9329
9330       xtensa_insnbuf_from_chars
9331         (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
9332       fmt = xtensa_format_decode (isa, vbuf);
9333       num_slots = xtensa_format_num_slots (isa, fmt);
9334
9335       for (slot = 0; slot < num_slots; slot++)
9336         {
9337           switch (fragp->tc_frag_data.slot_subtypes[slot])
9338             {
9339             case RELAX_NARROW:
9340               convert_frag_narrow (sec, fragp, fmt, slot);
9341               break;
9342
9343             case RELAX_IMMED:
9344             case RELAX_IMMED_STEP1:
9345             case RELAX_IMMED_STEP2:
9346             case RELAX_IMMED_STEP3:
9347               /* Place the immediate.  */
9348               convert_frag_immed
9349                 (sec, fragp,
9350                  fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9351                  fmt, slot);
9352               break;
9353
9354             default:
9355               /* This is OK because some slots could have
9356                  relaxations and others have none.  */
9357               break;
9358             }
9359         }
9360       break;
9361
9362     case RELAX_UNREACHABLE:
9363       memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
9364       fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
9365       fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
9366       frag_wane (fragp);
9367       break;
9368
9369     case RELAX_MAYBE_UNREACHABLE:
9370     case RELAX_MAYBE_DESIRE_ALIGN:
9371       frag_wane (fragp);
9372       break;
9373
9374     case RELAX_FILL_NOP:
9375       convert_frag_fill_nop (fragp);
9376       break;
9377
9378     case RELAX_LITERAL_NR:
9379       if (use_literal_section)
9380         {
9381           /* This should have been handled during relaxation.  When
9382              relaxing a code segment, literals sometimes need to be
9383              added to the corresponding literal segment.  If that
9384              literal segment has already been relaxed, then we end up
9385              in this situation.  Marking the literal segments as data
9386              would make this happen less often (since GAS always relaxes
9387              code before data), but we could still get into trouble if
9388              there are instructions in a segment that is not marked as
9389              containing code.  Until we can implement a better solution,
9390              cheat and adjust the addresses of all the following frags.
9391              This could break subsequent alignments, but the linker's
9392              literal coalescing will do that anyway.  */
9393
9394           fragS *f;
9395           fragp->fr_subtype = RELAX_LITERAL_FINAL;
9396           gas_assert (fragp->tc_frag_data.unreported_expansion == 4);
9397           memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9398           fragp->fr_var -= 4;
9399           fragp->fr_fix += 4;
9400           for (f = fragp->fr_next; f; f = f->fr_next)
9401             f->fr_address += 4;
9402         }
9403       else
9404         as_bad (_("invalid relaxation fragment result"));
9405       break;
9406     }
9407
9408   fragp->fr_var = 0;
9409   new_logical_line (file_name, line);
9410 }
9411
9412
9413 static void
9414 convert_frag_align_next_opcode (fragS *fragp)
9415 {
9416   char *nop_buf;                /* Location for Writing.  */
9417   bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
9418   addressT aligned_address;
9419   offsetT fill_size;
9420   int nop, nop_count;
9421
9422   aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
9423                                               fragp->fr_fix);
9424   fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
9425   nop_count = get_text_align_nop_count (fill_size, use_no_density);
9426   nop_buf = fragp->fr_literal + fragp->fr_fix;
9427
9428   for (nop = 0; nop < nop_count; nop++)
9429     {
9430       int nop_size;
9431       nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
9432
9433       assemble_nop (nop_size, nop_buf);
9434       nop_buf += nop_size;
9435     }
9436
9437   fragp->fr_fix += fill_size;
9438   fragp->fr_var -= fill_size;
9439 }
9440
9441
9442 static void
9443 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
9444 {
9445   TInsn tinsn, single_target;
9446   int size, old_size, diff;
9447   offsetT frag_offset;
9448
9449   gas_assert (slot == 0);
9450   tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
9451
9452   if (fragP->tc_frag_data.is_aligning_branch == 1)
9453     {
9454       gas_assert (fragP->tc_frag_data.text_expansion[0] == 1
9455               || fragP->tc_frag_data.text_expansion[0] == 0);
9456       convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
9457                           fmt, slot);
9458       return;
9459     }
9460
9461   if (fragP->tc_frag_data.text_expansion[0] == 0)
9462     {
9463       /* No conversion.  */
9464       fragP->fr_var = 0;
9465       return;
9466     }
9467
9468   gas_assert (fragP->fr_opcode != NULL);
9469
9470   /* Frags in this relaxation state should only contain
9471      single instruction bundles.  */
9472   tinsn_immed_from_frag (&tinsn, fragP, 0);
9473
9474   /* Just convert it to a wide form....  */
9475   size = 0;
9476   old_size = xg_get_single_size (tinsn.opcode);
9477
9478   tinsn_init (&single_target);
9479   frag_offset = fragP->fr_opcode - fragP->fr_literal;
9480
9481   if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
9482     {
9483       as_bad (_("unable to widen instruction"));
9484       return;
9485     }
9486
9487   size = xg_get_single_size (single_target.opcode);
9488   xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
9489                        frag_offset, TRUE);
9490
9491   diff = size - old_size;
9492   gas_assert (diff >= 0);
9493   gas_assert (diff <= fragP->fr_var);
9494   fragP->fr_var -= diff;
9495   fragP->fr_fix += diff;
9496
9497   /* clean it up */
9498   fragP->fr_var = 0;
9499 }
9500
9501
9502 static void
9503 convert_frag_fill_nop (fragS *fragP)
9504 {
9505   char *loc = &fragP->fr_literal[fragP->fr_fix];
9506   int size = fragP->tc_frag_data.text_expansion[0];
9507   gas_assert ((unsigned) size == (fragP->fr_next->fr_address
9508                               - fragP->fr_address - fragP->fr_fix));
9509   if (size == 0)
9510     {
9511       /* No conversion.  */
9512       fragP->fr_var = 0;
9513       return;
9514     }
9515   assemble_nop (size, loc);
9516   fragP->tc_frag_data.is_insn = TRUE;
9517   fragP->fr_var -= size;
9518   fragP->fr_fix += size;
9519   frag_wane (fragP);
9520 }
9521
9522
9523 static fixS *fix_new_exp_in_seg
9524   (segT, subsegT, fragS *, int, int, expressionS *, int,
9525    bfd_reloc_code_real_type);
9526 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
9527
9528 static void
9529 convert_frag_immed (segT segP,
9530                     fragS *fragP,
9531                     int min_steps,
9532                     xtensa_format fmt,
9533                     int slot)
9534 {
9535   char *immed_instr = fragP->fr_opcode;
9536   TInsn orig_tinsn;
9537   bfd_boolean expanded = FALSE;
9538   bfd_boolean branch_jmp_to_next = FALSE;
9539   char *fr_opcode = fragP->fr_opcode;
9540   xtensa_isa isa = xtensa_default_isa;
9541   bfd_boolean from_wide_insn = FALSE;
9542   int bytes;
9543   bfd_boolean is_loop;
9544
9545   gas_assert (fr_opcode != NULL);
9546
9547   xg_clear_vinsn (&cur_vinsn);
9548
9549   vinsn_from_chars (&cur_vinsn, fr_opcode);
9550   if (cur_vinsn.num_slots > 1)
9551     from_wide_insn = TRUE;
9552
9553   orig_tinsn = cur_vinsn.slots[slot];
9554   tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
9555
9556   is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
9557
9558   if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
9559     branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
9560
9561   if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
9562     {
9563       /* Conversion just inserts a NOP and marks the fix as completed.  */
9564       bytes = xtensa_format_length (isa, fmt);
9565       if (bytes >= 4)
9566         {
9567           cur_vinsn.slots[slot].opcode =
9568             xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot);
9569           cur_vinsn.slots[slot].ntok = 0;
9570         }
9571       else
9572         {
9573           bytes += fragP->tc_frag_data.text_expansion[0];
9574           gas_assert (bytes == 2 || bytes == 3);
9575           build_nop (&cur_vinsn.slots[0], bytes);
9576           fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
9577         }
9578       vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE);
9579       xtensa_insnbuf_to_chars
9580         (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
9581       fragP->fr_var = 0;
9582     }
9583   else
9584     {
9585       /* Here is the fun stuff:  Get the immediate field from this
9586          instruction.  If it fits, we're done.  If not, find the next
9587          instruction sequence that fits.  */
9588
9589       IStack istack;
9590       int i;
9591       symbolS *lit_sym = NULL;
9592       int total_size = 0;
9593       int target_offset = 0;
9594       int old_size;
9595       int diff;
9596       symbolS *gen_label = NULL;
9597       offsetT frag_offset;
9598       bfd_boolean first = TRUE;
9599       bfd_boolean last_is_jump;
9600
9601       /* It does not fit.  Find something that does and
9602          convert immediately.  */
9603       frag_offset = fr_opcode - fragP->fr_literal;
9604       istack_init (&istack);
9605       xg_assembly_relax (&istack, &orig_tinsn,
9606                          segP, fragP, frag_offset, min_steps, 0);
9607
9608       old_size = xtensa_format_length (isa, fmt);
9609
9610       /* Assemble this right inline.  */
9611
9612       /* First, create the mapping from a label name to the REAL label.  */
9613       target_offset = 0;
9614       for (i = 0; i < istack.ninsn; i++)
9615         {
9616           TInsn *tinsn = &istack.insn[i];
9617           fragS *lit_frag;
9618
9619           switch (tinsn->insn_type)
9620             {
9621             case ITYPE_LITERAL:
9622               if (lit_sym != NULL)
9623                 as_bad (_("multiple literals in expansion"));
9624               /* First find the appropriate space in the literal pool.  */
9625               lit_frag = fragP->tc_frag_data.literal_frags[slot];
9626               if (lit_frag == NULL)
9627                 as_bad (_("no registered fragment for literal"));
9628               if (tinsn->ntok != 1)
9629                 as_bad (_("number of literal tokens != 1"));
9630
9631               /* Set the literal symbol and add a fixup.  */
9632               lit_sym = lit_frag->fr_symbol;
9633               break;
9634
9635             case ITYPE_LABEL:
9636               if (align_targets && !is_loop)
9637                 {
9638                   fragS *unreach = fragP->fr_next;
9639                   while (!(unreach->fr_type == rs_machine_dependent
9640                            && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9641                                || unreach->fr_subtype == RELAX_UNREACHABLE)))
9642                     {
9643                       unreach = unreach->fr_next;
9644                     }
9645
9646                   gas_assert (unreach->fr_type == rs_machine_dependent
9647                           && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9648                               || unreach->fr_subtype == RELAX_UNREACHABLE));
9649
9650                   target_offset += unreach->tc_frag_data.text_expansion[0];
9651                 }
9652               gas_assert (gen_label == NULL);
9653               gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
9654                                       fr_opcode - fragP->fr_literal
9655                                       + target_offset, fragP);
9656               break;
9657
9658             case ITYPE_INSN:
9659               if (first && from_wide_insn)
9660                 {
9661                   target_offset += xtensa_format_length (isa, fmt);
9662                   first = FALSE;
9663                   if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9664                     target_offset += xg_get_single_size (tinsn->opcode);
9665                 }
9666               else
9667                 target_offset += xg_get_single_size (tinsn->opcode);
9668               break;
9669             }
9670         }
9671
9672       total_size = 0;
9673       first = TRUE;
9674       last_is_jump = FALSE;
9675       for (i = 0; i < istack.ninsn; i++)
9676         {
9677           TInsn *tinsn = &istack.insn[i];
9678           fragS *lit_frag;
9679           int size;
9680           segT target_seg;
9681           bfd_reloc_code_real_type reloc_type;
9682
9683           switch (tinsn->insn_type)
9684             {
9685             case ITYPE_LITERAL:
9686               lit_frag = fragP->tc_frag_data.literal_frags[slot];
9687               /* Already checked.  */
9688               gas_assert (lit_frag != NULL);
9689               gas_assert (lit_sym != NULL);
9690               gas_assert (tinsn->ntok == 1);
9691               /* Add a fixup.  */
9692               target_seg = S_GET_SEGMENT (lit_sym);
9693               gas_assert (target_seg);
9694               reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE);
9695               fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
9696                                   &tinsn->tok[0], FALSE, reloc_type);
9697               break;
9698
9699             case ITYPE_LABEL:
9700               break;
9701
9702             case ITYPE_INSN:
9703               xg_resolve_labels (tinsn, gen_label);
9704               xg_resolve_literals (tinsn, lit_sym);
9705               if (from_wide_insn && first)
9706                 {
9707                   first = FALSE;
9708                   if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9709                     {
9710                       cur_vinsn.slots[slot] = *tinsn;
9711                     }
9712                   else
9713                     {
9714                       cur_vinsn.slots[slot].opcode =
9715                         xtensa_format_slot_nop_opcode (isa, fmt, slot);
9716                       cur_vinsn.slots[slot].ntok = 0;
9717                     }
9718                   vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE);
9719                   xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
9720                                            (unsigned char *) immed_instr, 0);
9721                   fragP->tc_frag_data.is_insn = TRUE;
9722                   size = xtensa_format_length (isa, fmt);
9723                   if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9724                     {
9725                       xg_emit_insn_to_buf
9726                         (tinsn, immed_instr + size, fragP,
9727                          immed_instr - fragP->fr_literal + size, TRUE);
9728                       size += xg_get_single_size (tinsn->opcode);
9729                     }
9730                 }
9731               else
9732                 {
9733                   size = xg_get_single_size (tinsn->opcode);
9734                   xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
9735                                        immed_instr - fragP->fr_literal, TRUE);
9736                 }
9737               immed_instr += size;
9738               total_size += size;
9739               break;
9740             }
9741         }
9742
9743       diff = total_size - old_size;
9744       gas_assert (diff >= 0);
9745       if (diff != 0)
9746         expanded = TRUE;
9747       gas_assert (diff <= fragP->fr_var);
9748       fragP->fr_var -= diff;
9749       fragP->fr_fix += diff;
9750     }
9751
9752   /* Check for undefined immediates in LOOP instructions.  */
9753   if (is_loop)
9754     {
9755       symbolS *sym;
9756       sym = orig_tinsn.tok[1].X_add_symbol;
9757       if (sym != NULL && !S_IS_DEFINED (sym))
9758         {
9759           as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9760           return;
9761         }
9762       sym = orig_tinsn.tok[1].X_op_symbol;
9763       if (sym != NULL && !S_IS_DEFINED (sym))
9764         {
9765           as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9766           return;
9767         }
9768     }
9769
9770   if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
9771     convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
9772
9773   if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
9774     {
9775       /* Add an expansion note on the expanded instruction.  */
9776       fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
9777                           &orig_tinsn.tok[0], TRUE,
9778                           BFD_RELOC_XTENSA_ASM_EXPAND);
9779     }
9780 }
9781
9782
9783 /* Add a new fix expression into the desired segment.  We have to
9784    switch to that segment to do this.  */
9785
9786 static fixS *
9787 fix_new_exp_in_seg (segT new_seg,
9788                     subsegT new_subseg,
9789                     fragS *frag,
9790                     int where,
9791                     int size,
9792                     expressionS *exp,
9793                     int pcrel,
9794                     bfd_reloc_code_real_type r_type)
9795 {
9796   fixS *new_fix;
9797   segT seg = now_seg;
9798   subsegT subseg = now_subseg;
9799
9800   gas_assert (new_seg != 0);
9801   subseg_set (new_seg, new_subseg);
9802
9803   new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
9804   subseg_set (seg, subseg);
9805   return new_fix;
9806 }
9807
9808
9809 /* Relax a loop instruction so that it can span loop >256 bytes.
9810
9811                   loop    as, .L1
9812           .L0:
9813                   rsr     as, LEND
9814                   wsr     as, LBEG
9815                   addi    as, as, lo8 (label-.L1)
9816                   addmi   as, as, mid8 (label-.L1)
9817                   wsr     as, LEND
9818                   isync
9819                   rsr     as, LCOUNT
9820                   addi    as, as, 1
9821           .L1:
9822                   <<body>>
9823           label:
9824 */
9825
9826 static void
9827 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
9828 {
9829   TInsn loop_insn;
9830   TInsn addi_insn;
9831   TInsn addmi_insn;
9832   unsigned long target;
9833   static xtensa_insnbuf insnbuf = NULL;
9834   unsigned int loop_length, loop_length_hi, loop_length_lo;
9835   xtensa_isa isa = xtensa_default_isa;
9836   addressT loop_offset;
9837   addressT addi_offset = 9;
9838   addressT addmi_offset = 12;
9839   fragS *next_fragP;
9840   int target_count;
9841
9842   if (!insnbuf)
9843     insnbuf = xtensa_insnbuf_alloc (isa);
9844
9845   /* Get the loop offset.  */
9846   loop_offset = get_expanded_loop_offset (tinsn->opcode);
9847
9848   /* Validate that there really is a LOOP at the loop_offset.  Because
9849      loops are not bundleable, we can assume that the instruction will be
9850      in slot 0.  */
9851   tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
9852   tinsn_immed_from_frag (&loop_insn, fragP, 0);
9853
9854   gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
9855   addi_offset += loop_offset;
9856   addmi_offset += loop_offset;
9857
9858   gas_assert (tinsn->ntok == 2);
9859   if (tinsn->tok[1].X_op == O_constant)
9860     target = tinsn->tok[1].X_add_number;
9861   else if (tinsn->tok[1].X_op == O_symbol)
9862     {
9863       /* Find the fragment.  */
9864       symbolS *sym = tinsn->tok[1].X_add_symbol;
9865       gas_assert (S_GET_SEGMENT (sym) == segP
9866               || S_GET_SEGMENT (sym) == absolute_section);
9867       target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
9868     }
9869   else
9870     {
9871       as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
9872       target = 0;
9873     }
9874
9875   loop_length = target - (fragP->fr_address + fragP->fr_fix);
9876   loop_length_hi = loop_length & ~0x0ff;
9877   loop_length_lo = loop_length & 0x0ff;
9878   if (loop_length_lo >= 128)
9879     {
9880       loop_length_lo -= 256;
9881       loop_length_hi += 256;
9882     }
9883
9884   /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9885      32512.  If the loop is larger than that, then we just fail.  */
9886   if (loop_length_hi > 32512)
9887     as_bad_where (fragP->fr_file, fragP->fr_line,
9888                   _("loop too long for LOOP instruction"));
9889
9890   tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
9891   gas_assert (addi_insn.opcode == xtensa_addi_opcode);
9892
9893   tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
9894   gas_assert (addmi_insn.opcode == xtensa_addmi_opcode);
9895
9896   set_expr_const (&addi_insn.tok[2], loop_length_lo);
9897   tinsn_to_insnbuf (&addi_insn, insnbuf);
9898
9899   fragP->tc_frag_data.is_insn = TRUE;
9900   xtensa_insnbuf_to_chars
9901     (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0);
9902
9903   set_expr_const (&addmi_insn.tok[2], loop_length_hi);
9904   tinsn_to_insnbuf (&addmi_insn, insnbuf);
9905   xtensa_insnbuf_to_chars
9906     (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0);
9907
9908   /* Walk through all of the frags from here to the loop end
9909      and mark them as no_transform to keep them from being modified
9910      by the linker.  If we ever have a relocation for the
9911      addi/addmi of the difference of two symbols we can remove this.  */
9912
9913   target_count = 0;
9914   for (next_fragP = fragP; next_fragP != NULL;
9915        next_fragP = next_fragP->fr_next)
9916     {
9917       next_fragP->tc_frag_data.is_no_transform = TRUE;
9918       if (next_fragP->tc_frag_data.is_loop_target)
9919         target_count++;
9920       if (target_count == 2)
9921         break;
9922     }
9923 }
9924
9925 \f
9926 /* A map that keeps information on a per-subsegment basis.  This is
9927    maintained during initial assembly, but is invalid once the
9928    subsegments are smashed together.  I.E., it cannot be used during
9929    the relaxation.  */
9930
9931 typedef struct subseg_map_struct
9932 {
9933   /* the key */
9934   segT seg;
9935   subsegT subseg;
9936
9937   /* the data */
9938   unsigned flags;
9939   float total_freq;     /* fall-through + branch target frequency */
9940   float target_freq;    /* branch target frequency alone */
9941
9942   struct subseg_map_struct *next;
9943 } subseg_map;
9944
9945
9946 static subseg_map *sseg_map = NULL;
9947
9948 static subseg_map *
9949 get_subseg_info (segT seg, subsegT subseg)
9950 {
9951   subseg_map *subseg_e;
9952
9953   for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
9954     {
9955       if (seg == subseg_e->seg && subseg == subseg_e->subseg)
9956         break;
9957     }
9958   return subseg_e;
9959 }
9960
9961
9962 static subseg_map *
9963 add_subseg_info (segT seg, subsegT subseg)
9964 {
9965   subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
9966   memset (subseg_e, 0, sizeof (subseg_map));
9967   subseg_e->seg = seg;
9968   subseg_e->subseg = subseg;
9969   subseg_e->flags = 0;
9970   /* Start off considering every branch target very important.  */
9971   subseg_e->target_freq = 1.0;
9972   subseg_e->total_freq = 1.0;
9973   subseg_e->next = sseg_map;
9974   sseg_map = subseg_e;
9975   return subseg_e;
9976 }
9977
9978
9979 static unsigned
9980 get_last_insn_flags (segT seg, subsegT subseg)
9981 {
9982   subseg_map *subseg_e = get_subseg_info (seg, subseg);
9983   if (subseg_e)
9984     return subseg_e->flags;
9985   return 0;
9986 }
9987
9988
9989 static void
9990 set_last_insn_flags (segT seg,
9991                      subsegT subseg,
9992                      unsigned fl,
9993                      bfd_boolean val)
9994 {
9995   subseg_map *subseg_e = get_subseg_info (seg, subseg);
9996   if (! subseg_e)
9997     subseg_e = add_subseg_info (seg, subseg);
9998   if (val)
9999     subseg_e->flags |= fl;
10000   else
10001     subseg_e->flags &= ~fl;
10002 }
10003
10004
10005 static float
10006 get_subseg_total_freq (segT seg, subsegT subseg)
10007 {
10008   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10009   if (subseg_e)
10010     return subseg_e->total_freq;
10011   return 1.0;
10012 }
10013
10014
10015 static float
10016 get_subseg_target_freq (segT seg, subsegT subseg)
10017 {
10018   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10019   if (subseg_e)
10020     return subseg_e->target_freq;
10021   return 1.0;
10022 }
10023
10024
10025 static void
10026 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
10027 {
10028   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10029   if (! subseg_e)
10030     subseg_e = add_subseg_info (seg, subseg);
10031   subseg_e->total_freq = total_f;
10032   subseg_e->target_freq = target_f;
10033 }
10034
10035 \f
10036 /* Segment Lists and emit_state Stuff.  */
10037
10038 static void
10039 xtensa_move_seg_list_to_beginning (seg_list *head)
10040 {
10041   head = head->next;
10042   while (head)
10043     {
10044       segT literal_section = head->seg;
10045
10046       /* Move the literal section to the front of the section list.  */
10047       gas_assert (literal_section);
10048       if (literal_section != stdoutput->sections)
10049         {
10050           bfd_section_list_remove (stdoutput, literal_section);
10051           bfd_section_list_prepend (stdoutput, literal_section);
10052         }
10053       head = head->next;
10054     }
10055 }
10056
10057
10058 static void mark_literal_frags (seg_list *);
10059
10060 static void
10061 xtensa_move_literals (void)
10062 {
10063   seg_list *segment;
10064   frchainS *frchain_from, *frchain_to;
10065   fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
10066   fragS **frag_splice;
10067   emit_state state;
10068   segT dest_seg;
10069   fixS *fix, *next_fix, **fix_splice;
10070   sym_list *lit;
10071
10072   mark_literal_frags (literal_head->next);
10073
10074   if (use_literal_section)
10075     return;
10076
10077   for (segment = literal_head->next; segment; segment = segment->next)
10078     {
10079       /* Keep the literals for .init and .fini in separate sections.  */
10080       if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME)
10081           || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME))
10082         continue;
10083
10084       frchain_from = seg_info (segment->seg)->frchainP;
10085       search_frag = frchain_from->frch_root;
10086       literal_pool = NULL;
10087       frchain_to = NULL;
10088       frag_splice = &(frchain_from->frch_root);
10089
10090       while (!search_frag->tc_frag_data.literal_frag)
10091         {
10092           gas_assert (search_frag->fr_fix == 0
10093                   || search_frag->fr_type == rs_align);
10094           search_frag = search_frag->fr_next;
10095         }
10096
10097       gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype
10098               == RELAX_LITERAL_POOL_BEGIN);
10099       xtensa_switch_section_emit_state (&state, segment->seg, 0);
10100
10101       /* Make sure that all the frags in this series are closed, and
10102          that there is at least one left over of zero-size.  This
10103          prevents us from making a segment with an frchain without any
10104          frags in it.  */
10105       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10106       xtensa_set_frag_assembly_state (frag_now);
10107       last_frag = frag_now;
10108       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10109       xtensa_set_frag_assembly_state (frag_now);
10110
10111       while (search_frag != frag_now)
10112         {
10113           next_frag = search_frag->fr_next;
10114
10115           /* First, move the frag out of the literal section and
10116              to the appropriate place.  */
10117           if (search_frag->tc_frag_data.literal_frag)
10118             {
10119               literal_pool = search_frag->tc_frag_data.literal_frag;
10120               gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
10121               frchain_to = literal_pool->tc_frag_data.lit_frchain;
10122               gas_assert (frchain_to);
10123             }
10124           insert_after = literal_pool->tc_frag_data.literal_frag;
10125           dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
10126
10127           *frag_splice = next_frag;
10128           search_frag->fr_next = insert_after->fr_next;
10129           insert_after->fr_next = search_frag;
10130           search_frag->tc_frag_data.lit_seg = dest_seg;
10131           literal_pool->tc_frag_data.literal_frag = search_frag;
10132
10133           /* Now move any fixups associated with this frag to the
10134              right section.  */
10135           fix = frchain_from->fix_root;
10136           fix_splice = &(frchain_from->fix_root);
10137           while (fix)
10138             {
10139               next_fix = fix->fx_next;
10140               if (fix->fx_frag == search_frag)
10141                 {
10142                   *fix_splice = next_fix;
10143                   fix->fx_next = frchain_to->fix_root;
10144                   frchain_to->fix_root = fix;
10145                   if (frchain_to->fix_tail == NULL)
10146                     frchain_to->fix_tail = fix;
10147                 }
10148               else
10149                 fix_splice = &(fix->fx_next);
10150               fix = next_fix;
10151             }
10152           search_frag = next_frag;
10153         }
10154
10155       if (frchain_from->fix_root != NULL)
10156         {
10157           frchain_from = seg_info (segment->seg)->frchainP;
10158           as_warn (_("fixes not all moved from %s"), segment->seg->name);
10159
10160           gas_assert (frchain_from->fix_root == NULL);
10161         }
10162       frchain_from->fix_tail = NULL;
10163       xtensa_restore_emit_state (&state);
10164     }
10165
10166   /* Now fix up the SEGMENT value for all the literal symbols.  */
10167   for (lit = literal_syms; lit; lit = lit->next)
10168     {
10169       symbolS *lit_sym = lit->sym;
10170       segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
10171       if (dest_seg)
10172         S_SET_SEGMENT (lit_sym, dest_seg);
10173     }
10174 }
10175
10176
10177 /* Walk over all the frags for segments in a list and mark them as
10178    containing literals.  As clunky as this is, we can't rely on frag_var
10179    and frag_variant to get called in all situations.  */
10180
10181 static void
10182 mark_literal_frags (seg_list *segment)
10183 {
10184   frchainS *frchain_from;
10185   fragS *search_frag;
10186
10187   while (segment)
10188     {
10189       frchain_from = seg_info (segment->seg)->frchainP;
10190       search_frag = frchain_from->frch_root;
10191       while (search_frag)
10192         {
10193           search_frag->tc_frag_data.is_literal = TRUE;
10194           search_frag = search_frag->fr_next;
10195         }
10196       segment = segment->next;
10197     }
10198 }
10199
10200
10201 static void
10202 xtensa_reorder_seg_list (seg_list *head, segT after)
10203 {
10204   /* Move all of the sections in the section list to come
10205      after "after" in the gnu segment list.  */
10206
10207   head = head->next;
10208   while (head)
10209     {
10210       segT literal_section = head->seg;
10211
10212       /* Move the literal section after "after".  */
10213       gas_assert (literal_section);
10214       if (literal_section != after)
10215         {
10216           bfd_section_list_remove (stdoutput, literal_section);
10217           bfd_section_list_insert_after (stdoutput, after, literal_section);
10218         }
10219
10220       head = head->next;
10221     }
10222 }
10223
10224
10225 /* Push all the literal segments to the end of the gnu list.  */
10226
10227 static void
10228 xtensa_reorder_segments (void)
10229 {
10230   segT sec;
10231   segT last_sec = 0;
10232   int old_count = 0;
10233   int new_count = 0;
10234
10235   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10236     {
10237       last_sec = sec;
10238       old_count++;
10239     }
10240
10241   /* Now that we have the last section, push all the literal
10242      sections to the end.  */
10243   xtensa_reorder_seg_list (literal_head, last_sec);
10244
10245   /* Now perform the final error check.  */
10246   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10247     new_count++;
10248   gas_assert (new_count == old_count);
10249 }
10250
10251
10252 /* Change the emit state (seg, subseg, and frag related stuff) to the
10253    correct location.  Return a emit_state which can be passed to
10254    xtensa_restore_emit_state to return to current fragment.  */
10255
10256 static void
10257 xtensa_switch_to_literal_fragment (emit_state *result)
10258 {
10259   if (directive_state[directive_absolute_literals])
10260     {
10261       segT lit4_seg = cache_literal_section (TRUE);
10262       xtensa_switch_section_emit_state (result, lit4_seg, 0);
10263     }
10264   else
10265     xtensa_switch_to_non_abs_literal_fragment (result);
10266
10267   /* Do a 4-byte align here.  */
10268   frag_align (2, 0, 0);
10269   record_alignment (now_seg, 2);
10270 }
10271
10272
10273 static void
10274 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
10275 {
10276   static bfd_boolean recursive = FALSE;
10277   fragS *pool_location = get_literal_pool_location (now_seg);
10278   segT lit_seg;
10279   bfd_boolean is_init =
10280     (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
10281   bfd_boolean is_fini =
10282     (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
10283
10284   if (pool_location == NULL
10285       && !use_literal_section
10286       && !recursive
10287       && !is_init && ! is_fini)
10288     {
10289       as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10290
10291       /* When we mark a literal pool location, we want to put a frag in
10292          the literal pool that points to it.  But to do that, we want to
10293          switch_to_literal_fragment.  But literal sections don't have
10294          literal pools, so their location is always null, so we would
10295          recurse forever.  This is kind of hacky, but it works.  */
10296
10297       recursive = TRUE;
10298       xtensa_mark_literal_pool_location ();
10299       recursive = FALSE;
10300     }
10301
10302   lit_seg = cache_literal_section (FALSE);
10303   xtensa_switch_section_emit_state (result, lit_seg, 0);
10304
10305   if (!use_literal_section
10306       && !is_init && !is_fini
10307       && get_literal_pool_location (now_seg) != pool_location)
10308     {
10309       /* Close whatever frag is there.  */
10310       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10311       xtensa_set_frag_assembly_state (frag_now);
10312       frag_now->tc_frag_data.literal_frag = pool_location;
10313       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10314       xtensa_set_frag_assembly_state (frag_now);
10315     }
10316 }
10317
10318
10319 /* Call this function before emitting data into the literal section.
10320    This is a helper function for xtensa_switch_to_literal_fragment.
10321    This is similar to a .section new_now_seg subseg. */
10322
10323 static void
10324 xtensa_switch_section_emit_state (emit_state *state,
10325                                   segT new_now_seg,
10326                                   subsegT new_now_subseg)
10327 {
10328   state->name = now_seg->name;
10329   state->now_seg = now_seg;
10330   state->now_subseg = now_subseg;
10331   state->generating_literals = generating_literals;
10332   generating_literals++;
10333   subseg_set (new_now_seg, new_now_subseg);
10334 }
10335
10336
10337 /* Use to restore the emitting into the normal place.  */
10338
10339 static void
10340 xtensa_restore_emit_state (emit_state *state)
10341 {
10342   generating_literals = state->generating_literals;
10343   subseg_set (state->now_seg, state->now_subseg);
10344 }
10345
10346
10347 /* Predicate function used to look up a section in a particular group.  */
10348
10349 static bfd_boolean
10350 match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
10351 {
10352   const char *gname = inf;
10353   const char *group_name = elf_group_name (sec);
10354
10355   return (group_name == gname
10356           || (group_name != NULL
10357               && gname != NULL
10358               && strcmp (group_name, gname) == 0));
10359 }
10360
10361
10362 /* Get the literal section to be used for the current text section.
10363    The result may be cached in the default_lit_sections structure.  */
10364
10365 static segT
10366 cache_literal_section (bfd_boolean use_abs_literals)
10367 {
10368   const char *text_name, *group_name = 0;
10369   char *base_name, *name, *suffix;
10370   segT *pcached;
10371   segT seg, current_section;
10372   int current_subsec;
10373   bfd_boolean linkonce = FALSE;
10374
10375   /* Save the current section/subsection.  */
10376   current_section = now_seg;
10377   current_subsec = now_subseg;
10378
10379   /* Clear the cached values if they are no longer valid.  */
10380   if (now_seg != default_lit_sections.current_text_seg)
10381     {
10382       default_lit_sections.current_text_seg = now_seg;
10383       default_lit_sections.lit_seg = NULL;
10384       default_lit_sections.lit4_seg = NULL;
10385     }
10386
10387   /* Check if the literal section is already cached.  */
10388   if (use_abs_literals)
10389     pcached = &default_lit_sections.lit4_seg;
10390   else
10391     pcached = &default_lit_sections.lit_seg;
10392
10393   if (*pcached)
10394     return *pcached;
10395
10396   text_name = default_lit_sections.lit_prefix;
10397   if (! text_name || ! *text_name)
10398     {
10399       text_name = segment_name (current_section);
10400       group_name = elf_group_name (current_section);
10401       linkonce = (current_section->flags & SEC_LINK_ONCE) != 0;
10402     }
10403
10404   base_name = use_abs_literals ? ".lit4" : ".literal";
10405   if (group_name)
10406     {
10407       name = xmalloc (strlen (base_name) + strlen (group_name) + 2);
10408       sprintf (name, "%s.%s", base_name, group_name);
10409     }
10410   else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0)
10411     {
10412       suffix = strchr (text_name + linkonce_len, '.');
10413
10414       name = xmalloc (linkonce_len + strlen (base_name) + 1
10415                       + (suffix ? strlen (suffix) : 0));
10416       strcpy (name, ".gnu.linkonce");
10417       strcat (name, base_name);
10418       if (suffix)
10419         strcat (name, suffix);
10420       linkonce = TRUE;
10421     }
10422   else
10423     {
10424       /* If the section name ends with ".text", then replace that suffix
10425          instead of appending an additional suffix.  */
10426       size_t len = strlen (text_name);
10427       if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0)
10428         len -= 5;
10429
10430       name = xmalloc (len + strlen (base_name) + 1);
10431       strcpy (name, text_name);
10432       strcpy (name + len, base_name);
10433     }
10434
10435   /* Canonicalize section names to allow renaming literal sections.
10436      The group name, if any, came from the current text section and
10437      has already been canonicalized.  */
10438   name = tc_canonicalize_symbol_name (name);
10439
10440   seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group,
10441                                     (void *) group_name);
10442   if (! seg)
10443     {
10444       flagword flags;
10445
10446       seg = subseg_force_new (name, 0);
10447
10448       if (! use_abs_literals)
10449         {
10450           /* Add the newly created literal segment to the list.  */
10451           seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
10452           n->seg = seg;
10453           n->next = literal_head->next;
10454           literal_head->next = n;
10455         }
10456
10457       flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD
10458                | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0)
10459                | (use_abs_literals ? SEC_DATA : SEC_CODE));
10460
10461       elf_group_name (seg) = group_name;
10462
10463       bfd_set_section_flags (stdoutput, seg, flags);
10464       bfd_set_section_alignment (stdoutput, seg, 2);
10465     }
10466
10467   *pcached = seg;
10468   subseg_set (current_section, current_subsec);
10469   return seg;
10470 }
10471
10472 \f
10473 /* Property Tables Stuff.  */
10474
10475 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10476 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10477 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10478
10479 typedef bfd_boolean (*frag_predicate) (const fragS *);
10480 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
10481
10482 static bfd_boolean get_frag_is_literal (const fragS *);
10483 static void xtensa_create_property_segments
10484   (frag_predicate, frag_predicate, const char *, xt_section_type);
10485 static void xtensa_create_xproperty_segments
10486   (frag_flags_fn, const char *, xt_section_type);
10487 static bfd_boolean exclude_section_from_property_tables (segT);
10488 static bfd_boolean section_has_property (segT, frag_predicate);
10489 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
10490 static void add_xt_block_frags
10491   (segT, xtensa_block_info **, frag_predicate, frag_predicate);
10492 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
10493 static void xtensa_frag_flags_init (frag_flags *);
10494 static void get_frag_property_flags (const fragS *, frag_flags *);
10495 static flagword frag_flags_to_number (const frag_flags *);
10496 static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn);
10497
10498 /* Set up property tables after relaxation.  */
10499
10500 void
10501 xtensa_post_relax_hook (void)
10502 {
10503   xtensa_move_seg_list_to_beginning (literal_head);
10504
10505   xtensa_find_unmarked_state_frags ();
10506   xtensa_mark_frags_for_org ();
10507   xtensa_mark_difference_of_two_symbols ();
10508
10509   xtensa_create_property_segments (get_frag_is_literal,
10510                                    NULL,
10511                                    XTENSA_LIT_SEC_NAME,
10512                                    xt_literal_sec);
10513   xtensa_create_xproperty_segments (get_frag_property_flags,
10514                                     XTENSA_PROP_SEC_NAME,
10515                                     xt_prop_sec);
10516
10517   if (warn_unaligned_branch_targets)
10518     bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
10519   bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
10520 }
10521
10522
10523 /* This function is only meaningful after xtensa_move_literals.  */
10524
10525 static bfd_boolean
10526 get_frag_is_literal (const fragS *fragP)
10527 {
10528   gas_assert (fragP != NULL);
10529   return fragP->tc_frag_data.is_literal;
10530 }
10531
10532
10533 static void
10534 xtensa_create_property_segments (frag_predicate property_function,
10535                                  frag_predicate end_property_function,
10536                                  const char *section_name_base,
10537                                  xt_section_type sec_type)
10538 {
10539   segT *seclist;
10540
10541   /* Walk over all of the current segments.
10542      Walk over each fragment
10543      For each non-empty fragment,
10544      Build a property record (append where possible).  */
10545
10546   for (seclist = &stdoutput->sections;
10547        seclist && *seclist;
10548        seclist = &(*seclist)->next)
10549     {
10550       segT sec = *seclist;
10551
10552       if (exclude_section_from_property_tables (sec))
10553         continue;
10554
10555       if (section_has_property (sec, property_function))
10556         {
10557           segment_info_type *xt_seg_info;
10558           xtensa_block_info **xt_blocks;
10559           segT prop_sec = xtensa_make_property_section (sec, section_name_base);
10560
10561           prop_sec->output_section = prop_sec;
10562           subseg_set (prop_sec, 0);
10563           xt_seg_info = seg_info (prop_sec);
10564           xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10565
10566           /* Walk over all of the frchains here and add new sections.  */
10567           add_xt_block_frags (sec, xt_blocks, property_function,
10568                               end_property_function);
10569         }
10570     }
10571
10572   /* Now we fill them out....  */
10573
10574   for (seclist = &stdoutput->sections;
10575        seclist && *seclist;
10576        seclist = &(*seclist)->next)
10577     {
10578       segment_info_type *seginfo;
10579       xtensa_block_info *block;
10580       segT sec = *seclist;
10581
10582       seginfo = seg_info (sec);
10583       block = seginfo->tc_segment_info_data.blocks[sec_type];
10584
10585       if (block)
10586         {
10587           xtensa_block_info *cur_block;
10588           int num_recs = 0;
10589           bfd_size_type rec_size;
10590
10591           for (cur_block = block; cur_block; cur_block = cur_block->next)
10592             num_recs++;
10593
10594           rec_size = num_recs * 8;
10595           bfd_set_section_size (stdoutput, sec, rec_size);
10596
10597           if (num_recs)
10598             {
10599               char *frag_data;
10600               int i;
10601
10602               subseg_set (sec, 0);
10603               frag_data = frag_more (rec_size);
10604               cur_block = block;
10605               for (i = 0; i < num_recs; i++)
10606                 {
10607                   fixS *fix;
10608
10609                   /* Write the fixup.  */
10610                   gas_assert (cur_block);
10611                   fix = fix_new (frag_now, i * 8, 4,
10612                                  section_symbol (cur_block->sec),
10613                                  cur_block->offset,
10614                                  FALSE, BFD_RELOC_32);
10615                   fix->fx_file = "<internal>";
10616                   fix->fx_line = 0;
10617
10618                   /* Write the length.  */
10619                   md_number_to_chars (&frag_data[4 + i * 8],
10620                                       cur_block->size, 4);
10621                   cur_block = cur_block->next;
10622                 }
10623               frag_wane (frag_now);
10624               frag_new (0);
10625               frag_wane (frag_now);
10626             }
10627         }
10628     }
10629 }
10630
10631
10632 static void
10633 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
10634                                   const char *section_name_base,
10635                                   xt_section_type sec_type)
10636 {
10637   segT *seclist;
10638
10639   /* Walk over all of the current segments.
10640      Walk over each fragment.
10641      For each fragment that has instructions,
10642      build an instruction record (append where possible).  */
10643
10644   for (seclist = &stdoutput->sections;
10645        seclist && *seclist;
10646        seclist = &(*seclist)->next)
10647     {
10648       segT sec = *seclist;
10649
10650       if (exclude_section_from_property_tables (sec))
10651         continue;
10652
10653       if (section_has_xproperty (sec, flag_fn))
10654         {
10655           segment_info_type *xt_seg_info;
10656           xtensa_block_info **xt_blocks;
10657           segT prop_sec = xtensa_make_property_section (sec, section_name_base);
10658
10659           prop_sec->output_section = prop_sec;
10660           subseg_set (prop_sec, 0);
10661           xt_seg_info = seg_info (prop_sec);
10662           xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10663
10664           /* Walk over all of the frchains here and add new sections.  */
10665           add_xt_prop_frags (sec, xt_blocks, flag_fn);
10666         }
10667     }
10668
10669   /* Now we fill them out....  */
10670
10671   for (seclist = &stdoutput->sections;
10672        seclist && *seclist;
10673        seclist = &(*seclist)->next)
10674     {
10675       segment_info_type *seginfo;
10676       xtensa_block_info *block;
10677       segT sec = *seclist;
10678
10679       seginfo = seg_info (sec);
10680       block = seginfo->tc_segment_info_data.blocks[sec_type];
10681
10682       if (block)
10683         {
10684           xtensa_block_info *cur_block;
10685           int num_recs = 0;
10686           bfd_size_type rec_size;
10687
10688           for (cur_block = block; cur_block; cur_block = cur_block->next)
10689             num_recs++;
10690
10691           rec_size = num_recs * (8 + 4);
10692           bfd_set_section_size (stdoutput, sec, rec_size);
10693           /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10694
10695           if (num_recs)
10696             {
10697               char *frag_data;
10698               int i;
10699
10700               subseg_set (sec, 0);
10701               frag_data = frag_more (rec_size);
10702               cur_block = block;
10703               for (i = 0; i < num_recs; i++)
10704                 {
10705                   fixS *fix;
10706
10707                   /* Write the fixup.  */
10708                   gas_assert (cur_block);
10709                   fix = fix_new (frag_now, i * 12, 4,
10710                                  section_symbol (cur_block->sec),
10711                                  cur_block->offset,
10712                                  FALSE, BFD_RELOC_32);
10713                   fix->fx_file = "<internal>";
10714                   fix->fx_line = 0;
10715
10716                   /* Write the length.  */
10717                   md_number_to_chars (&frag_data[4 + i * 12],
10718                                       cur_block->size, 4);
10719                   md_number_to_chars (&frag_data[8 + i * 12],
10720                                       frag_flags_to_number (&cur_block->flags),
10721                                       sizeof (flagword));
10722                   cur_block = cur_block->next;
10723                 }
10724               frag_wane (frag_now);
10725               frag_new (0);
10726               frag_wane (frag_now);
10727             }
10728         }
10729     }
10730 }
10731
10732
10733 static bfd_boolean
10734 exclude_section_from_property_tables (segT sec)
10735 {
10736   flagword flags = bfd_get_section_flags (stdoutput, sec);
10737
10738   /* Sections that don't contribute to the memory footprint are excluded.  */
10739   if ((flags & SEC_DEBUGGING)
10740       || !(flags & SEC_ALLOC)
10741       || (flags & SEC_MERGE))
10742     return TRUE;
10743
10744   /* Linker cie and fde optimizations mess up property entries for
10745      eh_frame sections, but there is nothing inside them relevant to
10746      property tables anyway.  */
10747   if (strcmp (sec->name, ".eh_frame") == 0)
10748     return TRUE;
10749
10750   return FALSE;
10751 }
10752
10753
10754 static bfd_boolean
10755 section_has_property (segT sec, frag_predicate property_function)
10756 {
10757   segment_info_type *seginfo = seg_info (sec);
10758   fragS *fragP;
10759
10760   if (seginfo && seginfo->frchainP)
10761     {
10762       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10763         {
10764           if (property_function (fragP)
10765               && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10766             return TRUE;
10767         }
10768     }
10769   return FALSE;
10770 }
10771
10772
10773 static bfd_boolean
10774 section_has_xproperty (segT sec, frag_flags_fn property_function)
10775 {
10776   segment_info_type *seginfo = seg_info (sec);
10777   fragS *fragP;
10778
10779   if (seginfo && seginfo->frchainP)
10780     {
10781       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10782         {
10783           frag_flags prop_flags;
10784           property_function (fragP, &prop_flags);
10785           if (!xtensa_frag_flags_is_empty (&prop_flags))
10786             return TRUE;
10787         }
10788     }
10789   return FALSE;
10790 }
10791
10792
10793 /* Two types of block sections exist right now: literal and insns.  */
10794
10795 static void
10796 add_xt_block_frags (segT sec,
10797                     xtensa_block_info **xt_block,
10798                     frag_predicate property_function,
10799                     frag_predicate end_property_function)
10800 {
10801   fragS *fragP;
10802
10803   /* Build it if needed.  */
10804   while (*xt_block != NULL)
10805     xt_block = &(*xt_block)->next;
10806   /* We are either at NULL at the beginning or at the end.  */
10807
10808   /* Walk through the frags.  */
10809   if (seg_info (sec)->frchainP)
10810     {
10811       for (fragP = seg_info (sec)->frchainP->frch_root;
10812            fragP;
10813            fragP = fragP->fr_next)
10814         {
10815           if (property_function (fragP)
10816               && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10817             {
10818               if (*xt_block != NULL)
10819                 {
10820                   if ((*xt_block)->offset + (*xt_block)->size
10821                       == fragP->fr_address)
10822                     (*xt_block)->size += fragP->fr_fix;
10823                   else
10824                     xt_block = &((*xt_block)->next);
10825                 }
10826               if (*xt_block == NULL)
10827                 {
10828                   xtensa_block_info *new_block = (xtensa_block_info *)
10829                     xmalloc (sizeof (xtensa_block_info));
10830                   new_block->sec = sec;
10831                   new_block->offset = fragP->fr_address;
10832                   new_block->size = fragP->fr_fix;
10833                   new_block->next = NULL;
10834                   xtensa_frag_flags_init (&new_block->flags);
10835                   *xt_block = new_block;
10836                 }
10837               if (end_property_function
10838                   && end_property_function (fragP))
10839                 {
10840                   xt_block = &((*xt_block)->next);
10841                 }
10842             }
10843         }
10844     }
10845 }
10846
10847
10848 /* Break the encapsulation of add_xt_prop_frags here.  */
10849
10850 static bfd_boolean
10851 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
10852 {
10853   if (prop_flags->is_literal
10854       || prop_flags->is_insn
10855       || prop_flags->is_data
10856       || prop_flags->is_unreachable)
10857     return FALSE;
10858   return TRUE;
10859 }
10860
10861
10862 static void
10863 xtensa_frag_flags_init (frag_flags *prop_flags)
10864 {
10865   memset (prop_flags, 0, sizeof (frag_flags));
10866 }
10867
10868
10869 static void
10870 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
10871 {
10872   xtensa_frag_flags_init (prop_flags);
10873   if (fragP->tc_frag_data.is_literal)
10874     prop_flags->is_literal = TRUE;
10875   if (fragP->tc_frag_data.is_specific_opcode
10876       || fragP->tc_frag_data.is_no_transform)
10877     {
10878       prop_flags->is_no_transform = TRUE;
10879       if (xtensa_frag_flags_is_empty (prop_flags))
10880         prop_flags->is_data = TRUE;
10881     }
10882   if (fragP->tc_frag_data.is_unreachable)
10883     prop_flags->is_unreachable = TRUE;
10884   else if (fragP->tc_frag_data.is_insn)
10885     {
10886       prop_flags->is_insn = TRUE;
10887       if (fragP->tc_frag_data.is_loop_target)
10888         prop_flags->insn.is_loop_target = TRUE;
10889       if (fragP->tc_frag_data.is_branch_target)
10890         prop_flags->insn.is_branch_target = TRUE;
10891       if (fragP->tc_frag_data.is_no_density)
10892         prop_flags->insn.is_no_density = TRUE;
10893       if (fragP->tc_frag_data.use_absolute_literals)
10894         prop_flags->insn.is_abslit = TRUE;
10895     }
10896   if (fragP->tc_frag_data.is_align)
10897     {
10898       prop_flags->is_align = TRUE;
10899       prop_flags->alignment = fragP->tc_frag_data.alignment;
10900       if (xtensa_frag_flags_is_empty (prop_flags))
10901         prop_flags->is_data = TRUE;
10902     }
10903 }
10904
10905
10906 static flagword
10907 frag_flags_to_number (const frag_flags *prop_flags)
10908 {
10909   flagword num = 0;
10910   if (prop_flags->is_literal)
10911     num |= XTENSA_PROP_LITERAL;
10912   if (prop_flags->is_insn)
10913     num |= XTENSA_PROP_INSN;
10914   if (prop_flags->is_data)
10915     num |= XTENSA_PROP_DATA;
10916   if (prop_flags->is_unreachable)
10917     num |= XTENSA_PROP_UNREACHABLE;
10918   if (prop_flags->insn.is_loop_target)
10919     num |= XTENSA_PROP_INSN_LOOP_TARGET;
10920   if (prop_flags->insn.is_branch_target)
10921     {
10922       num |= XTENSA_PROP_INSN_BRANCH_TARGET;
10923       num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
10924     }
10925
10926   if (prop_flags->insn.is_no_density)
10927     num |= XTENSA_PROP_INSN_NO_DENSITY;
10928   if (prop_flags->is_no_transform)
10929     num |= XTENSA_PROP_NO_TRANSFORM;
10930   if (prop_flags->insn.is_no_reorder)
10931     num |= XTENSA_PROP_INSN_NO_REORDER;
10932   if (prop_flags->insn.is_abslit)
10933     num |= XTENSA_PROP_INSN_ABSLIT;
10934
10935   if (prop_flags->is_align)
10936     {
10937       num |= XTENSA_PROP_ALIGN;
10938       num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
10939     }
10940
10941   return num;
10942 }
10943
10944
10945 static bfd_boolean
10946 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
10947                               const frag_flags *prop_flags_2)
10948 {
10949   /* Cannot combine with an end marker.  */
10950
10951   if (prop_flags_1->is_literal != prop_flags_2->is_literal)
10952     return FALSE;
10953   if (prop_flags_1->is_insn != prop_flags_2->is_insn)
10954     return FALSE;
10955   if (prop_flags_1->is_data != prop_flags_2->is_data)
10956     return FALSE;
10957
10958   if (prop_flags_1->is_insn)
10959     {
10960       /* Properties of the beginning of the frag.  */
10961       if (prop_flags_2->insn.is_loop_target)
10962         return FALSE;
10963       if (prop_flags_2->insn.is_branch_target)
10964         return FALSE;
10965       if (prop_flags_1->insn.is_no_density !=
10966           prop_flags_2->insn.is_no_density)
10967         return FALSE;
10968       if (prop_flags_1->is_no_transform !=
10969           prop_flags_2->is_no_transform)
10970         return FALSE;
10971       if (prop_flags_1->insn.is_no_reorder !=
10972           prop_flags_2->insn.is_no_reorder)
10973         return FALSE;
10974       if (prop_flags_1->insn.is_abslit !=
10975           prop_flags_2->insn.is_abslit)
10976         return FALSE;
10977     }
10978
10979   if (prop_flags_1->is_align)
10980     return FALSE;
10981
10982   return TRUE;
10983 }
10984
10985
10986 static bfd_vma
10987 xt_block_aligned_size (const xtensa_block_info *xt_block)
10988 {
10989   bfd_vma end_addr;
10990   unsigned align_bits;
10991
10992   if (!xt_block->flags.is_align)
10993     return xt_block->size;
10994
10995   end_addr = xt_block->offset + xt_block->size;
10996   align_bits = xt_block->flags.alignment;
10997   end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
10998   return end_addr - xt_block->offset;
10999 }
11000
11001
11002 static bfd_boolean
11003 xtensa_xt_block_combine (xtensa_block_info *xt_block,
11004                          const xtensa_block_info *xt_block_2)
11005 {
11006   if (xt_block->sec != xt_block_2->sec)
11007     return FALSE;
11008   if (xt_block->offset + xt_block_aligned_size (xt_block)
11009       != xt_block_2->offset)
11010     return FALSE;
11011
11012   if (xt_block_2->size == 0
11013       && (!xt_block_2->flags.is_unreachable
11014           || xt_block->flags.is_unreachable))
11015     {
11016       if (xt_block_2->flags.is_align
11017           && xt_block->flags.is_align)
11018         {
11019           /* Nothing needed.  */
11020           if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
11021             return TRUE;
11022         }
11023       else
11024         {
11025           if (xt_block_2->flags.is_align)
11026             {
11027               /* Push alignment to previous entry.  */
11028               xt_block->flags.is_align = xt_block_2->flags.is_align;
11029               xt_block->flags.alignment = xt_block_2->flags.alignment;
11030             }
11031           return TRUE;
11032         }
11033     }
11034   if (!xtensa_frag_flags_combinable (&xt_block->flags,
11035                                      &xt_block_2->flags))
11036     return FALSE;
11037
11038   xt_block->size += xt_block_2->size;
11039
11040   if (xt_block_2->flags.is_align)
11041     {
11042       xt_block->flags.is_align = TRUE;
11043       xt_block->flags.alignment = xt_block_2->flags.alignment;
11044     }
11045
11046   return TRUE;
11047 }
11048
11049
11050 static void
11051 add_xt_prop_frags (segT sec,
11052                    xtensa_block_info **xt_block,
11053                    frag_flags_fn property_function)
11054 {
11055   fragS *fragP;
11056
11057   /* Build it if needed.  */
11058   while (*xt_block != NULL)
11059     {
11060       xt_block = &(*xt_block)->next;
11061     }
11062   /* We are either at NULL at the beginning or at the end.  */
11063
11064   /* Walk through the frags.  */
11065   if (seg_info (sec)->frchainP)
11066     {
11067       for (fragP = seg_info (sec)->frchainP->frch_root; fragP;
11068            fragP = fragP->fr_next)
11069         {
11070           xtensa_block_info tmp_block;
11071           tmp_block.sec = sec;
11072           tmp_block.offset = fragP->fr_address;
11073           tmp_block.size = fragP->fr_fix;
11074           tmp_block.next = NULL;
11075           property_function (fragP, &tmp_block.flags);
11076
11077           if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
11078             /* && fragP->fr_fix != 0) */
11079             {
11080               if ((*xt_block) == NULL
11081                   || !xtensa_xt_block_combine (*xt_block, &tmp_block))
11082                 {
11083                   xtensa_block_info *new_block;
11084                   if ((*xt_block) != NULL)
11085                     xt_block = &(*xt_block)->next;
11086                   new_block = (xtensa_block_info *)
11087                     xmalloc (sizeof (xtensa_block_info));
11088                   *new_block = tmp_block;
11089                   *xt_block = new_block;
11090                 }
11091             }
11092         }
11093     }
11094 }
11095
11096 \f
11097 /* op_placement_info_table */
11098
11099 /* op_placement_info makes it easier to determine which
11100    ops can go in which slots.  */
11101
11102 static void
11103 init_op_placement_info_table (void)
11104 {
11105   xtensa_isa isa = xtensa_default_isa;
11106   xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
11107   xtensa_opcode opcode;
11108   xtensa_format fmt;
11109   int slot;
11110   int num_opcodes = xtensa_isa_num_opcodes (isa);
11111
11112   op_placement_table = (op_placement_info_table)
11113     xmalloc (sizeof (op_placement_info) * num_opcodes);
11114   gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
11115
11116   for (opcode = 0; opcode < num_opcodes; opcode++)
11117     {
11118       op_placement_info *opi = &op_placement_table[opcode];
11119       /* FIXME: Make tinsn allocation dynamic.  */
11120       if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS)
11121         as_fatal (_("too many operands in instruction"));
11122       opi->narrowest = XTENSA_UNDEFINED;
11123       opi->narrowest_size = 0x7F;
11124       opi->narrowest_slot = 0;
11125       opi->formats = 0;
11126       opi->num_formats = 0;
11127       opi->issuef = 0;
11128       for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
11129         {
11130           opi->slots[fmt] = 0;
11131           for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
11132             {
11133               if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
11134                 {
11135                   int fmt_length = xtensa_format_length (isa, fmt);
11136                   opi->issuef++;
11137                   set_bit (fmt, opi->formats);
11138                   set_bit (slot, opi->slots[fmt]);
11139                   if (fmt_length < opi->narrowest_size
11140                       || (fmt_length == opi->narrowest_size
11141                           && (xtensa_format_num_slots (isa, fmt)
11142                               < xtensa_format_num_slots (isa,
11143                                                          opi->narrowest))))
11144                     {
11145                       opi->narrowest = fmt;
11146                       opi->narrowest_size = fmt_length;
11147                       opi->narrowest_slot = slot;
11148                     }
11149                 }
11150             }
11151           if (opi->formats)
11152             opi->num_formats++;
11153         }
11154     }
11155   xtensa_insnbuf_free (isa, ibuf);
11156 }
11157
11158
11159 bfd_boolean
11160 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
11161 {
11162   return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
11163 }
11164
11165
11166 /* If the opcode is available in a single slot format, return its size.  */
11167
11168 static int
11169 xg_get_single_size (xtensa_opcode opcode)
11170 {
11171   return op_placement_table[opcode].narrowest_size;
11172 }
11173
11174
11175 static xtensa_format
11176 xg_get_single_format (xtensa_opcode opcode)
11177 {
11178   return op_placement_table[opcode].narrowest;
11179 }
11180
11181
11182 static int
11183 xg_get_single_slot (xtensa_opcode opcode)
11184 {
11185   return op_placement_table[opcode].narrowest_slot;
11186 }
11187
11188 \f
11189 /* Instruction Stack Functions (from "xtensa-istack.h").  */
11190
11191 void
11192 istack_init (IStack *stack)
11193 {
11194   memset (stack, 0, sizeof (IStack));
11195   stack->ninsn = 0;
11196 }
11197
11198
11199 bfd_boolean
11200 istack_empty (IStack *stack)
11201 {
11202   return (stack->ninsn == 0);
11203 }
11204
11205
11206 bfd_boolean
11207 istack_full (IStack *stack)
11208 {
11209   return (stack->ninsn == MAX_ISTACK);
11210 }
11211
11212
11213 /* Return a pointer to the top IStack entry.
11214    It is an error to call this if istack_empty () is TRUE. */
11215
11216 TInsn *
11217 istack_top (IStack *stack)
11218 {
11219   int rec = stack->ninsn - 1;
11220   gas_assert (!istack_empty (stack));
11221   return &stack->insn[rec];
11222 }
11223
11224
11225 /* Add a new TInsn to an IStack.
11226    It is an error to call this if istack_full () is TRUE.  */
11227
11228 void
11229 istack_push (IStack *stack, TInsn *insn)
11230 {
11231   int rec = stack->ninsn;
11232   gas_assert (!istack_full (stack));
11233   stack->insn[rec] = *insn;
11234   stack->ninsn++;
11235 }
11236
11237
11238 /* Clear space for the next TInsn on the IStack and return a pointer
11239    to it.  It is an error to call this if istack_full () is TRUE.  */
11240
11241 TInsn *
11242 istack_push_space (IStack *stack)
11243 {
11244   int rec = stack->ninsn;
11245   TInsn *insn;
11246   gas_assert (!istack_full (stack));
11247   insn = &stack->insn[rec];
11248   tinsn_init (insn);
11249   stack->ninsn++;
11250   return insn;
11251 }
11252
11253
11254 /* Remove the last pushed instruction.  It is an error to call this if
11255    istack_empty () returns TRUE.  */
11256
11257 void
11258 istack_pop (IStack *stack)
11259 {
11260   int rec = stack->ninsn - 1;
11261   gas_assert (!istack_empty (stack));
11262   stack->ninsn--;
11263   tinsn_init (&stack->insn[rec]);
11264 }
11265
11266 \f
11267 /* TInsn functions.  */
11268
11269 void
11270 tinsn_init (TInsn *dst)
11271 {
11272   memset (dst, 0, sizeof (TInsn));
11273 }
11274
11275
11276 /* Return TRUE if ANY of the operands in the insn are symbolic.  */
11277
11278 static bfd_boolean
11279 tinsn_has_symbolic_operands (const TInsn *insn)
11280 {
11281   int i;
11282   int n = insn->ntok;
11283
11284   gas_assert (insn->insn_type == ITYPE_INSN);
11285
11286   for (i = 0; i < n; ++i)
11287     {
11288       switch (insn->tok[i].X_op)
11289         {
11290         case O_register:
11291         case O_constant:
11292           break;
11293         default:
11294           return TRUE;
11295         }
11296     }
11297   return FALSE;
11298 }
11299
11300
11301 bfd_boolean
11302 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
11303 {
11304   xtensa_isa isa = xtensa_default_isa;
11305   int i;
11306   int n = insn->ntok;
11307
11308   gas_assert (insn->insn_type == ITYPE_INSN);
11309
11310   for (i = 0; i < n; ++i)
11311     {
11312       switch (insn->tok[i].X_op)
11313         {
11314         case O_register:
11315         case O_constant:
11316           break;
11317         case O_big:
11318         case O_illegal:
11319         case O_absent:
11320           /* Errors for these types are caught later.  */
11321           break;
11322         case O_hi16:
11323         case O_lo16:
11324         default:
11325           /* Symbolic immediates are only allowed on the last immediate
11326              operand.  At this time, CONST16 is the only opcode where we
11327              support non-PC-relative relocations.  */
11328           if (i != get_relaxable_immed (insn->opcode)
11329               || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
11330                   && insn->opcode != xtensa_const16_opcode))
11331             {
11332               as_bad (_("invalid symbolic operand"));
11333               return TRUE;
11334             }
11335         }
11336     }
11337   return FALSE;
11338 }
11339
11340
11341 /* For assembly code with complex expressions (e.g. subtraction),
11342    we have to build them in the literal pool so that
11343    their results are calculated correctly after relaxation.
11344    The relaxation only handles expressions that
11345    boil down to SYMBOL + OFFSET.  */
11346
11347 static bfd_boolean
11348 tinsn_has_complex_operands (const TInsn *insn)
11349 {
11350   int i;
11351   int n = insn->ntok;
11352   gas_assert (insn->insn_type == ITYPE_INSN);
11353   for (i = 0; i < n; ++i)
11354     {
11355       switch (insn->tok[i].X_op)
11356         {
11357         case O_register:
11358         case O_constant:
11359         case O_symbol:
11360         case O_lo16:
11361         case O_hi16:
11362           break;
11363         default:
11364           return TRUE;
11365         }
11366     }
11367   return FALSE;
11368 }
11369
11370
11371 /* Encode a TInsn opcode and its constant operands into slotbuf.
11372    Return TRUE if there is a symbol in the immediate field.  This
11373    function assumes that:
11374    1) The number of operands are correct.
11375    2) The insn_type is ITYPE_INSN.
11376    3) The opcode can be encoded in the specified format and slot.
11377    4) Operands are either O_constant or O_symbol, and all constants fit.  */
11378
11379 static bfd_boolean
11380 tinsn_to_slotbuf (xtensa_format fmt,
11381                   int slot,
11382                   TInsn *tinsn,
11383                   xtensa_insnbuf slotbuf)
11384 {
11385   xtensa_isa isa = xtensa_default_isa;
11386   xtensa_opcode opcode = tinsn->opcode;
11387   bfd_boolean has_fixup = FALSE;
11388   int noperands = xtensa_opcode_num_operands (isa, opcode);
11389   int i;
11390
11391   gas_assert (tinsn->insn_type == ITYPE_INSN);
11392   if (noperands != tinsn->ntok)
11393     as_fatal (_("operand number mismatch"));
11394
11395   if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
11396     {
11397       as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11398               xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
11399       return FALSE;
11400     }
11401
11402   for (i = 0; i < noperands; i++)
11403     {
11404       expressionS *expr = &tinsn->tok[i];
11405       int rc;
11406       unsigned line;
11407       char *file_name;
11408       uint32 opnd_value;
11409
11410       switch (expr->X_op)
11411         {
11412         case O_register:
11413           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11414             break;
11415           /* The register number has already been checked in
11416              expression_maybe_register, so we don't need to check here.  */
11417           opnd_value = expr->X_add_number;
11418           (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11419           rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
11420                                          opnd_value);
11421           if (rc != 0)
11422             as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
11423           break;
11424
11425         case O_constant:
11426           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11427             break;
11428           as_where (&file_name, &line);
11429           /* It is a constant and we called this function
11430              then we have to try to fit it.  */
11431           xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
11432                                       expr->X_add_number, file_name, line);
11433           break;
11434
11435         default:
11436           has_fixup = TRUE;
11437           break;
11438         }
11439     }
11440
11441   return has_fixup;
11442 }
11443
11444
11445 /* Encode a single TInsn into an insnbuf.  If the opcode can only be encoded
11446    into a multi-slot instruction, fill the other slots with NOPs.
11447    Return TRUE if there is a symbol in the immediate field.  See also the
11448    assumptions listed for tinsn_to_slotbuf.  */
11449
11450 static bfd_boolean
11451 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
11452 {
11453   static xtensa_insnbuf slotbuf = 0;
11454   static vliw_insn vinsn;
11455   xtensa_isa isa = xtensa_default_isa;
11456   bfd_boolean has_fixup = FALSE;
11457   int i;
11458
11459   if (!slotbuf)
11460     {
11461       slotbuf = xtensa_insnbuf_alloc (isa);
11462       xg_init_vinsn (&vinsn);
11463     }
11464
11465   xg_clear_vinsn (&vinsn);
11466
11467   bundle_tinsn (tinsn, &vinsn);
11468
11469   xtensa_format_encode (isa, vinsn.format, insnbuf);
11470
11471   for (i = 0; i < vinsn.num_slots; i++)
11472     {
11473       /* Only one slot may have a fix-up because the rest contains NOPs.  */
11474       has_fixup |=
11475         tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]);
11476       xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]);
11477     }
11478
11479   return has_fixup;
11480 }
11481
11482
11483 /* Check the instruction arguments.  Return TRUE on failure.  */
11484
11485 static bfd_boolean
11486 tinsn_check_arguments (const TInsn *insn)
11487 {
11488   xtensa_isa isa = xtensa_default_isa;
11489   xtensa_opcode opcode = insn->opcode;
11490   xtensa_regfile t1_regfile, t2_regfile;
11491   int t1_reg, t2_reg;
11492   int t1_base_reg, t1_last_reg;
11493   int t2_base_reg, t2_last_reg;
11494   char t1_inout, t2_inout;
11495   int i, j;
11496
11497   if (opcode == XTENSA_UNDEFINED)
11498     {
11499       as_bad (_("invalid opcode"));
11500       return TRUE;
11501     }
11502
11503   if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
11504     {
11505       as_bad (_("too few operands"));
11506       return TRUE;
11507     }
11508
11509   if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
11510     {
11511       as_bad (_("too many operands"));
11512       return TRUE;
11513     }
11514
11515   /* Check registers.  */
11516   for (j = 0; j < insn->ntok; j++)
11517     {
11518       if (xtensa_operand_is_register (isa, insn->opcode, j) != 1)
11519         continue;
11520
11521       t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j);
11522       t2_base_reg = insn->tok[j].X_add_number;
11523       t2_last_reg
11524         = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j);
11525
11526       for (i = 0; i < insn->ntok; i++)
11527         {
11528           if (i == j)
11529             continue;
11530
11531           if (xtensa_operand_is_register (isa, insn->opcode, i) != 1)
11532             continue;
11533
11534           t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i);
11535
11536           if (t1_regfile != t2_regfile)
11537             continue;
11538
11539           t1_inout = xtensa_operand_inout (isa, insn->opcode, i);
11540           t2_inout = xtensa_operand_inout (isa, insn->opcode, j);
11541
11542           t1_base_reg = insn->tok[i].X_add_number;
11543           t1_last_reg = (t1_base_reg
11544                          + xtensa_operand_num_regs (isa, insn->opcode, i));
11545
11546           for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
11547             {
11548               for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
11549                 {
11550                   if (t1_reg != t2_reg)
11551                     continue;
11552
11553                   if (t1_inout != 'i' && t2_inout != 'i')
11554                     {
11555                       as_bad (_("multiple writes to the same register"));
11556                       return TRUE;
11557                     }
11558                 }
11559             }
11560         }
11561     }
11562   return FALSE;
11563 }
11564
11565
11566 /* Load an instruction from its encoded form.  */
11567
11568 static void
11569 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
11570 {
11571   vliw_insn vinsn;
11572
11573   xg_init_vinsn (&vinsn);
11574   vinsn_from_chars (&vinsn, f);
11575
11576   *tinsn = vinsn.slots[slot];
11577   xg_free_vinsn (&vinsn);
11578 }
11579
11580
11581 static void
11582 tinsn_from_insnbuf (TInsn *tinsn,
11583                     xtensa_insnbuf slotbuf,
11584                     xtensa_format fmt,
11585                     int slot)
11586 {
11587   int i;
11588   xtensa_isa isa = xtensa_default_isa;
11589
11590   /* Find the immed.  */
11591   tinsn_init (tinsn);
11592   tinsn->insn_type = ITYPE_INSN;
11593   tinsn->is_specific_opcode = FALSE;    /* must not be specific */
11594   tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
11595   tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
11596   for (i = 0; i < tinsn->ntok; i++)
11597     {
11598       set_expr_const (&tinsn->tok[i],
11599                       xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
11600                                                   tinsn->opcode, i));
11601     }
11602 }
11603
11604
11605 /* Read the value of the relaxable immed from the fr_symbol and fr_offset.  */
11606
11607 static void
11608 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
11609 {
11610   xtensa_opcode opcode = tinsn->opcode;
11611   int opnum;
11612
11613   if (fragP->tc_frag_data.slot_symbols[slot])
11614     {
11615       opnum = get_relaxable_immed (opcode);
11616       gas_assert (opnum >= 0);
11617       set_expr_symbol_offset (&tinsn->tok[opnum],
11618                               fragP->tc_frag_data.slot_symbols[slot],
11619                               fragP->tc_frag_data.slot_offsets[slot]);
11620     }
11621   tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot];
11622 }
11623
11624
11625 static int
11626 get_num_stack_text_bytes (IStack *istack)
11627 {
11628   int i;
11629   int text_bytes = 0;
11630
11631   for (i = 0; i < istack->ninsn; i++)
11632     {
11633       TInsn *tinsn = &istack->insn[i];
11634       if (tinsn->insn_type == ITYPE_INSN)
11635         text_bytes += xg_get_single_size (tinsn->opcode);
11636     }
11637   return text_bytes;
11638 }
11639
11640
11641 static int
11642 get_num_stack_literal_bytes (IStack *istack)
11643 {
11644   int i;
11645   int lit_bytes = 0;
11646
11647   for (i = 0; i < istack->ninsn; i++)
11648     {
11649       TInsn *tinsn = &istack->insn[i];
11650       if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
11651         lit_bytes += 4;
11652     }
11653   return lit_bytes;
11654 }
11655
11656 \f
11657 /* vliw_insn functions.  */
11658
11659 static void
11660 xg_init_vinsn (vliw_insn *v)
11661 {
11662   int i;
11663   xtensa_isa isa = xtensa_default_isa;
11664
11665   xg_clear_vinsn (v);
11666
11667   v->insnbuf = xtensa_insnbuf_alloc (isa);
11668   if (v->insnbuf == NULL)
11669     as_fatal (_("out of memory"));
11670
11671   for (i = 0; i < config_max_slots; i++)
11672     {
11673       v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
11674       if (v->slotbuf[i] == NULL)
11675         as_fatal (_("out of memory"));
11676     }
11677 }
11678
11679
11680 static void
11681 xg_clear_vinsn (vliw_insn *v)
11682 {
11683   int i;
11684
11685   memset (v, 0, offsetof (vliw_insn, slots)
11686                 + sizeof(TInsn) * config_max_slots);
11687
11688   v->format = XTENSA_UNDEFINED;
11689   v->num_slots = 0;
11690   v->inside_bundle = FALSE;
11691
11692   if (xt_saved_debug_type != DEBUG_NONE)
11693     debug_type = xt_saved_debug_type;
11694
11695   for (i = 0; i < config_max_slots; i++)
11696     v->slots[i].opcode = XTENSA_UNDEFINED;
11697 }
11698
11699
11700 static void
11701 xg_copy_vinsn (vliw_insn *dst, vliw_insn *src)
11702 {
11703   memcpy (dst, src,
11704           offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn));
11705   dst->insnbuf = src->insnbuf;
11706   memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf));
11707 }
11708
11709
11710 static bfd_boolean
11711 vinsn_has_specific_opcodes (vliw_insn *v)
11712 {
11713   int i;
11714
11715   for (i = 0; i < v->num_slots; i++)
11716     {
11717       if (v->slots[i].is_specific_opcode)
11718         return TRUE;
11719     }
11720   return FALSE;
11721 }
11722
11723
11724 static void
11725 xg_free_vinsn (vliw_insn *v)
11726 {
11727   int i;
11728   xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
11729   for (i = 0; i < config_max_slots; i++)
11730     xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
11731 }
11732
11733
11734 /* Encode a vliw_insn into an insnbuf.  Return TRUE if there are any symbolic
11735    operands.  See also the assumptions listed for tinsn_to_slotbuf.  */
11736
11737 static bfd_boolean
11738 vinsn_to_insnbuf (vliw_insn *vinsn,
11739                   char *frag_offset,
11740                   fragS *fragP,
11741                   bfd_boolean record_fixup)
11742 {
11743   xtensa_isa isa = xtensa_default_isa;
11744   xtensa_format fmt = vinsn->format;
11745   xtensa_insnbuf insnbuf = vinsn->insnbuf;
11746   int slot;
11747   bfd_boolean has_fixup = FALSE;
11748
11749   xtensa_format_encode (isa, fmt, insnbuf);
11750
11751   for (slot = 0; slot < vinsn->num_slots; slot++)
11752     {
11753       TInsn *tinsn = &vinsn->slots[slot];
11754       expressionS *extra_arg = &tinsn->extra_arg;
11755       bfd_boolean tinsn_has_fixup =
11756         tinsn_to_slotbuf (vinsn->format, slot, tinsn,
11757                           vinsn->slotbuf[slot]);
11758
11759       xtensa_format_set_slot (isa, fmt, slot,
11760                               insnbuf, vinsn->slotbuf[slot]);
11761       if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register)
11762         {
11763           if (vinsn->num_slots != 1)
11764             as_bad (_("TLS relocation not allowed in FLIX bundle"));
11765           else if (record_fixup)
11766             /* Instructions that generate TLS relocations should always be
11767                relaxed in the front-end.  If "record_fixup" is set, then this
11768                function is being called during back-end relaxation, so flag
11769                the unexpected behavior as an error.  */
11770             as_bad (_("unexpected TLS relocation"));
11771           else
11772             fix_new (fragP, frag_offset - fragP->fr_literal,
11773                      xtensa_format_length (isa, fmt),
11774                      extra_arg->X_add_symbol, extra_arg->X_add_number,
11775                      FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE));
11776         }
11777       if (tinsn_has_fixup)
11778         {
11779           int i;
11780           xtensa_opcode opcode = tinsn->opcode;
11781           int noperands = xtensa_opcode_num_operands (isa, opcode);
11782           has_fixup = TRUE;
11783
11784           for (i = 0; i < noperands; i++)
11785             {
11786               expressionS* expr = &tinsn->tok[i];
11787               switch (expr->X_op)
11788                 {
11789                 case O_symbol:
11790                 case O_lo16:
11791                 case O_hi16:
11792                   if (get_relaxable_immed (opcode) == i)
11793                     {
11794                       /* Add a fix record for the instruction, except if this
11795                          function is being called prior to relaxation, i.e.,
11796                          if record_fixup is false, and the instruction might
11797                          be relaxed later.  */
11798                       if (record_fixup
11799                           || tinsn->is_specific_opcode
11800                           || !xg_is_relaxable_insn (tinsn, 0))
11801                         {
11802                           xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP,
11803                                              frag_offset - fragP->fr_literal);
11804                         }
11805                       else
11806                         {
11807                           if (expr->X_op != O_symbol)
11808                             as_bad (_("invalid operand"));
11809                           tinsn->symbol = expr->X_add_symbol;
11810                           tinsn->offset = expr->X_add_number;
11811                         }
11812                     }
11813                   else
11814                     as_bad (_("symbolic operand not allowed"));
11815                   break;
11816
11817                 case O_constant:
11818                 case O_register:
11819                   break;
11820
11821                 default:
11822                   as_bad (_("expression too complex"));
11823                   break;
11824                 }
11825             }
11826         }
11827     }
11828
11829   return has_fixup;
11830 }
11831
11832
11833 static void
11834 vinsn_from_chars (vliw_insn *vinsn, char *f)
11835 {
11836   static xtensa_insnbuf insnbuf = NULL;
11837   static xtensa_insnbuf slotbuf = NULL;
11838   int i;
11839   xtensa_format fmt;
11840   xtensa_isa isa = xtensa_default_isa;
11841
11842   if (!insnbuf)
11843     {
11844       insnbuf = xtensa_insnbuf_alloc (isa);
11845       slotbuf = xtensa_insnbuf_alloc (isa);
11846     }
11847
11848   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
11849   fmt = xtensa_format_decode (isa, insnbuf);
11850   if (fmt == XTENSA_UNDEFINED)
11851     as_fatal (_("cannot decode instruction format"));
11852   vinsn->format = fmt;
11853   vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
11854
11855   for (i = 0; i < vinsn->num_slots; i++)
11856     {
11857       TInsn *tinsn = &vinsn->slots[i];
11858       xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
11859       tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
11860     }
11861 }
11862
11863 \f
11864 /* Expression utilities.  */
11865
11866 /* Return TRUE if the expression is an integer constant.  */
11867
11868 bfd_boolean
11869 expr_is_const (const expressionS *s)
11870 {
11871   return (s->X_op == O_constant);
11872 }
11873
11874
11875 /* Get the expression constant.
11876    Calling this is illegal if expr_is_const () returns TRUE.  */
11877
11878 offsetT
11879 get_expr_const (const expressionS *s)
11880 {
11881   gas_assert (expr_is_const (s));
11882   return s->X_add_number;
11883 }
11884
11885
11886 /* Set the expression to a constant value.  */
11887
11888 void
11889 set_expr_const (expressionS *s, offsetT val)
11890 {
11891   s->X_op = O_constant;
11892   s->X_add_number = val;
11893   s->X_add_symbol = NULL;
11894   s->X_op_symbol = NULL;
11895 }
11896
11897
11898 bfd_boolean
11899 expr_is_register (const expressionS *s)
11900 {
11901   return (s->X_op == O_register);
11902 }
11903
11904
11905 /* Get the expression constant.
11906    Calling this is illegal if expr_is_const () returns TRUE.  */
11907
11908 offsetT
11909 get_expr_register (const expressionS *s)
11910 {
11911   gas_assert (expr_is_register (s));
11912   return s->X_add_number;
11913 }
11914
11915
11916 /* Set the expression to a symbol + constant offset.  */
11917
11918 void
11919 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
11920 {
11921   s->X_op = O_symbol;
11922   s->X_add_symbol = sym;
11923   s->X_op_symbol = NULL;        /* unused */
11924   s->X_add_number = offset;
11925 }
11926
11927
11928 /* Return TRUE if the two expressions are equal.  */
11929
11930 bfd_boolean
11931 expr_is_equal (expressionS *s1, expressionS *s2)
11932 {
11933   if (s1->X_op != s2->X_op)
11934     return FALSE;
11935   if (s1->X_add_symbol != s2->X_add_symbol)
11936     return FALSE;
11937   if (s1->X_op_symbol != s2->X_op_symbol)
11938     return FALSE;
11939   if (s1->X_add_number != s2->X_add_number)
11940     return FALSE;
11941   return TRUE;
11942 }
11943
11944
11945 static void
11946 copy_expr (expressionS *dst, const expressionS *src)
11947 {
11948   memcpy (dst, src, sizeof (expressionS));
11949 }
11950
11951 \f
11952 /* Support for the "--rename-section" option.  */
11953
11954 struct rename_section_struct
11955 {
11956   char *old_name;
11957   char *new_name;
11958   struct rename_section_struct *next;
11959 };
11960
11961 static struct rename_section_struct *section_rename;
11962
11963
11964 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11965    entries to the section_rename list.  Note: Specifying multiple
11966    renamings separated by colons is not documented and is retained only
11967    for backward compatibility.  */
11968
11969 static void
11970 build_section_rename (const char *arg)
11971 {
11972   struct rename_section_struct *r;
11973   char *this_arg = NULL;
11974   char *next_arg = NULL;
11975
11976   for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
11977     {
11978       char *old_name, *new_name;
11979
11980       if (this_arg)
11981         {
11982           next_arg = strchr (this_arg, ':');
11983           if (next_arg)
11984             {
11985               *next_arg = '\0';
11986               next_arg++;
11987             }
11988         }
11989
11990       old_name = this_arg;
11991       new_name = strchr (this_arg, '=');
11992
11993       if (*old_name == '\0')
11994         {
11995           as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11996           continue;
11997         }
11998       if (!new_name || new_name[1] == '\0')
11999         {
12000           as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12001                    old_name);
12002           continue;
12003         }
12004       *new_name = '\0';
12005       new_name++;
12006
12007       /* Check for invalid section renaming.  */
12008       for (r = section_rename; r != NULL; r = r->next)
12009         {
12010           if (strcmp (r->old_name, old_name) == 0)
12011             as_bad (_("section %s renamed multiple times"), old_name);
12012           if (strcmp (r->new_name, new_name) == 0)
12013             as_bad (_("multiple sections remapped to output section %s"),
12014                     new_name);
12015         }
12016
12017       /* Now add it.  */
12018       r = (struct rename_section_struct *)
12019         xmalloc (sizeof (struct rename_section_struct));
12020       r->old_name = xstrdup (old_name);
12021       r->new_name = xstrdup (new_name);
12022       r->next = section_rename;
12023       section_rename = r;
12024     }
12025 }
12026
12027
12028 char *
12029 xtensa_section_rename (char *name)
12030 {
12031   struct rename_section_struct *r = section_rename;
12032
12033   for (r = section_rename; r != NULL; r = r->next)
12034     {
12035       if (strcmp (r->old_name, name) == 0)
12036         return r->new_name;
12037     }
12038
12039   return name;
12040 }