gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2024 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{cortex-a78c},
  74 @code{cortex-a510},
  75 @code{cortex-a520},
  76 @code{cortex-a710},
  77 @code{cortex-a720},
  78 @code{ares},
  79 @code{exynos-m1},
  80 @code{falkor},
  81 @code{neoverse-n1},
  82 @code{neoverse-n2},
  83 @code{neoverse-e1},
  84 @code{neoverse-v1},
  85 @code{qdf24xx},
  86 @code{saphira},
  87 @code{thunderx},
  88 @code{vulcan},
  89 @code{xgene1}
  90 @code{xgene2},
  91 @code{cortex-r82},
  92 @code{cortex-x1},
  93 @code{cortex-x2},
  94 @code{cortex-x3},
  95 and
  96 @code{cortex-x4}.
  97 The special name @code{all} may be used to allow the assembler to accept
  98 instructions valid for any supported processor, including all optional
  99 extensions.
 100
 101 In addition to the basic instruction set, the assembler can be told to
 102 accept, or restrict, various extension mnemonics that extend the
 103 processor.  @xref{AArch64 Extensions}.
 104
 105 If some implementations of a particular processor can have an
 106 extension, then then those extensions are automatically enabled.
 107 Consequently, you will not normally have to specify any additional
 108 extensions.
 109
 110 @cindex @option{-march=} command-line option, AArch64
 111 @item -march=@var{architecture}[+@var{extension}@dots{}]
 112 This option specifies the target architecture.  The assembler will
 113 issue an error message if an attempt is made to assemble an
 114 instruction which will not execute on the target architecture.  The
 115 following architecture names are recognized: @code{armv8-a},
 116 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 117 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a},
 118 @code{armv8.9-a}, @code{armv8-r}, @code{armv9-a}, @code{armv9.1-a},
 119 @code{armv9.2-a}, @code{armv9.3-a} and @code{armv9.4-a}.
 120
 121 If both @option{-mcpu} and @option{-march} are specified, the
 122 assembler will use the setting for @option{-mcpu}.  If neither are
 123 specified, the assembler will default to @option{-mcpu=all}.
 124
 125 The architecture option can be extended with the same instruction set
 126 extension options as the @option{-mcpu} option.  Unlike
 127 @option{-mcpu}, extensions are not always enabled by default,
 128 @xref{AArch64 Extensions}.
 129
 130 @cindex @code{-mverbose-error} command-line option, AArch64
 131 @item -mverbose-error
 132 This option enables verbose error messages for AArch64 gas.  This option
 133 is enabled by default.
 134
 135 @cindex @code{-mno-verbose-error} command-line option, AArch64
 136 @item -mno-verbose-error
 137 This option disables verbose error messages in AArch64 gas.
 138
 139 @end table
 140 @c man end
 141
 142 @node AArch64 Extensions
 143 @section Architecture Extensions
 144
 145 The table below lists the permitted architecture extensions that are
 146 supported by the assembler and the conditions under which they are
 147 automatically enabled.
 148
 149 Multiple extensions may be specified, separated by a @code{+}.
 150 Extension mnemonics may also be removed from those the assembler
 151 accepts.  This is done by prepending @code{no} to the option that adds
 152 the extension.  Extensions that are removed must be listed after all
 153 extensions that have been added.
 154
 155 Enabling an extension that requires other extensions will
 156 automatically cause those extensions to be enabled.  Similarly,
 157 disabling an extension that is required by other extensions will
 158 automatically cause those extensions to be disabled.
 159
 160 @multitable @columnfractions .12 .17 .17 .54
 161 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 162  @tab Description
 163 @item @code{aes} @tab ARMv8-A @tab No
 164  @tab Enable the AES cryptographic extensions. This implies @code{fp} and
 165  @code{simd}.
 166 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 167  @tab Enable BFloat16 extension.
 168 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 169  @tab Enable the complex number SIMD extensions.  This implies @code{fp16} and
 170  @code{simd}.
 171 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 172  @tab Enable CRC instructions.
 173 @item @code{crypto} @tab ARMv8-A @tab No
 174  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd},
 175  @code{aes} and @code{sha2}.
 176 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 177  @tab Enable the Dot Product extension.  This implies @code{simd}.
 178 @item @code{f32mm} @tab ARMv8.2-A @tab No
 179  @tab Enable F32 Matrix Multiply extension.  This implies @code{sve}.
 180 @item @code{f64mm} @tab ARMv8.2-A @tab No
 181  @tab Enable F64 Matrix Multiply extension.  This implies @code{sve}.
 182 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 183  @tab Enable Flag Manipulation instructions.
 184 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 185  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support. This
 186  implies @code{fp} and  @code{fp16}.
 187 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 188  @tab Enable ARMv8.2 16-bit floating-point support.  This implies @code{fp}.
 189 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 190  @tab Enable floating-point extensions.
 191 @item @code{hbc} @tab @tab Armv8.8-A or later
 192  @tab Enable Armv8.8-A hinted conditional branch instructions
 193 @item @code{cssc} @tab @tab Armv8.7-A or later
 194  @tab Enable Armv8.9-A Common Short Sequence Compression instructions.
 195 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 196  @tab Enable Int8 Matrix Multiply extension.
 197 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 198  @tab Enable Limited Ordering Regions extensions.
 199 @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
 200  @tab Enable 64 Byte Loads/Stores.
 201 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 202  @tab Enable Large System extensions.
 203 @item @code{memtag} @tab ARMv8.5-A @tab No
 204  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 205 @item @code{mops} @tab @tab Armv8.8-A or later
 206  @tab Enable Armv8.8-A memcpy and memset acceleration instructions
 207 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 208  @tab Enable Privileged Access Never support.
 209 @item @code{pauth} @tab ARMv8-A @tab No
 210  @tab Enable Pointer Authentication.
 211 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 212  @tab Enable the Execution and Data and Prediction instructions.
 213 @item @code{profile} @tab ARMv8.2-A @tab No
 214  @tab Enable statistical profiling extensions.
 215 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 216  @tab Enable the Reliability, Availability and Serviceability extension.
 217 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 218  @tab Enable the weak release consistency extension.
 219 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 220  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 221 @item @code{rng} @tab ARMv8.5-A @tab No
 222  @tab Enable ARMv8.5-A random number instructions.
 223 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 224  @tab Enable the speculation barrier instruction sb.
 225 @item @code{sha2} @tab ARMv8-A @tab No
 226  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and
 227  @code{simd}.
 228 @item @code{sha3} @tab ARMv8.2-A @tab No
 229  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies
 230  @code{fp}, @code{simd} and @code{sha2}.
 231 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 232  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 233 @item @code{sm4} @tab ARMv8.2-A @tab No
 234  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies
 235  @code{fp} and @code{simd}.
 236 @item @code{sme} @tab Armv9-A @tab No
 237  @tab Enable SME Extension.
 238 @item @code{sme-f64f64} @tab Armv9-A @tab No
 239  @tab Enable SME F64F64 Extension.
 240 @item @code{sme-i16i64} @tab Armv9-A @tab No
 241  @tab Enable SME I16I64 Extension.
 242 @item @code{sme2} @tab Armv9-A @tab No
 243  @tab Enable SME2.  This implies @code{sme}.
 244 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 245  @tab Enable Speculative Store Bypassing Safe state read and write.
 246 @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
 247  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 248  @code{simd} and @code{compnum}.
 249 @item @code{sve2} @tab ARMv8-A @tab Armv9-A or later
 250  @tab Enable the SVE2 Extension.  This implies @code{sve}.
 251 @item @code{sve2-aes} @tab ARMv8-A @tab No
 252  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 253  @code{pmullt} and @code{pmullb} instructions.  This implies @code{aes} and
 254  @code{sve2}.
 255 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 256  @tab Enable SVE2 BITPERM Extension.
 257 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 258  @tab Enable SVE2 SHA3 Extension.  This implies @code{sha3} and @code{sve2}.
 259 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 260  @tab Enable SVE2 SM4 Extension.  This implies @code{sm4} and @code{sve2}.
 261 @item @code{tme} @tab ARMv8-A @tab No
 262  @tab Enable Transactional Memory Extensions.
 263 @item @code{chk} @tab ARMv8-A @tab ARMv8-A
 264  @tab Enable Check Feature Status Extension.
 265 @item @code{gcs} @tab N/A @tab No
 266  @tab Enable Guarded Control Stack Extension.
 267 @item @code{the} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
 268  @tab Enable Translation Hardening extension.
 269 @item @code{lse128} @tab Armv9.4-A @tab No
 270  @tab Enable the 128-bit Atomic Instructions extension.  This implies @code{lse}.
 271 @item @code{rasv2} @tab N/A @tab Armv9.4-A or later
 272  @tab Enable the Reliability, Availability and Serviceability extension v2.
 273 @item @code{predres2} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
 274  @tab Enable Prediction instructions.
 275 @item @code{ite} @tab N/A @tab no
 276  @tab Enable TRCIT instruction.
 277 @end multitable
 278
 279 @node AArch64 Syntax
 280 @section Syntax
 281 @menu
 282 * AArch64-Chars::                Special Characters
 283 * AArch64-Regs::                 Register Names
 284 * AArch64-Relocations::      Relocations
 285 @end menu
 286
 287 @node AArch64-Chars
 288 @subsection Special Characters
 289
 290 @cindex line comment character, AArch64
 291 @cindex AArch64 line comment character
 292 The presence of a @samp{//} on a line indicates the start of a comment
 293 that extends to the end of the current line.  If a @samp{#} appears as
 294 the first character of a line, the whole line is treated as a comment.
 295
 296 @cindex line separator, AArch64
 297 @cindex statement separator, AArch64
 298 @cindex AArch64 line separator
 299 The @samp{;} character can be used instead of a newline to separate
 300 statements.
 301
 302 @cindex immediate character, AArch64
 303 @cindex AArch64 immediate character
 304 The @samp{#} can be optionally used to indicate immediate operands.
 305
 306 @node AArch64-Regs
 307 @subsection Register Names
 308
 309 @cindex AArch64 register names
 310 @cindex register names, AArch64
 311 Please refer to the section @samp{4.4 Register Names} of
 312 @samp{ARMv8 Instruction Set Overview}, which is available at
 313 @uref{http://infocenter.arm.com}.
 314
 315 @node AArch64-Relocations
 316 @subsection Relocations
 317
 318 @cindex relocations, AArch64
 319 @cindex AArch64 relocations
 320 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 321 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 322 by prefixing the label with @samp{#:abs_g2:} etc.
 323 For example to load the 48-bit absolute address of @var{foo} into x0:
 324
 325 @smallexample
 326         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 327         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 328         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 329 @end smallexample
 330
 331 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 332 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 333 instructions can be generated by prefixing the label with
 334 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 335
 336 For example to use 33-bit (+/-4GB) pc-relative addressing to
 337 load the address of @var{foo} into x0:
 338
 339 @smallexample
 340         adrp x0, :pg_hi21:foo
 341         add  x0, x0, #:lo12:foo
 342 @end smallexample
 343
 344 Or to load the value of @var{foo} into x0:
 345
 346 @smallexample
 347         adrp x0, :pg_hi21:foo
 348         ldr  x0, [x0, #:lo12:foo]
 349 @end smallexample
 350
 351 Note that @samp{:pg_hi21:} is optional.
 352
 353 @smallexample
 354         adrp x0, foo
 355 @end smallexample
 356
 357 is equivalent to
 358
 359 @smallexample
 360         adrp x0, :pg_hi21:foo
 361 @end smallexample
 362
 363 @node AArch64 Floating Point
 364 @section Floating Point
 365
 366 @cindex floating point, AArch64 (@sc{ieee})
 367 @cindex AArch64 floating point (@sc{ieee})
 368 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 369
 370 @node AArch64 Directives
 371 @section AArch64 Machine Directives
 372
 373 @cindex machine directives, AArch64
 374 @cindex AArch64 machine directives
 375 @table @code
 376
 377 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 378
 379 @cindex @code{.arch} directive, AArch64
 380 @item .arch @var{name}
 381 Select the target architecture.  Valid values for @var{name} are the same as
 382 for the @option{-march} command-line option.
 383
 384 Specifying @code{.arch} clears any previously selected architecture
 385 extensions.
 386
 387 @cindex @code{.arch_extension} directive, AArch64
 388 @item .arch_extension @var{name}
 389 Add or remove an architecture extension to the target architecture.  Valid
 390 values for @var{name} are the same as those accepted as architectural
 391 extensions by the @option{-mcpu} command-line option.
 392
 393 @code{.arch_extension} may be used multiple times to add or remove extensions
 394 incrementally to the architecture being compiled for.
 395
 396 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 397
 398 @cindex @code{.bss} directive, AArch64
 399 @item .bss
 400 This directive switches to the @code{.bss} section.
 401
 402 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 403
 404 @cindex @code{.cpu} directive, AArch64
 405 @item .cpu @var{name}
 406 Set the target processor.  Valid values for @var{name} are the same as
 407 those accepted by the @option{-mcpu=} command-line option.
 408
 409 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 410
 411 @cindex @code{.dword} directive, AArch64
 412 @item .dword @var{expressions}
 413 The @code{.dword} directive produces 64 bit values.
 414
 415 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 416
 417 @cindex @code{.even} directive, AArch64
 418 @item .even
 419 The @code{.even} directive aligns the output on the next even byte
 420 boundary.
 421
 422 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 423
 424 @cindex @code{.float16} directive, AArch64
 425 @item .float16 @var{value [,...,value_n]}
 426 Place the half precision floating point representation of one or more
 427 floating-point values into the current section.
 428 The format used to encode the floating point values is always the
 429 IEEE 754-2008 half precision floating point format.
 430
 431 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 432 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 433 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 434
 435 @cindex @code{.inst} directive, AArch64
 436 @item .inst @var{expressions}
 437 Inserts the expressions into the output as if they were instructions,
 438 rather than data.
 439
 440 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 441 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 442 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 443
 444 @cindex @code{.ltorg} directive, AArch64
 445 @item .ltorg
 446 This directive causes the current contents of the literal pool to be
 447 dumped into the current section (which is assumed to be the .text
 448 section) at the current location (aligned to a word boundary).
 449 GAS maintains a separate literal pool for each section and each
 450 sub-section.  The @code{.ltorg} directive will only affect the literal
 451 pool of the current section and sub-section.  At the end of assembly
 452 all remaining, un-empty literal pools will automatically be dumped.
 453
 454 Note - older versions of GAS would dump the current literal
 455 pool any time a section change occurred.  This is no longer done, since
 456 it prevents accurate control of the placement of literal pools.
 457
 458 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 459
 460 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 461 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 462
 463 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 464
 465 @cindex @code{.pool} directive, AArch64
 466 @item .pool
 467 This is a synonym for .ltorg.
 468
 469 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 470 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 471
 472 @cindex @code{.req} directive, AArch64
 473 @item @var{name} .req @var{register name}
 474 This creates an alias for @var{register name} called @var{name}.  For
 475 example:
 476
 477 @smallexample
 478         foo .req w0
 479 @end smallexample
 480
 481 ip0, ip1, lr and fp are automatically defined to
 482 alias to X16, X17, X30 and X29 respectively.
 483
 484 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 485
 486 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 487
 488 @cindex @code{.tlsdescadd} directive, AArch64
 489 @item   @code{.tlsdescadd}
 490 Emits a TLSDESC_ADD reloc on the next instruction.
 491
 492 @cindex @code{.tlsdesccall} directive, AArch64
 493 @item   @code{.tlsdesccall}
 494 Emits a TLSDESC_CALL reloc on the next instruction.
 495
 496 @cindex @code{.tlsdescldr} directive, AArch64
 497 @item   @code{.tlsdescldr}
 498 Emits a TLSDESC_LDR reloc on the next instruction.
 499
 500 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 501
 502 @cindex @code{.unreq} directive, AArch64
 503 @item .unreq @var{alias-name}
 504 This undefines a register alias which was previously defined using the
 505 @code{req} directive.  For example:
 506
 507 @smallexample
 508         foo .req w0
 509         .unreq foo
 510 @end smallexample
 511
 512 An error occurs if the name is undefined.  Note - this pseudo op can
 513 be used to delete builtin in register name aliases (eg 'w0').  This
 514 should only be done if it is really necessary.
 515
 516 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 517
 518 @cindex @code{.variant_pcs} directive, AArch64
 519 @item .variant_pcs @var{symbol}
 520 This directive marks @var{symbol} referencing a function that may
 521 follow a variant procedure call standard with different register
 522 usage convention from the base procedure call standard.
 523
 524 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 525 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 526
 527 @cindex @code{.xword} directive, AArch64
 528 @item .xword @var{expressions}
 529 The @code{.xword} directive produces 64 bit values.  This is the same
 530 as the @code{.dword} directive.
 531
 532 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 533 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 534
 535 @cindex @code{.cfi_b_key_frame} directive, AArch64
 536 @item   @code{.cfi_b_key_frame}
 537 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 538 corresponding to the current frame's FDE, meaning that its return address has
 539 been signed with the B-key.  If two frames are signed with differing keys then
 540 they will not share the same CIE.  This information is intended to be used by
 541 the stack unwinder in order to properly authenticate return addresses.
 542
 543 @end table
 544
 545 @node AArch64 Opcodes
 546 @section Opcodes
 547
 548 @cindex AArch64 opcodes
 549 @cindex opcodes for AArch64
 550 GAS implements all the standard AArch64 opcodes.  It also
 551 implements several pseudo opcodes, including several synthetic load
 552 instructions.
 553
 554 @table @code
 555
 556 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 557 @item LDR =
 558 @smallexample
 559   ldr <register> , =<expression>
 560 @end smallexample
 561
 562 The constant expression will be placed into the nearest literal pool (if it not
 563 already there) and a PC-relative LDR instruction will be generated.
 564
 565 @end table
 566
 567 For more information on the AArch64 instruction set and assembly language
 568 notation, see @samp{ARMv8 Instruction Set Overview} available at
 569 @uref{http://infocenter.arm.com}.
 570
 571
 572 @node AArch64 Mapping Symbols
 573 @section Mapping Symbols
 574
 575 The AArch64 ELF specification requires that special symbols be inserted
 576 into object files to mark certain features:
 577
 578 @table @code
 579
 580 @cindex @code{$x}
 581 @item $x
 582 At the start of a region of code containing AArch64 instructions.
 583
 584 @cindex @code{$d}
 585 @item $d
 586 At the start of a region of data.
 587
 588 @end table