gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2017 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a57},
  61 @code{cortex-a72},
  62 @code{cortex-a73},
  63 @code{exynos-m1},
  64 @code{falkor},
  65 @code{qdf24xx},
  66 @code{thunderx},
  67 @code{vulcan},
  68 @code{xgene1}
  69 and
  70 @code{xgene2}.
  71 The special name @code{all} may be used to allow the assembler to accept
  72 instructions valid for any supported processor, including all optional
  73 extensions.
  74
  75 In addition to the basic instruction set, the assembler can be told to
  76 accept, or restrict, various extension mnemonics that extend the
  77 processor.  @xref{AArch64 Extensions}.
  78
  79 If some implementations of a particular processor can have an
  80 extension, then then those extensions are automatically enabled.
  81 Consequently, you will not normally have to specify any additional
  82 extensions.
  83
  84 @cindex @option{-march=} command line option, AArch64
  85 @item -march=@var{architecture}[+@var{extension}@dots{}]
  86 This option specifies the target architecture.  The assembler will
  87 issue an error message if an attempt is made to assemble an
  88 instruction which will not execute on the target architecture.  The
  89 following architecture names are recognized: @code{armv8-a},
  90 @code{armv8.1-a}, @code{armv8.2-a} and @code{armv8.3-a}.
  91
  92 If both @option{-mcpu} and @option{-march} are specified, the
  93 assembler will use the setting for @option{-mcpu}.  If neither are
  94 specified, the assembler will default to @option{-mcpu=all}.
  95
  96 The architecture option can be extended with the same instruction set
  97 extension options as the @option{-mcpu} option.  Unlike
  98 @option{-mcpu}, extensions are not always enabled by default,
  99 @xref{AArch64 Extensions}.
 100
 101 @cindex @code{-mverbose-error} command line option, AArch64
 102 @item -mverbose-error
 103 This option enables verbose error messages for AArch64 gas.  This option
 104 is enabled by default.
 105
 106 @cindex @code{-mno-verbose-error} command line option, AArch64
 107 @item -mno-verbose-error
 108 This option disables verbose error messages in AArch64 gas.
 109
 110 @end table
 111 @c man end
 112
 113 @node AArch64 Extensions
 114 @section Architecture Extensions
 115
 116 The table below lists the permitted architecture extensions that are
 117 supported by the assembler and the conditions under which they are
 118 automatically enabled.
 119
 120 Multiple extensions may be specified, separated by a @code{+}.
 121 Extension mnemonics may also be removed from those the assembler
 122 accepts.  This is done by prepending @code{no} to the option that adds
 123 the extension.  Extensions that are removed must be listed after all
 124 extensions that have been added.
 125
 126 Enabling an extension that requires other extensions will
 127 automatically cause those extensions to be enabled.  Similarly,
 128 disabling an extension that is required by other extensions will
 129 automatically cause those extensions to be disabled.
 130
 131 @multitable @columnfractions .12 .17 .17 .54
 132 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 133  @tab Description
 134 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 135  @tab Enable CRC instructions.
 136 @item @code{crypto} @tab ARMv8-A @tab No
 137  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 138 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 139  @tab Enable floating-point extensions.
 140 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 141  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 142  @code{fp}.
 143 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 144  @tab Enable Limited Ordering Regions extensions.
 145 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 146  @tab Enable Large System extensions.
 147 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 148  @tab Enable Privileged Access Never support.
 149 @item @code{profile} @tab ARMv8.2-A @tab No
 150  @tab Enable statistical profiling extensions.
 151 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 152  @tab Enable the Reliability, Availability and Serviceability
 153  extension.
 154 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 155  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 156 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 157  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 158 @item @code{sve} @tab ARMv8-A @tab ARMv8-A or later
 159  @tab Enable the Scalable Vector Extensions.
 160 @end multitable
 161
 162 @node AArch64 Syntax
 163 @section Syntax
 164 @menu
 165 * AArch64-Chars::                Special Characters
 166 * AArch64-Regs::                 Register Names
 167 * AArch64-Relocations::      Relocations
 168 @end menu
 169
 170 @node AArch64-Chars
 171 @subsection Special Characters
 172
 173 @cindex line comment character, AArch64
 174 @cindex AArch64 line comment character
 175 The presence of a @samp{//} on a line indicates the start of a comment
 176 that extends to the end of the current line.  If a @samp{#} appears as
 177 the first character of a line, the whole line is treated as a comment.
 178
 179 @cindex line separator, AArch64
 180 @cindex statement separator, AArch64
 181 @cindex AArch64 line separator
 182 The @samp{;} character can be used instead of a newline to separate
 183 statements.
 184
 185 @cindex immediate character, AArch64
 186 @cindex AArch64 immediate character
 187 The @samp{#} can be optionally used to indicate immediate operands.
 188
 189 @node AArch64-Regs
 190 @subsection Register Names
 191
 192 @cindex AArch64 register names
 193 @cindex register names, AArch64
 194 Please refer to the section @samp{4.4 Register Names} of
 195 @samp{ARMv8 Instruction Set Overview}, which is available at
 196 @uref{http://infocenter.arm.com}.
 197
 198 @node AArch64-Relocations
 199 @subsection Relocations
 200
 201 @cindex relocations, AArch64
 202 @cindex AArch64 relocations
 203 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 204 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 205 by prefixing the label with @samp{#:abs_g2:} etc.
 206 For example to load the 48-bit absolute address of @var{foo} into x0:
 207
 208 @smallexample
 209         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 210         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 211         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 212 @end smallexample
 213
 214 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 215 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 216 instructions can be generated by prefixing the label with
 217 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 218
 219 For example to use 33-bit (+/-4GB) pc-relative addressing to
 220 load the address of @var{foo} into x0:
 221
 222 @smallexample
 223         adrp x0, :pg_hi21:foo
 224         add  x0, x0, #:lo12:foo
 225 @end smallexample
 226
 227 Or to load the value of @var{foo} into x0:
 228
 229 @smallexample
 230         adrp x0, :pg_hi21:foo
 231         ldr  x0, [x0, #:lo12:foo]
 232 @end smallexample
 233
 234 Note that @samp{:pg_hi21:} is optional.
 235
 236 @smallexample
 237         adrp x0, foo
 238 @end smallexample
 239
 240 is equivalent to
 241
 242 @smallexample
 243         adrp x0, :pg_hi21:foo
 244 @end smallexample
 245
 246 @node AArch64 Floating Point
 247 @section Floating Point
 248
 249 @cindex floating point, AArch64 (@sc{ieee})
 250 @cindex AArch64 floating point (@sc{ieee})
 251 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 252
 253 @node AArch64 Directives
 254 @section AArch64 Machine Directives
 255
 256 @cindex machine directives, AArch64
 257 @cindex AArch64 machine directives
 258 @table @code
 259
 260 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 261
 262 @cindex @code{.arch} directive, AArch64
 263 @item .arch @var{name}
 264 Select the target architecture.  Valid values for @var{name} are the same as
 265 for the @option{-march} commandline option.
 266
 267 Specifying @code{.arch} clears any previously selected architecture
 268 extensions.
 269
 270 @cindex @code{.arch_extension} directive, AArch64
 271 @item .arch_extension @var{name}
 272 Add or remove an architecture extension to the target architecture.  Valid
 273 values for @var{name} are the same as those accepted as architectural
 274 extensions by the @option{-mcpu} commandline option.
 275
 276 @code{.arch_extension} may be used multiple times to add or remove extensions
 277 incrementally to the architecture being compiled for.
 278
 279 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 280
 281 @cindex @code{.bss} directive, AArch64
 282 @item .bss
 283 This directive switches to the @code{.bss} section.
 284
 285 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 286
 287 @cindex @code{.cpu} directive, AArch64
 288 @item .cpu @var{name}
 289 Set the target processor.  Valid values for @var{name} are the same as
 290 those accepted by the @option{-mcpu=} command line option.
 291
 292 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 293
 294 @cindex @code{.dword} directive, AArch64
 295 @item .dword @var{expressions}
 296 The @code{.dword} directive produces 64 bit values.
 297
 298 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 299
 300 @cindex @code{.even} directive, AArch64
 301 @item .even
 302 The @code{.even} directive aligns the output on the next even byte
 303 boundary.
 304
 305 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 306 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 307 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 308 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 309
 310 @cindex @code{.inst} directive, AArch64
 311 @item .inst @var{expressions}
 312 Inserts the expressions into the output as if they were instructions,
 313 rather than data.
 314
 315 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 316 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 317 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 318
 319 @cindex @code{.ltorg} directive, AArch64
 320 @item .ltorg
 321 This directive causes the current contents of the literal pool to be
 322 dumped into the current section (which is assumed to be the .text
 323 section) at the current location (aligned to a word boundary).
 324 GAS maintains a separate literal pool for each section and each
 325 sub-section.  The @code{.ltorg} directive will only affect the literal
 326 pool of the current section and sub-section.  At the end of assembly
 327 all remaining, un-empty literal pools will automatically be dumped.
 328
 329 Note - older versions of GAS would dump the current literal
 330 pool any time a section change occurred.  This is no longer done, since
 331 it prevents accurate control of the placement of literal pools.
 332
 333 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 334
 335 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 336 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 337
 338 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 339
 340 @cindex @code{.pool} directive, AArch64
 341 @item .pool
 342 This is a synonym for .ltorg.
 343
 344 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 345 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 346
 347 @cindex @code{.req} directive, AArch64
 348 @item @var{name} .req @var{register name}
 349 This creates an alias for @var{register name} called @var{name}.  For
 350 example:
 351
 352 @smallexample
 353         foo .req w0
 354 @end smallexample
 355
 356 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 357
 358 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 359
 360 @cindex @code{.tlsdescadd} directive, AArch64
 361 @item   @code{.tlsdescadd}
 362 Emits a TLSDESC_ADD reloc on the next instruction.
 363
 364 @cindex @code{.tlsdesccall} directive, AArch64
 365 @item   @code{.tlsdesccall}
 366 Emits a TLSDESC_CALL reloc on the next instruction.
 367
 368 @cindex @code{.tlsdescldr} directive, AArch64
 369 @item   @code{.tlsdescldr}
 370 Emits a TLSDESC_LDR reloc on the next instruction.
 371
 372 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 373
 374 @cindex @code{.unreq} directive, AArch64
 375 @item .unreq @var{alias-name}
 376 This undefines a register alias which was previously defined using the
 377 @code{req} directive.  For example:
 378
 379 @smallexample
 380         foo .req w0
 381         .unreq foo
 382 @end smallexample
 383
 384 An error occurs if the name is undefined.  Note - this pseudo op can
 385 be used to delete builtin in register name aliases (eg 'w0').  This
 386 should only be done if it is really necessary.
 387
 388 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 389
 390 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 391 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 392
 393 @cindex @code{.xword} directive, AArch64
 394 @item .xword @var{expressions}
 395 The @code{.xword} directive produces 64 bit values.  This is the same
 396 as the @code{.dword} directive.
 397
 398 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 399 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 400
 401 @end table
 402
 403 @node AArch64 Opcodes
 404 @section Opcodes
 405
 406 @cindex AArch64 opcodes
 407 @cindex opcodes for AArch64
 408 GAS implements all the standard AArch64 opcodes.  It also
 409 implements several pseudo opcodes, including several synthetic load
 410 instructions.
 411
 412 @table @code
 413
 414 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 415 @item LDR =
 416 @smallexample
 417   ldr <register> , =<expression>
 418 @end smallexample
 419
 420 The constant expression will be placed into the nearest literal pool (if it not
 421 already there) and a PC-relative LDR instruction will be generated.
 422
 423 @end table
 424
 425 For more information on the AArch64 instruction set and assembly language
 426 notation, see @samp{ARMv8 Instruction Set Overview} available at
 427 @uref{http://infocenter.arm.com}.
 428
 429
 430 @node AArch64 Mapping Symbols
 431 @section Mapping Symbols
 432
 433 The AArch64 ELF specification requires that special symbols be inserted
 434 into object files to mark certain features:
 435
 436 @table @code
 437
 438 @cindex @code{$x}
 439 @item $x
 440 At the start of a region of code containing AArch64 instructions.
 441
 442 @cindex @code{$d}
 443 @item $d
 444 At the start of a region of data.
 445
 446 @end table