gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2017 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a55},
  61 @code{cortex-a57},
  62 @code{cortex-a72},
  63 @code{cortex-a73},
  64 @code{cortex-a75},
  65 @code{exynos-m1},
  66 @code{falkor},
  67 @code{qdf24xx},
  68 @code{thunderx},
  69 @code{vulcan},
  70 @code{xgene1}
  71 and
  72 @code{xgene2}.
  73 The special name @code{all} may be used to allow the assembler to accept
  74 instructions valid for any supported processor, including all optional
  75 extensions.
  76
  77 In addition to the basic instruction set, the assembler can be told to
  78 accept, or restrict, various extension mnemonics that extend the
  79 processor.  @xref{AArch64 Extensions}.
  80
  81 If some implementations of a particular processor can have an
  82 extension, then then those extensions are automatically enabled.
  83 Consequently, you will not normally have to specify any additional
  84 extensions.
  85
  86 @cindex @option{-march=} command line option, AArch64
  87 @item -march=@var{architecture}[+@var{extension}@dots{}]
  88 This option specifies the target architecture.  The assembler will
  89 issue an error message if an attempt is made to assemble an
  90 instruction which will not execute on the target architecture.  The
  91 following architecture names are recognized: @code{armv8-a},
  92 @code{armv8.1-a}, @code{armv8.2-a} and @code{armv8.3-a}.
  93
  94 If both @option{-mcpu} and @option{-march} are specified, the
  95 assembler will use the setting for @option{-mcpu}.  If neither are
  96 specified, the assembler will default to @option{-mcpu=all}.
  97
  98 The architecture option can be extended with the same instruction set
  99 extension options as the @option{-mcpu} option.  Unlike
 100 @option{-mcpu}, extensions are not always enabled by default,
 101 @xref{AArch64 Extensions}.
 102
 103 @cindex @code{-mverbose-error} command line option, AArch64
 104 @item -mverbose-error
 105 This option enables verbose error messages for AArch64 gas.  This option
 106 is enabled by default.
 107
 108 @cindex @code{-mno-verbose-error} command line option, AArch64
 109 @item -mno-verbose-error
 110 This option disables verbose error messages in AArch64 gas.
 111
 112 @end table
 113 @c man end
 114
 115 @node AArch64 Extensions
 116 @section Architecture Extensions
 117
 118 The table below lists the permitted architecture extensions that are
 119 supported by the assembler and the conditions under which they are
 120 automatically enabled.
 121
 122 Multiple extensions may be specified, separated by a @code{+}.
 123 Extension mnemonics may also be removed from those the assembler
 124 accepts.  This is done by prepending @code{no} to the option that adds
 125 the extension.  Extensions that are removed must be listed after all
 126 extensions that have been added.
 127
 128 Enabling an extension that requires other extensions will
 129 automatically cause those extensions to be enabled.  Similarly,
 130 disabling an extension that is required by other extensions will
 131 automatically cause those extensions to be disabled.
 132
 133 @multitable @columnfractions .12 .17 .17 .54
 134 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 135  @tab Description
 136 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 137  @tab Enable the complex number SIMD extensions.  This implies
 138  @code{fp16} and @code{simd}.
 139 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 140  @tab Enable CRC instructions.
 141 @item @code{crypto} @tab ARMv8-A @tab No
 142  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 143 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 144  @tab Enable floating-point extensions.
 145 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 146  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 147  @code{fp}.
 148 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 149  @tab Enable Limited Ordering Regions extensions.
 150 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 151  @tab Enable Large System extensions.
 152 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 153  @tab Enable Privileged Access Never support.
 154 @item @code{profile} @tab ARMv8.2-A @tab No
 155  @tab Enable statistical profiling extensions.
 156 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 157  @tab Enable the Reliability, Availability and Serviceability
 158  extension.
 159 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 160  @tab Enable the weak release consistency extension.
 161 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 162  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 163 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 164  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 165 @item @code{sve} @tab ARMv8.2-A @tab No
 166  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 167  @code{simd} and @code{compnum}.
 168 @item @code{dotprod} @tab ARMv8.2-A @tab No
 169  @tab Enable the Dot Product extension.  This implies @code{simd}.
 170 @end multitable
 171
 172 @node AArch64 Syntax
 173 @section Syntax
 174 @menu
 175 * AArch64-Chars::                Special Characters
 176 * AArch64-Regs::                 Register Names
 177 * AArch64-Relocations::      Relocations
 178 @end menu
 179
 180 @node AArch64-Chars
 181 @subsection Special Characters
 182
 183 @cindex line comment character, AArch64
 184 @cindex AArch64 line comment character
 185 The presence of a @samp{//} on a line indicates the start of a comment
 186 that extends to the end of the current line.  If a @samp{#} appears as
 187 the first character of a line, the whole line is treated as a comment.
 188
 189 @cindex line separator, AArch64
 190 @cindex statement separator, AArch64
 191 @cindex AArch64 line separator
 192 The @samp{;} character can be used instead of a newline to separate
 193 statements.
 194
 195 @cindex immediate character, AArch64
 196 @cindex AArch64 immediate character
 197 The @samp{#} can be optionally used to indicate immediate operands.
 198
 199 @node AArch64-Regs
 200 @subsection Register Names
 201
 202 @cindex AArch64 register names
 203 @cindex register names, AArch64
 204 Please refer to the section @samp{4.4 Register Names} of
 205 @samp{ARMv8 Instruction Set Overview}, which is available at
 206 @uref{http://infocenter.arm.com}.
 207
 208 @node AArch64-Relocations
 209 @subsection Relocations
 210
 211 @cindex relocations, AArch64
 212 @cindex AArch64 relocations
 213 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 214 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 215 by prefixing the label with @samp{#:abs_g2:} etc.
 216 For example to load the 48-bit absolute address of @var{foo} into x0:
 217
 218 @smallexample
 219         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 220         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 221         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 222 @end smallexample
 223
 224 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 225 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 226 instructions can be generated by prefixing the label with
 227 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 228
 229 For example to use 33-bit (+/-4GB) pc-relative addressing to
 230 load the address of @var{foo} into x0:
 231
 232 @smallexample
 233         adrp x0, :pg_hi21:foo
 234         add  x0, x0, #:lo12:foo
 235 @end smallexample
 236
 237 Or to load the value of @var{foo} into x0:
 238
 239 @smallexample
 240         adrp x0, :pg_hi21:foo
 241         ldr  x0, [x0, #:lo12:foo]
 242 @end smallexample
 243
 244 Note that @samp{:pg_hi21:} is optional.
 245
 246 @smallexample
 247         adrp x0, foo
 248 @end smallexample
 249
 250 is equivalent to
 251
 252 @smallexample
 253         adrp x0, :pg_hi21:foo
 254 @end smallexample
 255
 256 @node AArch64 Floating Point
 257 @section Floating Point
 258
 259 @cindex floating point, AArch64 (@sc{ieee})
 260 @cindex AArch64 floating point (@sc{ieee})
 261 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 262
 263 @node AArch64 Directives
 264 @section AArch64 Machine Directives
 265
 266 @cindex machine directives, AArch64
 267 @cindex AArch64 machine directives
 268 @table @code
 269
 270 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 271
 272 @cindex @code{.arch} directive, AArch64
 273 @item .arch @var{name}
 274 Select the target architecture.  Valid values for @var{name} are the same as
 275 for the @option{-march} commandline option.
 276
 277 Specifying @code{.arch} clears any previously selected architecture
 278 extensions.
 279
 280 @cindex @code{.arch_extension} directive, AArch64
 281 @item .arch_extension @var{name}
 282 Add or remove an architecture extension to the target architecture.  Valid
 283 values for @var{name} are the same as those accepted as architectural
 284 extensions by the @option{-mcpu} commandline option.
 285
 286 @code{.arch_extension} may be used multiple times to add or remove extensions
 287 incrementally to the architecture being compiled for.
 288
 289 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 290
 291 @cindex @code{.bss} directive, AArch64
 292 @item .bss
 293 This directive switches to the @code{.bss} section.
 294
 295 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 296
 297 @cindex @code{.cpu} directive, AArch64
 298 @item .cpu @var{name}
 299 Set the target processor.  Valid values for @var{name} are the same as
 300 those accepted by the @option{-mcpu=} command line option.
 301
 302 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 303
 304 @cindex @code{.dword} directive, AArch64
 305 @item .dword @var{expressions}
 306 The @code{.dword} directive produces 64 bit values.
 307
 308 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 309
 310 @cindex @code{.even} directive, AArch64
 311 @item .even
 312 The @code{.even} directive aligns the output on the next even byte
 313 boundary.
 314
 315 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 316 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 317 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 318 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 319
 320 @cindex @code{.inst} directive, AArch64
 321 @item .inst @var{expressions}
 322 Inserts the expressions into the output as if they were instructions,
 323 rather than data.
 324
 325 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 326 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 327 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 328
 329 @cindex @code{.ltorg} directive, AArch64
 330 @item .ltorg
 331 This directive causes the current contents of the literal pool to be
 332 dumped into the current section (which is assumed to be the .text
 333 section) at the current location (aligned to a word boundary).
 334 GAS maintains a separate literal pool for each section and each
 335 sub-section.  The @code{.ltorg} directive will only affect the literal
 336 pool of the current section and sub-section.  At the end of assembly
 337 all remaining, un-empty literal pools will automatically be dumped.
 338
 339 Note - older versions of GAS would dump the current literal
 340 pool any time a section change occurred.  This is no longer done, since
 341 it prevents accurate control of the placement of literal pools.
 342
 343 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 344
 345 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 346 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 347
 348 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 349
 350 @cindex @code{.pool} directive, AArch64
 351 @item .pool
 352 This is a synonym for .ltorg.
 353
 354 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 355 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 356
 357 @cindex @code{.req} directive, AArch64
 358 @item @var{name} .req @var{register name}
 359 This creates an alias for @var{register name} called @var{name}.  For
 360 example:
 361
 362 @smallexample
 363         foo .req w0
 364 @end smallexample
 365
 366 ip0, ip1, lr and fp are automatically defined to
 367 alias to X16, X17, X30 and X29 respectively.
 368
 369 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 370
 371 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 372
 373 @cindex @code{.tlsdescadd} directive, AArch64
 374 @item   @code{.tlsdescadd}
 375 Emits a TLSDESC_ADD reloc on the next instruction.
 376
 377 @cindex @code{.tlsdesccall} directive, AArch64
 378 @item   @code{.tlsdesccall}
 379 Emits a TLSDESC_CALL reloc on the next instruction.
 380
 381 @cindex @code{.tlsdescldr} directive, AArch64
 382 @item   @code{.tlsdescldr}
 383 Emits a TLSDESC_LDR reloc on the next instruction.
 384
 385 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 386
 387 @cindex @code{.unreq} directive, AArch64
 388 @item .unreq @var{alias-name}
 389 This undefines a register alias which was previously defined using the
 390 @code{req} directive.  For example:
 391
 392 @smallexample
 393         foo .req w0
 394         .unreq foo
 395 @end smallexample
 396
 397 An error occurs if the name is undefined.  Note - this pseudo op can
 398 be used to delete builtin in register name aliases (eg 'w0').  This
 399 should only be done if it is really necessary.
 400
 401 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 402
 403 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 404 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 405
 406 @cindex @code{.xword} directive, AArch64
 407 @item .xword @var{expressions}
 408 The @code{.xword} directive produces 64 bit values.  This is the same
 409 as the @code{.dword} directive.
 410
 411 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 412 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 413
 414 @end table
 415
 416 @node AArch64 Opcodes
 417 @section Opcodes
 418
 419 @cindex AArch64 opcodes
 420 @cindex opcodes for AArch64
 421 GAS implements all the standard AArch64 opcodes.  It also
 422 implements several pseudo opcodes, including several synthetic load
 423 instructions.
 424
 425 @table @code
 426
 427 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 428 @item LDR =
 429 @smallexample
 430   ldr <register> , =<expression>
 431 @end smallexample
 432
 433 The constant expression will be placed into the nearest literal pool (if it not
 434 already there) and a PC-relative LDR instruction will be generated.
 435
 436 @end table
 437
 438 For more information on the AArch64 instruction set and assembly language
 439 notation, see @samp{ARMv8 Instruction Set Overview} available at
 440 @uref{http://infocenter.arm.com}.
 441
 442
 443 @node AArch64 Mapping Symbols
 444 @section Mapping Symbols
 445
 446 The AArch64 ELF specification requires that special symbols be inserted
 447 into object files to mark certain features:
 448
 449 @table @code
 450
 451 @cindex @code{$x}
 452 @item $x
 453 At the start of a region of code containing AArch64 instructions.
 454
 455 @cindex @code{$d}
 456 @item $d
 457 At the start of a region of data.
 458
 459 @end table