1 @c Copyright (C) 1996-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
141 @code{cortex-m0plus},
144 @code{marvell-whitney},
149 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
150 @code{i80200} (Intel XScale processor)
151 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
154 The special name @code{all} may be used to allow the
155 assembler to accept instructions valid for any ARM processor.
157 In addition to the basic instruction set, the assembler can be told to
158 accept various extension mnemonics that extend the processor using the
159 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
160 is equivalent to specifying @code{-mcpu=ep9312}.
162 Multiple extensions may be specified, separated by a @code{+}. The
163 extensions should be specified in ascending alphabetical order.
165 Some extensions may be restricted to particular architectures; this is
166 documented in the list of extensions below.
168 Extension mnemonics may also be removed from those the assembler accepts.
169 This is done be prepending @code{no} to the option that adds the extension.
170 Extensions that are removed should be listed after all extensions which have
171 been added, again in ascending alphabetical order. For example,
172 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
175 The following extensions are currently supported:
177 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
178 @code{fp} (Floating Point Extensions for v8-A architecture),
179 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
184 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
186 @code{os} (Operating System for v6M architecture),
187 @code{sec} (Security Extensions for v6K and v7-A architectures),
188 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
189 @code{virt} (Virtualization Extensions for v7-A architecture, implies
191 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
192 @code{ras} (Reliability, Availability and Serviceability extensions
193 for v8-A architecture),
194 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
199 @cindex @code{-march=} command line option, ARM
200 @item -march=@var{architecture}[+@var{extension}@dots{}]
201 This option specifies the target architecture. The assembler will issue
202 an error message if an attempt is made to assemble an instruction which
203 will not execute on the target architecture. The following architecture
204 names are recognized:
241 If both @code{-mcpu} and
242 @code{-march} are specified, the assembler will use
243 the setting for @code{-mcpu}.
245 The architecture option can be extended with the same instruction set
246 extension options as the @code{-mcpu} option.
248 @cindex @code{-mfpu=} command line option, ARM
249 @item -mfpu=@var{floating-point-format}
251 This option specifies the floating point format to assemble for. The
252 assembler will issue an error message if an attempt is made to assemble
253 an instruction which will not execute on the target floating point unit.
254 The following format options are recognized:
274 @code{vfpv3-d16-fp16},
289 @code{neon-fp-armv8},
290 @code{crypto-neon-fp-armv8},
291 @code{neon-fp-armv8.1}
293 @code{crypto-neon-fp-armv8.1}.
295 In addition to determining which instructions are assembled, this option
296 also affects the way in which the @code{.double} assembler directive behaves
297 when assembling little-endian code.
299 The default is dependent on the processor selected. For Architecture 5 or
300 later, the default is to assembler for VFP instructions; for earlier
301 architectures the default is to assemble for FPA instructions.
303 @cindex @code{-mthumb} command line option, ARM
305 This option specifies that the assembler should start assembling Thumb
306 instructions; that is, it should behave as though the file starts with a
307 @code{.code 16} directive.
309 @cindex @code{-mthumb-interwork} command line option, ARM
310 @item -mthumb-interwork
311 This option specifies that the output generated by the assembler should
312 be marked as supporting interworking.
314 @cindex @code{-mimplicit-it} command line option, ARM
315 @item -mimplicit-it=never
316 @itemx -mimplicit-it=always
317 @itemx -mimplicit-it=arm
318 @itemx -mimplicit-it=thumb
319 The @code{-mimplicit-it} option controls the behavior of the assembler when
320 conditional instructions are not enclosed in IT blocks.
321 There are four possible behaviors.
322 If @code{never} is specified, such constructs cause a warning in ARM
323 code and an error in Thumb-2 code.
324 If @code{always} is specified, such constructs are accepted in both
325 ARM and Thumb-2 code, where the IT instruction is added implicitly.
326 If @code{arm} is specified, such constructs are accepted in ARM code
327 and cause an error in Thumb-2 code.
328 If @code{thumb} is specified, such constructs cause a warning in ARM
329 code and are accepted in Thumb-2 code. If you omit this option, the
330 behavior is equivalent to @code{-mimplicit-it=arm}.
332 @cindex @code{-mapcs-26} command line option, ARM
333 @cindex @code{-mapcs-32} command line option, ARM
336 These options specify that the output generated by the assembler should
337 be marked as supporting the indicated version of the Arm Procedure.
340 @cindex @code{-matpcs} command line option, ARM
342 This option specifies that the output generated by the assembler should
343 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
344 enabled this option will cause the assembler to create an empty
345 debugging section in the object file called .arm.atpcs. Debuggers can
346 use this to determine the ABI being used by.
348 @cindex @code{-mapcs-float} command line option, ARM
350 This indicates the floating point variant of the APCS should be
351 used. In this variant floating point arguments are passed in FP
352 registers rather than integer registers.
354 @cindex @code{-mapcs-reentrant} command line option, ARM
355 @item -mapcs-reentrant
356 This indicates that the reentrant variant of the APCS should be used.
357 This variant supports position independent code.
359 @cindex @code{-mfloat-abi=} command line option, ARM
360 @item -mfloat-abi=@var{abi}
361 This option specifies that the output generated by the assembler should be
362 marked as using specified floating point ABI.
363 The following values are recognized:
369 @cindex @code{-eabi=} command line option, ARM
370 @item -meabi=@var{ver}
371 This option specifies which EABI version the produced object files should
373 The following values are recognized:
379 @cindex @code{-EB} command line option, ARM
381 This option specifies that the output generated by the assembler should
382 be marked as being encoded for a big-endian processor.
384 Note: If a program is being built for a system with big-endian data
385 and little-endian instructions then it should be assembled with the
386 @option{-EB} option, (all of it, code and data) and then linked with
387 the @option{--be8} option. This will reverse the endianness of the
388 instructions back to little-endian, but leave the data as big-endian.
390 @cindex @code{-EL} command line option, ARM
392 This option specifies that the output generated by the assembler should
393 be marked as being encoded for a little-endian processor.
395 @cindex @code{-k} command line option, ARM
396 @cindex PIC code generation for ARM
398 This option specifies that the output of the assembler should be marked
399 as position-independent code (PIC).
401 @cindex @code{--fix-v4bx} command line option, ARM
403 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
404 the linker option of the same name.
406 @cindex @code{-mwarn-deprecated} command line option, ARM
407 @item -mwarn-deprecated
408 @itemx -mno-warn-deprecated
409 Enable or disable warnings about using deprecated options or
410 features. The default is to warn.
412 @cindex @code{-mccs} command line option, ARM
414 Turns on CodeComposer Studio assembly syntax compatibility mode.
416 @cindex @code{-mwarn-syms} command line option, ARM
418 @itemx -mno-warn-syms
419 Enable or disable warnings about symbols that match the names of ARM
420 instructions. The default is to warn.
428 * ARM-Instruction-Set:: Instruction Set
429 * ARM-Chars:: Special Characters
430 * ARM-Regs:: Register Names
431 * ARM-Relocations:: Relocations
432 * ARM-Neon-Alignment:: NEON Alignment Specifiers
435 @node ARM-Instruction-Set
436 @subsection Instruction Set Syntax
437 Two slightly different syntaxes are support for ARM and THUMB
438 instructions. The default, @code{divided}, uses the old style where
439 ARM and THUMB instructions had their own, separate syntaxes. The new,
440 @code{unified} syntax, which can be selected via the @code{.syntax}
441 directive, and has the following main features:
445 Immediate operands do not require a @code{#} prefix.
448 The @code{IT} instruction may appear, and if it does it is validated
449 against subsequent conditional affixes. In ARM mode it does not
450 generate machine code, in THUMB mode it does.
453 For ARM instructions the conditional affixes always appear at the end
454 of the instruction. For THUMB instructions conditional affixes can be
455 used, but only inside the scope of an @code{IT} instruction.
458 All of the instructions new to the V6T2 architecture (and later) are
459 available. (Only a few such instructions can be written in the
460 @code{divided} syntax).
463 The @code{.N} and @code{.W} suffixes are recognized and honored.
466 All instructions set the flags if and only if they have an @code{s}
471 @subsection Special Characters
473 @cindex line comment character, ARM
474 @cindex ARM line comment character
475 The presence of a @samp{@@} anywhere on a line indicates the start of
476 a comment that extends to the end of that line.
478 If a @samp{#} appears as the first character of a line then the whole
479 line is treated as a comment, but in this case the line could also be
480 a logical line number directive (@pxref{Comments}) or a preprocessor
481 control command (@pxref{Preprocessing}).
483 @cindex line separator, ARM
484 @cindex statement separator, ARM
485 @cindex ARM line separator
486 The @samp{;} character can be used instead of a newline to separate
489 @cindex immediate character, ARM
490 @cindex ARM immediate character
491 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
493 @cindex identifiers, ARM
494 @cindex ARM identifiers
495 *TODO* Explain about /data modifier on symbols.
498 @subsection Register Names
500 @cindex ARM register names
501 @cindex register names, ARM
502 *TODO* Explain about ARM register naming, and the predefined names.
504 @node ARM-Relocations
505 @subsection ARM relocation generation
507 @cindex data relocations, ARM
508 @cindex ARM data relocations
509 Specific data relocations can be generated by putting the relocation name
510 in parentheses after the symbol name. For example:
516 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
518 The following relocations are supported:
534 For compatibility with older toolchains the assembler also accepts
535 @code{(PLT)} after branch targets. On legacy targets this will
536 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
537 targets it will encode either the @samp{R_ARM_CALL} or
538 @samp{R_ARM_JUMP24} relocation, as appropriate.
540 @cindex MOVW and MOVT relocations, ARM
541 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
542 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
543 respectively. For example to load the 32-bit address of foo into r0:
546 MOVW r0, #:lower16:foo
547 MOVT r0, #:upper16:foo
550 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
551 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
552 generated by prefixing the value with @samp{#:lower0_7:#},
553 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
554 respectively. For example to load the 32-bit address of foo into r0:
557 MOVS r0, #:upper8_15:#foo
559 ADDS r0, #:upper0_7:#foo
561 ADDS r0, #:lower8_15:#foo
563 ADDS r0, #:lower0_7:#foo
566 @node ARM-Neon-Alignment
567 @subsection NEON Alignment Specifiers
569 @cindex alignment for NEON instructions
570 Some NEON load/store instructions allow an optional address
572 The ARM documentation specifies that this is indicated by
573 @samp{@@ @var{align}}. However GAS already interprets
574 the @samp{@@} character as a "line comment" start,
575 so @samp{: @var{align}} is used instead. For example:
578 vld1.8 @{q0@}, [r0, :128]
581 @node ARM Floating Point
582 @section Floating Point
584 @cindex floating point, ARM (@sc{ieee})
585 @cindex ARM floating point (@sc{ieee})
586 The ARM family uses @sc{ieee} floating-point numbers.
589 @section ARM Machine Directives
591 @cindex machine directives, ARM
592 @cindex ARM machine directives
595 @c AAAAAAAAAAAAAAAAAAAAAAAAA
598 @cindex @code{.2byte} directive, ARM
599 @cindex @code{.4byte} directive, ARM
600 @cindex @code{.8byte} directive, ARM
601 @item .2byte @var{expression} [, @var{expression}]*
602 @itemx .4byte @var{expression} [, @var{expression}]*
603 @itemx .8byte @var{expression} [, @var{expression}]*
604 These directives write 2, 4 or 8 byte values to the output section.
607 @cindex @code{.align} directive, ARM
608 @item .align @var{expression} [, @var{expression}]
609 This is the generic @var{.align} directive. For the ARM however if the
610 first argument is zero (ie no alignment is needed) the assembler will
611 behave as if the argument had been 2 (ie pad to the next four byte
612 boundary). This is for compatibility with ARM's own assembler.
614 @cindex @code{.arch} directive, ARM
615 @item .arch @var{name}
616 Select the target architecture. Valid values for @var{name} are the same as
617 for the @option{-march} commandline option.
619 Specifying @code{.arch} clears any previously selected architecture
622 @cindex @code{.arch_extension} directive, ARM
623 @item .arch_extension @var{name}
624 Add or remove an architecture extension to the target architecture. Valid
625 values for @var{name} are the same as those accepted as architectural
626 extensions by the @option{-mcpu} commandline option.
628 @code{.arch_extension} may be used multiple times to add or remove extensions
629 incrementally to the architecture being compiled for.
631 @cindex @code{.arm} directive, ARM
633 This performs the same action as @var{.code 32}.
635 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
637 @cindex @code{.bss} directive, ARM
639 This directive switches to the @code{.bss} section.
641 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
643 @cindex @code{.cantunwind} directive, ARM
645 Prevents unwinding through the current function. No personality routine
646 or exception table data is required or permitted.
648 @cindex @code{.code} directive, ARM
649 @item .code @code{[16|32]}
650 This directive selects the instruction set being generated. The value 16
651 selects Thumb, with the value 32 selecting ARM.
653 @cindex @code{.cpu} directive, ARM
654 @item .cpu @var{name}
655 Select the target processor. Valid values for @var{name} are the same as
656 for the @option{-mcpu} commandline option.
658 Specifying @code{.cpu} clears any previously selected architecture
661 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
663 @cindex @code{.dn} and @code{.qn} directives, ARM
664 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
665 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
667 The @code{dn} and @code{qn} directives are used to create typed
668 and/or indexed register aliases for use in Advanced SIMD Extension
669 (Neon) instructions. The former should be used to create aliases
670 of double-precision registers, and the latter to create aliases of
671 quad-precision registers.
673 If these directives are used to create typed aliases, those aliases can
674 be used in Neon instructions instead of writing types after the mnemonic
675 or after each operand. For example:
684 This is equivalent to writing the following:
690 Aliases created using @code{dn} or @code{qn} can be destroyed using
693 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
695 @cindex @code{.eabi_attribute} directive, ARM
696 @item .eabi_attribute @var{tag}, @var{value}
697 Set the EABI object attribute @var{tag} to @var{value}.
699 The @var{tag} is either an attribute number, or one of the following:
700 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
701 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
702 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
703 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
704 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
705 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
706 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
707 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
708 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
709 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
710 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
711 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
712 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
713 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
714 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
715 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
716 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
717 @code{Tag_conformance}, @code{Tag_T2EE_use},
718 @code{Tag_Virtualization_use}
720 The @var{value} is either a @code{number}, @code{"string"}, or
721 @code{number, "string"} depending on the tag.
723 Note - the following legacy values are also accepted by @var{tag}:
724 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
725 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
727 @cindex @code{.even} directive, ARM
729 This directive aligns to an even-numbered address.
731 @cindex @code{.extend} directive, ARM
732 @cindex @code{.ldouble} directive, ARM
733 @item .extend @var{expression} [, @var{expression}]*
734 @itemx .ldouble @var{expression} [, @var{expression}]*
735 These directives write 12byte long double floating-point values to the
736 output section. These are not compatible with current ARM processors
739 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
742 @cindex @code{.fnend} directive, ARM
744 Marks the end of a function with an unwind table entry. The unwind index
745 table entry is created when this directive is processed.
747 If no personality routine has been specified then standard personality
748 routine 0 or 1 will be used, depending on the number of unwind opcodes
752 @cindex @code{.fnstart} directive, ARM
754 Marks the start of a function with an unwind table entry.
756 @cindex @code{.force_thumb} directive, ARM
758 This directive forces the selection of Thumb instructions, even if the
759 target processor does not support those instructions
761 @cindex @code{.fpu} directive, ARM
762 @item .fpu @var{name}
763 Select the floating-point unit to assemble for. Valid values for @var{name}
764 are the same as for the @option{-mfpu} commandline option.
766 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
767 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
769 @cindex @code{.handlerdata} directive, ARM
771 Marks the end of the current function, and the start of the exception table
772 entry for that function. Anything between this directive and the
773 @code{.fnend} directive will be added to the exception table entry.
775 Must be preceded by a @code{.personality} or @code{.personalityindex}
778 @c IIIIIIIIIIIIIIIIIIIIIIIIII
780 @cindex @code{.inst} directive, ARM
781 @item .inst @var{opcode} [ , @dots{} ]
782 @itemx .inst.n @var{opcode} [ , @dots{} ]
783 @itemx .inst.w @var{opcode} [ , @dots{} ]
784 Generates the instruction corresponding to the numerical value @var{opcode}.
785 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
786 specified explicitly, overriding the normal encoding rules.
788 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
789 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
790 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
792 @item .ldouble @var{expression} [, @var{expression}]*
795 @cindex @code{.ltorg} directive, ARM
797 This directive causes the current contents of the literal pool to be
798 dumped into the current section (which is assumed to be the .text
799 section) at the current location (aligned to a word boundary).
800 @code{GAS} maintains a separate literal pool for each section and each
801 sub-section. The @code{.ltorg} directive will only affect the literal
802 pool of the current section and sub-section. At the end of assembly
803 all remaining, un-empty literal pools will automatically be dumped.
805 Note - older versions of @code{GAS} would dump the current literal
806 pool any time a section change occurred. This is no longer done, since
807 it prevents accurate control of the placement of literal pools.
809 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
811 @cindex @code{.movsp} directive, ARM
812 @item .movsp @var{reg} [, #@var{offset}]
813 Tell the unwinder that @var{reg} contains an offset from the current
814 stack pointer. If @var{offset} is not specified then it is assumed to be
817 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
818 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
820 @cindex @code{.object_arch} directive, ARM
821 @item .object_arch @var{name}
822 Override the architecture recorded in the EABI object attribute section.
823 Valid values for @var{name} are the same as for the @code{.arch} directive.
824 Typically this is useful when code uses runtime detection of CPU features.
826 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
828 @cindex @code{.packed} directive, ARM
829 @item .packed @var{expression} [, @var{expression}]*
830 This directive writes 12-byte packed floating-point values to the
831 output section. These are not compatible with current ARM processors
835 @cindex @code{.pad} directive, ARM
836 @item .pad #@var{count}
837 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
838 A positive value indicates the function prologue allocated stack space by
839 decrementing the stack pointer.
841 @cindex @code{.personality} directive, ARM
842 @item .personality @var{name}
843 Sets the personality routine for the current function to @var{name}.
845 @cindex @code{.personalityindex} directive, ARM
846 @item .personalityindex @var{index}
847 Sets the personality routine for the current function to the EABI standard
848 routine number @var{index}
850 @cindex @code{.pool} directive, ARM
852 This is a synonym for .ltorg.
854 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
855 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
857 @cindex @code{.req} directive, ARM
858 @item @var{name} .req @var{register name}
859 This creates an alias for @var{register name} called @var{name}. For
866 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
869 @cindex @code{.save} directive, ARM
870 @item .save @var{reglist}
871 Generate unwinder annotations to restore the registers in @var{reglist}.
872 The format of @var{reglist} is the same as the corresponding store-multiple
876 @exdent @emph{core registers}
877 .save @{r4, r5, r6, lr@}
878 stmfd sp!, @{r4, r5, r6, lr@}
879 @exdent @emph{FPA registers}
882 @exdent @emph{VFP registers}
883 .save @{d8, d9, d10@}
884 fstmdx sp!, @{d8, d9, d10@}
885 @exdent @emph{iWMMXt registers}
887 wstrd wr11, [sp, #-8]!
888 wstrd wr10, [sp, #-8]!
891 wstrd wr11, [sp, #-8]!
893 wstrd wr10, [sp, #-8]!
897 @cindex @code{.setfp} directive, ARM
898 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
899 Make all unwinder annotations relative to a frame pointer. Without this
900 the unwinder will use offsets from the stack pointer.
902 The syntax of this directive is the same as the @code{add} or @code{mov}
903 instruction used to set the frame pointer. @var{spreg} must be either
904 @code{sp} or mentioned in a previous @code{.movsp} directive.
914 @cindex @code{.secrel32} directive, ARM
915 @item .secrel32 @var{expression} [, @var{expression}]*
916 This directive emits relocations that evaluate to the section-relative
917 offset of each expression's symbol. This directive is only supported
920 @cindex @code{.syntax} directive, ARM
921 @item .syntax [@code{unified} | @code{divided}]
922 This directive sets the Instruction Set Syntax as described in the
923 @ref{ARM-Instruction-Set} section.
925 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
927 @cindex @code{.thumb} directive, ARM
929 This performs the same action as @var{.code 16}.
931 @cindex @code{.thumb_func} directive, ARM
933 This directive specifies that the following symbol is the name of a
934 Thumb encoded function. This information is necessary in order to allow
935 the assembler and linker to generate correct code for interworking
936 between Arm and Thumb instructions and should be used even if
937 interworking is not going to be performed. The presence of this
938 directive also implies @code{.thumb}
940 This directive is not necessary when generating EABI objects. On these
941 targets the encoding is implicit when generating Thumb code.
943 @cindex @code{.thumb_set} directive, ARM
945 This performs the equivalent of a @code{.set} directive in that it
946 creates a symbol which is an alias for another symbol (possibly not yet
947 defined). This directive also has the added property in that it marks
948 the aliased symbol as being a thumb function entry point, in the same
949 way that the @code{.thumb_func} directive does.
951 @cindex @code{.tlsdescseq} directive, ARM
952 @item .tlsdescseq @var{tls-variable}
953 This directive is used to annotate parts of an inlined TLS descriptor
954 trampoline. Normally the trampoline is provided by the linker, and
955 this directive is not needed.
957 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
959 @cindex @code{.unreq} directive, ARM
960 @item .unreq @var{alias-name}
961 This undefines a register alias which was previously defined using the
962 @code{req}, @code{dn} or @code{qn} directives. For example:
969 An error occurs if the name is undefined. Note - this pseudo op can
970 be used to delete builtin in register name aliases (eg 'r0'). This
971 should only be done if it is really necessary.
973 @cindex @code{.unwind_raw} directive, ARM
974 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
975 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
976 the stack pointer by @var{offset} bytes.
978 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
981 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
983 @cindex @code{.vsave} directive, ARM
984 @item .vsave @var{vfp-reglist}
985 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
986 using FLDMD. Also works for VFPv3 registers
987 that are to be restored using VLDM.
988 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
992 @exdent @emph{VFP registers}
993 .vsave @{d8, d9, d10@}
994 fstmdd sp!, @{d8, d9, d10@}
995 @exdent @emph{VFPv3 registers}
996 .vsave @{d15, d16, d17@}
997 vstm sp!, @{d15, d16, d17@}
1000 Since FLDMX and FSTMX are now deprecated, this directive should be
1001 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1003 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1004 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1005 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1006 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1014 @cindex opcodes for ARM
1015 @code{@value{AS}} implements all the standard ARM opcodes. It also
1016 implements several pseudo opcodes, including several synthetic load
1021 @cindex @code{NOP} pseudo op, ARM
1027 This pseudo op will always evaluate to a legal ARM instruction that does
1028 nothing. Currently it will evaluate to MOV r0, r0.
1030 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1033 ldr <register> , = <expression>
1036 If expression evaluates to a numeric constant then a MOV or MVN
1037 instruction will be used in place of the LDR instruction, if the
1038 constant can be generated by either of these instructions. Otherwise
1039 the constant will be placed into the nearest literal pool (if it not
1040 already there) and a PC relative LDR instruction will be generated.
1042 @cindex @code{ADR reg,<label>} pseudo op, ARM
1045 adr <register> <label>
1048 This instruction will load the address of @var{label} into the indicated
1049 register. The instruction will evaluate to a PC relative ADD or SUB
1050 instruction depending upon where the label is located. If the label is
1051 out of range, or if it is not defined in the same file (and section) as
1052 the ADR instruction, then an error will be generated. This instruction
1053 will not make use of the literal pool.
1055 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1058 adrl <register> <label>
1061 This instruction will load the address of @var{label} into the indicated
1062 register. The instruction will evaluate to one or two PC relative ADD
1063 or SUB instructions depending upon where the label is located. If a
1064 second instruction is not needed a NOP instruction will be generated in
1065 its place, so that this instruction is always 8 bytes long.
1067 If the label is out of range, or if it is not defined in the same file
1068 (and section) as the ADRL instruction, then an error will be generated.
1069 This instruction will not make use of the literal pool.
1073 For information on the ARM or Thumb instruction sets, see @cite{ARM
1074 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1077 @node ARM Mapping Symbols
1078 @section Mapping Symbols
1080 The ARM ELF specification requires that special symbols be inserted
1081 into object files to mark certain features:
1087 At the start of a region of code containing ARM instructions.
1091 At the start of a region of code containing THUMB instructions.
1095 At the start of a region of data.
1099 The assembler will automatically insert these symbols for you - there
1100 is no need to code them yourself. Support for tagging symbols ($b,
1101 $f, $p and $m) which is also mentioned in the current ARM ELF
1102 specification is not implemented. This is because they have been
1103 dropped from the new EABI and so tools cannot rely upon their
1106 @node ARM Unwinding Tutorial
1109 The ABI for the ARM Architecture specifies a standard format for
1110 exception unwind information. This information is used when an
1111 exception is thrown to determine where control should be transferred.
1112 In particular, the unwind information is used to determine which
1113 function called the function that threw the exception, and which
1114 function called that one, and so forth. This information is also used
1115 to restore the values of callee-saved registers in the function
1116 catching the exception.
1118 If you are writing functions in assembly code, and those functions
1119 call other functions that throw exceptions, you must use assembly
1120 pseudo ops to ensure that appropriate exception unwind information is
1121 generated. Otherwise, if one of the functions called by your assembly
1122 code throws an exception, the run-time library will be unable to
1123 unwind the stack through your assembly code and your program will not
1126 To illustrate the use of these pseudo ops, we will examine the code
1127 that G++ generates for the following C++ input:
1130 void callee (int *);
1141 This example does not show how to throw or catch an exception from
1142 assembly code. That is a much more complex operation and should
1143 always be done in a high-level language, such as C++, that directly
1144 supports exceptions.
1146 The code generated by one particular version of G++ when compiling the
1153 @ Function supports interworking.
1154 @ args = 0, pretend = 0, frame = 8
1155 @ frame_needed = 1, uses_anonymous_args = 0
1177 Of course, the sequence of instructions varies based on the options
1178 you pass to GCC and on the version of GCC in use. The exact
1179 instructions are not important since we are focusing on the pseudo ops
1180 that are used to generate unwind information.
1182 An important assumption made by the unwinder is that the stack frame
1183 does not change during the body of the function. In particular, since
1184 we assume that the assembly code does not itself throw an exception,
1185 the only point where an exception can be thrown is from a call, such
1186 as the @code{bl} instruction above. At each call site, the same saved
1187 registers (including @code{lr}, which indicates the return address)
1188 must be located in the same locations relative to the frame pointer.
1190 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1191 op appears immediately before the first instruction of the function
1192 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1193 op appears immediately after the last instruction of the function.
1194 These pseudo ops specify the range of the function.
1196 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1197 @code{.pad}) matters; their exact locations are irrelevant. In the
1198 example above, the compiler emits the pseudo ops with particular
1199 instructions. That makes it easier to understand the code, but it is
1200 not required for correctness. It would work just as well to emit all
1201 of the pseudo ops other than @code{.fnend} in the same order, but
1202 immediately after @code{.fnstart}.
1204 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1205 indicates registers that have been saved to the stack so that they can
1206 be restored before the function returns. The argument to the
1207 @code{.save} pseudo op is a list of registers to save. If a register
1208 is ``callee-saved'' (as specified by the ABI) and is modified by the
1209 function you are writing, then your code must save the value before it
1210 is modified and restore the original value before the function
1211 returns. If an exception is thrown, the run-time library restores the
1212 values of these registers from their locations on the stack before
1213 returning control to the exception handler. (Of course, if an
1214 exception is not thrown, the function that contains the @code{.save}
1215 pseudo op restores these registers in the function epilogue, as is
1216 done with the @code{ldmfd} instruction above.)
1218 You do not have to save callee-saved registers at the very beginning
1219 of the function and you do not need to use the @code{.save} pseudo op
1220 immediately following the point at which the registers are saved.
1221 However, if you modify a callee-saved register, you must save it on
1222 the stack before modifying it and before calling any functions which
1223 might throw an exception. And, you must use the @code{.save} pseudo
1224 op to indicate that you have done so.
1226 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1227 modification of the stack pointer that does not save any registers.
1228 The argument is the number of bytes (in decimal) that are subtracted
1229 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1230 subtracting from the stack pointer increases the size of the stack.)
1232 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1233 indicates the register that contains the frame pointer. The first
1234 argument is the register that is set, which is typically @code{fp}.
1235 The second argument indicates the register from which the frame
1236 pointer takes its value. The third argument, if present, is the value
1237 (in decimal) added to the register specified by the second argument to
1238 compute the value of the frame pointer. You should not modify the
1239 frame pointer in the body of the function.
1241 If you do not use a frame pointer, then you should not use the
1242 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1243 should avoid modifying the stack pointer outside of the function
1244 prologue. Otherwise, the run-time library will be unable to find
1245 saved registers when it is unwinding the stack.
1247 The pseudo ops described above are sufficient for writing assembly
1248 code that calls functions which may throw exceptions. If you need to
1249 know more about the object-file format used to represent unwind
1250 information, you may consult the @cite{Exception Handling ABI for the
1251 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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