1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
125 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
126 @code{i80200} (Intel XScale processor)
127 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
130 The special name @code{all} may be used to allow the
131 assembler to accept instructions valid for any ARM processor.
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics that extend the processor using the
135 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
136 is equivalent to specifying @code{-mcpu=ep9312}.
138 Multiple extensions may be specified, separated by a @code{+}. The
139 extensions should be specified in ascending alphabetical order.
141 Some extensions may be restricted to particular architectures; this is
142 documented in the list of extensions below.
144 Extension mnemonics may also be removed from those the assembler accepts.
145 This is done be prepending @code{no} to the option that adds the extension.
146 Extensions that are removed should be listed after all extensions which have
147 been added, again in ascending alphabetical order. For example,
148 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
151 The following extensions are currently supported:
152 @code{idiv}, (Integer Divide Extensions for v7-A architecture),
156 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
157 @code{os} (Operating System for v6M architecture),
158 @code{sec} (Security Extensions for v6K and v7-A architectures),
159 @code{virt} (Virtualization Extensions for v7-A architecture, implies
164 @cindex @code{-march=} command line option, ARM
165 @item -march=@var{architecture}[+@var{extension}@dots{}]
166 This option specifies the target architecture. The assembler will issue
167 an error message if an attempt is made to assemble an instruction which
168 will not execute on the target architecture. The following architecture
169 names are recognized:
200 If both @code{-mcpu} and
201 @code{-march} are specified, the assembler will use
202 the setting for @code{-mcpu}.
204 The architecture option can be extended with the same instruction set
205 extension options as the @code{-mcpu} option.
207 @cindex @code{-mfpu=} command line option, ARM
208 @item -mfpu=@var{floating-point-format}
210 This option specifies the floating point format to assemble for. The
211 assembler will issue an error message if an attempt is made to assemble
212 an instruction which will not execute on the target floating point unit.
213 The following format options are recognized:
233 @code{vfpv3-d16-fp16},
247 In addition to determining which instructions are assembled, this option
248 also affects the way in which the @code{.double} assembler directive behaves
249 when assembling little-endian code.
251 The default is dependent on the processor selected. For Architecture 5 or
252 later, the default is to assembler for VFP instructions; for earlier
253 architectures the default is to assemble for FPA instructions.
255 @cindex @code{-mthumb} command line option, ARM
257 This option specifies that the assembler should start assembling Thumb
258 instructions; that is, it should behave as though the file starts with a
259 @code{.code 16} directive.
261 @cindex @code{-mthumb-interwork} command line option, ARM
262 @item -mthumb-interwork
263 This option specifies that the output generated by the assembler should
264 be marked as supporting interworking.
266 @cindex @code{-mimplicit-it} command line option, ARM
267 @item -mimplicit-it=never
268 @itemx -mimplicit-it=always
269 @itemx -mimplicit-it=arm
270 @itemx -mimplicit-it=thumb
271 The @code{-mimplicit-it} option controls the behavior of the assembler when
272 conditional instructions are not enclosed in IT blocks.
273 There are four possible behaviors.
274 If @code{never} is specified, such constructs cause a warning in ARM
275 code and an error in Thumb-2 code.
276 If @code{always} is specified, such constructs are accepted in both
277 ARM and Thumb-2 code, where the IT instruction is added implicitly.
278 If @code{arm} is specified, such constructs are accepted in ARM code
279 and cause an error in Thumb-2 code.
280 If @code{thumb} is specified, such constructs cause a warning in ARM
281 code and are accepted in Thumb-2 code. If you omit this option, the
282 behavior is equivalent to @code{-mimplicit-it=arm}.
284 @cindex @code{-mapcs-26} command line option, ARM
285 @cindex @code{-mapcs-32} command line option, ARM
288 These options specify that the output generated by the assembler should
289 be marked as supporting the indicated version of the Arm Procedure.
292 @cindex @code{-matpcs} command line option, ARM
294 This option specifies that the output generated by the assembler should
295 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
296 enabled this option will cause the assembler to create an empty
297 debugging section in the object file called .arm.atpcs. Debuggers can
298 use this to determine the ABI being used by.
300 @cindex @code{-mapcs-float} command line option, ARM
302 This indicates the floating point variant of the APCS should be
303 used. In this variant floating point arguments are passed in FP
304 registers rather than integer registers.
306 @cindex @code{-mapcs-reentrant} command line option, ARM
307 @item -mapcs-reentrant
308 This indicates that the reentrant variant of the APCS should be used.
309 This variant supports position independent code.
311 @cindex @code{-mfloat-abi=} command line option, ARM
312 @item -mfloat-abi=@var{abi}
313 This option specifies that the output generated by the assembler should be
314 marked as using specified floating point ABI.
315 The following values are recognized:
321 @cindex @code{-eabi=} command line option, ARM
322 @item -meabi=@var{ver}
323 This option specifies which EABI version the produced object files should
325 The following values are recognized:
331 @cindex @code{-EB} command line option, ARM
333 This option specifies that the output generated by the assembler should
334 be marked as being encoded for a big-endian processor.
336 @cindex @code{-EL} command line option, ARM
338 This option specifies that the output generated by the assembler should
339 be marked as being encoded for a little-endian processor.
341 @cindex @code{-k} command line option, ARM
342 @cindex PIC code generation for ARM
344 This option specifies that the output of the assembler should be marked
345 as position-independent code (PIC).
347 @cindex @code{--fix-v4bx} command line option, ARM
349 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
350 the linker option of the same name.
352 @cindex @code{-mwarn-deprecated} command line option, ARM
353 @item -mwarn-deprecated
354 @itemx -mno-warn-deprecated
355 Enable or disable warnings about using deprecated options or
356 features. The default is to warn.
364 * ARM-Instruction-Set:: Instruction Set
365 * ARM-Chars:: Special Characters
366 * ARM-Regs:: Register Names
367 * ARM-Relocations:: Relocations
368 * ARM-Neon-Alignment:: NEON Alignment Specifiers
371 @node ARM-Instruction-Set
372 @subsection Instruction Set Syntax
373 Two slightly different syntaxes are support for ARM and THUMB
374 instructions. The default, @code{divided}, uses the old style where
375 ARM and THUMB instructions had their own, separate syntaxes. The new,
376 @code{unified} syntax, which can be selected via the @code{.syntax}
377 directive, and has the following main features:
381 Immediate operands do not require a @code{#} prefix.
384 The @code{IT} instruction may appear, and if it does it is validated
385 against subsequent conditional affixes. In ARM mode it does not
386 generate machine code, in THUMB mode it does.
389 For ARM instructions the conditional affixes always appear at the end
390 of the instruction. For THUMB instructions conditional affixes can be
391 used, but only inside the scope of an @code{IT} instruction.
394 All of the instructions new to the V6T2 architecture (and later) are
395 available. (Only a few such instructions can be written in the
396 @code{divided} syntax).
399 The @code{.N} and @code{.W} suffixes are recognized and honored.
402 All instructions set the flags if and only if they have an @code{s}
407 @subsection Special Characters
409 @cindex line comment character, ARM
410 @cindex ARM line comment character
411 The presence of a @samp{@@} anywhere on a line indicates the start of
412 a comment that extends to the end of that line.
414 If a @samp{#} appears as the first character of a line then the whole
415 line is treated as a comment, but in this case the line could also be
416 a logical line number directive (@pxref{Comments}) or a preprocessor
417 control command (@pxref{Preprocessing}).
419 @cindex line separator, ARM
420 @cindex statement separator, ARM
421 @cindex ARM line separator
422 The @samp{;} character can be used instead of a newline to separate
425 @cindex immediate character, ARM
426 @cindex ARM immediate character
427 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
429 @cindex identifiers, ARM
430 @cindex ARM identifiers
431 *TODO* Explain about /data modifier on symbols.
434 @subsection Register Names
436 @cindex ARM register names
437 @cindex register names, ARM
438 *TODO* Explain about ARM register naming, and the predefined names.
440 @node ARM-Neon-Alignment
441 @subsection NEON Alignment Specifiers
443 @cindex alignment for NEON instructions
444 Some NEON load/store instructions allow an optional address
446 The ARM documentation specifies that this is indicated by
447 @samp{@@ @var{align}}. However GAS already interprets
448 the @samp{@@} character as a "line comment" start,
449 so @samp{: @var{align}} is used instead. For example:
452 vld1.8 @{q0@}, [r0, :128]
455 @node ARM Floating Point
456 @section Floating Point
458 @cindex floating point, ARM (@sc{ieee})
459 @cindex ARM floating point (@sc{ieee})
460 The ARM family uses @sc{ieee} floating-point numbers.
462 @node ARM-Relocations
463 @subsection ARM relocation generation
465 @cindex data relocations, ARM
466 @cindex ARM data relocations
467 Specific data relocations can be generated by putting the relocation name
468 in parentheses after the symbol name. For example:
474 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
476 The following relocations are supported:
492 For compatibility with older toolchains the assembler also accepts
493 @code{(PLT)} after branch targets. This will generate the deprecated
494 @samp{R_ARM_PLT32} relocation.
496 @cindex MOVW and MOVT relocations, ARM
497 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
498 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
499 respectively. For example to load the 32-bit address of foo into r0:
502 MOVW r0, #:lower16:foo
503 MOVT r0, #:upper16:foo
507 @section ARM Machine Directives
509 @cindex machine directives, ARM
510 @cindex ARM machine directives
513 @c AAAAAAAAAAAAAAAAAAAAAAAAA
515 @cindex @code{.2byte} directive, ARM
516 @cindex @code{.4byte} directive, ARM
517 @cindex @code{.8byte} directive, ARM
518 @item .2byte @var{expression} [, @var{expression}]*
519 @itemx .4byte @var{expression} [, @var{expression}]*
520 @itemx .8byte @var{expression} [, @var{expression}]*
521 These directives write 2, 4 or 8 byte values to the output section.
523 @cindex @code{.align} directive, ARM
524 @item .align @var{expression} [, @var{expression}]
525 This is the generic @var{.align} directive. For the ARM however if the
526 first argument is zero (ie no alignment is needed) the assembler will
527 behave as if the argument had been 2 (ie pad to the next four byte
528 boundary). This is for compatibility with ARM's own assembler.
530 @cindex @code{.arch} directive, ARM
531 @item .arch @var{name}
532 Select the target architecture. Valid values for @var{name} are the same as
533 for the @option{-march} commandline option.
535 Specifying @code{.arch} clears any previously selected architecture
538 @cindex @code{.arch_extension} directive, ARM
539 @item .arch_extension @var{name}
540 Add or remove an architecture extension to the target architecture. Valid
541 values for @var{name} are the same as those accepted as architectural
542 extensions by the @option{-mcpu} commandline option.
544 @code{.arch_extension} may be used multiple times to add or remove extensions
545 incrementally to the architecture being compiled for.
547 @cindex @code{.arm} directive, ARM
549 This performs the same action as @var{.code 32}.
552 @cindex @code{.pad} directive, ARM
553 @item .pad #@var{count}
554 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
555 A positive value indicates the function prologue allocated stack space by
556 decrementing the stack pointer.
558 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
560 @cindex @code{.bss} directive, ARM
562 This directive switches to the @code{.bss} section.
564 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
566 @cindex @code{.cantunwind} directive, ARM
568 Prevents unwinding through the current function. No personality routine
569 or exception table data is required or permitted.
571 @cindex @code{.code} directive, ARM
572 @item .code @code{[16|32]}
573 This directive selects the instruction set being generated. The value 16
574 selects Thumb, with the value 32 selecting ARM.
576 @cindex @code{.cpu} directive, ARM
577 @item .cpu @var{name}
578 Select the target processor. Valid values for @var{name} are the same as
579 for the @option{-mcpu} commandline option.
581 Specifying @code{.cpu} clears any previously selected architecture
584 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
586 @cindex @code{.dn} and @code{.qn} directives, ARM
587 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
588 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
590 The @code{dn} and @code{qn} directives are used to create typed
591 and/or indexed register aliases for use in Advanced SIMD Extension
592 (Neon) instructions. The former should be used to create aliases
593 of double-precision registers, and the latter to create aliases of
594 quad-precision registers.
596 If these directives are used to create typed aliases, those aliases can
597 be used in Neon instructions instead of writing types after the mnemonic
598 or after each operand. For example:
607 This is equivalent to writing the following:
613 Aliases created using @code{dn} or @code{qn} can be destroyed using
616 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
618 @cindex @code{.eabi_attribute} directive, ARM
619 @item .eabi_attribute @var{tag}, @var{value}
620 Set the EABI object attribute @var{tag} to @var{value}.
622 The @var{tag} is either an attribute number, or one of the following:
623 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
624 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
625 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
626 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
627 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
628 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
629 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
630 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
631 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
632 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
633 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
634 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
635 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
636 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
637 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
638 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
639 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
640 @code{Tag_conformance}, @code{Tag_T2EE_use},
641 @code{Tag_Virtualization_use}
643 The @var{value} is either a @code{number}, @code{"string"}, or
644 @code{number, "string"} depending on the tag.
646 Note - the following legacy values are also accepted by @var{tag}:
647 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
648 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
650 @cindex @code{.even} directive, ARM
652 This directive aligns to an even-numbered address.
654 @cindex @code{.extend} directive, ARM
655 @cindex @code{.ldouble} directive, ARM
656 @item .extend @var{expression} [, @var{expression}]*
657 @itemx .ldouble @var{expression} [, @var{expression}]*
658 These directives write 12byte long double floating-point values to the
659 output section. These are not compatible with current ARM processors
662 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
665 @cindex @code{.fnend} directive, ARM
667 Marks the end of a function with an unwind table entry. The unwind index
668 table entry is created when this directive is processed.
670 If no personality routine has been specified then standard personality
671 routine 0 or 1 will be used, depending on the number of unwind opcodes
675 @cindex @code{.fnstart} directive, ARM
677 Marks the start of a function with an unwind table entry.
679 @cindex @code{.force_thumb} directive, ARM
681 This directive forces the selection of Thumb instructions, even if the
682 target processor does not support those instructions
684 @cindex @code{.fpu} directive, ARM
685 @item .fpu @var{name}
686 Select the floating-point unit to assemble for. Valid values for @var{name}
687 are the same as for the @option{-mfpu} commandline option.
689 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
690 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
692 @cindex @code{.handlerdata} directive, ARM
694 Marks the end of the current function, and the start of the exception table
695 entry for that function. Anything between this directive and the
696 @code{.fnend} directive will be added to the exception table entry.
698 Must be preceded by a @code{.personality} or @code{.personalityindex}
701 @c IIIIIIIIIIIIIIIIIIIIIIIIII
703 @cindex @code{.inst} directive, ARM
704 @item .inst @var{opcode} [ , @dots{} ]
705 @itemx .inst.n @var{opcode} [ , @dots{} ]
706 @itemx .inst.w @var{opcode} [ , @dots{} ]
707 Generates the instruction corresponding to the numerical value @var{opcode}.
708 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
709 specified explicitly, overriding the normal encoding rules.
711 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
712 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
713 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
715 @item .ldouble @var{expression} [, @var{expression}]*
718 @cindex @code{.ltorg} directive, ARM
720 This directive causes the current contents of the literal pool to be
721 dumped into the current section (which is assumed to be the .text
722 section) at the current location (aligned to a word boundary).
723 @code{GAS} maintains a separate literal pool for each section and each
724 sub-section. The @code{.ltorg} directive will only affect the literal
725 pool of the current section and sub-section. At the end of assembly
726 all remaining, un-empty literal pools will automatically be dumped.
728 Note - older versions of @code{GAS} would dump the current literal
729 pool any time a section change occurred. This is no longer done, since
730 it prevents accurate control of the placement of literal pools.
732 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
734 @cindex @code{.movsp} directive, ARM
735 @item .movsp @var{reg} [, #@var{offset}]
736 Tell the unwinder that @var{reg} contains an offset from the current
737 stack pointer. If @var{offset} is not specified then it is assumed to be
740 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
741 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
743 @cindex @code{.object_arch} directive, ARM
744 @item .object_arch @var{name}
745 Override the architecture recorded in the EABI object attribute section.
746 Valid values for @var{name} are the same as for the @code{.arch} directive.
747 Typically this is useful when code uses runtime detection of CPU features.
749 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
751 @cindex @code{.packed} directive, ARM
752 @item .packed @var{expression} [, @var{expression}]*
753 This directive writes 12-byte packed floating-point values to the
754 output section. These are not compatible with current ARM processors
757 @cindex @code{.pad} directive, ARM
758 @item .pad #@var{count}
759 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
760 A positive value indicates the function prologue allocated stack space by
761 decrementing the stack pointer.
763 @cindex @code{.personality} directive, ARM
764 @item .personality @var{name}
765 Sets the personality routine for the current function to @var{name}.
767 @cindex @code{.personalityindex} directive, ARM
768 @item .personalityindex @var{index}
769 Sets the personality routine for the current function to the EABI standard
770 routine number @var{index}
772 @cindex @code{.pool} directive, ARM
774 This is a synonym for .ltorg.
776 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
777 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
779 @cindex @code{.req} directive, ARM
780 @item @var{name} .req @var{register name}
781 This creates an alias for @var{register name} called @var{name}. For
788 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
791 @cindex @code{.save} directive, ARM
792 @item .save @var{reglist}
793 Generate unwinder annotations to restore the registers in @var{reglist}.
794 The format of @var{reglist} is the same as the corresponding store-multiple
798 @exdent @emph{core registers}
799 .save @{r4, r5, r6, lr@}
800 stmfd sp!, @{r4, r5, r6, lr@}
801 @exdent @emph{FPA registers}
804 @exdent @emph{VFP registers}
805 .save @{d8, d9, d10@}
806 fstmdx sp!, @{d8, d9, d10@}
807 @exdent @emph{iWMMXt registers}
809 wstrd wr11, [sp, #-8]!
810 wstrd wr10, [sp, #-8]!
813 wstrd wr11, [sp, #-8]!
815 wstrd wr10, [sp, #-8]!
819 @cindex @code{.setfp} directive, ARM
820 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
821 Make all unwinder annotations relative to a frame pointer. Without this
822 the unwinder will use offsets from the stack pointer.
824 The syntax of this directive is the same as the @code{add} or @code{mov}
825 instruction used to set the frame pointer. @var{spreg} must be either
826 @code{sp} or mentioned in a previous @code{.movsp} directive.
836 @cindex @code{.secrel32} directive, ARM
837 @item .secrel32 @var{expression} [, @var{expression}]*
838 This directive emits relocations that evaluate to the section-relative
839 offset of each expression's symbol. This directive is only supported
842 @cindex @code{.syntax} directive, ARM
843 @item .syntax [@code{unified} | @code{divided}]
844 This directive sets the Instruction Set Syntax as described in the
845 @ref{ARM-Instruction-Set} section.
847 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
849 @cindex @code{.thumb} directive, ARM
851 This performs the same action as @var{.code 16}.
853 @cindex @code{.thumb_func} directive, ARM
855 This directive specifies that the following symbol is the name of a
856 Thumb encoded function. This information is necessary in order to allow
857 the assembler and linker to generate correct code for interworking
858 between Arm and Thumb instructions and should be used even if
859 interworking is not going to be performed. The presence of this
860 directive also implies @code{.thumb}
862 This directive is not neccessary when generating EABI objects. On these
863 targets the encoding is implicit when generating Thumb code.
865 @cindex @code{.thumb_set} directive, ARM
867 This performs the equivalent of a @code{.set} directive in that it
868 creates a symbol which is an alias for another symbol (possibly not yet
869 defined). This directive also has the added property in that it marks
870 the aliased symbol as being a thumb function entry point, in the same
871 way that the @code{.thumb_func} directive does.
873 @cindex @code{.tlsdescseq} directive, ARM
874 @item .tlsdescseq @var{tls-variable}
875 This directive is used to annotate parts of an inlined TLS descriptor
876 trampoline. Normally the trampoline is provided by the linker, and
877 this directive is not needed.
879 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
881 @cindex @code{.unreq} directive, ARM
882 @item .unreq @var{alias-name}
883 This undefines a register alias which was previously defined using the
884 @code{req}, @code{dn} or @code{qn} directives. For example:
891 An error occurs if the name is undefined. Note - this pseudo op can
892 be used to delete builtin in register name aliases (eg 'r0'). This
893 should only be done if it is really necessary.
895 @cindex @code{.unwind_raw} directive, ARM
896 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
897 Insert one of more arbitary unwind opcode bytes, which are known to adjust
898 the stack pointer by @var{offset} bytes.
900 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
903 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
905 @cindex @code{.vsave} directive, ARM
906 @item .vsave @var{vfp-reglist}
907 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
908 using FLDMD. Also works for VFPv3 registers
909 that are to be restored using VLDM.
910 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
914 @exdent @emph{VFP registers}
915 .vsave @{d8, d9, d10@}
916 fstmdd sp!, @{d8, d9, d10@}
917 @exdent @emph{VFPv3 registers}
918 .vsave @{d15, d16, d17@}
919 vstm sp!, @{d15, d16, d17@}
922 Since FLDMX and FSTMX are now deprecated, this directive should be
923 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
925 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
926 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
927 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
928 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
936 @cindex opcodes for ARM
937 @code{@value{AS}} implements all the standard ARM opcodes. It also
938 implements several pseudo opcodes, including several synthetic load
943 @cindex @code{NOP} pseudo op, ARM
949 This pseudo op will always evaluate to a legal ARM instruction that does
950 nothing. Currently it will evaluate to MOV r0, r0.
952 @cindex @code{LDR reg,=<label>} pseudo op, ARM
955 ldr <register> , = <expression>
958 If expression evaluates to a numeric constant then a MOV or MVN
959 instruction will be used in place of the LDR instruction, if the
960 constant can be generated by either of these instructions. Otherwise
961 the constant will be placed into the nearest literal pool (if it not
962 already there) and a PC relative LDR instruction will be generated.
964 @cindex @code{ADR reg,<label>} pseudo op, ARM
967 adr <register> <label>
970 This instruction will load the address of @var{label} into the indicated
971 register. The instruction will evaluate to a PC relative ADD or SUB
972 instruction depending upon where the label is located. If the label is
973 out of range, or if it is not defined in the same file (and section) as
974 the ADR instruction, then an error will be generated. This instruction
975 will not make use of the literal pool.
977 @cindex @code{ADRL reg,<label>} pseudo op, ARM
980 adrl <register> <label>
983 This instruction will load the address of @var{label} into the indicated
984 register. The instruction will evaluate to one or two PC relative ADD
985 or SUB instructions depending upon where the label is located. If a
986 second instruction is not needed a NOP instruction will be generated in
987 its place, so that this instruction is always 8 bytes long.
989 If the label is out of range, or if it is not defined in the same file
990 (and section) as the ADRL instruction, then an error will be generated.
991 This instruction will not make use of the literal pool.
995 For information on the ARM or Thumb instruction sets, see @cite{ARM
996 Software Development Toolkit Reference Manual}, Advanced RISC Machines
999 @node ARM Mapping Symbols
1000 @section Mapping Symbols
1002 The ARM ELF specification requires that special symbols be inserted
1003 into object files to mark certain features:
1009 At the start of a region of code containing ARM instructions.
1013 At the start of a region of code containing THUMB instructions.
1017 At the start of a region of data.
1021 The assembler will automatically insert these symbols for you - there
1022 is no need to code them yourself. Support for tagging symbols ($b,
1023 $f, $p and $m) which is also mentioned in the current ARM ELF
1024 specification is not implemented. This is because they have been
1025 dropped from the new EABI and so tools cannot rely upon their
1028 @node ARM Unwinding Tutorial
1031 The ABI for the ARM Architecture specifies a standard format for
1032 exception unwind information. This information is used when an
1033 exception is thrown to determine where control should be transferred.
1034 In particular, the unwind information is used to determine which
1035 function called the function that threw the exception, and which
1036 function called that one, and so forth. This information is also used
1037 to restore the values of callee-saved registers in the function
1038 catching the exception.
1040 If you are writing functions in assembly code, and those functions
1041 call other functions that throw exceptions, you must use assembly
1042 pseudo ops to ensure that appropriate exception unwind information is
1043 generated. Otherwise, if one of the functions called by your assembly
1044 code throws an exception, the run-time library will be unable to
1045 unwind the stack through your assembly code and your program will not
1048 To illustrate the use of these pseudo ops, we will examine the code
1049 that G++ generates for the following C++ input:
1052 void callee (int *);
1063 This example does not show how to throw or catch an exception from
1064 assembly code. That is a much more complex operation and should
1065 always be done in a high-level language, such as C++, that directly
1066 supports exceptions.
1068 The code generated by one particular version of G++ when compiling the
1075 @ Function supports interworking.
1076 @ args = 0, pretend = 0, frame = 8
1077 @ frame_needed = 1, uses_anonymous_args = 0
1099 Of course, the sequence of instructions varies based on the options
1100 you pass to GCC and on the version of GCC in use. The exact
1101 instructions are not important since we are focusing on the pseudo ops
1102 that are used to generate unwind information.
1104 An important assumption made by the unwinder is that the stack frame
1105 does not change during the body of the function. In particular, since
1106 we assume that the assembly code does not itself throw an exception,
1107 the only point where an exception can be thrown is from a call, such
1108 as the @code{bl} instruction above. At each call site, the same saved
1109 registers (including @code{lr}, which indicates the return address)
1110 must be located in the same locations relative to the frame pointer.
1112 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1113 op appears immediately before the first instruction of the function
1114 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1115 op appears immediately after the last instruction of the function.
1116 These pseudo ops specify the range of the function.
1118 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1119 @code{.pad}) matters; their exact locations are irrelevant. In the
1120 example above, the compiler emits the pseudo ops with particular
1121 instructions. That makes it easier to understand the code, but it is
1122 not required for correctness. It would work just as well to emit all
1123 of the pseudo ops other than @code{.fnend} in the same order, but
1124 immediately after @code{.fnstart}.
1126 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1127 indicates registers that have been saved to the stack so that they can
1128 be restored before the function returns. The argument to the
1129 @code{.save} pseudo op is a list of registers to save. If a register
1130 is ``callee-saved'' (as specified by the ABI) and is modified by the
1131 function you are writing, then your code must save the value before it
1132 is modified and restore the original value before the function
1133 returns. If an exception is thrown, the run-time library restores the
1134 values of these registers from their locations on the stack before
1135 returning control to the exception handler. (Of course, if an
1136 exception is not thrown, the function that contains the @code{.save}
1137 pseudo op restores these registers in the function epilogue, as is
1138 done with the @code{ldmfd} instruction above.)
1140 You do not have to save callee-saved registers at the very beginning
1141 of the function and you do not need to use the @code{.save} pseudo op
1142 immediately following the point at which the registers are saved.
1143 However, if you modify a callee-saved register, you must save it on
1144 the stack before modifying it and before calling any functions which
1145 might throw an exception. And, you must use the @code{.save} pseudo
1146 op to indicate that you have done so.
1148 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1149 modification of the stack pointer that does not save any registers.
1150 The argument is the number of bytes (in decimal) that are subtracted
1151 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1152 subtracting from the stack pointer increases the size of the stack.)
1154 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1155 indicates the register that contains the frame pointer. The first
1156 argument is the register that is set, which is typically @code{fp}.
1157 The second argument indicates the register from which the frame
1158 pointer takes its value. The third argument, if present, is the value
1159 (in decimal) added to the register specified by the second argument to
1160 compute the value of the frame pointer. You should not modify the
1161 frame pointer in the body of the function.
1163 If you do not use a frame pointer, then you should not use the
1164 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1165 should avoid modifying the stack pointer outside of the function
1166 prologue. Otherwise, the run-time library will be unable to find
1167 saved registers when it is unwinding the stack.
1169 The pseudo ops described above are sufficient for writing assembly
1170 code that calls functions which may throw exceptions. If you need to
1171 know more about the object-file format used to represent unwind
1172 information, you may consult the @cite{Exception Handling ABI for the
1173 ARM Architecture} available from @uref{http://infocenter.arm.com}.