gas/doc/c-arm.texi

   1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5
   6 @ifset GENERIC
   7 @page
   8 @node ARM-Dependent
   9 @chapter ARM Dependent Features
  10 @end ifset
  11
  12 @ifclear GENERIC
  13 @node Machine Dependencies
  14 @chapter ARM Dependent Features
  15 @end ifclear
  16
  17 @cindex ARM support
  18 @cindex Thumb support
  19 @menu
  20 * ARM Options::              Options
  21 * ARM Syntax::               Syntax
  22 * ARM Floating Point::       Floating Point
  23 * ARM Directives::           ARM Machine Directives
  24 * ARM Opcodes::              Opcodes
  25 @end menu
  26
  27 @node ARM Options
  28 @section Options
  29 @cindex ARM options (none)
  30 @cindex options for ARM (none)
  31
  32 @table @code
  33
  34 @cindex @code{-marm} command line option, ARM
  35 @item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
  36 @itemx -mxscale
  37 @itemx -marm9e
  38 This option specifies the target processor.  The assembler will issue an
  39 error message if an attempt is made to assemble an instruction which
  40 will not execute on the target processor.
  41
  42 The option @code{-marm9e} specifies that the target processor is the
  43 Cirrus ARM processor with the Maverick DSP co-processor.
  44
  45 @cindex @code{-marmv} command line option, ARM
  46 @item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]}
  47 This option specifies the target architecture.  The assembler will issue
  48 an error message if an attempt is made to assemble an instruction which
  49 will not execute on the target architecture.
  50 The option @code{-marmv5te} specifies that v5t architecture should be
  51 used with the El Segundo extensions enabled.
  52
  53 @cindex @code{-mthumb} command line option, ARM
  54 @item -mthumb
  55 This option specifies that only Thumb instructions should be assembled.
  56
  57 @cindex @code{-mall} command line option, ARM
  58 @item -mall
  59 This option specifies that any Arm or Thumb instruction should be assembled.
  60
  61 @cindex @code{-mfpa} command line option, ARM
  62 @item -mfpa @code{[10|11]}
  63 This option specifies the floating point architecture in use on the
  64 target processor.
  65
  66 @cindex @code{-mfpe-old} command line option, ARM
  67 @item -mfpe-old
  68 Do not allow the assembly of floating point multiple instructions.
  69
  70 @cindex @code{-mno-fpu} command line option, ARM
  71 @item -mno-fpu
  72 Do not allow the assembly of any floating point instructions.
  73
  74 @cindex @code{-mthumb-interwork} command line option, ARM
  75 @item -mthumb-interwork
  76 This option specifies that the output generated by the assembler should
  77 be marked as supporting interworking.
  78
  79 @cindex @code{-mapcs} command line option, ARM
  80 @item -mapcs @code{[26|32]}
  81 This option specifies that the output generated by the assembler should
  82 be marked as supporting the indicated version of the Arm Procedure.
  83 Calling Standard.
  84
  85 @cindex @code{-matpcs} command line option, ARM
  86 @item -matpcs
  87 This option specifies that the output generated by the assembler should
  88 be marked as supporting the Arm/Thumb Procedure Calling Standard.  If
  89 enabled this option will cause the assembler to create an empty
  90 debugging section in the object file called .arm.atpcs.  Debuggers can
  91 use this to determine the ABI being used by.
  92
  93 @cindex @code{-mapcs-float} command line option, ARM
  94 @item -mapcs-float
  95 This indicates the the floating point variant of the APCS should be
  96 used.  In this variant floating point arguments are passed in FP
  97 registers rather than integer registers.
  98
  99 @cindex @code{-mapcs-reentrant} command line option, ARM
 100 @item -mapcs-reentrant
 101 This indicates that the reentrant variant of the APCS should be used.
 102 This variant supports position independent code.
 103
 104 @cindex @code{-EB} command line option, ARM
 105 @item -EB
 106 This option specifies that the output generated by the assembler should
 107 be marked as being encoded for a big-endian processor.
 108
 109 @cindex @code{-EL} command line option, ARM
 110 @item -EL
 111 This option specifies that the output generated by the assembler should
 112 be marked as being encoded for a little-endian processor.
 113
 114 @cindex @code{-k} command line option, ARM
 115 @cindex PIC code generation for ARM
 116 @item -k
 117 This option specifies that the output of the assembler should be marked
 118 as position-independent code (PIC).
 119
 120 @cindex @code{-moabi} command line option, ARM
 121 @item -moabi
 122 This indicates that the code should be assembled using the old ARM ELF
 123 conventions, based on a beta release release of the ARM-ELF
 124 specifications, rather than the default conventions which are based on
 125 the final release of the ARM-ELF specifications.
 126
 127 @end table
 128
 129
 130 @node ARM Syntax
 131 @section Syntax
 132 @menu
 133 * ARM-Chars::                Special Characters
 134 * ARM-Regs::                 Register Names
 135 @end menu
 136
 137 @node ARM-Chars
 138 @subsection Special Characters
 139
 140 @cindex line comment character, ARM
 141 @cindex ARM line comment character
 142 The presence of a @samp{@@} on a line indicates the start of a comment
 143 that extends to the end of the current line.  If a @samp{#} appears as
 144 the first character of a line, the whole line is treated as a comment.
 145
 146 @cindex line separator, ARM
 147 @cindex statement separator, ARM
 148 @cindex ARM line separator
 149 The @samp{;} character can be used instead of a newline to separate
 150 statements.
 151
 152 @cindex immediate character, ARM
 153 @cindex ARM immediate character
 154 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 155
 156 @cindex identifiers, ARM
 157 @cindex ARM identifiers
 158 *TODO* Explain about /data modifier on symbols.
 159
 160 @node ARM-Regs
 161 @subsection Register Names
 162
 163 @cindex ARM register names
 164 @cindex register names, ARM
 165 *TODO* Explain about ARM register naming, and the predefined names.
 166
 167 @node ARM Floating Point
 168 @section Floating Point
 169
 170 @cindex floating point, ARM (@sc{ieee})
 171 @cindex ARM floating point (@sc{ieee})
 172 The ARM family uses @sc{ieee} floating-point numbers.
 173
 174
 175
 176 @node ARM Directives
 177 @section ARM Machine Directives
 178
 179 @cindex machine directives, ARM
 180 @cindex ARM machine directives
 181 @table @code
 182
 183 @cindex @code{align} directive, ARM
 184 @item .align @var{expression} [, @var{expression}]
 185 This is the generic @var{.align} directive.  For the ARM however if the
 186 first argument is zero (ie no alignment is needed) the assembler will
 187 behave as if the argument had been 2 (ie pad to the next four byte
 188 boundary).  This is for compatability with ARM's own assembler.
 189
 190 @cindex @code{req} directive, ARM
 191 @item @var{name} .req @var{register name}
 192 This creates an alias for @var{register name} called @var{name}.  For
 193 example:
 194
 195 @smallexample
 196         foo .req r0
 197 @end smallexample
 198
 199 @cindex @code{code} directive, ARM
 200 @item .code @code{[16|32]}
 201 This directive selects the instruction set being generated. The value 16
 202 selects Thumb, with the value 32 selecting ARM.
 203
 204 @cindex @code{thumb} directive, ARM
 205 @item .thumb
 206 This performs the same action as @var{.code 16}.
 207
 208 @cindex @code{arm} directive, ARM
 209 @item .arm
 210 This performs the same action as @var{.code 32}.
 211
 212 @cindex @code{force_thumb} directive, ARM
 213 @item .force_thumb
 214 This directive forces the selection of Thumb instructions, even if the
 215 target processor does not support those instructions
 216
 217 @cindex @code{thumb_func} directive, ARM
 218 @item .thumb_func
 219 This directive specifies that the following symbol is the name of a
 220 Thumb encoded function.  This information is necessary in order to allow
 221 the assembler and linker to generate correct code for interworking
 222 between Arm and Thumb instructions and should be used even if
 223 interworking is not going to be performed.  The presence of this
 224 directive also implies @code{.thumb}
 225
 226 @cindex @code{thumb_set} directive, ARM
 227 @item .thumb_set
 228 This performs the equivalent of a @code{.set} directive in that it
 229 creates a symbol which is an alias for another symbol (possibly not yet
 230 defined).  This directive also has the added property in that it marks
 231 the aliased symbol as being a thumb function entry point, in the same
 232 way that the @code{.thumb_func} directive does.
 233
 234 @cindex @code{.ltorg} directive, ARM
 235 @item .ltorg
 236 This directive causes the current contents of the literal pool to be
 237 dumped into the current section (which is assumed to be the .text
 238 section) at the current location (aligned to a word boundary).
 239
 240 @cindex @code{.pool} directive, ARM
 241 @item .pool
 242 This is a synonym for .ltorg.
 243
 244 @end table
 245
 246 @node ARM Opcodes
 247 @section Opcodes
 248
 249 @cindex ARM opcodes
 250 @cindex opcodes for ARM
 251 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 252 implements several pseudo opcodes, including several synthetic load
 253 instructions.
 254
 255 @table @code
 256
 257 @cindex @code{NOP} pseudo op, ARM
 258 @item NOP
 259 @smallexample
 260   nop
 261 @end smallexample
 262
 263 This pseudo op will always evaluate to a legal ARM instruction that does
 264 nothing.  Currently it will evaluate to MOV r0, r0.
 265
 266 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 267 @item LDR
 268 @smallexample
 269   ldr <register> , = <expression>
 270 @end smallexample
 271
 272 If expression evaluates to a numeric constant then a MOV or MVN
 273 instruction will be used in place of the LDR instruction, if the
 274 constant can be generated by either of these instructions.  Otherwise
 275 the constant will be placed into the nearest literal pool (if it not
 276 already there) and a PC relative LDR instruction will be generated.
 277
 278 @cindex @code{ADR reg,<label>} pseudo op, ARM
 279 @item ADR
 280 @smallexample
 281   adr <register> <label>
 282 @end smallexample
 283
 284 This instruction will load the address of @var{label} into the indicated
 285 register.  The instruction will evaluate to a PC relative ADD or SUB
 286 instruction depending upon where the label is located.  If the label is
 287 out of range, or if it is not defined in the same file (and section) as
 288 the ADR instruction, then an error will be generated.  This instruction
 289 will not make use of the literal pool.
 290
 291 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 292 @item ADRL
 293 @smallexample
 294   adrl <register> <label>
 295 @end smallexample
 296
 297 This instruction will load the address of @var{label} into the indicated
 298 register.  The instruction will evaluate to one or two PC relative ADD
 299 or SUB instructions depending upon where the label is located.  If a
 300 second instruction is not needed a NOP instruction will be generated in
 301 its place, so that this instruction is always 8 bytes long.
 302
 303 If the label is out of range, or if it is not defined in the same file
 304 (and section) as the ADRL instruction, then an error will be generated.
 305 This instruction will not make use of the literal pool.
 306
 307 @end table
 308
 309 For information on the ARM or Thumb instruction sets, see @cite{ARM
 310 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 311 Ltd.
 312