1 @c Copyright 1996-2013 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
130 @code{cortex-m0plus},
131 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
132 @code{i80200} (Intel XScale processor)
133 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
136 The special name @code{all} may be used to allow the
137 assembler to accept instructions valid for any ARM processor.
139 In addition to the basic instruction set, the assembler can be told to
140 accept various extension mnemonics that extend the processor using the
141 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
142 is equivalent to specifying @code{-mcpu=ep9312}.
144 Multiple extensions may be specified, separated by a @code{+}. The
145 extensions should be specified in ascending alphabetical order.
147 Some extensions may be restricted to particular architectures; this is
148 documented in the list of extensions below.
150 Extension mnemonics may also be removed from those the assembler accepts.
151 This is done be prepending @code{no} to the option that adds the extension.
152 Extensions that are removed should be listed after all extensions which have
153 been added, again in ascending alphabetical order. For example,
154 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
157 The following extensions are currently supported:
158 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
159 @code{fp} (Floating Point Extensions for v8-A architecture),
160 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
164 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
165 @code{os} (Operating System for v6M architecture),
166 @code{sec} (Security Extensions for v6K and v7-A architectures),
167 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
168 @code{virt} (Virtualization Extensions for v7-A architecture, implies
173 @cindex @code{-march=} command line option, ARM
174 @item -march=@var{architecture}[+@var{extension}@dots{}]
175 This option specifies the target architecture. The assembler will issue
176 an error message if an attempt is made to assemble an instruction which
177 will not execute on the target architecture. The following architecture
178 names are recognized:
210 If both @code{-mcpu} and
211 @code{-march} are specified, the assembler will use
212 the setting for @code{-mcpu}.
214 The architecture option can be extended with the same instruction set
215 extension options as the @code{-mcpu} option.
217 @cindex @code{-mfpu=} command line option, ARM
218 @item -mfpu=@var{floating-point-format}
220 This option specifies the floating point format to assemble for. The
221 assembler will issue an error message if an attempt is made to assemble
222 an instruction which will not execute on the target floating point unit.
223 The following format options are recognized:
243 @code{vfpv3-d16-fp16},
256 @code{neon-fp-armv8},
258 @code{crypto-neon-fp-armv8}.
260 In addition to determining which instructions are assembled, this option
261 also affects the way in which the @code{.double} assembler directive behaves
262 when assembling little-endian code.
264 The default is dependent on the processor selected. For Architecture 5 or
265 later, the default is to assembler for VFP instructions; for earlier
266 architectures the default is to assemble for FPA instructions.
268 @cindex @code{-mthumb} command line option, ARM
270 This option specifies that the assembler should start assembling Thumb
271 instructions; that is, it should behave as though the file starts with a
272 @code{.code 16} directive.
274 @cindex @code{-mthumb-interwork} command line option, ARM
275 @item -mthumb-interwork
276 This option specifies that the output generated by the assembler should
277 be marked as supporting interworking.
279 @cindex @code{-mimplicit-it} command line option, ARM
280 @item -mimplicit-it=never
281 @itemx -mimplicit-it=always
282 @itemx -mimplicit-it=arm
283 @itemx -mimplicit-it=thumb
284 The @code{-mimplicit-it} option controls the behavior of the assembler when
285 conditional instructions are not enclosed in IT blocks.
286 There are four possible behaviors.
287 If @code{never} is specified, such constructs cause a warning in ARM
288 code and an error in Thumb-2 code.
289 If @code{always} is specified, such constructs are accepted in both
290 ARM and Thumb-2 code, where the IT instruction is added implicitly.
291 If @code{arm} is specified, such constructs are accepted in ARM code
292 and cause an error in Thumb-2 code.
293 If @code{thumb} is specified, such constructs cause a warning in ARM
294 code and are accepted in Thumb-2 code. If you omit this option, the
295 behavior is equivalent to @code{-mimplicit-it=arm}.
297 @cindex @code{-mapcs-26} command line option, ARM
298 @cindex @code{-mapcs-32} command line option, ARM
301 These options specify that the output generated by the assembler should
302 be marked as supporting the indicated version of the Arm Procedure.
305 @cindex @code{-matpcs} command line option, ARM
307 This option specifies that the output generated by the assembler should
308 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
309 enabled this option will cause the assembler to create an empty
310 debugging section in the object file called .arm.atpcs. Debuggers can
311 use this to determine the ABI being used by.
313 @cindex @code{-mapcs-float} command line option, ARM
315 This indicates the floating point variant of the APCS should be
316 used. In this variant floating point arguments are passed in FP
317 registers rather than integer registers.
319 @cindex @code{-mapcs-reentrant} command line option, ARM
320 @item -mapcs-reentrant
321 This indicates that the reentrant variant of the APCS should be used.
322 This variant supports position independent code.
324 @cindex @code{-mfloat-abi=} command line option, ARM
325 @item -mfloat-abi=@var{abi}
326 This option specifies that the output generated by the assembler should be
327 marked as using specified floating point ABI.
328 The following values are recognized:
334 @cindex @code{-eabi=} command line option, ARM
335 @item -meabi=@var{ver}
336 This option specifies which EABI version the produced object files should
338 The following values are recognized:
344 @cindex @code{-EB} command line option, ARM
346 This option specifies that the output generated by the assembler should
347 be marked as being encoded for a big-endian processor.
349 @cindex @code{-EL} command line option, ARM
351 This option specifies that the output generated by the assembler should
352 be marked as being encoded for a little-endian processor.
354 @cindex @code{-k} command line option, ARM
355 @cindex PIC code generation for ARM
357 This option specifies that the output of the assembler should be marked
358 as position-independent code (PIC).
360 @cindex @code{--fix-v4bx} command line option, ARM
362 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
363 the linker option of the same name.
365 @cindex @code{-mwarn-deprecated} command line option, ARM
366 @item -mwarn-deprecated
367 @itemx -mno-warn-deprecated
368 Enable or disable warnings about using deprecated options or
369 features. The default is to warn.
377 * ARM-Instruction-Set:: Instruction Set
378 * ARM-Chars:: Special Characters
379 * ARM-Regs:: Register Names
380 * ARM-Relocations:: Relocations
381 * ARM-Neon-Alignment:: NEON Alignment Specifiers
384 @node ARM-Instruction-Set
385 @subsection Instruction Set Syntax
386 Two slightly different syntaxes are support for ARM and THUMB
387 instructions. The default, @code{divided}, uses the old style where
388 ARM and THUMB instructions had their own, separate syntaxes. The new,
389 @code{unified} syntax, which can be selected via the @code{.syntax}
390 directive, and has the following main features:
394 Immediate operands do not require a @code{#} prefix.
397 The @code{IT} instruction may appear, and if it does it is validated
398 against subsequent conditional affixes. In ARM mode it does not
399 generate machine code, in THUMB mode it does.
402 For ARM instructions the conditional affixes always appear at the end
403 of the instruction. For THUMB instructions conditional affixes can be
404 used, but only inside the scope of an @code{IT} instruction.
407 All of the instructions new to the V6T2 architecture (and later) are
408 available. (Only a few such instructions can be written in the
409 @code{divided} syntax).
412 The @code{.N} and @code{.W} suffixes are recognized and honored.
415 All instructions set the flags if and only if they have an @code{s}
420 @subsection Special Characters
422 @cindex line comment character, ARM
423 @cindex ARM line comment character
424 The presence of a @samp{@@} anywhere on a line indicates the start of
425 a comment that extends to the end of that line.
427 If a @samp{#} appears as the first character of a line then the whole
428 line is treated as a comment, but in this case the line could also be
429 a logical line number directive (@pxref{Comments}) or a preprocessor
430 control command (@pxref{Preprocessing}).
432 @cindex line separator, ARM
433 @cindex statement separator, ARM
434 @cindex ARM line separator
435 The @samp{;} character can be used instead of a newline to separate
438 @cindex immediate character, ARM
439 @cindex ARM immediate character
440 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
442 @cindex identifiers, ARM
443 @cindex ARM identifiers
444 *TODO* Explain about /data modifier on symbols.
447 @subsection Register Names
449 @cindex ARM register names
450 @cindex register names, ARM
451 *TODO* Explain about ARM register naming, and the predefined names.
453 @node ARM-Relocations
454 @subsection ARM relocation generation
456 @cindex data relocations, ARM
457 @cindex ARM data relocations
458 Specific data relocations can be generated by putting the relocation name
459 in parentheses after the symbol name. For example:
465 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
467 The following relocations are supported:
483 For compatibility with older toolchains the assembler also accepts
484 @code{(PLT)} after branch targets. On legacy targets this will
485 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
486 targets it will encode either the @samp{R_ARM_CALL} or
487 @samp{R_ARM_JUMP24} relocation, as appropriate.
489 @cindex MOVW and MOVT relocations, ARM
490 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
491 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
492 respectively. For example to load the 32-bit address of foo into r0:
495 MOVW r0, #:lower16:foo
496 MOVT r0, #:upper16:foo
499 @node ARM-Neon-Alignment
500 @subsection NEON Alignment Specifiers
502 @cindex alignment for NEON instructions
503 Some NEON load/store instructions allow an optional address
505 The ARM documentation specifies that this is indicated by
506 @samp{@@ @var{align}}. However GAS already interprets
507 the @samp{@@} character as a "line comment" start,
508 so @samp{: @var{align}} is used instead. For example:
511 vld1.8 @{q0@}, [r0, :128]
514 @node ARM Floating Point
515 @section Floating Point
517 @cindex floating point, ARM (@sc{ieee})
518 @cindex ARM floating point (@sc{ieee})
519 The ARM family uses @sc{ieee} floating-point numbers.
522 @section ARM Machine Directives
524 @cindex machine directives, ARM
525 @cindex ARM machine directives
528 @c AAAAAAAAAAAAAAAAAAAAAAAAA
530 @cindex @code{.2byte} directive, ARM
531 @cindex @code{.4byte} directive, ARM
532 @cindex @code{.8byte} directive, ARM
533 @item .2byte @var{expression} [, @var{expression}]*
534 @itemx .4byte @var{expression} [, @var{expression}]*
535 @itemx .8byte @var{expression} [, @var{expression}]*
536 These directives write 2, 4 or 8 byte values to the output section.
538 @cindex @code{.align} directive, ARM
539 @item .align @var{expression} [, @var{expression}]
540 This is the generic @var{.align} directive. For the ARM however if the
541 first argument is zero (ie no alignment is needed) the assembler will
542 behave as if the argument had been 2 (ie pad to the next four byte
543 boundary). This is for compatibility with ARM's own assembler.
545 @cindex @code{.arch} directive, ARM
546 @item .arch @var{name}
547 Select the target architecture. Valid values for @var{name} are the same as
548 for the @option{-march} commandline option.
550 Specifying @code{.arch} clears any previously selected architecture
553 @cindex @code{.arch_extension} directive, ARM
554 @item .arch_extension @var{name}
555 Add or remove an architecture extension to the target architecture. Valid
556 values for @var{name} are the same as those accepted as architectural
557 extensions by the @option{-mcpu} commandline option.
559 @code{.arch_extension} may be used multiple times to add or remove extensions
560 incrementally to the architecture being compiled for.
562 @cindex @code{.arm} directive, ARM
564 This performs the same action as @var{.code 32}.
567 @cindex @code{.pad} directive, ARM
568 @item .pad #@var{count}
569 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
570 A positive value indicates the function prologue allocated stack space by
571 decrementing the stack pointer.
573 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
575 @cindex @code{.bss} directive, ARM
577 This directive switches to the @code{.bss} section.
579 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
581 @cindex @code{.cantunwind} directive, ARM
583 Prevents unwinding through the current function. No personality routine
584 or exception table data is required or permitted.
586 @cindex @code{.code} directive, ARM
587 @item .code @code{[16|32]}
588 This directive selects the instruction set being generated. The value 16
589 selects Thumb, with the value 32 selecting ARM.
591 @cindex @code{.cpu} directive, ARM
592 @item .cpu @var{name}
593 Select the target processor. Valid values for @var{name} are the same as
594 for the @option{-mcpu} commandline option.
596 Specifying @code{.cpu} clears any previously selected architecture
599 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
601 @cindex @code{.dn} and @code{.qn} directives, ARM
602 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
603 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
605 The @code{dn} and @code{qn} directives are used to create typed
606 and/or indexed register aliases for use in Advanced SIMD Extension
607 (Neon) instructions. The former should be used to create aliases
608 of double-precision registers, and the latter to create aliases of
609 quad-precision registers.
611 If these directives are used to create typed aliases, those aliases can
612 be used in Neon instructions instead of writing types after the mnemonic
613 or after each operand. For example:
622 This is equivalent to writing the following:
628 Aliases created using @code{dn} or @code{qn} can be destroyed using
631 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
633 @cindex @code{.eabi_attribute} directive, ARM
634 @item .eabi_attribute @var{tag}, @var{value}
635 Set the EABI object attribute @var{tag} to @var{value}.
637 The @var{tag} is either an attribute number, or one of the following:
638 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
639 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
640 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
641 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
642 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
643 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
644 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
645 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
646 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
647 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
648 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
649 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
650 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
651 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
652 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
653 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
654 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
655 @code{Tag_conformance}, @code{Tag_T2EE_use},
656 @code{Tag_Virtualization_use}
658 The @var{value} is either a @code{number}, @code{"string"}, or
659 @code{number, "string"} depending on the tag.
661 Note - the following legacy values are also accepted by @var{tag}:
662 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
663 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
665 @cindex @code{.even} directive, ARM
667 This directive aligns to an even-numbered address.
669 @cindex @code{.extend} directive, ARM
670 @cindex @code{.ldouble} directive, ARM
671 @item .extend @var{expression} [, @var{expression}]*
672 @itemx .ldouble @var{expression} [, @var{expression}]*
673 These directives write 12byte long double floating-point values to the
674 output section. These are not compatible with current ARM processors
677 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
680 @cindex @code{.fnend} directive, ARM
682 Marks the end of a function with an unwind table entry. The unwind index
683 table entry is created when this directive is processed.
685 If no personality routine has been specified then standard personality
686 routine 0 or 1 will be used, depending on the number of unwind opcodes
690 @cindex @code{.fnstart} directive, ARM
692 Marks the start of a function with an unwind table entry.
694 @cindex @code{.force_thumb} directive, ARM
696 This directive forces the selection of Thumb instructions, even if the
697 target processor does not support those instructions
699 @cindex @code{.fpu} directive, ARM
700 @item .fpu @var{name}
701 Select the floating-point unit to assemble for. Valid values for @var{name}
702 are the same as for the @option{-mfpu} commandline option.
704 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
705 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
707 @cindex @code{.handlerdata} directive, ARM
709 Marks the end of the current function, and the start of the exception table
710 entry for that function. Anything between this directive and the
711 @code{.fnend} directive will be added to the exception table entry.
713 Must be preceded by a @code{.personality} or @code{.personalityindex}
716 @c IIIIIIIIIIIIIIIIIIIIIIIIII
718 @cindex @code{.inst} directive, ARM
719 @item .inst @var{opcode} [ , @dots{} ]
720 @itemx .inst.n @var{opcode} [ , @dots{} ]
721 @itemx .inst.w @var{opcode} [ , @dots{} ]
722 Generates the instruction corresponding to the numerical value @var{opcode}.
723 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
724 specified explicitly, overriding the normal encoding rules.
726 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
727 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
728 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
730 @item .ldouble @var{expression} [, @var{expression}]*
733 @cindex @code{.ltorg} directive, ARM
735 This directive causes the current contents of the literal pool to be
736 dumped into the current section (which is assumed to be the .text
737 section) at the current location (aligned to a word boundary).
738 @code{GAS} maintains a separate literal pool for each section and each
739 sub-section. The @code{.ltorg} directive will only affect the literal
740 pool of the current section and sub-section. At the end of assembly
741 all remaining, un-empty literal pools will automatically be dumped.
743 Note - older versions of @code{GAS} would dump the current literal
744 pool any time a section change occurred. This is no longer done, since
745 it prevents accurate control of the placement of literal pools.
747 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
749 @cindex @code{.movsp} directive, ARM
750 @item .movsp @var{reg} [, #@var{offset}]
751 Tell the unwinder that @var{reg} contains an offset from the current
752 stack pointer. If @var{offset} is not specified then it is assumed to be
755 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
756 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
758 @cindex @code{.object_arch} directive, ARM
759 @item .object_arch @var{name}
760 Override the architecture recorded in the EABI object attribute section.
761 Valid values for @var{name} are the same as for the @code{.arch} directive.
762 Typically this is useful when code uses runtime detection of CPU features.
764 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
766 @cindex @code{.packed} directive, ARM
767 @item .packed @var{expression} [, @var{expression}]*
768 This directive writes 12-byte packed floating-point values to the
769 output section. These are not compatible with current ARM processors
772 @cindex @code{.pad} directive, ARM
773 @item .pad #@var{count}
774 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
775 A positive value indicates the function prologue allocated stack space by
776 decrementing the stack pointer.
778 @cindex @code{.personality} directive, ARM
779 @item .personality @var{name}
780 Sets the personality routine for the current function to @var{name}.
782 @cindex @code{.personalityindex} directive, ARM
783 @item .personalityindex @var{index}
784 Sets the personality routine for the current function to the EABI standard
785 routine number @var{index}
787 @cindex @code{.pool} directive, ARM
789 This is a synonym for .ltorg.
791 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
792 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
794 @cindex @code{.req} directive, ARM
795 @item @var{name} .req @var{register name}
796 This creates an alias for @var{register name} called @var{name}. For
803 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
806 @cindex @code{.save} directive, ARM
807 @item .save @var{reglist}
808 Generate unwinder annotations to restore the registers in @var{reglist}.
809 The format of @var{reglist} is the same as the corresponding store-multiple
813 @exdent @emph{core registers}
814 .save @{r4, r5, r6, lr@}
815 stmfd sp!, @{r4, r5, r6, lr@}
816 @exdent @emph{FPA registers}
819 @exdent @emph{VFP registers}
820 .save @{d8, d9, d10@}
821 fstmdx sp!, @{d8, d9, d10@}
822 @exdent @emph{iWMMXt registers}
824 wstrd wr11, [sp, #-8]!
825 wstrd wr10, [sp, #-8]!
828 wstrd wr11, [sp, #-8]!
830 wstrd wr10, [sp, #-8]!
834 @cindex @code{.setfp} directive, ARM
835 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
836 Make all unwinder annotations relative to a frame pointer. Without this
837 the unwinder will use offsets from the stack pointer.
839 The syntax of this directive is the same as the @code{add} or @code{mov}
840 instruction used to set the frame pointer. @var{spreg} must be either
841 @code{sp} or mentioned in a previous @code{.movsp} directive.
851 @cindex @code{.secrel32} directive, ARM
852 @item .secrel32 @var{expression} [, @var{expression}]*
853 This directive emits relocations that evaluate to the section-relative
854 offset of each expression's symbol. This directive is only supported
857 @cindex @code{.syntax} directive, ARM
858 @item .syntax [@code{unified} | @code{divided}]
859 This directive sets the Instruction Set Syntax as described in the
860 @ref{ARM-Instruction-Set} section.
862 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
864 @cindex @code{.thumb} directive, ARM
866 This performs the same action as @var{.code 16}.
868 @cindex @code{.thumb_func} directive, ARM
870 This directive specifies that the following symbol is the name of a
871 Thumb encoded function. This information is necessary in order to allow
872 the assembler and linker to generate correct code for interworking
873 between Arm and Thumb instructions and should be used even if
874 interworking is not going to be performed. The presence of this
875 directive also implies @code{.thumb}
877 This directive is not neccessary when generating EABI objects. On these
878 targets the encoding is implicit when generating Thumb code.
880 @cindex @code{.thumb_set} directive, ARM
882 This performs the equivalent of a @code{.set} directive in that it
883 creates a symbol which is an alias for another symbol (possibly not yet
884 defined). This directive also has the added property in that it marks
885 the aliased symbol as being a thumb function entry point, in the same
886 way that the @code{.thumb_func} directive does.
888 @cindex @code{.tlsdescseq} directive, ARM
889 @item .tlsdescseq @var{tls-variable}
890 This directive is used to annotate parts of an inlined TLS descriptor
891 trampoline. Normally the trampoline is provided by the linker, and
892 this directive is not needed.
894 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
896 @cindex @code{.unreq} directive, ARM
897 @item .unreq @var{alias-name}
898 This undefines a register alias which was previously defined using the
899 @code{req}, @code{dn} or @code{qn} directives. For example:
906 An error occurs if the name is undefined. Note - this pseudo op can
907 be used to delete builtin in register name aliases (eg 'r0'). This
908 should only be done if it is really necessary.
910 @cindex @code{.unwind_raw} directive, ARM
911 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
912 Insert one of more arbitary unwind opcode bytes, which are known to adjust
913 the stack pointer by @var{offset} bytes.
915 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
918 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
920 @cindex @code{.vsave} directive, ARM
921 @item .vsave @var{vfp-reglist}
922 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
923 using FLDMD. Also works for VFPv3 registers
924 that are to be restored using VLDM.
925 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
929 @exdent @emph{VFP registers}
930 .vsave @{d8, d9, d10@}
931 fstmdd sp!, @{d8, d9, d10@}
932 @exdent @emph{VFPv3 registers}
933 .vsave @{d15, d16, d17@}
934 vstm sp!, @{d15, d16, d17@}
937 Since FLDMX and FSTMX are now deprecated, this directive should be
938 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
940 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
941 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
942 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
943 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
951 @cindex opcodes for ARM
952 @code{@value{AS}} implements all the standard ARM opcodes. It also
953 implements several pseudo opcodes, including several synthetic load
958 @cindex @code{NOP} pseudo op, ARM
964 This pseudo op will always evaluate to a legal ARM instruction that does
965 nothing. Currently it will evaluate to MOV r0, r0.
967 @cindex @code{LDR reg,=<label>} pseudo op, ARM
970 ldr <register> , = <expression>
973 If expression evaluates to a numeric constant then a MOV or MVN
974 instruction will be used in place of the LDR instruction, if the
975 constant can be generated by either of these instructions. Otherwise
976 the constant will be placed into the nearest literal pool (if it not
977 already there) and a PC relative LDR instruction will be generated.
979 @cindex @code{ADR reg,<label>} pseudo op, ARM
982 adr <register> <label>
985 This instruction will load the address of @var{label} into the indicated
986 register. The instruction will evaluate to a PC relative ADD or SUB
987 instruction depending upon where the label is located. If the label is
988 out of range, or if it is not defined in the same file (and section) as
989 the ADR instruction, then an error will be generated. This instruction
990 will not make use of the literal pool.
992 @cindex @code{ADRL reg,<label>} pseudo op, ARM
995 adrl <register> <label>
998 This instruction will load the address of @var{label} into the indicated
999 register. The instruction will evaluate to one or two PC relative ADD
1000 or SUB instructions depending upon where the label is located. If a
1001 second instruction is not needed a NOP instruction will be generated in
1002 its place, so that this instruction is always 8 bytes long.
1004 If the label is out of range, or if it is not defined in the same file
1005 (and section) as the ADRL instruction, then an error will be generated.
1006 This instruction will not make use of the literal pool.
1010 For information on the ARM or Thumb instruction sets, see @cite{ARM
1011 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1014 @node ARM Mapping Symbols
1015 @section Mapping Symbols
1017 The ARM ELF specification requires that special symbols be inserted
1018 into object files to mark certain features:
1024 At the start of a region of code containing ARM instructions.
1028 At the start of a region of code containing THUMB instructions.
1032 At the start of a region of data.
1036 The assembler will automatically insert these symbols for you - there
1037 is no need to code them yourself. Support for tagging symbols ($b,
1038 $f, $p and $m) which is also mentioned in the current ARM ELF
1039 specification is not implemented. This is because they have been
1040 dropped from the new EABI and so tools cannot rely upon their
1043 @node ARM Unwinding Tutorial
1046 The ABI for the ARM Architecture specifies a standard format for
1047 exception unwind information. This information is used when an
1048 exception is thrown to determine where control should be transferred.
1049 In particular, the unwind information is used to determine which
1050 function called the function that threw the exception, and which
1051 function called that one, and so forth. This information is also used
1052 to restore the values of callee-saved registers in the function
1053 catching the exception.
1055 If you are writing functions in assembly code, and those functions
1056 call other functions that throw exceptions, you must use assembly
1057 pseudo ops to ensure that appropriate exception unwind information is
1058 generated. Otherwise, if one of the functions called by your assembly
1059 code throws an exception, the run-time library will be unable to
1060 unwind the stack through your assembly code and your program will not
1063 To illustrate the use of these pseudo ops, we will examine the code
1064 that G++ generates for the following C++ input:
1067 void callee (int *);
1078 This example does not show how to throw or catch an exception from
1079 assembly code. That is a much more complex operation and should
1080 always be done in a high-level language, such as C++, that directly
1081 supports exceptions.
1083 The code generated by one particular version of G++ when compiling the
1090 @ Function supports interworking.
1091 @ args = 0, pretend = 0, frame = 8
1092 @ frame_needed = 1, uses_anonymous_args = 0
1114 Of course, the sequence of instructions varies based on the options
1115 you pass to GCC and on the version of GCC in use. The exact
1116 instructions are not important since we are focusing on the pseudo ops
1117 that are used to generate unwind information.
1119 An important assumption made by the unwinder is that the stack frame
1120 does not change during the body of the function. In particular, since
1121 we assume that the assembly code does not itself throw an exception,
1122 the only point where an exception can be thrown is from a call, such
1123 as the @code{bl} instruction above. At each call site, the same saved
1124 registers (including @code{lr}, which indicates the return address)
1125 must be located in the same locations relative to the frame pointer.
1127 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1128 op appears immediately before the first instruction of the function
1129 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1130 op appears immediately after the last instruction of the function.
1131 These pseudo ops specify the range of the function.
1133 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1134 @code{.pad}) matters; their exact locations are irrelevant. In the
1135 example above, the compiler emits the pseudo ops with particular
1136 instructions. That makes it easier to understand the code, but it is
1137 not required for correctness. It would work just as well to emit all
1138 of the pseudo ops other than @code{.fnend} in the same order, but
1139 immediately after @code{.fnstart}.
1141 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1142 indicates registers that have been saved to the stack so that they can
1143 be restored before the function returns. The argument to the
1144 @code{.save} pseudo op is a list of registers to save. If a register
1145 is ``callee-saved'' (as specified by the ABI) and is modified by the
1146 function you are writing, then your code must save the value before it
1147 is modified and restore the original value before the function
1148 returns. If an exception is thrown, the run-time library restores the
1149 values of these registers from their locations on the stack before
1150 returning control to the exception handler. (Of course, if an
1151 exception is not thrown, the function that contains the @code{.save}
1152 pseudo op restores these registers in the function epilogue, as is
1153 done with the @code{ldmfd} instruction above.)
1155 You do not have to save callee-saved registers at the very beginning
1156 of the function and you do not need to use the @code{.save} pseudo op
1157 immediately following the point at which the registers are saved.
1158 However, if you modify a callee-saved register, you must save it on
1159 the stack before modifying it and before calling any functions which
1160 might throw an exception. And, you must use the @code{.save} pseudo
1161 op to indicate that you have done so.
1163 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1164 modification of the stack pointer that does not save any registers.
1165 The argument is the number of bytes (in decimal) that are subtracted
1166 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1167 subtracting from the stack pointer increases the size of the stack.)
1169 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1170 indicates the register that contains the frame pointer. The first
1171 argument is the register that is set, which is typically @code{fp}.
1172 The second argument indicates the register from which the frame
1173 pointer takes its value. The third argument, if present, is the value
1174 (in decimal) added to the register specified by the second argument to
1175 compute the value of the frame pointer. You should not modify the
1176 frame pointer in the body of the function.
1178 If you do not use a frame pointer, then you should not use the
1179 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1180 should avoid modifying the stack pointer outside of the function
1181 prologue. Otherwise, the run-time library will be unable to find
1182 saved registers when it is unwinding the stack.
1184 The pseudo ops described above are sufficient for writing assembly
1185 code that calls functions which may throw exceptions. If you need to
1186 know more about the object-file format used to represent unwind
1187 information, you may consult the @cite{Exception Handling ABI for the
1188 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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