gas/doc/c-arm.texi

   1 @c Copyright (C) 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4
   5 @ifset GENERIC
   6 @page
   7 @node ARM-Dependent
   8 @chapter ARM Dependent Features
   9 @end ifset
  10
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter ARM Dependent Features
  14 @end ifclear
  15
  16 @cindex ARM support
  17 @cindex Thumb support
  18 @menu
  19 * ARM Options::              Options
  20 * ARM Syntax::               Syntax
  21 * ARM Floating Point::       Floating Point
  22 * ARM Directives::           ARM Machine Directives
  23 * ARM Opcodes::              Opcodes
  24 @end menu
  25
  26 @node ARM Options
  27 @section Options
  28 @cindex ARM options (none)
  29 @cindex options for ARM (none)
  30
  31 @table @code
  32
  33 @cindex @code{-marm} command line option, ARM
  34 @item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
  35 @itemx -mxscale
  36 This option specifies the target processor.  The assembler will issue an
  37 error message if an attempt is made to assemble an instruction which
  38 will not execute on the target processor.
  39
  40 @cindex @code{-marmv} command line option, ARM
  41 @item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]}
  42 This option specifies the target architecture.  The assembler will issue
  43 an error message if an attempt is made to assemble an instruction which
  44 will not execute on the target architecture.
  45 The option @code{-marmv5te} specifies that v5t architecture should be
  46 used with the El Segundo extensions enabled.
  47
  48 @cindex @code{-mthumb} command line option, ARM
  49 @item -mthumb
  50 This option specifies that only Thumb instructions should be assembled.
  51
  52 @cindex @code{-mall} command line option, ARM
  53 @item -mall
  54 This option specifies that any Arm or Thumb instruction should be assembled.
  55
  56 @cindex @code{-mfpa} command line option, ARM
  57 @item -mfpa @code{[10|11]}
  58 This option specifies the floating point architecture in use on the
  59 target processor.
  60
  61 @cindex @code{-mfpe-old} command line option, ARM
  62 @item -mfpe-old
  63 Do not allow the assembly of floating point multiple instructions.
  64
  65 @cindex @code{-mno-fpu} command line option, ARM
  66 @item -mno-fpu
  67 Do not allow the assembly of any floating point instructions.
  68
  69 @cindex @code{-mthumb-interwork} command line option, ARM
  70 @item -mthumb-interwork
  71 This option specifies that the output generated by the assembler should
  72 be marked as supporting interworking.
  73
  74 @cindex @code{-mapcs} command line option, ARM
  75 @item -mapcs @code{[26|32]}
  76 This option specifies that the output generated by the assembler should
  77 be marked as supporting the indicated version of the Arm Procedure.
  78 Calling Standard.
  79
  80 @cindex @code{-matpcs} command line option, ARM
  81 @item -matpcs
  82 This option specifies that the output generated by the assembler should
  83 be marked as supporting the Arm/Thumb Procedure Calling Standard.  If
  84 enabled this option will cause the assembler to create an empty
  85 debugging section in the object file called .arm.atpcs.  Debuggers can
  86 use this to determine the ABI being used by.
  87
  88 @cindex @code{-mapcs-float} command line option, ARM
  89 @item -mapcs-float
  90 This indicates the the floating point variant of the APCS should be
  91 used.  In this variant floating point arguments are passed in FP
  92 registers rather than integer registers.
  93
  94 @cindex @code{-mapcs-reentrant} command line option, ARM
  95 @item -mapcs-reentrant
  96 This indicates that the reentrant variant of the APCS should be used.
  97 This variant supports position independent code.
  98
  99 @cindex @code{-EB} command line option, ARM
 100 @item -EB
 101 This option specifies that the output generated by the assembler should
 102 be marked as being encoded for a big-endian processor.
 103
 104 @cindex @code{-EL} command line option, ARM
 105 @item -EL
 106 This option specifies that the output generated by the assembler should
 107 be marked as being encoded for a little-endian processor.
 108
 109 @cindex @code{-k} command line option, ARM
 110 @cindex PIC code generation for ARM
 111 @item -k
 112 This option specifies that the output of the assembler should be marked
 113 as position-independent code (PIC).
 114
 115 @cindex @code{-moabi} command line option, ARM
 116 @item -moabi
 117 This indicates that the code should be assembled using the old ARM ELF
 118 conventions, based on a beta release release of the ARM-ELF
 119 specifications, rather than the default conventions which are based on
 120 the final release of the ARM-ELF specifications.
 121
 122 @end table
 123
 124
 125 @node ARM Syntax
 126 @section Syntax
 127 @menu
 128 * ARM-Chars::                Special Characters
 129 * ARM-Regs::                 Register Names
 130 @end menu
 131
 132 @node ARM-Chars
 133 @subsection Special Characters
 134
 135 @cindex line comment character, ARM
 136 @cindex ARM line comment character
 137 The presence of a @samp{@@} on a line indicates the start of a comment
 138 that extends to the end of the current line.  If a @samp{#} appears as
 139 the first character of a line, the whole line is treated as a comment.
 140
 141 @cindex line separator, ARM
 142 @cindex statement separator, ARM
 143 @cindex ARM line separator
 144 The @samp{;} character can be used instead of a newline to separate
 145 statements.
 146
 147 @cindex immediate character, ARM
 148 @cindex ARM immediate character
 149 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 150
 151 @cindex identifiers, ARM
 152 @cindex ARM identifiers
 153 *TODO* Explain about /data modifier on symbols.
 154
 155 @node ARM-Regs
 156 @subsection Register Names
 157
 158 @cindex ARM register names
 159 @cindex register names, ARM
 160 *TODO* Explain about ARM register naming, and the predefined names.
 161
 162 @node ARM Floating Point
 163 @section Floating Point
 164
 165 @cindex floating point, ARM (@sc{ieee})
 166 @cindex ARM floating point (@sc{ieee})
 167 The ARM family uses @sc{ieee} floating-point numbers.
 168
 169
 170
 171 @node ARM Directives
 172 @section ARM Machine Directives
 173
 174 @cindex machine directives, ARM
 175 @cindex ARM machine directives
 176 @table @code
 177
 178 @cindex @code{align} directive, ARM
 179 @item .align @var{expression} [, @var{expression}]
 180 This is the generic @var{.align} directive.  For the ARM however if the
 181 first argument is zero (ie no alignment is needed) the assembler will
 182 behave as if the argument had been 2 (ie pad to the next four byte
 183 boundary).  This is for compatability with ARM's own assembler.
 184
 185 @cindex @code{req} directive, ARM
 186 @item @var{name} .req @var{register name}
 187 This creates an alias for @var{register name} called @var{name}.  For
 188 example:
 189
 190 @smallexample
 191         foo .req r0
 192 @end smallexample
 193
 194 @cindex @code{code} directive, ARM
 195 @item .code @code{[16|32]}
 196 This directive selects the instruction set being generated. The value 16
 197 selects Thumb, with the value 32 selecting ARM.
 198
 199 @cindex @code{thumb} directive, ARM
 200 @item .thumb
 201 This performs the same action as @var{.code 16}.
 202
 203 @cindex @code{arm} directive, ARM
 204 @item .arm
 205 This performs the same action as @var{.code 32}.
 206
 207 @cindex @code{force_thumb} directive, ARM
 208 @item .force_thumb
 209 This directive forces the selection of Thumb instructions, even if the
 210 target processor does not support those instructions
 211
 212 @cindex @code{thumb_func} directive, ARM
 213 @item .thumb_func
 214 This directive specifies that the following symbol is the name of a
 215 Thumb encoded function.  This information is necessary in order to allow
 216 the assembler and linker to generate correct code for interworking
 217 between Arm and Thumb instructions and should be used even if
 218 interworking is not going to be performed.  The presence of this
 219 directive also implies @code{.thumb}
 220
 221 @cindex @code{thumb_set} directive, ARM
 222 @item .thumb_set
 223 This performs the equivalent of a @code{.set} directive in that it
 224 creates a symbol which is an alias for another symbol (possibly not yet
 225 defined).  This directive also has the added property in that it marks
 226 the aliased symbol as being a thumb function entry point, in the same
 227 way that the @code{.thumb_func} directive does.
 228
 229 @cindex @code{.ltorg} directive, ARM
 230 @item .ltorg
 231 This directive causes the current contents of the literal pool to be
 232 dumped into the current section (which is assumed to be the .text
 233 section) at the current location (aligned to a word boundary).
 234
 235 @cindex @code{.pool} directive, ARM
 236 @item .pool
 237 This is a synonym for .ltorg.
 238
 239 @end table
 240
 241 @node ARM Opcodes
 242 @section Opcodes
 243
 244 @cindex ARM opcodes
 245 @cindex opcodes for ARM
 246 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 247 implements several pseudo opcodes, including several synthetic load
 248 instructions.
 249
 250 @table @code
 251
 252 @cindex @code{NOP} pseudo op, ARM
 253 @item NOP
 254 @smallexample
 255   nop
 256 @end smallexample
 257
 258 This pseudo op will always evaluate to a legal ARM instruction that does
 259 nothing.  Currently it will evaluate to MOV r0, r0.
 260
 261 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 262 @item LDR
 263 @smallexample
 264   ldr <register> , = <expression>
 265 @end smallexample
 266
 267 If expression evaluates to a numeric constant then a MOV or MVN
 268 instruction will be used in place of the LDR instruction, if the
 269 constant can be generated by either of these instructions.  Otherwise
 270 the constant will be placed into the nearest literal pool (if it not
 271 already there) and a PC relative LDR instruction will be generated.
 272
 273 @cindex @code{ADR reg,<label>} pseudo op, ARM
 274 @item ADR
 275 @smallexample
 276   adr <register> <label>
 277 @end smallexample
 278
 279 This instruction will load the address of @var{label} into the indicated
 280 register.  The instruction will evaluate to a PC relative ADD or SUB
 281 instruction depending upon where the label is located.  If the label is
 282 out of range, or if it is not defined in the same file (and section) as
 283 the ADR instruction, then an error will be generated.  This instruction
 284 will not make use of the literal pool.
 285
 286 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 287 @item ADRL
 288 @smallexample
 289   adrl <register> <label>
 290 @end smallexample
 291
 292 This instruction will load the address of @var{label} into the indicated
 293 register.  The instruction will evaluate to one or two PC relative ADD
 294 or SUB instructions depending upon where the label is located.  If a
 295 second instruction is not needed a NOP instruction will be generated in
 296 its place, so that this instruction is always 8 bytes long.
 297
 298 If the label is out of range, or if it is not defined in the same file
 299 (and section) as the ADRL instruction, then an error will be generated.
 300 This instruction will not make use of the literal pool.
 301
 302 @end table
 303
 304 For information on the ARM or Thumb instruction sets, see @cite{ARM
 305 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 306 Ltd.
 307