1 @c Copyright (C) 1996-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
142 @code{cortex-m0plus},
145 @code{marvell-whitney},
148 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
149 @code{i80200} (Intel XScale processor)
150 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
153 The special name @code{all} may be used to allow the
154 assembler to accept instructions valid for any ARM processor.
156 In addition to the basic instruction set, the assembler can be told to
157 accept various extension mnemonics that extend the processor using the
158 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
159 is equivalent to specifying @code{-mcpu=ep9312}.
161 Multiple extensions may be specified, separated by a @code{+}. The
162 extensions should be specified in ascending alphabetical order.
164 Some extensions may be restricted to particular architectures; this is
165 documented in the list of extensions below.
167 Extension mnemonics may also be removed from those the assembler accepts.
168 This is done be prepending @code{no} to the option that adds the extension.
169 Extensions that are removed should be listed after all extensions which have
170 been added, again in ascending alphabetical order. For example,
171 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
174 The following extensions are currently supported:
176 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
177 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
178 @code{fp} (Floating Point Extensions for v8-A architecture),
179 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
184 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
186 @code{os} (Operating System for v6M architecture),
187 @code{sec} (Security Extensions for v6K and v7-A architectures),
188 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
189 @code{virt} (Virtualization Extensions for v7-A architecture, implies
191 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
192 @code{ras} (Reliability, Availability and Serviceability extensions
193 for v8-A architecture),
194 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
199 @cindex @code{-march=} command line option, ARM
200 @item -march=@var{architecture}[+@var{extension}@dots{}]
201 This option specifies the target architecture. The assembler will issue
202 an error message if an attempt is made to assemble an instruction which
203 will not execute on the target architecture. The following architecture
204 names are recognized:
242 If both @code{-mcpu} and
243 @code{-march} are specified, the assembler will use
244 the setting for @code{-mcpu}.
246 The architecture option can be extended with the same instruction set
247 extension options as the @code{-mcpu} option.
249 @cindex @code{-mfpu=} command line option, ARM
250 @item -mfpu=@var{floating-point-format}
252 This option specifies the floating point format to assemble for. The
253 assembler will issue an error message if an attempt is made to assemble
254 an instruction which will not execute on the target floating point unit.
255 The following format options are recognized:
275 @code{vfpv3-d16-fp16},
292 @code{neon-fp-armv8},
293 @code{crypto-neon-fp-armv8},
294 @code{neon-fp-armv8.1}
296 @code{crypto-neon-fp-armv8.1}.
298 In addition to determining which instructions are assembled, this option
299 also affects the way in which the @code{.double} assembler directive behaves
300 when assembling little-endian code.
302 The default is dependent on the processor selected. For Architecture 5 or
303 later, the default is to assemble for VFP instructions; for earlier
304 architectures the default is to assemble for FPA instructions.
306 @cindex @code{-mthumb} command line option, ARM
308 This option specifies that the assembler should start assembling Thumb
309 instructions; that is, it should behave as though the file starts with a
310 @code{.code 16} directive.
312 @cindex @code{-mthumb-interwork} command line option, ARM
313 @item -mthumb-interwork
314 This option specifies that the output generated by the assembler should
315 be marked as supporting interworking.
317 @cindex @code{-mimplicit-it} command line option, ARM
318 @item -mimplicit-it=never
319 @itemx -mimplicit-it=always
320 @itemx -mimplicit-it=arm
321 @itemx -mimplicit-it=thumb
322 The @code{-mimplicit-it} option controls the behavior of the assembler when
323 conditional instructions are not enclosed in IT blocks.
324 There are four possible behaviors.
325 If @code{never} is specified, such constructs cause a warning in ARM
326 code and an error in Thumb-2 code.
327 If @code{always} is specified, such constructs are accepted in both
328 ARM and Thumb-2 code, where the IT instruction is added implicitly.
329 If @code{arm} is specified, such constructs are accepted in ARM code
330 and cause an error in Thumb-2 code.
331 If @code{thumb} is specified, such constructs cause a warning in ARM
332 code and are accepted in Thumb-2 code. If you omit this option, the
333 behavior is equivalent to @code{-mimplicit-it=arm}.
335 @cindex @code{-mapcs-26} command line option, ARM
336 @cindex @code{-mapcs-32} command line option, ARM
339 These options specify that the output generated by the assembler should
340 be marked as supporting the indicated version of the Arm Procedure.
343 @cindex @code{-matpcs} command line option, ARM
345 This option specifies that the output generated by the assembler should
346 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
347 enabled this option will cause the assembler to create an empty
348 debugging section in the object file called .arm.atpcs. Debuggers can
349 use this to determine the ABI being used by.
351 @cindex @code{-mapcs-float} command line option, ARM
353 This indicates the floating point variant of the APCS should be
354 used. In this variant floating point arguments are passed in FP
355 registers rather than integer registers.
357 @cindex @code{-mapcs-reentrant} command line option, ARM
358 @item -mapcs-reentrant
359 This indicates that the reentrant variant of the APCS should be used.
360 This variant supports position independent code.
362 @cindex @code{-mfloat-abi=} command line option, ARM
363 @item -mfloat-abi=@var{abi}
364 This option specifies that the output generated by the assembler should be
365 marked as using specified floating point ABI.
366 The following values are recognized:
372 @cindex @code{-eabi=} command line option, ARM
373 @item -meabi=@var{ver}
374 This option specifies which EABI version the produced object files should
376 The following values are recognized:
382 @cindex @code{-EB} command line option, ARM
384 This option specifies that the output generated by the assembler should
385 be marked as being encoded for a big-endian processor.
387 Note: If a program is being built for a system with big-endian data
388 and little-endian instructions then it should be assembled with the
389 @option{-EB} option, (all of it, code and data) and then linked with
390 the @option{--be8} option. This will reverse the endianness of the
391 instructions back to little-endian, but leave the data as big-endian.
393 @cindex @code{-EL} command line option, ARM
395 This option specifies that the output generated by the assembler should
396 be marked as being encoded for a little-endian processor.
398 @cindex @code{-k} command line option, ARM
399 @cindex PIC code generation for ARM
401 This option specifies that the output of the assembler should be marked
402 as position-independent code (PIC).
404 @cindex @code{--fix-v4bx} command line option, ARM
406 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
407 the linker option of the same name.
409 @cindex @code{-mwarn-deprecated} command line option, ARM
410 @item -mwarn-deprecated
411 @itemx -mno-warn-deprecated
412 Enable or disable warnings about using deprecated options or
413 features. The default is to warn.
415 @cindex @code{-mccs} command line option, ARM
417 Turns on CodeComposer Studio assembly syntax compatibility mode.
419 @cindex @code{-mwarn-syms} command line option, ARM
421 @itemx -mno-warn-syms
422 Enable or disable warnings about symbols that match the names of ARM
423 instructions. The default is to warn.
431 * ARM-Instruction-Set:: Instruction Set
432 * ARM-Chars:: Special Characters
433 * ARM-Regs:: Register Names
434 * ARM-Relocations:: Relocations
435 * ARM-Neon-Alignment:: NEON Alignment Specifiers
438 @node ARM-Instruction-Set
439 @subsection Instruction Set Syntax
440 Two slightly different syntaxes are support for ARM and THUMB
441 instructions. The default, @code{divided}, uses the old style where
442 ARM and THUMB instructions had their own, separate syntaxes. The new,
443 @code{unified} syntax, which can be selected via the @code{.syntax}
444 directive, and has the following main features:
448 Immediate operands do not require a @code{#} prefix.
451 The @code{IT} instruction may appear, and if it does it is validated
452 against subsequent conditional affixes. In ARM mode it does not
453 generate machine code, in THUMB mode it does.
456 For ARM instructions the conditional affixes always appear at the end
457 of the instruction. For THUMB instructions conditional affixes can be
458 used, but only inside the scope of an @code{IT} instruction.
461 All of the instructions new to the V6T2 architecture (and later) are
462 available. (Only a few such instructions can be written in the
463 @code{divided} syntax).
466 The @code{.N} and @code{.W} suffixes are recognized and honored.
469 All instructions set the flags if and only if they have an @code{s}
474 @subsection Special Characters
476 @cindex line comment character, ARM
477 @cindex ARM line comment character
478 The presence of a @samp{@@} anywhere on a line indicates the start of
479 a comment that extends to the end of that line.
481 If a @samp{#} appears as the first character of a line then the whole
482 line is treated as a comment, but in this case the line could also be
483 a logical line number directive (@pxref{Comments}) or a preprocessor
484 control command (@pxref{Preprocessing}).
486 @cindex line separator, ARM
487 @cindex statement separator, ARM
488 @cindex ARM line separator
489 The @samp{;} character can be used instead of a newline to separate
492 @cindex immediate character, ARM
493 @cindex ARM immediate character
494 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
496 @cindex identifiers, ARM
497 @cindex ARM identifiers
498 *TODO* Explain about /data modifier on symbols.
501 @subsection Register Names
503 @cindex ARM register names
504 @cindex register names, ARM
505 *TODO* Explain about ARM register naming, and the predefined names.
507 @node ARM-Relocations
508 @subsection ARM relocation generation
510 @cindex data relocations, ARM
511 @cindex ARM data relocations
512 Specific data relocations can be generated by putting the relocation name
513 in parentheses after the symbol name. For example:
519 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
521 The following relocations are supported:
537 For compatibility with older toolchains the assembler also accepts
538 @code{(PLT)} after branch targets. On legacy targets this will
539 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
540 targets it will encode either the @samp{R_ARM_CALL} or
541 @samp{R_ARM_JUMP24} relocation, as appropriate.
543 @cindex MOVW and MOVT relocations, ARM
544 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
545 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
546 respectively. For example to load the 32-bit address of foo into r0:
549 MOVW r0, #:lower16:foo
550 MOVT r0, #:upper16:foo
553 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
554 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
555 generated by prefixing the value with @samp{#:lower0_7:#},
556 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
557 respectively. For example to load the 32-bit address of foo into r0:
560 MOVS r0, #:upper8_15:#foo
562 ADDS r0, #:upper0_7:#foo
564 ADDS r0, #:lower8_15:#foo
566 ADDS r0, #:lower0_7:#foo
569 @node ARM-Neon-Alignment
570 @subsection NEON Alignment Specifiers
572 @cindex alignment for NEON instructions
573 Some NEON load/store instructions allow an optional address
575 The ARM documentation specifies that this is indicated by
576 @samp{@@ @var{align}}. However GAS already interprets
577 the @samp{@@} character as a "line comment" start,
578 so @samp{: @var{align}} is used instead. For example:
581 vld1.8 @{q0@}, [r0, :128]
584 @node ARM Floating Point
585 @section Floating Point
587 @cindex floating point, ARM (@sc{ieee})
588 @cindex ARM floating point (@sc{ieee})
589 The ARM family uses @sc{ieee} floating-point numbers.
592 @section ARM Machine Directives
594 @cindex machine directives, ARM
595 @cindex ARM machine directives
598 @c AAAAAAAAAAAAAAAAAAAAAAAAA
601 @cindex @code{.2byte} directive, ARM
602 @cindex @code{.4byte} directive, ARM
603 @cindex @code{.8byte} directive, ARM
604 @item .2byte @var{expression} [, @var{expression}]*
605 @itemx .4byte @var{expression} [, @var{expression}]*
606 @itemx .8byte @var{expression} [, @var{expression}]*
607 These directives write 2, 4 or 8 byte values to the output section.
610 @cindex @code{.align} directive, ARM
611 @item .align @var{expression} [, @var{expression}]
612 This is the generic @var{.align} directive. For the ARM however if the
613 first argument is zero (ie no alignment is needed) the assembler will
614 behave as if the argument had been 2 (ie pad to the next four byte
615 boundary). This is for compatibility with ARM's own assembler.
617 @cindex @code{.arch} directive, ARM
618 @item .arch @var{name}
619 Select the target architecture. Valid values for @var{name} are the same as
620 for the @option{-march} commandline option.
622 Specifying @code{.arch} clears any previously selected architecture
625 @cindex @code{.arch_extension} directive, ARM
626 @item .arch_extension @var{name}
627 Add or remove an architecture extension to the target architecture. Valid
628 values for @var{name} are the same as those accepted as architectural
629 extensions by the @option{-mcpu} commandline option.
631 @code{.arch_extension} may be used multiple times to add or remove extensions
632 incrementally to the architecture being compiled for.
634 @cindex @code{.arm} directive, ARM
636 This performs the same action as @var{.code 32}.
638 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
640 @cindex @code{.bss} directive, ARM
642 This directive switches to the @code{.bss} section.
644 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
646 @cindex @code{.cantunwind} directive, ARM
648 Prevents unwinding through the current function. No personality routine
649 or exception table data is required or permitted.
651 @cindex @code{.code} directive, ARM
652 @item .code @code{[16|32]}
653 This directive selects the instruction set being generated. The value 16
654 selects Thumb, with the value 32 selecting ARM.
656 @cindex @code{.cpu} directive, ARM
657 @item .cpu @var{name}
658 Select the target processor. Valid values for @var{name} are the same as
659 for the @option{-mcpu} commandline option.
661 Specifying @code{.cpu} clears any previously selected architecture
664 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
666 @cindex @code{.dn} and @code{.qn} directives, ARM
667 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
668 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
670 The @code{dn} and @code{qn} directives are used to create typed
671 and/or indexed register aliases for use in Advanced SIMD Extension
672 (Neon) instructions. The former should be used to create aliases
673 of double-precision registers, and the latter to create aliases of
674 quad-precision registers.
676 If these directives are used to create typed aliases, those aliases can
677 be used in Neon instructions instead of writing types after the mnemonic
678 or after each operand. For example:
687 This is equivalent to writing the following:
693 Aliases created using @code{dn} or @code{qn} can be destroyed using
696 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
698 @cindex @code{.eabi_attribute} directive, ARM
699 @item .eabi_attribute @var{tag}, @var{value}
700 Set the EABI object attribute @var{tag} to @var{value}.
702 The @var{tag} is either an attribute number, or one of the following:
703 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
704 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
705 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
706 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
707 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
708 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
709 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
710 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
711 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
712 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
713 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
714 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
715 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
716 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
717 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
718 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
719 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
720 @code{Tag_conformance}, @code{Tag_T2EE_use},
721 @code{Tag_Virtualization_use}
723 The @var{value} is either a @code{number}, @code{"string"}, or
724 @code{number, "string"} depending on the tag.
726 Note - the following legacy values are also accepted by @var{tag}:
727 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
728 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
730 @cindex @code{.even} directive, ARM
732 This directive aligns to an even-numbered address.
734 @cindex @code{.extend} directive, ARM
735 @cindex @code{.ldouble} directive, ARM
736 @item .extend @var{expression} [, @var{expression}]*
737 @itemx .ldouble @var{expression} [, @var{expression}]*
738 These directives write 12byte long double floating-point values to the
739 output section. These are not compatible with current ARM processors
742 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
745 @cindex @code{.fnend} directive, ARM
747 Marks the end of a function with an unwind table entry. The unwind index
748 table entry is created when this directive is processed.
750 If no personality routine has been specified then standard personality
751 routine 0 or 1 will be used, depending on the number of unwind opcodes
755 @cindex @code{.fnstart} directive, ARM
757 Marks the start of a function with an unwind table entry.
759 @cindex @code{.force_thumb} directive, ARM
761 This directive forces the selection of Thumb instructions, even if the
762 target processor does not support those instructions
764 @cindex @code{.fpu} directive, ARM
765 @item .fpu @var{name}
766 Select the floating-point unit to assemble for. Valid values for @var{name}
767 are the same as for the @option{-mfpu} commandline option.
769 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
770 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
772 @cindex @code{.handlerdata} directive, ARM
774 Marks the end of the current function, and the start of the exception table
775 entry for that function. Anything between this directive and the
776 @code{.fnend} directive will be added to the exception table entry.
778 Must be preceded by a @code{.personality} or @code{.personalityindex}
781 @c IIIIIIIIIIIIIIIIIIIIIIIIII
783 @cindex @code{.inst} directive, ARM
784 @item .inst @var{opcode} [ , @dots{} ]
785 @itemx .inst.n @var{opcode} [ , @dots{} ]
786 @itemx .inst.w @var{opcode} [ , @dots{} ]
787 Generates the instruction corresponding to the numerical value @var{opcode}.
788 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
789 specified explicitly, overriding the normal encoding rules.
791 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
792 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
793 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
795 @item .ldouble @var{expression} [, @var{expression}]*
798 @cindex @code{.ltorg} directive, ARM
800 This directive causes the current contents of the literal pool to be
801 dumped into the current section (which is assumed to be the .text
802 section) at the current location (aligned to a word boundary).
803 @code{GAS} maintains a separate literal pool for each section and each
804 sub-section. The @code{.ltorg} directive will only affect the literal
805 pool of the current section and sub-section. At the end of assembly
806 all remaining, un-empty literal pools will automatically be dumped.
808 Note - older versions of @code{GAS} would dump the current literal
809 pool any time a section change occurred. This is no longer done, since
810 it prevents accurate control of the placement of literal pools.
812 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
814 @cindex @code{.movsp} directive, ARM
815 @item .movsp @var{reg} [, #@var{offset}]
816 Tell the unwinder that @var{reg} contains an offset from the current
817 stack pointer. If @var{offset} is not specified then it is assumed to be
820 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
821 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
823 @cindex @code{.object_arch} directive, ARM
824 @item .object_arch @var{name}
825 Override the architecture recorded in the EABI object attribute section.
826 Valid values for @var{name} are the same as for the @code{.arch} directive.
827 Typically this is useful when code uses runtime detection of CPU features.
829 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
831 @cindex @code{.packed} directive, ARM
832 @item .packed @var{expression} [, @var{expression}]*
833 This directive writes 12-byte packed floating-point values to the
834 output section. These are not compatible with current ARM processors
838 @cindex @code{.pad} directive, ARM
839 @item .pad #@var{count}
840 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
841 A positive value indicates the function prologue allocated stack space by
842 decrementing the stack pointer.
844 @cindex @code{.personality} directive, ARM
845 @item .personality @var{name}
846 Sets the personality routine for the current function to @var{name}.
848 @cindex @code{.personalityindex} directive, ARM
849 @item .personalityindex @var{index}
850 Sets the personality routine for the current function to the EABI standard
851 routine number @var{index}
853 @cindex @code{.pool} directive, ARM
855 This is a synonym for .ltorg.
857 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
858 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
860 @cindex @code{.req} directive, ARM
861 @item @var{name} .req @var{register name}
862 This creates an alias for @var{register name} called @var{name}. For
869 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
872 @cindex @code{.save} directive, ARM
873 @item .save @var{reglist}
874 Generate unwinder annotations to restore the registers in @var{reglist}.
875 The format of @var{reglist} is the same as the corresponding store-multiple
879 @exdent @emph{core registers}
880 .save @{r4, r5, r6, lr@}
881 stmfd sp!, @{r4, r5, r6, lr@}
882 @exdent @emph{FPA registers}
885 @exdent @emph{VFP registers}
886 .save @{d8, d9, d10@}
887 fstmdx sp!, @{d8, d9, d10@}
888 @exdent @emph{iWMMXt registers}
890 wstrd wr11, [sp, #-8]!
891 wstrd wr10, [sp, #-8]!
894 wstrd wr11, [sp, #-8]!
896 wstrd wr10, [sp, #-8]!
900 @cindex @code{.setfp} directive, ARM
901 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
902 Make all unwinder annotations relative to a frame pointer. Without this
903 the unwinder will use offsets from the stack pointer.
905 The syntax of this directive is the same as the @code{add} or @code{mov}
906 instruction used to set the frame pointer. @var{spreg} must be either
907 @code{sp} or mentioned in a previous @code{.movsp} directive.
917 @cindex @code{.secrel32} directive, ARM
918 @item .secrel32 @var{expression} [, @var{expression}]*
919 This directive emits relocations that evaluate to the section-relative
920 offset of each expression's symbol. This directive is only supported
923 @cindex @code{.syntax} directive, ARM
924 @item .syntax [@code{unified} | @code{divided}]
925 This directive sets the Instruction Set Syntax as described in the
926 @ref{ARM-Instruction-Set} section.
928 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
930 @cindex @code{.thumb} directive, ARM
932 This performs the same action as @var{.code 16}.
934 @cindex @code{.thumb_func} directive, ARM
936 This directive specifies that the following symbol is the name of a
937 Thumb encoded function. This information is necessary in order to allow
938 the assembler and linker to generate correct code for interworking
939 between Arm and Thumb instructions and should be used even if
940 interworking is not going to be performed. The presence of this
941 directive also implies @code{.thumb}
943 This directive is not necessary when generating EABI objects. On these
944 targets the encoding is implicit when generating Thumb code.
946 @cindex @code{.thumb_set} directive, ARM
948 This performs the equivalent of a @code{.set} directive in that it
949 creates a symbol which is an alias for another symbol (possibly not yet
950 defined). This directive also has the added property in that it marks
951 the aliased symbol as being a thumb function entry point, in the same
952 way that the @code{.thumb_func} directive does.
954 @cindex @code{.tlsdescseq} directive, ARM
955 @item .tlsdescseq @var{tls-variable}
956 This directive is used to annotate parts of an inlined TLS descriptor
957 trampoline. Normally the trampoline is provided by the linker, and
958 this directive is not needed.
960 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
962 @cindex @code{.unreq} directive, ARM
963 @item .unreq @var{alias-name}
964 This undefines a register alias which was previously defined using the
965 @code{req}, @code{dn} or @code{qn} directives. For example:
972 An error occurs if the name is undefined. Note - this pseudo op can
973 be used to delete builtin in register name aliases (eg 'r0'). This
974 should only be done if it is really necessary.
976 @cindex @code{.unwind_raw} directive, ARM
977 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
978 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
979 the stack pointer by @var{offset} bytes.
981 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
984 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
986 @cindex @code{.vsave} directive, ARM
987 @item .vsave @var{vfp-reglist}
988 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
989 using FLDMD. Also works for VFPv3 registers
990 that are to be restored using VLDM.
991 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
995 @exdent @emph{VFP registers}
996 .vsave @{d8, d9, d10@}
997 fstmdd sp!, @{d8, d9, d10@}
998 @exdent @emph{VFPv3 registers}
999 .vsave @{d15, d16, d17@}
1000 vstm sp!, @{d15, d16, d17@}
1003 Since FLDMX and FSTMX are now deprecated, this directive should be
1004 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1006 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1007 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1008 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1009 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1017 @cindex opcodes for ARM
1018 @code{@value{AS}} implements all the standard ARM opcodes. It also
1019 implements several pseudo opcodes, including several synthetic load
1024 @cindex @code{NOP} pseudo op, ARM
1030 This pseudo op will always evaluate to a legal ARM instruction that does
1031 nothing. Currently it will evaluate to MOV r0, r0.
1033 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1036 ldr <register> , = <expression>
1039 If expression evaluates to a numeric constant then a MOV or MVN
1040 instruction will be used in place of the LDR instruction, if the
1041 constant can be generated by either of these instructions. Otherwise
1042 the constant will be placed into the nearest literal pool (if it not
1043 already there) and a PC relative LDR instruction will be generated.
1045 @cindex @code{ADR reg,<label>} pseudo op, ARM
1048 adr <register> <label>
1051 This instruction will load the address of @var{label} into the indicated
1052 register. The instruction will evaluate to a PC relative ADD or SUB
1053 instruction depending upon where the label is located. If the label is
1054 out of range, or if it is not defined in the same file (and section) as
1055 the ADR instruction, then an error will be generated. This instruction
1056 will not make use of the literal pool.
1058 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1061 adrl <register> <label>
1064 This instruction will load the address of @var{label} into the indicated
1065 register. The instruction will evaluate to one or two PC relative ADD
1066 or SUB instructions depending upon where the label is located. If a
1067 second instruction is not needed a NOP instruction will be generated in
1068 its place, so that this instruction is always 8 bytes long.
1070 If the label is out of range, or if it is not defined in the same file
1071 (and section) as the ADRL instruction, then an error will be generated.
1072 This instruction will not make use of the literal pool.
1076 For information on the ARM or Thumb instruction sets, see @cite{ARM
1077 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1080 @node ARM Mapping Symbols
1081 @section Mapping Symbols
1083 The ARM ELF specification requires that special symbols be inserted
1084 into object files to mark certain features:
1090 At the start of a region of code containing ARM instructions.
1094 At the start of a region of code containing THUMB instructions.
1098 At the start of a region of data.
1102 The assembler will automatically insert these symbols for you - there
1103 is no need to code them yourself. Support for tagging symbols ($b,
1104 $f, $p and $m) which is also mentioned in the current ARM ELF
1105 specification is not implemented. This is because they have been
1106 dropped from the new EABI and so tools cannot rely upon their
1109 @node ARM Unwinding Tutorial
1112 The ABI for the ARM Architecture specifies a standard format for
1113 exception unwind information. This information is used when an
1114 exception is thrown to determine where control should be transferred.
1115 In particular, the unwind information is used to determine which
1116 function called the function that threw the exception, and which
1117 function called that one, and so forth. This information is also used
1118 to restore the values of callee-saved registers in the function
1119 catching the exception.
1121 If you are writing functions in assembly code, and those functions
1122 call other functions that throw exceptions, you must use assembly
1123 pseudo ops to ensure that appropriate exception unwind information is
1124 generated. Otherwise, if one of the functions called by your assembly
1125 code throws an exception, the run-time library will be unable to
1126 unwind the stack through your assembly code and your program will not
1129 To illustrate the use of these pseudo ops, we will examine the code
1130 that G++ generates for the following C++ input:
1133 void callee (int *);
1144 This example does not show how to throw or catch an exception from
1145 assembly code. That is a much more complex operation and should
1146 always be done in a high-level language, such as C++, that directly
1147 supports exceptions.
1149 The code generated by one particular version of G++ when compiling the
1156 @ Function supports interworking.
1157 @ args = 0, pretend = 0, frame = 8
1158 @ frame_needed = 1, uses_anonymous_args = 0
1180 Of course, the sequence of instructions varies based on the options
1181 you pass to GCC and on the version of GCC in use. The exact
1182 instructions are not important since we are focusing on the pseudo ops
1183 that are used to generate unwind information.
1185 An important assumption made by the unwinder is that the stack frame
1186 does not change during the body of the function. In particular, since
1187 we assume that the assembly code does not itself throw an exception,
1188 the only point where an exception can be thrown is from a call, such
1189 as the @code{bl} instruction above. At each call site, the same saved
1190 registers (including @code{lr}, which indicates the return address)
1191 must be located in the same locations relative to the frame pointer.
1193 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1194 op appears immediately before the first instruction of the function
1195 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1196 op appears immediately after the last instruction of the function.
1197 These pseudo ops specify the range of the function.
1199 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1200 @code{.pad}) matters; their exact locations are irrelevant. In the
1201 example above, the compiler emits the pseudo ops with particular
1202 instructions. That makes it easier to understand the code, but it is
1203 not required for correctness. It would work just as well to emit all
1204 of the pseudo ops other than @code{.fnend} in the same order, but
1205 immediately after @code{.fnstart}.
1207 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1208 indicates registers that have been saved to the stack so that they can
1209 be restored before the function returns. The argument to the
1210 @code{.save} pseudo op is a list of registers to save. If a register
1211 is ``callee-saved'' (as specified by the ABI) and is modified by the
1212 function you are writing, then your code must save the value before it
1213 is modified and restore the original value before the function
1214 returns. If an exception is thrown, the run-time library restores the
1215 values of these registers from their locations on the stack before
1216 returning control to the exception handler. (Of course, if an
1217 exception is not thrown, the function that contains the @code{.save}
1218 pseudo op restores these registers in the function epilogue, as is
1219 done with the @code{ldmfd} instruction above.)
1221 You do not have to save callee-saved registers at the very beginning
1222 of the function and you do not need to use the @code{.save} pseudo op
1223 immediately following the point at which the registers are saved.
1224 However, if you modify a callee-saved register, you must save it on
1225 the stack before modifying it and before calling any functions which
1226 might throw an exception. And, you must use the @code{.save} pseudo
1227 op to indicate that you have done so.
1229 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1230 modification of the stack pointer that does not save any registers.
1231 The argument is the number of bytes (in decimal) that are subtracted
1232 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1233 subtracting from the stack pointer increases the size of the stack.)
1235 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1236 indicates the register that contains the frame pointer. The first
1237 argument is the register that is set, which is typically @code{fp}.
1238 The second argument indicates the register from which the frame
1239 pointer takes its value. The third argument, if present, is the value
1240 (in decimal) added to the register specified by the second argument to
1241 compute the value of the frame pointer. You should not modify the
1242 frame pointer in the body of the function.
1244 If you do not use a frame pointer, then you should not use the
1245 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1246 should avoid modifying the stack pointer outside of the function
1247 prologue. Otherwise, the run-time library will be unable to find
1248 saved registers when it is unwinding the stack.
1250 The pseudo ops described above are sufficient for writing assembly
1251 code that calls functions which may throw exceptions. If you need to
1252 know more about the object-file format used to represent unwind
1253 information, you may consult the @cite{Exception Handling ABI for the
1254 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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