1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
136 @code{cortex-m0plus},
139 @code{marvell-whitney},
143 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
144 @code{i80200} (Intel XScale processor)
145 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
148 The special name @code{all} may be used to allow the
149 assembler to accept instructions valid for any ARM processor.
151 In addition to the basic instruction set, the assembler can be told to
152 accept various extension mnemonics that extend the processor using the
153 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
154 is equivalent to specifying @code{-mcpu=ep9312}.
156 Multiple extensions may be specified, separated by a @code{+}. The
157 extensions should be specified in ascending alphabetical order.
159 Some extensions may be restricted to particular architectures; this is
160 documented in the list of extensions below.
162 Extension mnemonics may also be removed from those the assembler accepts.
163 This is done be prepending @code{no} to the option that adds the extension.
164 Extensions that are removed should be listed after all extensions which have
165 been added, again in ascending alphabetical order. For example,
166 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
169 The following extensions are currently supported:
171 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
172 @code{fp} (Floating Point Extensions for v8-A architecture),
173 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
178 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
180 @code{os} (Operating System for v6M architecture),
181 @code{sec} (Security Extensions for v6K and v7-A architectures),
182 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
183 @code{virt} (Virtualization Extensions for v7-A architecture, implies
185 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
186 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
191 @cindex @code{-march=} command line option, ARM
192 @item -march=@var{architecture}[+@var{extension}@dots{}]
193 This option specifies the target architecture. The assembler will issue
194 an error message if an attempt is made to assemble an instruction which
195 will not execute on the target architecture. The following architecture
196 names are recognized:
232 If both @code{-mcpu} and
233 @code{-march} are specified, the assembler will use
234 the setting for @code{-mcpu}.
236 The architecture option can be extended with the same instruction set
237 extension options as the @code{-mcpu} option.
239 @cindex @code{-mfpu=} command line option, ARM
240 @item -mfpu=@var{floating-point-format}
242 This option specifies the floating point format to assemble for. The
243 assembler will issue an error message if an attempt is made to assemble
244 an instruction which will not execute on the target floating point unit.
245 The following format options are recognized:
265 @code{vfpv3-d16-fp16},
280 @code{neon-fp-armv8},
281 @code{crypto-neon-fp-armv8},
282 @code{neon-fp-armv8.1}
284 @code{crypto-neon-fp-armv8.1}.
286 In addition to determining which instructions are assembled, this option
287 also affects the way in which the @code{.double} assembler directive behaves
288 when assembling little-endian code.
290 The default is dependent on the processor selected. For Architecture 5 or
291 later, the default is to assembler for VFP instructions; for earlier
292 architectures the default is to assemble for FPA instructions.
294 @cindex @code{-mthumb} command line option, ARM
296 This option specifies that the assembler should start assembling Thumb
297 instructions; that is, it should behave as though the file starts with a
298 @code{.code 16} directive.
300 @cindex @code{-mthumb-interwork} command line option, ARM
301 @item -mthumb-interwork
302 This option specifies that the output generated by the assembler should
303 be marked as supporting interworking.
305 @cindex @code{-mimplicit-it} command line option, ARM
306 @item -mimplicit-it=never
307 @itemx -mimplicit-it=always
308 @itemx -mimplicit-it=arm
309 @itemx -mimplicit-it=thumb
310 The @code{-mimplicit-it} option controls the behavior of the assembler when
311 conditional instructions are not enclosed in IT blocks.
312 There are four possible behaviors.
313 If @code{never} is specified, such constructs cause a warning in ARM
314 code and an error in Thumb-2 code.
315 If @code{always} is specified, such constructs are accepted in both
316 ARM and Thumb-2 code, where the IT instruction is added implicitly.
317 If @code{arm} is specified, such constructs are accepted in ARM code
318 and cause an error in Thumb-2 code.
319 If @code{thumb} is specified, such constructs cause a warning in ARM
320 code and are accepted in Thumb-2 code. If you omit this option, the
321 behavior is equivalent to @code{-mimplicit-it=arm}.
323 @cindex @code{-mapcs-26} command line option, ARM
324 @cindex @code{-mapcs-32} command line option, ARM
327 These options specify that the output generated by the assembler should
328 be marked as supporting the indicated version of the Arm Procedure.
331 @cindex @code{-matpcs} command line option, ARM
333 This option specifies that the output generated by the assembler should
334 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
335 enabled this option will cause the assembler to create an empty
336 debugging section in the object file called .arm.atpcs. Debuggers can
337 use this to determine the ABI being used by.
339 @cindex @code{-mapcs-float} command line option, ARM
341 This indicates the floating point variant of the APCS should be
342 used. In this variant floating point arguments are passed in FP
343 registers rather than integer registers.
345 @cindex @code{-mapcs-reentrant} command line option, ARM
346 @item -mapcs-reentrant
347 This indicates that the reentrant variant of the APCS should be used.
348 This variant supports position independent code.
350 @cindex @code{-mfloat-abi=} command line option, ARM
351 @item -mfloat-abi=@var{abi}
352 This option specifies that the output generated by the assembler should be
353 marked as using specified floating point ABI.
354 The following values are recognized:
360 @cindex @code{-eabi=} command line option, ARM
361 @item -meabi=@var{ver}
362 This option specifies which EABI version the produced object files should
364 The following values are recognized:
370 @cindex @code{-EB} command line option, ARM
372 This option specifies that the output generated by the assembler should
373 be marked as being encoded for a big-endian processor.
375 Note: If a program is being built for a system with big-endian data
376 and little-endian instructions then it should be assembled with the
377 @option{-EB} option, (all of it, code and data) and then linked with
378 the @option{--be8} option. This will reverse the endianness of the
379 instructions back to little-endian, but leave the data as big-endian.
381 @cindex @code{-EL} command line option, ARM
383 This option specifies that the output generated by the assembler should
384 be marked as being encoded for a little-endian processor.
386 @cindex @code{-k} command line option, ARM
387 @cindex PIC code generation for ARM
389 This option specifies that the output of the assembler should be marked
390 as position-independent code (PIC).
392 @cindex @code{--fix-v4bx} command line option, ARM
394 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
395 the linker option of the same name.
397 @cindex @code{-mwarn-deprecated} command line option, ARM
398 @item -mwarn-deprecated
399 @itemx -mno-warn-deprecated
400 Enable or disable warnings about using deprecated options or
401 features. The default is to warn.
403 @cindex @code{-mccs} command line option, ARM
405 Turns on CodeComposer Studio assembly syntax compatibility mode.
407 @cindex @code{-mwarn-syms} command line option, ARM
409 @itemx -mno-warn-syms
410 Enable or disable warnings about symbols that match the names of ARM
411 instructions. The default is to warn.
419 * ARM-Instruction-Set:: Instruction Set
420 * ARM-Chars:: Special Characters
421 * ARM-Regs:: Register Names
422 * ARM-Relocations:: Relocations
423 * ARM-Neon-Alignment:: NEON Alignment Specifiers
426 @node ARM-Instruction-Set
427 @subsection Instruction Set Syntax
428 Two slightly different syntaxes are support for ARM and THUMB
429 instructions. The default, @code{divided}, uses the old style where
430 ARM and THUMB instructions had their own, separate syntaxes. The new,
431 @code{unified} syntax, which can be selected via the @code{.syntax}
432 directive, and has the following main features:
436 Immediate operands do not require a @code{#} prefix.
439 The @code{IT} instruction may appear, and if it does it is validated
440 against subsequent conditional affixes. In ARM mode it does not
441 generate machine code, in THUMB mode it does.
444 For ARM instructions the conditional affixes always appear at the end
445 of the instruction. For THUMB instructions conditional affixes can be
446 used, but only inside the scope of an @code{IT} instruction.
449 All of the instructions new to the V6T2 architecture (and later) are
450 available. (Only a few such instructions can be written in the
451 @code{divided} syntax).
454 The @code{.N} and @code{.W} suffixes are recognized and honored.
457 All instructions set the flags if and only if they have an @code{s}
462 @subsection Special Characters
464 @cindex line comment character, ARM
465 @cindex ARM line comment character
466 The presence of a @samp{@@} anywhere on a line indicates the start of
467 a comment that extends to the end of that line.
469 If a @samp{#} appears as the first character of a line then the whole
470 line is treated as a comment, but in this case the line could also be
471 a logical line number directive (@pxref{Comments}) or a preprocessor
472 control command (@pxref{Preprocessing}).
474 @cindex line separator, ARM
475 @cindex statement separator, ARM
476 @cindex ARM line separator
477 The @samp{;} character can be used instead of a newline to separate
480 @cindex immediate character, ARM
481 @cindex ARM immediate character
482 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
484 @cindex identifiers, ARM
485 @cindex ARM identifiers
486 *TODO* Explain about /data modifier on symbols.
489 @subsection Register Names
491 @cindex ARM register names
492 @cindex register names, ARM
493 *TODO* Explain about ARM register naming, and the predefined names.
495 @node ARM-Relocations
496 @subsection ARM relocation generation
498 @cindex data relocations, ARM
499 @cindex ARM data relocations
500 Specific data relocations can be generated by putting the relocation name
501 in parentheses after the symbol name. For example:
507 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
509 The following relocations are supported:
525 For compatibility with older toolchains the assembler also accepts
526 @code{(PLT)} after branch targets. On legacy targets this will
527 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
528 targets it will encode either the @samp{R_ARM_CALL} or
529 @samp{R_ARM_JUMP24} relocation, as appropriate.
531 @cindex MOVW and MOVT relocations, ARM
532 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
533 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
534 respectively. For example to load the 32-bit address of foo into r0:
537 MOVW r0, #:lower16:foo
538 MOVT r0, #:upper16:foo
541 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
542 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
543 generated by prefixing the value with @samp{#:lower0_7:#},
544 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
545 respectively. For example to load the 32-bit address of foo into r0:
548 MOVS r0, #:upper8_15:#foo
550 ADDS r0, #:upper0_7:#foo
552 ADDS r0, #:lower8_15:#foo
554 ADDS r0, #:lower0_7:#foo
557 @node ARM-Neon-Alignment
558 @subsection NEON Alignment Specifiers
560 @cindex alignment for NEON instructions
561 Some NEON load/store instructions allow an optional address
563 The ARM documentation specifies that this is indicated by
564 @samp{@@ @var{align}}. However GAS already interprets
565 the @samp{@@} character as a "line comment" start,
566 so @samp{: @var{align}} is used instead. For example:
569 vld1.8 @{q0@}, [r0, :128]
572 @node ARM Floating Point
573 @section Floating Point
575 @cindex floating point, ARM (@sc{ieee})
576 @cindex ARM floating point (@sc{ieee})
577 The ARM family uses @sc{ieee} floating-point numbers.
580 @section ARM Machine Directives
582 @cindex machine directives, ARM
583 @cindex ARM machine directives
586 @c AAAAAAAAAAAAAAAAAAAAAAAAA
588 @cindex @code{.2byte} directive, ARM
589 @cindex @code{.4byte} directive, ARM
590 @cindex @code{.8byte} directive, ARM
591 @item .2byte @var{expression} [, @var{expression}]*
592 @itemx .4byte @var{expression} [, @var{expression}]*
593 @itemx .8byte @var{expression} [, @var{expression}]*
594 These directives write 2, 4 or 8 byte values to the output section.
596 @cindex @code{.align} directive, ARM
597 @item .align @var{expression} [, @var{expression}]
598 This is the generic @var{.align} directive. For the ARM however if the
599 first argument is zero (ie no alignment is needed) the assembler will
600 behave as if the argument had been 2 (ie pad to the next four byte
601 boundary). This is for compatibility with ARM's own assembler.
603 @cindex @code{.arch} directive, ARM
604 @item .arch @var{name}
605 Select the target architecture. Valid values for @var{name} are the same as
606 for the @option{-march} commandline option.
608 Specifying @code{.arch} clears any previously selected architecture
611 @cindex @code{.arch_extension} directive, ARM
612 @item .arch_extension @var{name}
613 Add or remove an architecture extension to the target architecture. Valid
614 values for @var{name} are the same as those accepted as architectural
615 extensions by the @option{-mcpu} commandline option.
617 @code{.arch_extension} may be used multiple times to add or remove extensions
618 incrementally to the architecture being compiled for.
620 @cindex @code{.arm} directive, ARM
622 This performs the same action as @var{.code 32}.
624 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
626 @cindex @code{.bss} directive, ARM
628 This directive switches to the @code{.bss} section.
630 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
632 @cindex @code{.cantunwind} directive, ARM
634 Prevents unwinding through the current function. No personality routine
635 or exception table data is required or permitted.
637 @cindex @code{.code} directive, ARM
638 @item .code @code{[16|32]}
639 This directive selects the instruction set being generated. The value 16
640 selects Thumb, with the value 32 selecting ARM.
642 @cindex @code{.cpu} directive, ARM
643 @item .cpu @var{name}
644 Select the target processor. Valid values for @var{name} are the same as
645 for the @option{-mcpu} commandline option.
647 Specifying @code{.cpu} clears any previously selected architecture
650 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
652 @cindex @code{.dn} and @code{.qn} directives, ARM
653 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
654 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
656 The @code{dn} and @code{qn} directives are used to create typed
657 and/or indexed register aliases for use in Advanced SIMD Extension
658 (Neon) instructions. The former should be used to create aliases
659 of double-precision registers, and the latter to create aliases of
660 quad-precision registers.
662 If these directives are used to create typed aliases, those aliases can
663 be used in Neon instructions instead of writing types after the mnemonic
664 or after each operand. For example:
673 This is equivalent to writing the following:
679 Aliases created using @code{dn} or @code{qn} can be destroyed using
682 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
684 @cindex @code{.eabi_attribute} directive, ARM
685 @item .eabi_attribute @var{tag}, @var{value}
686 Set the EABI object attribute @var{tag} to @var{value}.
688 The @var{tag} is either an attribute number, or one of the following:
689 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
690 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
691 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
692 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
693 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
694 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
695 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
696 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
697 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
698 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
699 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
700 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
701 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
702 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
703 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
704 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
705 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
706 @code{Tag_conformance}, @code{Tag_T2EE_use},
707 @code{Tag_Virtualization_use}
709 The @var{value} is either a @code{number}, @code{"string"}, or
710 @code{number, "string"} depending on the tag.
712 Note - the following legacy values are also accepted by @var{tag}:
713 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
714 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
716 @cindex @code{.even} directive, ARM
718 This directive aligns to an even-numbered address.
720 @cindex @code{.extend} directive, ARM
721 @cindex @code{.ldouble} directive, ARM
722 @item .extend @var{expression} [, @var{expression}]*
723 @itemx .ldouble @var{expression} [, @var{expression}]*
724 These directives write 12byte long double floating-point values to the
725 output section. These are not compatible with current ARM processors
728 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
731 @cindex @code{.fnend} directive, ARM
733 Marks the end of a function with an unwind table entry. The unwind index
734 table entry is created when this directive is processed.
736 If no personality routine has been specified then standard personality
737 routine 0 or 1 will be used, depending on the number of unwind opcodes
741 @cindex @code{.fnstart} directive, ARM
743 Marks the start of a function with an unwind table entry.
745 @cindex @code{.force_thumb} directive, ARM
747 This directive forces the selection of Thumb instructions, even if the
748 target processor does not support those instructions
750 @cindex @code{.fpu} directive, ARM
751 @item .fpu @var{name}
752 Select the floating-point unit to assemble for. Valid values for @var{name}
753 are the same as for the @option{-mfpu} commandline option.
755 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
756 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
758 @cindex @code{.handlerdata} directive, ARM
760 Marks the end of the current function, and the start of the exception table
761 entry for that function. Anything between this directive and the
762 @code{.fnend} directive will be added to the exception table entry.
764 Must be preceded by a @code{.personality} or @code{.personalityindex}
767 @c IIIIIIIIIIIIIIIIIIIIIIIIII
769 @cindex @code{.inst} directive, ARM
770 @item .inst @var{opcode} [ , @dots{} ]
771 @itemx .inst.n @var{opcode} [ , @dots{} ]
772 @itemx .inst.w @var{opcode} [ , @dots{} ]
773 Generates the instruction corresponding to the numerical value @var{opcode}.
774 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
775 specified explicitly, overriding the normal encoding rules.
777 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
778 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
779 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
781 @item .ldouble @var{expression} [, @var{expression}]*
784 @cindex @code{.ltorg} directive, ARM
786 This directive causes the current contents of the literal pool to be
787 dumped into the current section (which is assumed to be the .text
788 section) at the current location (aligned to a word boundary).
789 @code{GAS} maintains a separate literal pool for each section and each
790 sub-section. The @code{.ltorg} directive will only affect the literal
791 pool of the current section and sub-section. At the end of assembly
792 all remaining, un-empty literal pools will automatically be dumped.
794 Note - older versions of @code{GAS} would dump the current literal
795 pool any time a section change occurred. This is no longer done, since
796 it prevents accurate control of the placement of literal pools.
798 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
800 @cindex @code{.movsp} directive, ARM
801 @item .movsp @var{reg} [, #@var{offset}]
802 Tell the unwinder that @var{reg} contains an offset from the current
803 stack pointer. If @var{offset} is not specified then it is assumed to be
806 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
807 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
809 @cindex @code{.object_arch} directive, ARM
810 @item .object_arch @var{name}
811 Override the architecture recorded in the EABI object attribute section.
812 Valid values for @var{name} are the same as for the @code{.arch} directive.
813 Typically this is useful when code uses runtime detection of CPU features.
815 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
817 @cindex @code{.packed} directive, ARM
818 @item .packed @var{expression} [, @var{expression}]*
819 This directive writes 12-byte packed floating-point values to the
820 output section. These are not compatible with current ARM processors
824 @cindex @code{.pad} directive, ARM
825 @item .pad #@var{count}
826 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
827 A positive value indicates the function prologue allocated stack space by
828 decrementing the stack pointer.
830 @cindex @code{.personality} directive, ARM
831 @item .personality @var{name}
832 Sets the personality routine for the current function to @var{name}.
834 @cindex @code{.personalityindex} directive, ARM
835 @item .personalityindex @var{index}
836 Sets the personality routine for the current function to the EABI standard
837 routine number @var{index}
839 @cindex @code{.pool} directive, ARM
841 This is a synonym for .ltorg.
843 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
844 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
846 @cindex @code{.req} directive, ARM
847 @item @var{name} .req @var{register name}
848 This creates an alias for @var{register name} called @var{name}. For
855 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
858 @cindex @code{.save} directive, ARM
859 @item .save @var{reglist}
860 Generate unwinder annotations to restore the registers in @var{reglist}.
861 The format of @var{reglist} is the same as the corresponding store-multiple
865 @exdent @emph{core registers}
866 .save @{r4, r5, r6, lr@}
867 stmfd sp!, @{r4, r5, r6, lr@}
868 @exdent @emph{FPA registers}
871 @exdent @emph{VFP registers}
872 .save @{d8, d9, d10@}
873 fstmdx sp!, @{d8, d9, d10@}
874 @exdent @emph{iWMMXt registers}
876 wstrd wr11, [sp, #-8]!
877 wstrd wr10, [sp, #-8]!
880 wstrd wr11, [sp, #-8]!
882 wstrd wr10, [sp, #-8]!
886 @cindex @code{.setfp} directive, ARM
887 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
888 Make all unwinder annotations relative to a frame pointer. Without this
889 the unwinder will use offsets from the stack pointer.
891 The syntax of this directive is the same as the @code{add} or @code{mov}
892 instruction used to set the frame pointer. @var{spreg} must be either
893 @code{sp} or mentioned in a previous @code{.movsp} directive.
903 @cindex @code{.secrel32} directive, ARM
904 @item .secrel32 @var{expression} [, @var{expression}]*
905 This directive emits relocations that evaluate to the section-relative
906 offset of each expression's symbol. This directive is only supported
909 @cindex @code{.syntax} directive, ARM
910 @item .syntax [@code{unified} | @code{divided}]
911 This directive sets the Instruction Set Syntax as described in the
912 @ref{ARM-Instruction-Set} section.
914 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
916 @cindex @code{.thumb} directive, ARM
918 This performs the same action as @var{.code 16}.
920 @cindex @code{.thumb_func} directive, ARM
922 This directive specifies that the following symbol is the name of a
923 Thumb encoded function. This information is necessary in order to allow
924 the assembler and linker to generate correct code for interworking
925 between Arm and Thumb instructions and should be used even if
926 interworking is not going to be performed. The presence of this
927 directive also implies @code{.thumb}
929 This directive is not neccessary when generating EABI objects. On these
930 targets the encoding is implicit when generating Thumb code.
932 @cindex @code{.thumb_set} directive, ARM
934 This performs the equivalent of a @code{.set} directive in that it
935 creates a symbol which is an alias for another symbol (possibly not yet
936 defined). This directive also has the added property in that it marks
937 the aliased symbol as being a thumb function entry point, in the same
938 way that the @code{.thumb_func} directive does.
940 @cindex @code{.tlsdescseq} directive, ARM
941 @item .tlsdescseq @var{tls-variable}
942 This directive is used to annotate parts of an inlined TLS descriptor
943 trampoline. Normally the trampoline is provided by the linker, and
944 this directive is not needed.
946 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
948 @cindex @code{.unreq} directive, ARM
949 @item .unreq @var{alias-name}
950 This undefines a register alias which was previously defined using the
951 @code{req}, @code{dn} or @code{qn} directives. For example:
958 An error occurs if the name is undefined. Note - this pseudo op can
959 be used to delete builtin in register name aliases (eg 'r0'). This
960 should only be done if it is really necessary.
962 @cindex @code{.unwind_raw} directive, ARM
963 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
964 Insert one of more arbitary unwind opcode bytes, which are known to adjust
965 the stack pointer by @var{offset} bytes.
967 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
970 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
972 @cindex @code{.vsave} directive, ARM
973 @item .vsave @var{vfp-reglist}
974 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
975 using FLDMD. Also works for VFPv3 registers
976 that are to be restored using VLDM.
977 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
981 @exdent @emph{VFP registers}
982 .vsave @{d8, d9, d10@}
983 fstmdd sp!, @{d8, d9, d10@}
984 @exdent @emph{VFPv3 registers}
985 .vsave @{d15, d16, d17@}
986 vstm sp!, @{d15, d16, d17@}
989 Since FLDMX and FSTMX are now deprecated, this directive should be
990 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
992 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
993 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
994 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
995 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1003 @cindex opcodes for ARM
1004 @code{@value{AS}} implements all the standard ARM opcodes. It also
1005 implements several pseudo opcodes, including several synthetic load
1010 @cindex @code{NOP} pseudo op, ARM
1016 This pseudo op will always evaluate to a legal ARM instruction that does
1017 nothing. Currently it will evaluate to MOV r0, r0.
1019 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1022 ldr <register> , = <expression>
1025 If expression evaluates to a numeric constant then a MOV or MVN
1026 instruction will be used in place of the LDR instruction, if the
1027 constant can be generated by either of these instructions. Otherwise
1028 the constant will be placed into the nearest literal pool (if it not
1029 already there) and a PC relative LDR instruction will be generated.
1031 @cindex @code{ADR reg,<label>} pseudo op, ARM
1034 adr <register> <label>
1037 This instruction will load the address of @var{label} into the indicated
1038 register. The instruction will evaluate to a PC relative ADD or SUB
1039 instruction depending upon where the label is located. If the label is
1040 out of range, or if it is not defined in the same file (and section) as
1041 the ADR instruction, then an error will be generated. This instruction
1042 will not make use of the literal pool.
1044 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1047 adrl <register> <label>
1050 This instruction will load the address of @var{label} into the indicated
1051 register. The instruction will evaluate to one or two PC relative ADD
1052 or SUB instructions depending upon where the label is located. If a
1053 second instruction is not needed a NOP instruction will be generated in
1054 its place, so that this instruction is always 8 bytes long.
1056 If the label is out of range, or if it is not defined in the same file
1057 (and section) as the ADRL instruction, then an error will be generated.
1058 This instruction will not make use of the literal pool.
1062 For information on the ARM or Thumb instruction sets, see @cite{ARM
1063 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1066 @node ARM Mapping Symbols
1067 @section Mapping Symbols
1069 The ARM ELF specification requires that special symbols be inserted
1070 into object files to mark certain features:
1076 At the start of a region of code containing ARM instructions.
1080 At the start of a region of code containing THUMB instructions.
1084 At the start of a region of data.
1088 The assembler will automatically insert these symbols for you - there
1089 is no need to code them yourself. Support for tagging symbols ($b,
1090 $f, $p and $m) which is also mentioned in the current ARM ELF
1091 specification is not implemented. This is because they have been
1092 dropped from the new EABI and so tools cannot rely upon their
1095 @node ARM Unwinding Tutorial
1098 The ABI for the ARM Architecture specifies a standard format for
1099 exception unwind information. This information is used when an
1100 exception is thrown to determine where control should be transferred.
1101 In particular, the unwind information is used to determine which
1102 function called the function that threw the exception, and which
1103 function called that one, and so forth. This information is also used
1104 to restore the values of callee-saved registers in the function
1105 catching the exception.
1107 If you are writing functions in assembly code, and those functions
1108 call other functions that throw exceptions, you must use assembly
1109 pseudo ops to ensure that appropriate exception unwind information is
1110 generated. Otherwise, if one of the functions called by your assembly
1111 code throws an exception, the run-time library will be unable to
1112 unwind the stack through your assembly code and your program will not
1115 To illustrate the use of these pseudo ops, we will examine the code
1116 that G++ generates for the following C++ input:
1119 void callee (int *);
1130 This example does not show how to throw or catch an exception from
1131 assembly code. That is a much more complex operation and should
1132 always be done in a high-level language, such as C++, that directly
1133 supports exceptions.
1135 The code generated by one particular version of G++ when compiling the
1142 @ Function supports interworking.
1143 @ args = 0, pretend = 0, frame = 8
1144 @ frame_needed = 1, uses_anonymous_args = 0
1166 Of course, the sequence of instructions varies based on the options
1167 you pass to GCC and on the version of GCC in use. The exact
1168 instructions are not important since we are focusing on the pseudo ops
1169 that are used to generate unwind information.
1171 An important assumption made by the unwinder is that the stack frame
1172 does not change during the body of the function. In particular, since
1173 we assume that the assembly code does not itself throw an exception,
1174 the only point where an exception can be thrown is from a call, such
1175 as the @code{bl} instruction above. At each call site, the same saved
1176 registers (including @code{lr}, which indicates the return address)
1177 must be located in the same locations relative to the frame pointer.
1179 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1180 op appears immediately before the first instruction of the function
1181 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1182 op appears immediately after the last instruction of the function.
1183 These pseudo ops specify the range of the function.
1185 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1186 @code{.pad}) matters; their exact locations are irrelevant. In the
1187 example above, the compiler emits the pseudo ops with particular
1188 instructions. That makes it easier to understand the code, but it is
1189 not required for correctness. It would work just as well to emit all
1190 of the pseudo ops other than @code{.fnend} in the same order, but
1191 immediately after @code{.fnstart}.
1193 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1194 indicates registers that have been saved to the stack so that they can
1195 be restored before the function returns. The argument to the
1196 @code{.save} pseudo op is a list of registers to save. If a register
1197 is ``callee-saved'' (as specified by the ABI) and is modified by the
1198 function you are writing, then your code must save the value before it
1199 is modified and restore the original value before the function
1200 returns. If an exception is thrown, the run-time library restores the
1201 values of these registers from their locations on the stack before
1202 returning control to the exception handler. (Of course, if an
1203 exception is not thrown, the function that contains the @code{.save}
1204 pseudo op restores these registers in the function epilogue, as is
1205 done with the @code{ldmfd} instruction above.)
1207 You do not have to save callee-saved registers at the very beginning
1208 of the function and you do not need to use the @code{.save} pseudo op
1209 immediately following the point at which the registers are saved.
1210 However, if you modify a callee-saved register, you must save it on
1211 the stack before modifying it and before calling any functions which
1212 might throw an exception. And, you must use the @code{.save} pseudo
1213 op to indicate that you have done so.
1215 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1216 modification of the stack pointer that does not save any registers.
1217 The argument is the number of bytes (in decimal) that are subtracted
1218 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1219 subtracting from the stack pointer increases the size of the stack.)
1221 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1222 indicates the register that contains the frame pointer. The first
1223 argument is the register that is set, which is typically @code{fp}.
1224 The second argument indicates the register from which the frame
1225 pointer takes its value. The third argument, if present, is the value
1226 (in decimal) added to the register specified by the second argument to
1227 compute the value of the frame pointer. You should not modify the
1228 frame pointer in the body of the function.
1230 If you do not use a frame pointer, then you should not use the
1231 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1232 should avoid modifying the stack pointer outside of the function
1233 prologue. Otherwise, the run-time library will be unable to find
1234 saved registers when it is unwinding the stack.
1236 The pseudo ops described above are sufficient for writing assembly
1237 code that calls functions which may throw exceptions. If you need to
1238 know more about the object-file format used to represent unwind
1239 information, you may consult the @cite{Exception Handling ABI for the
1240 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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