1 @c Copyright (C) 1991-2023 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-ISA:: AMD64 ISA vs. Intel64 ISA
41 * i386-Bugs:: AT&T Syntax bugs
48 @cindex options for i386
49 @cindex options for x86-64
51 @cindex x86-64 options
53 The i386 version of @code{@value{AS}} has a few machine
58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
64 @item --32 | --x32 | --64
65 Select the word size, either 32 bits or 64 bits. @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
67 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
70 These options are only available with the ELF object file format, and
71 require that the necessary BFD support has been included (on a 32-bit
72 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
73 usage and use x86-64 as target platform).
76 By default, x86 GAS replaces multiple nop instructions used for
77 alignment within code sections with multi-byte nop instructions such
78 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
79 byte nop (0x90) is explicitly specified as the fill byte for alignment.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics. For example,
135 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
136 @var{vmx}. The following extensions are currently supported:
187 @code{avx512_4fmaps},
188 @code{avx512_4vnniw},
189 @code{avx512_vpopcntdq},
192 @code{avx512_bitalg},
193 @code{avx512_vp2intersect},
200 @code{avx_vnni_int8},
204 @code{avx_ne_convert},
258 Note that these extension mnemonics can be prefixed with @code{no} to revoke
259 the respective (and any dependent) functionality.
261 When the @code{.arch} directive is used with @option{-march}, the
262 @code{.arch} directive will take precedent.
264 @cindex @samp{-mtune=} option, i386
265 @cindex @samp{-mtune=} option, x86-64
266 @item -mtune=@var{CPU}
267 This option specifies a processor to optimize for. When used in
268 conjunction with the @option{-march} option, only instructions
269 of the processor specified by the @option{-march} option will be
272 Valid @var{CPU} values are identical to the processor list of
273 @option{-march=@var{CPU}}.
275 @cindex @samp{-msse2avx} option, i386
276 @cindex @samp{-msse2avx} option, x86-64
278 This option specifies that the assembler should encode SSE instructions
281 @cindex @samp{-muse-unaligned-vector-move} option, i386
282 @cindex @samp{-muse-unaligned-vector-move} option, x86-64
283 @item -muse-unaligned-vector-move
284 This option specifies that the assembler should encode aligned vector
285 move as unaligned vector move.
287 @cindex @samp{-msse-check=} option, i386
288 @cindex @samp{-msse-check=} option, x86-64
289 @item -msse-check=@var{none}
290 @itemx -msse-check=@var{warning}
291 @itemx -msse-check=@var{error}
292 These options control if the assembler should check SSE instructions.
293 @option{-msse-check=@var{none}} will make the assembler not to check SSE
294 instructions, which is the default. @option{-msse-check=@var{warning}}
295 will make the assembler issue a warning for any SSE instruction.
296 @option{-msse-check=@var{error}} will make the assembler issue an error
297 for any SSE instruction.
299 @cindex @samp{-mavxscalar=} option, i386
300 @cindex @samp{-mavxscalar=} option, x86-64
301 @item -mavxscalar=@var{128}
302 @itemx -mavxscalar=@var{256}
303 These options control how the assembler should encode scalar AVX
304 instructions. @option{-mavxscalar=@var{128}} will encode scalar
305 AVX instructions with 128bit vector length, which is the default.
306 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
307 with 256bit vector length.
309 WARNING: Don't use this for production code - due to CPU errata the
310 resulting code may not work on certain models.
312 @cindex @samp{-mvexwig=} option, i386
313 @cindex @samp{-mvexwig=} option, x86-64
314 @item -mvexwig=@var{0}
315 @itemx -mvexwig=@var{1}
316 These options control how the assembler should encode VEX.W-ignored (WIG)
317 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
318 instructions with vex.w = 0, which is the default.
319 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
322 WARNING: Don't use this for production code - due to CPU errata the
323 resulting code may not work on certain models.
325 @cindex @samp{-mevexlig=} option, i386
326 @cindex @samp{-mevexlig=} option, x86-64
327 @item -mevexlig=@var{128}
328 @itemx -mevexlig=@var{256}
329 @itemx -mevexlig=@var{512}
330 These options control how the assembler should encode length-ignored
331 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
332 EVEX instructions with 128bit vector length, which is the default.
333 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
334 encode LIG EVEX instructions with 256bit and 512bit vector length,
337 @cindex @samp{-mevexwig=} option, i386
338 @cindex @samp{-mevexwig=} option, x86-64
339 @item -mevexwig=@var{0}
340 @itemx -mevexwig=@var{1}
341 These options control how the assembler should encode w-ignored (WIG)
342 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
343 EVEX instructions with evex.w = 0, which is the default.
344 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
347 @cindex @samp{-mmnemonic=} option, i386
348 @cindex @samp{-mmnemonic=} option, x86-64
349 @item -mmnemonic=@var{att}
350 @itemx -mmnemonic=@var{intel}
351 This option specifies instruction mnemonic for matching instructions.
352 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
355 @cindex @samp{-msyntax=} option, i386
356 @cindex @samp{-msyntax=} option, x86-64
357 @item -msyntax=@var{att}
358 @itemx -msyntax=@var{intel}
359 This option specifies instruction syntax when processing instructions.
360 The @code{.att_syntax} and @code{.intel_syntax} directives will
363 @cindex @samp{-mnaked-reg} option, i386
364 @cindex @samp{-mnaked-reg} option, x86-64
366 This option specifies that registers don't require a @samp{%} prefix.
367 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
369 @cindex @samp{-madd-bnd-prefix} option, i386
370 @cindex @samp{-madd-bnd-prefix} option, x86-64
371 @item -madd-bnd-prefix
372 This option forces the assembler to add BND prefix to all branches, even
373 if such prefix was not explicitly specified in the source code.
375 @cindex @samp{-mshared} option, i386
376 @cindex @samp{-mshared} option, x86-64
378 On ELF target, the assembler normally optimizes out non-PLT relocations
379 against defined non-weak global branch targets with default visibility.
380 The @samp{-mshared} option tells the assembler to generate code which
381 may go into a shared library where all non-weak global branch targets
382 with default visibility can be preempted. The resulting code is
383 slightly bigger. This option only affects the handling of branch
386 @cindex @samp{-mbig-obj} option, i386
387 @cindex @samp{-mbig-obj} option, x86-64
389 On PE/COFF target this option forces the use of big object file
390 format, which allows more than 32768 sections.
392 @cindex @samp{-momit-lock-prefix=} option, i386
393 @cindex @samp{-momit-lock-prefix=} option, x86-64
394 @item -momit-lock-prefix=@var{no}
395 @itemx -momit-lock-prefix=@var{yes}
396 These options control how the assembler should encode lock prefix.
397 This option is intended as a workaround for processors, that fail on
398 lock prefix. This option can only be safely used with single-core,
399 single-thread computers
400 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
401 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
402 which is the default.
404 @cindex @samp{-mfence-as-lock-add=} option, i386
405 @cindex @samp{-mfence-as-lock-add=} option, x86-64
406 @item -mfence-as-lock-add=@var{no}
407 @itemx -mfence-as-lock-add=@var{yes}
408 These options control how the assembler should encode lfence, mfence and
410 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
411 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
412 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
413 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
414 sfence as usual, which is the default.
416 @cindex @samp{-mrelax-relocations=} option, i386
417 @cindex @samp{-mrelax-relocations=} option, x86-64
418 @item -mrelax-relocations=@var{no}
419 @itemx -mrelax-relocations=@var{yes}
420 These options control whether the assembler should generate relax
421 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
422 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
423 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
424 @option{-mrelax-relocations=@var{no}} will not generate relax
425 relocations. The default can be controlled by a configure option
426 @option{--enable-x86-relax-relocations}.
428 @cindex @samp{-malign-branch-boundary=} option, i386
429 @cindex @samp{-malign-branch-boundary=} option, x86-64
430 @item -malign-branch-boundary=@var{NUM}
431 This option controls how the assembler should align branches with segment
432 prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or
433 no less than 16. Branches will be aligned within @var{NUM} byte
434 boundary. @option{-malign-branch-boundary=0}, which is the default,
435 doesn't align branches.
437 @cindex @samp{-malign-branch=} option, i386
438 @cindex @samp{-malign-branch=} option, x86-64
439 @item -malign-branch=@var{TYPE}[+@var{TYPE}...]
440 This option specifies types of branches to align. @var{TYPE} is
441 combination of @samp{jcc}, which aligns conditional jumps,
442 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
443 which aligns unconditional jumps, @samp{call} which aligns calls,
444 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
445 jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}.
447 @cindex @samp{-malign-branch-prefix-size=} option, i386
448 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
449 @item -malign-branch-prefix-size=@var{NUM}
450 This option specifies the maximum number of prefixes on an instruction
451 to align branches. @var{NUM} should be between 0 and 5. The default
454 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
455 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
456 @item -mbranches-within-32B-boundaries
457 This option aligns conditional jumps, fused conditional jumps and
458 unconditional jumps within 32 byte boundary with up to 5 segment prefixes
459 on an instruction. It is equivalent to
460 @option{-malign-branch-boundary=32}
461 @option{-malign-branch=jcc+fused+jmp}
462 @option{-malign-branch-prefix-size=5}.
463 The default doesn't align branches.
465 @cindex @samp{-mlfence-after-load=} option, i386
466 @cindex @samp{-mlfence-after-load=} option, x86-64
467 @item -mlfence-after-load=@var{no}
468 @itemx -mlfence-after-load=@var{yes}
469 These options control whether the assembler should generate lfence
470 after load instructions. @option{-mlfence-after-load=@var{yes}} will
471 generate lfence. @option{-mlfence-after-load=@var{no}} will not generate
472 lfence, which is the default.
474 @cindex @samp{-mlfence-before-indirect-branch=} option, i386
475 @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
476 @item -mlfence-before-indirect-branch=@var{none}
477 @item -mlfence-before-indirect-branch=@var{all}
478 @item -mlfence-before-indirect-branch=@var{register}
479 @itemx -mlfence-before-indirect-branch=@var{memory}
480 These options control whether the assembler should generate lfence
481 before indirect near branch instructions.
482 @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
483 before indirect near branch via register and issue a warning before
484 indirect near branch via memory.
485 It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when
486 there's no explicit @option{-mlfence-before-ret=}.
487 @option{-mlfence-before-indirect-branch=@var{register}} will generate
488 lfence before indirect near branch via register.
489 @option{-mlfence-before-indirect-branch=@var{memory}} will issue a
490 warning before indirect near branch via memory.
491 @option{-mlfence-before-indirect-branch=@var{none}} will not generate
492 lfence nor issue warning, which is the default. Note that lfence won't
493 be generated before indirect near branch via register with
494 @option{-mlfence-after-load=@var{yes}} since lfence will be generated
495 after loading branch target register.
497 @cindex @samp{-mlfence-before-ret=} option, i386
498 @cindex @samp{-mlfence-before-ret=} option, x86-64
499 @item -mlfence-before-ret=@var{none}
500 @item -mlfence-before-ret=@var{shl}
501 @item -mlfence-before-ret=@var{or}
502 @item -mlfence-before-ret=@var{yes}
503 @itemx -mlfence-before-ret=@var{not}
504 These options control whether the assembler should generate lfence
505 before ret. @option{-mlfence-before-ret=@var{or}} will generate
506 generate or instruction with lfence.
507 @option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction
508 with lfence. @option{-mlfence-before-ret=@var{not}} will generate not
509 instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not
510 generate lfence, which is the default.
512 @cindex @samp{-mx86-used-note=} option, i386
513 @cindex @samp{-mx86-used-note=} option, x86-64
514 @item -mx86-used-note=@var{no}
515 @itemx -mx86-used-note=@var{yes}
516 These options control whether the assembler should generate
517 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
518 GNU property notes. The default can be controlled by the
519 @option{--enable-x86-used-note} configure option.
521 @cindex @samp{-mevexrcig=} option, i386
522 @cindex @samp{-mevexrcig=} option, x86-64
523 @item -mevexrcig=@var{rne}
524 @itemx -mevexrcig=@var{rd}
525 @itemx -mevexrcig=@var{ru}
526 @itemx -mevexrcig=@var{rz}
527 These options control how the assembler should encode SAE-only
528 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
529 of EVEX instruction with 00, which is the default.
530 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
531 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
532 with 01, 10 and 11 RC bits, respectively.
534 @cindex @samp{-mamd64} option, x86-64
535 @cindex @samp{-mintel64} option, x86-64
538 This option specifies that the assembler should accept only AMD64 or
539 Intel64 ISA in 64-bit mode. The default is to accept common, Intel64
542 @cindex @samp{-O0} option, i386
543 @cindex @samp{-O0} option, x86-64
544 @cindex @samp{-O} option, i386
545 @cindex @samp{-O} option, x86-64
546 @cindex @samp{-O1} option, i386
547 @cindex @samp{-O1} option, x86-64
548 @cindex @samp{-O2} option, i386
549 @cindex @samp{-O2} option, x86-64
550 @cindex @samp{-Os} option, i386
551 @cindex @samp{-Os} option, x86-64
552 @item -O0 | -O | -O1 | -O2 | -Os
553 Optimize instruction encoding with smaller instruction size. @samp{-O}
554 and @samp{-O1} encode 64-bit register load instructions with 64-bit
555 immediate as 32-bit register load instructions with 31-bit or 32-bits
556 immediates, encode 64-bit register clearing instructions with 32-bit
557 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
558 register clearing instructions with 128-bit VEX vector register
559 clearing instructions, encode 128-bit/256-bit EVEX vector
560 register load/store instructions with VEX vector register load/store
561 instructions, and encode 128-bit/256-bit EVEX packed integer logical
562 instructions with 128-bit/256-bit VEX packed integer logical.
564 @samp{-O2} includes @samp{-O1} optimization plus encodes
565 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
566 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
567 instructions with commutative source operands will also have their
568 source operands swapped if this allows using the 2-byte VEX prefix form
569 instead of the 3-byte one. Certain forms of AND as well as OR with the
570 same (register) operand specified twice will also be changed to TEST.
572 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
573 and 64-bit register tests with immediate as 8-bit register test with
574 immediate. @samp{-O0} turns off this optimization.
579 @node i386-Directives
580 @section x86 specific Directives
582 @cindex machine directives, x86
583 @cindex x86 machine directives
586 @cindex @code{lcomm} directive, COFF
587 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
588 Reserve @var{length} (an absolute expression) bytes for a local common
589 denoted by @var{symbol}. The section and value of @var{symbol} are
590 those of the new local common. The addresses are allocated in the bss
591 section, so that at run-time the bytes start off zeroed. Since
592 @var{symbol} is not declared global, it is normally not visible to
593 @code{@value{LD}}. The optional third parameter, @var{alignment},
594 specifies the desired alignment of the symbol in the bss section.
596 This directive is only available for COFF based x86 targets.
598 @cindex @code{largecomm} directive, ELF
599 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
600 This directive behaves in the same way as the @code{comm} directive
601 except that the data is placed into the @var{.lbss} section instead of
602 the @var{.bss} section @ref{Comm}.
604 The directive is intended to be used for data which requires a large
605 amount of space, and it is only available for ELF based x86_64
608 @cindex @code{value} directive
609 @item .value @var{expression} [, @var{expression}]
610 This directive behaves in the same way as the @code{.short} directive,
611 taking a series of comma separated expressions and storing them as
612 two-byte wide values into the current section.
614 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
619 @section i386 Syntactical Considerations
621 * i386-Variations:: AT&T Syntax versus Intel Syntax
622 * i386-Chars:: Special Characters
625 @node i386-Variations
626 @subsection AT&T Syntax versus Intel Syntax
628 @cindex i386 intel_syntax pseudo op
629 @cindex intel_syntax pseudo op, i386
630 @cindex i386 att_syntax pseudo op
631 @cindex att_syntax pseudo op, i386
632 @cindex i386 syntax compatibility
633 @cindex syntax compatibility, i386
634 @cindex x86-64 intel_syntax pseudo op
635 @cindex intel_syntax pseudo op, x86-64
636 @cindex x86-64 att_syntax pseudo op
637 @cindex att_syntax pseudo op, x86-64
638 @cindex x86-64 syntax compatibility
639 @cindex syntax compatibility, x86-64
641 @code{@value{AS}} now supports assembly using Intel assembler syntax.
642 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
643 back to the usual AT&T mode for compatibility with the output of
644 @code{@value{GCC}}. Either of these directives may have an optional
645 argument, @code{prefix}, or @code{noprefix} specifying whether registers
646 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
647 different from Intel syntax. We mention these differences because
648 almost all 80386 documents use Intel syntax. Notable differences
649 between the two syntaxes are:
651 @cindex immediate operands, i386
652 @cindex i386 immediate operands
653 @cindex register operands, i386
654 @cindex i386 register operands
655 @cindex jump/call operands, i386
656 @cindex i386 jump/call operands
657 @cindex operand delimiters, i386
659 @cindex immediate operands, x86-64
660 @cindex x86-64 immediate operands
661 @cindex register operands, x86-64
662 @cindex x86-64 register operands
663 @cindex jump/call operands, x86-64
664 @cindex x86-64 jump/call operands
665 @cindex operand delimiters, x86-64
668 AT&T immediate operands are preceded by @samp{$}; Intel immediate
669 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
670 AT&T register operands are preceded by @samp{%}; Intel register operands
671 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
672 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
674 @cindex i386 source, destination operands
675 @cindex source, destination operands; i386
676 @cindex x86-64 source, destination operands
677 @cindex source, destination operands; x86-64
679 AT&T and Intel syntax use the opposite order for source and destination
680 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
681 @samp{source, dest} convention is maintained for compatibility with
682 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
683 instructions with 2 immediate operands, such as the @samp{enter}
684 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
686 @cindex mnemonic suffixes, i386
687 @cindex sizes operands, i386
688 @cindex i386 size suffixes
689 @cindex mnemonic suffixes, x86-64
690 @cindex sizes operands, x86-64
691 @cindex x86-64 size suffixes
693 In AT&T syntax the size of memory operands is determined from the last
694 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
695 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
696 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
697 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
698 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
699 no other way to disambiguate an instruction. Intel syntax accomplishes this by
700 prefixing memory operands (@emph{not} the instruction mnemonics) with
701 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
702 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
703 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
704 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
705 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
707 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
708 instruction with the 64-bit displacement or immediate operand.
710 @cindex return instructions, i386
711 @cindex i386 jump, call, return
712 @cindex return instructions, x86-64
713 @cindex x86-64 jump, call, return
715 Immediate form long jumps and calls are
716 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
718 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
720 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
721 @samp{ret far @var{stack-adjust}}.
723 @cindex sections, i386
724 @cindex i386 sections
725 @cindex sections, x86-64
726 @cindex x86-64 sections
728 The AT&T assembler does not provide support for multiple section
729 programs. Unix style systems expect all programs to be single sections.
733 @subsection Special Characters
735 @cindex line comment character, i386
736 @cindex i386 line comment character
737 The presence of a @samp{#} appearing anywhere on a line indicates the
738 start of a comment that extends to the end of that line.
740 If a @samp{#} appears as the first character of a line then the whole
741 line is treated as a comment, but in this case the line can also be a
742 logical line number directive (@pxref{Comments}) or a preprocessor
743 control command (@pxref{Preprocessing}).
745 If the @option{--divide} command-line option has not been specified
746 then the @samp{/} character appearing anywhere on a line also
747 introduces a line comment.
749 @cindex line separator, i386
750 @cindex statement separator, i386
751 @cindex i386 line separator
752 The @samp{;} character can be used to separate statements on the same
756 @section i386-Mnemonics
757 @subsection Instruction Naming
759 @cindex i386 instruction naming
760 @cindex instruction naming, i386
761 @cindex x86-64 instruction naming
762 @cindex instruction naming, x86-64
764 Instruction mnemonics are suffixed with one character modifiers which
765 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
766 and @samp{q} specify byte, word, long and quadruple word operands. If
767 no suffix is specified by an instruction then @code{@value{AS}} tries to
768 fill in the missing suffix based on the destination register operand
769 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
770 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
771 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
772 assembler which assumes that a missing mnemonic suffix implies long
773 operand size. (This incompatibility does not affect compiler output
774 since compilers always explicitly specify the mnemonic suffix.)
776 When there is no sizing suffix and no (suitable) register operands to
777 deduce the size of memory operands, with a few exceptions and where long
778 operand size is possible in the first place, operand size will default
779 to long in 32- and 64-bit modes. Similarly it will default to short in
780 16-bit mode. Noteworthy exceptions are
784 Instructions with an implicit on-stack operand as well as branches,
785 which default to quad in 64-bit mode.
788 Sign- and zero-extending moves, which default to byte size source
792 Floating point insns with integer operands, which default to short (for
793 perhaps historical reasons).
796 CRC32 with a 64-bit destination, which defaults to a quad source
801 @cindex encoding options, i386
802 @cindex encoding options, x86-64
804 Different encoding options can be specified via pseudo prefixes:
808 @samp{@{disp8@}} -- prefer 8-bit displacement.
811 @samp{@{disp32@}} -- prefer 32-bit displacement.
814 @samp{@{disp16@}} -- prefer 16-bit displacement.
817 @samp{@{load@}} -- prefer load-form instruction.
820 @samp{@{store@}} -- prefer store-form instruction.
823 @samp{@{vex@}} -- encode with VEX prefix.
826 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
829 @samp{@{evex@}} -- encode with EVEX prefix.
832 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
833 instructions (x86-64 only). Note that this differs from the @samp{rex}
834 prefix which generates REX prefix unconditionally.
837 @samp{@{nooptimize@}} -- disable instruction size optimization.
840 Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix
841 by default. The pseudo @samp{@{vex@}} prefix can be used to encode
842 mnemonics of Intel VNNI/IFMA instructions with the VEX prefix.
844 @cindex conversion instructions, i386
845 @cindex i386 conversion instructions
846 @cindex conversion instructions, x86-64
847 @cindex x86-64 conversion instructions
848 The Intel-syntax conversion instructions
852 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
855 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
858 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
861 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
864 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
868 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
869 @samp{%rdx:%rax} (x86-64 only),
873 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
874 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
877 @cindex extension instructions, i386
878 @cindex i386 extension instructions
879 @cindex extension instructions, x86-64
880 @cindex x86-64 extension instructions
881 The Intel-syntax extension instructions
885 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}.
888 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}.
891 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64}
895 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32}
898 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64}
902 @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64}
906 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}.
909 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}.
912 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64}
916 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32}
919 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64}
924 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
925 @samp{movsbq/movsxb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
926 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
927 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
928 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
930 @cindex jump instructions, i386
931 @cindex call instructions, i386
932 @cindex jump instructions, x86-64
933 @cindex call instructions, x86-64
934 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
935 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
938 @subsection AT&T Mnemonic versus Intel Mnemonic
940 @cindex i386 mnemonic compatibility
941 @cindex mnemonic compatibility, i386
943 @code{@value{AS}} supports assembly using Intel mnemonic.
944 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
945 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
946 syntax for compatibility with the output of @code{@value{GCC}}.
947 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
948 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
949 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
950 assembler with different mnemonics from those in Intel IA32 specification.
951 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
954 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
955 register. @samp{movsxd} should be used to encode 16-bit or 32-bit
956 destination register with both AT&T and Intel mnemonics.
960 @section Register Naming
962 @cindex i386 registers
963 @cindex registers, i386
964 @cindex x86-64 registers
965 @cindex registers, x86-64
966 Register operands are always prefixed with @samp{%}. The 80386 registers
971 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
972 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
973 frame pointer), and @samp{%esp} (the stack pointer).
976 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
977 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
980 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
981 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
982 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
983 @samp{%cx}, and @samp{%dx})
986 the 6 section registers @samp{%cs} (code section), @samp{%ds}
987 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
991 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
992 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
995 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
996 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
999 the 2 test registers @samp{%tr6} and @samp{%tr7}.
1002 the 8 floating point register stack @samp{%st} or equivalently
1003 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
1004 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
1005 These registers are overloaded by 8 MMX registers @samp{%mm0},
1006 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
1007 @samp{%mm6} and @samp{%mm7}.
1010 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
1011 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
1014 The AMD x86-64 architecture extends the register set by:
1018 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
1019 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
1020 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
1024 the 8 extended registers @samp{%r8}--@samp{%r15}.
1027 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
1030 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
1033 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
1036 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
1039 the 8 debug registers: @samp{%db8}--@samp{%db15}.
1042 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
1045 With the AVX extensions more registers were made available:
1050 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
1051 available in 32-bit mode). The bottom 128 bits are overlaid with the
1052 @samp{xmm0}--@samp{xmm15} registers.
1056 The AVX512 extensions added the following registers:
1061 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
1062 available in 32-bit mode). The bottom 128 bits are overlaid with the
1063 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
1064 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
1067 the 8 mask registers @samp{%k0}--@samp{%k7}.
1072 @section Instruction Prefixes
1074 @cindex i386 instruction prefixes
1075 @cindex instruction prefixes, i386
1076 @cindex prefixes, i386
1077 Instruction prefixes are used to modify the following instruction. They
1078 are used to repeat string instructions, to provide section overrides, to
1079 perform bus lock operations, and to change operand and address sizes.
1080 (Most instructions that normally operate on 32-bit operands will use
1081 16-bit operands if the instruction has an ``operand size'' prefix.)
1082 Instruction prefixes are best written on the same line as the instruction
1083 they act upon. For example, the @samp{scas} (scan string) instruction is
1087 repne scas %es:(%edi),%al
1090 You may also place prefixes on the lines immediately preceding the
1091 instruction, but this circumvents checks that @code{@value{AS}} does
1092 with prefixes, and will not work with all prefixes.
1094 Here is a list of instruction prefixes:
1096 @cindex section override prefixes, i386
1099 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1100 @samp{fs}, @samp{gs}. These are automatically added by specifying
1101 using the @var{section}:@var{memory-operand} form for memory references.
1103 @cindex size prefixes, i386
1105 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1106 change 32-bit operands/addresses into 16-bit operands/addresses,
1107 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1108 @code{.code16} section) into 32-bit operands/addresses. These prefixes
1109 @emph{must} appear on the same line of code as the instruction they
1110 modify. For example, in a 16-bit @code{.code16} section, you might
1117 @cindex bus lock prefixes, i386
1118 @cindex inhibiting interrupts, i386
1120 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1121 the instruction it precedes. (This is only valid with certain
1122 instructions; see a 80386 manual for details).
1124 @cindex coprocessor wait, i386
1126 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1127 complete the current instruction. This should never be needed for the
1128 80386/80387 combination.
1130 @cindex repeat prefixes, i386
1132 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1133 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1134 times if the current address size is 16-bits).
1135 @cindex REX prefixes, i386
1137 The @samp{rex} family of prefixes is used by x86-64 to encode
1138 extensions to i386 instruction set. The @samp{rex} prefix has four
1139 bits --- an operand size overwrite (@code{64}) used to change operand size
1140 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
1143 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1144 instruction emits @samp{rex} prefix with all the bits set. By omitting
1145 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
1146 prefixes as well. Normally, there is no need to write the prefixes
1147 explicitly, since gas will automatically generate them based on the
1148 instruction operands.
1152 @section Memory References
1154 @cindex i386 memory references
1155 @cindex memory references, i386
1156 @cindex x86-64 memory references
1157 @cindex memory references, x86-64
1158 An Intel syntax indirect memory reference of the form
1161 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1165 is translated into the AT&T syntax
1168 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1172 where @var{base} and @var{index} are the optional 32-bit base and
1173 index registers, @var{disp} is the optional displacement, and
1174 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1175 to calculate the address of the operand. If no @var{scale} is
1176 specified, @var{scale} is taken to be 1. @var{section} specifies the
1177 optional section register for the memory operand, and may override the
1178 default section register (see a 80386 manual for section register
1179 defaults). Note that section overrides in AT&T syntax @emph{must}
1180 be preceded by a @samp{%}. If you specify a section override which
1181 coincides with the default section register, @code{@value{AS}} does @emph{not}
1182 output any section register override prefixes to assemble the given
1183 instruction. Thus, section overrides can be specified to emphasize which
1184 section register is used for a given memory operand.
1186 Here are some examples of Intel and AT&T style memory references:
1189 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1190 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1191 missing, and the default section is used (@samp{%ss} for addressing with
1192 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1194 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1195 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1196 @samp{foo}. All other fields are missing. The section register here
1197 defaults to @samp{%ds}.
1199 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1200 This uses the value pointed to by @samp{foo} as a memory operand.
1201 Note that @var{base} and @var{index} are both missing, but there is only
1202 @emph{one} @samp{,}. This is a syntactic exception.
1204 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1205 This selects the contents of the variable @samp{foo} with section
1206 register @var{section} being @samp{%gs}.
1209 Absolute (as opposed to PC relative) call and jump operands must be
1210 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1211 always chooses PC relative addressing for jump/call labels.
1213 Any instruction that has a memory operand, but no register operand,
1214 @emph{must} specify its size (byte, word, long, or quadruple) with an
1215 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1218 The x86-64 architecture adds an RIP (instruction pointer relative)
1219 addressing. This addressing mode is specified by using @samp{rip} as a
1220 base register. Only constant offsets are valid. For example:
1223 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1224 Points to the address 1234 bytes past the end of the current
1227 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1228 Points to the @code{symbol} in RIP relative way, this is shorter than
1229 the default absolute addressing.
1232 Other addressing modes remain unchanged in x86-64 architecture, except
1233 registers used are 64-bit instead of 32-bit.
1236 @section Handling of Jump Instructions
1238 @cindex jump optimization, i386
1239 @cindex i386 jump optimization
1240 @cindex jump optimization, x86-64
1241 @cindex x86-64 jump optimization
1242 Jump instructions are always optimized to use the smallest possible
1243 displacements. This is accomplished by using byte (8-bit) displacement
1244 jumps whenever the target is sufficiently close. If a byte displacement
1245 is insufficient a long displacement is used. We do not support
1246 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1247 instruction with the @samp{data16} instruction prefix), since the 80386
1248 insists upon masking @samp{%eip} to 16 bits after the word displacement
1249 is added. (See also @pxref{i386-Arch})
1251 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1252 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1253 displacements, so that if you use these instructions (@code{@value{GCC}} does
1254 not use them) you may get an error message (and incorrect code). The AT&T
1255 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1266 @section Floating Point
1268 @cindex i386 floating point
1269 @cindex floating point, i386
1270 @cindex x86-64 floating point
1271 @cindex floating point, x86-64
1272 All 80387 floating point types except packed BCD are supported.
1273 (BCD support may be added without much difficulty). These data
1274 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1275 double (64-bit), and extended (80-bit) precision floating point.
1276 Each supported type has an instruction mnemonic suffix and a constructor
1277 associated with it. Instruction mnemonic suffixes specify the operand's
1278 data type. Constructors build these data types into memory.
1280 @cindex @code{float} directive, i386
1281 @cindex @code{single} directive, i386
1282 @cindex @code{double} directive, i386
1283 @cindex @code{tfloat} directive, i386
1284 @cindex @code{hfloat} directive, i386
1285 @cindex @code{bfloat16} directive, i386
1286 @cindex @code{float} directive, x86-64
1287 @cindex @code{single} directive, x86-64
1288 @cindex @code{double} directive, x86-64
1289 @cindex @code{tfloat} directive, x86-64
1290 @cindex @code{hfloat} directive, x86-64
1291 @cindex @code{bfloat16} directive, x86-64
1294 Floating point constructors are @samp{.float} or @samp{.single},
1295 @samp{.double}, @samp{.tfloat}, @samp{.hfloat}, and @samp{.bfloat16} for 32-,
1296 64-, 80-, and 16-bit (two flavors) formats respectively. The former three
1297 correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, and @samp{t}.
1298 @samp{t} stands for 80-bit (ten byte) real. The 80387 only supports this
1299 format via the @samp{fldt} (load 80-bit real to stack top) and @samp{fstpt}
1300 (store 80-bit real and pop stack) instructions.
1302 @cindex @code{word} directive, i386
1303 @cindex @code{long} directive, i386
1304 @cindex @code{int} directive, i386
1305 @cindex @code{quad} directive, i386
1306 @cindex @code{word} directive, x86-64
1307 @cindex @code{long} directive, x86-64
1308 @cindex @code{int} directive, x86-64
1309 @cindex @code{quad} directive, x86-64
1311 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1312 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1313 corresponding instruction mnemonic suffixes are @samp{s} (short),
1314 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1315 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1316 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1317 stack) instructions.
1320 Register to register operations should not use instruction mnemonic suffixes.
1321 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1322 wrote @samp{fst %st, %st(1)}, since all register to register operations
1323 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1324 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1325 then stores the result in the 4 byte location @samp{mem})
1328 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1331 @cindex 3DNow!, i386
1334 @cindex 3DNow!, x86-64
1335 @cindex SIMD, x86-64
1337 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1338 instructions for integer data), available on Intel's Pentium MMX
1339 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1340 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1341 instruction set (SIMD instructions for 32-bit floating point data)
1342 available on AMD's K6-2 processor and possibly others in the future.
1344 Currently, @code{@value{AS}} does not support Intel's floating point
1347 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1348 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1349 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1350 floating point values. The MMX registers cannot be used at the same time
1351 as the floating point stack.
1353 See Intel and AMD documentation, keeping in mind that the operand order in
1354 instructions is reversed from the Intel syntax.
1357 @section AMD's Lightweight Profiling Instructions
1362 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1363 instruction set, available on AMD's Family 15h (Orochi) processors.
1365 LWP enables applications to collect and manage performance data, and
1366 react to performance events. The collection of performance data
1367 requires no context switches. LWP runs in the context of a thread and
1368 so several counters can be used independently across multiple threads.
1369 LWP can be used in both 64-bit and legacy 32-bit modes.
1371 For detailed information on the LWP instruction set, see the
1372 @cite{AMD Lightweight Profiling Specification} available at
1373 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1376 @section Bit Manipulation Instructions
1381 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1383 BMI instructions provide several instructions implementing individual
1384 bit manipulation operations such as isolation, masking, setting, or
1387 @c Need to add a specification citation here when available.
1390 @section AMD's Trailing Bit Manipulation Instructions
1395 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1396 instruction set, available on AMD's BDVER2 processors (Trinity and
1399 TBM instructions provide instructions implementing individual bit
1400 manipulation operations such as isolating, masking, setting, resetting,
1401 complementing, and operations on trailing zeros and ones.
1403 @c Need to add a specification citation here when available.
1406 @section Writing 16-bit Code
1408 @cindex i386 16-bit code
1409 @cindex 16-bit code, i386
1410 @cindex real-mode code, i386
1411 @cindex @code{code16gcc} directive, i386
1412 @cindex @code{code16} directive, i386
1413 @cindex @code{code32} directive, i386
1414 @cindex @code{code64} directive, i386
1415 @cindex @code{code64} directive, x86-64
1416 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1417 or 64-bit x86-64 code depending on the default configuration,
1418 it also supports writing code to run in real mode or in 16-bit protected
1419 mode code segments. To do this, put a @samp{.code16} or
1420 @samp{.code16gcc} directive before the assembly language instructions to
1421 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1422 32-bit code with the @samp{.code32} directive or 64-bit code with the
1423 @samp{.code64} directive.
1425 @samp{.code16gcc} provides experimental support for generating 16-bit
1426 code from gcc, and differs from @samp{.code16} in that @samp{call},
1427 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1428 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1429 default to 32-bit size. This is so that the stack pointer is
1430 manipulated in the same way over function calls, allowing access to
1431 function parameters at the same stack offsets as in 32-bit mode.
1432 @samp{.code16gcc} also automatically adds address size prefixes where
1433 necessary to use the 32-bit addressing modes that gcc generates.
1435 The code which @code{@value{AS}} generates in 16-bit mode will not
1436 necessarily run on a 16-bit pre-80386 processor. To write code that
1437 runs on such a processor, you must refrain from using @emph{any} 32-bit
1438 constructs which require @code{@value{AS}} to output address or operand
1441 Note that writing 16-bit code instructions by explicitly specifying a
1442 prefix or an instruction mnemonic suffix within a 32-bit code section
1443 generates different machine instructions than those generated for a
1444 16-bit code segment. In a 32-bit code section, the following code
1445 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1446 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1452 The same code in a 16-bit code section would generate the machine
1453 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1454 is correct since the processor default operand size is assumed to be 16
1455 bits in a 16-bit code section.
1458 @section Specifying CPU Architecture
1460 @cindex arch directive, i386
1461 @cindex i386 arch directive
1462 @cindex arch directive, x86-64
1463 @cindex x86-64 arch directive
1465 @code{@value{AS}} may be told to assemble for a particular CPU
1466 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1467 directive enables a warning when gas detects an instruction that is not
1468 supported on the CPU specified. The choices for @var{cpu_type} are:
1470 @multitable @columnfractions .20 .20 .20 .20
1471 @item @samp{default} @tab @samp{push} @tab @samp{pop}
1472 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1473 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1474 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1475 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1476 @item @samp{corei7} @tab @samp{iamcu}
1477 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1478 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1479 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
1480 @item @samp{znver4} @tab @samp{btver1} @tab @samp{btver2} @tab @samp{generic32}
1481 @item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1482 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
1483 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1484 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1485 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1486 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1487 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1488 @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1489 @item @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
1490 @item @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1491 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1492 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1493 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1494 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1495 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1496 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1497 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1498 @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
1499 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
1500 @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
1501 @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
1502 @item @samp{.avx_ne_convert} @tab @samp{.rao_int}
1503 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1504 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1505 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
1506 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16} @tab @samp{.amx_tile}
1507 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
1508 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1509 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1510 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1511 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1512 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
1513 @item @samp{.tlbsync}
1516 Apart from the warning, there are only two other effects on
1517 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1518 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1519 will automatically use a two byte opcode sequence. The larger three
1520 byte opcode sequence is used on the 486 (and when no architecture is
1521 specified) because it executes faster on the 486. Note that you can
1522 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1523 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1524 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1525 conditional jumps will be promoted when necessary to a two instruction
1526 sequence consisting of a conditional jump of the opposite sense around
1527 an unconditional jump to the target.
1529 Note that the sub-architecture specifiers (starting with a dot) can be prefixed
1530 with @code{no} to revoke the respective (and any dependent) functionality.
1532 Following the CPU architecture (but not a sub-architecture, which are those
1533 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1534 control automatic promotion of conditional jumps. @samp{jumps} is the
1535 default, and enables jump promotion; All external jumps will be of the long
1536 variety, and file-local jumps will be promoted as necessary.
1537 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1538 byte offset jumps, and warns about file-local conditional jumps that
1539 @code{@value{AS}} promotes.
1540 Unconditional jumps are treated as for @samp{jumps}.
1549 @section AMD64 ISA vs. Intel64 ISA
1551 There are some discrepancies between AMD64 and Intel64 ISAs.
1554 @item For @samp{movsxd} with 16-bit destination register, AMD64
1555 supports 32-bit source operand and Intel64 supports 16-bit source
1558 @item For far branches (with explicit memory operand), both ISAs support
1559 32- and 16-bit operand size. Intel64 additionally supports 64-bit
1560 operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax
1561 and with an explicit @samp{tbyte ptr} operand size specifier in Intel
1564 @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16-
1565 and 32-bit operand size (32- and 48-bit memory operand) in both ISAs,
1566 while Intel64 additionally supports 64-bit operand sise (80-bit memory
1572 @section AT&T Syntax bugs
1574 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1575 assemblers, generate floating point instructions with reversed source
1576 and destination registers in certain cases. Unfortunately, gcc and
1577 possibly many other programs use this reversed syntax, so we're stuck
1586 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1587 than the expected @samp{%st(3) - %st}. This happens with all the
1588 non-commutative arithmetic floating point operations with two register
1589 operands where the source register is @samp{%st} and the destination
1590 register is @samp{%st(i)}.
1595 @cindex i386 @code{mul}, @code{imul} instructions
1596 @cindex @code{mul} instruction, i386
1597 @cindex @code{imul} instruction, i386
1598 @cindex @code{mul} instruction, x86-64
1599 @cindex @code{imul} instruction, x86-64
1600 There is some trickery concerning the @samp{mul} and @samp{imul}
1601 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1602 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1603 for @samp{imul}) can be output only in the one operand form. Thus,
1604 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1605 the expanding multiply would clobber the @samp{%edx} register, and this
1606 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1607 64-bit product in @samp{%edx:%eax}.
1609 We have added a two operand form of @samp{imul} when the first operand
1610 is an immediate mode expression and the second operand is a register.
1611 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1612 example, can be done with @samp{imul $69, %eax} rather than @samp{imul