]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - gas/doc/c-i386.texi
x86: optimize AND/OR with twice the same register
[thirdparty/binutils-gdb.git] / gas / doc / c-i386.texi
1 @c Copyright (C) 1991-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4 @c man end
5
6 @ifset GENERIC
7 @page
8 @node i386-Dependent
9 @chapter 80386 Dependent Features
10 @end ifset
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
14 @end ifclear
15
16 @cindex i386 support
17 @cindex i80386 support
18 @cindex x86-64 support
19
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
23
24 @menu
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
41 * i386-Notes:: Notes
42 @end menu
43
44 @node i386-Options
45 @section Options
46
47 @cindex options for i386
48 @cindex options for x86-64
49 @cindex i386 options
50 @cindex x86-64 options
51
52 The i386 version of @code{@value{AS}} has a few machine
53 dependent options:
54
55 @c man begin OPTIONS
56 @table @gcctabopt
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
67 respectively.
68
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
73
74 @item -n
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
79
80 @cindex @samp{--divide} option, i386
81 @item --divide
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
87
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
95 @code{i8086},
96 @code{i186},
97 @code{i286},
98 @code{i386},
99 @code{i486},
100 @code{i586},
101 @code{i686},
102 @code{pentium},
103 @code{pentiumpro},
104 @code{pentiumii},
105 @code{pentiumiii},
106 @code{pentium4},
107 @code{prescott},
108 @code{nocona},
109 @code{core},
110 @code{core2},
111 @code{corei7},
112 @code{l1om},
113 @code{k1om},
114 @code{iamcu},
115 @code{k6},
116 @code{k6_2},
117 @code{athlon},
118 @code{opteron},
119 @code{k8},
120 @code{amdfam10},
121 @code{bdver1},
122 @code{bdver2},
123 @code{bdver3},
124 @code{bdver4},
125 @code{znver1},
126 @code{znver2},
127 @code{btver1},
128 @code{btver2},
129 @code{generic32} and
130 @code{generic64}.
131
132 In addition to the basic instruction set, the assembler can be told to
133 accept various extension mnemonics. For example,
134 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
135 @var{vmx}. The following extensions are currently supported:
136 @code{8087},
137 @code{287},
138 @code{387},
139 @code{687},
140 @code{no87},
141 @code{no287},
142 @code{no387},
143 @code{no687},
144 @code{cmov},
145 @code{nocmov},
146 @code{fxsr},
147 @code{nofxsr},
148 @code{mmx},
149 @code{nommx},
150 @code{sse},
151 @code{sse2},
152 @code{sse3},
153 @code{ssse3},
154 @code{sse4.1},
155 @code{sse4.2},
156 @code{sse4},
157 @code{nosse},
158 @code{nosse2},
159 @code{nosse3},
160 @code{nossse3},
161 @code{nosse4.1},
162 @code{nosse4.2},
163 @code{nosse4},
164 @code{avx},
165 @code{avx2},
166 @code{noavx},
167 @code{noavx2},
168 @code{adx},
169 @code{rdseed},
170 @code{prfchw},
171 @code{smap},
172 @code{mpx},
173 @code{sha},
174 @code{rdpid},
175 @code{ptwrite},
176 @code{cet},
177 @code{gfni},
178 @code{vaes},
179 @code{vpclmulqdq},
180 @code{prefetchwt1},
181 @code{clflushopt},
182 @code{se1},
183 @code{clwb},
184 @code{movdiri},
185 @code{movdir64b},
186 @code{enqcmd},
187 @code{avx512f},
188 @code{avx512cd},
189 @code{avx512er},
190 @code{avx512pf},
191 @code{avx512vl},
192 @code{avx512bw},
193 @code{avx512dq},
194 @code{avx512ifma},
195 @code{avx512vbmi},
196 @code{avx512_4fmaps},
197 @code{avx512_4vnniw},
198 @code{avx512_vpopcntdq},
199 @code{avx512_vbmi2},
200 @code{avx512_vnni},
201 @code{avx512_bitalg},
202 @code{avx512_bf16},
203 @code{noavx512f},
204 @code{noavx512cd},
205 @code{noavx512er},
206 @code{noavx512pf},
207 @code{noavx512vl},
208 @code{noavx512bw},
209 @code{noavx512dq},
210 @code{noavx512ifma},
211 @code{noavx512vbmi},
212 @code{noavx512_4fmaps},
213 @code{noavx512_4vnniw},
214 @code{noavx512_vpopcntdq},
215 @code{noavx512_vbmi2},
216 @code{noavx512_vnni},
217 @code{noavx512_bitalg},
218 @code{noavx512_vp2intersect},
219 @code{noavx512_bf16},
220 @code{noenqcmd},
221 @code{vmx},
222 @code{vmfunc},
223 @code{smx},
224 @code{xsave},
225 @code{xsaveopt},
226 @code{xsavec},
227 @code{xsaves},
228 @code{aes},
229 @code{pclmul},
230 @code{fsgsbase},
231 @code{rdrnd},
232 @code{f16c},
233 @code{bmi2},
234 @code{fma},
235 @code{movbe},
236 @code{ept},
237 @code{lzcnt},
238 @code{hle},
239 @code{rtm},
240 @code{invpcid},
241 @code{clflush},
242 @code{mwaitx},
243 @code{clzero},
244 @code{wbnoinvd},
245 @code{pconfig},
246 @code{waitpkg},
247 @code{cldemote},
248 @code{lwp},
249 @code{fma4},
250 @code{xop},
251 @code{cx16},
252 @code{syscall},
253 @code{rdtscp},
254 @code{3dnow},
255 @code{3dnowa},
256 @code{sse4a},
257 @code{sse5},
258 @code{svme},
259 @code{abm} and
260 @code{padlock}.
261 Note that rather than extending a basic instruction set, the extension
262 mnemonics starting with @code{no} revoke the respective functionality.
263
264 When the @code{.arch} directive is used with @option{-march}, the
265 @code{.arch} directive will take precedent.
266
267 @cindex @samp{-mtune=} option, i386
268 @cindex @samp{-mtune=} option, x86-64
269 @item -mtune=@var{CPU}
270 This option specifies a processor to optimize for. When used in
271 conjunction with the @option{-march} option, only instructions
272 of the processor specified by the @option{-march} option will be
273 generated.
274
275 Valid @var{CPU} values are identical to the processor list of
276 @option{-march=@var{CPU}}.
277
278 @cindex @samp{-msse2avx} option, i386
279 @cindex @samp{-msse2avx} option, x86-64
280 @item -msse2avx
281 This option specifies that the assembler should encode SSE instructions
282 with VEX prefix.
283
284 @cindex @samp{-msse-check=} option, i386
285 @cindex @samp{-msse-check=} option, x86-64
286 @item -msse-check=@var{none}
287 @itemx -msse-check=@var{warning}
288 @itemx -msse-check=@var{error}
289 These options control if the assembler should check SSE instructions.
290 @option{-msse-check=@var{none}} will make the assembler not to check SSE
291 instructions, which is the default. @option{-msse-check=@var{warning}}
292 will make the assembler issue a warning for any SSE instruction.
293 @option{-msse-check=@var{error}} will make the assembler issue an error
294 for any SSE instruction.
295
296 @cindex @samp{-mavxscalar=} option, i386
297 @cindex @samp{-mavxscalar=} option, x86-64
298 @item -mavxscalar=@var{128}
299 @itemx -mavxscalar=@var{256}
300 These options control how the assembler should encode scalar AVX
301 instructions. @option{-mavxscalar=@var{128}} will encode scalar
302 AVX instructions with 128bit vector length, which is the default.
303 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
304 with 256bit vector length.
305
306 WARNING: Don't use this for production code - due to CPU errata the
307 resulting code may not work on certain models.
308
309 @cindex @samp{-mvexwig=} option, i386
310 @cindex @samp{-mvexwig=} option, x86-64
311 @item -mvexwig=@var{0}
312 @itemx -mvexwig=@var{1}
313 These options control how the assembler should encode VEX.W-ignored (WIG)
314 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
315 instructions with vex.w = 0, which is the default.
316 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
317 vex.w = 1.
318
319 WARNING: Don't use this for production code - due to CPU errata the
320 resulting code may not work on certain models.
321
322 @cindex @samp{-mevexlig=} option, i386
323 @cindex @samp{-mevexlig=} option, x86-64
324 @item -mevexlig=@var{128}
325 @itemx -mevexlig=@var{256}
326 @itemx -mevexlig=@var{512}
327 These options control how the assembler should encode length-ignored
328 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
329 EVEX instructions with 128bit vector length, which is the default.
330 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
331 encode LIG EVEX instructions with 256bit and 512bit vector length,
332 respectively.
333
334 @cindex @samp{-mevexwig=} option, i386
335 @cindex @samp{-mevexwig=} option, x86-64
336 @item -mevexwig=@var{0}
337 @itemx -mevexwig=@var{1}
338 These options control how the assembler should encode w-ignored (WIG)
339 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
340 EVEX instructions with evex.w = 0, which is the default.
341 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
342 evex.w = 1.
343
344 @cindex @samp{-mmnemonic=} option, i386
345 @cindex @samp{-mmnemonic=} option, x86-64
346 @item -mmnemonic=@var{att}
347 @itemx -mmnemonic=@var{intel}
348 This option specifies instruction mnemonic for matching instructions.
349 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
350 take precedent.
351
352 @cindex @samp{-msyntax=} option, i386
353 @cindex @samp{-msyntax=} option, x86-64
354 @item -msyntax=@var{att}
355 @itemx -msyntax=@var{intel}
356 This option specifies instruction syntax when processing instructions.
357 The @code{.att_syntax} and @code{.intel_syntax} directives will
358 take precedent.
359
360 @cindex @samp{-mnaked-reg} option, i386
361 @cindex @samp{-mnaked-reg} option, x86-64
362 @item -mnaked-reg
363 This option specifies that registers don't require a @samp{%} prefix.
364 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
365
366 @cindex @samp{-madd-bnd-prefix} option, i386
367 @cindex @samp{-madd-bnd-prefix} option, x86-64
368 @item -madd-bnd-prefix
369 This option forces the assembler to add BND prefix to all branches, even
370 if such prefix was not explicitly specified in the source code.
371
372 @cindex @samp{-mshared} option, i386
373 @cindex @samp{-mshared} option, x86-64
374 @item -mno-shared
375 On ELF target, the assembler normally optimizes out non-PLT relocations
376 against defined non-weak global branch targets with default visibility.
377 The @samp{-mshared} option tells the assembler to generate code which
378 may go into a shared library where all non-weak global branch targets
379 with default visibility can be preempted. The resulting code is
380 slightly bigger. This option only affects the handling of branch
381 instructions.
382
383 @cindex @samp{-mbig-obj} option, x86-64
384 @item -mbig-obj
385 On x86-64 PE/COFF target this option forces the use of big object file
386 format, which allows more than 32768 sections.
387
388 @cindex @samp{-momit-lock-prefix=} option, i386
389 @cindex @samp{-momit-lock-prefix=} option, x86-64
390 @item -momit-lock-prefix=@var{no}
391 @itemx -momit-lock-prefix=@var{yes}
392 These options control how the assembler should encode lock prefix.
393 This option is intended as a workaround for processors, that fail on
394 lock prefix. This option can only be safely used with single-core,
395 single-thread computers
396 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
397 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
398 which is the default.
399
400 @cindex @samp{-mfence-as-lock-add=} option, i386
401 @cindex @samp{-mfence-as-lock-add=} option, x86-64
402 @item -mfence-as-lock-add=@var{no}
403 @itemx -mfence-as-lock-add=@var{yes}
404 These options control how the assembler should encode lfence, mfence and
405 sfence.
406 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
407 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
408 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
409 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
410 sfence as usual, which is the default.
411
412 @cindex @samp{-mrelax-relocations=} option, i386
413 @cindex @samp{-mrelax-relocations=} option, x86-64
414 @item -mrelax-relocations=@var{no}
415 @itemx -mrelax-relocations=@var{yes}
416 These options control whether the assembler should generate relax
417 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
418 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
419 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
420 @option{-mrelax-relocations=@var{no}} will not generate relax
421 relocations. The default can be controlled by a configure option
422 @option{--enable-x86-relax-relocations}.
423
424 @cindex @samp{-mx86-used-note=} option, i386
425 @cindex @samp{-mx86-used-note=} option, x86-64
426 @item -mx86-used-note=@var{no}
427 @itemx -mx86-used-note=@var{yes}
428 These options control whether the assembler should generate
429 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
430 GNU property notes. The default can be controlled by the
431 @option{--enable-x86-used-note} configure option.
432
433 @cindex @samp{-mevexrcig=} option, i386
434 @cindex @samp{-mevexrcig=} option, x86-64
435 @item -mevexrcig=@var{rne}
436 @itemx -mevexrcig=@var{rd}
437 @itemx -mevexrcig=@var{ru}
438 @itemx -mevexrcig=@var{rz}
439 These options control how the assembler should encode SAE-only
440 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
441 of EVEX instruction with 00, which is the default.
442 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
443 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
444 with 01, 10 and 11 RC bits, respectively.
445
446 @cindex @samp{-mamd64} option, x86-64
447 @cindex @samp{-mintel64} option, x86-64
448 @item -mamd64
449 @itemx -mintel64
450 This option specifies that the assembler should accept only AMD64 or
451 Intel64 ISA in 64-bit mode. The default is to accept both.
452
453 @cindex @samp{-O0} option, i386
454 @cindex @samp{-O0} option, x86-64
455 @cindex @samp{-O} option, i386
456 @cindex @samp{-O} option, x86-64
457 @cindex @samp{-O1} option, i386
458 @cindex @samp{-O1} option, x86-64
459 @cindex @samp{-O2} option, i386
460 @cindex @samp{-O2} option, x86-64
461 @cindex @samp{-Os} option, i386
462 @cindex @samp{-Os} option, x86-64
463 @item -O0 | -O | -O1 | -O2 | -Os
464 Optimize instruction encoding with smaller instruction size. @samp{-O}
465 and @samp{-O1} encode 64-bit register load instructions with 64-bit
466 immediate as 32-bit register load instructions with 31-bit or 32-bits
467 immediates, encode 64-bit register clearing instructions with 32-bit
468 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
469 register clearing instructions with 128-bit VEX vector register
470 clearing instructions, encode 128-bit/256-bit EVEX vector
471 register load/store instructions with VEX vector register load/store
472 instructions, and encode 128-bit/256-bit EVEX packed integer logical
473 instructions with 128-bit/256-bit VEX packed integer logical.
474
475 @samp{-O2} includes @samp{-O1} optimization plus encodes
476 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
477 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
478 instructions with commutative source operands will also have their
479 source operands swapped if this allows using the 2-byte VEX prefix form
480 instead of the 3-byte one. Certain forms of AND as well as OR with the
481 same (register) operand specified twice will also be changed to TEST.
482
483 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
484 and 64-bit register tests with immediate as 8-bit register test with
485 immediate. @samp{-O0} turns off this optimization.
486
487 @end table
488 @c man end
489
490 @node i386-Directives
491 @section x86 specific Directives
492
493 @cindex machine directives, x86
494 @cindex x86 machine directives
495 @table @code
496
497 @cindex @code{lcomm} directive, COFF
498 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
499 Reserve @var{length} (an absolute expression) bytes for a local common
500 denoted by @var{symbol}. The section and value of @var{symbol} are
501 those of the new local common. The addresses are allocated in the bss
502 section, so that at run-time the bytes start off zeroed. Since
503 @var{symbol} is not declared global, it is normally not visible to
504 @code{@value{LD}}. The optional third parameter, @var{alignment},
505 specifies the desired alignment of the symbol in the bss section.
506
507 This directive is only available for COFF based x86 targets.
508
509 @cindex @code{largecomm} directive, ELF
510 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
511 This directive behaves in the same way as the @code{comm} directive
512 except that the data is placed into the @var{.lbss} section instead of
513 the @var{.bss} section @ref{Comm}.
514
515 The directive is intended to be used for data which requires a large
516 amount of space, and it is only available for ELF based x86_64
517 targets.
518
519 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
520
521 @end table
522
523 @node i386-Syntax
524 @section i386 Syntactical Considerations
525 @menu
526 * i386-Variations:: AT&T Syntax versus Intel Syntax
527 * i386-Chars:: Special Characters
528 @end menu
529
530 @node i386-Variations
531 @subsection AT&T Syntax versus Intel Syntax
532
533 @cindex i386 intel_syntax pseudo op
534 @cindex intel_syntax pseudo op, i386
535 @cindex i386 att_syntax pseudo op
536 @cindex att_syntax pseudo op, i386
537 @cindex i386 syntax compatibility
538 @cindex syntax compatibility, i386
539 @cindex x86-64 intel_syntax pseudo op
540 @cindex intel_syntax pseudo op, x86-64
541 @cindex x86-64 att_syntax pseudo op
542 @cindex att_syntax pseudo op, x86-64
543 @cindex x86-64 syntax compatibility
544 @cindex syntax compatibility, x86-64
545
546 @code{@value{AS}} now supports assembly using Intel assembler syntax.
547 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
548 back to the usual AT&T mode for compatibility with the output of
549 @code{@value{GCC}}. Either of these directives may have an optional
550 argument, @code{prefix}, or @code{noprefix} specifying whether registers
551 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
552 different from Intel syntax. We mention these differences because
553 almost all 80386 documents use Intel syntax. Notable differences
554 between the two syntaxes are:
555
556 @cindex immediate operands, i386
557 @cindex i386 immediate operands
558 @cindex register operands, i386
559 @cindex i386 register operands
560 @cindex jump/call operands, i386
561 @cindex i386 jump/call operands
562 @cindex operand delimiters, i386
563
564 @cindex immediate operands, x86-64
565 @cindex x86-64 immediate operands
566 @cindex register operands, x86-64
567 @cindex x86-64 register operands
568 @cindex jump/call operands, x86-64
569 @cindex x86-64 jump/call operands
570 @cindex operand delimiters, x86-64
571 @itemize @bullet
572 @item
573 AT&T immediate operands are preceded by @samp{$}; Intel immediate
574 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
575 AT&T register operands are preceded by @samp{%}; Intel register operands
576 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
577 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
578
579 @cindex i386 source, destination operands
580 @cindex source, destination operands; i386
581 @cindex x86-64 source, destination operands
582 @cindex source, destination operands; x86-64
583 @item
584 AT&T and Intel syntax use the opposite order for source and destination
585 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
586 @samp{source, dest} convention is maintained for compatibility with
587 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
588 instructions with 2 immediate operands, such as the @samp{enter}
589 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
590
591 @cindex mnemonic suffixes, i386
592 @cindex sizes operands, i386
593 @cindex i386 size suffixes
594 @cindex mnemonic suffixes, x86-64
595 @cindex sizes operands, x86-64
596 @cindex x86-64 size suffixes
597 @item
598 In AT&T syntax the size of memory operands is determined from the last
599 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
600 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
601 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
602 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
603 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
604 no other way to disambiguate an instruction. Intel syntax accomplishes this by
605 prefixing memory operands (@emph{not} the instruction mnemonics) with
606 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
607 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
608 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
609 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
610 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
611
612 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
613 instruction with the 64-bit displacement or immediate operand.
614
615 @cindex return instructions, i386
616 @cindex i386 jump, call, return
617 @cindex return instructions, x86-64
618 @cindex x86-64 jump, call, return
619 @item
620 Immediate form long jumps and calls are
621 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
622 Intel syntax is
623 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
624 instruction
625 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
626 @samp{ret far @var{stack-adjust}}.
627
628 @cindex sections, i386
629 @cindex i386 sections
630 @cindex sections, x86-64
631 @cindex x86-64 sections
632 @item
633 The AT&T assembler does not provide support for multiple section
634 programs. Unix style systems expect all programs to be single sections.
635 @end itemize
636
637 @node i386-Chars
638 @subsection Special Characters
639
640 @cindex line comment character, i386
641 @cindex i386 line comment character
642 The presence of a @samp{#} appearing anywhere on a line indicates the
643 start of a comment that extends to the end of that line.
644
645 If a @samp{#} appears as the first character of a line then the whole
646 line is treated as a comment, but in this case the line can also be a
647 logical line number directive (@pxref{Comments}) or a preprocessor
648 control command (@pxref{Preprocessing}).
649
650 If the @option{--divide} command-line option has not been specified
651 then the @samp{/} character appearing anywhere on a line also
652 introduces a line comment.
653
654 @cindex line separator, i386
655 @cindex statement separator, i386
656 @cindex i386 line separator
657 The @samp{;} character can be used to separate statements on the same
658 line.
659
660 @node i386-Mnemonics
661 @section i386-Mnemonics
662 @subsection Instruction Naming
663
664 @cindex i386 instruction naming
665 @cindex instruction naming, i386
666 @cindex x86-64 instruction naming
667 @cindex instruction naming, x86-64
668
669 Instruction mnemonics are suffixed with one character modifiers which
670 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
671 and @samp{q} specify byte, word, long and quadruple word operands. If
672 no suffix is specified by an instruction then @code{@value{AS}} tries to
673 fill in the missing suffix based on the destination register operand
674 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
675 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
676 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
677 assembler which assumes that a missing mnemonic suffix implies long
678 operand size. (This incompatibility does not affect compiler output
679 since compilers always explicitly specify the mnemonic suffix.)
680
681 Almost all instructions have the same names in AT&T and Intel format.
682 There are a few exceptions. The sign extend and zero extend
683 instructions need two sizes to specify them. They need a size to
684 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
685 is accomplished by using two instruction mnemonic suffixes in AT&T
686 syntax. Base names for sign extend and zero extend are
687 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
688 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
689 are tacked on to this base name, the @emph{from} suffix before the
690 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
691 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
692 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
693 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
694 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
695 quadruple word).
696
697 @cindex encoding options, i386
698 @cindex encoding options, x86-64
699
700 Different encoding options can be specified via pseudo prefixes:
701
702 @itemize @bullet
703 @item
704 @samp{@{disp8@}} -- prefer 8-bit displacement.
705
706 @item
707 @samp{@{disp32@}} -- prefer 32-bit displacement.
708
709 @item
710 @samp{@{load@}} -- prefer load-form instruction.
711
712 @item
713 @samp{@{store@}} -- prefer store-form instruction.
714
715 @item
716 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
717
718 @item
719 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
720
721 @item
722 @samp{@{evex@}} -- encode with EVEX prefix.
723
724 @item
725 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
726 instructions (x86-64 only). Note that this differs from the @samp{rex}
727 prefix which generates REX prefix unconditionally.
728
729 @item
730 @samp{@{nooptimize@}} -- disable instruction size optimization.
731 @end itemize
732
733 @cindex conversion instructions, i386
734 @cindex i386 conversion instructions
735 @cindex conversion instructions, x86-64
736 @cindex x86-64 conversion instructions
737 The Intel-syntax conversion instructions
738
739 @itemize @bullet
740 @item
741 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
742
743 @item
744 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
745
746 @item
747 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
748
749 @item
750 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
751
752 @item
753 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
754 (x86-64 only),
755
756 @item
757 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
758 @samp{%rdx:%rax} (x86-64 only),
759 @end itemize
760
761 @noindent
762 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
763 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
764 instructions.
765
766 @cindex jump instructions, i386
767 @cindex call instructions, i386
768 @cindex jump instructions, x86-64
769 @cindex call instructions, x86-64
770 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
771 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
772 convention.
773
774 @subsection AT&T Mnemonic versus Intel Mnemonic
775
776 @cindex i386 mnemonic compatibility
777 @cindex mnemonic compatibility, i386
778
779 @code{@value{AS}} supports assembly using Intel mnemonic.
780 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
781 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
782 syntax for compatibility with the output of @code{@value{GCC}}.
783 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
784 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
785 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
786 assembler with different mnemonics from those in Intel IA32 specification.
787 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
788
789 @node i386-Regs
790 @section Register Naming
791
792 @cindex i386 registers
793 @cindex registers, i386
794 @cindex x86-64 registers
795 @cindex registers, x86-64
796 Register operands are always prefixed with @samp{%}. The 80386 registers
797 consist of
798
799 @itemize @bullet
800 @item
801 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
802 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
803 frame pointer), and @samp{%esp} (the stack pointer).
804
805 @item
806 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
807 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
808
809 @item
810 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
811 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
812 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
813 @samp{%cx}, and @samp{%dx})
814
815 @item
816 the 6 section registers @samp{%cs} (code section), @samp{%ds}
817 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
818 and @samp{%gs}.
819
820 @item
821 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
822 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
823
824 @item
825 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
826 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
827
828 @item
829 the 2 test registers @samp{%tr6} and @samp{%tr7}.
830
831 @item
832 the 8 floating point register stack @samp{%st} or equivalently
833 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
834 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
835 These registers are overloaded by 8 MMX registers @samp{%mm0},
836 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
837 @samp{%mm6} and @samp{%mm7}.
838
839 @item
840 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
841 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
842 @end itemize
843
844 The AMD x86-64 architecture extends the register set by:
845
846 @itemize @bullet
847 @item
848 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
849 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
850 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
851 pointer)
852
853 @item
854 the 8 extended registers @samp{%r8}--@samp{%r15}.
855
856 @item
857 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
858
859 @item
860 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
861
862 @item
863 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
864
865 @item
866 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
867
868 @item
869 the 8 debug registers: @samp{%db8}--@samp{%db15}.
870
871 @item
872 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
873 @end itemize
874
875 With the AVX extensions more registers were made available:
876
877 @itemize @bullet
878
879 @item
880 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
881 available in 32-bit mode). The bottom 128 bits are overlaid with the
882 @samp{xmm0}--@samp{xmm15} registers.
883
884 @end itemize
885
886 The AVX2 extensions made in 64-bit mode more registers available:
887
888 @itemize @bullet
889
890 @item
891 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
892 registers @samp{%ymm16}--@samp{%ymm31}.
893
894 @end itemize
895
896 The AVX512 extensions added the following registers:
897
898 @itemize @bullet
899
900 @item
901 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
902 available in 32-bit mode). The bottom 128 bits are overlaid with the
903 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
904 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
905
906 @item
907 the 8 mask registers @samp{%k0}--@samp{%k7}.
908
909 @end itemize
910
911 @node i386-Prefixes
912 @section Instruction Prefixes
913
914 @cindex i386 instruction prefixes
915 @cindex instruction prefixes, i386
916 @cindex prefixes, i386
917 Instruction prefixes are used to modify the following instruction. They
918 are used to repeat string instructions, to provide section overrides, to
919 perform bus lock operations, and to change operand and address sizes.
920 (Most instructions that normally operate on 32-bit operands will use
921 16-bit operands if the instruction has an ``operand size'' prefix.)
922 Instruction prefixes are best written on the same line as the instruction
923 they act upon. For example, the @samp{scas} (scan string) instruction is
924 repeated with:
925
926 @smallexample
927 repne scas %es:(%edi),%al
928 @end smallexample
929
930 You may also place prefixes on the lines immediately preceding the
931 instruction, but this circumvents checks that @code{@value{AS}} does
932 with prefixes, and will not work with all prefixes.
933
934 Here is a list of instruction prefixes:
935
936 @cindex section override prefixes, i386
937 @itemize @bullet
938 @item
939 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
940 @samp{fs}, @samp{gs}. These are automatically added by specifying
941 using the @var{section}:@var{memory-operand} form for memory references.
942
943 @cindex size prefixes, i386
944 @item
945 Operand/Address size prefixes @samp{data16} and @samp{addr16}
946 change 32-bit operands/addresses into 16-bit operands/addresses,
947 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
948 @code{.code16} section) into 32-bit operands/addresses. These prefixes
949 @emph{must} appear on the same line of code as the instruction they
950 modify. For example, in a 16-bit @code{.code16} section, you might
951 write:
952
953 @smallexample
954 addr32 jmpl *(%ebx)
955 @end smallexample
956
957 @cindex bus lock prefixes, i386
958 @cindex inhibiting interrupts, i386
959 @item
960 The bus lock prefix @samp{lock} inhibits interrupts during execution of
961 the instruction it precedes. (This is only valid with certain
962 instructions; see a 80386 manual for details).
963
964 @cindex coprocessor wait, i386
965 @item
966 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
967 complete the current instruction. This should never be needed for the
968 80386/80387 combination.
969
970 @cindex repeat prefixes, i386
971 @item
972 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
973 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
974 times if the current address size is 16-bits).
975 @cindex REX prefixes, i386
976 @item
977 The @samp{rex} family of prefixes is used by x86-64 to encode
978 extensions to i386 instruction set. The @samp{rex} prefix has four
979 bits --- an operand size overwrite (@code{64}) used to change operand size
980 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
981 register set.
982
983 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
984 instruction emits @samp{rex} prefix with all the bits set. By omitting
985 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
986 prefixes as well. Normally, there is no need to write the prefixes
987 explicitly, since gas will automatically generate them based on the
988 instruction operands.
989 @end itemize
990
991 @node i386-Memory
992 @section Memory References
993
994 @cindex i386 memory references
995 @cindex memory references, i386
996 @cindex x86-64 memory references
997 @cindex memory references, x86-64
998 An Intel syntax indirect memory reference of the form
999
1000 @smallexample
1001 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1002 @end smallexample
1003
1004 @noindent
1005 is translated into the AT&T syntax
1006
1007 @smallexample
1008 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1009 @end smallexample
1010
1011 @noindent
1012 where @var{base} and @var{index} are the optional 32-bit base and
1013 index registers, @var{disp} is the optional displacement, and
1014 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1015 to calculate the address of the operand. If no @var{scale} is
1016 specified, @var{scale} is taken to be 1. @var{section} specifies the
1017 optional section register for the memory operand, and may override the
1018 default section register (see a 80386 manual for section register
1019 defaults). Note that section overrides in AT&T syntax @emph{must}
1020 be preceded by a @samp{%}. If you specify a section override which
1021 coincides with the default section register, @code{@value{AS}} does @emph{not}
1022 output any section register override prefixes to assemble the given
1023 instruction. Thus, section overrides can be specified to emphasize which
1024 section register is used for a given memory operand.
1025
1026 Here are some examples of Intel and AT&T style memory references:
1027
1028 @table @asis
1029 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1030 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1031 missing, and the default section is used (@samp{%ss} for addressing with
1032 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1033
1034 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1035 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1036 @samp{foo}. All other fields are missing. The section register here
1037 defaults to @samp{%ds}.
1038
1039 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1040 This uses the value pointed to by @samp{foo} as a memory operand.
1041 Note that @var{base} and @var{index} are both missing, but there is only
1042 @emph{one} @samp{,}. This is a syntactic exception.
1043
1044 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1045 This selects the contents of the variable @samp{foo} with section
1046 register @var{section} being @samp{%gs}.
1047 @end table
1048
1049 Absolute (as opposed to PC relative) call and jump operands must be
1050 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1051 always chooses PC relative addressing for jump/call labels.
1052
1053 Any instruction that has a memory operand, but no register operand,
1054 @emph{must} specify its size (byte, word, long, or quadruple) with an
1055 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1056 respectively).
1057
1058 The x86-64 architecture adds an RIP (instruction pointer relative)
1059 addressing. This addressing mode is specified by using @samp{rip} as a
1060 base register. Only constant offsets are valid. For example:
1061
1062 @table @asis
1063 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1064 Points to the address 1234 bytes past the end of the current
1065 instruction.
1066
1067 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1068 Points to the @code{symbol} in RIP relative way, this is shorter than
1069 the default absolute addressing.
1070 @end table
1071
1072 Other addressing modes remain unchanged in x86-64 architecture, except
1073 registers used are 64-bit instead of 32-bit.
1074
1075 @node i386-Jumps
1076 @section Handling of Jump Instructions
1077
1078 @cindex jump optimization, i386
1079 @cindex i386 jump optimization
1080 @cindex jump optimization, x86-64
1081 @cindex x86-64 jump optimization
1082 Jump instructions are always optimized to use the smallest possible
1083 displacements. This is accomplished by using byte (8-bit) displacement
1084 jumps whenever the target is sufficiently close. If a byte displacement
1085 is insufficient a long displacement is used. We do not support
1086 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1087 instruction with the @samp{data16} instruction prefix), since the 80386
1088 insists upon masking @samp{%eip} to 16 bits after the word displacement
1089 is added. (See also @pxref{i386-Arch})
1090
1091 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1092 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1093 displacements, so that if you use these instructions (@code{@value{GCC}} does
1094 not use them) you may get an error message (and incorrect code). The AT&T
1095 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1096 to
1097
1098 @smallexample
1099 jcxz cx_zero
1100 jmp cx_nonzero
1101 cx_zero: jmp foo
1102 cx_nonzero:
1103 @end smallexample
1104
1105 @node i386-Float
1106 @section Floating Point
1107
1108 @cindex i386 floating point
1109 @cindex floating point, i386
1110 @cindex x86-64 floating point
1111 @cindex floating point, x86-64
1112 All 80387 floating point types except packed BCD are supported.
1113 (BCD support may be added without much difficulty). These data
1114 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1115 double (64-bit), and extended (80-bit) precision floating point.
1116 Each supported type has an instruction mnemonic suffix and a constructor
1117 associated with it. Instruction mnemonic suffixes specify the operand's
1118 data type. Constructors build these data types into memory.
1119
1120 @cindex @code{float} directive, i386
1121 @cindex @code{single} directive, i386
1122 @cindex @code{double} directive, i386
1123 @cindex @code{tfloat} directive, i386
1124 @cindex @code{float} directive, x86-64
1125 @cindex @code{single} directive, x86-64
1126 @cindex @code{double} directive, x86-64
1127 @cindex @code{tfloat} directive, x86-64
1128 @itemize @bullet
1129 @item
1130 Floating point constructors are @samp{.float} or @samp{.single},
1131 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1132 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1133 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1134 only supports this format via the @samp{fldt} (load 80-bit real to stack
1135 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1136
1137 @cindex @code{word} directive, i386
1138 @cindex @code{long} directive, i386
1139 @cindex @code{int} directive, i386
1140 @cindex @code{quad} directive, i386
1141 @cindex @code{word} directive, x86-64
1142 @cindex @code{long} directive, x86-64
1143 @cindex @code{int} directive, x86-64
1144 @cindex @code{quad} directive, x86-64
1145 @item
1146 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1147 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1148 corresponding instruction mnemonic suffixes are @samp{s} (single),
1149 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1150 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1151 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1152 stack) instructions.
1153 @end itemize
1154
1155 Register to register operations should not use instruction mnemonic suffixes.
1156 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1157 wrote @samp{fst %st, %st(1)}, since all register to register operations
1158 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1159 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1160 then stores the result in the 4 byte location @samp{mem})
1161
1162 @node i386-SIMD
1163 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1164
1165 @cindex MMX, i386
1166 @cindex 3DNow!, i386
1167 @cindex SIMD, i386
1168 @cindex MMX, x86-64
1169 @cindex 3DNow!, x86-64
1170 @cindex SIMD, x86-64
1171
1172 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1173 instructions for integer data), available on Intel's Pentium MMX
1174 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1175 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1176 instruction set (SIMD instructions for 32-bit floating point data)
1177 available on AMD's K6-2 processor and possibly others in the future.
1178
1179 Currently, @code{@value{AS}} does not support Intel's floating point
1180 SIMD, Katmai (KNI).
1181
1182 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1183 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1184 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1185 floating point values. The MMX registers cannot be used at the same time
1186 as the floating point stack.
1187
1188 See Intel and AMD documentation, keeping in mind that the operand order in
1189 instructions is reversed from the Intel syntax.
1190
1191 @node i386-LWP
1192 @section AMD's Lightweight Profiling Instructions
1193
1194 @cindex LWP, i386
1195 @cindex LWP, x86-64
1196
1197 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1198 instruction set, available on AMD's Family 15h (Orochi) processors.
1199
1200 LWP enables applications to collect and manage performance data, and
1201 react to performance events. The collection of performance data
1202 requires no context switches. LWP runs in the context of a thread and
1203 so several counters can be used independently across multiple threads.
1204 LWP can be used in both 64-bit and legacy 32-bit modes.
1205
1206 For detailed information on the LWP instruction set, see the
1207 @cite{AMD Lightweight Profiling Specification} available at
1208 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1209
1210 @node i386-BMI
1211 @section Bit Manipulation Instructions
1212
1213 @cindex BMI, i386
1214 @cindex BMI, x86-64
1215
1216 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1217
1218 BMI instructions provide several instructions implementing individual
1219 bit manipulation operations such as isolation, masking, setting, or
1220 resetting.
1221
1222 @c Need to add a specification citation here when available.
1223
1224 @node i386-TBM
1225 @section AMD's Trailing Bit Manipulation Instructions
1226
1227 @cindex TBM, i386
1228 @cindex TBM, x86-64
1229
1230 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1231 instruction set, available on AMD's BDVER2 processors (Trinity and
1232 Viperfish).
1233
1234 TBM instructions provide instructions implementing individual bit
1235 manipulation operations such as isolating, masking, setting, resetting,
1236 complementing, and operations on trailing zeros and ones.
1237
1238 @c Need to add a specification citation here when available.
1239
1240 @node i386-16bit
1241 @section Writing 16-bit Code
1242
1243 @cindex i386 16-bit code
1244 @cindex 16-bit code, i386
1245 @cindex real-mode code, i386
1246 @cindex @code{code16gcc} directive, i386
1247 @cindex @code{code16} directive, i386
1248 @cindex @code{code32} directive, i386
1249 @cindex @code{code64} directive, i386
1250 @cindex @code{code64} directive, x86-64
1251 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1252 or 64-bit x86-64 code depending on the default configuration,
1253 it also supports writing code to run in real mode or in 16-bit protected
1254 mode code segments. To do this, put a @samp{.code16} or
1255 @samp{.code16gcc} directive before the assembly language instructions to
1256 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1257 32-bit code with the @samp{.code32} directive or 64-bit code with the
1258 @samp{.code64} directive.
1259
1260 @samp{.code16gcc} provides experimental support for generating 16-bit
1261 code from gcc, and differs from @samp{.code16} in that @samp{call},
1262 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1263 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1264 default to 32-bit size. This is so that the stack pointer is
1265 manipulated in the same way over function calls, allowing access to
1266 function parameters at the same stack offsets as in 32-bit mode.
1267 @samp{.code16gcc} also automatically adds address size prefixes where
1268 necessary to use the 32-bit addressing modes that gcc generates.
1269
1270 The code which @code{@value{AS}} generates in 16-bit mode will not
1271 necessarily run on a 16-bit pre-80386 processor. To write code that
1272 runs on such a processor, you must refrain from using @emph{any} 32-bit
1273 constructs which require @code{@value{AS}} to output address or operand
1274 size prefixes.
1275
1276 Note that writing 16-bit code instructions by explicitly specifying a
1277 prefix or an instruction mnemonic suffix within a 32-bit code section
1278 generates different machine instructions than those generated for a
1279 16-bit code segment. In a 32-bit code section, the following code
1280 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1281 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1282
1283 @smallexample
1284 pushw $4
1285 @end smallexample
1286
1287 The same code in a 16-bit code section would generate the machine
1288 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1289 is correct since the processor default operand size is assumed to be 16
1290 bits in a 16-bit code section.
1291
1292 @node i386-Arch
1293 @section Specifying CPU Architecture
1294
1295 @cindex arch directive, i386
1296 @cindex i386 arch directive
1297 @cindex arch directive, x86-64
1298 @cindex x86-64 arch directive
1299
1300 @code{@value{AS}} may be told to assemble for a particular CPU
1301 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1302 directive enables a warning when gas detects an instruction that is not
1303 supported on the CPU specified. The choices for @var{cpu_type} are:
1304
1305 @multitable @columnfractions .20 .20 .20 .20
1306 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1307 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1308 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1309 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1310 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1311 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1312 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1313 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1314 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1315 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1316 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1317 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1318 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1319 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1320 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1321 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1322 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1323 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1324 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1325 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1326 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1327 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1328 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1329 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1330 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1331 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1332 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1333 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1334 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
1335 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1336 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1337 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1338 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1339 @end multitable
1340
1341 Apart from the warning, there are only two other effects on
1342 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1343 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1344 will automatically use a two byte opcode sequence. The larger three
1345 byte opcode sequence is used on the 486 (and when no architecture is
1346 specified) because it executes faster on the 486. Note that you can
1347 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1348 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1349 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1350 conditional jumps will be promoted when necessary to a two instruction
1351 sequence consisting of a conditional jump of the opposite sense around
1352 an unconditional jump to the target.
1353
1354 Following the CPU architecture (but not a sub-architecture, which are those
1355 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1356 control automatic promotion of conditional jumps. @samp{jumps} is the
1357 default, and enables jump promotion; All external jumps will be of the long
1358 variety, and file-local jumps will be promoted as necessary.
1359 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1360 byte offset jumps, and warns about file-local conditional jumps that
1361 @code{@value{AS}} promotes.
1362 Unconditional jumps are treated as for @samp{jumps}.
1363
1364 For example
1365
1366 @smallexample
1367 .arch i8086,nojumps
1368 @end smallexample
1369
1370 @node i386-Bugs
1371 @section AT&T Syntax bugs
1372
1373 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1374 assemblers, generate floating point instructions with reversed source
1375 and destination registers in certain cases. Unfortunately, gcc and
1376 possibly many other programs use this reversed syntax, so we're stuck
1377 with it.
1378
1379 For example
1380
1381 @smallexample
1382 fsub %st,%st(3)
1383 @end smallexample
1384 @noindent
1385 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1386 than the expected @samp{%st(3) - %st}. This happens with all the
1387 non-commutative arithmetic floating point operations with two register
1388 operands where the source register is @samp{%st} and the destination
1389 register is @samp{%st(i)}.
1390
1391 @node i386-Notes
1392 @section Notes
1393
1394 @cindex i386 @code{mul}, @code{imul} instructions
1395 @cindex @code{mul} instruction, i386
1396 @cindex @code{imul} instruction, i386
1397 @cindex @code{mul} instruction, x86-64
1398 @cindex @code{imul} instruction, x86-64
1399 There is some trickery concerning the @samp{mul} and @samp{imul}
1400 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1401 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1402 for @samp{imul}) can be output only in the one operand form. Thus,
1403 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1404 the expanding multiply would clobber the @samp{%edx} register, and this
1405 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1406 64-bit product in @samp{%edx:%eax}.
1407
1408 We have added a two operand form of @samp{imul} when the first operand
1409 is an immediate mode expression and the second operand is a register.
1410 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1411 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
1412 $69, %eax, %eax}.
1413