1 @c Copyright (C) 1991-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-ISA:: AMD64 ISA vs. Intel64 ISA
41 * i386-Bugs:: AT&T Syntax bugs
48 @cindex options for i386
49 @cindex options for x86-64
51 @cindex x86-64 options
53 The i386 version of @code{@value{AS}} has a few machine
58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
64 @item --32 | --x32 | --64
65 Select the word size, either 32 bits or 64 bits. @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
67 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
70 These options are only available with the ELF object file format, and
71 require that the necessary BFD support has been included (on a 32-bit
72 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
73 usage and use x86-64 as target platform).
76 By default, x86 GAS replaces multiple nop instructions used for
77 alignment within code sections with multi-byte nop instructions such
78 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
79 byte nop (0x90) is explicitly specified as the fill byte for alignment.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics. For example,
135 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
136 @var{vmx}. The following extensions are currently supported:
206 @code{avx512_4fmaps},
207 @code{avx512_4vnniw},
208 @code{avx512_vpopcntdq},
211 @code{avx512_bitalg},
212 @code{avx512_vp2intersect},
224 @code{noavx512_4fmaps},
225 @code{noavx512_4vnniw},
226 @code{noavx512_vpopcntdq},
227 @code{noavx512_vbmi2},
228 @code{noavx512_vnni},
229 @code{noavx512_bitalg},
230 @code{noavx512_vp2intersect},
232 @code{noavx512_bf16},
288 Note that rather than extending a basic instruction set, the extension
289 mnemonics starting with @code{no} revoke the respective functionality.
291 When the @code{.arch} directive is used with @option{-march}, the
292 @code{.arch} directive will take precedent.
294 @cindex @samp{-mtune=} option, i386
295 @cindex @samp{-mtune=} option, x86-64
296 @item -mtune=@var{CPU}
297 This option specifies a processor to optimize for. When used in
298 conjunction with the @option{-march} option, only instructions
299 of the processor specified by the @option{-march} option will be
302 Valid @var{CPU} values are identical to the processor list of
303 @option{-march=@var{CPU}}.
305 @cindex @samp{-msse2avx} option, i386
306 @cindex @samp{-msse2avx} option, x86-64
308 This option specifies that the assembler should encode SSE instructions
311 @cindex @samp{-msse-check=} option, i386
312 @cindex @samp{-msse-check=} option, x86-64
313 @item -msse-check=@var{none}
314 @itemx -msse-check=@var{warning}
315 @itemx -msse-check=@var{error}
316 These options control if the assembler should check SSE instructions.
317 @option{-msse-check=@var{none}} will make the assembler not to check SSE
318 instructions, which is the default. @option{-msse-check=@var{warning}}
319 will make the assembler issue a warning for any SSE instruction.
320 @option{-msse-check=@var{error}} will make the assembler issue an error
321 for any SSE instruction.
323 @cindex @samp{-mavxscalar=} option, i386
324 @cindex @samp{-mavxscalar=} option, x86-64
325 @item -mavxscalar=@var{128}
326 @itemx -mavxscalar=@var{256}
327 These options control how the assembler should encode scalar AVX
328 instructions. @option{-mavxscalar=@var{128}} will encode scalar
329 AVX instructions with 128bit vector length, which is the default.
330 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
331 with 256bit vector length.
333 WARNING: Don't use this for production code - due to CPU errata the
334 resulting code may not work on certain models.
336 @cindex @samp{-mvexwig=} option, i386
337 @cindex @samp{-mvexwig=} option, x86-64
338 @item -mvexwig=@var{0}
339 @itemx -mvexwig=@var{1}
340 These options control how the assembler should encode VEX.W-ignored (WIG)
341 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
342 instructions with vex.w = 0, which is the default.
343 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
346 WARNING: Don't use this for production code - due to CPU errata the
347 resulting code may not work on certain models.
349 @cindex @samp{-mevexlig=} option, i386
350 @cindex @samp{-mevexlig=} option, x86-64
351 @item -mevexlig=@var{128}
352 @itemx -mevexlig=@var{256}
353 @itemx -mevexlig=@var{512}
354 These options control how the assembler should encode length-ignored
355 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
356 EVEX instructions with 128bit vector length, which is the default.
357 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
358 encode LIG EVEX instructions with 256bit and 512bit vector length,
361 @cindex @samp{-mevexwig=} option, i386
362 @cindex @samp{-mevexwig=} option, x86-64
363 @item -mevexwig=@var{0}
364 @itemx -mevexwig=@var{1}
365 These options control how the assembler should encode w-ignored (WIG)
366 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
367 EVEX instructions with evex.w = 0, which is the default.
368 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
371 @cindex @samp{-mmnemonic=} option, i386
372 @cindex @samp{-mmnemonic=} option, x86-64
373 @item -mmnemonic=@var{att}
374 @itemx -mmnemonic=@var{intel}
375 This option specifies instruction mnemonic for matching instructions.
376 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
379 @cindex @samp{-msyntax=} option, i386
380 @cindex @samp{-msyntax=} option, x86-64
381 @item -msyntax=@var{att}
382 @itemx -msyntax=@var{intel}
383 This option specifies instruction syntax when processing instructions.
384 The @code{.att_syntax} and @code{.intel_syntax} directives will
387 @cindex @samp{-mnaked-reg} option, i386
388 @cindex @samp{-mnaked-reg} option, x86-64
390 This option specifies that registers don't require a @samp{%} prefix.
391 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
393 @cindex @samp{-madd-bnd-prefix} option, i386
394 @cindex @samp{-madd-bnd-prefix} option, x86-64
395 @item -madd-bnd-prefix
396 This option forces the assembler to add BND prefix to all branches, even
397 if such prefix was not explicitly specified in the source code.
399 @cindex @samp{-mshared} option, i386
400 @cindex @samp{-mshared} option, x86-64
402 On ELF target, the assembler normally optimizes out non-PLT relocations
403 against defined non-weak global branch targets with default visibility.
404 The @samp{-mshared} option tells the assembler to generate code which
405 may go into a shared library where all non-weak global branch targets
406 with default visibility can be preempted. The resulting code is
407 slightly bigger. This option only affects the handling of branch
410 @cindex @samp{-mbig-obj} option, i386
411 @cindex @samp{-mbig-obj} option, x86-64
413 On PE/COFF target this option forces the use of big object file
414 format, which allows more than 32768 sections.
416 @cindex @samp{-momit-lock-prefix=} option, i386
417 @cindex @samp{-momit-lock-prefix=} option, x86-64
418 @item -momit-lock-prefix=@var{no}
419 @itemx -momit-lock-prefix=@var{yes}
420 These options control how the assembler should encode lock prefix.
421 This option is intended as a workaround for processors, that fail on
422 lock prefix. This option can only be safely used with single-core,
423 single-thread computers
424 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
425 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
426 which is the default.
428 @cindex @samp{-mfence-as-lock-add=} option, i386
429 @cindex @samp{-mfence-as-lock-add=} option, x86-64
430 @item -mfence-as-lock-add=@var{no}
431 @itemx -mfence-as-lock-add=@var{yes}
432 These options control how the assembler should encode lfence, mfence and
434 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
435 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
436 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
437 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
438 sfence as usual, which is the default.
440 @cindex @samp{-mrelax-relocations=} option, i386
441 @cindex @samp{-mrelax-relocations=} option, x86-64
442 @item -mrelax-relocations=@var{no}
443 @itemx -mrelax-relocations=@var{yes}
444 These options control whether the assembler should generate relax
445 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
446 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
447 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
448 @option{-mrelax-relocations=@var{no}} will not generate relax
449 relocations. The default can be controlled by a configure option
450 @option{--enable-x86-relax-relocations}.
452 @cindex @samp{-malign-branch-boundary=} option, i386
453 @cindex @samp{-malign-branch-boundary=} option, x86-64
454 @item -malign-branch-boundary=@var{NUM}
455 This option controls how the assembler should align branches with segment
456 prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or
457 no less than 16. Branches will be aligned within @var{NUM} byte
458 boundary. @option{-malign-branch-boundary=0}, which is the default,
459 doesn't align branches.
461 @cindex @samp{-malign-branch=} option, i386
462 @cindex @samp{-malign-branch=} option, x86-64
463 @item -malign-branch=@var{TYPE}[+@var{TYPE}...]
464 This option specifies types of branches to align. @var{TYPE} is
465 combination of @samp{jcc}, which aligns conditional jumps,
466 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
467 which aligns unconditional jumps, @samp{call} which aligns calls,
468 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
469 jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}.
471 @cindex @samp{-malign-branch-prefix-size=} option, i386
472 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
473 @item -malign-branch-prefix-size=@var{NUM}
474 This option specifies the maximum number of prefixes on an instruction
475 to align branches. @var{NUM} should be between 0 and 5. The default
478 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
479 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
480 @item -mbranches-within-32B-boundaries
481 This option aligns conditional jumps, fused conditional jumps and
482 unconditional jumps within 32 byte boundary with up to 5 segment prefixes
483 on an instruction. It is equivalent to
484 @option{-malign-branch-boundary=32}
485 @option{-malign-branch=jcc+fused+jmp}
486 @option{-malign-branch-prefix-size=5}.
487 The default doesn't align branches.
489 @cindex @samp{-mlfence-after-load=} option, i386
490 @cindex @samp{-mlfence-after-load=} option, x86-64
491 @item -mlfence-after-load=@var{no}
492 @itemx -mlfence-after-load=@var{yes}
493 These options control whether the assembler should generate lfence
494 after load instructions. @option{-mlfence-after-load=@var{yes}} will
495 generate lfence. @option{-mlfence-after-load=@var{no}} will not generate
496 lfence, which is the default.
498 @cindex @samp{-mlfence-before-indirect-branch=} option, i386
499 @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
500 @item -mlfence-before-indirect-branch=@var{none}
501 @item -mlfence-before-indirect-branch=@var{all}
502 @item -mlfence-before-indirect-branch=@var{register}
503 @itemx -mlfence-before-indirect-branch=@var{memory}
504 These options control whether the assembler should generate lfence
505 before indirect near branch instructions.
506 @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
507 before indirect near branch via register and issue a warning before
508 indirect near branch via memory.
509 It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when
510 there's no explict @option{-mlfence-before-ret=}.
511 @option{-mlfence-before-indirect-branch=@var{register}} will generate
512 lfence before indirect near branch via register.
513 @option{-mlfence-before-indirect-branch=@var{memory}} will issue a
514 warning before indirect near branch via memory.
515 @option{-mlfence-before-indirect-branch=@var{none}} will not generate
516 lfence nor issue warning, which is the default. Note that lfence won't
517 be generated before indirect near branch via register with
518 @option{-mlfence-after-load=@var{yes}} since lfence will be generated
519 after loading branch target register.
521 @cindex @samp{-mlfence-before-ret=} option, i386
522 @cindex @samp{-mlfence-before-ret=} option, x86-64
523 @item -mlfence-before-ret=@var{none}
524 @item -mlfence-before-ret=@var{shl}
525 @item -mlfence-before-ret=@var{or}
526 @item -mlfence-before-ret=@var{yes}
527 @itemx -mlfence-before-ret=@var{not}
528 These options control whether the assembler should generate lfence
529 before ret. @option{-mlfence-before-ret=@var{or}} will generate
530 generate or instruction with lfence.
531 @option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction
532 with lfence. @option{-mlfence-before-ret=@var{not}} will generate not
533 instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not
534 generate lfence, which is the default.
536 @cindex @samp{-mx86-used-note=} option, i386
537 @cindex @samp{-mx86-used-note=} option, x86-64
538 @item -mx86-used-note=@var{no}
539 @itemx -mx86-used-note=@var{yes}
540 These options control whether the assembler should generate
541 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
542 GNU property notes. The default can be controlled by the
543 @option{--enable-x86-used-note} configure option.
545 @cindex @samp{-mevexrcig=} option, i386
546 @cindex @samp{-mevexrcig=} option, x86-64
547 @item -mevexrcig=@var{rne}
548 @itemx -mevexrcig=@var{rd}
549 @itemx -mevexrcig=@var{ru}
550 @itemx -mevexrcig=@var{rz}
551 These options control how the assembler should encode SAE-only
552 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
553 of EVEX instruction with 00, which is the default.
554 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
555 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
556 with 01, 10 and 11 RC bits, respectively.
558 @cindex @samp{-mamd64} option, x86-64
559 @cindex @samp{-mintel64} option, x86-64
562 This option specifies that the assembler should accept only AMD64 or
563 Intel64 ISA in 64-bit mode. The default is to accept common, Intel64
566 @cindex @samp{-O0} option, i386
567 @cindex @samp{-O0} option, x86-64
568 @cindex @samp{-O} option, i386
569 @cindex @samp{-O} option, x86-64
570 @cindex @samp{-O1} option, i386
571 @cindex @samp{-O1} option, x86-64
572 @cindex @samp{-O2} option, i386
573 @cindex @samp{-O2} option, x86-64
574 @cindex @samp{-Os} option, i386
575 @cindex @samp{-Os} option, x86-64
576 @item -O0 | -O | -O1 | -O2 | -Os
577 Optimize instruction encoding with smaller instruction size. @samp{-O}
578 and @samp{-O1} encode 64-bit register load instructions with 64-bit
579 immediate as 32-bit register load instructions with 31-bit or 32-bits
580 immediates, encode 64-bit register clearing instructions with 32-bit
581 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
582 register clearing instructions with 128-bit VEX vector register
583 clearing instructions, encode 128-bit/256-bit EVEX vector
584 register load/store instructions with VEX vector register load/store
585 instructions, and encode 128-bit/256-bit EVEX packed integer logical
586 instructions with 128-bit/256-bit VEX packed integer logical.
588 @samp{-O2} includes @samp{-O1} optimization plus encodes
589 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
590 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
591 instructions with commutative source operands will also have their
592 source operands swapped if this allows using the 2-byte VEX prefix form
593 instead of the 3-byte one. Certain forms of AND as well as OR with the
594 same (register) operand specified twice will also be changed to TEST.
596 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
597 and 64-bit register tests with immediate as 8-bit register test with
598 immediate. @samp{-O0} turns off this optimization.
603 @node i386-Directives
604 @section x86 specific Directives
606 @cindex machine directives, x86
607 @cindex x86 machine directives
610 @cindex @code{lcomm} directive, COFF
611 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
612 Reserve @var{length} (an absolute expression) bytes for a local common
613 denoted by @var{symbol}. The section and value of @var{symbol} are
614 those of the new local common. The addresses are allocated in the bss
615 section, so that at run-time the bytes start off zeroed. Since
616 @var{symbol} is not declared global, it is normally not visible to
617 @code{@value{LD}}. The optional third parameter, @var{alignment},
618 specifies the desired alignment of the symbol in the bss section.
620 This directive is only available for COFF based x86 targets.
622 @cindex @code{largecomm} directive, ELF
623 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
624 This directive behaves in the same way as the @code{comm} directive
625 except that the data is placed into the @var{.lbss} section instead of
626 the @var{.bss} section @ref{Comm}.
628 The directive is intended to be used for data which requires a large
629 amount of space, and it is only available for ELF based x86_64
632 @cindex @code{value} directive
633 @item .value @var{expression} [, @var{expression}]
634 This directive behaves in the same way as the @code{.short} directive,
635 taking a series of comma separated expressions and storing them as
636 two-byte wide values into the current section.
638 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
643 @section i386 Syntactical Considerations
645 * i386-Variations:: AT&T Syntax versus Intel Syntax
646 * i386-Chars:: Special Characters
649 @node i386-Variations
650 @subsection AT&T Syntax versus Intel Syntax
652 @cindex i386 intel_syntax pseudo op
653 @cindex intel_syntax pseudo op, i386
654 @cindex i386 att_syntax pseudo op
655 @cindex att_syntax pseudo op, i386
656 @cindex i386 syntax compatibility
657 @cindex syntax compatibility, i386
658 @cindex x86-64 intel_syntax pseudo op
659 @cindex intel_syntax pseudo op, x86-64
660 @cindex x86-64 att_syntax pseudo op
661 @cindex att_syntax pseudo op, x86-64
662 @cindex x86-64 syntax compatibility
663 @cindex syntax compatibility, x86-64
665 @code{@value{AS}} now supports assembly using Intel assembler syntax.
666 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
667 back to the usual AT&T mode for compatibility with the output of
668 @code{@value{GCC}}. Either of these directives may have an optional
669 argument, @code{prefix}, or @code{noprefix} specifying whether registers
670 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
671 different from Intel syntax. We mention these differences because
672 almost all 80386 documents use Intel syntax. Notable differences
673 between the two syntaxes are:
675 @cindex immediate operands, i386
676 @cindex i386 immediate operands
677 @cindex register operands, i386
678 @cindex i386 register operands
679 @cindex jump/call operands, i386
680 @cindex i386 jump/call operands
681 @cindex operand delimiters, i386
683 @cindex immediate operands, x86-64
684 @cindex x86-64 immediate operands
685 @cindex register operands, x86-64
686 @cindex x86-64 register operands
687 @cindex jump/call operands, x86-64
688 @cindex x86-64 jump/call operands
689 @cindex operand delimiters, x86-64
692 AT&T immediate operands are preceded by @samp{$}; Intel immediate
693 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
694 AT&T register operands are preceded by @samp{%}; Intel register operands
695 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
696 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
698 @cindex i386 source, destination operands
699 @cindex source, destination operands; i386
700 @cindex x86-64 source, destination operands
701 @cindex source, destination operands; x86-64
703 AT&T and Intel syntax use the opposite order for source and destination
704 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
705 @samp{source, dest} convention is maintained for compatibility with
706 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
707 instructions with 2 immediate operands, such as the @samp{enter}
708 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
710 @cindex mnemonic suffixes, i386
711 @cindex sizes operands, i386
712 @cindex i386 size suffixes
713 @cindex mnemonic suffixes, x86-64
714 @cindex sizes operands, x86-64
715 @cindex x86-64 size suffixes
717 In AT&T syntax the size of memory operands is determined from the last
718 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
719 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
720 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
721 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
722 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
723 no other way to disambiguate an instruction. Intel syntax accomplishes this by
724 prefixing memory operands (@emph{not} the instruction mnemonics) with
725 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
726 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
727 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
728 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
729 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
731 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
732 instruction with the 64-bit displacement or immediate operand.
734 @cindex return instructions, i386
735 @cindex i386 jump, call, return
736 @cindex return instructions, x86-64
737 @cindex x86-64 jump, call, return
739 Immediate form long jumps and calls are
740 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
742 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
744 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
745 @samp{ret far @var{stack-adjust}}.
747 @cindex sections, i386
748 @cindex i386 sections
749 @cindex sections, x86-64
750 @cindex x86-64 sections
752 The AT&T assembler does not provide support for multiple section
753 programs. Unix style systems expect all programs to be single sections.
757 @subsection Special Characters
759 @cindex line comment character, i386
760 @cindex i386 line comment character
761 The presence of a @samp{#} appearing anywhere on a line indicates the
762 start of a comment that extends to the end of that line.
764 If a @samp{#} appears as the first character of a line then the whole
765 line is treated as a comment, but in this case the line can also be a
766 logical line number directive (@pxref{Comments}) or a preprocessor
767 control command (@pxref{Preprocessing}).
769 If the @option{--divide} command-line option has not been specified
770 then the @samp{/} character appearing anywhere on a line also
771 introduces a line comment.
773 @cindex line separator, i386
774 @cindex statement separator, i386
775 @cindex i386 line separator
776 The @samp{;} character can be used to separate statements on the same
780 @section i386-Mnemonics
781 @subsection Instruction Naming
783 @cindex i386 instruction naming
784 @cindex instruction naming, i386
785 @cindex x86-64 instruction naming
786 @cindex instruction naming, x86-64
788 Instruction mnemonics are suffixed with one character modifiers which
789 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
790 and @samp{q} specify byte, word, long and quadruple word operands. If
791 no suffix is specified by an instruction then @code{@value{AS}} tries to
792 fill in the missing suffix based on the destination register operand
793 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
794 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
795 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
796 assembler which assumes that a missing mnemonic suffix implies long
797 operand size. (This incompatibility does not affect compiler output
798 since compilers always explicitly specify the mnemonic suffix.)
800 When there is no sizing suffix and no (suitable) register operands to
801 deduce the size of memory operands, with a few exceptions and where long
802 operand size is possible in the first place, operand size will default
803 to long in 32- and 64-bit modes. Similarly it will default to short in
804 16-bit mode. Noteworthy exceptions are
808 Instructions with an implicit on-stack operand as well as branches,
809 which default to quad in 64-bit mode.
812 Sign- and zero-extending moves, which default to byte size source
816 Floating point insns with integer operands, which default to short (for
817 perhaps historical reasons).
820 CRC32 with a 64-bit destination, which defaults to a quad source
825 @cindex encoding options, i386
826 @cindex encoding options, x86-64
828 Different encoding options can be specified via pseudo prefixes:
832 @samp{@{disp8@}} -- prefer 8-bit displacement.
835 @samp{@{disp32@}} -- prefer 32-bit displacement.
838 @samp{@{disp16@}} -- prefer 16-bit displacement.
841 @samp{@{load@}} -- prefer load-form instruction.
844 @samp{@{store@}} -- prefer store-form instruction.
847 @samp{@{vex@}} -- encode with VEX prefix.
850 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
853 @samp{@{evex@}} -- encode with EVEX prefix.
856 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
857 instructions (x86-64 only). Note that this differs from the @samp{rex}
858 prefix which generates REX prefix unconditionally.
861 @samp{@{nooptimize@}} -- disable instruction size optimization.
864 @cindex conversion instructions, i386
865 @cindex i386 conversion instructions
866 @cindex conversion instructions, x86-64
867 @cindex x86-64 conversion instructions
868 The Intel-syntax conversion instructions
872 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
875 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
878 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
881 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
884 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
888 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
889 @samp{%rdx:%rax} (x86-64 only),
893 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
894 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
897 @cindex extension instructions, i386
898 @cindex i386 extension instructions
899 @cindex extension instructions, x86-64
900 @cindex x86-64 extension instructions
901 The Intel-syntax extension instructions
905 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}.
908 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}.
911 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64}
915 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32}
918 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64}
922 @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64}
926 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}.
929 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}.
932 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64}
936 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32}
939 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64}
944 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
945 @samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
946 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
947 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
948 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
950 @cindex jump instructions, i386
951 @cindex call instructions, i386
952 @cindex jump instructions, x86-64
953 @cindex call instructions, x86-64
954 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
955 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
958 @subsection AT&T Mnemonic versus Intel Mnemonic
960 @cindex i386 mnemonic compatibility
961 @cindex mnemonic compatibility, i386
963 @code{@value{AS}} supports assembly using Intel mnemonic.
964 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
965 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
966 syntax for compatibility with the output of @code{@value{GCC}}.
967 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
968 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
969 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
970 assembler with different mnemonics from those in Intel IA32 specification.
971 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
974 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
975 register. @samp{movsxd} should be used to encode 16-bit or 32-bit
976 destination register with both AT&T and Intel mnemonics.
980 @section Register Naming
982 @cindex i386 registers
983 @cindex registers, i386
984 @cindex x86-64 registers
985 @cindex registers, x86-64
986 Register operands are always prefixed with @samp{%}. The 80386 registers
991 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
992 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
993 frame pointer), and @samp{%esp} (the stack pointer).
996 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
997 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
1000 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
1001 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
1002 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
1003 @samp{%cx}, and @samp{%dx})
1006 the 6 section registers @samp{%cs} (code section), @samp{%ds}
1007 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
1011 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
1012 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
1015 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
1016 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
1019 the 2 test registers @samp{%tr6} and @samp{%tr7}.
1022 the 8 floating point register stack @samp{%st} or equivalently
1023 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
1024 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
1025 These registers are overloaded by 8 MMX registers @samp{%mm0},
1026 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
1027 @samp{%mm6} and @samp{%mm7}.
1030 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
1031 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
1034 The AMD x86-64 architecture extends the register set by:
1038 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
1039 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
1040 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
1044 the 8 extended registers @samp{%r8}--@samp{%r15}.
1047 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
1050 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
1053 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
1056 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
1059 the 8 debug registers: @samp{%db8}--@samp{%db15}.
1062 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
1065 With the AVX extensions more registers were made available:
1070 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
1071 available in 32-bit mode). The bottom 128 bits are overlaid with the
1072 @samp{xmm0}--@samp{xmm15} registers.
1076 The AVX512 extensions added the following registers:
1081 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
1082 available in 32-bit mode). The bottom 128 bits are overlaid with the
1083 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
1084 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
1087 the 8 mask registers @samp{%k0}--@samp{%k7}.
1092 @section Instruction Prefixes
1094 @cindex i386 instruction prefixes
1095 @cindex instruction prefixes, i386
1096 @cindex prefixes, i386
1097 Instruction prefixes are used to modify the following instruction. They
1098 are used to repeat string instructions, to provide section overrides, to
1099 perform bus lock operations, and to change operand and address sizes.
1100 (Most instructions that normally operate on 32-bit operands will use
1101 16-bit operands if the instruction has an ``operand size'' prefix.)
1102 Instruction prefixes are best written on the same line as the instruction
1103 they act upon. For example, the @samp{scas} (scan string) instruction is
1107 repne scas %es:(%edi),%al
1110 You may also place prefixes on the lines immediately preceding the
1111 instruction, but this circumvents checks that @code{@value{AS}} does
1112 with prefixes, and will not work with all prefixes.
1114 Here is a list of instruction prefixes:
1116 @cindex section override prefixes, i386
1119 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1120 @samp{fs}, @samp{gs}. These are automatically added by specifying
1121 using the @var{section}:@var{memory-operand} form for memory references.
1123 @cindex size prefixes, i386
1125 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1126 change 32-bit operands/addresses into 16-bit operands/addresses,
1127 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1128 @code{.code16} section) into 32-bit operands/addresses. These prefixes
1129 @emph{must} appear on the same line of code as the instruction they
1130 modify. For example, in a 16-bit @code{.code16} section, you might
1137 @cindex bus lock prefixes, i386
1138 @cindex inhibiting interrupts, i386
1140 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1141 the instruction it precedes. (This is only valid with certain
1142 instructions; see a 80386 manual for details).
1144 @cindex coprocessor wait, i386
1146 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1147 complete the current instruction. This should never be needed for the
1148 80386/80387 combination.
1150 @cindex repeat prefixes, i386
1152 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1153 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1154 times if the current address size is 16-bits).
1155 @cindex REX prefixes, i386
1157 The @samp{rex} family of prefixes is used by x86-64 to encode
1158 extensions to i386 instruction set. The @samp{rex} prefix has four
1159 bits --- an operand size overwrite (@code{64}) used to change operand size
1160 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
1163 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1164 instruction emits @samp{rex} prefix with all the bits set. By omitting
1165 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
1166 prefixes as well. Normally, there is no need to write the prefixes
1167 explicitly, since gas will automatically generate them based on the
1168 instruction operands.
1172 @section Memory References
1174 @cindex i386 memory references
1175 @cindex memory references, i386
1176 @cindex x86-64 memory references
1177 @cindex memory references, x86-64
1178 An Intel syntax indirect memory reference of the form
1181 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1185 is translated into the AT&T syntax
1188 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1192 where @var{base} and @var{index} are the optional 32-bit base and
1193 index registers, @var{disp} is the optional displacement, and
1194 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1195 to calculate the address of the operand. If no @var{scale} is
1196 specified, @var{scale} is taken to be 1. @var{section} specifies the
1197 optional section register for the memory operand, and may override the
1198 default section register (see a 80386 manual for section register
1199 defaults). Note that section overrides in AT&T syntax @emph{must}
1200 be preceded by a @samp{%}. If you specify a section override which
1201 coincides with the default section register, @code{@value{AS}} does @emph{not}
1202 output any section register override prefixes to assemble the given
1203 instruction. Thus, section overrides can be specified to emphasize which
1204 section register is used for a given memory operand.
1206 Here are some examples of Intel and AT&T style memory references:
1209 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1210 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1211 missing, and the default section is used (@samp{%ss} for addressing with
1212 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1214 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1215 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1216 @samp{foo}. All other fields are missing. The section register here
1217 defaults to @samp{%ds}.
1219 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1220 This uses the value pointed to by @samp{foo} as a memory operand.
1221 Note that @var{base} and @var{index} are both missing, but there is only
1222 @emph{one} @samp{,}. This is a syntactic exception.
1224 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1225 This selects the contents of the variable @samp{foo} with section
1226 register @var{section} being @samp{%gs}.
1229 Absolute (as opposed to PC relative) call and jump operands must be
1230 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1231 always chooses PC relative addressing for jump/call labels.
1233 Any instruction that has a memory operand, but no register operand,
1234 @emph{must} specify its size (byte, word, long, or quadruple) with an
1235 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1238 The x86-64 architecture adds an RIP (instruction pointer relative)
1239 addressing. This addressing mode is specified by using @samp{rip} as a
1240 base register. Only constant offsets are valid. For example:
1243 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1244 Points to the address 1234 bytes past the end of the current
1247 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1248 Points to the @code{symbol} in RIP relative way, this is shorter than
1249 the default absolute addressing.
1252 Other addressing modes remain unchanged in x86-64 architecture, except
1253 registers used are 64-bit instead of 32-bit.
1256 @section Handling of Jump Instructions
1258 @cindex jump optimization, i386
1259 @cindex i386 jump optimization
1260 @cindex jump optimization, x86-64
1261 @cindex x86-64 jump optimization
1262 Jump instructions are always optimized to use the smallest possible
1263 displacements. This is accomplished by using byte (8-bit) displacement
1264 jumps whenever the target is sufficiently close. If a byte displacement
1265 is insufficient a long displacement is used. We do not support
1266 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1267 instruction with the @samp{data16} instruction prefix), since the 80386
1268 insists upon masking @samp{%eip} to 16 bits after the word displacement
1269 is added. (See also @pxref{i386-Arch})
1271 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1272 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1273 displacements, so that if you use these instructions (@code{@value{GCC}} does
1274 not use them) you may get an error message (and incorrect code). The AT&T
1275 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1286 @section Floating Point
1288 @cindex i386 floating point
1289 @cindex floating point, i386
1290 @cindex x86-64 floating point
1291 @cindex floating point, x86-64
1292 All 80387 floating point types except packed BCD are supported.
1293 (BCD support may be added without much difficulty). These data
1294 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1295 double (64-bit), and extended (80-bit) precision floating point.
1296 Each supported type has an instruction mnemonic suffix and a constructor
1297 associated with it. Instruction mnemonic suffixes specify the operand's
1298 data type. Constructors build these data types into memory.
1300 @cindex @code{float} directive, i386
1301 @cindex @code{single} directive, i386
1302 @cindex @code{double} directive, i386
1303 @cindex @code{tfloat} directive, i386
1304 @cindex @code{float} directive, x86-64
1305 @cindex @code{single} directive, x86-64
1306 @cindex @code{double} directive, x86-64
1307 @cindex @code{tfloat} directive, x86-64
1310 Floating point constructors are @samp{.float} or @samp{.single},
1311 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1312 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1313 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1314 only supports this format via the @samp{fldt} (load 80-bit real to stack
1315 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1317 @cindex @code{word} directive, i386
1318 @cindex @code{long} directive, i386
1319 @cindex @code{int} directive, i386
1320 @cindex @code{quad} directive, i386
1321 @cindex @code{word} directive, x86-64
1322 @cindex @code{long} directive, x86-64
1323 @cindex @code{int} directive, x86-64
1324 @cindex @code{quad} directive, x86-64
1326 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1327 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1328 corresponding instruction mnemonic suffixes are @samp{s} (single),
1329 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1330 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1331 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1332 stack) instructions.
1335 Register to register operations should not use instruction mnemonic suffixes.
1336 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1337 wrote @samp{fst %st, %st(1)}, since all register to register operations
1338 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1339 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1340 then stores the result in the 4 byte location @samp{mem})
1343 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1346 @cindex 3DNow!, i386
1349 @cindex 3DNow!, x86-64
1350 @cindex SIMD, x86-64
1352 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1353 instructions for integer data), available on Intel's Pentium MMX
1354 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1355 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1356 instruction set (SIMD instructions for 32-bit floating point data)
1357 available on AMD's K6-2 processor and possibly others in the future.
1359 Currently, @code{@value{AS}} does not support Intel's floating point
1362 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1363 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1364 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1365 floating point values. The MMX registers cannot be used at the same time
1366 as the floating point stack.
1368 See Intel and AMD documentation, keeping in mind that the operand order in
1369 instructions is reversed from the Intel syntax.
1372 @section AMD's Lightweight Profiling Instructions
1377 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1378 instruction set, available on AMD's Family 15h (Orochi) processors.
1380 LWP enables applications to collect and manage performance data, and
1381 react to performance events. The collection of performance data
1382 requires no context switches. LWP runs in the context of a thread and
1383 so several counters can be used independently across multiple threads.
1384 LWP can be used in both 64-bit and legacy 32-bit modes.
1386 For detailed information on the LWP instruction set, see the
1387 @cite{AMD Lightweight Profiling Specification} available at
1388 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1391 @section Bit Manipulation Instructions
1396 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1398 BMI instructions provide several instructions implementing individual
1399 bit manipulation operations such as isolation, masking, setting, or
1402 @c Need to add a specification citation here when available.
1405 @section AMD's Trailing Bit Manipulation Instructions
1410 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1411 instruction set, available on AMD's BDVER2 processors (Trinity and
1414 TBM instructions provide instructions implementing individual bit
1415 manipulation operations such as isolating, masking, setting, resetting,
1416 complementing, and operations on trailing zeros and ones.
1418 @c Need to add a specification citation here when available.
1421 @section Writing 16-bit Code
1423 @cindex i386 16-bit code
1424 @cindex 16-bit code, i386
1425 @cindex real-mode code, i386
1426 @cindex @code{code16gcc} directive, i386
1427 @cindex @code{code16} directive, i386
1428 @cindex @code{code32} directive, i386
1429 @cindex @code{code64} directive, i386
1430 @cindex @code{code64} directive, x86-64
1431 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1432 or 64-bit x86-64 code depending on the default configuration,
1433 it also supports writing code to run in real mode or in 16-bit protected
1434 mode code segments. To do this, put a @samp{.code16} or
1435 @samp{.code16gcc} directive before the assembly language instructions to
1436 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1437 32-bit code with the @samp{.code32} directive or 64-bit code with the
1438 @samp{.code64} directive.
1440 @samp{.code16gcc} provides experimental support for generating 16-bit
1441 code from gcc, and differs from @samp{.code16} in that @samp{call},
1442 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1443 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1444 default to 32-bit size. This is so that the stack pointer is
1445 manipulated in the same way over function calls, allowing access to
1446 function parameters at the same stack offsets as in 32-bit mode.
1447 @samp{.code16gcc} also automatically adds address size prefixes where
1448 necessary to use the 32-bit addressing modes that gcc generates.
1450 The code which @code{@value{AS}} generates in 16-bit mode will not
1451 necessarily run on a 16-bit pre-80386 processor. To write code that
1452 runs on such a processor, you must refrain from using @emph{any} 32-bit
1453 constructs which require @code{@value{AS}} to output address or operand
1456 Note that writing 16-bit code instructions by explicitly specifying a
1457 prefix or an instruction mnemonic suffix within a 32-bit code section
1458 generates different machine instructions than those generated for a
1459 16-bit code segment. In a 32-bit code section, the following code
1460 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1461 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1467 The same code in a 16-bit code section would generate the machine
1468 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1469 is correct since the processor default operand size is assumed to be 16
1470 bits in a 16-bit code section.
1473 @section Specifying CPU Architecture
1475 @cindex arch directive, i386
1476 @cindex i386 arch directive
1477 @cindex arch directive, x86-64
1478 @cindex x86-64 arch directive
1480 @code{@value{AS}} may be told to assemble for a particular CPU
1481 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1482 directive enables a warning when gas detects an instruction that is not
1483 supported on the CPU specified. The choices for @var{cpu_type} are:
1485 @multitable @columnfractions .20 .20 .20 .20
1486 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1487 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1488 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1489 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1490 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1491 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1492 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1493 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1494 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1495 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1496 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
1497 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1498 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1499 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1500 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1501 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1502 @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1504 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1505 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1506 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1507 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1508 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1509 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1510 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1511 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1513 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1514 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1515 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1516 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
1517 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
1518 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
1519 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1520 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1521 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1522 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1523 @item @samp{.mcommit} @tab @samp{.sev_es}
1526 Apart from the warning, there are only two other effects on
1527 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1528 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1529 will automatically use a two byte opcode sequence. The larger three
1530 byte opcode sequence is used on the 486 (and when no architecture is
1531 specified) because it executes faster on the 486. Note that you can
1532 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1533 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1534 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1535 conditional jumps will be promoted when necessary to a two instruction
1536 sequence consisting of a conditional jump of the opposite sense around
1537 an unconditional jump to the target.
1539 Following the CPU architecture (but not a sub-architecture, which are those
1540 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1541 control automatic promotion of conditional jumps. @samp{jumps} is the
1542 default, and enables jump promotion; All external jumps will be of the long
1543 variety, and file-local jumps will be promoted as necessary.
1544 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1545 byte offset jumps, and warns about file-local conditional jumps that
1546 @code{@value{AS}} promotes.
1547 Unconditional jumps are treated as for @samp{jumps}.
1556 @section AMD64 ISA vs. Intel64 ISA
1558 There are some discrepancies between AMD64 and Intel64 ISAs.
1561 @item For @samp{movsxd} with 16-bit destination register, AMD64
1562 supports 32-bit source operand and Intel64 supports 16-bit source
1565 @item For far branches (with explicit memory operand), both ISAs support
1566 32- and 16-bit operand size. Intel64 additionally supports 64-bit
1567 operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax
1568 and with an explicit @samp{tbyte ptr} operand size specifier in Intel
1571 @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16-
1572 and 32-bit operand size (32- and 48-bit memory operand) in both ISAs,
1573 while Intel64 additionally supports 64-bit operand sise (80-bit memory
1579 @section AT&T Syntax bugs
1581 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1582 assemblers, generate floating point instructions with reversed source
1583 and destination registers in certain cases. Unfortunately, gcc and
1584 possibly many other programs use this reversed syntax, so we're stuck
1593 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1594 than the expected @samp{%st(3) - %st}. This happens with all the
1595 non-commutative arithmetic floating point operations with two register
1596 operands where the source register is @samp{%st} and the destination
1597 register is @samp{%st(i)}.
1602 @cindex i386 @code{mul}, @code{imul} instructions
1603 @cindex @code{mul} instruction, i386
1604 @cindex @code{imul} instruction, i386
1605 @cindex @code{mul} instruction, x86-64
1606 @cindex @code{imul} instruction, x86-64
1607 There is some trickery concerning the @samp{mul} and @samp{imul}
1608 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1609 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1610 for @samp{imul}) can be output only in the one operand form. Thus,
1611 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1612 the expanding multiply would clobber the @samp{%edx} register, and this
1613 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1614 64-bit product in @samp{%edx:%eax}.
1616 We have added a two operand form of @samp{imul} when the first operand
1617 is an immediate mode expression and the second operand is a register.
1618 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1619 example, can be done with @samp{imul $69, %eax} rather than @samp{imul