1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
18 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the MIPS instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of MIPS assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Options:: Assembler options
26 * MIPS Macros:: High-level assembly macros
27 * MIPS Symbol Sizes:: Directives to override the size of symbols
28 * MIPS Small Data:: Controlling the use of small data accesses
29 * MIPS ISA:: Directives to override the ISA level
30 * MIPS assembly options:: Directives to control code generation
31 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
32 * MIPS insn:: Directive to mark data as an instruction
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
41 @section Assembler options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
49 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
87 Generate code for a particular MIPS Instruction Set Architecture level.
88 @samp{-mips1} corresponds to the R2000 and R3000 processors,
89 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
90 R4000 processor, and @samp{-mips4} to the R8000 and
91 R10000 processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
92 @samp{-mips64}, and @samp{-mips64r2}
94 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
95 and @sc{MIPS64 Release 2}
96 ISA processors, respectively. You can also switch
97 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
98 override the ISA level}.
102 Some macros have different expansions for 32-bit and 64-bit registers.
103 The register sizes are normally inferred from the ISA and ABI, but these
104 flags force a certain group of registers to be treated as 32 bits wide at
105 all times. @samp{-mgp32} controls the size of general-purpose registers
106 and @samp{-mfp32} controls the size of floating-point registers.
108 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
109 of registers to be changed for parts of an object. The default value is
110 restored by @code{.set gp=default} and @code{.set fp=default}.
112 On some MIPS variants there is a 32-bit mode flag; when this flag is
113 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
114 save the 32-bit registers on a context switch, so it is essential never
115 to use the 64-bit registers.
119 Assume that 64-bit registers are available. This is provided in the
120 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
122 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
123 of registers to be changed for parts of an object. The default value is
124 restored by @code{.set gp=default} and @code{.set fp=default}.
128 Generate code for the MIPS 16 processor. This is equivalent to putting
129 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
130 turns off this option.
133 @itemx -mno-micromips
134 Generate code for the microMIPS processor. This is equivalent to putting
135 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
136 turns off this option. This is equivalent to putting @code{.set nomicromips}
137 at the start of the assembly file.
140 @itemx -mno-smartmips
141 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
142 provides a number of new instructions which target smartcard and
143 cryptographic applications. This is equivalent to putting
144 @code{.set smartmips} at the start of the assembly file.
145 @samp{-mno-smartmips} turns off this option.
149 Generate code for the MIPS-3D Application Specific Extension.
150 This tells the assembler to accept MIPS-3D instructions.
151 @samp{-no-mips3d} turns off this option.
155 Generate code for the MDMX Application Specific Extension.
156 This tells the assembler to accept MDMX instructions.
157 @samp{-no-mdmx} turns off this option.
161 Generate code for the DSP Release 1 Application Specific Extension.
162 This tells the assembler to accept DSP Release 1 instructions.
163 @samp{-mno-dsp} turns off this option.
167 Generate code for the DSP Release 2 Application Specific Extension.
168 This option implies -mdsp.
169 This tells the assembler to accept DSP Release 2 instructions.
170 @samp{-mno-dspr2} turns off this option.
174 Generate code for the MT Application Specific Extension.
175 This tells the assembler to accept MT instructions.
176 @samp{-mno-mt} turns off this option.
180 Generate code for the MCU Application Specific Extension.
181 This tells the assembler to accept MCU instructions.
182 @samp{-mno-mcu} turns off this option.
186 Generate code for the Virtualization Application Specific Extension.
187 This tells the assembler to accept Virtualization instructions.
188 @samp{-mno-virt} turns off this option.
192 Only use 32-bit instruction encodings when generating code for the
193 microMIPS processor. This option inhibits the use of any 16-bit
194 instructions. This is equivalent to putting @code{.set insn32} at
195 the start of the assembly file. @samp{-mno-insn32} turns off this
196 option. This is equivalent to putting @code{.set noinsn32} at the
197 start of the assembly file. By default @samp{-mno-insn32} is
198 selected, allowing all instructions to be used.
202 Cause nops to be inserted if the read of the destination register
203 of an mfhi or mflo instruction occurs in the following two instructions.
205 @item -mfix-loongson2f-jump
206 @itemx -mno-fix-loongson2f-jump
207 Eliminate instruction fetch from outside 256M region to work around the
208 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
209 the kernel may crash. The issue has been solved in latest processor
210 batches, but this fix has no side effect to them.
212 @item -mfix-loongson2f-nop
213 @itemx -mno-fix-loongson2f-nop
214 Replace nops by @code{or at,at,zero} to work around the Loongson2F
215 @samp{nop} errata. Without it, under extreme cases, the CPU might
216 deadlock. The issue has been solved in later Loongson2F batches, but
217 this fix has no side effect to them.
220 @itemx -mno-fix-vr4120
221 Insert nops to work around certain VR4120 errata. This option is
222 intended to be used on GCC-generated code: it is not designed to catch
223 all problems in hand-written assembler code.
226 @itemx -mno-fix-vr4130
227 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
231 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
234 @itemx -mno-fix-cn63xxp1
235 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
236 certain CN63XXP1 errata.
240 Generate code for the LSI R4010 chip. This tells the assembler to
241 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
242 etc.), and to not schedule @samp{nop} instructions around accesses to
243 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
248 Generate code for the MIPS R4650 chip. This tells the assembler to accept
249 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
250 instructions around accesses to the @samp{HI} and @samp{LO} registers.
251 @samp{-no-m4650} turns off this option.
257 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
258 R@var{nnnn} chip. This tells the assembler to accept instructions
259 specific to that chip, and to schedule for that chip's hazards.
261 @item -march=@var{cpu}
262 Generate code for a particular MIPS CPU. It is exactly equivalent to
263 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
264 understood. Valid @var{cpu} value are:
349 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
350 accepted as synonyms for @samp{@var{n}f1_1}. These values are
353 @item -mtune=@var{cpu}
354 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
355 identical to @samp{-march=@var{cpu}}.
357 @item -mabi=@var{abi}
358 Record which ABI the source code uses. The recognized arguments
359 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
365 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
366 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
368 @cindex @code{-nocpp} ignored (MIPS)
370 This option is ignored. It is accepted for command-line compatibility with
371 other assemblers, which use it to turn off C style preprocessing. With
372 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
373 @sc{gnu} assembler itself never runs the C preprocessor.
377 Disable or enable floating-point instructions. Note that by default
378 floating-point instructions are always allowed even with CPU targets
379 that don't have support for these instructions.
382 @itemx -mdouble-float
383 Disable or enable double-precision floating-point operations. Note
384 that by default double-precision floating-point operations are always
385 allowed even with CPU targets that don't have support for these
388 @item --construct-floats
389 @itemx --no-construct-floats
390 The @code{--no-construct-floats} option disables the construction of
391 double width floating point constants by loading the two halves of the
392 value into the two single width floating point registers that make up
393 the double width register. This feature is useful if the processor
394 support the FR bit in its status register, and this bit is known (by
395 the programmer) to be set. This bit prevents the aliasing of the double
396 width register by the single width registers.
398 By default @code{--construct-floats} is selected, allowing construction
399 of these floating point constants.
402 @itemx --no-relax-branch
403 The @samp{--relax-branch} option enables the relaxation of out-of-range
404 branches. Any branches whose target cannot be reached directly are
405 converted to a small instruction sequence including an inverse-condition
406 branch to the physically next instruction, and a jump to the original
407 target is inserted between the two instructions. In PIC code the jump
408 will involve further instructions for address calculation.
410 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
411 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
412 relaxation, because they have no complementing counterparts. They could
413 be relaxed with the use of a longer sequence involving another branch,
414 however this has not been implemented and if their target turns out of
415 reach, they produce an error even if branch relaxation is enabled.
417 Also no @sc{mips16} branches are ever relaxed.
419 By default @samp{--no-relax-branch} is selected, causing any out-of-range
420 branches to produce an error.
424 @c FIXME! (1) reflect these options (next item too) in option summaries;
425 @c (2) stop teasing, say _which_ instructions expanded _how_.
426 @code{@value{AS}} automatically macro expands certain division and
427 multiplication instructions to check for overflow and division by zero. This
428 option causes @code{@value{AS}} to generate code to take a trap exception
429 rather than a break exception when an error is detected. The trap instructions
430 are only supported at Instruction Set Architecture level 2 and higher.
434 Generate code to take a break exception rather than a trap exception when an
435 error is detected. This is the default.
439 Control generation of @code{.pdr} sections. Off by default on IRIX, on
444 When generating code using the Unix calling conventions (selected by
445 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
446 which can go into a shared library. The @samp{-mno-shared} option
447 tells gas to generate code which uses the calling convention, but can
448 not go into a shared library. The resulting code is slightly more
449 efficient. This option only affects the handling of the
450 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
454 @section High-level assembly macros
456 MIPS assemblers have traditionally provided a wider range of
457 instructions than the MIPS architecture itself. These extra
458 instructions are usually referred to as ``macro'' instructions
459 @footnote{The term ``macro'' is somewhat overloaded here, since
460 these macros have no relation to those defined by @code{.macro},
461 @pxref{Macro,, @code{.macro}}.}.
463 Some MIPS macro instructions extend an underlying architectural instruction
464 while others are entirely new. An example of the former type is @code{and},
465 which allows the third operand to be either a register or an arbitrary
466 immediate value. Examples of the latter type include @code{bgt}, which
467 branches to the third operand when the first operand is greater than
468 the second operand, and @code{ulh}, which implements an unaligned
471 One of the most common extensions provided by macros is to expand
472 memory offsets to the full address range (32 or 64 bits) and to allow
473 symbolic offsets such as @samp{my_data + 4} to be used in place of
474 integer constants. For example, the architectural instruction
475 @code{lbu} allows only a signed 16-bit offset, whereas the macro
476 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
477 The implementation of these symbolic offsets depends on several factors,
478 such as whether the assembler is generating SVR4-style PIC (selected by
479 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
480 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
481 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
482 of small data accesses}).
484 @kindex @code{.set macro}
485 @kindex @code{.set nomacro}
486 Sometimes it is undesirable to have one assembly instruction expand
487 to several machine instructions. The directive @code{.set nomacro}
488 tells the assembler to warn when this happens. @code{.set macro}
489 restores the default behavior.
491 @cindex @code{at} register, MIPS
492 @kindex @code{.set at=@var{reg}}
493 Some macro instructions need a temporary register to store intermediate
494 results. This register is usually @code{$1}, also known as @code{$at},
495 but it can be changed to any core register @var{reg} using
496 @code{.set at=@var{reg}}. Note that @code{$at} always refers
497 to @code{$1} regardless of which register is being used as the
500 @kindex @code{.set at}
501 @kindex @code{.set noat}
502 Implicit uses of the temporary register in macros could interfere with
503 explicit uses in the assembly code. The assembler therefore warns
504 whenever it sees an explicit use of the temporary register. The directive
505 @code{.set noat} silences this warning while @code{.set at} restores
506 the default behavior. It is safe to use @code{.set noat} while
507 @code{.set nomacro} is in effect since single-instruction macros
508 never need a temporary register.
510 Note that while the @sc{gnu} assembler provides these macros for compatibility,
511 it does not make any attempt to optimize them with the surrounding code.
513 @node MIPS Symbol Sizes
514 @section Directives to override the size of symbols
516 @kindex @code{.set sym32}
517 @kindex @code{.set nosym32}
518 The n64 ABI allows symbols to have any 64-bit value. Although this
519 provides a great deal of flexibility, it means that some macros have
520 much longer expansions than their 32-bit counterparts. For example,
521 the non-PIC expansion of @samp{dla $4,sym} is usually:
526 daddiu $4,$4,%higher(sym)
527 daddiu $1,$1,%lo(sym)
532 whereas the 32-bit expansion is simply:
536 daddiu $4,$4,%lo(sym)
539 n64 code is sometimes constructed in such a way that all symbolic
540 constants are known to have 32-bit values, and in such cases, it's
541 preferable to use the 32-bit expansion instead of the 64-bit
544 You can use the @code{.set sym32} directive to tell the assembler
545 that, from this point on, all expressions of the form
546 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
547 have 32-bit values. For example:
556 will cause the assembler to treat @samp{sym}, @code{sym+16} and
557 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
558 addresses is not affected.
560 The directive @code{.set nosym32} ends a @code{.set sym32} block and
561 reverts to the normal behavior. It is also possible to change the
562 symbol size using the command-line options @option{-msym32} and
565 These options and directives are always accepted, but at present,
566 they have no effect for anything other than n64.
568 @node MIPS Small Data
569 @section Controlling the use of small data accesses
571 @c This section deliberately glosses over the possibility of using -G
572 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
573 @cindex small data, MIPS
574 @cindex @code{gp} register, MIPS
575 It often takes several instructions to load the address of a symbol.
576 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
577 of @samp{dla $4,addr} is usually:
581 daddiu $4,$4,%lo(addr)
584 The sequence is much longer when @samp{addr} is a 64-bit symbol.
585 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
587 In order to cut down on this overhead, most embedded MIPS systems
588 set aside a 64-kilobyte ``small data'' area and guarantee that all
589 data of size @var{n} and smaller will be placed in that area.
590 The limit @var{n} is passed to both the assembler and the linker
591 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
592 Assembler options}. Note that the same value of @var{n} must be used
593 when linking and when assembling all input files to the link; any
594 inconsistency could cause a relocation overflow error.
596 The size of an object in the @code{.bss} section is set by the
597 @code{.comm} or @code{.lcomm} directive that defines it. The size of
598 an external object may be set with the @code{.extern} directive. For
599 example, @samp{.extern sym,4} declares that the object at @code{sym}
600 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
602 When no @option{-G} option is given, the default limit is 8 bytes.
603 The option @option{-G 0} prevents any data from being automatically
606 It is also possible to mark specific objects as small by putting them
607 in the special sections @code{.sdata} and @code{.sbss}, which are
608 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
609 The toolchain will treat such data as small regardless of the
612 On startup, systems that support a small data area are expected to
613 initialize register @code{$28}, also known as @code{$gp}, in such a
614 way that small data can be accessed using a 16-bit offset from that
615 register. For example, when @samp{addr} is small data,
616 the @samp{dla $4,addr} instruction above is equivalent to:
619 daddiu $4,$28,%gp_rel(addr)
622 Small data is not supported for SVR4-style PIC.
625 @section Directives to override the ISA level
627 @cindex MIPS ISA override
628 @kindex @code{.set mips@var{n}}
629 @sc{gnu} @code{@value{AS}} supports an additional directive to change
630 the MIPS Instruction Set Architecture level on the fly: @code{.set
631 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
633 The values other than 0 make the assembler accept instructions
634 for the corresponding @sc{isa} level, from that point on in the
635 assembly. @code{.set mips@var{n}} affects not only which instructions
636 are permitted, but also how certain macros are expanded. @code{.set
637 mips0} restores the @sc{isa} level to its original level: either the
638 level you selected with command line options, or the default for your
639 configuration. You can use this feature to permit specific @sc{mips3}
640 instructions while assembling in 32 bit mode. Use this directive with
643 @cindex MIPS CPU override
644 @kindex @code{.set arch=@var{cpu}}
645 The @code{.set arch=@var{cpu}} directive provides even finer control.
646 It changes the effective CPU target and allows the assembler to use
647 instructions specific to a particular CPU. All CPUs supported by the
648 @samp{-march} command line option are also selectable by this directive.
649 The original value is restored by @code{.set arch=default}.
651 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
652 in which it will assemble instructions for the MIPS 16 processor. Use
653 @code{.set nomips16} to return to normal 32 bit mode.
655 Traditional MIPS assemblers do not support this directive.
657 The directive @code{.set micromips} puts the assembler into microMIPS mode,
658 in which it will assemble instructions for the microMIPS processor. Use
659 @code{.set nomicromips} to return to normal 32 bit mode.
661 Traditional MIPS assemblers do not support this directive.
663 @node MIPS assembly options
664 @section Directives to control code generation
666 @cindex MIPS 32-bit microMIPS instruction generation override
667 @kindex @code{.set insn32}
668 @kindex @code{.set noinsn32}
669 The directive @code{.set insn32} makes the assembler only use 32-bit
670 instruction encodings when generating code for the microMIPS processor.
671 This directive inhibits the use of any 16-bit instructions from that
672 point on in the assembly. The @code{.set noinsn32} directive allows
673 16-bit instructions to be accepted.
675 Traditional MIPS assemblers do not support this directive.
677 @node MIPS autoextend
678 @section Directives for extending MIPS 16 bit instructions
680 @kindex @code{.set autoextend}
681 @kindex @code{.set noautoextend}
682 By default, MIPS 16 instructions are automatically extended to 32 bits
683 when necessary. The directive @code{.set noautoextend} will turn this
684 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
685 must be explicitly extended with the @code{.e} modifier (e.g.,
686 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
687 to once again automatically extend instructions when necessary.
689 This directive is only meaningful when in MIPS 16 mode. Traditional
690 MIPS assemblers do not support this directive.
693 @section Directive to mark data as an instruction
696 The @code{.insn} directive tells @code{@value{AS}} that the following
697 data is actually instructions. This makes a difference in MIPS 16 and
698 microMIPS modes: when loading the address of a label which precedes
699 instructions, @code{@value{AS}} automatically adds 1 to the value, so
700 that jumping to the loaded address will do the right thing.
702 @kindex @code{.global}
703 The @code{.global} and @code{.globl} directives supported by
704 @code{@value{AS}} will by default mark the symbol as pointing to a
705 region of data not code. This means that, for example, any
706 instructions following such a symbol will not be disassembled by
707 @code{objdump} as it will regard them as data. To change this
708 behaviour an optional section name can be placed after the symbol name
709 in the @code{.global} directive. If this section exists and is known
710 to be a code section, then the symbol will be marked as poiting at
711 code not data. Ie the syntax for the directive is:
713 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
715 Here is a short example:
718 .global foo .text, bar, baz .data
728 @node MIPS Option Stack
729 @section Directives to save and restore options
731 @cindex MIPS option stack
732 @kindex @code{.set push}
733 @kindex @code{.set pop}
734 The directives @code{.set push} and @code{.set pop} may be used to save
735 and restore the current settings for all the options which are
736 controlled by @code{.set}. The @code{.set push} directive saves the
737 current settings on a stack. The @code{.set pop} directive pops the
738 stack and restores the settings.
740 These directives can be useful inside an macro which must change an
741 option such as the ISA level or instruction reordering but does not want
742 to change the state of the code which invoked the macro.
744 Traditional MIPS assemblers do not support these directives.
746 @node MIPS ASE Instruction Generation Overrides
747 @section Directives to control generation of MIPS ASE instructions
749 @cindex MIPS MIPS-3D instruction generation override
750 @kindex @code{.set mips3d}
751 @kindex @code{.set nomips3d}
752 The directive @code{.set mips3d} makes the assembler accept instructions
753 from the MIPS-3D Application Specific Extension from that point on
754 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
755 instructions from being accepted.
757 @cindex SmartMIPS instruction generation override
758 @kindex @code{.set smartmips}
759 @kindex @code{.set nosmartmips}
760 The directive @code{.set smartmips} makes the assembler accept
761 instructions from the SmartMIPS Application Specific Extension to the
762 MIPS32 @sc{isa} from that point on in the assembly. The
763 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
766 @cindex MIPS MDMX instruction generation override
767 @kindex @code{.set mdmx}
768 @kindex @code{.set nomdmx}
769 The directive @code{.set mdmx} makes the assembler accept instructions
770 from the MDMX Application Specific Extension from that point on
771 in the assembly. The @code{.set nomdmx} directive prevents MDMX
772 instructions from being accepted.
774 @cindex MIPS DSP Release 1 instruction generation override
775 @kindex @code{.set dsp}
776 @kindex @code{.set nodsp}
777 The directive @code{.set dsp} makes the assembler accept instructions
778 from the DSP Release 1 Application Specific Extension from that point
779 on in the assembly. The @code{.set nodsp} directive prevents DSP
780 Release 1 instructions from being accepted.
782 @cindex MIPS DSP Release 2 instruction generation override
783 @kindex @code{.set dspr2}
784 @kindex @code{.set nodspr2}
785 The directive @code{.set dspr2} makes the assembler accept instructions
786 from the DSP Release 2 Application Specific Extension from that point
787 on in the assembly. This dirctive implies @code{.set dsp}. The
788 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
791 @cindex MIPS MT instruction generation override
792 @kindex @code{.set mt}
793 @kindex @code{.set nomt}
794 The directive @code{.set mt} makes the assembler accept instructions
795 from the MT Application Specific Extension from that point on
796 in the assembly. The @code{.set nomt} directive prevents MT
797 instructions from being accepted.
799 @cindex MIPS MCU instruction generation override
800 @kindex @code{.set mcu}
801 @kindex @code{.set nomcu}
802 The directive @code{.set mcu} makes the assembler accept instructions
803 from the MCU Application Specific Extension from that point on
804 in the assembly. The @code{.set nomcu} directive prevents MCU
805 instructions from being accepted.
807 @cindex Virtualization instruction generation override
808 @kindex @code{.set virt}
809 @kindex @code{.set novirt}
810 The directive @code{.set virt} makes the assembler accept instructions
811 from the Virtualization Application Specific Extension from that point
812 on in the assembly. The @code{.set novirt} directive prevents Virtualization
813 instructions from being accepted.
815 Traditional MIPS assemblers do not support these directives.
817 @node MIPS Floating-Point
818 @section Directives to override floating-point options
820 @cindex Disable floating-point instructions
821 @kindex @code{.set softfloat}
822 @kindex @code{.set hardfloat}
823 The directives @code{.set softfloat} and @code{.set hardfloat} provide
824 finer control of disabling and enabling float-point instructions.
825 These directives always override the default (that hard-float
826 instructions are accepted) or the command-line options
827 (@samp{-msoft-float} and @samp{-mhard-float}).
829 @cindex Disable single-precision floating-point operations
830 @kindex @code{.set singlefloat}
831 @kindex @code{.set doublefloat}
832 The directives @code{.set singlefloat} and @code{.set doublefloat}
833 provide finer control of disabling and enabling double-precision
834 float-point operations. These directives always override the default
835 (that double-precision operations are accepted) or the command-line
836 options (@samp{-msingle-float} and @samp{-mdouble-float}).
838 Traditional MIPS assemblers do not support these directives.
841 @section Syntactical considerations for the MIPS assembler
843 * MIPS-Chars:: Special Characters
847 @subsection Special Characters
849 @cindex line comment character, MIPS
850 @cindex MIPS line comment character
851 The presence of a @samp{#} on a line indicates the start of a comment
852 that extends to the end of the current line.
854 If a @samp{#} appears as the first character of a line, the whole line
855 is treated as a comment, but in this case the line can also be a
856 logical line number directive (@pxref{Comments}) or a
857 preprocessor control command (@pxref{Preprocessing}).
859 @cindex line separator, MIPS
860 @cindex statement separator, MIPS
861 @cindex MIPS line separator
862 The @samp{;} character can be used to separate statements on the same