gas/doc/c-riscv.texi

   1 @c Copyright (C) 2016-2023 Free Software Foundation, Inc.
   2 @c This is part of the GAS anual.
   3 @c For copying conditions, see the file as.texinfo
   4 @c man end
   5
   6 @ifset GENERIC
   7 @page
   8 @node RISC-V-Dependent
   9 @chapter RISC-V Dependent Features
  10 @end ifset
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter RISC-V Dependent Features
  14 @end ifclear
  15
  16 @cindex RISC-V support
  17 @menu
  18 * RISC-V-Options::        RISC-V Options
  19 * RISC-V-Directives::     RISC-V Directives
  20 * RISC-V-Modifiers::      RISC-V Assembler Modifiers
  21 * RISC-V-Formats::        RISC-V Instruction Formats
  22 * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
  23 * RISC-V-CustomExts::     RISC-V Custom (Vendor-Defined) Extensions
  24 @end menu
  25
  26 @node RISC-V-Options
  27 @section RISC-V Options
  28
  29 The following table lists all available RISC-V specific options.
  30
  31 @c man begin OPTIONS
  32 @table @gcctabopt
  33
  34 @cindex @samp{-fpic} option, RISC-V
  35 @item -fpic
  36 @itemx -fPIC
  37 Generate position-independent code
  38
  39 @cindex @samp{-fno-pic} option, RISC-V
  40 @item -fno-pic
  41 Don't generate position-independent code (default)
  42
  43 @cindex @samp{-march=ISA} option, RISC-V
  44 @item -march=ISA
  45 Select the base isa, as specified by ISA.  For example -march=rv32ima.
  46 If this option and the architecture attributes aren't set, then assembler
  47 will check the default configure setting --with-arch=ISA.
  48
  49 @cindex @samp{-misa-spec=ISAspec} option, RISC-V
  50 @item -misa-spec=ISAspec
  51 Select the default isa spec version.  If the version of ISA isn't set
  52 by -march, then assembler helps to set the version according to
  53 the default chosen spec.  If this option isn't set, then assembler will
  54 check the default configure setting --with-isa-spec=ISAspec.
  55
  56 @cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V
  57 @item -mpriv-spec=PRIVspec
  58 Select the privileged spec version.  We can decide whether the CSR is valid or
  59 not according to the chosen spec.  If this option and the privilege attributes
  60 aren't set, then assembler will check the default configure setting
  61 --with-priv-spec=PRIVspec.
  62
  63 @cindex @samp{-mabi=ABI} option, RISC-V
  64 @item -mabi=ABI
  65 Selects the ABI, which is either "ilp32" or "lp64", optionally followed
  66 by "f", "d", or "q" to indicate single-precision, double-precision, or
  67 quad-precision floating-point calling convention, or none to indicate
  68 the soft-float calling convention.  Also, "ilp32" can optionally be followed
  69 by "e" to indicate the RVE ABI, which is always soft-float.
  70
  71 @cindex @samp{-mrelax} option, RISC-V
  72 @item -mrelax
  73 Take advantage of linker relaxations to reduce the number of instructions
  74 required to materialize symbol addresses. (default)
  75
  76 @cindex @samp{-mno-relax} option, RISC-V
  77 @item -mno-relax
  78 Don't do linker relaxations.
  79
  80 @cindex @samp{-march-attr} option, RISC-V
  81 @item -march-attr
  82 Generate the default contents for the riscv elf attribute section if the
  83 .attribute directives are not set.  This section is used to record the
  84 information that a linker or runtime loader needs to check compatibility.
  85 This information includes ISA string, stack alignment requirement, unaligned
  86 memory accesses, and the major, minor and revision version of privileged
  87 specification.
  88
  89 @cindex @samp{-mno-arch-attr} option, RISC-V
  90 @item -mno-arch-attr
  91 Don't generate the default riscv elf attribute section if the .attribute
  92 directives are not set.
  93
  94 @cindex @samp{-mcsr-check} option, RISC-V
  95 @item -mcsr-check
  96 Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
  97 The ISA-dependent CSR are only valid when the specific ISA is set.  The
  98 read-only CSR can not be written by the CSR instructions.
  99
 100 @cindex @samp{-mno-csr-check} option, RISC-V
 101 @item -mno-csr-check
 102 Don't do CSR checking.
 103
 104 @cindex @samp{-mlittle-endian} option, RISC-V
 105 @item -mlittle-endian
 106 Generate code for a little endian machine.
 107
 108 @cindex @samp{-mbig-endian} option, RISC-V
 109 @item -mbig-endian
 110 Generate code for a big endian machine.
 111 @end table
 112 @c man end
 113
 114 @node RISC-V-Directives
 115 @section RISC-V Directives
 116 @cindex machine directives, RISC-V
 117 @cindex RISC-V machine directives
 118
 119 The following table lists all available RISC-V specific directives.
 120
 121 @table @code
 122
 123 @cindex @code{align} directive
 124 @item .align @var{size-log-2}
 125 Align to the given boundary, with the size given as log2 the number of bytes to
 126 align to.
 127
 128 @cindex Data directives
 129 @item .half @var{value}
 130 @itemx .word @var{value}
 131 @itemx .dword @var{value}
 132 Emits a half-word, word, or double-word value at the current position.
 133
 134 @cindex DTP-relative data directives
 135 @item .dtprelword @var{value}
 136 @itemx .dtpreldword @var{value}
 137 Emits a DTP-relative word (or double-word) at the current position.  This is
 138 meant to be used by the compiler in shared libraries for DWARF debug info for
 139 thread local variables.
 140
 141 @cindex BSS directive
 142 @item .bss
 143 Sets the current section to the BSS section.
 144
 145 @cindex LEB128 directives
 146 @item .uleb128 @var{value}
 147 @itemx .sleb128 @var{value}
 148 Emits a signed or unsigned LEB128 value at the current position.  This only
 149 accepts constant expressions, because symbol addresses can change with
 150 relaxation, and we don't support relocations to modify LEB128 values at link
 151 time.
 152
 153 @cindex Option directive
 154 @cindex @code{option} directive
 155 @item .option @var{argument}
 156 Modifies RISC-V specific assembler options inline with the assembly code.
 157 This is used when particular instruction sequences must be assembled with a
 158 specific set of options.  For example, since we relax addressing sequences to
 159 shorter GP-relative sequences when possible the initial load of GP must not be
 160 relaxed and should be emitted as something like
 161
 162 @smallexample
 163         .option push
 164         .option norelax
 165         la gp, __global_pointer$
 166         .option pop
 167 @end smallexample
 168
 169 in order to produce after linker relaxation the expected
 170
 171 @smallexample
 172         auipc gp, %pcrel_hi(__global_pointer$)
 173         addi gp, gp, %pcrel_lo(__global_pointer$)
 174 @end smallexample
 175
 176 instead of just
 177
 178 @smallexample
 179         addi gp, gp, 0
 180 @end smallexample
 181
 182 It's not expected that options are changed in this manner during regular use,
 183 but there are a handful of esoteric cases like the one above where users need
 184 to disable particular features of the assembler for particular code sequences.
 185 The complete list of option arguments is shown below:
 186
 187 @table @code
 188 @item push
 189 @itemx pop
 190 Pushes or pops the current option stack.  These should be used whenever
 191 changing an option in line with assembly code in order to ensure the user's
 192 command-line options are respected for the bulk of the file being assembled.
 193
 194 @item rvc
 195 @itemx norvc
 196 Enables or disables the generation of compressed instructions.  Instructions
 197 are opportunistically compressed by the RISC-V assembler when possible, but
 198 sometimes this behavior is not desirable, especially when handling alignments.
 199
 200 @item pic
 201 @itemx nopic
 202 Enables or disables position-independent code generation.  Unless you really
 203 know what you're doing, this should only be at the top of a file.
 204
 205 @item relax
 206 @itemx norelax
 207 Enables or disables relaxation.  The RISC-V assembler and linker
 208 opportunistically relax some code sequences, but sometimes this behavior is not
 209 desirable.
 210
 211 @item csr-check
 212 @itemx no-csr-check
 213 Enables or disables the CSR checking.
 214
 215 @item arch, @var{+extension[version]} [,...,@var{+extension_n[version_n]}]
 216 @itemx arch, @var{-extension} [,...,@var{-extension_n}]
 217 @itemx arch, @var{=ISA}
 218 Enables or disables the extensions for specific code region.  For example,
 219 @samp{.option arch, +m2p0} means add m extension with version 2.0, and
 220 @samp{.option arch, -f, -d} means remove extensions, f and d, from the
 221 architecture string.  Note that, @samp{.option arch, +c, -c} have the same
 222 behavior as @samp{.option rvc, norvc}.  However, they are also undesirable
 223 sometimes.  Besides, @samp{.option arch, -i} is illegal, since we cannot
 224 remove the base i extension anytime.  If you want to reset the whole ISA
 225 string, you can also use @samp{.option arch, =rv32imac} to overwrite the
 226 previous settings.
 227 @end table
 228
 229 @cindex INSN directives
 230 @item .insn @var{type}, @var{operand} [,...,@var{operand_n}]
 231 @itemx .insn @var{insn_length}, @var{value}
 232 @itemx .insn @var{value}
 233 This directive permits the numeric representation of an instructions
 234 and makes the assembler insert the operands according to one of the
 235 instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
 236 For example, the instruction @samp{add a0, a1, a2} could be written as
 237 @samp{.insn r 0x33, 0, 0, a0, a1, a2}.  But in fact, the instruction
 238 formats are difficult to use for some users, so most of them are using
 239 @samp{.word} to encode the instruction directly, rather than using
 240 @samp{.insn}.  It is fine for now, but will be wrong when the mapping
 241 symbols are supported, since @samp{.word} will not be shown as an
 242 instruction, it should be shown as data.  Therefore, we also support
 243 two more formats of the @samp{.insn}, the instruction @samp{add a0, a1, a2}
 244 could also be written as @samp{.insn 0x4, 0xc58533} or @samp{.insn 0xc58533}.
 245 When the @var{insn_length} is set, then assembler will check if the
 246 @var{value} is a valid @var{insn_length} bytes instruction.
 247
 248 @cindex @code{.attribute} directive, RISC-V
 249 @item .attribute @var{tag}, @var{value}
 250 Set the object attribute @var{tag} to @var{value}.
 251
 252 The @var{tag} is either an attribute number, or one of the following:
 253 @code{Tag_RISCV_arch}, @code{Tag_RISCV_stack_align},
 254 @code{Tag_RISCV_unaligned_access}, @code{Tag_RISCV_priv_spec},
 255 @code{Tag_RISCV_priv_spec_minor}, @code{Tag_RISCV_priv_spec_revision}.
 256
 257 @end table
 258
 259 @node RISC-V-Modifiers
 260 @section RISC-V Assembler Modifiers
 261
 262 The RISC-V assembler supports following modifiers for relocatable addresses
 263 used in RISC-V instruction operands.  However, we also support some pseudo
 264 instructions that are easier to use than these modifiers.
 265
 266 @table @code
 267 @item %lo(@var{symbol})
 268 The low 12 bits of absolute address for @var{symbol}.
 269
 270 @item %hi(@var{symbol})
 271 The high 20 bits of absolute address for @var{symbol}.  This is usually
 272 used with the %lo modifier to represent a 32-bit absolute address.
 273
 274 @smallexample
 275         lui        a0, %hi(@var{symbol})     // R_RISCV_HI20
 276         addi       a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I
 277
 278         lui        a0, %hi(@var{symbol})     // R_RISCV_HI20
 279         load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S
 280 @end smallexample
 281
 282 @item %pcrel_lo(@var{label})
 283 The low 12 bits of relative address between pc and @var{symbol}.
 284 The @var{symbol} is related to the high part instruction which is marked
 285 by @var{label}.
 286
 287 @item %pcrel_hi(@var{symbol})
 288 The high 20 bits of relative address between pc and @var{symbol}.
 289 This is usually used with the %pcrel_lo modifier to represent a +/-2GB
 290 pc-relative range.
 291
 292 @smallexample
 293 @var{label}:
 294         auipc      a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
 295         addi       a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
 296
 297 @var{label}:
 298         auipc      a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
 299         load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S
 300 @end smallexample
 301
 302 Or you can use the pseudo lla/lw/sw/... instruction to do this.
 303
 304 @smallexample
 305         lla  a0, @var{symbol}
 306 @end smallexample
 307
 308 @item %got_pcrel_hi(@var{symbol})
 309 The high 20 bits of relative address between pc and the GOT entry of
 310 @var{symbol}.  This is usually used with the %pcrel_lo modifier to access
 311 the GOT entry.
 312
 313 @smallexample
 314 @var{label}:
 315         auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
 316         addi       a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I
 317
 318 @var{label}:
 319         auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
 320         load/store a0, %pcrel_lo(@var{label})(a0)  // R_RISCV_PCREL_LO12_I/S
 321 @end smallexample
 322
 323 Also, the pseudo la instruction with PIC has similar behavior.
 324
 325 @item %tprel_add(@var{symbol})
 326 This is used purely to associate the R_RISCV_TPREL_ADD relocation for
 327 TLS relaxation.  This one is only valid as the fourth operand to the normally
 328 3 operand add instruction.
 329
 330 @item %tprel_lo(@var{symbol})
 331 The low 12 bits of relative address between tp and @var{symbol}.
 332
 333 @item %tprel_hi(@var{symbol})
 334 The high 20 bits of relative address between tp and @var{symbol}.  This is
 335 usually used with the %tprel_lo and %tprel_add modifiers to access the thread
 336 local variable @var{symbol} in TLS Local Exec.
 337
 338 @smallexample
 339         lui        a5, %tprel_hi(@var{symbol})          // R_RISCV_TPREL_HI20
 340         add        a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
 341         load/store t0, %tprel_lo(@var{symbol})(a5)      // R_RISCV_TPREL_LO12_I/S
 342 @end smallexample
 343
 344 @item %tls_ie_pcrel_hi(@var{symbol})
 345 The high 20 bits of relative address between pc and GOT entry.  It is
 346 usually used with the %pcrel_lo modifier to access the thread local
 347 variable @var{symbol} in TLS Initial Exec.
 348
 349 @smallexample
 350         la.tls.ie  a5, @var{symbol}
 351         add        a5, a5, tp
 352         load/store t0, 0(a5)
 353 @end smallexample
 354
 355 The pseudo la.tls.ie instruction can be expended to
 356
 357 @smallexample
 358 @var{label}:
 359         auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
 360         load  a5, %pcrel_lo(@var{label})(a5)     // R_RISCV_PCREL_LO12_I
 361 @end smallexample
 362
 363 @item %tls_gd_pcrel_hi(@var{symbol})
 364 The high 20 bits of relative address between pc and GOT entry.  It is
 365 usually used with the %pcrel_lo modifier to access the thread local variable
 366 @var{symbol} in TLS Global Dynamic.
 367
 368 @smallexample
 369         la.tls.gd  a0, @var{symbol}
 370         call       __tls_get_addr@@plt
 371         mv         a5, a0
 372         load/store t0, 0(a5)
 373 @end smallexample
 374
 375 The pseudo la.tls.gd instruction can be expended to
 376
 377 @smallexample
 378 @var{label}:
 379         auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
 380         addi  a0, a0, %pcrel_lo(@var{label})     // R_RISCV_PCREL_LO12_I
 381 @end smallexample
 382
 383 @end table
 384
 385 @node RISC-V-Formats
 386 @section RISC-V Instruction Formats
 387 @cindex instruction formats, risc-v
 388 @cindex RISC-V instruction formats
 389
 390 The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15
 391 instruction formats where some of the formats have multiple variants.
 392 For the @samp{.insn} pseudo directive the assembler recognizes some
 393 of the formats.
 394 Typically, the most general variant of the instruction format is used
 395 by the @samp{.insn} directive.
 396
 397 The following table lists the abbreviations used in the table of
 398 instruction formats:
 399
 400 @display
 401 @multitable @columnfractions .15 .40
 402 @item opcode @tab Unsigned immediate or opcode name for 7-bits opcode.
 403 @item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
 404 @item func7 @tab Unsigned immediate for 7-bits function code.
 405 @item func6 @tab Unsigned immediate for 6-bits function code.
 406 @item func4 @tab Unsigned immediate for 4-bits function code.
 407 @item func3 @tab Unsigned immediate for 3-bits function code.
 408 @item func2 @tab Unsigned immediate for 2-bits function code.
 409 @item rd @tab Destination register number for operand x, can be GPR or FPR.
 410 @item rd' @tab Destination register number for operand x,
 411 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 412 @item rs1 @tab First source register number for operand x, can be GPR or FPR.
 413 @item rs1' @tab First source register number for operand x,
 414 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 415 @item rs2 @tab Second source register number for operand x, can be GPR or FPR.
 416 @item rs2' @tab Second source register number for operand x,
 417 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 418 @item simm12 @tab Sign-extended 12-bit immediate for operand x.
 419 @item simm20 @tab Sign-extended 20-bit immediate for operand x.
 420 @item simm6 @tab Sign-extended 6-bit immediate for operand x.
 421 @item uimm5 @tab Unsigned 5-bit immediate for operand x.
 422 @item uimm6 @tab Unsigned 6-bit immediate for operand x.
 423 @item uimm8 @tab Unsigned 8-bit immediate for operand x.
 424 @item symbol @tab Symbol or lable reference for operand x.
 425 @end multitable
 426 @end display
 427
 428 The following table lists all available opcode name:
 429
 430 @table @code
 431 @item C0
 432 @item C1
 433 @item C2
 434 Opcode space for compressed instructions.
 435
 436 @item LOAD
 437 Opcode space for load instructions.
 438
 439 @item LOAD_FP
 440 Opcode space for floating-point load instructions.
 441
 442 @item STORE
 443 Opcode space for store instructions.
 444
 445 @item STORE_FP
 446 Opcode space for floating-point store instructions.
 447
 448 @item AUIPC
 449 Opcode space for auipc instruction.
 450
 451 @item LUI
 452 Opcode space for lui instruction.
 453
 454 @item BRANCH
 455 Opcode space for branch instructions.
 456
 457 @item JAL
 458 Opcode space for jal instruction.
 459
 460 @item JALR
 461 Opcode space for jalr instruction.
 462
 463 @item OP
 464 Opcode space for ALU instructions.
 465
 466 @item OP_32
 467 Opcode space for 32-bits ALU instructions.
 468
 469 @item OP_IMM
 470 Opcode space for ALU with immediate instructions.
 471
 472 @item OP_IMM_32
 473 Opcode space for 32-bits ALU with immediate instructions.
 474
 475 @item OP_FP
 476 Opcode space for floating-point operation instructions.
 477
 478 @item MADD
 479 Opcode space for madd instruction.
 480
 481 @item MSUB
 482 Opcode space for msub instruction.
 483
 484 @item NMADD
 485 Opcode space for nmadd instruction.
 486
 487 @item NMSUB
 488 Opcode space for msub instruction.
 489
 490 @item AMO
 491 Opcode space for atomic memory operation instructions.
 492
 493 @item MISC_MEM
 494 Opcode space for misc instructions.
 495
 496 @item SYSTEM
 497 Opcode space for system instructions.
 498
 499 @item CUSTOM_0
 500 @item CUSTOM_1
 501 @item CUSTOM_2
 502 @item CUSTOM_3
 503 Opcode space for customize instructions.
 504
 505 @end table
 506
 507 An instruction is two or four bytes in length and must be aligned
 508 on a 2 byte boundary. The first two bits of the instruction specify the
 509 length of the instruction, 00, 01 and 10 indicates a two byte instruction,
 510 11 indicates a four byte instruction.
 511
 512 The following table lists the RISC-V instruction formats that are available
 513 with the @samp{.insn} pseudo directive:
 514
 515 @table @code
 516 @item R type: .insn r opcode6, func3, func7, rd, rs1, rs2
 517 @verbatim
 518 +-------+-----+-----+-------+----+---------+
 519 | func7 | rs2 | rs1 | func3 | rd | opcode6 |
 520 +-------+-----+-----+-------+----+---------+
 521 31      25    20    15      12   7        0
 522 @end verbatim
 523
 524 @item R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3
 525 @itemx R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3
 526 @verbatim
 527 +-----+-------+-----+-----+-------+----+---------+
 528 | rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 |
 529 +-----+-------+-----+-----+-------+----+---------+
 530 31    27      25    20    15      12   7         0
 531 @end verbatim
 532
 533 @item I type: .insn i opcode6, func3, rd, rs1, simm12
 534 @itemx I type: .insn i opcode6, func3, rd, simm12(rs1)
 535 @verbatim
 536 +--------------+-----+-------+----+---------+
 537 | simm12[11:0] | rs1 | func3 | rd | opcode6 |
 538 +--------------+-----+-------+----+---------+
 539 31             20    15      12   7         0
 540 @end verbatim
 541
 542 @item S type: .insn s opcode6, func3, rs2, simm12(rs1)
 543 @verbatim
 544 +--------------+-----+-----+-------+-------------+---------+
 545 | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 |
 546 +--------------+-----+-----+-------+-------------+---------+
 547 31             25    20    15      12            7         0
 548 @end verbatim
 549
 550 @item B type: .insn s opcode6, func3, rs1, rs2, symbol
 551 @itemx SB type: .insn sb opcode6, func3, rs1, rs2, symbol
 552 @verbatim
 553 +-----------------+-----+-----+-------+----------------+---------+
 554 | simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 |
 555 +-----------------+-----+-----+-------+----------------+---------+
 556 31                25    20    15      12               7         0
 557 @end verbatim
 558
 559 @item U type: .insn u opcode6, rd, simm20
 560 @verbatim
 561 +--------------------------+----+---------+
 562 | simm20[20|10:1|11|19:12] | rd | opcode6 |
 563 +--------------------------+----+---------+
 564 31                         12   7         0
 565 @end verbatim
 566
 567 @item J type: .insn j opcode6, rd, symbol
 568 @itemx UJ type: .insn uj opcode6, rd, symbol
 569 @verbatim
 570 +------------+--------------+------------+---------------+----+---------+
 571 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 |
 572 +------------+--------------+------------+---------------+----+---------+
 573 31           30             21           20              12   7         0
 574 @end verbatim
 575
 576 @item CR type: .insn cr opcode2, func4, rd, rs2
 577 @verbatim
 578 +-------+--------+-----+---------+
 579 | func4 | rd/rs1 | rs2 | opcode2 |
 580 +-------+--------+-----+---------+
 581 15      12       7     2        0
 582 @end verbatim
 583
 584 @item CI type: .insn ci opcode2, func3, rd, simm6
 585 @verbatim
 586 +-------+----------+--------+------------+---------+
 587 | func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
 588 +-------+----------+--------+------------+---------+
 589 15      13         12       7            2         0
 590 @end verbatim
 591
 592 @item CIW type: .insn ciw opcode2, func3, rd', uimm8
 593 @verbatim
 594 +-------+------------+-----+---------+
 595 | func3 | uimm8[7:0] | rd' | opcode2 |
 596 +-------+-------- ---+-----+---------+
 597 15      13           5     2         0
 598 @end verbatim
 599
 600 @item CSS type: .insn css opcode2, func3, rd, uimm6
 601 @verbatim
 602 +-------+------------+----+---------+
 603 | func3 | uimm6[5:0] | rd | opcode2 |
 604 +-------+------------+----+---------+
 605 15      13           7    2         0
 606 @end verbatim
 607
 608 @item CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
 609 @verbatim
 610 +-------+------------+------+------------+------+---------+
 611 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
 612 +-------+------------+------+------------+------+---------+
 613 15      13           10     7            5      2         0
 614 @end verbatim
 615
 616 @item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
 617 @verbatim
 618 +-------+------------+------+------------+------+---------+
 619 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
 620 +-------+------------+------+------------+------+---------+
 621 15      13           10     7            5      2         0
 622 @end verbatim
 623
 624 @item CA type: .insn ca opcode2, func6, func2, rd', rs2'
 625 @verbatim
 626 +-- ----+----------+-------+------+---------+
 627 | func6 | rd'/rs1' | func2 | rs2' | opcode2 |
 628 +-------+----------+-------+------+---------+
 629 15      10         7       5      2         0
 630 @end verbatim
 631
 632 @item CB type: .insn cb opcode2, func3, rs1', symbol
 633 @verbatim
 634 +-------+--------------+------+------------------+---------+
 635 | func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
 636 +-------+--------------+------+------------------+---------+
 637 15      13             10     7                  2         0
 638 @end verbatim
 639
 640 @item CJ type: .insn cj opcode2, symbol
 641 @verbatim
 642 +-------+-------------------------------+---------+
 643 | func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
 644 +-------+-------------------------------+---------+
 645 15      13                              2         0
 646 @end verbatim
 647
 648
 649 @end table
 650
 651 For the complete list of all instruction format variants see
 652 The RISC-V Instruction Set Manual Volume I: User-Level ISA.
 653
 654 @node RISC-V-ATTRIBUTE
 655 @section RISC-V Object Attribute
 656 @cindex Object Attribute, RISC-V
 657
 658 RISC-V attributes have a string value if the tag number is odd and an integer
 659 value if the tag number is even.
 660
 661 @table @r
 662 @item Tag_RISCV_stack_align (4)
 663 Tag_RISCV_strict_align records the N-byte stack alignment for this object.  The
 664 default value is 16 for RV32I or RV64I, and 4 for RV32E.
 665
 666 The smallest value will be used if object files with different
 667 Tag_RISCV_stack_align values are merged.
 668
 669 @item Tag_RISCV_arch (5)
 670 Tag_RISCV_arch contains a string for the target architecture taken from the
 671 option @option{-march}.  Different architectures will be integrated into a
 672 superset when object files are merged.
 673
 674 Note that the version information of the target architecture must be presented
 675 explicitly in the attribute and abbreviations must be expanded.  The version
 676 information, if not given by @option{-march}, must be in accordance with the
 677 default specified by the tool.  For example, the architecture @code{RV32I} has
 678 to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
 679 for the default version of its base ISA.  On the other hand, the architecture
 680 @code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
 681 which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
 682 with default versions of the standard extensions.
 683
 684 @item Tag_RISCV_unaligned_access (6)
 685 Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
 686 memory accesses, and 1 for files that do allow unaligned memory accesses.
 687
 688 @item Tag_RISCV_priv_spec (8)
 689 @item Tag_RISCV_priv_spec_minor (10)
 690 @item Tag_RISCV_priv_spec_revision (12)
 691 Tag_RISCV_priv_spec contains the major/minor/revision version information of
 692 the privileged specification.  It will report errors if object files of
 693 different privileged specification versions are merged.
 694
 695 @end table
 696
 697 @node RISC-V-CustomExts
 698 @section RISC-V Custom (Vendor-Defined) Extensions
 699 @cindex custom (vendor-defined) extensions, RISC-V
 700 @cindex RISC-V custom (vendor-defined) extensions
 701
 702 The following table lists the custom (vendor-defined) RISC-V
 703 extensions supported and provides the location of their
 704 publicly-released documentation:
 705
 706 @table @r
 707 @item XTheadBa
 708 The XTheadBa extension provides instructions for address calculations.
 709
 710 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 711
 712 @item XTheadBb
 713 The XTheadBb extension provides instructions for basic bit-manipulation
 714
 715 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 716
 717 @item XTheadBs
 718 The XTheadBs extension provides single-bit instructions.
 719
 720 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 721
 722 @item XTheadCmo
 723 The XTheadCmo extension provides instructions for cache management.
 724
 725 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 726
 727 @item XTheadCondMov
 728 The XTheadCondMov extension provides instructions for conditional moves.
 729
 730 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 731
 732 @item XTheadFMemIdx
 733 The XTheadFMemIdx extension provides floating-point memory operations.
 734
 735 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 736
 737 @item XTheadFmv
 738 The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register.
 739
 740 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}.
 741
 742 @item XTheadInt
 743 The XTheadInt extension provides access to ISR stack management instructions.
 744
 745 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}.
 746
 747 @item XTheadMac
 748 The XTheadMac extension provides multiply-accumulate instructions.
 749
 750 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 751
 752 @item XTheadMemIdx
 753 The XTheadMemIdx extension provides GPR memory operations.
 754
 755 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 756
 757 @item XTheadMemPair
 758 The XTheadMemPair extension provides two-GP-register memory operations.
 759
 760 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 761
 762 @item XTheadSync
 763 The XTheadSync extension provides instructions for multi-processor synchronization.
 764
 765 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 766
 767 @end table