1 /* addsub.s Test file for AArch64 add-subtract instructions.
3 Copyright (C) 2012-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 // TODO: also cover the addsub_imm instructions.
27 .macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
28 // for 64-bit instruction, Rm is Xm when <extend> is explicitely
29 // or implicitly UXTX, SXTX or LSL; otherwise it Wm.
35 \op \rd, \rn, W\()\rm_n, \extend
37 \op \rd, \rn, W\()\rm_n, \extend #\amount
46 \op \rd, \rn, \rm_r\()\rm_n, \extend
48 \op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
53 * Emitting addsub_ext instruction
55 .macro do_addsub_ext type, op, Rn, reg, extend, amount
57 // normal add/adds/sub/subs
59 \op \reg\()16, \Rn, \reg\()1
62 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
64 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
69 // adds/subs with ZR as Rd
71 \op \reg\()ZR, \Rn, \reg\()1
74 adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend
76 adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend, \amount
85 \op \Rn, \reg\()1, \extend
87 \op \Rn, \reg\()1, \extend #\amount
95 * Optional extension and optional shift amount
97 .macro do_extend type, op, Rn, reg
99 // note that when SP is not used, the GAS will encode it as addsub_shift
100 do_addsub_ext \type, \op, \Rn, \reg
101 // optional absent <amount>
102 .irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
103 .irp amount, , 0, 1, 2, 3, 4
104 do_addsub_ext \type, \op, \Rn, \reg, \extend, \amount
107 // when <extend> is LSL, <amount> cannot be absent
108 // note that when SP is not used, the GAS will encode it as addsub_shift
109 .irp amount, 0, 1, 2, 3, 4
110 do_addsub_ext \type, \op, \Rn, \reg, LSL, \amount
115 * Leaf macro emitting addsub_shift instruction
117 .macro do_addsub_shift type, op, R, reg, shift, amount
119 // normal add/adds/sub/subs
121 \op \reg\()16, \R, \reg\()1
123 \op \reg\()16, \R, \reg\()1, \shift #\amount
127 // adds/subs with ZR as Rd
129 \op \reg\()ZR, \R, \reg\()1
131 \op \reg\()ZR, \R, \reg\()1, \shift #\amount
139 \op \R, \reg\()1, \shift #\amount
142 // sub/subs with ZR as Rn
144 \op \R, \reg\()ZR, \reg\()1
146 \op \R, \reg\()ZR, \reg\()1, \shift #\amount
154 * Optional shift and optional shift amount
156 .macro do_shift type, op, R, reg
158 do_addsub_shift \type, \op, \R, \reg
159 // optional absent <amount>
160 .irp shift, LSL, LSR, ASR
161 .irp amount, 0, 1, 2, 3, 4, 5, 16, 31
162 // amount cannot be absent when shift is present.
163 do_addsub_shift \type, \op, \R, \reg, \shift, \amount
166 do_addsub_shift \type, \op, \R, \reg, \shift, 63
173 * Add-subtract (extended register)
176 .irp op, ADD, ADDS, SUB, SUBS
177 do_extend 0, \op, W7, W
178 do_extend 0, \op, WSP, W
179 do_extend 0, \op, X7, X
180 do_extend 0, \op, SP, X
184 do_extend 1, \op, W7, W
185 do_extend 1, \op, WSP, W
186 do_extend 1, \op, X7, X
187 do_extend 1, \op, SP, X
191 do_extend 2, \op, W7, W
192 do_extend 2, \op, WSP, W
193 do_extend 2, \op, X7, X
194 do_extend 2, \op, SP, X
198 * Add-subtract (shift register)
201 .irp op, ADD, ADDS, SUB, SUBS
202 do_shift 0, \op, W7, W
203 do_shift 0, \op, X7, X
207 do_shift 1, \op, W7, W
208 do_shift 1, \op, X7, X
212 do_shift 2, \op, W7, W
213 do_shift 2, \op, X7, X
217 do_shift 3, \op, W7, W
218 do_shift 3, \op, X7, X
222 do_shift 2, \op, W7, W
223 do_shift 2, \op, X7, X
227 * Check for correct aliasing
231 do_shift 2, \op, WZR, W
232 do_shift 2, \op, XZR, X
236 do_shift 3, \op, W7, W
237 do_shift 3, \op, X7, X
238 do_shift 0, \op, WZR, W
239 do_shift 0, \op, XZR, X