gcc/ChangeLog

   1 2024-04-15  Georg-Johann Lay  <avr@gjlay.de>
   2
   3         * config/avr/avr-mcus.def: Add: avr16du14, avr16du20, avr16du28,
   4         avr16du32, avr32du14, avr32du20, avr32du28,  avr32du32.
   5         * doc/avr-mmcu.texi: Rebuild.
   6
   7 2024-04-15  Robin Dapp  <rdapp@ventanamicro.com>
   8
   9         PR target/114668
  10         * config/riscv/autovec.md: Add VLS.
  11
  12 2024-04-15  Richard Biener  <rguenther@suse.de>
  13
  14         PR gcov-profile/114715
  15         * gimplify.cc (gimplify_switch_expr): Set the location of the
  16         GIMPLE switch.
  17
  18 2024-04-15  H.J. Lu  <hjl.tools@gmail.com>
  19
  20         PR target/114696
  21         * config/i386/i386.md (isa): Add apx_ndd_64.
  22         (enabled): Likewise.
  23         (*add<dwi>3_doubleword): Change rjO to r,ro,jO with 8-bit
  24         signed integer constant and enable jO only for apx_ndd_64.
  25         (*add<dwi>3_doubleword_cc_overflow_1): Likewise.
  26         (*and<dwi>3_doubleword): Likewise.
  27         (*<code><dwi>3_doubleword): Likewise.
  28
  29 2024-04-15  Tamar Christina  <tamar.christina@arm.com>
  30
  31         PR tree-optimization/114403
  32         * tree-vect-loop.cc (vect_transform_loop): Adjust upper bounds for when
  33         peeling for gaps and early break.
  34
  35 2024-04-15  Jakub Jelinek  <jakub@redhat.com>
  36
  37         PR c++/114634
  38         * attribs.cc (diag_attr_exclusions): Set attrs[1] to NULL_TREE for
  39         decls with NULL TREE_TYPE.
  40
  41 2024-04-12  Andrew Carlotti  <andrew.carlotti@arm.com>
  42
  43         * config/aarch64/aarch64-option-extensions.def: Add RCPC to
  44         RCPC3 dependencies.
  45         * config/aarch64/aarch64.h (AARCH64_ISA_RCPC8_4): Add test for
  46         RCPC3 bit
  47
  48 2024-04-12  Andrew Carlotti  <andrew.carlotti@arm.com>
  49
  50         * config/aarch64/aarch64-arches.def: Add CSSC to V8_9A
  51         dependencies.
  52
  53 2024-04-12  Will Schmidt  <will_schmidt@linux.ibm.com>
  54             Peter Bergner  <bergner@linux.ibm.com>
  55
  56         PR target/101865
  57         * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
  58         TARGET_POWER8.
  59         * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
  60         OPTION_MASK_POWER8.
  61         * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8.
  62         (ISA_2_7_MASKS_SERVER): Likewise.
  63         * config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
  64         comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
  65         * config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
  66         * config/rs6000/rs6000.md (define_attr "isa"): Add p8.
  67         (define_attr "enabled"): Handle it.
  68         (define_insn "prefetch"): Use TARGET_POWER8.
  69         * config/rs6000/rs6000.opt (mpower8-internal): New.
  70
  71 2024-04-12  Jason Merrill  <jason@redhat.com>
  72             Patrick Palka  <ppalka@redhat.com>
  73
  74         PR c++/113141
  75         * doc/invoke.texi: Document -Wcast-user-defined.
  76
  77 2024-04-12  Tatsuyuki Ishi  <ishitatsuyuki@gmail.com>
  78
  79         * config/riscv/riscv.opt.urls: Regenerated.
  80
  81 2024-04-12  Andrew Pinski  <quic_apinski@quicinc.com>
  82
  83         PR tree-optimization/114666
  84         * match.pd (`!a?b:c`): Reject signed types for the condition.
  85         (`a?~t:t`): Likewise.
  86
  87 2024-04-12  Richard Sandiford  <richard.sandiford@arm.com>
  88
  89         * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Require
  90         all tiles to have the same suffix.
  91
  92 2024-04-12  Pan Li  <pan2.li@intel.com>
  93
  94         * config/riscv/riscv.cc (riscv_vector_float_type_p): Take int
  95         as the return value instead of unsigned.
  96         (riscv_vector_element_bitsize): Ditto.
  97         (riscv_vector_required_min_vlen): Ditto.
  98         (riscv_validate_vector_type): Take int type for local variable(s).
  99
 100 2024-04-12  Jakub Jelinek  <jakub@redhat.com>
 101
 102         * tree-cfg.cc (gimple_verify_flow_info): Make the misplaced
 103         returns_twice diagnostics translatable.
 104
 105 2024-04-12  Jakub Jelinek  <jakub@redhat.com>
 106
 107         PR sanitizer/114687
 108         * gimple-iterator.cc (gsi_safe_insert_before): Only use
 109         edge_before_returns_twice_call if bb_has_abnormal_pred.
 110         (gsi_safe_insert_seq_before): Likewise.
 111         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Only
 112         push to m_returns_twice_calls if bb_has_abnormal_pred.
 113
 114 2024-04-12  Pan Li  <pan2.li@intel.com>
 115
 116         PR target/114639
 117         * config/riscv/riscv.cc (riscv_function_value_regno_p): Add
 118         TARGET_VECTOR predicate for V_RETURN regno.
 119
 120 2024-04-11  David Faust  <david.faust@oracle.com>
 121
 122         * btfout.cc (btf_asm_type_ref): Convert IDs to BTF internally and
 123         fix potentially looking up wrong type for asm debug comment info.
 124         Split into...
 125         (btf_asm_datasec_type_ref): ... This. New.
 126         (btf_asm_datasec_entry): Call it here, instead of btf_asm_type_ref.
 127         (btf_asm_type, btf_asm_array, btf_asm_varent, btf_asm_sou_member)
 128         (btf_asm_func_arg, btf_asm_func_type): Adapt btf_asm_type_ref call.
 129
 130 2024-04-11  David Faust  <david.faust@oracle.com>
 131
 132         * btfout.cc (btf_asm_sou_member): Always emit non-representable
 133         bitfield members as having 'void' type.  Refactor slightly.
 134
 135 2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>
 136
 137         * config/aarch64/aarch64-option-extensions.def:
 138         Remove "memtag", "memtag2", "ssbs", "ssbs2", "ls64", "ls64_v"
 139         and "ls64_accdata" FMV features.
 140
 141 2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>
 142
 143         * config/aarch64/aarch64-option-extensions.def:
 144         Remove "flagm2", "sha1", "pmull", "dit", "dpb", "dpb2", "jscvt",
 145         "fcma", "rcpc2", "frintts", "dgh", "ebf16", "sve-bf16",
 146         "sve-ebf16", "sve-i8mm", "sve2-pmull128", "memtag3", "bti" and
 147         "wfxt" entries.
 148
 149 2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>
 150
 151         * config/aarch64/aarch64-option-extensions.def:
 152         Fix "rmd"->"rdm", and add FMV to "rdma".
 153         * config/aarch64/aarch64.cc (FEAT_RDMA): Define as FEAT_RDM.
 154
 155 2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>
 156
 157         * config/aarch64/aarch64.cc (compare_feature_masks):
 158         Use ARRAY_SIZE and >=0 for iteration bounds.
 159         (aarch64_mangle_decl_assembler_name): Use ARRAY_SIZE.
 160
 161 2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>
 162
 163         * config/aarch64/aarch64-option-extensions.def: Reorder FMV entries.
 164
 165 2024-04-11  Gaius Mulley  <gaiusmod2@gmail.com>
 166
 167         * doc/standards.texi (Language Standards Supported by GCC):
 168         Add Modula-2 language section.
 169
 170 2024-04-11  Jakub Jelinek  <jakub@redhat.com>
 171
 172         PR middle-end/110027
 173         * asan.cc (asan_emit_stack_protection): Assert offsets[0] is
 174         zero if there is no stack protect guard, otherwise
 175         -ASAN_RED_ZONE_SIZE.  If alignb > ASAN_RED_ZONE_SIZE and there is
 176         stack pointer guard, take the ASAN_RED_ZONE_SIZE bytes allocated at
 177         the top of the stack into account when computing base_align_bias.
 178         Recompute use_after_return_class from asan_frame_size + base_align_bias
 179         and set to -1 if that would overflow to 11.
 180
 181 2024-04-11  Richard Biener  <rguenther@suse.de>
 182
 183         PR tree-optimization/109596
 184         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Propagate
 185         debug stmts to nonexit->dest rather than exit->dest.
 186
 187 2024-04-11  Richard Biener  <rguenther@suse.de>
 188
 189         PR middle-end/114681
 190         * tree-inline.cc (copy_bb): Key on the remapped stmt
 191         to identify gconds to have condition coverage data remapped.
 192
 193 2024-04-11  Pan Li  <pan2.li@intel.com>
 194
 195         PR target/114639
 196         * config/riscv/riscv.cc (riscv_function_value_regno_p): New func
 197         impl for hook TARGET_FUNCTION_VALUE_REGNO_P.
 198         (riscv_get_raw_result_mode): New func imple for hook
 199         TARGET_GET_RAW_RESULT_MODE.
 200         (TARGET_FUNCTION_VALUE_REGNO_P): Impl the hook.
 201         (TARGET_GET_RAW_RESULT_MODE): Ditto.
 202         * config/riscv/riscv.h (V_RETURN): New macro for vector return.
 203         (GP_RETURN_FIRST): New macro for the first GPR in return.
 204         (GP_RETURN_LAST): New macro for the last GPR in return.
 205         (FP_RETURN_FIRST): Diito but for FPR.
 206         (FP_RETURN_LAST): Ditto.
 207         (FUNCTION_VALUE_REGNO_P): Remove as deprecated and replace by
 208         TARGET_FUNCTION_VALUE_REGNO_P.
 209
 210 2024-04-11  Indu Bhagat  <indu.bhagat@oracle.com>
 211
 212         * btfout.cc (btf_asm_type): Do not skip emitting members of
 213         unknown type.
 214
 215 2024-04-11  Indu Bhagat  <indu.bhagat@oracle.com>
 216
 217         PR debug/112878
 218         * dwarf2ctf.cc (gen_ctf_sou_type): Check for conditions before
 219         call to ctf_add_slice.  Use CTF_K_UNKNOWN type if fail.
 220
 221 2024-04-10  Marek Polacek  <polacek@redhat.com>
 222
 223         PR target/114606
 224         * config/i386/i386-options.cc (ix86_option_override_internal): Use
 225         opts_set rather than checking == CF_NONE.
 226
 227 2024-04-10  David Malcolm  <dmalcolm@redhat.com>
 228
 229         * doc/analyzer.texi: Various tweaks.
 230
 231 2024-04-10  Richard Biener  <rguenther@suse.de>
 232
 233         PR tree-optimization/114672
 234         * tree-ssa-math-opts.cc (convert_plusminus_to_widen): Only
 235         allow mode-precision results.
 236
 237 2024-04-10  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 238
 239         * config/aarch64/aarch64.cc (TARGET_C_BITINT_TYPE_INFO): Declare MACRO.
 240         (aarch64_bitint_type_info): New function.
 241         (aarch64_return_in_memory_1): Return large _BitInt's in memory.
 242         (aarch64_function_arg_alignment): Adapt to correctly return the ABI
 243         mandated alignment of _BitInt(N) where N > 128 as the alignment of
 244         TImode.
 245         (aarch64_composite_type_p): Return true for _BitInt(N), where N > 128.
 246
 247 2024-04-10  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 248
 249         * config/aarch64/aarch64.cc (bitint_or_aggr_of_bitint_p): New function.
 250         (aarch64_layout_arg): Don't emit diagnostics for types involving
 251         _BitInt(N).
 252
 253 2024-04-10  Jakub Jelinek  <jakub@redhat.com>
 254
 255         PR c++/114462
 256         * tree-core.h (enum annot_expr_kind): Add
 257         annot_expr_maybe_infinite_kind enumerator.
 258         * gimplify.cc (gimple_boolify): Handle annot_expr_maybe_infinite_kind.
 259         * tree-cfg.cc (replace_loop_annotate_in_block): Likewise.
 260         (replace_loop_annotate): Likewise.  Move loop->finite_p initialization
 261         before the replace_loop_annotate_in_block calls.
 262         * tree-pretty-print.cc (dump_generic_node): Handle
 263         annot_expr_maybe_infinite_kind.
 264
 265 2024-04-10  Richard Biener  <rguenther@suse.de>
 266
 267         Revert:
 268         2024-03-27  Segher Boessenkool  <segher@kernel.crashing.org>
 269
 270         PR rtl-optimization/101523
 271         * combine.cc (try_combine): Don't do a 2-insn combination if
 272         it does not in fact change I2.
 273
 274 2024-04-10  Peter Bergner  <bergner@linux.ibm.com>
 275
 276         PR target/101865
 277         * config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
 278         * config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
 279         OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete redundant
 280         OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
 281         (rs6000_opt_masks): Neuter the "direct-move" option.
 282         * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Replace
 283         OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
 284         comment.
 285         * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
 286         OPTION_MASK_DIRECT_MOVE.
 287         (OTHER_VSX_VECTOR_MASKS): Likewise.
 288         (POWERPC_MASKS): Likewise.
 289         * config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.
 290
 291 2024-04-10  Hongyu Wang  <hongyu.wang@intel.com>
 292
 293         * config/i386/sse.md (sha1msg1): Use "ja" instead of "Bm" for
 294         memory constraint.
 295         (sha1msg2): Likewise.
 296         (sha1nexte): Likewise.
 297         (sha1rnds4): Likewise.
 298         (sha256msg1): Likewise.
 299         (sha256msg2): Likewise.
 300         (sha256rnds2): Likewise.
 301         (aes<aesklvariant>u8): Use "jm" instead of "m" for memory
 302         constraint.
 303         (*aes<aeswideklvariant>u8): Likewise.
 304         (*encodekey128u32): Use "jr" instead of "r" for register
 305         constraints.
 306         (*encodekey256u32): Likewise.
 307
 308 2024-04-09  Juergen Christ  <jchrist@linux.ibm.com>
 309
 310         * config/s390/s390.cc (expand_perm_as_replicate): Implement.
 311         (vectorize_vec_perm_const_1): Call new function.
 312         * config/s390/vx-builtins.md (vec_splat<mode>): Change to...
 313         (@vec_splat<mode>): ...this.
 314
 315 2024-04-09  David Faust  <david.faust@oracle.com>
 316
 317         PR debug/114608
 318         * btfout.cc (btf_asm_datasec_entry): Only emit a symbol reference when
 319         generating BTF for BPF CO-RE target.
 320
 321 2024-04-09  Richard Ball  <richard.ball@arm.com>
 322
 323         * config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64):
 324         Add functions_nulls parameter to pragma_handlers.
 325         * config/aarch64/aarch64-protos.h: Likewise.
 326         * config/aarch64/aarch64-sve-builtins.h
 327         (enum handle_pragma_index): Add enum to count
 328         number of pragmas to be handled.
 329         * config/aarch64/aarch64-sve-builtins.cc
 330         (GTY): Add global variable for initial indexes
 331         and change overload_names to an array.
 332         (function_builder::function_builder):
 333         Add pragma handler information.
 334         (function_builder::add_function):
 335         Add code for overwriting previous
 336         registered_functions entries.
 337         (add_unique_function):
 338         Use an array to register overload_names
 339         for both pragma handler modes.
 340         (add_overloaded_function): Likewise.
 341         (init_builtins):
 342         Add functions_nulls parameter to pragma_handlers.
 343         (handle_arm_sve_h):
 344         Initialize pragma handler information.
 345         (handle_arm_neon_sve_bridge_h): Likewise.
 346         (handle_arm_sme_h): Likewise.
 347
 348 2024-04-09  Richard Biener  <rguenther@suse.de>
 349
 350         PR lto/114655
 351         * lto-wrapper.cc (merge_flto_options): Add force argument.
 352         (merge_and_complain): Do not force here.
 353         (run_gcc): But here to make the link-time -flto option override
 354         any compile-time one.
 355
 356 2024-04-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 357
 358         * config/rs6000/rtems.h (OS_MISSING_POWERPC64): Define.
 359
 360 2024-04-09  Jørgen Kvalsvik  <j@lambda.is>
 361
 362         PR gcov-profile/114601
 363         * tree-profile.cc (condition_uid): Guard fn->cond_uids access.
 364
 365 2024-04-09  Jakub Jelinek  <jakub@redhat.com>
 366
 367         PR target/114576
 368         * config/i386/i386.md (isa): Remove aes, add vaes_avx512vl.
 369         (enabled): Remove aes isa check, add vaes_avx512vl.
 370         * config/i386/sse.md (aesenc, aesenclast, aesdec, aesdeclast): Use
 371         jm instead of m for second alternative and emit {evex} prefix
 372         for it if !TARGET_AES.  Use noavx,avx,vaes_avx512vl isa attribute.
 373         (vaesdec_<mode>, vaesdeclast_<mode>, vaesenc_<mode>,
 374         vaesenclast_<mode>): Add second alternative with x instead of v
 375         and jm instead of m.
 376
 377 2024-04-09  Gaius Mulley  <gaiusmod2@gmail.com>
 378
 379         * doc/gm2.texi (Compiler options): Remove -fdebug-trace-quad.
 380         Remove -fdebug-trace-api.
 381         Add -fm2-debug-trace=.
 382
 383 2024-04-09  Yang Yujie  <yangyujie@loongson.cn>
 384
 385         PR target/113233
 386         * config/loongarch/loongarch.cc (loongarch_reg_init):
 387         Reinitialize the loongarch_regno_mode_ok cache.
 388         (loongarch_option_override): Same.
 389         (loongarch_save_restore_target_globals): Restore target globals.
 390         (loongarch_set_current_function): Restore the target contexts
 391         for functions.
 392         (TARGET_SET_CURRENT_FUNCTION): Define.
 393         * config/loongarch/loongarch.h (SWITCHABLE_TARGET): Enable
 394         switchable target context.
 395         * config/loongarch/loongarch-builtins.cc (loongarch_init_builtins):
 396         Initialize all builtin functions at startup.
 397         (loongarch_expand_builtin): Turn assertion of builtin availability
 398         into a test.
 399
 400 2024-04-09  Jørgen Kvalsvik  <j@lambda.is>
 401
 402         PR middle-end/114627
 403         * tree-profile.cc (instrument_decisions): Generate constant
 404         at the start of loop.
 405
 406 2024-04-09  Jørgen Kvalsvik  <j@lambda.is>
 407
 408         PR middle-end/114599
 409         * tree-inline.cc (copy_bb): Copy cond_uids into callee.
 410         (prepend_lexical_block): Remove outdated comment.
 411         (add_local_variables): Remove bad cond_uids copy.
 412
 413 2024-04-09  Jakub Jelinek  <jakub@redhat.com>
 414
 415         * expr.cc (convert_mode_scalar): Fix duplicated words in comment;
 416         into into -> it into.
 417         * function.h (function::cond_uids): Fix duplicated words in comment;
 418         same same -> same.
 419         * config/riscv/riscv-vector-costs.cc
 420         (costs::adjust_vect_cost_per_loop): Fix duplicated words in comment;
 421         model model -> model.
 422         * config/riscv/riscv-vector-builtins-shapes.cc (build_base): Fix
 423         duplicated words in comment; for for -> for.
 424         * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Fix
 425         duplicated words in comment; more more -> more.
 426         * config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Fix
 427         duplicated words in comment; be be -> be.
 428         * tree-profile.cc (masking_vectors): Fix duplicated words in comment;
 429         has has -> has, the the -> the.
 430         * value-range.cc (irange::set_range_from_bitmask): Fix duplicated
 431         words in comment; the the -> the.
 432         * gcov.cc (add_condition_counts): Fix duplicated words in comment;
 433         to to -> to.
 434         * vr-values.cc (get_scev_info): Fix duplicated words in comment;
 435         the the -> to the.
 436         * tree-vrp.cc (fully_replaceable): Fix duplicated words in comment;
 437         by by -> by.
 438         * mode-switching.cc (single_succ_confluence_n): Fix duplicated words
 439         in comment; the the -> the.
 440         * tree-ssa-phiopt.cc (value_replacement): Fix duplicated words in
 441         comment; can can -> we can.
 442         * gimple-range-phi.cc (phi_analyzer::process_phi): Fix duplicated words
 443         in comment; it it -> it is.
 444         * tree-ssa-sccvn.cc (visit_phi): Fix duplicated words in comment;
 445         to to -> to.
 446         * rtl-ssa/accesses.h (use_info::next_debug_insn_use): Fix duplicated
 447         words in comment; if if -> if.
 448         * doc/options.texi (InverseMask): Fix duplicated words; and and -> and.
 449         Change take to takes.
 450         * doc/invoke.texi (fanalyzer-undo-inlining): Fix duplicated words;
 451         be be -> be.
 452         (-minline-memops-threshold): Likewise.
 453
 454 2024-04-09  Jakub Jelinek  <jakub@redhat.com>
 455
 456         PR middle-end/114628
 457         * gimple-lower-bitint.cc (gimple_lower_bitint): Keep debug stmts
 458         before returns_twice calls as is, don't push them into arg_stmts
 459         vector/move to edges.
 460
 461 2024-04-09  Sergey Bugaev  <bugaevc@gmail.com>
 462
 463         * config.gcc: Recognize aarch64*-*-gnu* targets.
 464         * config/aarch64/aarch64-gnu.h: New file.
 465
 466 2024-04-09  Sergey Bugaev  <bugaevc@gmail.com>
 467
 468         * config/i386/gnu.h: Move GNU/Hurd STARTFILE_SPEC from here...
 469         * config/gnu.h: ...to here.
 470
 471 2024-04-09  Richard Biener  <rguenther@suse.de>
 472
 473         PR middle-end/114604
 474         * gimple-range.cc (enable_ranger): Initialize the global
 475         bitmap obstack.
 476         (disable_ranger): Release it.
 477
 478 2024-04-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 479
 480         * config.gcc (aarch64-*-rtems*): Add target makefile fragment
 481         t-aarch64-rtems.
 482         * config/aarch64/t-aarch64-rtems: New file.
 483
 484 2024-04-09  H.J. Lu  <hjl.tools@gmail.com>
 485
 486         PR target/114587
 487         * config/i386/i386-c.cc (ix86_target_macros_internal): Define
 488         __APX_INLINE_ASM_USE_GPR32__ for -mapx-inline-asm-use-gpr32.
 489
 490 2024-04-09  Kewen Lin  <linkw@linux.ibm.com>
 491             Andrew Pinski  <quic_apinski@quicinc.com>
 492
 493         PR target/88309
 494         * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Fix
 495         wrong align passed to function build_aligned_type.
 496         * tree-ssa-loop-prefetch.cc (is_miss_rate_acceptable): Add an
 497         assertion to ensure align_unit should be positive.
 498         * tree.cc (build_qualified_type): Update function comments.
 499
 500 2024-04-08  Uros Bizjak  <ubizjak@gmail.com>
 501
 502         PR rtl-optimization/112560
 503         * combine.cc (try_combine): Replace cc_use_loc with the entire
 504         new RTX only in case cc_use_loc satisfies COMPARISON_P predicate.
 505         Otherwise scan the entire cc_use_loc RTX for CC reg to be updated
 506         with a new mode.
 507         * config/i386/i386.md (@pushf<mode>2): Allow all CC modes for
 508         operand 1.
 509
 510 2024-04-08  Thomas Schwinge  <tschwinge@baylibre.com>
 511
 512         * config/gcn/gcn.opt (--param=gcn-preferred-vectorization-factor):
 513         New.
 514         * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode) Use it.
 515         * doc/invoke.texi (Optimize Options): Document it.
 516
 517 2024-04-08  Thomas Schwinge  <tschwinge@baylibre.com>
 518
 519         * doc/sourcebuild.texi (Effective-Target Keywords): Document
 520         'asm_goto_with_outputs'.  Add comment to 'lra'.
 521
 522 2024-04-08  Martin Jambor  <mjambor@suse.cz>
 523
 524         PR ipa/113359
 525         * ipa-icf-gimple.h (func_checker): New members
 526         safe_for_total_scalarization_p, m_total_scalarization_limit_known_p
 527         and m_total_scalarization_limit.
 528         (func_checker::func_checker): Initialize new member variables.
 529         * ipa-icf-gimple.cc: Include tree-sra.h.
 530         (func_checker::func_checker): Initialize new member variables.
 531         (func_checker::safe_for_total_scalarization_p): New function.
 532         (func_checker::compare_operand): Use the new function.
 533         * tree-sra.h (sra_get_max_scalarization_size): Declare.
 534         (sra_total_scalarization_would_copy_same_data_p): Likewise.
 535         * tree-sra.cc (prepare_iteration_over_array_elts): New function.
 536         (class sra_padding_collecting): New.
 537         (sra_padding_collecting::record_padding): Likewise.
 538         (scalarizable_type_p): Rename to totally_scalarizable_type_p.  Add
 539         ability to record padding when requested.
 540         (totally_scalarize_subtree): Split out gathering information necessary
 541         to iterate over array elements to prepare_iteration_over_array_elts.
 542         Fix errornous early exit.
 543         (analyze_all_variable_accesses): Adjust the call to
 544         totally_scalarizable_type_p.  Move determining of total scalariation
 545         size limit...
 546         (sra_get_max_scalarization_size): ...here.
 547         (check_ts_and_push_padding_to_vec): New function.
 548         (sra_total_scalarization_would_copy_same_data_p): Likewise.
 549
 550 2024-04-08  Martin Jambor  <mjambor@suse.cz>
 551
 552         PR ipa/113907
 553         * ipa-prop.h (class ipa_vr): Declare new overload of a member function
 554         equal_p.
 555         (ipa_jump_functions_equivalent_p): Declare.
 556         * ipa-prop.cc (ipa_vr::equal_p): New function.
 557         (ipa_agg_pass_through_jf_equivalent_p): Likewise.
 558         (ipa_agg_jump_functions_equivalent_p): Likewise.
 559         (ipa_jump_functions_equivalent_p): Likewise.
 560         * ipa-cp.h (values_equal_for_ipcp_p): Declare.
 561         * ipa-cp.cc (values_equal_for_ipcp_p): Make function public.
 562         * ipa-icf-gimple.cc: Include alloc-pool.h, symbol-summary.h, sreal.h,
 563         ipa-cp.h and ipa-prop.h.
 564         (func_checker::compare_gimple_call): Comapre jump functions.
 565
 566 2024-04-08  Richard Sandiford  <richard.sandiford@arm.com>
 567
 568         PR target/114607
 569         * config/aarch64/aarch64-sve-builtins-base.cc
 570         (svusdot_impl::expand): Fix botched attempt to swap the operands
 571         for svsudot.
 572
 573 2024-04-08  Tatsuyuki Ishi  <ishitatsuyuki@gmail.com>
 574
 575         * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
 576         * config.gcc: Add --with-tls configuration option to change the
 577         default TLS flavor.
 578         * config/riscv/riscv.h: Add TARGET_TLSDESC determined from
 579         -mtls-dialect and with_tls defaults.
 580         * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
 581         two TLS flavors.
 582         * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
 583         * config/riscv/riscv.md: Add instruction sequence for TLSDESC.
 584         * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
 585         sequence length data for TLSDESC.
 586         (riscv_legitimize_tls_address): Add lowering of TLSDESC.
 587         * doc/install.texi: Document --with-tls for RISC-V.
 588         * doc/invoke.texi: Document -mtls-dialect for RISC-V.
 589
 590 2024-04-08  Jakub Jelinek  <jakub@redhat.com>
 591
 592         PR target/114605
 593         * config/s390/s390.cc (s390_const_int_pool_entry_p): Punt
 594         if mem doesn't have MODE_INT mode, or pool constant doesn't
 595         have MODE_INT mode, or if pool constant mode is smaller than
 596         mem mode.  If mem mode is different from pool constant mode,
 597         try to simplify subreg.  If that doesn't work, punt, if it
 598         does, use the simplified constant instead of the constant pool
 599         constant.
 600         * config/s390/s390.md (movdi from const pool peephole): If
 601         either low or high 32-bit part is zero, just emit move insn
 602         instead of move + ior.
 603
 604 2024-04-08  Richard Biener  <rguenther@suse.de>
 605
 606         PR tree-optimization/114624
 607         * tree-scalar-evolution.cc (final_value_replacement_loop):
 608         Get at the PHI arg location before releasing the PHI node.
 609
 610 2024-04-08  Pan Li  <pan2.li@intel.com>
 611
 612         * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Pass
 613         required_ext arg when invoke add function.
 614         (build_th_loadstore): Ditto.
 615         (struct vcreate_def): Ditto.
 616         (struct read_vl_def): Ditto.
 617         (struct vlenb_def): Ditto.
 618         * config/riscv/riscv-vector-builtins.cc (function_builder::add_function):
 619         Introduce new arg required_ext to fill in the register func.
 620         (function_builder::add_unique_function): Ditto.
 621         (function_builder::add_overloaded_function): Ditto.
 622         (expand_builtin): Leverage required_extensions_specified to
 623         check if the required extension is provided.
 624         * config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): New
 625         func impl to convert the required_ext enum to the extension name.
 626         (required_extensions_specified): New func impl to predicate if
 627         the required extension is well feeded.
 628
 629 2024-04-08  Iain Sandoe  <iain@sandoe.co.uk>
 630
 631         * config/darwin.h (LINK_COMMAND_SPEC_A): Update coverage
 632         specs.
 633
 634 2024-04-08  demin.han  <demin.han@starfivetech.com>
 635
 636         * config/riscv/riscv-vector-costs.cc: Use length()
 637
 638 2024-04-08  Pan Li  <pan2.li@intel.com>
 639
 640         * config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): New
 641         struct to hold all intrinisc related flags.
 642         (riscv_pragma_intrinsic_flags_pollute): New func to pollute
 643         the intrinsic flags and backup original flags.
 644         (riscv_pragma_intrinsic_flags_restore): New func to restore
 645         the flags from the backup intrinsic flags.
 646         (riscv_pragma_intrinsic): Pollute the flags and register all
 647         possible builtin types and functions, then restore and reinit.
 648         * config/riscv/riscv-protos.h (reinit_builtins): New func
 649         decl to reinit after flags pollution.
 650         (riscv_option_override): New extern func decl.
 651         * config/riscv/riscv-vector-builtins.cc (register_builtin_types_on_null):
 652         New func to register builtin types if null.
 653         (DEF_RVV_TYPE): Ditto.
 654         (DEF_RVV_TUPLE_TYPE): Ditto.
 655         (reinit_builtins): New func impl to reinit after flags pollution.
 656         (expand_builtin): Return
 657         target rtx after error_at.
 658         * config/riscv/riscv.cc (riscv_vector_int_type_p): New predicate
 659         func to tell one tree type is integer or not.
 660         (riscv_vector_float_type_p): New predicate func to tell one tree
 661         type is float or not.
 662         (riscv_vector_element_bitsize): New func to get the element bitsize
 663         of a vector tree type.
 664         (riscv_vector_required_min_vlen): New func to get the required min vlen
 665         of a vector tree type.
 666         (riscv_validate_vector_type): New func to validate the tree type
 667         is valid on flags.
 668         (riscv_return_value_is_vector_type_p): Leverage the func
 669         riscv_validate_vector_type to do the tree type validation.
 670         (riscv_arguments_is_vector_type_p): Ditto.
 671         (riscv_override_options_internal): Ditto.
 672
 673 2024-04-08  Lulu Cheng  <chenglulu@loongson.cn>
 674
 675         PR target/112919
 676         * config/loongarch/loongarch-def.cc (la664_align): Newly defined
 677         function that sets alignment rules under the LA664 microarchitecture.
 678         * config/loongarch/loongarch-opts.cc
 679         (loongarch_target_option_override): If not optimizing for size, set
 680         the default alignment to what the target wants.
 681         * config/loongarch/loongarch-tune.h (struct loongarch_align): Add
 682         new member variables jump and loop.
 683
 684 2024-04-06  H.J. Lu  <hjl.tools@gmail.com>
 685
 686         PR target/114590
 687         * config/i386/i386.md (x86_64_shld): Use explicit shift count in
 688         AT&T syntax.
 689         (x86_64_shld_ndd): Likewise.
 690         (x86_shld): Likewise.
 691         (x86_shld_ndd): Likewise.
 692         (x86_64_shrd): Likewise.
 693         (x86_64_shrd_ndd): Likewise.
 694         (x86_shrd): Likewise.
 695         (x86_shrd_ndd): Likewise.
 696
 697 2024-04-06  Jørgen Kvalsvik  <j@lambda.is>
 698
 699         PR middle-end/114599
 700         * tree-inline.cc (add_local_variables): Copy cond_uids mappings.
 701
 702 2024-04-05  David Malcolm  <dmalcolm@redhat.com>
 703
 704         PR analyzer/114588
 705         * diagnostic-color.cc (color_dict): Add "valid" and "invalid" as
 706         color capability names.
 707         * doc/invoke.texi: Document them in description of GCC_COLORS.
 708         * text-art/style.cc: Include "diagnostic-color.h".
 709         (text_art::get_style_from_color_cap_name): New.
 710         * text-art/types.h (get_style_from_color_cap_name): New decl.
 711
 712 2024-04-05  Alex Coplan  <alex.coplan@arm.com>
 713
 714         * config/aarch64/aarch64-ldp-fusion.cc (struct alias_walker):
 715         Fix double space after const qualifier on valid ().
 716
 717 2024-04-05  Martin Jambor  <mjambor@suse.cz>
 718
 719         PR ipa/113964
 720         * ipa-param-manipulation.cc (ipa_param_adjustments::modify_call):
 721         Force values obtined through pass-through maps to the expected
 722         split type.
 723
 724 2024-04-05  Mark Wielaard  <mark@klomp.org>
 725
 726         * common.opt.urls: Regenerate.
 727
 728 2024-04-05  Richard Sandiford  <richard.sandiford@arm.com>
 729
 730         PR target/114603
 731         * config/aarch64/aarch64-sve.md (@aarch64_pred_cnot<mode>): Replace
 732         with...
 733         (@aarch64_ptrue_cnot<mode>): ...this, requiring operand 1 to be
 734         a ptrue.
 735         (*cnot<mode>): Require operand 1 to be a ptrue.
 736         * config/aarch64/aarch64-sve-builtins-base.cc (svcnot_impl::expand):
 737         Use aarch64_ptrue_cnot<mode> for _x operations that are predicated
 738         with a ptrue.  Represent other _x operations as fully-defined _m
 739         operations.
 740
 741 2024-04-05  Jakub Jelinek  <jakub@redhat.com>
 742
 743         PR tree-optimization/114566
 744         * tree-vect-loop.cc (update_epilogue_loop_vinfo): Don't clear
 745         base_misaligned.
 746
 747 2024-04-05  Richard Biener  <rguenther@suse.de>
 748
 749         PR middle-end/114599
 750         PR gcov-profile/114115
 751         * symtab.cc (ifunc_ref_map): Do not use auto_bitmap.
 752         (is_caller_ifunc_resolver): Optimize bitmap_bit_p/bitmap_set_bit
 753         pair.
 754         (symtab_node::check_ifunc_callee_symtab_nodes): Properly
 755         allocate ifunc_ref_map here.
 756
 757 2024-04-04  Martin Jambor  <mjambor@suse.cz>
 758
 759         PR ipa/111571
 760         * ipa-param-manipulation.cc
 761         (ipa_param_body_adjustments::common_initialization): Avoid creating
 762         duplicate replacement entries.
 763
 764 2024-04-04  Vladimir N. Makarov  <vmakarov@redhat.com>
 765
 766         PR rtl-optimization/114415
 767         * sched-deps.cc (add_insn_mem_dependence): Add memory check for mem argument.
 768         (sched_analyze_1): Treat stack pointer modification as memory read.
 769         (sched_analyze_2, sched_analyze_insn): Add memory guard for processing pending_read_mems.
 770         * sched-int.h (deps_desc): Add comment to pending_read_mems.
 771
 772 2024-04-04  Tobias Burnus  <tburnus@baylibre.com>
 773
 774         * config/nvptx/mkoffload.cc (main): Call
 775         gcc_init_libintl and diagnostic_color_init.
 776
 777 2024-04-04  H.J. Lu  <hjl.tools@gmail.com>
 778
 779         PR target/114587
 780         * config/i386/i386-c.cc (ix86_target_macros_internal): Define
 781         __APX_F__ when APX is enabled.
 782
 783 2024-04-04  Jørgen Kvalsvik  <j@lambda.is>
 784
 785         * builtins.cc (expand_builtin_fork_or_exec): Check
 786         condition_coverage_flag.
 787         * collect2.cc (main): Add -fno-condition-coverage to OBSTACK.
 788         * common.opt: Add new options -fcondition-coverage and
 789         -Wcoverage-too-many-conditions.
 790         * doc/gcov.texi: Add --conditions documentation.
 791         * doc/invoke.texi: Add -fcondition-coverage documentation.
 792         * function.cc (free_after_compilation): Free cond_uids.
 793         * function.h (struct function): Add cond_uids.
 794         * gcc.cc: Link gcov on -fcondition-coverage.
 795         * gcov-counter.def (GCOV_COUNTER_CONDS): New.
 796         * gcov-dump.cc (tag_conditions): New.
 797         * gcov-io.h (GCOV_TAG_CONDS): New.
 798         (GCOV_TAG_CONDS_LENGTH): New.
 799         (GCOV_TAG_CONDS_NUM): New.
 800         * gcov.cc (class condition_info): New.
 801         (condition_info::condition_info): New.
 802         (condition_info::popcount): New.
 803         (struct coverage_info): New.
 804         (add_condition_counts): New.
 805         (output_conditions): New.
 806         (print_usage): Add -g, --conditions.
 807         (process_args): Likewise.
 808         (output_intermediate_json_line): Output conditions.
 809         (read_graph_file): Read condition counters.
 810         (read_count_file): Likewise.
 811         (file_summary): Print conditions.
 812         (accumulate_line_info): Accumulate conditions.
 813         (output_line_details): Print conditions.
 814         * gimplify.cc (next_cond_uid): New.
 815         (reset_cond_uid): New.
 816         (shortcut_cond_r): Set condition discriminator.
 817         (tag_shortcut_cond): New.
 818         (gimple_associate_condition_with_expr): New.
 819         (shortcut_cond_expr): Set condition discriminator.
 820         (gimplify_cond_expr): Likewise.
 821         (gimplify_function_tree): Call reset_cond_uid.
 822         * ipa-inline.cc (can_early_inline_edge_p): Check
 823         condition_coverage_flag.
 824         * ipa-split.cc (pass_split_functions::gate): Likewise.
 825         * passes.cc (finish_optimization_passes): Likewise.
 826         * profile.cc (struct condcov): New declaration.
 827         (cov_length): Likewise.
 828         (cov_blocks): Likewise.
 829         (cov_masks): Likewise.
 830         (cov_maps): Likewise.
 831         (cov_free): Likewise.
 832         (instrument_decisions): New.
 833         (read_thunk_profile): Control output to file.
 834         (branch_prob): Call find_conditions, instrument_decisions.
 835         (init_branch_prob): Add total_num_conds.
 836         (end_branch_prob): Likewise.
 837         * tree-core.h (struct tree_exp): Add condition_uid.
 838         * tree-profile.cc (struct conds_ctx): New.
 839         (CONDITIONS_MAX_TERMS): New.
 840         (EDGE_CONDITION): New.
 841         (topological_cmp): New.
 842         (index_of): New.
 843         (single_p): New.
 844         (single_edge): New.
 845         (contract_edge_up): New.
 846         (struct outcomes): New.
 847         (conditional_succs): New.
 848         (condition_index): New.
 849         (condition_uid): New.
 850         (masking_vectors): New.
 851         (emit_assign): New.
 852         (emit_bitwise_op): New.
 853         (make_top_index_visit): New.
 854         (make_top_index): New.
 855         (paths_between): New.
 856         (struct condcov): New.
 857         (cov_length): New.
 858         (cov_blocks): New.
 859         (cov_masks): New.
 860         (cov_maps): New.
 861         (cov_free): New.
 862         (find_conditions): New.
 863         (struct counters): New.
 864         (find_counters): New.
 865         (resolve_counter): New.
 866         (resolve_counters): New.
 867         (instrument_decisions): New.
 868         (tree_profiling): Check condition_coverage_flag.
 869         (pass_ipa_tree_profile::gate): Likewise.
 870         * tree.h (SET_EXPR_UID): New.
 871         (EXPR_COND_UID): New.
 872
 873 2024-04-04  Richard Sandiford  <richard.sandiford@arm.com>
 874
 875         PR target/114577
 876         * config/aarch64/aarch64-sve-builtins.h (aarch64_sve::lookup_fndecl):
 877         Declare.
 878         * config/aarch64/aarch64-sve-builtins.cc (aarch64_sve::lookup_fndecl):
 879         New function.
 880         * config/aarch64/aarch64-sve-builtins-base.cc (is_undef): Likewise.
 881         (svset_neonq_impl::expand): Optimise expansions whose first argument
 882         is undefined.
 883
 884 2024-04-04  Richard Biener  <rguenther@suse.de>
 885
 886         PR tree-optimization/114485
 887         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
 888         vect_step_op_neg isn't OK for partial vectors but only
 889         for unknown niter.
 890
 891 2024-04-04  Jakub Jelinek  <jakub@redhat.com>
 892
 893         PR c++/114537
 894         * fold-const.cc (native_encode_initializer): Look through
 895         NON_LVALUE_EXPR if val is INTEGER_CST.
 896
 897 2024-04-04  Jakub Jelinek  <jakub@redhat.com>
 898
 899         PR tree-optimization/114555
 900         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
 901         m_bitfld_load and save_cast_conditional add any needed PHIs
 902         and adjust t4 accordingly.
 903
 904 2024-04-04  Richard Biener  <rguenther@suse.de>
 905
 906         PR tree-optimization/114551
 907         * tree-ssa-loop-split.cc (split_loop): If the guard is
 908         only conditionally evaluated rewrite computations with
 909         possibly undefined overflow to unsigned arithmetic.
 910
 911 2024-04-04  Eugene Rozenfeld  <erozen@microsoft.com>
 912
 913         PR gcov-profile/113765
 914         * auto-profile.cc (afdo_annotate_cfg): Don't set full_profile to true
 915
 916 2024-04-03  Mark Wielaard  <mark@klomp.org>
 917
 918         * config/i386/i386.opt.urls: Regenerate.
 919
 920 2024-04-03  H.J. Lu  <hjl.tools@gmail.com>
 921
 922         PR tree-optimization/114115
 923         * cgraph.h (symtab_node): Add check_ifunc_callee_symtab_nodes.
 924         (cgraph_node): Add called_by_ifunc_resolver.
 925         * cgraphunit.cc (symbol_table::compile): Call
 926         symtab_node::check_ifunc_callee_symtab_nodes.
 927         * symtab.cc (check_ifunc_resolver): New.
 928         (ifunc_ref_map): Likewise.
 929         (is_caller_ifunc_resolver): Likewise.
 930         (symtab_node::check_ifunc_callee_symtab_nodes): Likewise.
 931         * tree-profile.cc (gimple_gen_ic_func_profiler): Disable indirect
 932         call profiling for IFUNC resolvers and their callees.
 933
 934 2024-04-03  Tobias Burnus  <tburnus@baylibre.com>
 935
 936         * lto-wrapper.cc (compile_offload_image): Prefix 'offload_args'
 937         suffix by the target name.
 938
 939 2024-04-03  Tobias Burnus  <tburnus@baylibre.com>
 940
 941         * doc/install.texi (amdgcn-*-amdhsa): Update Newlib recommendation
 942         and update wording for LLVM 18 release.
 943
 944 2024-04-03  Tobias Burnus  <tburnus@baylibre.com>
 945
 946         PR other/111966
 947         * config/gcn/mkoffload.cc (get_arch): New; moved -march= flag
 948         handling from ...
 949         (main): ... here; call it to handle --with-arch config option
 950         and -march= commandline.
 951
 952 2024-04-03  Jakub Jelinek  <jakub@redhat.com>
 953
 954         PR middle-end/114552
 955         * expr.cc (emit_push_insn): Only use store_constructor for
 956         immediate_const_ctor_p if int_expr_size matches size.
 957
 958 2024-04-03  Richard Biener  <rguenther@suse.de>
 959
 960         PR tree-optimization/114557
 961         PR tree-optimization/114480
 962         * tree-phinodes.cc (release_phi_node): Return PHIs from
 963         allocation buckets not covered by free_phinodes to GC.
 964         (remove_phi_node): Release the PHI LHS before freeing the
 965         PHI node.
 966         * tree-vect-loop.cc (vectorizable_live_operation): Get PHI lhs
 967         before releasing it.
 968
 969 2024-04-03  Jiahao Xu  <xujiahao@loongson.cn>
 970
 971         * config/loongarch/lasx.md: Remove unused code.
 972         * config/loongarch/loongarch-protos.h
 973         (loongarch_split_lsx_copy_d): Remove.
 974         (loongarch_split_lsx_insert_d): Ditto.
 975         (loongarch_split_lsx_fill_d): Ditto.
 976         * config/loongarch/loongarch.cc
 977         (loongarch_split_lsx_copy_d): Ditto.
 978         (loongarch_split_lsx_insert_d): Ditto.
 979         (loongarch_split_lsx_fill_d): Ditto.
 980         * config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter.
 981         (lsx_vpickve2gr_<lsxfmt_f>): Ditto.
 982         (abs<mode>2): Remove expander.
 983         (vabs<mode>2): Rename 2 abs<mode>2.
 984
 985 2024-04-02  Christophe Lyon  <christophe.lyon@linaro.org>
 986
 987         * config/aarch64/aarch64-option-extensions.def: Fix comment.
 988
 989 2024-04-02  Tom Tromey  <tromey@adacore.com>
 990
 991         * dwarf2out.cc (print_dw_val) <dw_val_class_loc>: Don't
 992         print newline when not recursing.
 993
 994 2024-04-02  Iain Sandoe  <iain@sandoe.co.uk>
 995
 996         * config/darwin.cc (darwin_override_options): Update the
 997         clang major version value in the dsymutil check.
 998
 999 2024-04-02  Iain Sandoe  <iain@sandoe.co.uk>
1000
1001         * config/darwin.cc (darwin_override_options): Reduce the debug
1002         level to 2 if dsymutil cannot handle .macinfo sections.
1003
1004 2024-04-02  Yang Yujie  <yangyujie@loongson.cn>
1005
1006         * config/loongarch/t-loongarch: Add loongarch-def-arrays.h
1007         to OPTION_H_EXTRA.
1008
1009 2024-04-02  mengqinggang  <mengqinggang@loongson.cn>
1010             Lulu Cheng  <chenglulu@loongson.cn>
1011             Xi Ruoyao  <xry111@xry111.site>
1012
1013         * config.gcc: Add --with-tls option to change TLS flavor.
1014         * config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to
1015         configure TLS flavor.
1016         * config/loongarch/loongarch-def.h (struct loongarch_target): Add
1017         tls_dialect.
1018         * config/loongarch/loongarch-driver.cc (la_driver_init): Add tls
1019         flavor.
1020         * config/loongarch/loongarch-opts.cc (loongarch_init_target): Add
1021         tls_dialect.
1022         (loongarch_config_target): Ditto.
1023         (loongarch_update_gcc_opt_status): Ditto.
1024         * config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto.
1025         (TARGET_TLS_DESC): New define.
1026         * config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS
1027         DESC instructions sequence length.
1028         (loongarch_legitimize_tls_address): New TLS DESC instruction sequence.
1029         (loongarch_option_override_internal): Add la_opt_tls_dialect.
1030         (loongarch_option_restore): Add la_target.tls_dialect.
1031         * config/loongarch/loongarch.md (@got_load_tls_desc<mode>): Normal
1032         code model for TLS DESC.
1033         (got_load_tls_desc_off64): Extreme cmode model for TLS DESC.
1034         * config/loongarch/loongarch.opt: Regenerate.
1035         * config/loongarch/loongarch.opt.urls: Ditto.
1036         * doc/invoke.texi: Add a description of the compilation option
1037         '-mtls-dialect={trad,desc}'.
1038
1039 2024-04-02  Lulu Cheng  <chenglulu@loongson.cn>
1040
1041         * config/loongarch/loongarch.opt.urls: Regenerate.
1042
1043 2024-04-01  Yang Yujie  <yangyujie@loongson.cn>
1044
1045         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
1046         aliases to -mrecip={all,none}, respectively.
1047         * config/loongarch/loongarch.opt: Regenerate.
1048         * config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to...
1049         (ABI_FPU64_P): ...this.
1050         (ABI_FPU_32): Rename to...
1051         (ABI_FPU32_P): ...this.
1052         (ABI_FPU_NONE): Rename to...
1053         (ABI_NOFPU_P): ...this.
1054         (ABI_LP64_P): Define.
1055         * config/loongarch/loongarch.cc (loongarch_init_print_operand_punct):
1056         Merged into loongarch_global_init.
1057         (loongarch_cpu_option_override): Renamed to
1058         loongarch_target_option_override.
1059         (loongarch_option_override_internal): Move the work after
1060         loongarch_config_target into loongarch_target_option_override.
1061         (loongarch_global_init): Define.
1062         (INIT_TARGET_FLAG): Move to loongarch-opts.cc.
1063         (loongarch_option_override): Call loongarch_global_init
1064         separately.
1065         * config/loongarch/loongarch-opts.cc (loongarch_parse_mrecip_scheme):
1066         Split the parsing of -mrecip=<string> from
1067         loongarch_option_override_internal.
1068         (loongarch_generate_mrecip_scheme): Define. Split from
1069         loongarch_option_override_internal.
1070         (loongarch_target_option_override): Define. Renamed from
1071         loongarch_cpu_option_override.
1072         (loongarch_init_misc_options): Define. Split from
1073         loongarch_option_override_internal.
1074         (INIT_TARGET_FLAG): Move from loongarch.cc.
1075         * config/loongarch/loongarch-opts.h (loongarch_target_option_override):
1076         New prototype.
1077         (loongarch_parse_mrecip_scheme): New prototype.
1078         (loongarch_init_misc_options): New prototype.
1079         (TARGET_ABI_LP64): Simplify with ABI_LP64_P.
1080         * config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify.
1081         Do not reference specific CPU architecture (LA664).
1082         (TARGET_RECIP_SQRT): Same.
1083         (TARGET_RECIP_RSQRT): Same.
1084         (TARGET_RECIP_VEC_DIV): Same.
1085         (TARGET_RECIP_VEC_SQRT): Same.
1086         (TARGET_RECIP_VEC_RSQRT): Same.
1087
1088 2024-04-01  Lulu Cheng  <chenglulu@loongson.cn>
1089
1090         * doc/invoke.texi: Add descriptions for the compilation
1091         options.
1092
1093 2024-03-31  Jeff Law  <jlaw@ventanamicro.com>
1094
1095         * config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
1096         and sfb_alu.
1097
1098 2024-03-31  Pan Li  <pan2.li@intel.com>
1099
1100         * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
1101         the term built-in over builtin.
1102
1103 2024-03-31  Pan Li  <pan2.li@intel.com>
1104
1105         * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
1106         Remove unused var decl.
1107
1108 2024-03-30  Xi Ruoyao  <xry111@xry111.site>
1109
1110         PR target/114175
1111         * config/mips/mips.cc (mips_setup_incoming_varargs): Only skip
1112         mips_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
1113         functions if arg.type is NULL.
1114
1115 2024-03-29  Andrew Pinski  <quic_apinski@quicinc.com>
1116
1117         * lto-compress.cc (lto_end_uncompression): Use
1118         fatal_error instead of internal_error when ZSTD
1119         is not enabled.
1120
1121 2024-03-28  Jeff Law  <jlaw@ventanamicro.com>
1122
1123         * config/h8300/extensions.md (zero_extendqihi*): Add output
1124         template for reg->reg case where the regs don't match.
1125
1126 2024-03-28  Gaius Mulley  <(no_default)>
1127
1128         PR modula2/114517
1129         * doc/gm2.texi: Mention gm2 treats a # in the first column
1130         as a preprocessor directive unless -fno-cpp is supplied.
1131
1132 2024-03-28  Jakub Jelinek  <jakub@redhat.com>
1133
1134         * predict.cc (estimate_bb_frequencies): Fix comment typo,
1135         scalling -> scaling.
1136
1137 2024-03-28  Jakub Jelinek  <jakub@redhat.com>
1138
1139         PR tree-optimization/112303
1140         * profile-count.h (profile_count::operator+): Perform
1141         addition in uint64_t variable and set m_val to MIN of that
1142         val and max_count.
1143         (profile_count::operator+=): Likewise.
1144         (profile_count::operator-=): Formatting fix.
1145         (profile_count::apply_probability): Use safe_scale_64bit
1146         even in the int overload.
1147
1148 2024-03-28  Jan Hubicka  <jh@suse.cz>
1149
1150         PR middle-end/113907
1151         * ipa-icf.cc (sem_function::init): Hash PHI operands
1152         (sem_function::compare_phi_node): Add argument about preserving order
1153
1154 2024-03-28  Richard Biener  <rguenther@suse.de>
1155
1156         PR middle-end/114480
1157         * cfganal.cc (compute_idf): Use simpler bitmap iteration,
1158         touch work_set only when phi_insertion_points changed.
1159
1160 2024-03-28  Palmer Dabbelt  <palmer@rivosinc.com>
1161
1162         * config/riscv/riscv.h (REGISTER_NAMES): Add vxsat.
1163
1164 2024-03-27  Segher Boessenkool  <segher@kernel.crashing.org>
1165
1166         PR rtl-optimization/101523
1167         * combine.cc (try_combine): Don't do a 2-insn combination if
1168         it does not in fact change I2.
1169
1170 2024-03-27  Jakub Jelinek  <jakub@redhat.com>
1171
1172         * doc/invoke.texi (Spec Files): Use @var{S} instead of S,
1173         @var{X} instead of X etc. for other placeholders.
1174
1175 2024-03-27  Richard Biener  <rguenther@suse.de>
1176
1177         PR tree-optimization/114057
1178         * tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Mark
1179         BB reduction remain defs as scalar uses.
1180
1181 2024-03-27  Victor Do Nascimento  <victor.donascimento@arm.com>
1182
1183         * config/aarch64/aarch64-option-extensions.def (rcpc3):
1184         Fix FEATURE_STRING field to "lrcpc3".
1185
1186 2024-03-27  Victor Do Nascimento  <victor.donascimento@arm.com>
1187
1188         * config/aarch64/aarch64-option-extensions.def: Add LSE128
1189         AARCH64_OPT_EXTENSION, adding it as a dependency for the D128
1190         feature.
1191         * doc/invoke.texi (AArch64 Options): Document +lse128.
1192
1193 2024-03-26  Richard Sandiford  <richard.sandiford@arm.com>
1194
1195         * config/aarch64/aarch64-feature-deps.h: Use constexpr for
1196         out-of-line statics.
1197
1198 2024-03-26  Cupertino Miranda  <cupertino.miranda@oracle.com>
1199
1200         PR target/114431
1201         * btfout.cc (get_name_for_datasec_entry): Add function.
1202         (btf_asm_datasec_entry): Print label when possible.
1203
1204 2024-03-26  Richard Ball  <richard.ball@arm.com>
1205
1206         PR target/114272
1207         * config/aarch64/aarch64-cores.def (AARCH64_CORE):
1208         Change SCHEDULER_IDENT from cortexa55 to cortexa53
1209         for Cortex-A510 and Cortex-A520.
1210
1211 2024-03-26  Jakub Jelinek  <jakub@redhat.com>
1212
1213         PR middle-end/111151
1214         * fold-const.cc (extract_muldiv_1) <case MAX_EXPR>: Punt for
1215         MULT_EXPR altogether, or for MAX_EXPR if c is -1.
1216
1217 2024-03-26  Jakub Jelinek  <jakub@redhat.com>
1218
1219         PR sanitizer/111736
1220         * tsan.cc (instrument_expr): Punt on non-generic address space
1221         accesses.
1222
1223 2024-03-26  Richard Biener  <rguenther@suse.de>
1224
1225         PR tree-optimization/114471
1226         * tree-vect-stmts.cc (vectorizable_operation): Verify operand
1227         types are compatible with the result type.
1228
1229 2024-03-26  Richard Biener  <rguenther@suse.de>
1230
1231         PR tree-optimization/114464
1232         * tree-vect-loop.cc (vectorizable_recurr): Verify the latch
1233         vector type is compatible with what we chose for the recurrence.
1234
1235 2024-03-26  Jakub Jelinek  <jakub@redhat.com>
1236
1237         * cfgloopmanip.cc (update_loop_exit_probability_scale_dom_bbs):
1238         Fix comment typo - multple -> multiple.
1239         * config/i386/x86-tune.def (X86_TUNE_ACCUMULATE_OUTGOING_ARGS):
1240         Likewise.
1241
1242 2024-03-26  YunQiang Su  <syq@gcc.gnu.org>
1243
1244         * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine
1245         __mips_strict_alignment if STRICT_ALIGNMENT.
1246
1247 2024-03-25  Richard Biener  <rguenther@suse.de>
1248
1249         * config.gcc (amdgcn): Add gfx1036 entries.
1250         * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
1251         (gcn_local_sym_hash): Likewise.
1252         * config/gcn/gcn-opts.h (enum processor_type): Likewise.
1253         (TARGET_GFX1036): New macro.
1254         * config/gcn/gcn.cc (gcn_option_override): Handle gfx1036.
1255         (gcn_omp_device_kind_arch_isa): Likewise.
1256         (output_file_start): Likewise.
1257         * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__.
1258         (TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__.
1259         * config/gcn/gcn.opt: Add gfx1036.
1260         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New.
1261         (main): Handle gfx1036.
1262         * config/gcn/t-omp-device: Add gfx1036 isa.
1263         * doc/install.texi (amdgcn): Add gfx1036.
1264         * doc/invoke.texi (-march): Likewise.
1265
1266 2024-03-25  Pan Li  <pan2.li@intel.com>
1267
1268         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
1269         when V is disabled and init the RVV types and intrinic APIs.
1270         * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
1271         error if V ext is disabled.
1272         * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
1273         Ditto.
1274         (riscv_arguments_is_vector_type_p): Ditto.
1275         (riscv_vector_cc_function_p): Ditto.
1276         * config/riscv/riscv_vector.h: Remove error if V is disable.
1277
1278 2024-03-23  John David Anglin  <danglin@gcc.gnu.org>
1279
1280         * config/pa/pa.cc (pa_output_global_address): Handle
1281         UNSPEC_DLTIND14R addresses.
1282         * config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
1283         UNSPEC_DLTIND14R address.
1284
1285 2024-03-23  Jakub Jelinek  <jakub@redhat.com>
1286
1287         PR tree-optimization/114433
1288         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
1289         m_bitfld_load check save_first rather than m_first.
1290
1291 2024-03-23  Jakub Jelinek  <jakub@redhat.com>
1292
1293         PR tree-optimization/114425
1294         * gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
1295         _Complex large/huge _BitInt types like the large/huge _BitInt types.
1296
1297 2024-03-23  Jakub Jelinek  <jakub@redhat.com>
1298
1299         PR middle-end/111683
1300         * tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
1301         and comp_step is RS_NONZERO, return false if any reference in the
1302         component doesn't have DR_STEP a multiple of access size.
1303
1304 2024-03-23  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
1305
1306         * config/xtensa/xtensa.md: Add new split pattern described above.
1307
1308 2024-03-22  Georg-Johann Lay  <avr@gjlay.de>
1309
1310         * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
1311         for deprecated SIGNAL and INTERRUPT usage without respective header.
1312
1313 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
1314
1315         * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
1316         (atomic_load<mode>): Adjust RDNA cache settings.
1317         (atomic_store<mode>): Likewise.
1318         (atomic_exchange<mode>): Likewise.
1319
1320 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
1321
1322         * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
1323         RDNA devices.
1324
1325 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
1326
1327         * config.gcc (amdgcn): Add gfx1103 entries.
1328         * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
1329         (gcn_local_sym_hash): Likewise.
1330         * config/gcn/gcn-opts.h (enum processor_type): Likewise.
1331         (TARGET_GFX1103): New macro.
1332         * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
1333         (gcn_omp_device_kind_arch_isa): Likewise.
1334         (output_file_start): Likewise.
1335         (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
1336         * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
1337         * config/gcn/gcn.opt: Add gfx1103.
1338         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
1339         (main): Handle gfx1103.
1340         * config/gcn/t-omp-device: Add gfx1103 isa.
1341         * doc/install.texi (amdgcn): Add gfx1103.
1342         * doc/invoke.texi (-march): Likewise.
1343
1344 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
1345
1346         * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
1347         bitmasks.
1348         (do_compare_and_jump): Remove now-redundant similar code.
1349         * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
1350         bitmasks.
1351         (add_mask_and_len_args): Likewise.
1352
1353 2024-03-22  Pan Li  <pan2.li@intel.com>
1354
1355         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
1356         macro __riscv_v_fixed_vlen when zvl.
1357         * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
1358         New static func to take care of the RVV types decorated by
1359         the attributes.
1360
1361 2024-03-22  Andrew Pinski  <quic_apinski@quicinc.com>
1362
1363         PR c/109619
1364         * builtins.cc (fold_builtin_1): Use error_operand_p
1365         instead of checking against ERROR_MARK.
1366         (fold_builtin_2): Likewise.
1367         (fold_builtin_3): Likewise.
1368
1369 2024-03-22  Jakub Jelinek  <jakub@redhat.com>
1370
1371         PR sanitizer/111736
1372         * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
1373         SANITIZE_NULL instrumentation for non-generic address spaces
1374         for which targetm.addr_space.zero_address_valid (as) is true.
1375
1376 2024-03-22  Jakub Jelinek  <jakub@redhat.com>
1377
1378         PR tree-optimization/114405
1379         * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
1380         Set rprec to limb_prec rather than 0 if tprec is divisible by
1381         limb_prec.  In the last bf_cur handling, set rprec to (tprec + bo_bit)
1382         % limb_prec rather than tprec % limb_prec and use just rprec instead
1383         of rprec + bo_bit.  For build_bit_field_ref offset, divide
1384         (tprec + bo_bit) by limb_prec rather than just tprec.
1385
1386 2024-03-22  Christoph Müllner  <christoph.muellner@vrull.eu>
1387
1388         PR target/114194
1389         * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
1390         Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
1391
1392 2024-03-22  Jeff Law  <jlaw@ventanamicro.com>
1393
1394         * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
1395         tie for scalable and final stack adjustment if needed.
1396         Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
1397
1398 2024-03-22  Pan Li  <pan2.li@intel.com>
1399
1400         PR target/114352
1401         * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
1402         New struct for func decl and target name.
1403         (struct riscv_func_target_hasher): New hasher for hash table mapping
1404         from the fn_decl to fn_target_name.
1405         (riscv_func_decl_hash): New func to compute the hash for fn_decl.
1406         (riscv_func_target_hasher::hash): New func to impl hash interface.
1407         (riscv_func_target_hasher::equal): New func to impl equal interface.
1408         (riscv_cmdline_subset_list): New static var for cmdline subset list.
1409         (riscv_func_target_table_lazy_init): New func to lazy init the func
1410         target hash table.
1411         (riscv_func_target_get): New func to get target name from hash table.
1412         (riscv_func_target_put): New func to put target name into hash table.
1413         (riscv_func_target_remove_and_destory): New func to remove target
1414         info from the hash table and destory it.
1415         (riscv_parse_arch_string): Set the static var cmdline_subset_list.
1416         * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
1417         var for cmdline subset list.
1418         (riscv_func_target_get): New func decl.
1419         (riscv_func_target_put): Ditto.
1420         (riscv_func_target_remove_and_destory): Ditto.
1421         * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
1422         Take cmdline_subset_list instead of current_subset_list when clone.
1423         (riscv_process_target_attr): Record the func target info to hash table.
1424         (riscv_option_valid_attribute_p): Add new arg tree fndel.
1425         * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
1426         func target info and print the arch message.
1427
1428 2024-03-22  Pan Li  <pan2.li@intel.com>
1429
1430         PR target/114352
1431         * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
1432         Replace implied, combine and check to func finalize.
1433         (riscv_subset_list::finalize): New func impl to take care of
1434         implied, combine ext and related checks.
1435         * config/riscv/riscv-subset.h: Add func decl for finalize.
1436         * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
1437         Finalize the ext before return succeed.
1438         * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
1439         machine mode before when set cur function.
1440
1441 2024-03-21  Andrew Stubbs  <ams@baylibre.com>
1442
1443         * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
1444
1445 2024-03-21  Andrew Stubbs  <ams@baylibre.com>
1446
1447         * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
1448
1449 2024-03-21  Andrew Stubbs  <ams@baylibre.com>
1450
1451         * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
1452         device_malloc call.
1453
1454 2024-03-21  liuhongt  <hongtao.liu@intel.com>
1455
1456         PR tree-optimization/114396
1457         * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
1458         and true to wi::from_mpz.
1459
1460 2024-03-21  Richard Biener  <rguenther@suse.de>
1461
1462         PR tree-optimization/111736
1463         * asan.cc (instrument_derefs): Do not instrument accesses
1464         to non-generic address-spaces.
1465
1466 2024-03-21  Richard Biener  <rguenther@suse.de>
1467
1468         PR tree-optimization/113727
1469         * tree-sra.cc (analyze_access_subtree): Do not allow
1470         replacements in subtrees when grp_partial_lhs.
1471
1472 2024-03-21  liuhongt  <hongtao.liu@intel.com>
1473
1474         PR middle-end/114347
1475         * doc/invoke.texi: Document -fexcess-precision=16.
1476
1477 2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>
1478
1479         * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
1480         field contains a DECL_NAME.
1481
1482 2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>
1483
1484         * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
1485         Add assert to validate the string is set.
1486         * config/bpf/core-builtins.cc (cr_final): Make string struct
1487         field as const.
1488         (process_enum_value): Correct for field type change.
1489         (process_type): Set access string to "0".
1490
1491 2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>
1492
1493         * config/bpf/core-builtins.cc (core_field_info): Add
1494         support for POINTER_PLUS_EXPR in the root of the field expression.
1495         (bpf_core_get_index): Likewise.
1496         (pack_field_expr): Make the BTF type to point to the structure
1497         related node, instead of its pointer type.
1498         (make_core_safe_access_index): Correct to new code.
1499
1500 2024-03-20  Xi Ruoyao  <xry111@xry111.site>
1501
1502         PR target/114407
1503         * config/loongarch/loongarch-opts.cc (loongarch_config_target):
1504         Fix typo in diagnostic message, enabing -> enabling.
1505
1506 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1507
1508         PR target/114175
1509         * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
1510         TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
1511         if arg.type is NULL.
1512
1513 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1514
1515         PR target/114175
1516         * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
1517         nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1518         if arg.type is NULL.
1519
1520 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1521
1522         PR target/114175
1523         * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
1524         function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1525         if arg.type is NULL.
1526
1527 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1528
1529         PR target/114175
1530         * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
1531         function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1532         if arg.type is NULL.
1533
1534 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1535
1536         PR target/114175
1537         * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
1538         function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1539         if arg.type is NULL.
1540
1541 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1542
1543         PR target/114175
1544         * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
1545         skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1546         if arg.type is NULL.
1547
1548 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1549
1550         PR target/114175
1551         * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
1552         csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1553         if arg.type is NULL.
1554
1555 2024-03-20  Yury Khrustalev  <yury.khrustalev@arm.com>
1556
1557         * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
1558
1559 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1560
1561         PR tree-optimization/114365
1562         * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
1563         a PHI node, set iv2 to its result afterwards.
1564
1565 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1566
1567         * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
1568         probabbility -> probability.
1569         (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
1570
1571 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
1572
1573         PR bootstrap/114369
1574         * system.h (vec_step): Define to vec_step_ when compiling
1575         with clang on PowerPC.
1576
1577 2024-03-20  demin.han  <demin.han@starfivetech.com>
1578
1579         PR target/112651
1580         * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
1581         (enum rvv_max_lmul_enum): Ditto
1582         (TARGET_MAX_LMUL): Ditto
1583         * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
1584         * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
1585         (costs::better_main_loop_than_p): Ditto
1586         * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
1587
1588 2024-03-20  Richard Biener  <rguenther@suse.de>
1589
1590         PR middle-end/113396
1591         * tree-dfa.cc (get_ref_base_and_extent): Use index range
1592         bounds only if they fit within the address-range constraints
1593         of offset_int.
1594
1595 2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>
1596
1597         * config/loongarch/loongarch.cc
1598         (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
1599         UNITS_PER_FPREG macros.
1600         (loongarch_hard_regno_nregs): Ditto.
1601         (loongarch_class_max_nregs): Ditto.
1602         (loongarch_get_separate_components): Ditto.
1603         (loongarch_process_components): Ditto.
1604         * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
1605         (UNITS_PER_HWFPVALUE): Ditto.
1606         (UNITS_PER_FPVALUE): Ditto.
1607
1608 2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>
1609
1610         * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
1611         of loongarch_expand_vec_cmp()'s return value.
1612         (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
1613         * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
1614         (vec_cmpu<ILSX:mode><mode_i>): Ditto.
1615         * config/loongarch/loongarch-protos.h
1616         (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
1617         type from bool to void.
1618         * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
1619
1620 2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>
1621
1622         * config/loongarch/loongarch-protos.h
1623         (loongarch_cfun_has_cprestore_slot_p): Delete.
1624         (loongarch_adjust_insn_length): Delete.
1625         (current_section_name): Delete.
1626         (loongarch_split_symbol_type): Delete.
1627         * config/loongarch/loongarch.cc
1628         (loongarch_case_values_threshold): Delete.
1629         (loongarch_spill_class): Delete.
1630         (TARGET_OPTAB_SUPPORTED_P): Delete.
1631         (TARGET_CASE_VALUES_THRESHOLD): Delete.
1632         (TARGET_SPILL_CLASS): Delete.
1633
1634 2024-03-20  Lewis Hyatt  <lhyatt@gmail.com>
1635
1636         PR c++/111918
1637         * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
1638         * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
1639         Make use of DK_ANY to indicate a diagnostic was initially enabled.
1640         (diagnostic_context::diagnostic_enabled): Do not change the type of
1641         a diagnostic if the saved classification is type DK_ANY.
1642
1643 2024-03-19  Martin Jambor  <mjambor@suse.cz>
1644
1645         PR ipa/108802
1646         PR ipa/114254
1647         * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
1648         at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
1649         a pointer parameter.
1650         (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
1651         parameter, also recognize the case when pfn pointer is loaded in its
1652         own BB.
1653
1654 2024-03-19  Vladimir N. Makarov  <vmakarov@redhat.com>
1655
1656         PR target/99829
1657         * lra-constraints.cc (lra_constraints): Prevent removing insn
1658         with reverse equivalence to memory if the memory was reloaded.
1659
1660 2024-03-19  David Malcolm  <dmalcolm@redhat.com>
1661
1662         PR middle-end/114348
1663         * diagnostic-format-json.cc
1664         (json_stderr_output_format::machine_readable_stderr_p): New.
1665         (json_file_output_format::machine_readable_stderr_p): New.
1666         * diagnostic-format-sarif.cc
1667         (sarif_stream_output_format::machine_readable_stderr_p): New.
1668         (sarif_file_output_format::machine_readable_stderr_p): New.
1669         * diagnostic.cc (diagnostic_context::action_after_output): Move
1670         "fnotice" to before "finish" call, so that we still have the
1671         diagnostic_context.
1672         (fnotice): Bail out if the user requested one of the
1673         machine-readable diagnostic output formats on stderr.
1674         * diagnostic.h
1675         (diagnostic_output_format::machine_readable_stderr_p): New pure
1676         virtual function.
1677         (diagnostic_text_output_format::machine_readable_stderr_p): New.
1678         (diagnostic_context::get_output_format): New accessor.
1679
1680 2024-03-19  Edwin Lu  <ewlu@rivosinc.com>
1681
1682         PR target/114175
1683         * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
1684         riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1685         if arg.type is NULL
1686
1687 2024-03-19  Jonathan Wakely  <jwakely@redhat.com>
1688
1689         * doc/install.texi (Prerequisites): Document use of autogen for
1690         libstdc++.
1691
1692 2024-03-19  Richard Biener  <rguenther@suse.de>
1693
1694         PR tree-optimization/114151
1695         PR tree-optimization/114269
1696         PR tree-optimization/114322
1697         PR tree-optimization/114074
1698         * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
1699         unsigned arithmetic when actual overflow on constant operands
1700         is observed.
1701
1702 2024-03-19  Jakub Jelinek  <jakub@redhat.com>
1703
1704         PR target/114175
1705         * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
1706         arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1707         if arg.type is NULL.
1708
1709 2024-03-19  Xi Ruoyao  <xry111@xry111.site>
1710
1711         PR target/114175
1712         * config/loongarch/loongarch.cc
1713         (loongarch_setup_incoming_varargs): Only skip
1714         loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
1715         functions if arg.type is NULL.
1716
1717 2024-03-19  Christophe Lyon  <christophe.lyon@linaro.org>
1718
1719         PR target/114323
1720         * config/arm/arm-mve-builtins.cc
1721         (function_instance::reads_global_state_p): Take CP_READ_MEMORY
1722         into account.
1723
1724 2024-03-19  Jakub Jelinek  <jakub@redhat.com>
1725
1726         PR target/114175
1727         * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
1728         function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1729         if arg.type is NULL.
1730
1731 2024-03-19  Jakub Jelinek  <jakub@redhat.com>
1732
1733         PR target/114175
1734         * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
1735         rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
1736         if arg.type is NULL.
1737
1738 2024-03-19  Richard Biener  <rguenther@suse.de>
1739
1740         PR tree-optimization/114375
1741         * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
1742         load permutation for masked loads but reject it when any
1743         such is necessary.
1744         * tree-vect-stmts.cc (vectorizable_load): Reject masked
1745         VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
1746         supported.
1747
1748 2024-03-19  Mary Bennett  <mary.bennett@embecosm.com>
1749
1750         * common/config/riscv/riscv-common.cc: Create XCVbi extension
1751         support.
1752         * config/riscv/riscv.opt: Likewise.
1753         * config/riscv/corev.md: Implement cv_branch<mode> pattern
1754         for cv.beqimm and cv.bneimm.
1755         * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
1756         branch instruction pattern.
1757         * config/riscv/constraints.md: Implement constraints
1758         cv_bi_s5 - signed 5-bit immediate.
1759         * config/riscv/predicates.md: Implement predicate
1760         const_int5s_operand - signed 5 bit immediate.
1761         * doc/sourcebuild.texi: Add XCVbi documentation.
1762
1763 2024-03-19  Chen Jiawei  <jiawei@iscas.ac.cn>
1764
1765         * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
1766         (RISCV_CORE): Ditto.
1767         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
1768         option.
1769         * config/riscv/riscv.cc: New def.
1770         * config/riscv/riscv.md: New include.
1771         * config/riscv/xiangshan.md: New file.
1772
1773 2024-03-18  David Malcolm  <dmalcolm@redhat.com>
1774
1775         PR analyzer/110902
1776         PR analyzer/110928
1777         PR analyzer/111305
1778         PR analyzer/111441
1779         * selftest.h (ASSERT_NE_AT): New macro.
1780
1781 2024-03-18  Uros Bizjak  <ubizjak@gmail.com>
1782
1783         PR target/111822
1784         * config/i386/i386-features.cc (smode_convert_cst): New function
1785         to handle SImode, DImode and TImode immediates, generalized from
1786         timode_convert_cst.
1787         (timode_convert_cst): Remove.
1788         (scalar_chain::convert_op): Unify from
1789         general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
1790         (general_scalar_chain::convert_op): Remove.
1791         (timode_scalar_chain::convert_op): Remove.
1792         (timode_scalar_chain::convert_insn): Update the call to
1793         renamed timode_convert_cst.
1794         * config/i386/i386-features.h (class scalar_chain):
1795         Redeclare convert_op as protected class member.
1796         (class general_calar_chain): Remove convert_op.
1797         (class timode_scalar_chain): Ditto.
1798
1799 2024-03-18  Jan Hubicka  <jh@suse.cz>
1800
1801         * config/i386/zn4zn5.md: Add file missed in the previous commit.
1802
1803 2024-03-18  Jan Hubicka  <jh@suse.cz>
1804             Karthiban Anbazhagan  <Karthiban.Anbazhagan@amd.com>
1805
1806         * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
1807         * common/config/i386/i386-common.cc (processor_names): Add znver5.
1808         (processor_alias_table): Likewise.
1809         * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
1810         family.
1811         (processor_subtypes): Add znver5.
1812         * config.gcc (x86_64-*-* |...): Likewise.
1813         * config/i386/driver-i386.cc (host_detect_local_cpu): Let
1814         march=native detect znver5 cpu's.
1815         * config/i386/i386-c.cc (ix86_target_macros_internal): Add
1816         znver5.
1817         * config/i386/i386-options.cc (m_ZNVER5): New definition
1818         (processor_cost_table): Add znver5.
1819         * config/i386/i386.cc (ix86_reassociation_width): Likewise.
1820         * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
1821         (PTA_ZNVER5): New definition.
1822         * config/i386/i386.md (define_attr "cpu"): Add znver5.
1823         (Scheduling descriptions) Add znver5.md.
1824         * config/i386/x86-tune-costs.h (znver5_cost): New definition.
1825         * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
1826         (ix86_adjust_cost): Likewise.
1827         * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
1828         (avx512_store_by_pieces): Add m_ZNVER5.
1829         * doc/extend.texi: Add znver5.
1830         * doc/invoke.texi: Likewise.
1831         * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
1832
1833 2024-03-18  Georg-Johann Lay  <avr@gjlay.de>
1834
1835         * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
1836         * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
1837         * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
1838         * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
1839         (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
1840         (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
1841
1842 2024-03-18  liuhongt  <hongtao.liu@intel.com>
1843
1844         PR target/114334
1845         * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
1846         (MODEF248): New mode iterator.
1847         (ssevecmodesuffix): Hanlde BF and HF.
1848         * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
1849         (<code><mode>3): Ditto.
1850
1851 2024-03-18  John David Anglin  <danglin@gcc.gnu.org>
1852
1853         PR rtl-optimization/112415
1854         * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
1855         for symbolic memory operands.
1856         (pa_legitimate_address_p): Revise LO_SUM condition.
1857         * config/pa/pa.h (INT14_OK_STRICT): Revise define.  Move
1858         comment about GNU linker to predicates.md.
1859         * config/pa/predicates.md (floating_point_store_memory_operand):
1860         Revise condition for symbolic memory operands.  Update
1861         comment.
1862
1863 2024-03-17  John David Anglin  <danglin@gcc.gnu.org>
1864
1865         * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
1866
1867 2024-03-16  Jakub Jelinek  <jakub@redhat.com>
1868
1869         PR target/114175
1870         * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
1871         ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1872         if arg.type is NULL.
1873
1874 2024-03-16  Jakub Jelinek  <jakub@redhat.com>
1875
1876         PR tree-optimization/114329
1877         * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
1878         build_bit_field_ref method.
1879         (bitint_large_huge::build_bit_field_ref): New method.
1880         (bitint_large_huge::lower_mergeable_stmt): Use it.
1881
1882 2024-03-15  YunQiang Su  <syq@gcc.gnu.org>
1883
1884         * config/riscv/riscv.opt.urls: Regenerated.
1885         * config/rs6000/sysv4.opt.urls: Likewise.
1886         * config/xtensa/xtensa.opt.urls: Likewise.
1887
1888 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
1889
1890         * lower-subreg.cc (resolve_simple_move): Fix comment typo,
1891         betwee -> between.
1892         * edit-context.cc (class line_event): Fix comment typo,
1893         betweeen -> between.
1894
1895 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
1896
1897         PR target/114339
1898         * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
1899         a pasto, compare code against LE rather than GE.
1900
1901 2024-03-15  Joe Ramsay  <Joe.Ramsay@arm.com>
1902
1903         * match.pd: Fix truncation pattern for -fno-signed-zeroes
1904
1905 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
1906
1907         PR middle-end/114332
1908         * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
1909
1910 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
1911
1912         PR tree-optimization/113466
1913         * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
1914         member.
1915         (bitint_large_huge::bitint_large_huge): Initialize it.
1916         (bitint_large_huge::~bitint_large_huge): Release it.
1917         (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
1918         before which at least one statement has been inserted.
1919         (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
1920         calls to a different block and add corresponding PHIs.
1921
1922 2024-03-15  YunQiang Su  <syq@gcc.gnu.org>
1923
1924         * config/mips/mips.opt: Support -mstrict-align, and use
1925         TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
1926         as alias.
1927         * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
1928         * config/mips/mips.opt.urls: Regenerate.
1929         * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
1930
1931 2024-03-15  Tejas Belagod  <tejas.belagod@arm.com>
1932
1933         PR middle-end/114108
1934         * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
1935         vect_convert_output with the correct vecitype.
1936
1937 2024-03-15  Chenghui Pan  <panchenghui@loongson.cn>
1938
1939         * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
1940         Remove masking of operand 3.
1941
1942 2024-03-14  Jason Merrill  <jason@redhat.com>
1943
1944         * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
1945         comments.
1946
1947 2024-03-14  John David Anglin  <danglin@gcc.gnu.org>
1948
1949         PR target/114288
1950         * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
1951         14-bit displacements before reload for modes that may use
1952         a floating-point load or store.
1953
1954 2024-03-14  David Faust  <david.faust@oracle.com>
1955
1956         * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
1957
1958 2024-03-14  Max Filippov  <jcmvbkbc@gmail.com>
1959
1960         * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
1961         patterns ahead of the l32i.n and s32i.n.
1962
1963 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
1964
1965         * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
1966
1967 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
1968
1969         PR middle-end/113907
1970         * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
1971         SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
1972         functions.
1973
1974 2024-03-14  Xi Ruoyao  <xry111@xry111.site>
1975
1976         * config/loongarch/loongarch.md (any_ge): Remove.
1977         (sge<u>_<X:mode><GPR:mode>): Remove.
1978
1979 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
1980
1981         PR target/114310
1982         * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
1983         TImode force newval into a register.
1984
1985 2024-03-14  Chung-Lin Tang  <cltang@baylibre.com>
1986
1987         * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
1988         (OMP_CLAUSE__CACHE__READONLY): New macro.
1989         * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
1990         uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
1991         OMP_CLAUSE__CACHE__READONLY.
1992         * tree-pretty-print.cc (dump_omp_clause): Add support for printing
1993         OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
1994
1995 2024-03-14  Andreas Krebbel  <krebbel@linux.ibm.com>
1996
1997         * config/s390/s390.cc (s390_encode_section_info): Adjust the check
1998         for misaligned symbols.
1999         * config/s390/s390.opt: Improve documentation.
2000
2001 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
2002
2003         * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
2004         flags and probability from ad_edge to e edge.  If CDI_DOMINATORS
2005         are computed, recompute immediate dominator of other_edge->src
2006         and other_edge->dest.
2007         (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
2008         for the returns_twice call case to the gsi_for_stmt (stmt) to deal
2009         with update it for bb splitting.
2010
2011 2024-03-14  liuhongt  <hongtao.liu@intel.com>
2012
2013         * config/i386/i386-features.cc
2014         (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
2015         (convert_scalars_to_vector): Ditto.
2016         * config/i386/i386-features.h (class scalar_chain): New
2017         memeber control_flow_insns.
2018
2019 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
2020
2021         PR middle-end/114319
2022         * gimple-ssa-store-merging.cc
2023         (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
2024         allow matching __builtin_bswap64 if there is bswapsi2 optab.
2025
2026 2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2027
2028         * config/s390/s390.cc (s390_secondary_reload): Guard
2029         SYMBOL_FLAG_NOTALIGN2_P.
2030
2031 2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2032
2033         * config/s390/s390-builtin-types.def: Update to reflect latest
2034         changes.
2035         * config/s390/s390-builtins.def: Streamline vector builtins with
2036         LLVM.
2037
2038 2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2039
2040         * config/s390/s390-builtins.def (vec_permi): Deprecate.
2041         (vec_ctd): Deprecate.
2042         (vec_ctd_s64): Deprecate.
2043         (vec_ctd_u64): Deprecate.
2044         (vec_ctsl): Deprecate.
2045         (vec_ctul): Deprecate.
2046         (vec_ld2f): Deprecate.
2047         (vec_st2f): Deprecate.
2048         (vec_insert): Deprecate overloads with bool vectors.
2049
2050 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
2051
2052         PR middle-end/114313
2053         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
2054         TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
2055         (bitint_large_huge::handle_load): Pass NULL_TREE rather than
2056         rhs_type to limb_access for the bitfield load cases.
2057         (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
2058         lhs_type to limb_access if nlhs is non-NULL.
2059
2060 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
2061
2062         PR sanitizer/112709
2063         * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
2064         build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
2065         gsi_safe_insert_before instead of gsi_insert_before.
2066
2067 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
2068
2069         PR sanitizer/112709
2070         * gimple-iterator.h (gsi_safe_insert_before,
2071         gsi_safe_insert_seq_before): Declare.
2072         * gimple-iterator.cc: Include gimplify.h.
2073         (edge_before_returns_twice_call, adjust_before_returns_twice_call,
2074         gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
2075         * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
2076         instrument_nonnull_arg, instrument_nonnull_return): Use
2077         gsi_safe_insert_before instead of gsi_insert_before.
2078         (maybe_instrument_pointer_overflow): Use force_gimple_operand,
2079         gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
2080         instead of force_gimple_operand_gsi.
2081         (instrument_object_size): Likewise.  Use gsi_safe_insert_before
2082         instead of gsi_insert_before.
2083
2084 2024-03-12  Richard Biener  <rguenther@suse.de>
2085
2086         PR tree-optimization/114121
2087         * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
2088         converted operand properly.
2089         (chrec_fold_multiply): Likewise.  Handle missed recursion.
2090
2091 2024-03-12  Jakub Jelinek  <jakub@redhat.com>
2092
2093         PR sanitizer/112709
2094         * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
2095         stores on the caller side unless it is a call to a builtin or
2096         internal function or function doesn't return by hidden reference.
2097         (maybe_instrument_call): Likewise.
2098         (instrument_derefs): Instrument stores to RESULT_DECL if
2099         returning by hidden reference.
2100
2101 2024-03-12  Jakub Jelinek  <jakub@redhat.com>
2102
2103         PR tree-optimization/114293
2104         * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
2105         max is smaller than min, set max to ~(size_t)0.
2106
2107 2024-03-12  Pan Li  <pan2.li@intel.com>
2108
2109         * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
2110         code style greater than 80 chars.
2111         (riscv_cpu_cpp_builtins): Fix useless empty line, indent
2112         with 3 space(s) and argument unalignment.
2113
2114 2024-03-12  Richard Biener  <rguenther@suse.de>
2115
2116         PR tree-optimization/114297
2117         * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
2118         live stmts SLP node to vect_create_epilog_for_reduction.
2119
2120 2024-03-12  Andrew Pinski  <quic_apinski@quicinc.com>
2121
2122         PR driver/114314
2123         * common.opt (fmultiflags): Add RejectNegative.
2124
2125 2024-03-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
2126
2127         * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
2128         * config/aarch64/aarch64.opt: Likewise.
2129         * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
2130         * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
2131         (aarch64_expand_epilogue): Likewise.
2132         (aarch64_post_cfi_startproc): Likewise.
2133         (aarch64_handle_no_branch_protection): Copy and rename.
2134         (aarch64_handle_standard_branch_protection): Likewise.
2135         (aarch64_handle_pac_ret_protection): Likewise.
2136         (aarch64_handle_pac_ret_leaf): Likewise.
2137         (aarch64_handle_pac_ret_b_key): Likewise.
2138         (aarch64_handle_bti_protection): Likewise.
2139         (aarch64_override_options): Update branch protection validation.
2140         (aarch64_handle_attr_branch_protection): Likewise.
2141         * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
2142         Pass branch protection type description as argument.
2143         (struct aarch_branch_protect_type): Move from aarch-common.h.
2144         * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
2145         Remove.
2146         (aarch_handle_standard_branch_protection): Remove.
2147         (aarch_handle_pac_ret_protection): Remove.
2148         (aarch_handle_pac_ret_leaf): Remove.
2149         (aarch_handle_pac_ret_b_key): Remove.
2150         (aarch_handle_bti_protection): Remove.
2151         (aarch_validate_mbranch_protection): Pass branch protection type
2152         description as argument.
2153         * config/arm/aarch-common.h (enum aarch_key_type): Remove.
2154         (struct aarch_branch_protect_type): Remove.
2155         * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
2156         * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
2157         (arm_handle_standard_branch_protection): Likewise.
2158         (arm_handle_pac_ret_protection): Likewise.
2159         (arm_handle_pac_ret_leaf): Likewise.
2160         (arm_handle_bti_protection): Likewise.
2161         (arm_configure_build_target): Update branch protection validation.
2162         * config/arm/arm.opt: Remove aarch_ra_sign_key.
2163
2164 2024-03-11  Richard Biener  <rguenther@suse.de>
2165
2166         PR middle-end/114299
2167         * gimplify.cc (internal_get_tmp_var): When gimplification
2168         of VAL failed, return a decl.
2169
2170 2024-03-11  Jakub Jelinek  <jakub@redhat.com>
2171
2172         PR tree-optimization/114278
2173         * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
2174         longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
2175
2176 2024-03-11  Eric Botcazou  <ebotcazou@adacore.com>
2177
2178         PR debug/113519
2179         PR debug/113777
2180         * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
2181         generate the DIE with the same parent as in the regular case.
2182
2183 2024-03-11  Andrew Pinski  <quic_apinski@quicinc.com>
2184
2185         PR middle-end/95351
2186         * fold-const.cc (merge_truthop_with_opposite_arm): Use
2187         the type of the operands of the comparison and not the type
2188         of the comparison.
2189
2190 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
2191
2192         PR tree-optimization/110199
2193         * tree-ssa-scopedtables.cc
2194         (avail_exprs_stack::simplify_binary_operation): Generalize handling
2195         of MIN_EXPR/MAX_EXPR to allow additional simplifications.  Canonicalize
2196         comparison operands for other cases.
2197
2198 2024-03-10  Pan Li  <pan2.li@intel.com>
2199
2200         * tree-vect-stmts.cc (vectorizable_store): Enable the assert
2201         during transform process.
2202         (vectorizable_load): Ditto.
2203
2204 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
2205
2206         PR target/102250
2207         * doc/install.texi: Document need for python when building
2208         RISC-V compilers.
2209
2210 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
2211
2212         PR target/111362
2213         * mode-switching.cc (optimize_mode_switching): Only process
2214         NONDEBUG insns.
2215
2216 2024-03-09  Georg-Johann Lay  <avr@gjlay.de>
2217
2218         * config/avr/avr.md: Fix typos in comment, indentation glitches
2219         and some other nits.
2220
2221 2024-03-09  Jakub Jelinek  <jakub@redhat.com>
2222
2223         PR target/114284
2224         * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
2225         src containing MEMs unless prop.likely_profitable_p ().
2226
2227 2024-03-09  Xi Ruoyao  <xry111@xry111.site>
2228
2229         * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
2230         Support 'Q' for R_LARCH_RELAX for TLS IE.
2231         (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
2232         IE.
2233         * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
2234
2235 2024-03-09  Georg-Johann Lay  <avr@gjlay.de>
2236
2237         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
2238         usum_widenqihi and add_zero_extend1.
2239         [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
2240         sub+sign_extend.
2241         * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
2242         Compute exact insn lengths.
2243         (*usum_widenqihi3): Allow input operands to commute.
2244
2245 2024-03-09  Jakub Jelinek  <jakub@redhat.com>
2246
2247         * config/i386/i386.opt.urls: Regenerate.
2248
2249 2024-03-09  Lulu Cheng  <chenglulu@loongson.cn>
2250
2251         * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
2252         In loongarch64, a sign extension operation is added when
2253         operands[2] is a register operand and the mode is SImode.
2254
2255 2024-03-08  Martin Jambor  <mjambor@suse.cz>
2256
2257         PR ipa/113757
2258         * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
2259         id->killed_new_ssa_names.
2260
2261 2024-03-08  Vladimir N. Makarov  <vmakarov@redhat.com>
2262
2263         PR target/113790
2264         * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
2265         for non-reload pseudo too.
2266
2267 2024-03-08  David Faust  <david.faust@oracle.com>
2268
2269         * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
2270         not attempt inline expansion if size is above threshold.
2271         * config/bpf/bpf.opt (-minline-memops-threshold): New option.
2272         * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
2273         Document.
2274
2275 2024-03-08  Richard Biener  <rguenther@suse.de>
2276
2277         PR tree-optimization/114269
2278         PR tree-optimization/114074
2279         * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
2280         in the third CASE_CONVERT case as well.
2281         (chrec_fold_multiply): Handle sign-conversions from unsigned
2282         by performing the operation in the unsigned type.
2283
2284 2024-03-08  Georg-Johann Lay  <avr@gjlay.de>
2285
2286         * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
2287         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
2288
2289 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
2290
2291         * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
2292         asm_noperands < 0 means it is not asm goto too.
2293
2294 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
2295
2296         PR target/38534
2297         * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
2298         option.
2299         * config/i386/i386-options.cc (ix86_set_func_type): Don't use
2300         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
2301         ix86_noreturn_no_callee_saved_registers is enabled.
2302         * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
2303
2304 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
2305
2306         PR debug/113918
2307         * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
2308         on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
2309
2310 2024-03-08  demin.han  <demin.han@starfivetech.com>
2311
2312         PR target/114264
2313         * config/riscv/riscv-vector-costs.cc: Fix ICE
2314
2315 2024-03-08  Haochen Gui  <guihaoc@gcc.gnu.org>
2316
2317         * fwprop.cc (forward_propagate_into): Return false for volatile set
2318         source rtx.
2319
2320 2024-03-07  Wilco Dijkstra  <wilco.dijkstra@arm.com>
2321
2322         PR target/113618
2323         * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
2324         (aarch64_expand_cpymem): Emit single load/store only.
2325         (aarch64_set_one_block): Emit single stores only.
2326
2327 2024-03-07  Robin Dapp  <rdapp@ventanamicro.com>
2328
2329         PR middle-end/114196
2330         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
2331         vectorization guards.
2332
2333 2024-03-07  Jonathan Wakely  <jwakely@redhat.com>
2334
2335         * doc/cppopts.texi: Remove incorrect claim about -dD not
2336         outputting predefined macros.
2337
2338 2024-03-07  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
2339
2340         PR target/113950
2341         * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
2342         and simplify else if with else.
2343
2344 2024-03-07  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
2345
2346         * system.h: Include safe-ctype.h after C++ standard headers.
2347
2348 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
2349
2350         PR rtl-optimization/110079
2351         * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
2352         asm goto.
2353
2354 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
2355
2356         PR middle-end/105533
2357         * expmed.cc (choose_mult_variant): Only try the val - 1 variant
2358         if val is not HOST_WIDE_INT_MIN or if mode has exactly
2359         HOST_BITS_PER_WIDE_INT precision.  Avoid triggering UB while computing
2360         val - 1.
2361
2362 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
2363
2364         PR middle-end/105533
2365         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
2366         Multiple op->off by BITS_PER_UNIT instead of shifting it left by
2367         LOG2_BITS_PER_UNIT.
2368
2369 2024-03-07  Yang Yujie  <yangyujie@loongson.cn>
2370
2371         * config.gcc: Add a case for loongarch*-*-linux-musl*.
2372         * config/loongarch/linux.h: Disable the multilib-compatible
2373         treatment for *musl* targets.
2374         * config/loongarch/musl.h: New file.
2375
2376 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
2377
2378         PR tree-optimization/114009
2379         * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
2380         argument even for GENERIC, not just for GIMPLE.
2381         * match.pd (a * !a -> 0): New simplifications.
2382
2383 2024-03-07  demin.han  <demin.han@starfivetech.com>
2384
2385         * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
2386         * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
2387         (expand_vec_cmp_float): Adapt arguments
2388
2389 2024-03-06  Uros Bizjak  <ubizjak@gmail.com>
2390
2391         PR target/114232
2392         * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
2393         of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
2394         (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
2395         (<plusminus:insn>v2qi3): Enable for optimize_size instead
2396         of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
2397         (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
2398         (<any_shift:insn>v2qi3): Enable for optimize_size instead
2399         of optimize_function_for_size_p.
2400
2401 2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>
2402
2403         PR target/114200
2404         PR target/114202
2405         * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
2406
2407 2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>
2408
2409         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
2410         (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
2411         offset handling.
2412         (costs::add_stmt_cost): Also adjust cost for statements without
2413         stmt_info.
2414         * config/riscv/riscv-vector-costs.h: Define zero constant.
2415
2416 2024-03-06  Wilco Dijkstra  <wilco.dijkstra@arm.com>
2417
2418         PR target/113915
2419         * config/arm/arm.md (NOCOND): Improve comment.
2420         (arm_rev*) Add predicable.
2421         * config/arm/arm.cc (arm_final_prescan_insn): Add check for
2422         PREDICABLE_YES.
2423
2424 2024-03-06  Jeff Law  <jlaw@ventanamicro.com>
2425
2426         PR target/113001
2427         PR target/112871
2428         * config/riscv/riscv.cc (expand_conditional_move): Do not swap
2429         operands when the comparison operand is the same as the false
2430         arm for a NE test.
2431
2432 2024-03-06  Uros Bizjak  <ubizjak@gmail.com>
2433
2434         * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
2435         Eliminate common code and use generic code instead.
2436
2437 2024-03-06  Georg-Johann Lay  <avr@gjlay.de>
2438
2439         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
2440         rtx cost.
2441
2442 2024-03-06  Richard Biener  <rguenther@suse.de>
2443
2444         PR tree-optimization/114239
2445         * tree-vect-loop.cc (vect_get_vect_def): Remove.
2446         (vect_create_epilog_for_reduction): The passed in stmt_info
2447         should now be the live stmt that produces the scalar reduction
2448         result.  Revert PR114192 fix.  Base reduction info off
2449         info_for_reduction.  Remove special handling of
2450         early-break/peeled, restore original vector def gathering.
2451         Make sure to pick the correct exit PHIs.
2452         (vectorizable_live_operation): Pass in the proper stmt_info
2453         for early break exits.
2454
2455 2024-03-06  Richard Sandiford  <richard.sandiford@arm.com>
2456
2457         * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
2458         out-of-class definitions of static constants.
2459
2460 2024-03-06  Richard Biener  <rguenther@suse.de>
2461
2462         PR tree-optimization/114249
2463         * tree-vect-slp.cc (vect_build_slp_instance): Move making
2464         a BB reduction lane number even ...
2465         (vect_slp_check_for_roots): ... here to avoid leaking
2466         pattern defs.
2467
2468 2024-03-06  Richard Biener  <rguenther@suse.de>
2469
2470         PR tree-optimization/114246
2471         * tree-ssa-dse.cc (increment_start_addr): Strip useless
2472         type conversions from the adjusted address.
2473
2474 2024-03-06  Jakub Jelinek  <jakub@redhat.com>
2475
2476         PR rtl-optimization/114190
2477         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2478         Call df_remove_problem for df_note before calling df_analyze.
2479
2480 2024-03-05  Cupertino Miranda  <cupertino.miranda@oracle.com>
2481             Indu Bhagat  <indu.bhagat@oracle.com>
2482
2483         PR debug/114186
2484         * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
2485         in the correct order of the dimensions.
2486         (gen_ctf_subrange_type): Refactor out handling of
2487         DW_TAG_subrange_type DIE to here.
2488
2489 2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>
2490
2491         PR sanitizer/97696
2492         * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
2493
2494 2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>
2495
2496         * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
2497         and luti_strided.
2498         * config/aarch64/aarch64-sme.md
2499         (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
2500         (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
2501         (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
2502         * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
2503         (early_ra::maybe_convert_to_strided_access): Remove support for
2504         strided LUTI2 and LUTI4.
2505
2506 2024-03-05  Richard Earnshaw  <rearnsha@arm.com>
2507
2508         PR target/113510
2509         * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
2510         low_register_operand.
2511
2512 2024-03-05  Georg-Johann Lay  <avr@gjlay.de>
2513
2514         * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
2515         in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
2516         to "X = Y, X o= CST".
2517
2518 2024-03-05  Xi Ruoyao  <xry111@xry111.site>
2519
2520         * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
2521         s9 as an alias of r22.
2522
2523 2024-03-05  Roger Sayle  <roger@nextmovesoftware.com>
2524
2525         * config/avr/avr-protos.h (avr_out_insv): New proto.
2526         * config/avr/avr.cc (avr_out_insv): New function.
2527         (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
2528         (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
2529         * config/avr/avr.md (define_attr "adjust_len") Add insv.
2530         (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
2531         Add constraint alternative where the 3rd operand is a power
2532         of 2, and the source register may differ from the destination.
2533         (*insv.any_shift.<mode>_split): Call avr_out_insv to output
2534         instructions.  Set attr "length" to "insv".
2535         * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
2536
2537 2024-03-05  Richard Biener  <rguenther@suse.de>
2538
2539         PR tree-optimization/114231
2540         * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
2541         processing a BB SLP root.
2542
2543 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
2544
2545         PR rtl-optimization/114211
2546         * lower-subreg.cc (resolve_simple_move): For double-word
2547         rotates by BITS_PER_WORD if there is overlap between source
2548         and destination use a temporary.
2549
2550 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
2551
2552         PR middle-end/114157
2553         * gimple-lower-bitint.cc: Include stor-layout.h.
2554         (mergeable_op): Return true for BIT_FIELD_REF.
2555         (struct bitint_large_huge): Declare handle_bit_field_ref method.
2556         (bitint_large_huge::handle_bit_field_ref): New method.
2557         (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
2558
2559 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
2560
2561         PR target/114116
2562         * config/i386/i386.h (enum call_saved_registers_type): Add
2563         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
2564         * config/i386/i386-options.cc (ix86_set_func_type): Remove
2565         has_no_callee_saved_registers variable, add no_callee_saved_registers
2566         instead, initialize it depending on whether it is
2567         no_callee_saved_registers function or not.  Don't set it if
2568         no_caller_saved_registers attribute is present.  Adjust users.
2569         * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
2570         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
2571         TYPE_NO_CALLEE_SAVED_REGISTERS.
2572         (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
2573
2574 2024-03-05  Pan Li  <pan2.li@intel.com>
2575
2576         * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
2577         mode_size related code.
2578
2579 2024-03-05  Patrick Palka  <ppalka@redhat.com>
2580
2581         * doc/invoke.texi (-Wno-global-module): Document.
2582
2583 2024-03-04  David Faust  <david.faust@oracle.com>
2584
2585         * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
2586         * config/bpf/bpf.cc (bpf_expand_setmem): New.
2587         * config/bpf/bpf.md (setmemdi): New define_expand.
2588
2589 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
2590
2591         PR rtl-optimization/113010
2592         * combine.cc (simplify_comparison): Guard the
2593         WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
2594         and initialize inner_mode.
2595
2596 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
2597
2598         * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
2599         VMLALDAVAXQ_U cases.
2600         (VMLALDAVXQ): Remove iterator.
2601         (VMLALDAVXQ_P): Likewise.
2602         (VMLALDAVAXQ): Likewise.
2603         * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
2604         mode iterator attribute with V4BI mode.
2605         * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
2606         VMLALDAVAXQ_U): Remove unused unspecs.
2607
2608 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
2609
2610         * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
2611         * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
2612         attribute.
2613         * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
2614         vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
2615         vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
2616         vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
2617         vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
2618         vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
2619         vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
2620         vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
2621         vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
2622         vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
2623
2624 2024-03-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2625
2626         * config/arm/arm.md (mve_unpredicated_insn): New attribute.
2627         * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
2628         (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
2629         (MVE_VPT_PREDICABLE_INSN_P): Likewise.
2630         * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
2631         * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
2632         (arm_vcx1q<a>v16qi): Likewise.
2633         (arm_vcx1qav16qi): Likewise.
2634         (arm_vcx1qv16qi): Likewise.
2635         (arm_vcx2q<a>_p_v16qi): Likewise.
2636         (arm_vcx2q<a>v16qi): Likewise.
2637         (arm_vcx2qav16qi): Likewise.
2638         (arm_vcx2qv16qi): Likewise.
2639         (arm_vcx3q<a>_p_v16qi): Likewise.
2640         (arm_vcx3q<a>v16qi): Likewise.
2641         (arm_vcx3qav16qi): Likewise.
2642         (arm_vcx3qv16qi): Likewise.
2643         (@mve_<mve_insn>q_<supf><mode>): Likewise.
2644         (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
2645         (@mve_<mve_insn>q_<supf>v4si): Likewise.
2646         (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
2647         (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
2648         (@mve_<mve_insn>q_f<mode>): Likewise.
2649         (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
2650         (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
2651         (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
2652         (@mve_<mve_insn>q_m_f<mode>): Likewise.
2653         (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
2654         (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
2655         (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
2656         (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
2657         (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
2658         (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
2659         (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
2660         (mve_v<absneg_str>q_f<mode>): Likewise.
2661         (mve_<mve_addsubmul>q<mode>): Likewise.
2662         (mve_<mve_addsubmul>q_f<mode>): Likewise.
2663         (mve_vadciq_<supf>v4si): Likewise.
2664         (mve_vadciq_m_<supf>v4si): Likewise.
2665         (mve_vadcq_<supf>v4si): Likewise.
2666         (mve_vadcq_m_<supf>v4si): Likewise.
2667         (mve_vandq_<supf><mode>): Likewise.
2668         (mve_vandq_f<mode>): Likewise.
2669         (mve_vandq_m_<supf><mode>): Likewise.
2670         (mve_vandq_m_f<mode>): Likewise.
2671         (mve_vandq_s<mode>): Likewise.
2672         (mve_vandq_u<mode>): Likewise.
2673         (mve_vbicq_<supf><mode>): Likewise.
2674         (mve_vbicq_f<mode>): Likewise.
2675         (mve_vbicq_m_<supf><mode>): Likewise.
2676         (mve_vbicq_m_f<mode>): Likewise.
2677         (mve_vbicq_m_n_<supf><mode>): Likewise.
2678         (mve_vbicq_n_<supf><mode>): Likewise.
2679         (mve_vbicq_s<mode>): Likewise.
2680         (mve_vbicq_u<mode>): Likewise.
2681         (@mve_vclzq_s<mode>): Likewise.
2682         (mve_vclzq_u<mode>): Likewise.
2683         (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
2684         (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
2685         (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
2686         (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
2687         (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
2688         (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
2689         (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
2690         (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
2691         (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
2692         (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
2693         (mve_vcvtaq_<supf><mode>): Likewise.
2694         (mve_vcvtaq_m_<supf><mode>): Likewise.
2695         (mve_vcvtbq_f16_f32v8hf): Likewise.
2696         (mve_vcvtbq_f32_f16v4sf): Likewise.
2697         (mve_vcvtbq_m_f16_f32v8hf): Likewise.
2698         (mve_vcvtbq_m_f32_f16v4sf): Likewise.
2699         (mve_vcvtmq_<supf><mode>): Likewise.
2700         (mve_vcvtmq_m_<supf><mode>): Likewise.
2701         (mve_vcvtnq_<supf><mode>): Likewise.
2702         (mve_vcvtnq_m_<supf><mode>): Likewise.
2703         (mve_vcvtpq_<supf><mode>): Likewise.
2704         (mve_vcvtpq_m_<supf><mode>): Likewise.
2705         (mve_vcvtq_from_f_<supf><mode>): Likewise.
2706         (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
2707         (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
2708         (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
2709         (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
2710         (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
2711         (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
2712         (mve_vcvtq_to_f_<supf><mode>): Likewise.
2713         (mve_vcvttq_f16_f32v8hf): Likewise.
2714         (mve_vcvttq_f32_f16v4sf): Likewise.
2715         (mve_vcvttq_m_f16_f32v8hf): Likewise.
2716         (mve_vcvttq_m_f32_f16v4sf): Likewise.
2717         (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
2718         (mve_vdwdupq_wb_u<mode>_insn): Likewise.
2719         (mve_veorq_s><mode>): Likewise.
2720         (mve_veorq_u><mode>): Likewise.
2721         (mve_veorq_f<mode>): Likewise.
2722         (mve_vidupq_m_wb_u<mode>_insn): Likewise.
2723         (mve_vidupq_u<mode>_insn): Likewise.
2724         (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
2725         (mve_viwdupq_wb_u<mode>_insn): Likewise.
2726         (mve_vldrbq_<supf><mode>): Likewise.
2727         (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
2728         (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
2729         (mve_vldrbq_z_<supf><mode>): Likewise.
2730         (mve_vldrdq_gather_base_<supf>v2di): Likewise.
2731         (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
2732         (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
2733         (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
2734         (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
2735         (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
2736         (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
2737         (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
2738         (mve_vldrhq_<supf><mode>): Likewise.
2739         (mve_vldrhq_fv8hf): Likewise.
2740         (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
2741         (mve_vldrhq_gather_offset_fv8hf): Likewise.
2742         (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
2743         (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
2744         (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
2745         (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
2746         (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
2747         (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
2748         (mve_vldrhq_z_<supf><mode>): Likewise.
2749         (mve_vldrhq_z_fv8hf): Likewise.
2750         (mve_vldrwq_<supf>v4si): Likewise.
2751         (mve_vldrwq_fv4sf): Likewise.
2752         (mve_vldrwq_gather_base_<supf>v4si): Likewise.
2753         (mve_vldrwq_gather_base_fv4sf): Likewise.
2754         (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
2755         (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
2756         (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
2757         (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
2758         (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
2759         (mve_vldrwq_gather_base_z_fv4sf): Likewise.
2760         (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
2761         (mve_vldrwq_gather_offset_fv4sf): Likewise.
2762         (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
2763         (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
2764         (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
2765         (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
2766         (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
2767         (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
2768         (mve_vldrwq_z_<supf>v4si): Likewise.
2769         (mve_vldrwq_z_fv4sf): Likewise.
2770         (mve_vmvnq_s<mode>): Likewise.
2771         (mve_vmvnq_u<mode>): Likewise.
2772         (mve_vornq_<supf><mode>): Likewise.
2773         (mve_vornq_f<mode>): Likewise.
2774         (mve_vornq_m_<supf><mode>): Likewise.
2775         (mve_vornq_m_f<mode>): Likewise.
2776         (mve_vornq_s<mode>): Likewise.
2777         (mve_vornq_u<mode>): Likewise.
2778         (mve_vorrq_<supf><mode>): Likewise.
2779         (mve_vorrq_f<mode>): Likewise.
2780         (mve_vorrq_m_<supf><mode>): Likewise.
2781         (mve_vorrq_m_f<mode>): Likewise.
2782         (mve_vorrq_m_n_<supf><mode>): Likewise.
2783         (mve_vorrq_n_<supf><mode>): Likewise.
2784         (mve_vorrq_s<mode>): Likewise.
2785         (mve_vorrq_s<mode>): Likewise.
2786         (mve_vsbciq_<supf>v4si): Likewise.
2787         (mve_vsbciq_m_<supf>v4si): Likewise.
2788         (mve_vsbcq_<supf>v4si): Likewise.
2789         (mve_vsbcq_m_<supf>v4si): Likewise.
2790         (mve_vshlcq_<supf><mode>): Likewise.
2791         (mve_vshlcq_m_<supf><mode>): Likewise.
2792         (mve_vshrq_m_n_<supf><mode>): Likewise.
2793         (mve_vshrq_n_<supf><mode>): Likewise.
2794         (mve_vstrbq_<supf><mode>): Likewise.
2795         (mve_vstrbq_p_<supf><mode>): Likewise.
2796         (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
2797         (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
2798         (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
2799         (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
2800         (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
2801         (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
2802         (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
2803         (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
2804         (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
2805         (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
2806         (mve_vstrhq_<supf><mode>): Likewise.
2807         (mve_vstrhq_fv8hf): Likewise.
2808         (mve_vstrhq_p_<supf><mode>): Likewise.
2809         (mve_vstrhq_p_fv8hf): Likewise.
2810         (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
2811         (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
2812         (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
2813         (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
2814         (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
2815         (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
2816         (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
2817         (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
2818         (mve_vstrwq_<supf>v4si): Likewise.
2819         (mve_vstrwq_fv4sf): Likewise.
2820         (mve_vstrwq_p_<supf>v4si): Likewise.
2821         (mve_vstrwq_p_fv4sf): Likewise.
2822         (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
2823         (mve_vstrwq_scatter_base_fv4sf): Likewise.
2824         (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
2825         (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
2826         (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
2827         (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
2828         (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
2829         (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
2830         (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
2831         (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
2832         (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
2833         (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
2834         (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
2835         (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
2836         (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
2837         (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
2838
2839 2024-03-04  Marek Polacek  <polacek@redhat.com>
2840
2841         * doc/extend.texi: Update [[gnu::no_dangling]].
2842
2843 2024-03-04  Andrew Stubbs  <ams@baylibre.com>
2844
2845         * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
2846         * expr.cc (store_constructor): Likewise.
2847         (do_store_flag): Likewise.
2848
2849 2024-03-04  Mark Wielaard  <mark@klomp.org>
2850
2851         * common.opt.urls: Regenerate.
2852         * config/avr/avr.opt.urls: Likewise.
2853         * config/i386/i386.opt.urls: Likewise.
2854         * config/pru/pru.opt.urls: Likewise.
2855         * config/riscv/riscv.opt.urls: Likewise.
2856         * config/rs6000/rs6000.opt.urls: Likewise.
2857
2858 2024-03-04  Richard Biener  <rguenther@suse.de>
2859
2860         PR tree-optimization/114197
2861         * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
2862         there are volatile bitfield accesses.
2863         (pass_if_conversion::execute): Throw away result if the
2864         if-converted and original loops are not nested as expected.
2865
2866 2024-03-04  Richard Biener  <rguenther@suse.de>
2867
2868         PR tree-optimization/114164
2869         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
2870         the code generated for mask argument setup is not supported.
2871
2872 2024-03-04  Richard Biener  <rguenther@suse.de>
2873
2874         PR tree-optimization/114203
2875         * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
2876         adjustment before making the result defined at zero.
2877
2878 2024-03-04  Richard Biener  <rguenther@suse.de>
2879
2880         PR tree-optimization/114192
2881         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
2882         appropriate def for the live out stmt in case of an alternate
2883         exit.
2884
2885 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
2886
2887         PR middle-end/114209
2888         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
2889         unshare_expr when creating a MEM_REF from MEM_REF.
2890         (bitint_large_huge::lower_stmt): Call unshare_expr.
2891
2892 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
2893
2894         PR target/114184
2895         * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
2896         is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
2897         register.
2898
2899 2024-03-04  Roger Sayle  <roger@nextmovesoftware.com>
2900
2901         PR target/114187
2902         * simplify-rtx.cc (simplify_context::simplify_subreg): Call
2903         lowpart_subreg to perform type conversion, to avoid confusion
2904         over the offset to use in the call to simplify_reg_subreg.
2905
2906 2024-03-03  Greg McGary  <gkm@rivosinc.com>
2907
2908         PR rtl-optimization/113010
2909         * combine.cc (simplify_comparison): Simplify a SUBREG on
2910         WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
2911         MEM load.
2912
2913 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
2914
2915         * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
2916         Use bool in place of int for boolean logic (if possible).
2917         Move declarations to definitions (if possible).
2918         * config/avr/avr.md: Use C++ comments.  Fix some indentation glitches.
2919         * config/avr/avr-dimode.md: Same.
2920         * config/avr/constraints.md: Same.
2921         * config/avr/predicates.md: Same.
2922
2923 2024-03-03  Uros Bizjak  <ubizjak@gmail.com>
2924
2925         PR target/113720
2926         * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
2927         (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
2928         simplify insn RTX using UMUL_HIGHPART rtx_code.
2929         (*umuldi3_highpart_const): Remove.
2930
2931 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
2932
2933         PR target/114100
2934         * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
2935         * config/avr/avr.cc (_reg_unused_after): Make static.  And
2936         add 3rd argument to skip the current insn.
2937         (reg_unused_after): Adjust call of reg_unused_after.
2938         (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
2939         unneeded frame pointer adjustments.
2940
2941 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
2942
2943         PR target/92729
2944         * config/avr/avr.md (define_attr "cc"): Remove.
2945         * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
2946         from prototype.
2947         * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
2948         its uses.  Add insn argument.
2949         (avr_out_plus_symbol): Remove pcc argument and its uses.
2950         (avr_out_plus): Remove pcc argument and its uses.
2951         Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
2952         (avr_out_round): Adjust call of avr_out_plus.
2953
2954 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
2955
2956         * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
2957         from  r14-9273.
2958
2959 2024-03-03  Oleg Endo  <olegendo@gcc.gnu.org>
2960
2961         PR target/101737
2962         * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
2963         is not an insn, but e.g. a code label.
2964
2965 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
2966
2967         * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
2968         * config/avr/avr.cc: Use them instead of magic numbers when it
2969         means a register number.
2970
2971 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
2972
2973         * config/avr/avr.cc: Adjust some comments.
2974
2975 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
2976
2977         PR target/114100
2978         * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
2979         the low part of the frame pointer with 8-bit stack pointer.
2980
2981 2024-03-01  Patrick Palka  <ppalka@redhat.com>
2982
2983         PR c++/104919
2984         PR c++/106009
2985         * tree-inline.cc (remap_decl): Handle copy_decl returning the
2986         original decl.
2987         (remap_decls): Handle remap_decl returning the original decl.
2988         (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
2989         CONST_DECL.
2990
2991 2024-03-01  Jeff Law  <jlaw@ventanamicro.com>
2992
2993         * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
2994         type attribute.
2995         (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
2996         (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
2997         (movhi_internal, movqi_internal): Likewise.
2998         (movsf_softfloat, movsf_hardfloat): Likewise.
2999         (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
3000         (movdf_softfloat): Likewise.
3001
3002 2024-03-01  Marek Polacek  <polacek@redhat.com>
3003
3004         PR c++/110358
3005         PR c++/109642
3006         * doc/extend.texi: Document gnu::no_dangling.
3007         * doc/invoke.texi: Mention that gnu::no_dangling disables
3008         -Wdangling-reference.
3009
3010 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
3011
3012         * config/avr/avr.opt: Overhaul help screen.
3013
3014 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
3015             Tobias Burnus  <tburnus@baylibre.com>
3016
3017         PR c++/110347
3018         * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
3019         lang_hooks.decls.omp_disregard_value_expr for
3020         (first)private in target regions.
3021
3022 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
3023
3024         PR middle-end/114136
3025         * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
3026         n_named_args initially before INIT_CUMULATIVE_ARGS to
3027         structure_value_addr_parm rather than 0, after it don't modify
3028         it if strict_argument_naming and clear only if
3029         !pretend_outgoing_varargs_named.
3030
3031 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
3032
3033         PR debug/114015
3034         * dwarf2out.cc (should_move_die_to_comdat): Return false for
3035         aggregates without DW_AT_byte_size attribute or with non-constant
3036         DW_AT_byte_size.
3037
3038 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
3039
3040         * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
3041         valid values for level.
3042
3043 2024-03-01  Richard Biener  <rguenther@suse.de>
3044
3045         PR middle-end/114070
3046         * match.pd ((c ? a : b) op d  -->  c ? (a op d) : (b op d)):
3047         Allow the folding if before lowering and the current IL
3048         isn't supported with vcond_mask.
3049
3050 2024-03-01  xuli  <xuli1@eswincomputing.com>
3051
3052         * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
3053         attribute to riscv_attribute_table.
3054         (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
3055         (riscv_fntype_abi): Add riscv_vector_cc attribute check.
3056         * doc/extend.texi: Add riscv_vector_cc attribute description.
3057
3058 2024-03-01  Pan Li  <pan2.li@intel.com>
3059
3060         PR target/112817
3061         * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
3062         RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
3063         * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
3064         (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
3065         * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
3066         comments for option replacement.
3067         * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
3068         riscv_autovec_preference to rvv_vector_bits.
3069         (vls_mode_valid_p): Ditto.
3070         (estimated_poly_value): Ditto.
3071         * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
3072         vector chunks and honor new option mrvv-vector-bits.
3073         (riscv_override_options_internal): Update comments and rename the
3074         vector chunks.
3075         * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
3076         internal option param=riscv-autovec-preference.
3077
3078 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
3079
3080         * function.cc (assign_parms): Only call assign_parms_setup_varargs
3081         early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
3082
3083 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
3084
3085         PR middle-end/114156
3086         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
3087         rhs1 of a VCE to have no underlying variable if it is a load and
3088         handle that case.
3089
3090 2024-02-29  David Malcolm  <dmalcolm@redhat.com>
3091
3092         PR analyzer/114159
3093         * function.cc (function_name): Make param const.
3094         * function.h (function_name): Likewise.
3095
3096 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
3097
3098         PR target/114100
3099         * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
3100         * config/avr/avr.opt (-mfuse-add=): New target option.
3101         * common/config/avr/avr-common.cc (avr_option_optimization_table)
3102         [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
3103         [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
3104         * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
3105         * config/avr/avr-protos.h (avr_split_tiny_move)
3106         (make_avr_pass_fuse_add): New protos.
3107         * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
3108         avr_split_tiny_move to split indirect memory accesses.
3109         (gen_move_clobbercc): New define_expand helper.
3110         * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
3111         (avr_pass_fuse_add): New class from rtl_opt_pass.
3112         (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
3113         (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
3114         (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
3115         of PLUS addressing for AVR_TINY.
3116         (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
3117         (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
3118         (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
3119
3120 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
3121
3122         PR target/114132
3123         * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
3124         * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
3125         (avr_function_arg): Set it.
3126         (avr_frame_pointer_required_p): Use it instead of .nregs.
3127
3128 2024-02-29  Andrew Pinski  <quic_apinski@quicinc.com>
3129
3130         PR target/108174
3131         * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
3132         static and mark with GTY.
3133
3134 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
3135
3136         * config/loongarch/loongarch.md
3137         (loongarch_<crc>_w_<size>_w_extended): New define_insn.
3138
3139 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
3140
3141         * config/loongarch/loongarch.md (CRC): New define_int_iterator.
3142         (crc): New define_int_attr.
3143         (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
3144         into ...
3145         (loongarch_<crc>_w_<size>_w): ... here.
3146
3147 2024-02-29  Kito Cheng  <kito.cheng@sifive.com>
3148
3149         PR target/114130
3150         * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
3151         extend the expected value if needed.
3152
3153 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
3154
3155         * config.gcc (target_gtfiles): Change coreout to btfext-out.
3156         (extra_objs): Change coreout to btfext-out.
3157         * config/bpf/coreout.cc: Rename to btfext-out.cc.
3158         * config/bpf/btfext-out.cc: Add.
3159         * config/bpf/coreout.h: Rename to btfext-out.h.
3160         * config/bpf/btfext-out.h: Add.
3161         * config/bpf/core-builtins.cc: Change include.
3162         * config/bpf/core-builtins.h: Change include.
3163         * config/bpf/t-bpf: Accomodate renamed files.
3164
3165 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
3166
3167         PR target/113453
3168         * config/bpf/bpf.cc (bpf_function_prologue): Define target
3169         hook.
3170         * config/bpf/coreout.cc (brf_ext_info_section)
3171         (btf_ext_info): Move from coreout.h
3172         (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
3173         (bpf_core_reloc): Rename to btf_ext_core_reloc.
3174         (btf_ext): Add static variable.
3175         (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
3176         (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
3177         (btf_ext_add_string, btf_funcinfo_type_callback)
3178         (btf_add_func_info_for, btf_validate_funcinfo)
3179         (btf_ext_info_len, output_btfext_func_info): Add function.
3180         (output_btfext_header, bpf_core_reloc_add)
3181         (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
3182         Change to support new structs.
3183         * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
3184         Move and change in coreout.cc.
3185         (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
3186
3187 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
3188
3189         * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
3190         enabled by default for BPF.
3191         (bpf_file_end): Call BTF deallocation.
3192         (bpf_asm_init_sections): Correct condition.
3193         * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
3194         deallocation.
3195         (ctf_debuf_finish): Correct condition for calling
3196         ctf_debug_finalize.
3197
3198 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
3199
3200         * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
3201         (traverse_btf_func_types): Define function.
3202         * ctfc.h (funcs_traverse_callback): Typedef for function
3203         prototype.
3204         (traverse_btf_func_types): Add prototype.
3205
3206 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
3207
3208         * btfout.cc (btf_collect_dataset): Corrects BTF type id.
3209
3210 2024-02-28  Richard Biener  <rguenther@suse.de>
3211
3212         PR tree-optimization/113831
3213         PR tree-optimization/108355
3214         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
3215         PR113831 fix.
3216
3217 2024-02-28  Richard Biener  <rguenther@suse.de>
3218
3219         PR tree-optimization/114121
3220         * tree-ssa-sccvn.h (vn_reference_s::offset,
3221         vn_reference_s::max_size): New fields.
3222         (vn_reference_insert_pieces): Adjust prototype.
3223         * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
3224         * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
3225         size, allow using "don't know" state.
3226         (vn_walk_cb_data::finish): Pass along offset/max_size.
3227         (vn_reference_lookup_or_insert_for_pieces): Take offset and
3228         max_size as argument and use it.
3229         (vn_reference_lookup_3): Properly adjust offset and max_size
3230         according to the adjusted ao_ref.
3231         (vn_reference_lookup_pieces): Initialize offset and max_size.
3232         (vn_reference_lookup): Likewise.
3233         (vn_reference_lookup_call): Likewise.
3234         (vn_reference_insert): Likewise.
3235         (visit_reference_op_call): Likewise.
3236         (vn_reference_insert_pieces): Take offset and max_size
3237         as argument and use it.
3238
3239 2024-02-28  Juergen Christ  <jchrist@linux.ibm.com>
3240
3241         PR tree-optimization/114075
3242         * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
3243         point vectors
3244
3245 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
3246
3247         PR tree-optimization/114041
3248         * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
3249         INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
3250
3251 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
3252
3253         PR tree-optimization/113988
3254         * stor-layout.h (bitwise_mode_for_size): Declare.
3255         * stor-layout.cc (bitwise_mode_for_size): New function.
3256         * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
3257         Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
3258         Use BITS_PER_UNIT instead of 8.
3259
3260 2024-02-27  Uros Bizjak  <ubizjak@gmail.com>
3261
3262         PR target/113871
3263         * config/i386/mmx.md (V248FI): Add V2BF mode.
3264         (V24FI_32): Ditto.
3265
3266 2024-02-27  Eric Botcazou  <ebotcazou@adacore.com>
3267
3268         * tree-ssa-dse.cc (compute_trims): Fix description.  Return early
3269         if either ref->offset is not byte aligned or ref->size is not known
3270         to be equal to ref->max_size.
3271         (maybe_trim_complex_store): Fix description.
3272         (maybe_trim_constructor_store): Likewise.
3273         (maybe_trim_partially_dead_store): Likewise.
3274
3275 2024-02-27  Richard Earnshaw  <rearnsha@arm.com>
3276
3277         * config/arm/mmintrin.h: Warn if this header is included without
3278         defining __ENABLE_DEPRECATED_IWMMXT.
3279
3280 2024-02-27  Richard Biener  <rguenther@suse.de>
3281
3282         PR tree-optimization/114074
3283         * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
3284         * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
3285         Handle poly vs. non-poly multiplication correctly with respect
3286         to undefined behavior on overflow.
3287
3288 2024-02-27  Jakub Jelinek  <jakub@redhat.com>
3289
3290         PR rtl-optimization/114044
3291         * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
3292         DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
3293         * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
3294         expand_PARITY): Declare.
3295         * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
3296         expand_CTZ, expand_FFS, expand_PARITY): New functions.
3297         (expand_POPCOUNT): Use expand_bitquery.
3298
3299 2024-02-27  Richard Biener  <rguenther@suse.de>
3300
3301         PR tree-optimization/114081
3302         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3303         Perform manual dominator update for prologue peeling.
3304         (vect_do_peeling): Properly update dominators after adding the
3305         prologue-around guard.
3306
3307 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
3308
3309         * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
3310         (mstrict-X): Tag as "Optimization".
3311
3312 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
3313
3314         * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
3315         an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
3316
3317 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
3318             H.J. Lu  <hjl.tools@gmail.com>
3319
3320         PR rtl-optimization/113617
3321         * varasm.cc (default_elf_select_rtx_section): For
3322         references to private symbols in comdat sections
3323         use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
3324         or .rodata.<comdat> comdat sections.
3325
3326 2024-02-26  Richard Biener  <rguenther@suse.de>
3327
3328         PR tree-optimization/114099
3329         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3330         Create and fill in a needed virtual LC PHI for the alternate
3331         exits.  Remove code dealing with that missing.
3332
3333 2024-02-26  Richard Biener  <rguenther@suse.de>
3334
3335         PR tree-optimization/114068
3336         * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
3337         New function.
3338         (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
3339         on the main exit if needed.  Remove band-aid for the case
3340         it was missing.
3341
3342 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
3343
3344         PR target/114097
3345         * config/i386/i386-options.cc (ix86_set_func_type): Check
3346         interrupt instead of noreturn attribute.
3347
3348 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
3349
3350         * config/i386/i386.cc (ix86_bitint_type_info): Add support for
3351         !TARGET_64BIT.
3352
3353 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
3354
3355         PR tree-optimization/114090
3356         * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
3357         Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
3358         types.
3359         ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
3360
3361 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
3362
3363         PR middle-end/114084
3364         * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
3365         if all subtrees of var0 come from one of the op0 or op1 operands
3366         and all subtrees of con0 come from the other one.  Don't clear
3367         variables which are never used afterwards.
3368
3369 2024-02-26  Richard Biener  <rguenther@suse.de>
3370
3371         PR middle-end/114070
3372         * genmatch.cc (parser::parse_c_expr): Do not record operand
3373         lists but only mark operators used.
3374         * match.pd ((c ? a : b) op (c ? d : e)  -->  c ? (a op d) : (b op e)):
3375         Properly guard the case of tcc_comparison changing the VEC_COND
3376         value operand type.
3377
3378 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
3379
3380         PR target/114094
3381         * config/i386/i386.cc (x86_function_profiler): Add missing new-line
3382         to printed instruction.
3383
3384 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
3385
3386         PR target/114098
3387         * config/i386/amxtileintrin.h (_tile_loadconfig): Use
3388         __builtin_ia32_ldtilecfg.
3389         (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
3390         * config/i386/i386-builtin.def (BDESC): Add
3391         __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
3392         * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
3393         IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
3394         * config/i386/i386.md (ldtilecfg): New pattern.
3395         (sttilecfg): Likewise.
3396
3397 2024-02-24  Richard Sandiford  <richard.sandiford@arm.com>
3398
3399         PR tree-optimization/113205
3400         * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
3401         the proposed layout if it does not allow a source partition with
3402         layout 2 to keep that layout.
3403
3404 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
3405
3406         * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
3407         * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
3408         * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
3409         * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
3410         (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
3411         * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
3412         macros.
3413         * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
3414         * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
3415         * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
3416         HOST_WIDE_INT_UC macros.
3417         * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
3418         * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
3419         * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
3420         * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
3421         macros.
3422         * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
3423         * config/i386/constraints.md (define_constraint "L"): Use
3424         HOST_WIDE_INT_C macro.
3425         * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
3426         macro.
3427         (movl + movb peephole2): Likewise.
3428         * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
3429         (const_32bit_mask): Likewise.
3430
3431 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
3432
3433         PR middle-end/114073
3434         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
3435         VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
3436         types like vector or complex types.
3437         (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
3438         types.  Fix up VIEW_CONVERT_EXPR handling.  Allow merging
3439         VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
3440
3441 2024-02-23  Robin Dapp  <rdapp@ventanamicro.com>
3442
3443         PR target/114028
3444         * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
3445         Return false if inner mode is already Pmode.
3446         (rvv_builder::is_all_same_sequence): New function.
3447         (expand_vec_init): Emit broadcast if sequence is all same.
3448
3449 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
3450
3451         PR target/113613
3452         * config/aarch64/aarch64-early-ra.cc
3453         (early_ra::m_current_region): New member variable.
3454         (early_ra::m_fpr_recency): Likewise.
3455         (early_ra::start_new_region): Bump m_current_region.
3456         (early_ra::allocate_colors): Prefer less recently used registers
3457         in the event of a tie.  Add a comment to explain why we prefer(ed)
3458         higher-numbered registers.
3459         (early_ra::find_oldest_color): Prefer less recently used registers
3460         here too.
3461         (early_ra::finalize_allocation): Update recency information for
3462         allocated registers.
3463         (early_ra::process_blocks): Initialize m_current_region and
3464         m_fpr_recency.
3465
3466 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
3467
3468         PR target/113295
3469         * config/aarch64/aarch64-early-ra.cc
3470         (early_ra::test_strictness): New enum.
3471         (early_ra::is_chain_candidate): Add a strictness parameter to
3472         control whether only correctness matters, or whether both correctness
3473         and heuristics should be used.  Handle multiple levels of equivalence.
3474         (early_ra::find_related_start): Update call accordingly.
3475         (early_ra::strided_polarity_pref): Likewise.
3476         (early_ra::form_chains): Likewise.
3477         (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
3478         correctness mode rather than trying to inline the test.
3479
3480 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
3481
3482         PR target/113295
3483         * config/aarch64/aarch64-early-ra.cc
3484         (early_ra::find_related_start): Account for definitions by shared
3485         registers when testing for a single register definition.
3486         (early_ra::accumulate_defs): New function.
3487         (early_ra::record_copy): If A shares B's register, fold A's
3488         definition information into B's.  Fold A's use information into B's.
3489
3490 2024-02-23  H.J. Lu  <hjl.tools@gmail.com>
3491
3492         * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
3493         if R_X86_64_CODE_6_GOTTPOFF is supported.
3494         * config.in: Regenerated.
3495         * configure: Likewise.
3496         * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
3497         UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
3498
3499 2024-02-23  Richard Earnshaw  <rearnsha@arm.com>
3500
3501         PR target/108120
3502         * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
3503         Gate with ARM_HAVE_NEON_<MODE>_ARITH.
3504
3505 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
3506
3507         PR rtl-optimization/114054
3508         * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
3509         temp variable instead of target parameter for result.
3510
3511 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
3512
3513         PR tree-optimization/114040
3514         * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
3515         Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
3516         probability from likely to unlikely.  When handling the true true
3517         store, first cast to limb_access_type and then to l's type.
3518
3519 2024-02-23  Richard Biener  <rguenther@suse.de>
3520
3521         PR target/90785
3522         * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
3523
3524 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
3525
3526         PR other/109668
3527         * config/riscv/arch-canonicalize: Move to python3
3528         * config/riscv/multilib-generator: Likewise
3529
3530 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
3531
3532         * doc/invoke.texi: Document -mcpu.
3533
3534 2024-02-23  Lulu Cheng  <chenglulu@loongson.cn>
3535
3536         * configure: Regenerate.
3537         * configure.ac: Add parameter "--fatal-warnings" to assemble
3538         when checking whether the assemble support conditional branch
3539         relaxation.
3540
3541 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
3542
3543         PR c/114007
3544         * doc/extend.texi: (__extension__): Remove comments about scope
3545         tokens vs. two colons.
3546
3547 2024-02-22  Andrew Pinski  <quic_apinski@quicinc.com>
3548
3549         PR tree-optimization/109804
3550         * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
3551         DEMANGLE_COMPONENT_UNNAMED_TYPE.
3552
3553 2024-02-22  Richard Biener  <rguenther@suse.de>
3554
3555         PR tree-optimization/114048
3556         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
3557         can also produce -1 off.
3558
3559 2024-02-22  Richard Biener  <rguenther@suse.de>
3560
3561         PR tree-optimization/114027
3562         * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
3563         condition reduction classification only for single-element
3564         chains.
3565
3566 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
3567
3568         PR ipa/111960
3569         * profile-count.h (profile_count::dump): Remove overload with
3570         char * first argument.
3571         * profile-count.cc (profile_count::dump): Change overload with char *
3572         first argument which uses sprintf into the overfload with FILE *
3573         first argument and use fprintf instead.  Remove overload which wrapped
3574         it.
3575
3576 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
3577
3578         PR tree-optimization/113993
3579         * tree-call-cdce.cc (get_no_error_domain): Handle
3580         BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}.  Handle
3581         BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
3582         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
3583         the as the F128 suffixed cases, otherwise as non-suffixed ones.
3584         Handle BUILT_IN_{EXP,POW}10L for
3585         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
3586         as (-inf, 4932).
3587
3588 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
3589
3590         PR tree-optimization/114038
3591         * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
3592         loop exit condition if end is divisible by limb_prec.
3593
3594 2024-02-22  YunQiang Su  <syq@gcc.gnu.org>
3595
3596         * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
3597         problem of mabi=, mno-flush-func, mexplicit-relocs;
3598         add missing leading - of mbranch-cost option.
3599         * config/mips/mips.opt.urls: Regenerate.
3600
3601 2024-02-22  Kewen Lin  <linkw@linux.ibm.com>
3602
3603         PR target/109987
3604         * config/rs6000/constraints.md (we): Update internal doc without
3605         referring to option -mpower9-vector.
3606         * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
3607         special handlings.
3608         * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
3609         OTHER_P8_VECTOR_MASKS): Merge to ...
3610         (OTHER_VSX_VECTOR_MASKS): ... here.
3611         * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
3612         some error message handlings and explicit option mask adjustments on
3613         explicit option power{8,9}-vector conflicting with other options.
3614         (rs6000_print_isa_options): Update comments.
3615         (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
3616         related array items and handlings.
3617         * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
3618         special handlings.
3619         * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
3620         WarnRemoved.
3621         * doc/extend.texi: Remove documentation referring to option
3622         -mpower8-vector.
3623         * doc/invoke.texi: Remove documentation for option
3624         -mpower{8,9}-vector and adjust some documentation referring to them.
3625         * doc/md.texi: Update documentation for constraint we.
3626         * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
3627
3628 2024-02-22  Pan Li  <pan2.li@intel.com>
3629
3630         PR target/114017
3631         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
3632         the version to 0.12.
3633
3634 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
3635
3636         * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
3637
3638 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
3639             Robin Dapp  <rdapp.gcc@gmail.com>
3640
3641         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3642         (generic_ooo_vec_load): Ditto
3643         (generic_ooo_vec_store): Ditto
3644         (generic_ooo_vec_loadstore_seg): Ditto
3645         (generic_ooo_vec_alu): Ditto
3646         (generic_ooo_vec_fcmp): Ditto
3647         (generic_ooo_vec_imul): Ditto
3648         (generic_ooo_vec_fadd): Ditto
3649         (generic_ooo_vec_fmul): Ditto
3650         (generic_ooo_crypto): Ditto
3651         (generic_ooo_perm): Ditto
3652         (generic_ooo_vec_reduction): Ditto
3653         (generic_ooo_vec_ordered_reduction): Ditto
3654         (generic_ooo_vec_idiv): Ditto
3655         (generic_ooo_vec_float_divsqrt): Ditto
3656         (generic_ooo_vec_mask): Ditto
3657         (generic_ooo_vec_vesetvl): Ditto
3658         (generic_ooo_vec_setrm): Ditto
3659         (generic_ooo_vec_readlen): Ditto
3660         * config/riscv/riscv.md: Include generic-vector-ooo
3661         * config/riscv/generic-vector-ooo.md: New file. To here
3662
3663 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
3664
3665         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3666         (generic_ooo_branch): Ditto
3667         * config/riscv/generic.md (generic_sfb_alu): Ditto
3668         (generic_fmul_half): Ditto
3669         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3670         * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
3671         (sifive_7_popcount): Ditto
3672         * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
3673         * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
3674         * config/riscv/vector.md: Change rdfrm to fmove
3675         * config/riscv/zc.md: Change pushpop to load/store
3676
3677 2024-02-21  Jonathan Wakely  <jwakely@redhat.com>
3678
3679         * doc/invoke.texi (Warning Options): Fix typos.
3680
3681 2024-02-21  David Faust  <david.faust@oracle.com>
3682
3683         * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
3684         * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
3685         * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
3686
3687 2024-02-21  Martin Jambor  <mjambor@suse.cz>
3688
3689         PR ipa/113476
3690         * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
3691         initializers in the contructor.
3692         (ipa_node_params::~ipa_node_params): Release lattices as a vector.
3693         * ipa-cp.h: New file.
3694         * ipa-cp.cc: Include sreal.h and ipa-cp.h.
3695         (ipcp_value_source): Move to ipa-cp.h.
3696         (ipcp_value_base): Likewise.
3697         (ipcp_value): Likewise.
3698         (ipcp_lattice): Likewise.
3699         (ipcp_agg_lattice): Likewise.
3700         (ipcp_bits_lattice): Likewise.
3701         (ipcp_vr_lattice): Likewise.
3702         (ipcp_param_lattices): Likewise.
3703         (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
3704         (ipa_value_from_jfunc): Adjust a check for empty lattices.
3705         (ipa_context_from_jfunc): Likewise.
3706         (ipa_agg_value_from_jfunc): Likewise.
3707         (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
3708         (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
3709         just in contiguous memory.
3710         (ipcp_store_vr_results): Adjust a check for empty lattices.
3711         * auto-profile.cc: Include sreal.h and ipa-cp.h.
3712         * cgraph.cc: Likewise.
3713         * cgraphclones.cc: Likewise.
3714         * cgraphunit.cc: Likewise.
3715         * config/aarch64/aarch64.cc: Likewise.
3716         * config/i386/i386-builtins.cc: Likewise.
3717         * config/i386/i386-expand.cc: Likewise.
3718         * config/i386/i386-features.cc: Likewise.
3719         * config/i386/i386-options.cc: Likewise.
3720         * config/i386/i386.cc: Likewise.
3721         * config/rs6000/rs6000.cc: Likewise.
3722         * config/s390/s390.cc: Likewise.
3723         * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
3724         files to be included in gtype-desc.cc.
3725         * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
3726         * ipa-devirt.cc: Likewise.
3727         * ipa-fnsummary.cc: Likewise.
3728         * ipa-icf.cc: Likewise.
3729         * ipa-inline-analysis.cc: Likewise.
3730         * ipa-inline-transform.cc: Likewise.
3731         * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
3732         * ipa-modref.cc: Include sreal.h and ipa-cp.h.
3733         * ipa-param-manipulation.cc: Likewise.
3734         * ipa-predicate.cc: Likewise.
3735         * ipa-profile.cc: Likewise.
3736         * ipa-prop.cc: Likewise.
3737         (ipa_node_params_t::duplicate): Assert new lattices remain empty
3738         instead of setting them to NULL.
3739         * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
3740         * ipa-split.cc: Likewise.
3741         * ipa-sra.cc: Likewise.
3742         * ipa-strub.cc: Likewise.
3743         * ipa-utils.cc: Likewise.
3744         * ipa.cc: Likewise.
3745         * toplev.cc: Likewise.
3746         * tree-ssa-ccp.cc: Likewise.
3747         * tree-ssa-sccvn.cc: Likewise.
3748         * tree-vrp.cc: Likewise.
3749
3750 2024-02-21  Tamar Christina  <tamar.christina@arm.com>
3751
3752         * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
3753         Armv8.7-a.
3754
3755 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
3756
3757         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
3758         Use aarch64_gen_compare_zero_and_branch rather than emitting
3759         a CBZ directly.
3760
3761 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
3762
3763         * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
3764         Remove duplicated call.
3765
3766 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
3767
3768         * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
3769         Check that each individual piece of state is shared in the same
3770         way, rather than using an aggregate check for PSTATE.ZA.
3771
3772 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
3773
3774         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
3775         In the code that commits a lazy save, only zero ZA if the function
3776         has ZA state.  Similarly zero ZT0 if the function has ZT0 state.
3777
3778 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
3779
3780         * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
3781         directly inserting the associated sequence
3782         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
3783         ...here instead.
3784
3785 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
3786
3787         PR target/113995
3788         * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
3789         fold the SVE allocation into the initial allocation if the
3790         initial allocation includes a VG save.
3791
3792 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
3793
3794         PR target/113220
3795         * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
3796         contain jumps even if called after initial RTL expansion.
3797         * mode-switching.cc: Include cfgbuild.h.
3798         (optimize_mode_switching): Allow the sequence returned by the
3799         emit hook to contain internal jumps.  Record which blocks
3800         contain such jumps and split the blocks at the end.
3801         * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
3802         non-debug insns when scanning the sequence.
3803
3804 2024-02-21  Tobias Burnus  <tburnus@baylibre.com>
3805
3806         * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
3807         * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
3808
3809 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
3810
3811         * doc/invoke.texi (-mmcu): Add information about MCU specs.
3812
3813 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
3814
3815         * doc/invoke.texi (-minrt): Clarify that main
3816         must take no arguments.
3817
3818 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
3819
3820         * config/avr/builtins.def: Use function prototypes of given size
3821         and signedness.
3822         * config/avr/avr.cc (avr_init_builtins): Adjust types required
3823         by builtins.def.
3824         * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
3825
3826 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
3827
3828         * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
3829         instead of @table.
3830
3831 2024-02-20  Will Hawkins  <hawkinsw@obs.cr>
3832
3833         * config/bpf/bpf.opt: Add help information for -mcpu.
3834
3835 2024-02-20  Richard Sandiford  <richard.sandiford@arm.com>
3836
3837         PR target/113805
3838         * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
3839         New pass.
3840         * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
3841         Declare.
3842         * config/aarch64/aarch64.md (is_call): New attribute.
3843         (*and<mode>3nr_compare0): Rename to...
3844         (@aarch64_and<mode>3nr_compare0): ...this.
3845         * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
3846         (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
3847         * config/aarch64/aarch64-speculation.cc: Update file comment to
3848         describe the new late pass.
3849         (aarch64_do_track_speculation): Handle is_call insns like other calls.
3850         (pass_track_speculation): Add an is_late member variable.
3851         (pass_track_speculation::gate): Run the late pass for streaming-
3852         compatible functions and the early pass for other functions.
3853         (make_pass_track_speculation): Update accordingly.
3854         (make_pass_late_track_speculation): New function.
3855         * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
3856         function.
3857         (aarch64_guard_switch_pstate_sm): Use it.
3858
3859 2024-02-19  Iain Sandoe  <iain@sandoe.co.uk>
3860
3861         * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
3862         Register these builtins with a pointer to uint64_t rather than unsigned
3863         DI mode.
3864
3865 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
3866
3867         PR target/113615
3868         * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
3869         Conditionalize on '!TARGET_RDNA2_PLUS'.
3870         * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
3871         (gcn_expand_reduc_scalar):
3872         'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
3873
3874 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
3875
3876         * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
3877         '__gfx90a__' target CPU definition.  Add some safeguards for the future.
3878
3879 2024-02-19  Richard Biener  <rguenther@suse.de>
3880
3881         PR rtl-optimization/54052
3882         * rtl-ssa/blocks.cc (function_info::place_phis): Filter
3883         local defs by LR_OUT.
3884
3885 2024-02-19  Jakub Jelinek  <jakub@redhat.com>
3886
3887         PR tree-optimization/113967
3888         * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
3889         in condition that @rpos is multiple of vector element size.
3890
3891 2024-02-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3892
3893         PR target/113696
3894         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
3895         Suppress vsetvl fusion.
3896
3897 2024-02-18  H.J. Lu  <hjl.tools@gmail.com>
3898
3899         PR target/113912
3900         * config/i386/i386.cc (ix86_can_use_push2pop2): New.
3901         (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
3902         (ix86_emit_save_regs): Don't generate push2 if
3903         ix86_can_use_push2pop2 return false.
3904         (ix86_expand_epilogue): Don't generate pop2 if
3905         ix86_can_use_push2pop2 return false.
3906
3907 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
3908
3909         * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
3910         Note on complete device support.
3911
3912 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
3913
3914         * doc/extend.texi (AVR Function Attributes): Fuse description
3915         of "signal" and "interrupt" attribute.  Link pseudo instruction.
3916
3917 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
3918
3919         * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
3920         symbol type conversions.
3921         (__cacop_d): Likewise.
3922         (__cpucfg): Likewise.
3923         (__asrtle_d): Likewise.
3924         (__asrtgt_d): Likewise.
3925         (__lddir_d): Likewise.
3926         (__ldpte_d): Likewise.
3927         (__crc_w_b_w): Likewise.
3928         (__crc_w_h_w): Likewise.
3929         (__crc_w_w_w): Likewise.
3930         (__crc_w_d_w): Likewise.
3931         (__crcc_w_b_w): Likewise.
3932         (__crcc_w_h_w): Likewise.
3933         (__crcc_w_w_w): Likewise.
3934         (__crcc_w_d_w): Likewise.
3935         (__csrrd_w): Likewise.
3936         (__csrwr_w): Likewise.
3937         (__csrxchg_w): Likewise.
3938         (__csrrd_d): Likewise.
3939         (__csrwr_d): Likewise.
3940         (__csrxchg_d): Likewise.
3941         (__iocsrrd_b): Likewise.
3942         (__iocsrrd_h): Likewise.
3943         (__iocsrrd_w): Likewise.
3944         (__iocsrrd_d): Likewise.
3945         (__iocsrwr_b): Likewise.
3946         (__iocsrwr_h): Likewise.
3947         (__iocsrwr_w): Likewise.
3948         (__iocsrwr_d): Likewise.
3949         (__frecipe_s): Likewise.
3950         (__frecipe_d): Likewise.
3951         (__frsqrte_s): Likewise.
3952         (__frsqrte_d): Likewise.
3953
3954 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
3955
3956         * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
3957         function return value type to unsigned short.
3958
3959 2024-02-16  Edwin Lu  <ewlu@rivosinc.com>
3960
3961         * doc/sourcebuild.texi: add scan-assembler-bound
3962
3963 2024-02-16  Jason Merrill  <jason@redhat.com>
3964
3965         * gdbhooks.py: Fix regex syntax.
3966
3967 2024-02-16  Richard Biener  <rguenther@suse.de>
3968
3969         PR tree-optimization/113895
3970         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
3971         consistency checking when there are out-of-bound array
3972         accesses.  Allow -1 off when from an array reference with
3973         constant index.
3974
3975 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
3976
3977         PR target/106543
3978         * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
3979         pattern.
3980
3981 2024-02-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
3982
3983         * doc/sourcebuild.texi (Effective-Target Keywords, Other
3984         attribugs): Document linker_plugin.
3985         (Require Support): Document dg-require-linker-plugin.
3986
3987 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
3988
3989         PR target/109349
3990         * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
3991         * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
3992         (RISCV_MINOR_VERSION_BASE): Ditto.
3993         (RISCV_REVISION_VERSION_BASE): Ditto.
3994         * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
3995         rather than magic number.
3996         * config/riscv/riscv.h (riscv_arch_help): New.
3997         (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
3998         (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
3999         --print-supported-extensions.
4000         * config/riscv/riscv.opt (march=help): New.
4001         (print-supported-extensions): New.
4002         (-print-supported-extensions): New.
4003         * doc/invoke.texi (RISC-V Options): Document -march=help.
4004
4005 2024-02-16  Tejas Belagod  <tejas.belagod@arm.com>
4006
4007         PR target/113780
4008         * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
4009         for indirect calls with 4 or more arguments in pac-enabled functions.
4010
4011 2024-02-15  David Faust  <david.faust@oracle.com>
4012
4013         * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
4014         use ldxb instead of ldxh.
4015
4016 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
4017
4018         PR middle-end/113921
4019         * cfgrtl.h (prepend_insn_to_edge): New declaration.
4020         * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
4021         comment.
4022         (prepend_insn_to_edge): New function.
4023         * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
4024         insert_insn_on_edge.
4025
4026 2024-02-15  Richard Biener  <rguenther@suse.de>
4027
4028         PR tree-optimization/111156
4029         * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
4030         at the pattern stmt if any.
4031
4032 2024-02-15  Georg-Johann Lay  <avr@gjlay.de>
4033
4034         PR target/113927
4035         * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
4036         * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
4037         * config/avr/avr.cc (avr_adiw_reg_p): New function.
4038         (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
4039         Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
4040         * config/avr/avr.md: Same.
4041         (attr "isa") <tiny, no_tiny>: Remove.
4042         <adiw, no_adiw>: Add.
4043         (define_insn, define_insn_and_split): When an alternative has
4044         constraint "w", then set attribute "isa" to "adiw".
4045         * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
4046         Built-in define __AVR_HAVE_ADIW__.
4047         * doc/invoke.texi (AVR Options): Document it.
4048
4049 2024-02-15  Andrew Stubbs  <ams@baylibre.com>
4050
4051         * config/gcn/gcn-valu.md
4052         (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
4053         * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
4054         details are supported on RDNA devices.
4055
4056 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
4057
4058         PR middle-end/113508
4059         * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
4060         usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
4061         smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
4062         Add sentence about what the mode m is.
4063
4064 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
4065
4066         * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
4067         smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
4068         var.
4069
4070 2024-02-15  Richard Biener  <rguenther@suse.de>
4071
4072         * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
4073         stmts.
4074
4075 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
4076
4077         PR tree-optimization/113567
4078         * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
4079         _BitInt multiplication, division or modulo with
4080         SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
4081         force the affected inputs into a new SSA_NAME.
4082
4083 2024-02-14  Uros Bizjak  <ubizjak@gmail.com>
4084
4085         PR target/113871
4086         * config/i386/mmx.md (V248FI): New mode iterator.
4087         (V24FI_32): DItto.
4088         (vec_shl_<V248FI:mode>): New expander.
4089         (vec_shl_<V24FI_32:mode>): Ditto.
4090         (vec_shr_<V248FI:mode>): Ditto.
4091         (vec_shr_<V24FI_32:mode>): Ditto.
4092         * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
4093         (vec_shr_<V248FI:mode>): Ditto.
4094
4095 2024-02-14  Jan Hubicka  <jh@suse.cz>
4096
4097         PR tree-optimization/111054
4098         * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
4099
4100 2024-02-14  Tamar Christina  <tamar.christina@arm.com>
4101
4102         * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
4103
4104 2024-02-14  Richard Biener  <rguenther@suse.de>
4105
4106         PR tree-optimization/113910
4107         * bitmap.cc (bitmap_hash): Mix the full element "hash" to
4108         the hashval_t hash.
4109
4110 2024-02-14  Jakub Jelinek  <jakub@redhat.com>
4111
4112         * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
4113         (pp_integer_with_precision): For unsigned ptrdiff_t printing
4114         with u, o or x print ptrdiff_t argument converted to
4115         unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
4116
4117 2024-02-14  Richard Biener  <rguenther@suse.de>
4118
4119         PR middle-end/113576
4120         * expr.cc (do_store_flag): For vector bool compares of vectors
4121         with padding zero that.
4122         * dojump.cc (do_compare_and_jump): Likewise.
4123
4124 2024-02-14  Gerald Pfeifer  <gerald@pfeifer.com>
4125
4126         * doc/install.texi (Prerequisites): Update gettext link.
4127
4128 2024-02-13  H.J. Lu  <hjl.tools@gmail.com>
4129
4130         PR target/113876
4131         * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
4132         Return false if the incoming stack isn't 16-byte aligned.
4133
4134 2024-02-13  Tobias Burnus  <tburnus@baylibre.com>
4135
4136         PR middle-end/113904
4137         * omp-general.cc (struct omp_ts_info): Update for splitting of
4138         OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
4139         * omp-selectors.h (enum omp_tp_type): Replace
4140         OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
4141
4142 2024-02-13  Monk Chiang  <monk.chiang@sifive.com>
4143
4144         PR target/113742
4145         * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
4146         recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
4147
4148 2024-02-13  Richard Biener  <rguenther@suse.de>
4149
4150         PR tree-optimization/113895
4151         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
4152         offset to discover constant array indices in bits, handle
4153         COMPONENT_REF to bitfields.
4154
4155 2024-02-13  Richard Biener  <rguenther@suse.de>
4156
4157         PR tree-optimization/113831
4158         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
4159         typo in comment.
4160
4161 2024-02-13  Richard Biener  <rguenther@suse.de>
4162
4163         PR tree-optimization/113902
4164         * tree-vect-loop.cc (move_early_exit_stmts): Track
4165         last_seen_vuse for VUSE updating.
4166
4167 2024-02-13  Tamar Christina  <tamar.christina@arm.com>
4168
4169         PR tree-optimization/113734
4170         * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
4171         an early break loop as partial.
4172
4173 2024-02-13  Richard Biener  <rguenther@suse.de>
4174
4175         PR tree-optimization/113898
4176         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
4177         missing accumulated off adjustment.
4178
4179 2024-02-13  Jakub Jelinek  <jakub@redhat.com>
4180
4181         * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
4182         instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
4183         it against UINT_MAX and ULONG_MAX.
4184
4185 2024-02-13  David Malcolm  <dmalcolm@redhat.com>
4186
4187         * diagnostic-core.h (emit_diagnostic_valist): Rename overload
4188         to...
4189         (emit_diagnostic_valist_meta): ...this.
4190         * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
4191         (emit_diagnostic_valist_meta): ...this.
4192
4193 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
4194
4195         PR tree-optimization/113849
4196         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
4197         fast path for widening casts where !m_upwards_2limb and lhs_type
4198         has precision which is a multiple of limb_prec.
4199
4200 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
4201
4202         PR c++/113674
4203         * attribs.cc (extract_attribute_substring): Remove.
4204         (lookup_scoped_attribute_spec): Don't call it.
4205
4206 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
4207
4208         * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
4209         and cast to fmt_size_t instead of %lu and cast to unsigned long.
4210
4211 2024-02-12  Christophe Lyon  <christophe.lyon@linaro.org>
4212
4213         * Makefile.in: Add no-info dependency.
4214         * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
4215         available.
4216         * configure: Regenerate.
4217
4218 2024-02-12  Iain Sandoe  <iain@sandoe.co.uk>
4219
4220         PR target/113855
4221         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
4222         available to all sub-targets.
4223         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
4224         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
4225
4226 2024-02-12  Richard Biener  <rguenther@suse.de>
4227
4228         PR tree-optimization/113831
4229         PR tree-optimization/108355
4230         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
4231         we see variable array indices and get_ref_base_and_extent
4232         can resolve those to constants fix up the ops to constants
4233         as well.
4234         (ao_ref_init_from_vn_reference): Use 'off' member for
4235         ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
4236         (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
4237
4238 2024-02-12  Pan Li  <pan2.li@intel.com>
4239
4240         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
4241         Replace args to arguments for misspelled term.
4242
4243 2024-02-12  Georg-Johann Lay  <avr@gjlay.de>
4244
4245         PR target/112944
4246         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
4247         <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
4248         when not linked with -mrodata-in-ram.
4249
4250 2024-02-12  Richard Biener  <rguenther@suse.de>
4251
4252         PR tree-optimization/113863
4253         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
4254         Record crossed virtual PHIs.
4255         * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
4256         virtual PHIs.
4257
4258 2024-02-10  Marek Polacek  <polacek@redhat.com>
4259
4260         DR 2237
4261         PR c++/107126
4262         PR c++/97202
4263         * doc/invoke.texi: Document -Wtemplate-id-cdtor.
4264
4265 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
4266
4267         * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
4268         computation of idx for i == 4 of bitint_prec_huge.
4269
4270 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
4271
4272         PR middle-end/110754
4273         * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
4274         decls create PARM_DECL with pointer to original type, set
4275         TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
4276         DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
4277         (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
4278         wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
4279         (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
4280         of the var as argument.
4281
4282 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
4283
4284         * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
4285         size_t and precision 4 for ptrdiff_t.  Formatting fix.
4286         (pp_format): Document %{t,z}{d,i,u,o,x}.  Implement t and z modifiers.
4287         Formatting fixes.
4288         (test_pp_format): Test t and z modifiers.
4289         * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
4290
4291 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
4292
4293         * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
4294         sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
4295         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
4296         * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
4297         and casts to fmt_size_t instead of "%ld" and casts to long.
4298         (print_value_expr_statistics, print_type_hash_statistics): Likewise.
4299         * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
4300         instead of "%lu" and casts to unsigned long.
4301         * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
4302         unsigned long.
4303         * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
4304         and casts to fmt_size_t instead of "%ld" and casts to long.
4305         * cfgexpand.cc (dump_stack_var_partition): Use
4306         HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
4307         and casts to unsigned long.
4308         * gengtype.cc (adjust_field_rtx_def): Likewise.
4309         * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
4310         and casts to fmt_size_t instead of "%ld" and casts to long.
4311         * postreload-gcse.cc (dump_hash_table): Likewise.
4312         * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
4313         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
4314         (ggc_internal_alloc, ggc_free): Likewise.
4315         * genpreds.cc (write_lookup_constraint_1): Likewise.
4316         (write_insn_constraint_len): Likewise.
4317         * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
4318         and casts to fmt_size_t instead of "%ld" and casts to long.
4319         * varasm.cc (output_constant_pool_contents): Use
4320         HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
4321         * var-tracking.cc (dump_var): Likewise.
4322
4323 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
4324
4325         PR tree-optimization/113783
4326         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
4327         through VIEW_CONVERT_EXPR for final cast checks.  Handle
4328         VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
4329         INTEGER_TYPEs.
4330         (gimple_lower_bitint): Don't merge mergeable operations or other
4331         casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
4332         * expr.cc (expand_expr_real_1): Don't use convert_modes if either
4333         mode is BLKmode.
4334
4335 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
4336
4337         * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
4338         HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
4339         HOST_SIZE_T_PRINT_HEX_PURE): Define.
4340         * ira-conflicts.cc (build_conflict_bit_table): Use it.  Formatting
4341         fixes.
4342
4343 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
4344
4345         PR middle-end/113415
4346         * cfgexpand.cc (expand_asm_stmt): For asm goto, use
4347         duplicate_insn_chain to duplicate after_rtl_seq sequence instead
4348         of hand written loop with emit_insn of copy_insn and emit original
4349         after_rtl_seq on the last edge.
4350
4351 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
4352
4353         PR tree-optimization/113818
4354         * gimple-lower-bitint.cc (add_eh_edge): New function.
4355         (bitint_large_huge::handle_load,
4356         bitint_large_huge::lower_mergeable_stmt,
4357         bitint_large_huge::lower_muldiv_stmt): Use it.
4358
4359 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
4360
4361         PR tree-optimization/113774
4362         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
4363         emit any comparison if m_first and low + 1 is equal to
4364         m_upwards_2limb, simplify condition for that.  If not
4365         single_comparison, not m_first and we can prove that the idx <= low
4366         comparison will be always true, emit instead of idx <= low
4367         comparison low <= low such that cfg cleanup will optimize it at
4368         the end of the pass.
4369
4370 2024-02-08  Aldy Hernandez  <aldyh@redhat.com>
4371
4372         PR tree-optimization/113735
4373         * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
4374         limit_check().
4375
4376 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
4377
4378         * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
4379         (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
4380
4381 2024-02-08  H.J. Lu  <hjl.tools@gmail.com>
4382
4383         PR target/113711
4384         PR target/113733
4385         * config/i386/constraints.md: List all constraints with j prefix.
4386         (j>): Change auto-dec to auto-inc in documentation.
4387         (je): Changed to a memory constraint with APX NDD TLS operand
4388         check.
4389         (jM): New memory constraint for APX NDD instructions.
4390         (jO): Likewise.
4391         * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
4392         * config/i386/i386.cc (x86_poff_operand_p): Likewise.
4393         * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
4394         (*add<mode>_1[SWI48]): Use je and jM.
4395         (addsi_1_zext): Use jM.
4396         (*addv<dwi>4_doubleword_1[DWI]): Likewise.
4397         (*sub<mode>_1[SWI]): Use jM.
4398         (@add<mode>3_cc_overflow_1[SWI]): Likewise.
4399         (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
4400         (*and<dwi>3_doubleword): Likewise.
4401         (*anddi_1): Use jM.
4402         (*andsi_1_zext): Likewise.
4403         (*and<mode>_1[SWI24]): Likewise.
4404         (*<code><dwi>3_doubleword[any_or]): Use rjO
4405         (*code<mode>_1[any_or SWI248]): Use jM.
4406         (*<code>si_1_zext[zero_extend + any_or]): Likewise.
4407         * config/i386/predicates.md (apx_ndd_memory_operand): New.
4408         (apx_ndd_add_memory_operand): Likewise.
4409
4410 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
4411
4412         PR target/113824
4413         * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
4414         * doc/avr-mmcu.texi: Rebuild.
4415
4416 2024-02-08  Tamar Christina  <tamar.christina@arm.com>
4417
4418         PR tree-optimization/113808
4419         * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
4420         value cross iterations.
4421
4422 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
4423
4424         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
4425         defines __AVR_PM_BASE_ADDRESS__ if the core has it.
4426
4427 2024-02-08  Richard Biener  <rguenther@suse.de>
4428
4429         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
4430         Revert last change to dr_may_alias_p.
4431
4432 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
4433
4434         * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
4435         cc1_rodata_in_ram.  Rename spec link_misc to link_rodata_in_ram.
4436         Remove spec asm_misc.
4437         * config/avr/specs.h: Same.
4438
4439 2024-02-08  Pan Li  <pan2.li@intel.com>
4440
4441         PR target/113766
4442         * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
4443         sure the c.arg_num is >= 2 before checking.
4444         (struct build_frm_base): Ditto.
4445         (struct narrow_alu_def): Ditto.
4446
4447 2024-02-07  Richard Biener  <rguenther@suse.de>
4448
4449         PR tree-optimization/113796
4450         * tree-if-conv.cc (combine_blocks): Wipe range-info before
4451         replacing PHIs and inserting predicates.
4452
4453 2024-02-07  Roger Sayle  <roger@nextmovesoftware.com>
4454             Uros Bizjak  <ubizjak@gmail.com>
4455
4456         PR target/113690
4457         * config/i386/i386-features.cc (timode_convert_cst): New helper
4458         function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
4459         CONST_VECTOR.
4460         (timode_scalar_chain::convert_op): Use timode_convert_cst.
4461         (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
4462         Use timode_convert_cst.
4463
4464 2024-02-07  Victor Do Nascimento  <victor.donascimento@arm.com>
4465
4466         * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
4467         * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
4468         (AARCH64_FL_DEBUGv8p9): Likewise.
4469         (AARCH64_FL_FGT2): Likewise.Likewise.
4470         (AARCH64_FL_ITE): Likewise.
4471         (AARCH64_FL_PFAR): Likewise.
4472         (AARCH64_FL_PMUv3_ICNTR): Likewise.
4473         (AARCH64_FL_PMUv3_SS): Likewise.
4474         (AARCH64_FL_PMUv3p9): Likewise.
4475         (AARCH64_FL_RASv2): Likewise.
4476         (AARCH64_FL_S1PIE): Likewise.
4477         (AARCH64_FL_S1POE): Likewise.
4478         (AARCH64_FL_S2PIE): Likewise.
4479         (AARCH64_FL_S2POE): Likewise.
4480         (AARCH64_FL_SCTLR2): Likewise.
4481         (AARCH64_FL_SEBEP): Likewise.
4482         (AARCH64_FL_SPE_FDS): Likewise.
4483         (AARCH64_FL_TCR2): Likewise.
4484
4485 2024-02-07  Richard Biener  <rguenther@suse.de>
4486
4487         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
4488         Only check whether reads are in-bound in places that are not safe.
4489         Fix dependence check.  Add missing newline.  Clarify comments.
4490
4491 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
4492
4493         PR tree-optimization/113750
4494         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
4495         for single predecessor when doing early break vect.
4496         * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
4497         after labels.
4498
4499 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
4500
4501         PR tree-optimization/113731
4502         * gimple-iterator.cc (gsi_move_before): Take new parameter for update
4503         method.
4504         * gimple-iterator.h (gsi_move_before): Default new param to
4505         GSI_SAME_STMT.
4506         * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
4507         GSI_NEW_STMT.
4508
4509 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
4510
4511         PR tree-optimization/113756
4512         * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
4513         use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
4514         of lh_bits value and mask.
4515
4516 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
4517
4518         PR tree-optimization/113753
4519         * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
4520         UNSIGNED rather than SIGNED.  If high or needs_overflow and prec is
4521         not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
4522         so that they start with r[half_blocks_needed] lowest bit.  Fix up
4523         computation of top mask for SIGNED.
4524
4525 2024-02-07  Pan Li  <pan2.li@intel.com>
4526
4527         PR target/113766
4528         * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
4529         the signature of func.
4530         * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
4531         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
4532         overloaded func with empty args error.
4533
4534 2024-02-06  H.J. Lu  <hjl.tools@gmail.com>
4535
4536         PR target/113689
4537         * config/i386/i386.cc (x86_64_select_profile_regnum): Return
4538         R10_REG after sorry.
4539
4540 2024-02-06  Andrew Carlotti  <andrew.carlotti@arm.com>
4541
4542         * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
4543         Move before new caller, and add ".default" suffix.
4544         (get_suffixed_assembler_name): New.
4545         (make_resolver_func): Use get_suffixed_assembler_name.
4546         (aarch64_generate_version_dispatcher_body): Redo name mangling.
4547
4548 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
4549
4550         PR target/113763
4551         * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
4552         element from std::pair<unsigned int, char> to an unnamed struct.
4553         Adjust uses of tile range variable.
4554
4555 2024-02-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4556
4557         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
4558         (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
4559
4560 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
4561
4562         PR sanitizer/110676
4563         * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
4564         reset maxlen to sizetype maximum.
4565
4566 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
4567
4568         PR tree-optimization/113736
4569         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
4570         var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
4571
4572 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
4573
4574         PR tree-optimization/113759
4575         * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
4576         or from_unsignedN differs from properties of typeN, update typeN
4577         to build_nonstandard_integer_type.  If TREE_TYPE (rhsN) is not
4578         uselessly convertible to typeN, convert it using fold_convert or
4579         build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
4580         (convert_plusminus_to_widen): Likewise.
4581
4582 2024-02-06  Tejas Belagod  <tejas.belagod@arm.com>
4583
4584         PR target/112577
4585         * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
4586         vector structure modes correctly.
4587
4588 2024-02-05  Christoph Müllner  <christoph.muellner@vrull.eu>
4589
4590         * config/riscv/thead.cc (th_print_operand_address): Fix compiler
4591         warning.
4592
4593 2024-02-05  H.J. Lu  <hjl.tools@gmail.com>
4594
4595         PR target/113689
4596         * config/i386/i386.cc (x86_64_select_profile_regnum): New.
4597         (x86_function_profiler): Call x86_64_select_profile_regnum to
4598         get a scratch register for large model profiling.
4599
4600 2024-02-05  Richard Ball  <richard.ball@arm.com>
4601
4602         * config/arm/arm.cc (arm_output_mi_thunk): Emit
4603         insn for bti_c when bti is enabled.
4604
4605 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
4606
4607         * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
4608         neg.
4609
4610 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
4611
4612         * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
4613         (neg<mode>2): Change the mode iterator from MSA to IMSA because
4614         in FP arithmetic we cannot use (0 - x) for -x.
4615         (neg<mode>2): New define_insn to implement FP vector negation,
4616         using a bnegi instruction to negate the sign bit.
4617
4618 2024-02-05  Richard Biener  <rguenther@suse.de>
4619
4620         PR tree-optimization/113707
4621         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
4622         checking the avail set treat out-of-region defines as
4623         available.
4624
4625 2024-02-05  Richard Biener  <rguenther@suse.de>
4626
4627         * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
4628         the default mode when building a pointer.
4629
4630 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
4631
4632         PR tree-optimization/113737
4633         * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
4634         has just a single label, remove it and make single successor edge
4635         EDGE_FALLTHRU.
4636
4637 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
4638
4639         PR target/113059
4640         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
4641         Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
4642         df_analyze call.
4643
4644 2024-02-05  Richard Biener  <rguenther@suse.de>
4645
4646         PR target/113255
4647         * config/i386/i386-expand.cc
4648         (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
4649         Use a new pseudo for the skipped number of bytes.
4650
4651 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
4652
4653         * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
4654         * doc/invoke.texi (RISC-V Options): Add sifive-p450,
4655         sifive-p670.
4656
4657 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
4658
4659         * config/riscv/riscv.md: Include sifive-p400.md.
4660         * config/riscv/sifive-p400.md: New file.
4661         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
4662         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
4663         Add sifive_p400.
4664         * config/riscv/riscv.cc (sifive_p400_tune_info): New.
4665         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
4666         * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
4667
4668 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
4669
4670         * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
4671         Add missing ":SI" to the match_operator.
4672
4673 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
4674
4675         * config/xtensa/xtensa.md (SHI): New mode iterator.
4676         (2 split patterns related to constsynth):
4677         Change to also accept HImode operands.
4678
4679 2024-02-04  Jeff Law  <jlaw@ventanamicro.com>
4680
4681         * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
4682         similarly.
4683
4684 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
4685
4686         * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
4687         incorrect expand.
4688         * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
4689         (elmsgnbit): Likewise.
4690         (neg<mode:FVEC>2): New define_insn.
4691         * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
4692         are now instantiated in simd.md.
4693
4694 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
4695
4696         * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
4697         use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
4698         MAX_MACHINE_MODE.
4699
4700 2024-02-04  Li Wei  <liwei@loongson.cn>
4701
4702         * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
4703         (loongarch_expand_vselect_vconcat): Ditto.
4704         (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
4705         all 128-bit constant permutation situations.
4706         (loongarch_expand_lsx_shuffle): Adjust and rename function name.
4707         (loongarch_is_imm_set_shuffle): Renamed function name.
4708         (loongarch_expand_vec_perm_even_odd): Function forward declaration.
4709         (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
4710         extract-even and extract-odd permutations.
4711         (loongarch_is_odd_extraction): Delete.
4712         (loongarch_is_even_extraction): Ditto.
4713         (loongarch_expand_vec_perm_const): Adjust.
4714
4715 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
4716
4717         PR middle-end/113722
4718         * wide-int.cc (wi::bswap_large): Rename third argument from
4719         len to xlen and adjust use in safe_uhwi.  Add len variable, set
4720         it to BLOCKS_NEEDED (precision) and use it for clearing of val
4721         and as canonize argument.  Clear val using memset instead of
4722         a loop.
4723
4724 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
4725
4726         * ggc-common.cc (gt_pch_save): Allow addr to be equal to
4727         mmi.preferred_base + mmi.size - sizeof (void *).
4728
4729 2024-02-03  Xi Ruoyao  <xry111@xry111.site>
4730
4731         * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
4732         * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
4733         the ODR-violating locale declaration.
4734
4735 2024-02-02  Tamar Christina  <tamar.christina@arm.com>
4736
4737         PR tree-optimization/113588
4738         PR tree-optimization/113467
4739         * tree-vect-data-refs.cc
4740         (vect_analyze_data_ref_dependence):  Choose correct dest and fix checks.
4741         (vect_analyze_early_break_dependences): Update comments.
4742
4743 2024-02-02  John David Anglin  <danglin@gcc.gnu.org>
4744
4745         PR target/59778
4746         * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
4747         and PA_BUILTIN_SET_FPSR builtins.
4748         * (pa_builtins_icode): Declare.
4749         * (def_builtin, pa_fpu_init_builtins): New.
4750         * (pa_init_builtins): Initialize FPU builtins.
4751         * (pa_builtin_decl, pa_expand_builtin_1): New.
4752         * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
4753         PA_BUILTIN_SET_FPSR builtins.
4754         * (pa_atomic_assign_expand_fenv): New.
4755         * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
4756         UNSPECV constants.
4757         (get_fpsr, put_fpsr): New expanders.
4758         (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
4759         insn patterns.
4760
4761 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4762
4763         PR target/113697
4764         * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
4765
4766 2024-02-02  Jonathan Wakely  <jwakely@redhat.com>
4767
4768         * doc/extend.texi (Common Type Attributes): Fix typo in
4769         description of hardbool.
4770
4771 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
4772
4773         PR tree-optimization/113692
4774         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
4775         from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
4776         final_cast_p.
4777
4778 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
4779
4780         PR middle-end/113699
4781         * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
4782         uninitialized large/huge _BitInt SSA_NAME inputs.
4783
4784 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
4785
4786         PR middle-end/113705
4787         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
4788         around wi::to_wide in order to compare value in prec precision.
4789
4790 2024-02-02  Lehua Ding  <lehua.ding@rivai.ai>
4791
4792         Revert:
4793         2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4794
4795         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
4796
4797 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4798
4799         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
4800
4801 2024-02-02  Pan Li  <pan2.li@intel.com>
4802
4803         * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
4804         (riscv_pass_by_reference): Ditto.
4805         (riscv_fntype_abi): Ditto.
4806
4807 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4808
4809         * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
4810         (pre_vsetvl::cleaup): Remove vsetvl_pre.
4811         (pre_vsetvl::remove_vsetvl_pre_insns): New function.
4812
4813 2024-02-02  Jiahao Xu  <xujiahao@loongson.cn>
4814
4815         * config/loongarch/larchintrin.h
4816         (__frecipe_s): Update function return type.
4817         (__frecipe_d): Ditto.
4818         (__frsqrte_s): Ditto.
4819         (__frsqrte_d): Ditto.
4820
4821 2024-02-02  Li Wei  <liwei@loongson.cn>
4822
4823         * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
4824         (loongarch_vector_costs::add_stmt_cost): Adjust.
4825
4826 2024-02-02  Xi Ruoyao  <xry111@xry111.site>
4827
4828         * config/loongarch/loongarch.md (unspec): Add
4829         UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
4830         (la_pcrel64_two_parts): New define_insn.
4831         * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
4832         typo in the comment.
4833         (loongarch_call_tls_get_addr): If -mcmodel=extreme
4834         -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
4835         addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
4836         note to allow CSE addressing __tls_get_addr.
4837         (loongarch_legitimize_tls_address): If -mcmodel=extreme
4838         -mexplicit-relocs={always,auto}, address TLS IE symbols with
4839         la_pcrel64_two_parts.
4840         (loongarch_split_symbol): If -mcmodel=extreme
4841         -mexplicit-relocs={always,auto}, address symbols with
4842         la_pcrel64_two_parts.
4843         (loongarch_output_mi_thunk): Clean up unreachable code.  If
4844         -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
4845         thunks with la_pcrel64_two_parts.
4846
4847 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
4848
4849         * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
4850         Add support for call36.
4851
4852 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
4853
4854         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4855         When the code model of the symbol is extreme and -mexplicit-relocs=auto,
4856         the macro instruction loading symbol address is not applicable.
4857         (loongarch_call_tls_get_addr): Adjust code.
4858         (loongarch_legitimize_tls_address): Likewise.
4859
4860 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
4861
4862         * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
4863         Add function declaration.
4864         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4865         For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
4866         is not allowed
4867         (loongarch_load_tls): Added macro support in extreme mode.
4868         (loongarch_call_tls_get_addr): Likewise.
4869         (loongarch_legitimize_tls_address): Likewise.
4870         (loongarch_force_address): Likewise.
4871         (loongarch_legitimize_move): Likewise.
4872         (loongarch_output_mi_thunk): Likewise.
4873         (loongarch_option_override_internal): Remove the code that detects
4874         explicit relocs status.
4875         (loongarch_handle_model_attribute): Likewise.
4876         * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
4877         * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
4878         (symbolic_off64_or_reg_operand): Likewise.
4879
4880 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
4881
4882         * config/loongarch/loongarch.cc (loongarch_load_tls):
4883         Load all types of tls symbols through one function.
4884         (loongarch_got_load_tls_gd): Delete.
4885         (loongarch_got_load_tls_ld): Delete.
4886         (loongarch_got_load_tls_ie): Delete.
4887         (loongarch_got_load_tls_le): Delete.
4888         (loongarch_call_tls_get_addr): Modify the called function name.
4889         (loongarch_legitimize_tls_address): Likewise.
4890         * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
4891         (@load_tls<mode>): New template.
4892         (@got_load_tls_ld<mode>): Delete.
4893         (@got_load_tls_le<mode>): Delete.
4894         (@got_load_tls_ie<mode>): Delete.
4895
4896 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
4897
4898         * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
4899         (loongarch_legitimize_address): Add logical transformation code.
4900
4901 2024-02-01  Marek Polacek  <polacek@redhat.com>
4902
4903         * doc/invoke.texi: Update -Wdangling-reference documentation.
4904
4905 2024-02-01  Uros Bizjak  <ubizjak@gmail.com>
4906
4907         PR target/113701
4908         * config/i386/i386.md (*cmp<dwi>_doubleword):
4909         Do not force SUBREG pieces to pseudos.
4910
4911 2024-02-01  John David Anglin  <danglin@gcc.gnu.org>
4912
4913         * config/pa/pa.md (atomic_storedi_1): Fix bug in
4914         alternative 1.
4915
4916 2024-02-01  Georg-Johann Lay  <avr@gjlay.de>
4917
4918         * config/avr/avr.cc: Tabify.
4919
4920 2024-02-01  Richard Ball  <richard.ball@arm.com>
4921
4922         PR tree-optimization/111268
4923         * tree-vect-slp.cc (vectorizable_slp_permutation_1):
4924         Add variable-length check for vector input arguments
4925         to a function.
4926
4927 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
4928
4929         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
4930         hard-code number of SGPR/VGPR/AVGPR registers.
4931         * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
4932         SGPR/VGPR/AVGPR registers.
4933
4934 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
4935
4936         * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
4937         attribute, and include sifive-p600.md.
4938         * config/riscv/generic-ooo.md: Update type attribute.
4939         * config/riscv/generic.md: Update type attribute.
4940         * config/riscv/sifive-7.md: Update type attribute.
4941         * config/riscv/sifive-p600.md: New file.
4942         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
4943         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
4944         Add sifive_p600.
4945         * config/riscv/riscv.cc (sifive_p600_tune_info): New.
4946         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
4947         * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
4948
4949 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
4950
4951         * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
4952         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
4953         * config/riscv/riscv.opt: New macro for 7 new unprivileged
4954         extensions.
4955         * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
4956         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
4957
4958 2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
4959
4960         * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
4961         -static-libasan.  Add missing whitespace.
4962
4963 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
4964
4965         * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
4966         (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
4967         Don't 'define_constants'.
4968
4969 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
4970
4971         * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
4972
4973 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
4974
4975         * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
4976         [TARGET_RDNA3]: Adjust.
4977
4978 2024-02-01  Richard Biener  <rguenther@suse.de>
4979
4980         PR tree-optimization/113693
4981         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
4982         data when available.
4983
4984 2024-02-01  Jakub Jelinek  <jakub@redhat.com>
4985             Jason Merrill  <jason@redhat.com>
4986
4987         PR c++/113531
4988         * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
4989         on variables which were promoted to TREE_STATIC.
4990
4991 2024-02-01  Roger Sayle  <roger@nextmovesoftware.com>
4992             Richard Biener  <rguenther@suse.de>
4993
4994         PR target/113560
4995         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
4996         information via tree_non_zero_bits to check if this operand
4997         is suitably extended for a widening (or highpart) multiplication.
4998         (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
4999         isn't already of the claimed type.
5000
5001 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5002
5003         Revert:
5004         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5005
5006         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
5007         (generic_ooo_branch): ditto
5008         * config/riscv/generic.md (generic_sfb_alu): ditto
5009         (generic_fmul_half): ditto
5010         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
5011         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
5012         (sifive_7_popcount): ditto
5013         * config/riscv/vector.md: change rdfrm to fmove
5014         * config/riscv/zc.md: change pushpop to load/store
5015
5016 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5017
5018         Revert:
5019         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5020                     Robin Dapp  <rdapp.gcc@gmail.com>
5021
5022         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
5023         (generic_ooo_vec_load): ditto
5024         (generic_ooo_vec_store): ditto
5025         (generic_ooo_vec_loadstore_seg): ditto
5026         (generic_ooo_vec_alu): ditto
5027         (generic_ooo_vec_fcmp): ditto
5028         (generic_ooo_vec_imul): ditto
5029         (generic_ooo_vec_fadd): ditto
5030         (generic_ooo_vec_fmul): ditto
5031         (generic_ooo_crypto): ditto
5032         (generic_ooo_perm): ditto
5033         (generic_ooo_vec_reduction): ditto
5034         (generic_ooo_vec_ordered_reduction): ditto
5035         (generic_ooo_vec_idiv): ditto
5036         (generic_ooo_vec_float_divsqrt): ditto
5037         (generic_ooo_vec_mask): ditto
5038         (generic_ooo_vec_vesetvl): ditto
5039         (generic_ooo_vec_setrm): ditto
5040         (generic_ooo_vec_readlen): ditto
5041         * config/riscv/riscv.md: include generic-vector-ooo
5042         * config/riscv/generic-vector-ooo.md: New file. to here
5043
5044 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5045
5046         Revert:
5047         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5048
5049         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
5050
5051 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5052
5053         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
5054
5055 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5056             Robin Dapp  <rdapp.gcc@gmail.com>
5057
5058         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
5059         (generic_ooo_vec_load): ditto
5060         (generic_ooo_vec_store): ditto
5061         (generic_ooo_vec_loadstore_seg): ditto
5062         (generic_ooo_vec_alu): ditto
5063         (generic_ooo_vec_fcmp): ditto
5064         (generic_ooo_vec_imul): ditto
5065         (generic_ooo_vec_fadd): ditto
5066         (generic_ooo_vec_fmul): ditto
5067         (generic_ooo_crypto): ditto
5068         (generic_ooo_perm): ditto
5069         (generic_ooo_vec_reduction): ditto
5070         (generic_ooo_vec_ordered_reduction): ditto
5071         (generic_ooo_vec_idiv): ditto
5072         (generic_ooo_vec_float_divsqrt): ditto
5073         (generic_ooo_vec_mask): ditto
5074         (generic_ooo_vec_vesetvl): ditto
5075         (generic_ooo_vec_setrm): ditto
5076         (generic_ooo_vec_readlen): ditto
5077         * config/riscv/riscv.md: include generic-vector-ooo
5078         * config/riscv/generic-vector-ooo.md: New file. to here
5079
5080 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
5081
5082         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
5083         (generic_ooo_branch): ditto
5084         * config/riscv/generic.md (generic_sfb_alu): ditto
5085         (generic_fmul_half): ditto
5086         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
5087         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
5088         (sifive_7_popcount): ditto
5089         * config/riscv/vector.md: change rdfrm to fmove
5090         * config/riscv/zc.md: change pushpop to load/store
5091
5092 2024-02-01  Andrew Pinski  <quic_apinski@quicinc.com>
5093
5094         PR target/113657
5095         * config/aarch64/aarch64-simd.md (split for movv8di):
5096         For strict aligned mode, use DImode instead of TImode.
5097
5098 2024-01-31  Robin Dapp  <rdapp@ventanamicro.com>
5099
5100         PR middle-end/113607
5101         * match.pd: Make sure else values match when folding a
5102         vec_cond into a conditional operation.
5103
5104 2024-01-31  Marek Polacek  <polacek@redhat.com>
5105
5106         * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
5107
5108 2024-01-31  Tamar Christina  <tamar.christina@arm.com>
5109             Matthew Malcomson  <matthew.malcomson@arm.com>
5110
5111         PR sanitizer/112644
5112         * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
5113         memcmp.
5114         * builtins.cc (expand_builtin): Include HWASAN when checking for
5115         builtin inlining.
5116
5117 2024-01-31  Richard Biener  <rguenther@suse.de>
5118
5119         PR middle-end/110176
5120         * match.pd (zext (bool) <= (int) 4294967295u): Make sure
5121         to match INTEGER_CST only without outstanding conversion.
5122
5123 2024-01-31  Alex Coplan  <alex.coplan@arm.com>
5124
5125         PR target/111677
5126         * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
5127         V16QImode for the full 16-byte FPR saves in the vector PCS case.
5128
5129 2024-01-31  Richard Biener  <rguenther@suse.de>
5130
5131         PR tree-optimization/111444
5132         * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
5133         vn_reference_lookup_2 when optimistically skipping may-defs.
5134
5135 2024-01-31  Richard Biener  <rguenther@suse.de>
5136
5137         PR tree-optimization/113630
5138         * tree-ssa-pre.cc (compute_avail): Avoid registering a
5139         reference with a representation with not matching base
5140         access size.
5141
5142 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
5143
5144         PR rtl-optimization/113656
5145         * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
5146         <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
5147
5148 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
5149
5150         PR debug/113637
5151         * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
5152         with BLKmode are larger than DWARF2_ADDR_SIZE.
5153
5154 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
5155
5156         PR tree-optimization/113639
5157         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5158         For VIEW_CONVERT_EXPR set rhs1 to its operand.
5159
5160 2024-01-31  Richard Biener  <rguenther@suse.de>
5161
5162         PR tree-optimization/113670
5163         * tree-vect-data-refs.cc (vect_check_gather_scatter):
5164         Make sure we can take the address of the reference base.
5165
5166 2024-01-31  Georg-Johann Lay  <avr@gjlay.de>
5167
5168         * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
5169         ATA5835, ATtiny64AUTO, ATA5700M322.
5170         * doc/avr-mmcu.texi: Rebuild.
5171
5172 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
5173
5174         PR debug/113394
5175         * ipa-strub.cc (build_ref_type_for): Drop nonaliased.  Adjust
5176         caller.
5177
5178 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
5179
5180         PR middle-end/112917
5181         PR middle-end/113100
5182         * builtins.cc (expand_builtin_stack_address): Use
5183         STACK_ADDRESS_OFFSET.
5184         * doc/extend.texi (__builtin_stack_address): Adjust.
5185         * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
5186         * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
5187         * doc/tm.texi: Rebuilt.
5188
5189 2024-01-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5190
5191         PR target/113495
5192         * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
5193         (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
5194         (pre_vsetvl::compute_transparent): New function.
5195         (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
5196
5197 2024-01-30  Fangrui Song  <maskray@google.com>
5198
5199         PR target/105576
5200         * config/i386/constraints.md: Define constraint "Ws".
5201         * doc/md.texi: Document it.
5202
5203 2024-01-30  Marek Polacek  <polacek@redhat.com>
5204
5205         PR c++/110358
5206         PR c++/109640
5207         * doc/invoke.texi: Update -Wdangling-reference description.
5208
5209 2024-01-30  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
5210
5211         * config/xtensa/constraints.md (R, T, U):
5212         Change define_constraint to define_memory_constraint.
5213         * config/xtensa/predicates.md (move_operand): Don't check that a
5214         constant pool operand size is a multiple of UNITS_PER_WORD.
5215         * config/xtensa/xtensa.cc
5216         (xtensa_lra_p, TARGET_LRA_P): Remove.
5217         (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
5218         clause as it can no longer be true.
5219         (fixup_subreg_mem): Drop function.
5220         (xtensa_output_integer_literal_parts): Consider 16-bit wide
5221         constants.
5222         (xtensa_legitimate_constant_p): Add short-circuit path for
5223         integer load instructions. Don't check that mode size is
5224         at least UNITS_PER_WORD.
5225         * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
5226         rather reload_in_progress and reload_completed.
5227         (doloop_end): Drop operand 2.
5228         (movhi_internal): Add alternative loading constant from a
5229         literal pool.
5230         (define_split for DI register_operand): Don't limit to
5231         !TARGET_AUTO_LITPOOLS.
5232         * config/xtensa/xtensa.opt (mlra): Change to no effect.
5233
5234 2024-01-30  Pan Li  <pan2.li@intel.com>
5235
5236         * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
5237         calculate the gpr count required by vls mode.
5238         (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
5239         (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
5240         for vls mode.
5241         (riscv_get_arg_info): Add vls mode handling.
5242         (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
5243
5244 2024-01-30  Richard Biener  <rguenther@suse.de>
5245
5246         PR tree-optimization/113659
5247         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5248         Handle main exit without virtual use.
5249
5250 2024-01-30  Christoph Müllner  <christoph.muellner@vrull.eu>
5251
5252         * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
5253
5254 2024-01-30  Iain Sandoe  <iain@sandoe.co.uk>
5255
5256         PR libgcc/113403
5257         * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
5258         (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
5259         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
5260         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
5261         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
5262         * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
5263
5264 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
5265
5266         PR target/113623
5267         * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
5268         Mark all registers that occur in addresses as needing a GPR.
5269
5270 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
5271
5272         PR target/113636
5273         * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
5274         the containing insn as an extra parameter.  Reset debug instructions
5275         if they reference a register that is no longer used by real insns.
5276         (early_ra::apply_allocation): Update calls accordingly.
5277
5278 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
5279
5280         PR tree-optimization/113603
5281         * tree-ssa-strlen.cc (strlen_pass::handle_store): After
5282         count_nonzero_bytes call refetch si using get_strinfo in case it
5283         has been unshared in the meantime.
5284
5285 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
5286
5287         PR middle-end/101195
5288         * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
5289         fit into unsigned HOST_WIDE_INT, return constm1_rtx.
5290
5291 2024-01-30  Jin Ma  <jinma@linux.alibaba.com>
5292
5293         * config/riscv/thead.cc (th_print_operand_address): Change %ld
5294         to %lld.
5295
5296 2024-01-29  Manos Anagnostakis  <manos.anagnostakis@vrull.eu>
5297             Manolis Tsamis  <manolis.tsamis@vrull.eu>
5298             Philipp Tomsich  <philipp.tomsich@vrull.eu>
5299
5300         * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
5301         * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
5302         Likewise.
5303         * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
5304         Call on framework moved later.
5305
5306 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
5307
5308         * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
5309         instruction in naked function epilogues.
5310
5311 2024-01-29  YunQiang Su  <syq@gcc.gnu.org>
5312
5313         PR target/113655
5314         * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
5315         gcc_cv_as_mips_explicit_relocs.
5316         * configure: Regnerated.
5317
5318 2024-01-29  Matthieu Longo  <matthieu.longo@arm.com>
5319
5320         PR target/108933
5321         * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
5322         Correct generated RTL.
5323         (arm_rev16si2_alt1): Correctly handle conditional execution.
5324         (arm_rev16si2_alt2): Likewise.
5325
5326 2024-01-29  Richard Biener  <rguenther@suse.de>
5327
5328         PR middle-end/113622
5329         * expr.cc (expand_assignment): Spill hard registers if
5330         we index them with a variable offset.
5331
5332 2024-01-29  Richard Biener  <rguenther@suse.de>
5333
5334         PR middle-end/113622
5335         * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
5336         Also allow DECL_HARD_REGISTER variables.
5337
5338 2024-01-29  Alex Coplan  <alex.coplan@arm.com>
5339
5340         PR target/113616
5341         * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
5342         Use iterate_safely when iterating over debug uses.
5343         (fixup_debug_uses): Likewise.
5344         (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
5345         over nondebug insns instead of manually maintaining the next insn.
5346         * iterator-utils.h (class safe_iterator): New.
5347         (iterate_safely): New.
5348
5349 2024-01-29  H.J. Lu  <hjl.tools@gmail.com>
5350
5351         PR target/38534
5352         * config/i386/i386-options.cc (ix86_set_func_type): Save
5353         callee-saved registers in noreturn functions for -O0/-Og.
5354
5355 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
5356
5357         PR target/113615
5358         * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
5359         define for !TARGET_RDNA2_PLUS.
5360
5361 2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>
5362
5363         PR target/113281
5364         * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
5365         workaround for right shifts.
5366         (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
5367         (vect_determine_precisions_from_range): Be more selective about
5368         which codes can be narrowed based on their input and output ranges.
5369         For shifts, require at least one more bit of precision than the
5370         maximum shift amount.
5371
5372 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
5373
5374         * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
5375
5376 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
5377
5378         * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
5379         but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
5380         LLVM 13.0.1+.
5381
5382 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
5383
5384         PR other/111966
5385         * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
5386         (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
5387         (SET_SRAM_ECC_UNSET): ... this.
5388         (copy_early_debug_info): Remove gfx900 special case, now handled as
5389         part of the generic handling.
5390         (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
5391
5392 2024-01-29  Jakub Jelinek  <jakub@redhat.com>
5393
5394         PR tree-optimization/110603
5395         * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
5396         setting of pdata->maxlen to vr.upper_bound (which is unconditionally
5397         overwritten anyway).  Avoid creating invalid range with minlen
5398         larger than maxlen.  Formatting fix.
5399
5400 2024-01-29  Richard Biener  <rguenther@suse.de>
5401
5402         PR debug/103047
5403         * tree-inline.cc (initialize_inlined_parameters): Reverse
5404         the decl chain of inlined parameters.
5405
5406 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
5407
5408         * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
5409         alignment of CFString constants by setting DECL_USER_ALIGN.
5410
5411 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
5412             Jakub Jelinek   <jakub@redhat.com>
5413
5414         PR libgcc/113402
5415         * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
5416         and BUILT_IN_GCC_NESTED_PTR_DELETED.
5417         * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
5418         BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
5419         rename the library fallbacks to __gcc_nested_func_ptr_created and
5420         __gcc_nested_func_ptr_deleted.
5421         * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
5422         and __gcc_nested_func_ptr_deleted.
5423         * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
5424         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
5425         * tree.cc (build_common_builtin_nodes): Build the
5426         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
5427         builtins only for non-explicit.
5428
5429 2024-01-28  YunQiang Su  <syq@gcc.gnu.org>
5430
5431         * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
5432
5433 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
5434
5435         PR target/38534
5436         * config/i386/i386-options.cc (ix86_set_func_type): Don't
5437         save and restore callee saved registers for a noreturn function
5438         with nothrow or compiled with -fno-exceptions.
5439
5440 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
5441
5442         PR target/103503
5443         PR target/113312
5444         * config/i386/i386-expand.cc (ix86_expand_call): Replace
5445         no_caller_saved_registers check with call_saved_registers check.
5446         Clobber all registers that are not used by the callee with
5447         no_callee_saved_registers attribute.
5448         * config/i386/i386-options.cc (ix86_set_func_type): Set
5449         call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
5450         noreturn function.  Disallow no_callee_saved_registers with
5451         interrupt or no_caller_saved_registers attributes together.
5452         (ix86_set_current_function): Replace no_caller_saved_registers
5453         check with call_saved_registers check.
5454         (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
5455         (ix86_handle_call_saved_registers_attribute): This.
5456         (ix86_gnu_attributes): Add
5457         ix86_handle_call_saved_registers_attribute.
5458         * config/i386/i386.cc (ix86_conditional_register_usage): Replace
5459         no_caller_saved_registers check with call_saved_registers check.
5460         (ix86_function_ok_for_sibcall): Don't allow callee with
5461         no_callee_saved_registers attribute when the calling function
5462         has callee-saved registers.
5463         (ix86_comp_type_attributes): Also check
5464         no_callee_saved_registers.
5465         (ix86_epilogue_uses): Replace no_caller_saved_registers check
5466         with call_saved_registers check.
5467         (ix86_hard_regno_scratch_ok): Likewise.
5468         (ix86_save_reg): Replace no_caller_saved_registers check with
5469         call_saved_registers check.  Don't save any registers for
5470         TYPE_NO_CALLEE_SAVED_REGISTERS.  Save all registers with
5471         TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
5472         no_callee_saved_registers attribute is called.
5473         (find_drap_reg): Replace no_caller_saved_registers check with
5474         call_saved_registers check.
5475         * config/i386/i386.h (call_saved_registers_type): New enum.
5476         (machine_function): Replace no_caller_saved_registers with
5477         call_saved_registers.
5478         * doc/extend.texi: Document no_callee_saved_registers attribute.
5479
5480 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
5481
5482         PR tree-optimization/113614
5483         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
5484         widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
5485         TRUNC_MOD_EXPR or FLOAT_EXPR uses.
5486
5487 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
5488
5489         PR tree-optimization/113568
5490         * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
5491         For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
5492         in the widening extension checks.
5493
5494 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
5495
5496         * gimple-lower-bitint.cc (gimple_lower_bitint): For
5497         TDF_DETAILS dump mapping of SSA_NAMEs to decls.
5498
5499 2024-01-26  Hans-Peter Nilsson  <hp@axis.com>
5500
5501         * cgraphunit.cc (process_function_and_variable_attributes): Tweak
5502         the warning for an attribute-always_inline without inline declaration.
5503
5504 2024-01-26  Robin Dapp  <rdapp@ventanamicro.com>
5505
5506         PR other/113575
5507         * genopinit.cc (main): Split init_all_optabs into functions
5508         of 1000 patterns each.
5509
5510 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
5511
5512         * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
5513         TM_MULTILIB_CONFIG.
5514         * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
5515         * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
5516         -march/-mtune.
5517
5518 2024-01-26  Andrew Stubbs  <ams@baylibre.com>
5519
5520         * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
5521         * config/gcn/gcn-valu.md (all_convert): New iterator.
5522         (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
5523         define_expand, and rename the old one to ...
5524         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
5525         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
5526         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
5527         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
5528         * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
5529         (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
5530         * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
5531         (<u>mulqihi3_scalar): Likewise.
5532
5533 2024-01-26  Richard Biener  <rguenther@suse.de>
5534
5535         PR tree-optimization/113602
5536         * tree-data-ref.cc (dr_analyze_innermost): Fail when
5537         the base object isn't addressable.
5538
5539 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
5540
5541         * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
5542         "--amdhsa-code-object-version=" argument.
5543         (ASM_SPEC): Use it; replace previous version of it.
5544
5545 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5546
5547         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
5548         (pre_vsetvl::emit_vsetvl): Ditto.
5549
5550 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
5551
5552         * config/loongarch/lasx.md (vec_extract<mode>_0):
5553         New define_insn_and_split patten.
5554
5555 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
5556
5557         * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
5558
5559 2024-01-26  Li Wei  <liwei@loongson.cn>
5560
5561         * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
5562
5563 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5564
5565         PR target/113469
5566         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
5567
5568 2024-01-26  Andrew Pinski  <quic_apinski@quicinc.com>
5569
5570         PR target/100212
5571         * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
5572         undefined shift after the call to exact_log2.
5573
5574 2024-01-25  Andrew Pinski  <quic_apinski@quicinc.com>
5575
5576         PR target/100204
5577         * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
5578         before taking the negative of it.
5579
5580 2024-01-25  Vladimir N. Makarov  <vmakarov@redhat.com>
5581
5582         PR target/113526
5583         * lra-constraints.cc (curr_insn_transform): Change class even for
5584         spilled pseudo successfully matched with with NO_REGS.
5585
5586 2024-01-25  Georg-Johann Lay  <avr@gjlay.de>
5587
5588         PR target/113601
5589         * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
5590
5591 2024-01-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
5592
5593         PR target/112987
5594         * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
5595         (aarch64_expand_epilogue): Use the new function.
5596         (aarch64_split_compare_and_swap): Likewise.
5597         (aarch64_split_atomic_op): Likewise.
5598
5599 2024-01-25  Robin Dapp  <rdapp.gcc@gmail.com>
5600
5601         PR middle-end/112971
5602         * fold-const.cc (simplify_const_binop): New function for binop
5603         simplification of two constant vectors when element-wise
5604         handling is not necessary.
5605         (const_binop): Call new function.
5606
5607 2024-01-25  Mary Bennett  <mary.bennett@embecosm.com>
5608
5609         * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
5610         * config/riscv/constraints.md: Likewise.
5611         * config/riscv/corev.def: Likewise.
5612         * config/riscv/corev.md: Likewise.
5613         * config/riscv/predicates.md: Likewise.
5614         * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
5615         * config/riscv/riscv-ftypes.def: Likewise.
5616         * config/riscv/riscv.opt: Likewise.
5617         * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
5618         * doc/extend.texi: Add XCVbitmanip builtin documentation.
5619         * doc/sourcebuild.texi: Likewise.
5620
5621 2024-01-25  Tobias Burnus  <tburnus@baylibre.com>
5622
5623         * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
5624
5625 2024-01-25  Yanzhang Wang  <yanzhang.wang@intel.com>
5626
5627         PR target/113538
5628         * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
5629         (riscv_fntype_abi): Ditto.
5630         * config/riscv/riscv.opt: Ditto.
5631
5632 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
5633
5634         PR middle-end/113574
5635         * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
5636         count against TYPE_PRECISION rather than TYPE_SIZE.
5637
5638 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
5639
5640         PR target/113572
5641         * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
5642         Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
5643
5644 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
5645
5646         PR target/113550
5647         * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
5648         whether each split instruction is a load that clobbers the source
5649         address.  Emit that instruction last if so.
5650
5651 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
5652
5653         PR target/113485
5654         * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
5655         pattern.
5656         (<optab><Vnarrowq><mode>2): Use it instead of generating a
5657         paradoxical subreg for the input.
5658
5659 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5660
5661         * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
5662         (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
5663         predecessors dump information.
5664
5665 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5666
5667         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
5668         redundant full available computation.
5669         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
5670
5671 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
5672
5673         * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
5674         * doc/rtl.texi (CONST_VECTOR): Likewise.
5675
5676 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5677
5678         * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
5679         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
5680         (pass_vsetvl::execute): Ditto.
5681         * config/riscv/riscv.opt: Ditto.
5682
5683 2024-01-25  Jiahao Xu  <xujiahao@loongson.cn>
5684
5685         * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
5686         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
5687
5688 2024-01-25  Richard Biener  <rguenther@suse.de>
5689
5690         PR tree-optimization/113576
5691         * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
5692         exits with may_be_zero niters when its the last one.
5693
5694 2024-01-25  Lulu Cheng  <chenglulu@loongson.cn>
5695
5696         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
5697         For symbols of type tls, non-zero Offset is not generated.
5698
5699 2024-01-25  Haochen Gui  <guihaoc@gcc.gnu.org>
5700
5701         * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
5702         P9 with m32 and mpowerpc64.
5703
5704 2024-01-25  liuhongt  <hongtao.liu@intel.com>
5705
5706         * config/i386/i386-options.cc (ix86_option_override_internal):
5707         Enable -mlam=u57 by default when compiled with
5708         -fsanitize=hwaddress.
5709
5710 2024-01-25  Palmer Dabbelt  <palmer@rivosinc.com>
5711
5712         * common/config/riscv/riscv-common.cc (riscv_implied_info):
5713         Remove {"ztso", "a"}.
5714
5715 2024-01-24  Martin Jambor  <mjambor@suse.cz>
5716
5717         PR ipa/108007
5718         PR ipa/112616
5719         * cgraph.h (cgraph_edge): Add a parameter to
5720         redirect_call_stmt_to_callee.
5721         * ipa-param-manipulation.h (ipa_param_adjustments): Add a
5722         parameter to modify_call.
5723         (ipa_release_ssas_in_hash): Declare.
5724         * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
5725         parameter killed_ssas, pass it to padjs->modify_call.
5726         * ipa-param-manipulation.cc (purge_all_uses): New function.
5727         (ipa_param_adjustments::modify_call): New parameter killed_ssas.
5728         Instead of substituting uses, invoke purge_all_uses.  If
5729         hash of killed SSAs has not been provided, create a temporary one
5730         and release SSAs that have been added to it.
5731         (compare_ssa_versions): New function.
5732         (ipa_release_ssas_in_hash): Likewise.
5733         * tree-inline.cc (redirect_all_calls): Create
5734         id->killed_new_ssa_names earlier, pass it to edge redirection,
5735         adjust a comment.
5736         (copy_body): Release SSAs in id->killed_new_ssa_names.
5737
5738 2024-01-24  Andrew Pinski  <quic_apinski@quicinc.com>
5739
5740         PR target/113486
5741         * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
5742         TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
5743
5744 2024-01-24  Monk Chiang  <monk.chiang@sifive.com>
5745
5746         PR target/113095
5747         * config/riscv/sfb.md: New splitters to rewrite single bit
5748         sign extension as the condition to SFB instructions.
5749
5750 2024-01-24  Jan Hubicka  <jh@suse.cz>
5751
5752         PR middle-end/88345
5753         * common.opt: (flimit-function-alignment): Reorder alphabeticaly
5754         (fmin-function-alignment): New parameter.
5755         * doc/invoke.texi: (-fmin-function-alignment): Document.
5756         (-falign-functions,-falign-loops,-falign-labels): Mention that
5757         aglinments are ignored in cold code.
5758         * varasm.cc (assemble_start_function): Handle min-function-alignment.
5759
5760 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
5761
5762         PR target/109636
5763         * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
5764         mulv2di3): Remove.
5765         * config/aarch64/iterators.md (VQDIV): Remove.
5766         (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
5767         SVE_I_SIMD_DI): New.
5768         (VPRED, sve_lane_con): Add V4SI and V2DI.
5769         * config/aarch64/aarch64-sve.md (<optab><mode>3,
5770         @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
5771         (mul<mode>3): New, split from <optab><mode>3.
5772         (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
5773         * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
5774         *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
5775         SVE_FULL_HSDI_SIMD_DI.
5776
5777 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
5778
5779         PR tree-optimization/113552
5780         * config/aarch64/aarch64.cc
5781         (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
5782
5783 2024-01-24  Martin Jambor  <mjambor@suse.cz>
5784
5785         PR ipa/113490
5786         * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
5787         count is equal or greater than the limit.  Use the limit from the
5788         callee.
5789
5790 2024-01-24  YunQiang Su  <syq@gcc.gnu.org>
5791
5792         * configure.ac: Detect the explicit relocs support for
5793         mips, and define C macro MIPS_EXPLICIT_RELOCS.
5794         * config.in: Regenerated.
5795         * configure: Regenerated.
5796         * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
5797         * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
5798         * config/mips/mips.cc(mips_set_compression_mode): Sorry if
5799         !TARGET_EXPLICIT_RELOCS instead of just set it.
5800         * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
5801         TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
5802         * config/mips/mips.opt: Introduce -mexplicit-relocs= option
5803         and define -m(no-)explicit-relocs as aliases.
5804
5805 2024-01-24  Alex Coplan  <alex.coplan@arm.com>
5806
5807         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
5808         to 1.
5809         (-mlate-ldp-fusion): Likewise.
5810
5811 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
5812
5813         * tree-vect-loop.cc (vect_get_vect_def,
5814         vect_create_epilog_for_reduction): Rename main_exit_p to
5815         last_val_reduc_p.
5816
5817 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
5818
5819         PR tree-optimization/113364
5820         * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
5821         early exits then we must reduce from the first offset for all of them.
5822
5823 2024-01-24  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5824
5825         PR target/113495
5826         * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
5827         (get_regno): Ditto.
5828         (get_bb_index): Ditto.
5829         (pre_vsetvl::compute_avl_def_data): Ditto.
5830         (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
5831         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
5832
5833 2024-01-23  Andrew Pinski  <quic_apinski@quicinc.com>
5834             Richard Sandiford  <richard.sandiford@arm.com>
5835
5836         PR target/100942
5837         * ccmp.cc (ccmp_candidate_p): Add outer argument.
5838         Allow if the outer is true and the lhs is used more
5839         than once.
5840         (expand_ccmp_expr): Update call to ccmp_candidate_p.
5841         * expr.h (expand_expr_real_gassign): Declare.
5842         * expr.cc (expand_expr_real_gassign): New function, split out from...
5843         (expand_expr_real_1): ...here.
5844         * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
5845
5846 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5847
5848         PR target/113089
5849         * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
5850         (fixup_debug_use): New.
5851         (fixup_debug_uses_trailing_add): New.
5852         (fixup_debug_uses): New. Use it ...
5853         (ldp_bb_info::fuse_pair): ... here.
5854         (try_promote_writeback): Call fixup_debug_uses_trailing_add to
5855         fix up debug uses of the base register that are affected by
5856         folding in the trailing add insn.
5857
5858 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5859
5860         PR target/113089
5861         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
5862         Update trailing nondebug uses of the base register in the case
5863         of cancelling writeback.
5864
5865 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5866
5867         PR target/113089
5868         * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
5869         (debug_insn_use_iterator): New.
5870         (set_info::first_debug_insn_use): New.
5871         (set_info::debug_insn_uses): New.
5872         * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
5873         (set_info::first_debug_insn_use): New.
5874         (set_info::debug_insn_uses): New.
5875
5876 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5877
5878         PR target/113356
5879         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
5880         Don't record hazards against the opposite insn in the pair.
5881
5882 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5883
5884         PR target/113070
5885         * config/aarch64/aarch64-ldp-fusion.cc
5886         (struct stp_change_builder): New.
5887         (decide_stp_strategy): Reanme to ...
5888         (try_repurpose_store): ... this.
5889         (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
5890         construct stp changes.  Fix up uses when inserting new stp insns.
5891
5892 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5893
5894         PR target/113070
5895         * rtl-ssa.h: Include hash-set.h.
5896         * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
5897         new_sets parameter and use it to keep track of new user-created sets.
5898         (function_info::apply_changes_to_insn): Also call add_def on new sets.
5899         (function_info::change_insns): Add hash_set to keep track of new
5900         user-created defs.  Plumb it through.
5901         * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
5902         apply_changes_to_insn.
5903
5904 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5905
5906         PR target/113070
5907         * rtl-ssa/accesses.cc (function_info::create_use): New.
5908         * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
5909         Ensure new uses end up referring to permanent defs.
5910         * rtl-ssa/functions.h (function_info::create_use): Declare.
5911
5912 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5913
5914         PR target/113070
5915         * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
5916         to finalize_new_accesses from the backwards placement loop, run it
5917         forwards in a separate loop.
5918
5919 2024-01-23  Richard Biener  <rguenther@suse.de>
5920
5921         PR tree-optimization/113552
5922         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
5923         floor_log2 instead of exact_log2 on the number of calls.
5924
5925 2024-01-23  Jeff Law  <jlaw@ventanamicro.com>
5926             Jakub Jelinek  <jakub@redhat.com>
5927
5928         * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
5929         decl.
5930
5931 2024-01-23  Richard Biener  <rguenther@suse.de>
5932
5933         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5934         Separate single and multi-exit case when creating PHIs between
5935         the main and epilogue.
5936
5937 2024-01-23  Richard Sandiford  <richard.sandiford@arm.com>
5938
5939         PR target/112989
5940         * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
5941         MODE_single variants of functions that don't take tuple arguments.
5942
5943 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
5944
5945         PR target/113114
5946         * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
5947         Don't assert recog success, just punt if the writeback pair
5948         isn't recognized.
5949
5950 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
5951
5952         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
5953         ATTRIBUTE_UNUSED to decl.
5954
5955 2024-01-23  Richard Biener  <rguenther@suse.de>
5956
5957         PR debug/107058
5958         * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
5959         handle unexpected but bogus DIE contexts when not checking
5960         enabled.
5961
5962 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
5963
5964         PR tree-optimization/113462
5965         * fold-const.cc (native_interpret_int): Don't punt if total_bytes
5966         is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
5967         (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
5968         sizes between 129 and 8192 bytes.
5969
5970 2024-01-23  Xi Ruoyao  <xry111@xry111.site>
5971
5972         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
5973         If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
5974         for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
5975         (loongarch_call_tls_get_addr): Do not split symbols of
5976         SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
5977         EXPLICIT_RELOCS_AUTO.
5978
5979 2024-01-23  Richard Biener  <rguenther@suse.de>
5980
5981         * alias.cc (known_base_value_p): Remove.
5982         (find_base_value): Remove PLUS/MINUS handling
5983         when both operands are not CONST_INT_P.
5984
5985 2024-01-23  Richard Biener  <rguenther@suse.de>
5986
5987         PR rtl-optimization/113255
5988         * alias.cc (find_base_term): Remove PLUS/MINUS handling
5989         when both operands are not CONST_INT_P.
5990
5991 2024-01-23  Richard Biener  <rguenther@suse.de>
5992
5993         PR debug/112718
5994         * dwarf2out.cc (dwarf2out_finish): Reset all type units
5995         for the fat part of an LTO compile.
5996
5997 2024-01-23  chenxiaolong  <chenxiaolong@loongson.cn>
5998
5999         * doc/sourcebuild.texi: Add attributes for keywords.
6000
6001 2024-01-23  Sandra Loosemore  <sandra@codesourcery.com>
6002
6003         PR c++/90463
6004         * doc/invoke.texi (Warning Options): Correct lists of options
6005         enabled by -Wall and -Wextra by checking against common.opt
6006         and c-family/c.opt.
6007
6008 2024-01-22  Andrew Pinski  <quic_apinski@quicinc.com>
6009
6010         PR target/113030
6011         * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
6012         instead of cpu_optaliases.
6013         (check_arch): Use arch_opt_alias instead of arch_optaliases.
6014
6015 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6016
6017         * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
6018         * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
6019         * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
6020
6021 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6022
6023         PR target/109092
6024         * config/riscv/riscv.md: Use reg instead of subreg.
6025
6026 2024-01-22  Tobias Burnus  <tburnus@baylibre.com>
6027
6028         PR other/111966
6029         * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
6030         to match the compiler default.
6031         (simple_object_copy_lto_debug_sections): Never unlink the outfile
6032         on error as the caller does so.
6033         (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
6034         (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
6035
6036 2024-01-22  Richard Biener  <rguenther@suse.de>
6037
6038         PR tree-optimization/113373
6039         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6040         Create LC PHIs in the exit blocks where necessary.
6041         * tree-vect-loop.cc (vectorizable_live_operation): Do not try
6042         to handle missing LC PHIs.
6043         (find_connected_edge): Remove.
6044         (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
6045
6046 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6047
6048         * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
6049
6050 2024-01-22  xuli  <xuli1@eswincomputing.com>
6051
6052         PR target/113420
6053         * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
6054         (registered_function::overloaded_hash):refactor.
6055         (resolve_overloaded_builtin):avoid internal ICE.
6056
6057 2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>
6058
6059         PR target/82420
6060         PR target/111279
6061         * calls.cc (emit_library_call_value_1): Pass valid TYPE
6062         to emit_push_insn.
6063         * expr.cc (emit_push_insn): Likewise.
6064
6065 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
6066
6067         * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
6068         correcction version of last change.
6069
6070 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
6071
6072         * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
6073         fix bugs in signature.
6074
6075 2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
6076             Richard Biener  <rguenther@suse.de>
6077
6078         PR rtl-optimization/111267
6079         * fwprop.cc (fwprop_propagation::profitabe_p): Rename
6080         profitable_p method to likely_profitable_p.
6081         (try_fwprop_subst_node): Update call to likely_profitable_p.
6082         Only bail-out early when !prop.likely_profitable_p for instructions
6083         that are not single sets.  When comparing costs, bail-out if the
6084         cost is unchanged and !prop.likely_profitable_p.
6085
6086 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
6087
6088         PR c++/90464
6089         * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
6090         isn't enabled by -Wunused unless -Wextra is provided, and that
6091         -Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
6092         -Wunused doesn't enable -Wunused-* options documented as behaving
6093         otherwise, and list them explicitly.
6094
6095 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
6096
6097         PR c/109708
6098         * doc/invoke.texi (Warning Options): Fix broken example and
6099         clean up/reorganize the others.  Also describe what the short-form
6100         options mean.
6101
6102 2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>
6103
6104         PR c/102998
6105         * doc/invoke.texi (Option Summary): Add -Warray-parameter.
6106         (Warning Options): Correct/edit discussion of -Warray-parameter
6107         to make the first example less confusing, and fill in missing info.
6108
6109 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
6110
6111         PR tree-optimization/113462
6112         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
6113         Handle rhs1 INTEGER_CST like SSA_NAME.
6114
6115 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
6116
6117         PR tree-optimization/113491
6118         * tree-switch-conversion.cc (switch_conversion::build_constructors):
6119         If elt.index has precision higher than sizetype, fold_convert it to
6120         sizetype.
6121         (switch_conversion::array_value_type): Return type if type is
6122         BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
6123         (switch_conversion::build_arrays): Use unsigned_type_for rather than
6124         lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
6125         above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
6126         higher than sizetype, use sizetype as tidx type and fold_convert the
6127         subtraction to sizetype.
6128
6129 2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6130
6131         * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
6132         (riscv_vector_mode_supported_any_target_p): Ditto.
6133
6134 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
6135
6136         PR target/110934
6137         * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
6138         (TARGET_ZERO_CALL_USED_REGS): Define.
6139
6140 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
6141
6142         PR target/108640
6143         * config/m68k/m68k.cc (output_andsi3): Use QImode for
6144         address adjusted for 1-byte RMW access.
6145         (output_iorsi3): Likewise.
6146         (output_xorsi3): Likewise.
6147
6148 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
6149
6150         * doc/invoke.texi (RISC-V Options): Add list of supported
6151         extensions.
6152
6153 2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6154
6155         PR target/113495
6156         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
6157         (RVV_VUNDEF): Ditto.
6158         * config/riscv/riscv-vsetvl.cc: Add timevar.
6159
6160 2024-01-19  Richard Biener  <rguenther@suse.de>
6161
6162         PR debug/113488
6163         * lto-streamer-in.cc (lto_read_tree_1): When there isn't
6164         an early DIE but there should be, do not pretend there is.
6165
6166 2024-01-19  Richard Biener  <rguenther@suse.de>
6167
6168         PR tree-optimization/113494
6169         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6170         Handle endless loop on exit.  Handle re-allocated PHI.
6171
6172 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
6173
6174         PR tree-optimization/113464
6175         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
6176         optimize loads into GIMPLE_ASM stmts.
6177
6178 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
6179
6180         PR tree-optimization/113463
6181         * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
6182         Only look through NOP_EXPRs if rhs1 doesn't have wider type than
6183         lhs.
6184
6185 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
6186
6187         PR tree-optimization/113459
6188         * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
6189         TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
6190         of SCALAR_INT_TYPE_MODE if type has BLKmode.
6191         (vn_reference_lookup_3): Likewise.  Formatting fix.
6192
6193 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
6194             Richard Biener  <rguenther@suse.de>
6195
6196         * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
6197         VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
6198         * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
6199         but adjust_address also for BLKmode mode and MEM op0.
6200
6201 2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>
6202
6203         * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
6204         extensions.
6205
6206 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
6207
6208         * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
6209
6210 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
6211
6212         * common/config/riscv/riscv-common.cc
6213         (riscv_subset_list::parse_std_ext): Remove.
6214         (riscv_subset_list::parse_multiletter_ext): Remove.
6215         * config/riscv/riscv-subset.h
6216         (riscv_subset_list::parse_std_ext): Remove.
6217         (riscv_subset_list::parse_multiletter_ext): Remove.
6218
6219 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
6220
6221         * common/config/riscv/riscv-common.cc
6222         (riscv_subset_list::parse_single_std_ext): New parameter.
6223         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
6224         (riscv_subset_list::parse_single_ext): Ditto.
6225         (riscv_subset_list::parse): Relax the order for the input of ISA
6226         string.
6227         * config/riscv/riscv-subset.h
6228         (riscv_subset_list::parse_single_std_ext): New parameter.
6229         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
6230         (riscv_subset_list::parse_single_ext): Ditto.
6231
6232 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
6233
6234         * common/config/riscv/riscv-common.cc
6235         (riscv_subset_list::parse_base_ext): New.
6236         (riscv_subset_list::parse): Extract part of logic into
6237         riscv_subset_list::parse_base_ext.
6238         * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
6239         New.
6240
6241 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
6242
6243         * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
6244         sorry message.
6245
6246 2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>
6247
6248         * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
6249         UNSPEC_CLMUL_VC.
6250
6251 2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>
6252
6253         PR c/110029
6254         * doc/extend.texi (Common Variable Attributes): Explain what
6255         happens when multiple variables with cleanups are in the same scope.
6256
6257 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
6258
6259         PR ipa/108470
6260         * doc/extend.texi (Common Function Attributes): Document that
6261         noinline also disables some interprocedural optimizations and
6262         improve flow to the part about using inline asm instead to
6263         disable calls from being optimized away completely.  Remove the
6264         sentence that says noipa is mainly for internal compiler testing.
6265
6266 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
6267
6268         PR tree-optimization/69807
6269         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
6270
6271 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
6272
6273         PR target/108521
6274         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
6275         from x86 Windows Options.
6276
6277 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
6278
6279         PR c/107942
6280         * doc/extend.texi (C Extensions): Add new section to menu.
6281         (Function Attributes):  Move dangling index entries to....
6282         (Const and Volatile Functions): New section.
6283
6284 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
6285
6286         PR middle-end/112684
6287         * toplev.cc (toplev::main): Don't ICE in
6288         -fdiagnostics-generate-patch when exiting after options,
6289         since no edit context will have been created.
6290
6291 2024-01-18  Richard Biener  <rguenther@suse.de>
6292
6293         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
6294         operands vector.
6295
6296 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
6297
6298         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
6299         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
6300
6301 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6302             Jin Ma  <jinma@linux.alibaba.com>
6303             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6304             Christoph Müllner  <christoph.muellner@vrull.eu>
6305
6306         * config/riscv/thead.cc
6307         (th_asm_output_opcode): Rewrite some instructions.
6308
6309 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6310             Jin Ma  <jinma@linux.alibaba.com>
6311             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6312             Christoph Müllner  <christoph.muellner@vrull.eu>
6313
6314         * config/riscv/riscv.md (none,thv,rvv): New attribute.
6315         (no,yes): Add an attribute to disable alternative
6316         for xtheadvector or RVV1.0.
6317         * config/riscv/vector.md:
6318         Disable alternatives that destination register overlaps
6319         source register group for xtheadvector.
6320
6321 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6322             Jin Ma  <jinma@linux.alibaba.com>
6323             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6324             Christoph Müllner  <christoph.muellner@vrull.eu>
6325
6326         * config/riscv/riscv-vector-builtins-bases.cc
6327         (class th_loadstore_width): Define new builtin bases.
6328         (class th_extract): Define new builtin bases.
6329         (BASE): Define new builtin bases.
6330         * config/riscv/riscv-vector-builtins-bases.h:
6331         Define new builtin class.
6332         * config/riscv/riscv-vector-builtins-shapes.cc
6333         (struct th_loadstore_width_def): Define new builtin shapes.
6334         (struct th_indexed_loadstore_width_def):
6335         Define new builtin shapes.
6336         (struct th_extract_def): Define new builtin shapes.
6337         (SHAPE): Define new builtin shapes.
6338         * config/riscv/riscv-vector-builtins-shapes.h:
6339         Define new builtin shapes.
6340         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
6341         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
6342         * config/riscv/riscv-vector-builtins.h
6343         (enum required_ext): Add new XTheadVector member.
6344         (struct function_group_info): Likewise.
6345         * config/riscv/t-riscv:
6346         Add thead-vector-builtins-functions.def
6347         * config/riscv/thead-vector.md
6348         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
6349         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
6350         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
6351         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
6352         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
6353         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
6354         (@pred_th_extract<mode>): Likewise.
6355         (*pred_th_extract<mode>): Likewise.
6356         * config/riscv/thead-vector-builtins-functions.def: New file.
6357
6358 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6359             Jin Ma  <jinma@linux.alibaba.com>
6360             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6361             Christoph Müllner  <christoph.muellner@vrull.eu>
6362
6363         * config.gcc:  Add files for XTheadVector intrinsics.
6364         * config/riscv/autovec.md: Guard XTheadVector.
6365         * config/riscv/predicates.md: Disable immediate vl
6366         for XTheadVector.
6367         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
6368         Add pragma for XTheadVector.
6369         * config/riscv/riscv-string.cc (riscv_expand_block_move):
6370         Guard XTheadVector.
6371         * config/riscv/riscv-v.cc (vls_mode_valid_p):
6372         Avoid autovec.
6373         * config/riscv/riscv-vector-builtins-bases.cc:
6374         Do not normalize vsetvl instructions for XTheadVector.
6375         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
6376         New check type function.
6377         (build_one): Adjust for XTheadVector.
6378         * config/riscv/riscv-vector-switch.def (ENTRY):
6379         Disable fractional mode for the XTheadVector extension.
6380         (TUPLE_ENTRY): Likewise.
6381         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
6382         Guard XTheadVector.
6383         (riscv_preferred_simd_mode): Likewsie.
6384         (riscv_autovectorize_vector_modes): Likewise.
6385         (riscv_vector_mode_supported_any_target_p): Likewise.
6386         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
6387         * config/riscv/thead.cc (th_asm_output_opcode):
6388         Rewrite vsetvl instructions.
6389         * config/riscv/vector.md:
6390         Include thead-vector.md and change fractional LMUL
6391         into 1 for vbool.
6392         * config/riscv/riscv_th_vector.h: New file.
6393         * config/riscv/thead-vector.md: New file.
6394
6395 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6396             Jin Ma  <jinma@linux.alibaba.com>
6397             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6398             Christoph Müllner  <christoph.muellner@vrull.eu>
6399
6400         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
6401         Add new function to add assembler insn code prefix/suffix.
6402         (th_asm_output_opcode):
6403         Add Thead function to add assembler insn code prefix/suffix.
6404         * config/riscv/riscv.cc (riscv_asm_output_opcode):
6405         Implement function to add assembler insn code prefix/suffix.
6406         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
6407         Add new function to add assembler insn code prefix/suffix.
6408         * config/riscv/thead.cc (th_asm_output_opcode):
6409         Implement Thead function to add assembler insn code
6410         prefix/suffix.
6411
6412 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
6413             Jin Ma  <jinma@linux.alibaba.com>
6414             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
6415             Christoph Müllner  <christoph.muellner@vrull.eu>
6416
6417         * common/config/riscv/riscv-common.cc
6418         (riscv_subset_list::parse): Add new vendor extension.
6419         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
6420         Add test marco.
6421         * config/riscv/riscv.opt:  Add new mask.
6422
6423 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
6424
6425         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
6426         to be conditional on macosx-version-min.
6427
6428 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
6429
6430         * config/darwin.cc (darwin_objc1_section): Use the correct
6431         meta-data version for constant strings.
6432         (machopic_select_section): Assert if we fail to handle CFString
6433         sections as Obejctive-C meta-data or drectly.
6434
6435 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
6436
6437         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
6438         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
6439         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
6440         versions when the object format is Mach-O.
6441
6442 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
6443
6444         PR target/105522
6445         * config/darwin.cc (machopic_select_section): Handle C and C++
6446         CFStrings.
6447         (darwin_rename_builtins): Move this out of the CFString code.
6448         (darwin_libc_has_function): Likewise.
6449         (darwin_build_constant_cfstring): Create an anonymous var to
6450         hold each CFString.
6451         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
6452         CFstrings.
6453
6454 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
6455
6456         PR bootstrap/113445
6457         * haifa-sched.cc (dep_list_size): Make global.
6458         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
6459         * sched-int.h (dep_list_size): Declare.
6460
6461 2024-01-18  Martin Jambor  <mjambor@suse.cz>
6462
6463         PR tree-optimization/110422
6464         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
6465         gotos.
6466
6467 2024-01-18  Richard Biener  <rguenther@suse.de>
6468
6469         PR tree-optimization/113475
6470         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
6471         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
6472         (phi_analyzer::~phi_analyzer): Deallocate and free collected
6473         phi_grous.
6474         (phi_analyzer::process_phi): Record allocated phi_groups.
6475
6476 2024-01-18  Richard Biener  <rguenther@suse.de>
6477
6478         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
6479         storage for gvec_oprnds elements.
6480
6481 2024-01-18  Richard Biener  <rguenther@suse.de>
6482
6483         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
6484         prefer all later exits we can handle.
6485         (vect_analyze_loop_form): Free the allocated loop body.
6486         Adjust comments.
6487
6488 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
6489
6490         * config/avr/avr-log.cc: Tabify.
6491
6492 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6493
6494         * config/riscv/autovec.md: Support vi variant.
6495
6496 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
6497
6498         * config/avr/avr-devices.cc: Tabify.
6499
6500 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
6501
6502         * config/avr/avr-c.cc: Tabify.
6503
6504 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
6505
6506         * config/avr/driver-avr.cc: Tabify.
6507
6508 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
6509
6510         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
6511
6512 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
6513
6514         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
6515
6516 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
6517
6518         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
6519         minline-strcmp, minline-strncmp, minline-strlen,
6520         -param=riscv-vector-abi): Remove Bool keywords.
6521
6522 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
6523
6524         PR target/113122
6525         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
6526         support.  Add missing space after , in emitted assembly in some
6527         cases.  Formatting fixes.
6528
6529 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
6530
6531         * config/loongarch/loongarch.md (movsi_internal): Remove
6532         constraint z.
6533
6534 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
6535
6536         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
6537         in the diagnostic, and capitalize the device name.
6538         (print_mcu): Generate specs such that:
6539         <*check_rodata_in_ram>: New.
6540         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
6541         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
6542         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
6543
6544 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
6545
6546         PR other/113399
6547         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
6548         Common and Optimization.
6549
6550 2024-01-18  Richard Biener  <rguenther@suse.de>
6551
6552         PR tree-optimization/113431
6553         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
6554         When there is an invariant load we might not preserve
6555         scalar order.
6556
6557 2024-01-18  Richard Biener  <rguenther@suse.de>
6558
6559         PR tree-optimization/113374
6560         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
6561         * tree-vect-loop.cc (move_early_exit_stmts): Update
6562         virtual LC PHIs.
6563         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6564         Refactor.  Preserve virtual LC PHIs on all exits.
6565
6566 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
6567
6568         * config/loongarch/loongarch.cc (loongarch_split_symbol):
6569         Assign the '/u' attribute to the mem.
6570
6571 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
6572
6573         PR middle-end/110847
6574         * doc/invoke.texi (Option Summary): Document negative forms of
6575         -Wtsan and -Wxor-used-as-pow.
6576         (Warning Options): Likewise.
6577
6578 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6579
6580         PR target/113429
6581         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
6582
6583 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
6584
6585         * doc/extend.texi (Common Function Attributes): Re-alphabetize
6586         the table.
6587         (Common Variable Attributes): Likewise.
6588         (Common Type Attributes): Likewise.
6589
6590 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
6591
6592         PR middle-end/111659
6593         * doc/extend.texi (Common Variable Attributes): Fix long lines
6594         in documentation of strict_flex_array + other minor copy-editing.
6595         Add a cross-reference to -Wstrict-flex-arrays.
6596         * doc/invoke.texi (Option Summary): Fix whitespace in tables
6597         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
6598         (C Dialect Options): Combine the docs for the two
6599         -fstrict-flex-arrays forms into a single entry.  Note this option
6600         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
6601         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
6602         Minor copy-editing.  Add cross references to the strict_flex_array
6603         attribute and -fstrict-flex-arrays option.  Add note that this
6604         option depends on -ftree-vrp.
6605
6606 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
6607
6608         PR target/113221
6609         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
6610         only allow REG operands instead of allowing all.
6611
6612 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
6613
6614         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
6615         Remove redundant checks in else condition for readablity.
6616         (earliest_fuse_vsetvl_info) Print iteration count in debug
6617         prints.
6618         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
6619         dump details in certain cases.
6620
6621 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
6622
6623         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
6624         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
6625         * config/riscv/riscv-vsetvl.cc
6626         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
6627         (pass_vsetvl::execute): Use vsetvl_strategy.
6628
6629 2024-01-17  Jan Hubicka  <jh@suse.cz>
6630
6631         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
6632         accidental hack reseting offset.
6633
6634 2024-01-17  Jan Hubicka  <jh@suse.cz>
6635
6636         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
6637         handling of X86_TUNE_AVOID_512FMA_CHAINS.
6638
6639 2024-01-17  Jan Hubicka  <jh@suse.cz>
6640             Jakub Jelinek  <jakub@redhat.com>
6641
6642         PR tree-optimization/110852
6643         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
6644         binary operations
6645         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
6646         PRED_COMBINED_VALUE_PREDICTIONS_PHI
6647         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
6648         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
6649
6650 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
6651
6652         PR tree-optimization/113421
6653         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
6654         comment.
6655         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
6656         formatting.  Start at vop rather than cvop even if stmt is a store
6657         and needs_operand_addr.
6658
6659 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
6660
6661         PR middle-end/113410
6662         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
6663         If access_nelts is integral with larger precision than sizetype,
6664         fold_convert it to sizetype.
6665
6666 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
6667
6668         PR tree-optimization/113408
6669         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
6670         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
6671         to handle_cast.
6672
6673 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
6674
6675         PR middle-end/113406
6676         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
6677         regardless of whether is_gimple_reg_type (restype) or not.
6678
6679 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
6680
6681         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
6682         funcions -> functions, and use were instead of was.
6683         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
6684         and guaranteee -> guarantee.
6685         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
6686
6687 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
6688
6689         PR middle-end/113409
6690         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
6691         INTEGER_TYPE.
6692         (omp_extract_for_data): Use build_bitint_type rather than
6693         build_nonstandard_integer_type if either iter_type or loop->v type
6694         is BITINT_TYPE.
6695         * omp-expand.cc (expand_omp_for_generic,
6696         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
6697         BITINT_TYPE like INTEGER_TYPE.
6698
6699 2024-01-17  Richard Biener  <rguenther@suse.de>
6700
6701         PR tree-optimization/113371
6702         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
6703         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
6704         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
6705         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
6706
6707 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
6708
6709         PR rtl-optimization/96388
6710         PR rtl-optimization/111554
6711         * sched-deps.cc (find_inc): Avoid exponential behavior.
6712
6713 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
6714
6715         PR c/111693
6716         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
6717         from C++ Language Options to Warning Options.  Add entry for
6718         -Wuse-after-free.
6719         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
6720         from here....
6721         (Warning Options): ...to here.  Minor copy-editing to fix typo
6722         and grammar.
6723
6724 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
6725
6726         * config/mips/mips.cc (mips_compute_frame_info): If another
6727         register is used as global_pointer, mark $GP live false.
6728
6729 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
6730
6731         PR target/112973
6732         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
6733         give the section a light copy-editing pass.
6734
6735 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
6736
6737         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
6738         * config/aarch64/aarch64-tune.md: Regenerated.
6739         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
6740
6741 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
6742
6743         PR target/112573
6744         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
6745         badly formed CONST expressions.
6746
6747 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
6748
6749         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
6750
6751 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
6752
6753         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
6754         * config/sparc/sync.md (membar_storeload): Turn into named insn
6755         and add GR712RC errata workaround.
6756         (membar_v8): Add GR712RC errata workaround.
6757
6758 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
6759
6760         * config/sparc/sync.md (*membar_storeload_leon3): Remove
6761         (*membar_storeload): Enable for LEON
6762
6763 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
6764
6765         PR tree-optimization/113372
6766         PR middle-end/90348
6767         PR middle-end/110115
6768         PR middle-end/111422
6769         * cfgexpand.cc (add_scope_conflicts_2): New function.
6770         (add_scope_conflicts_1): Use it.
6771
6772 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
6773
6774         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
6775         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
6776         * doc/avr-mmcu.texi: Regenerate.
6777
6778 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
6779
6780         PR tree-optimization/113091
6781         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
6782         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
6783         scalar use with new function.
6784         (vect_bb_slp_mark_live_stmts): New function as entry to existing
6785         overriden functions with same name.
6786         (vect_slp_analyze_operations): Call new entry function to mark
6787         live statements.
6788
6789 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6790
6791         PR target/113404
6792         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
6793         for RVV in big-endian mode.
6794
6795 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
6796
6797         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
6798         (riscv_pass_in_vector_p): Delete.
6799         (riscv_init_cumulative_args): Delete the checking.
6800         (riscv_get_arg_info): Delete the checking.
6801         (riscv_function_value): Delete the checking.
6802         * config/riscv/riscv.h: Delete the member for checking.
6803
6804 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
6805
6806         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
6807
6808 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
6809
6810         * config.gcc: Include riscv_bitmanip.h.
6811         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
6812         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
6813         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
6814         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
6815         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
6816         * config/riscv/riscv-ftypes.def (2): New ftypes.
6817         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
6818         (RISCV_BUILTIN_NO_PREFIX): Likewise.
6819         * config/riscv/riscv_bitmanip.h: New file.
6820
6821 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
6822
6823         * config.gcc: Include riscv_crypto.h.
6824         * config/riscv/riscv_crypto.h: New file.
6825
6826 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
6827
6828         PR middle-end/113354
6829         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
6830         in the insn if the corresponding operand does not require hard
6831         register anymore.
6832
6833 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
6834
6835         PR target/107201
6836         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
6837         * config/avr/driver-avr.cc (avr_no_devlib): New function.
6838         (avr_devicespecs_file): Use it to remove -nodevicelib from the
6839         options for cores only.
6840         * config/avr/avr-arch.h (avr_get_parch): New prototype.
6841         * config/avr/avr-devices.cc (avr_get_parch): New function.
6842
6843 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6844
6845         PR target/113247
6846         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
6847         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
6848         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
6849
6850 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6851
6852         PR target/113281
6853         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
6854         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
6855         * config/riscv/riscv-vector-costs.h: New function.
6856
6857 2024-01-15  Richard Biener  <rguenther@suse.de>
6858
6859         PR tree-optimization/113385
6860         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6861         First redirect, then split the exit edge.
6862
6863 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6864
6865         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
6866         Remove m_num_vector_iterations.
6867         * config/riscv/riscv-vector-costs.h: Ditto.
6868
6869 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
6870
6871         PR target/113156
6872         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
6873         (-mbranch-cost): Set "Optimization" flag.
6874
6875 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
6876
6877         PR tree-optimization/113370
6878         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
6879         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
6880         set it to just prec % limb_prec.
6881
6882 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6883
6884         PR target/113393
6885         * config/riscv/vector.md: Fix ternary attributes.
6886
6887 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
6888
6889         PR target/112944
6890         * configure.ac [target=avr]: Check availability of emulations
6891         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
6892         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
6893         * configure: Regenerate.
6894         * config.in: Regenerate.
6895         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
6896         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
6897         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
6898         * config/avr/avr-arch.h (enum avr_device_specific_features):
6899         Add AVR_ISA_FLMAP.
6900         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
6901         AVR_ISA_FLMAP.
6902         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
6903         (avr_set_core_architecture): Set avr_arch_index.
6904         (have_avrxmega2_flmap, have_avrxmega4_flmap)
6905         (have_avrxmega3_rodata_in_flash): Set new static const bool according
6906         to configure results.
6907         (avr_rodata_in_flash_p): New function using them.
6908         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
6909         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
6910         (avr_asm_named_section): Track avr_has_rodata_p.
6911         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
6912         and not avr_rodata_in_flash_p ().
6913         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
6914         (LINK_SPEC): Add %(link_rodata_in_ram).
6915         (LINK_ARCH_SPEC): Remove.
6916         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
6917         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
6918         const bool according to configure results.
6919         (diagnose_mrodata_in_ram): New function.
6920         (print_mcu): Generate specs with the following changes:
6921         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
6922         need to extend avr/specs.h each time we add a new bell or whistle.
6923         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
6924         -m[no-]rodata-in-ram.
6925         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
6926         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
6927         <*cpp>: Add %(cpp_rodata_in_ram).
6928         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
6929         requested.
6930         <*self_spec>: Add -mflmap or %<mflmap as needed.
6931
6932 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
6933
6934         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
6935         not the GPR iterator.  Adjust pattern name and mode attribute
6936         accordingly.
6937
6938 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
6939
6940         PR tree-optimization/113361
6941         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
6942         Fix up determination of the type for > limb_prec constants.
6943
6944 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
6945
6946         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
6947         Add web-link to the avr-gcc wiki.
6948
6949 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
6950
6951         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
6952         documentation for a version without argument, which is not supported.
6953
6954 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
6955
6956         * config/arm/arm_neon.h
6957         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
6958         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
6959         (vld1_f16_x4, vld1_f32_x4): New.
6960         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
6961         (vld1_bf16_x4): New.
6962         (vld1q_types_x4): Updated to use vld1q_x4
6963         from arm_neon_builtins.def
6964         * config/arm/arm_neon_builtins.def
6965         (vld1_x4): Updated entries.
6966         (vld1q_x4): New entries, but comes from the old vld1_x4
6967         * config/arm/neon.md
6968         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
6969
6970 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
6971
6972         * config/arm/arm_neon.h
6973         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
6974         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
6975         (vld1_f16_x3, vld1_f32_x3): New.
6976         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
6977         (vld1_bf16_x3): New.
6978         (vld1q_types_x3): Updated to use vld1q_x3 from
6979         arm_neon_builtins.def
6980         * config/arm/arm_neon_builtins.def
6981         (vld1_x3): Updated entries.
6982         (vld1q_x3): New entries, but comes from the old vld1_x2
6983         * config/arm/neon.md
6984         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
6985
6986 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
6987
6988         * config/arm/arm_neon.h
6989         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
6990         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
6991         (vld1_f16_x2, vld1_f32_x2): New.
6992         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
6993         (vld1_bf16_x2): New.
6994         (vld1q_types_x2): Updated to use vld1q_x2 from
6995         arm_neon_builtins.def
6996         * config/arm/arm_neon_builtins.def
6997         (vld1_x2): Updated entries.
6998         (vld1q_x2): New entries, but comes from the old vld1_x2
6999         * config/arm/neon.md
7000         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
7001         neon_vld1_x2<mode>.
7002
7003 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7004
7005         * config/arm/arm_neon.h
7006         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
7007         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
7008         (vst1q_f16_x4, vst1q_f32_x4): New.
7009         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
7010         (vst1q_bf16_x4): New.
7011         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
7012         * config/arm/neon.md
7013         (neon_vst1q_x4<mode>): New.
7014         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
7015         * config/arm/unspecs.md
7016         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
7017
7018 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7019
7020         * config/arm/arm_neon.h
7021         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
7022         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
7023         (vst1q_f16_x3, vst1q_f32_x3): New.
7024         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
7025         (vst1q_bf16_x3): New.
7026         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
7027         * config/arm/neon.md
7028         (neon_vst1q_x3<mode>): New.
7029         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
7030         * config/arm/unspecs.md
7031         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
7032
7033 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7034
7035         * config/arm/arm_neon.h
7036         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
7037         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
7038         (vst1q_f16_x2, vst1q_f32_x2): New.
7039         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
7040         (vst1q_bf16_x2): New.
7041         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
7042         * config/arm/neon.md
7043         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
7044         neon_vst1_x2<mode>.
7045         * config/arm/iterators.md
7046         (VMEMX2): New mode iterator.
7047         (VMEMX2_q): New mode attribute.
7048
7049 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7050
7051         * config/arm/arm_neon.h
7052         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
7053         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
7054         (vst1_f16_x4, vst1_f32_x4): New.
7055         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
7056         (vst1_bf16_x4): New.
7057         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
7058         * config/arm/neon.md (vst1_x4<mode>): New.
7059
7060 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7061
7062         * config/arm/arm_neon.h
7063         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
7064         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
7065         (vst1_f16_x3, vst1_f32_x3): New.
7066         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
7067         (vst1_bf16_x3): New.
7068         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
7069         * config/arm/neon.md (vst1_x3<mode>): New.
7070
7071 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7072
7073         * config/arm/arm_neon.h
7074         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
7075         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
7076         (vst1_f16_x2, vst1_f32_x2): New.
7077         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
7078         (vst1_bf16_x2): New.
7079         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
7080         * config/arm/neon.md (vst1_x2<mode>): New.
7081
7082 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7083
7084         * config/arm/arm_neon.h
7085         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
7086         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
7087         (vld1q_f16_x4, vld1q_f32_x4): New.
7088         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
7089         (vld1q_bf16_x4): New.
7090         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
7091         * config/arm/neon.md
7092         (neon_vld1_x4<mode>): New.
7093         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
7094         * config/arm/unspecs.md
7095         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
7096
7097 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7098
7099         * config/arm/arm_neon.h
7100         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
7101         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
7102         (vld1q_f16_x3, vld1q_f32_x3): New.
7103         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
7104         (vld1q_bf16_x3): New.
7105         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
7106         * config/arm/neon.md
7107         (neon_vld1_x3<mode>): New.
7108         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
7109         * config/arm/unspecs.md
7110         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
7111
7112 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
7113
7114         * config/arm/arm_neon.h
7115         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
7116         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
7117         (vld1q_f16_x2, vld1q_f32_x2): New.
7118         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
7119         (vld1q_bf16_x2): New.
7120         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
7121         * config/arm/neon.md (vld1_x2<mode>): New.
7122
7123 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
7124
7125         PR tree-optimization/113287
7126         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
7127
7128 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
7129
7130         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
7131         * tree-vect-loop.cc (vect_transform_loop): Likewise.
7132
7133 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
7134
7135         PR tree-optimization/113178
7136         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
7137         alternate exits.
7138
7139 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
7140
7141         PR tree-optimization/113237
7142         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
7143         existing LCSSA variable for exit when all exits are early break.
7144
7145 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
7146
7147         PR tree-optimization/113137
7148         PR tree-optimization/113136
7149         PR tree-optimization/113172
7150         PR tree-optimization/113178
7151         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
7152         Maintain PHIs on inverted loops.
7153         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
7154         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
7155         latch.
7156         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
7157
7158 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
7159
7160         PR tree-optimization/113135
7161         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
7162         dependency analysis.
7163
7164 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
7165
7166         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
7167         diagnostics class member name for abort of error.
7168
7169 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
7170
7171         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
7172         format string to %s argument.
7173
7174 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
7175             Jakub Jelinek  <jakub@redhat.com>
7176
7177         PR middle-end/113182
7178         * varasm.cc (process_pending_assemble_externals,
7179         assemble_external_libcall): Use targetm.strip_name_encoding
7180         before calling get_identifier.
7181
7182 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
7183
7184         PR target/113196
7185         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
7186         New member variable.
7187         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
7188         Declare.
7189         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
7190         * config/aarch64/aarch64-simd.md
7191         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
7192         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
7193         zip2 for zero-extends to...
7194         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
7195         instruction.  Fix big-endian handling.
7196         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
7197         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
7198         zip1 for zero-extends to...
7199         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
7200         Fix big-endian handling.
7201         (*aarch64_zip1_uxtl): New pattern.
7202         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
7203         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
7204         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
7205         (aarch64_gen_shareable_zero): Use it.
7206         (aarch64_split_simd_shift_p): New function.
7207
7208 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
7209
7210         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
7211         (function_beg_insn): New macro.
7212         * function.cc (expand_function_start): Initialize function_beg_insn.
7213
7214 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
7215
7216         PR target/112989
7217         * config/aarch64/aarch64-sve-builtins.h
7218         (function_builder::m_overload_names): Replace with...
7219         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
7220         new global.
7221         (add_overloaded_function): Update accordingly, using get_identifier
7222         to get a GGC-friendly record of the name.
7223
7224 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
7225
7226         PR target/112989
7227         * config/aarch64/aarch64-sve-builtins.def: Don't include
7228         aarch64-sve-builtins-sme.def.
7229         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
7230         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
7231         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
7232         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
7233         requires AARCH64_FL_SME2.
7234         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
7235         AARCH64_FL_SME adjustment here.
7236         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
7237         include SME intrinsics.
7238         (sme_function_groups): New array.
7239         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
7240         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
7241
7242 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7243
7244         PR target/113281
7245         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
7246         (struct cpu_vector_cost): Add regmove struct.
7247         (get_vector_costs): Export as global.
7248         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
7249         (costs::add_stmt_cost): Ditto.
7250         * config/riscv/riscv.cc (get_common_costs): Export global function.
7251
7252 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
7253
7254         PR tree-optimization/113334
7255         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
7256         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
7257         to determine if number should be extended by all ones rather than zero
7258         extended.
7259
7260 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
7261
7262         PR tree-optimization/113330
7263         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
7264         too large size.
7265
7266 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
7267
7268         PR tree-optimization/113323
7269         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
7270         check for lhs being large/huge _BitInt not in m_names.
7271
7272 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
7273
7274         PR tree-optimization/113316
7275         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
7276         uninitialized large/huge _BitInt arguments to calls.
7277
7278 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
7279
7280         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
7281         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
7282         CEIL (TYPE_PRECISION (t), limb_prec).
7283         (bitint_large_huge::handle_cast): Likewise.
7284
7285 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
7286
7287         PR sanitizer/113284
7288         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
7289         Use assemble_function_label_final () for Power ELF V1 ABI.
7290         * output.h (assemble_function_label_final): New function.
7291         * varasm.cc (assemble_function_label_raw): Use
7292         assemble_function_label_final ().
7293         (assemble_function_label_final): New function.
7294
7295 2024-01-12  Richard Biener  <rguenther@suse.de>
7296
7297         PR middle-end/113344
7298         * match.pd ((double)float CMP (double)float -> float CMP float):
7299         Perform result type check only for vectors.
7300         * fold-const.cc (fold_binary_loc): Likewise.
7301
7302 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
7303
7304         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
7305         (usdot_prod<mode>): Ditto.
7306         (sdot_prod<mode>): Ditto.
7307         (udot_prod<mode>): Ditto.
7308
7309 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
7310
7311         PR target/113288
7312         * config/i386/i386-c.cc (ix86_target_macros_internal):
7313         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
7314
7315 2024-01-12  Richard Biener  <rguenther@suse.de>
7316
7317         PR target/112280
7318         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
7319         Do not generate code when d.testing_p.
7320
7321 2024-01-12  liuhongt  <hongtao.liu@intel.com>
7322
7323         PR target/113039
7324         * doc/invoke.texi (fcf-protection=): Update documents.
7325
7326 2024-01-12  Pan Li  <pan2.li@intel.com>
7327
7328         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
7329         comments of predicate func riscv_v_ext_mode_p.
7330
7331 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
7332
7333         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
7334                         Modify ABI-name length of vfloat16m8_t
7335
7336 2024-01-12  Li Wei  <liwei@loongson.cn>
7337
7338         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
7339         Adjust.
7340
7341 2024-01-12  Li Wei  <liwei@loongson.cn>
7342
7343         * config/loongarch/loongarch.md (add<mode>3): Removed.
7344         (*addsi3): New.
7345         (addsi3): Ditto.
7346         (adddi3): Ditto.
7347         (*addsi3_extended): Removed.
7348         (addsi3_extended): New.
7349
7350 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
7351
7352         * config/riscv/thead.md: Add limits for splits.
7353
7354 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
7355
7356         PR middle-end/113322
7357         * expr.cc (do_store_flag): Don't try single bit tests with
7358         comparison on vector types.
7359
7360 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
7361
7362         PR tree-optimization/113301
7363         * match.pd (`1/x`): Delay signed case until late.
7364
7365 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
7366
7367         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
7368         and -msp8 to...
7369         (AVR Internal Options): ...this new @subsubsection.
7370
7371 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
7372
7373         PR rtl-optimization/112918
7374         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
7375         (in_class_p): Restrict condition for narrowing class in case of
7376         allow_all_reload_class_changes_p.
7377         (process_alt_operands): Try to match operand without and with
7378         narrowing reg class.  Discourage narrowing the class.  Finish insn
7379         matching only if there is no class narrowing.
7380         (curr_insn_transform): Pass true to in_class_p for reg operand win.
7381
7382 2024-01-11  Richard Biener  <rguenther@suse.de>
7383
7384         PR tree-optimization/112505
7385         * tree-vect-loop.cc (vectorizable_induction): Reject
7386         bit-precision induction.
7387
7388 2024-01-11  Richard Biener  <rguenther@suse.de>
7389
7390         PR tree-optimization/113126
7391         * match.pd ((double)float CMP (double)float -> float CMP float):
7392         Make sure the boolean type is the same.
7393         * fold-const.cc (fold_binary_loc): Likewise.
7394
7395 2024-01-11  Richard Biener  <rguenther@suse.de>
7396
7397         PR tree-optimization/112636
7398         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
7399         estimate_numbers_of_iterations before querying
7400         get_max_loop_iterations_int.
7401         (pass_ch::execute): Initialize SCEV and loops appropriately.
7402
7403 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
7404
7405         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
7406         Reduced Tiny.
7407         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
7408         * doc/extend.texi (AVR Variable Attributes): Improve documentation
7409         of io, io_low and address attributes.
7410         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
7411         * doc/avr-mmcu.texi: Rebuild.
7412
7413 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
7414
7415         PR target/113233
7416         * config/loongarch/genopts/loongarch.opt.in: Mark options with
7417         the "Save" property.
7418         * config/loongarch/loongarch.opt: Same.
7419         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
7420         according to la_target.
7421         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
7422         RESTORE} for the la_target structure; Rename option conditions
7423         to have the same "la_" prefix.
7424         * config/loongarch/loongarch.h: Same.
7425
7426 2024-01-11  Pan Li  <pan2.li@intel.com>
7427
7428         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
7429         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
7430
7431 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
7432
7433         PR target/113077
7434         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
7435         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
7436         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
7437         synthesize these if needed.  Update caller ...
7438         (ldp_bb_info::fuse_pair): ... here.
7439         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
7440         and either insn is frame-related.
7441         (find_trailing_add): Punt on frame-related insns.
7442         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
7443         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
7444
7445 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
7446
7447         * config/mips/mips.cc (mips_start_function_definition):
7448         Add ATTRIBUTE_UNUSED.
7449
7450 2024-01-11  Richard Biener  <rguenther@suse.de>
7451
7452         PR middle-end/112740
7453         * expr.cc (store_constructor): Check the integer vector
7454         mask has a single bit per element before using sign-extension
7455         to expand an uniform vector.
7456
7457 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7458
7459         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
7460         preempt VLS on unknown NITERS loop.
7461
7462 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
7463
7464         * doc/invoke.texi: Add -mevex512.
7465
7466 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
7467
7468         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
7469         (*nor<mode>3): Likewise.
7470         (nor<mode>3): Likewise.
7471         (*negsi2_extended): New template.
7472         (*<optab>si3_internal): Likewise.
7473         (*one_cmplsi2_internal): Likewise.
7474         (*norsi3_internal): Likewise.
7475         (*<optab>nsi_internal): Likewise.
7476         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
7477         modified bit operation to make the optimization work.
7478
7479 2024-01-11  liuhongt  <hongtao.liu@intel.com>
7480
7481         PR target/104401
7482         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
7483
7484 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7485
7486         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
7487         (get_vector_costs): Ditto.
7488         (riscv_builtin_vectorization_cost): Ditto.
7489
7490 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7491
7492         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
7493
7494 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
7495
7496         PR jit/111396
7497         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
7498         ipa_free_size_summary.
7499         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
7500         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
7501         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
7502         * ipa-prop.h (ipa_prop_cc_finalize): New function.
7503         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
7504         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
7505         ipa_sra_cc_finalize): New functions.
7506         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
7507         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
7508         ipa_sra_cc_finalize
7509         Include ipa-utils.h.
7510
7511 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
7512
7513         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
7514         (th_int_get_save_adjustment): Likewise.
7515         (th_int_adjust_cfi_prologue): Likewise.
7516         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
7517         (TH_INT_INTERRUPT): New macro.
7518         (riscv_expand_prologue): Add the processing of XTheadInt.
7519         (riscv_expand_epilogue): Likewise.
7520         * config/riscv/riscv.h (BITSET_P): Moved to here.
7521         * config/riscv/riscv.md: New unspec.
7522         * config/riscv/thead.cc (th_int_get_mask): New function.
7523         (th_int_get_save_adjustment): Likewise.
7524         (th_int_adjust_cfi_prologue): Likewise.
7525         * config/riscv/thead.md (th_int_push): New pattern.
7526         (th_int_pop): new pattern.
7527
7528 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
7529
7530         PR tree-optimization/112468
7531         * doc/sourcebuild.texi: Document ifn_copysign.
7532         * match.pd: Only apply transformation if target supports the IFN.
7533
7534 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
7535
7536         PR tree-optimization/112581
7537         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
7538         mark_ssa_maybe_undefs.
7539         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
7540         variables can not be reassociated.
7541         (init_range_entry): Check for uninitialized variables too.
7542         (init_reassoc): Call mark_ssa_maybe_undefs.
7543
7544 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
7545
7546         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
7547         Also handle sign extension.
7548
7549 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
7550
7551         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
7552         to 0.
7553         (-mlate-ldp-fusion): Likewise.
7554
7555 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
7556
7557         PR tree-optimization/113287
7558         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
7559         instead of using BRANCH_EDGE to determine true edge.
7560
7561 2024-01-10  Richard Biener  <rguenther@suse.de>
7562
7563         PR tree-optimization/113078
7564         * tree-vect-loop.cc (check_reduction_path): Canonicalize
7565         .COND_SUB to .COND_ADD.
7566
7567 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
7568
7569         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
7570         Handle prefix mappings before calling find_opt.
7571         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
7572         "-fno-"-prefixed command-line option.
7573         * opts-common.cc (get_option_prefix_remapping): New.
7574         * opts.h (get_option_prefix_remapping): New decl.
7575
7576 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
7577
7578         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
7579         m_urlifier to pp_output_formatted_text.
7580         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
7581         (obstack_append_string): New overload, taking a length.
7582         (urlify_quoted_string): Pass in an obstack ptr, rather than using
7583         that of the pp's buffer.  Generalize to handle trailing text in
7584         the buffer beyond the run of quoted text.
7585         (class quoting_info): New.
7586         (on_begin_quote): New.
7587         (on_end_quote): New.
7588         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
7589         it to calls to on_begin_quote and on_end_quote.
7590         (struct auto_obstack): New.
7591         (quoting_info::handle_phase_3): New.
7592         (pp_output_formatted_text): Add urlifier param.  Use it if there
7593         is deferred urlification.  Delete m_quotes.
7594         (selftest::pp_printf_with_urlifier): Pass urlifier to
7595         pp_output_formatted_text.
7596         (selftest::test_urlification): Update results for the existing
7597         case of quoted text stradding chunks; add more such test cases.
7598         * pretty-print.h (class quoting_info): New forward decl.
7599         (chunk_info::m_quotes): New field.
7600         (pp_output_formatted_text): Add optional urlifier param.
7601
7602 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
7603
7604         * pretty-print.cc (selftest::test_pp_format): Add selftest
7605         coverage for numbered args.
7606
7607 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
7608
7609         PR tree-optimization/113144
7610         PR tree-optimization/113145
7611         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
7612         Update all BB that the original exits dominated.
7613
7614 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
7615
7616         * dwarf2out.cc (modified_type_die): Extend the support of reverse
7617         storage order to enumeration types if -gstrict-dwarf is not passed.
7618         (gen_enumeration_type_die): Add REVERSE parameter and generate the
7619         DIE immediately after the existing one if it is true.
7620         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
7621         call to gen_enumeration_type_die.
7622         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
7623         first recursive call as well as the call to gen_tagged_type_die.
7624         (gen_type_die): Add REVERSE parameter and pass it in the call to
7625         gen_type_die_with_usage.
7626
7627 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
7628
7629         PR tree-optimization/113120
7630         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
7631         with root->size TYPE_PRECISION don't build anything new.
7632         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
7633         rather than build_nonstandard_integer_type.
7634
7635 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
7636
7637         * config/i386/i386.opt: Adjust document.
7638         * doc/invoke.texi: Add description for
7639         -mapx-inline-asm-use-gpr32.
7640
7641 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7642
7643         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
7644         (avg<v_double_trunc>3_floor): New pattern.
7645         (<u>avg<v_double_trunc>3_ceil): Remove.
7646         (avg<v_double_trunc>3_ceil): New pattern.
7647         (uavg<mode>3_floor): Ditto.
7648         (uavg<mode>3_ceil): Ditto.
7649         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
7650         (enum insn_type): Ditto.
7651         * config/riscv/riscv-v.cc: Ditto.
7652         * config/riscv/vector-iterators.md (ashiftrt): Remove.
7653         (ASHIFTRT): Ditto.
7654         * config/riscv/vector.md: Add VLS modes.
7655
7656 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
7657
7658         PR target/111480
7659         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
7660         (vczlsbb_char): New int attribute.
7661         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
7662         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
7663         (*vctzlsbb_zext_<mode>): Rename to ...
7664         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
7665         cover vclzlsbb.
7666
7667 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
7668
7669         PR target/112606
7670         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
7671         of the last argument from altivec_register_operand to any_operand.  If
7672         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
7673         otherwise if it doesn't satisfy altivec_register_operand, force it to
7674         REG using copy_to_mode_reg.
7675
7676 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
7677
7678         PR middle-end/113100
7679         * builtins.cc (expand_builtin_stack_address): Guard stack point
7680         adjustment with SPARC_STACK_BOUNDARY_HACK.
7681
7682 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
7683
7684         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
7685         argument string definitions.
7686         * config/loongarch/loongarch-str.h: Same.
7687         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
7688         as aliases to -mexplicit-relocs={always,none}
7689         * config/loongarch/loongarch.opt: Regenerate.
7690         * config/loongarch/loongarch.cc: Same.
7691
7692 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
7693
7694         * config/loongarch/loongarch-def.h: Define constants with
7695         enums instead of Macros.
7696
7697 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
7698
7699         * config/loongarch/genopts/loongarch-strings: Rename.
7700         * config/loongarch/genopts/loongarch.opt.in: Same.
7701         * config/loongarch/loongarch-cpu.cc: Same.
7702         * config/loongarch/loongarch-def.cc: Same.
7703         * config/loongarch/loongarch-def.h: Same.
7704         * config/loongarch/loongarch-opts.cc: Same.
7705         * config/loongarch/loongarch-opts.h: Same.
7706         * config/loongarch/loongarch-str.h: Same.
7707         * config/loongarch/loongarch.opt: Same.
7708
7709 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
7710
7711         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
7712         variable with the common la_ prefix.
7713         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
7714         flags as saved using TargetVariable.
7715         * config/loongarch/loongarch.opt: Same.
7716         * config/loongarch/loongarch-def.h: Define evolution_set to
7717         mark changes to the -march default.
7718         * config/loongarch/loongarch-driver.cc: Same.
7719         * config/loongarch/loongarch-opts.cc: Same.
7720         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
7721         conditions around the la_target structure.
7722         * config/loongarch/loongarch.cc: Same.
7723         * config/loongarch/loongarch.md: Same.
7724         * config/loongarch/loongarch-builtins.cc: Same.
7725         * config/loongarch/loongarch-c.cc: Same.
7726         * config/loongarch/lasx.md: Same.
7727         * config/loongarch/lsx.md: Same.
7728         * config/loongarch/sync.md: Same.
7729
7730 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
7731
7732         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
7733         no less.
7734
7735 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
7736
7737         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
7738
7739 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
7740
7741         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
7742         restart_loop.
7743         (vectorizable_live_operation): Likewise.
7744
7745 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
7746
7747         PR tree-optimization/113199
7748         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
7749         BIT_FIELD_REF.
7750
7751 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
7752
7753         PR target/113270
7754         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
7755         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
7756         GTY(()) declaration before the definition, drop GTY(()) drom the
7757         definition.
7758
7759 2024-01-09  Richard Biener  <rguenther@suse.de>
7760
7761         PR tree-optimization/113026
7762         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
7763         redundant and wrong niter bound setting.  Move niter
7764         bound adjustment down.
7765
7766 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
7767
7768         PR middle-end/113163
7769         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
7770         Reject non-linear inductions that aren't supported.
7771
7772 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
7773
7774         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
7775         left shift implementation strategies.
7776         (arc_shift_info): Type for each entry of the shift strategy table.
7777         (arc_shift_context_idx): Return a integer value for each code
7778         generation context, used as an index
7779         (arc_ashl_alg): Table indexed by context and shifted bit count.
7780         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
7781         left shift implementation.
7782         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
7783         provide accurate costs, when optimizing for speed or size.
7784
7785 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7786
7787         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
7788
7789 2024-01-09  Julian Brown  <julian@codesourcery.com>
7790
7791         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
7792         processed out before gimplification.
7793         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
7794         * tree.def (OMP_ARRAY_SECTION): New tree code.
7795
7796 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
7797
7798         PR tree-optimization/113210
7799         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
7800         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
7801         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
7802         minus 1.
7803
7804 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
7805
7806         PR rtl-optimization/113140
7807         * reorg.cc (fill_slots_from_thread): If we are to branch after the
7808         last instruction of the function, create an end label.
7809
7810 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
7811             Hongtao Liu  <hongtao.liu@intel.com>
7812
7813         PR target/112992
7814         * config/i386/i386-expand.cc
7815         (ix86_convert_const_wide_int_to_broadcast): Allow call to
7816         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
7817         (ix86_broadcast_from_constant): Revert recent change; Return a
7818         suitable MEMREF independently of mode/target combinations.
7819         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
7820         to decide whether expansion is possible/preferrable.  Only try
7821         forcing DImode constants to memory (and trying again) if calling
7822         ix86_expand_vector_init_duplicate fails with an DImode immediate
7823         constant.
7824         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
7825         V4SImode for suitable immediate constants.
7826         <case E_V4DImode>: Try using V8SImode for suitable constants.
7827         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
7828         <case E_V2HImode>: Likewise.
7829         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
7830         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
7831         <label widen>: Handle CONT_INTs via simplify_binary_operation.
7832         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
7833         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
7834         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
7835         (ix86_expand_vector_init): Move try using a broadcast for all_same
7836         with ix86_expand_vector_init_duplicate before using constant pool.
7837
7838 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
7839
7840         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
7841
7842 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
7843
7844         * config/arm/arm-cpus.in (cortex-m52): New cpu.
7845         * config/arm/arm-tables.opt: Regenerate.
7846         * config/arm/arm-tune.md: Regenerate.
7847
7848 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
7849
7850         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
7851         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
7852         (@vec_concatz<mode>): New insn pattern.
7853         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
7854         Handle VALS containing two vectors.
7855
7856 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7857
7858         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
7859         (vundefined): Ditto.
7860
7861 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
7862
7863         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7864                                 Add new function_base for crypto vector.
7865         (class bitmanip): Ditto.
7866         (class b_reverse):Ditto.
7867         (class vwsll):   Ditto.
7868         (class clmul):   Ditto.
7869         (class vg_nhab):  Ditto.
7870         (class crypto_vv):Ditto.
7871         (class crypto_vi):Ditto.
7872         (class vaeskf2_vsm3c):Ditto.
7873         (class vsm3me): Ditto.
7874         (BASE): Add BASE declaration for crypto vector.
7875         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7876         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7877                                 Add crypto vector intrinsic definition.
7878         (vbrev): Ditto.
7879         (vclz): Ditto.
7880         (vctz): Ditto.
7881         (vwsll): Ditto.
7882         (vandn): Ditto.
7883         (vbrev8): Ditto.
7884         (vrev8): Ditto.
7885         (vrol): Ditto.
7886         (vror): Ditto.
7887         (vclmul): Ditto.
7888         (vclmulh): Ditto.
7889         (vghsh): Ditto.
7890         (vgmul): Ditto.
7891         (vaesef): Ditto.
7892         (vaesem): Ditto.
7893         (vaesdf): Ditto.
7894         (vaesdm): Ditto.
7895         (vaesz): Ditto.
7896         (vaeskf1): Ditto.
7897         (vaeskf2): Ditto.
7898         (vsha2ms): Ditto.
7899         (vsha2ch): Ditto.
7900         (vsha2cl): Ditto.
7901         (vsm4k): Ditto.
7902         (vsm4r): Ditto.
7903         (vsm3me): Ditto.
7904         (vsm3c): Ditto.
7905         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7906                                 Add new function_shape for crypto vector.
7907         (struct crypto_vi_def): Ditto.
7908         (struct crypto_vv_no_op_type_def): Ditto.
7909         (SHAPE): Add SHAPE declaration of crypto vector.
7910         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7911         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7912                                 Add new data type for crypto vector.
7913         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7914         (vuint32mf2_t): Ditto.
7915         (vuint32m1_t): Ditto.
7916         (vuint32m2_t): Ditto.
7917         (vuint32m4_t): Ditto.
7918         (vuint32m8_t): Ditto.
7919         (vuint64m1_t): Ditto.
7920         (vuint64m2_t): Ditto.
7921         (vuint64m4_t): Ditto.
7922         (vuint64m8_t): Ditto.
7923         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7924                                 Add new data struct for crypto vector.
7925         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7926         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7927         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7928
7929 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
7930
7931         PR sanitizer/113251
7932         * varasm.cc (assemble_function_label_raw): Do not call
7933         asan_function_start () without the current function.
7934
7935 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
7936
7937         PR target/113225
7938         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
7939         extern and kernel_helper attributed function decls.
7940
7941 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
7942
7943         * btfout.cc (output_btf_strs): Changed.
7944
7945 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
7946
7947         * config/gcn/mkoffload.cc (main): Handle gfx1100
7948         when setting the default XNACK.
7949
7950 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
7951
7952         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
7953         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
7954         (ASM_SPEC): Handle gfx1100.
7955         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
7956         (enum gcn_isa): Add ISA_RDNA3.
7957         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
7958         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
7959         * config/gcn/gcn.cc (gcn_option_override,
7960         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
7961         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
7962         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
7963         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
7964         with gfx1100.
7965         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
7966         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
7967         __gfx1100__.
7968         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
7969         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
7970         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
7971         (isa_has_combined_avgprs, main): Handle gfx1100.
7972         * config/gcn/t-omp-device (isa): Add gfx1100.
7973
7974 2024-01-08  Richard Biener  <rguenther@suse.de>
7975
7976         * doc/invoke.texi (-mmovbe): Clarify.
7977
7978 2024-01-08  Richard Biener  <rguenther@suse.de>
7979
7980         PR tree-optimization/113026
7981         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
7982         Avoid an epilog in more cases.
7983         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
7984         epilogues niter upper bounds and estimates.
7985
7986 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
7987
7988         PR tree-optimization/113228
7989         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
7990
7991 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
7992
7993         PR tree-optimization/113120
7994         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
7995         large _BitInt zero INTEGER_CST PHI argument.
7996
7997 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
7998
7999         PR tree-optimization/113119
8000         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
8001         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
8002         is before REALPART_EXPR.
8003
8004 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
8005
8006         PR target/112952
8007         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
8008         range when diagnosing attribute "io" and "io_low" are out of range.
8009         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
8010         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
8011         in contexts other than static storage.
8012         (avr_asm_output_aligned_decl_common): Move output of decls with
8013         attribute "address", "io", and "io_low" to...
8014         (avr_output_addr_attrib): ...this new function.
8015         (avr_asm_asm_output_aligned_bss): Remove output for decls with
8016         attribute "address", "io", and "io_low".
8017         (avr_encode_section_info): Rectify handling of decls with attribute
8018         "address", "io", and "io_low".
8019
8020 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
8021
8022         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
8023         (elf_flags): Remove XNACK from the default value.
8024         (main): Set a default XNACK according to the arch.
8025
8026 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
8027
8028         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
8029         (process_asm): Don't count avgprs.
8030
8031 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
8032
8033         * config/i386/i386.opt: Add supported sub-features.
8034         * doc/extend.texi: Add description for target attribute.
8035
8036 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
8037
8038         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
8039
8040 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
8041             Uros Bizjak  <ubizjak@gmail.com>
8042
8043         PR target/113231
8044         * config/i386/i386-features.cc (compute_convert_gain): Include
8045         the overhead of explicit load and store (movd) instructions when
8046         converting non-store scalar operations with memory destinations.
8047         Various indentation whitespace fixes.
8048
8049 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
8050
8051         * config/arm/neon.md (cbranch<mode>4): New.
8052
8053 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8054
8055         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
8056
8057 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
8058
8059         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
8060
8061 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8062
8063         PR target/113248
8064         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
8065         Update the MAX_SEW.
8066
8067 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8068
8069         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
8070         (variable_vectorized_p): Teach loop invariant.
8071         (has_unexpected_spills_p): Ditto.
8072
8073 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8074
8075         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
8076         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
8077         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
8078
8079 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
8080
8081         PR target/113104
8082         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
8083         (aarch64-vect-compare-costs): ...this.
8084         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
8085         Replace with...
8086         (-param=aarch64-vect-compare-costs=): ...this new param.
8087         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
8088         Don't disable it when vectorizing for Advanced SIMD only.
8089         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
8090         whenever aarch64_vect_compare_costs is true.
8091
8092 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
8093
8094         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
8095         Modify the method of determining the memory offset of [x]vld/[x]vst.
8096         (lasx_mxst_<lasxfmt_f>): Likewise.
8097         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
8098         (loongarch_address_insns): Likewise.
8099         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
8100         (lsx_st_<lsxfmt_f>): Likewise.
8101         * config/loongarch/predicates.md (aq10b_operand): Likewise.
8102         (aq10h_operand): Likewise.
8103         (aq10w_operand): Likewise.
8104         (aq10d_operand): Likewise.
8105
8106 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
8107
8108         PR target/113217
8109         * config/aarch64/aarch64-ldp-fusion.cc
8110         (ldp_bb_info::try_fuse_pair): If the second access can throw,
8111         narrow the move range to exactly that insn.
8112
8113 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
8114
8115         * asan.cc (asan_function_start): Drop switch_to_section ().
8116         (asan_emit_stack_protection): Set .LASANPC alignment.
8117         * config/i386/i386.cc: Use assemble_function_label_raw ()
8118         instead of ASM_OUTPUT_LABEL ().
8119         * config/s390/s390.cc (s390_asm_output_function_label):
8120         Likewise.
8121         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
8122         * final.cc (final_start_function_1): Drop
8123         asan_function_start ().
8124         * output.h (assemble_function_label_raw): New function.
8125         * varasm.cc (assemble_function_label_raw): Likewise.
8126
8127 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
8128
8129         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
8130         Use ASM_OUTPUT_FUNCTION_LABEL ().
8131         * config/alpha/alpha.cc (alpha_start_function): Likewise.
8132         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8133         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
8134         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8135         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8136         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
8137         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8138         * config/ia64/ia64.cc (ia64_start_function): Likewise.
8139         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
8140         Likewise.
8141         * config/microblaze/microblaze.cc (microblaze_function_prologue):
8142         Likewise.
8143         * config/mips/mips.cc (mips_start_unique_function): Return the
8144         tree.
8145         (mips_start_function_definition): Use
8146         ASM_OUTPUT_FUNCTION_LABEL ().
8147         (mips_finish_stub): Pass the tree to
8148         mips_start_function_definition ().
8149         (mips16_build_function_stub): Likewise.
8150         (mips16_build_call_stub): Likewise.
8151         (mips_output_function_prologue): Likewise.
8152         * config/pa/pa.cc (pa_output_function_label): Use
8153         ASM_OUTPUT_FUNCTION_LABEL ().
8154         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
8155         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
8156         Likewise.
8157         (rs6000_xcoff_declare_function_name): Likewise.
8158
8159 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
8160
8161         PR tree-optimization/113201
8162         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
8163         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
8164
8165 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
8166
8167         PR tree-optimization/90693
8168         * tree-ssa-math-opts.cc (match_single_bit_test): If
8169         tree_expr_nonzero_p (arg), remember it in the second argument to
8170         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
8171         arg ^ (arg - 1) > arg - 1.
8172         * internal-fn.cc (expand_POPCOUNT): If second argument to
8173         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
8174         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
8175
8176 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
8177
8178         * config/riscv/riscv-v.cc (expand_load_store):
8179         Remove `value`.
8180         (expand_cond_len_op): Ditto.
8181         (expand_gather_scatter): Ditto.
8182         (expand_lanes_load_store): Ditto.
8183         (expand_fold_extract_last): Ditto.
8184
8185 2024-01-05  Pan Li  <pan2.li@intel.com>
8186
8187         Revert:
8188         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
8189
8190         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
8191                                 Add new function_base for crypto vector.
8192         (class bitmanip): Ditto.
8193         (class b_reverse):Ditto.
8194         (class vwsll):   Ditto.
8195         (class clmul):   Ditto.
8196         (class vg_nhab):  Ditto.
8197         (class crypto_vv):Ditto.
8198         (class crypto_vi):Ditto.
8199         (class vaeskf2_vsm3c):Ditto.
8200         (class vsm3me): Ditto.
8201         (BASE): Add BASE declaration for crypto vector.
8202         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
8203         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
8204                                 Add crypto vector intrinsic definition.
8205         (vbrev): Ditto.
8206         (vclz): Ditto.
8207         (vctz): Ditto.
8208         (vwsll): Ditto.
8209         (vandn): Ditto.
8210         (vbrev8): Ditto.
8211         (vrev8): Ditto.
8212         (vrol): Ditto.
8213         (vror): Ditto.
8214         (vclmul): Ditto.
8215         (vclmulh): Ditto.
8216         (vghsh): Ditto.
8217         (vgmul): Ditto.
8218         (vaesef): Ditto.
8219         (vaesem): Ditto.
8220         (vaesdf): Ditto.
8221         (vaesdm): Ditto.
8222         (vaesz): Ditto.
8223         (vaeskf1): Ditto.
8224         (vaeskf2): Ditto.
8225         (vsha2ms): Ditto.
8226         (vsha2ch): Ditto.
8227         (vsha2cl): Ditto.
8228         (vsm4k): Ditto.
8229         (vsm4r): Ditto.
8230         (vsm3me): Ditto.
8231         (vsm3c): Ditto.
8232         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
8233                                 Add new function_shape for crypto vector.
8234         (struct crypto_vi_def): Ditto.
8235         (struct crypto_vv_no_op_type_def): Ditto.
8236         (SHAPE): Add SHAPE declaration of crypto vector.
8237         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
8238         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
8239                                 Add new data type for crypto vector.
8240         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8241         (vuint32mf2_t): Ditto.
8242         (vuint32m1_t): Ditto.
8243         (vuint32m2_t): Ditto.
8244         (vuint32m4_t): Ditto.
8245         (vuint32m8_t): Ditto.
8246         (vuint64m1_t): Ditto.
8247         (vuint64m2_t): Ditto.
8248         (vuint64m4_t): Ditto.
8249         (vuint64m8_t): Ditto.
8250         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
8251                                 Add new data struct for crypto vector.
8252         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8253         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
8254         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
8255
8256 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
8257
8258         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
8259                                 Add new function_base for crypto vector.
8260         (class bitmanip): Ditto.
8261         (class b_reverse):Ditto.
8262         (class vwsll):   Ditto.
8263         (class clmul):   Ditto.
8264         (class vg_nhab):  Ditto.
8265         (class crypto_vv):Ditto.
8266         (class crypto_vi):Ditto.
8267         (class vaeskf2_vsm3c):Ditto.
8268         (class vsm3me): Ditto.
8269         (BASE): Add BASE declaration for crypto vector.
8270         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
8271         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
8272                                 Add crypto vector intrinsic definition.
8273         (vbrev): Ditto.
8274         (vclz): Ditto.
8275         (vctz): Ditto.
8276         (vwsll): Ditto.
8277         (vandn): Ditto.
8278         (vbrev8): Ditto.
8279         (vrev8): Ditto.
8280         (vrol): Ditto.
8281         (vror): Ditto.
8282         (vclmul): Ditto.
8283         (vclmulh): Ditto.
8284         (vghsh): Ditto.
8285         (vgmul): Ditto.
8286         (vaesef): Ditto.
8287         (vaesem): Ditto.
8288         (vaesdf): Ditto.
8289         (vaesdm): Ditto.
8290         (vaesz): Ditto.
8291         (vaeskf1): Ditto.
8292         (vaeskf2): Ditto.
8293         (vsha2ms): Ditto.
8294         (vsha2ch): Ditto.
8295         (vsha2cl): Ditto.
8296         (vsm4k): Ditto.
8297         (vsm4r): Ditto.
8298         (vsm3me): Ditto.
8299         (vsm3c): Ditto.
8300         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
8301                                 Add new function_shape for crypto vector.
8302         (struct crypto_vi_def): Ditto.
8303         (struct crypto_vv_no_op_type_def): Ditto.
8304         (SHAPE): Add SHAPE declaration of crypto vector.
8305         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
8306         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
8307                                 Add new data type for crypto vector.
8308         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8309         (vuint32mf2_t): Ditto.
8310         (vuint32m1_t): Ditto.
8311         (vuint32m2_t): Ditto.
8312         (vuint32m4_t): Ditto.
8313         (vuint32m8_t): Ditto.
8314         (vuint64m1_t): Ditto.
8315         (vuint64m2_t): Ditto.
8316         (vuint64m4_t): Ditto.
8317         (vuint64m8_t): Ditto.
8318         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
8319                                 Add new data struct for crypto vector.
8320         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8321         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
8322         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
8323
8324 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8325
8326         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
8327
8328 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
8329
8330         PR tree-optimization/113186
8331         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
8332         Match `^` with the `==` for 1bit integral types.
8333         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
8334         integral types.
8335
8336 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
8337
8338         * toplev.cc (general_init): Pass lang_mask to urlifier.
8339
8340 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
8341
8342         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
8343         param.
8344         (diagnostic_context::make_option_url): Update for lang_mask param.
8345         * gcc-urlifier.cc: Include "opts.h" and "options.h".
8346         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
8347         (gcc_urlifier::m_lang_mask): New field.
8348         (doc_urls): Make static.
8349         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
8350         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
8351         Look for an option by name before trying a binary search in
8352         doc_urls.
8353         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
8354         (gcc_urlifier::get_url_suffix_for_option): New.
8355         (make_gcc_urlifier): Add lang_mask param.
8356         (selftest::gcc_urlifier_cc_tests): Update for above changes.
8357         Verify that a URL is found for "-fpack-struct".
8358         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
8359         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
8360         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
8361         to make_gcc_urlifier.
8362         * opts-diagnostic.h (get_option_url): Add lang_mask param.
8363         * opts.cc (get_option_html_page): Remove special-casing for
8364         analyzer and LTO.
8365         (get_option_url_suffix): New.
8366         (get_option_url): Reimplement.
8367         (selftest::test_get_option_html_page): Rename to...
8368         (selftest::test_get_option_url_suffix): ...this and update for
8369         above changes.
8370         (selftest::opts_cc_tests): Update for renaming.
8371         * opts.h: Include "rich-location.h".
8372         (get_option_url_suffix): New decl.
8373
8374 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
8375
8376         * Makefile.in (ALL_OPT_URL_FILES): New.
8377         (GCC_OBJS): Add options-urls.o.
8378         (OBJS): Likewise.
8379         (OBJS-libcommon): Likewise.
8380         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
8381         inputs to opt-gather.awk.
8382         (options-urls.cc): New Makefile target.
8383         * opt-functions.awk (url_suffix): New function.
8384         (lang_url_suffix): New function.
8385         * options-urls-cc-gen.awk: New file.
8386         * opts.h (get_opt_url_suffix): New decl.
8387
8388 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
8389
8390         * params.opt.urls: New file, autogenerated by
8391         regenerate-opt-urls.py.
8392
8393 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
8394
8395         * common.opt.urls: New file, autogenerated by
8396         regenerate-opt-urls.py.
8397         * config/aarch64/aarch64.opt.urls: Likewise.
8398         * config/alpha/alpha.opt.urls: Likewise.
8399         * config/alpha/elf.opt.urls: Likewise.
8400         * config/arc/arc-tables.opt.urls: Likewise.
8401         * config/arc/arc.opt.urls: Likewise.
8402         * config/arm/arm-tables.opt.urls: Likewise.
8403         * config/arm/arm.opt.urls: Likewise.
8404         * config/arm/vxworks.opt.urls: Likewise.
8405         * config/avr/avr.opt.urls: Likewise.
8406         * config/bpf/bpf.opt.urls: Likewise.
8407         * config/c6x/c6x-tables.opt.urls: Likewise.
8408         * config/c6x/c6x.opt.urls: Likewise.
8409         * config/cris/cris.opt.urls: Likewise.
8410         * config/cris/elf.opt.urls: Likewise.
8411         * config/csky/csky.opt.urls: Likewise.
8412         * config/csky/csky_tables.opt.urls: Likewise.
8413         * config/darwin.opt.urls: Likewise.
8414         * config/dragonfly.opt.urls: Likewise.
8415         * config/epiphany/epiphany.opt.urls: Likewise.
8416         * config/fr30/fr30.opt.urls: Likewise.
8417         * config/freebsd.opt.urls: Likewise.
8418         * config/frv/frv.opt.urls: Likewise.
8419         * config/ft32/ft32.opt.urls: Likewise.
8420         * config/fused-madd.opt.urls: Likewise.
8421         * config/g.opt.urls: Likewise.
8422         * config/gcn/gcn.opt.urls: Likewise.
8423         * config/gnu-user.opt.urls: Likewise.
8424         * config/h8300/h8300.opt.urls: Likewise.
8425         * config/hpux11.opt.urls: Likewise.
8426         * config/i386/cygming.opt.urls: Likewise.
8427         * config/i386/cygwin.opt.urls: Likewise.
8428         * config/i386/djgpp.opt.urls: Likewise.
8429         * config/i386/i386.opt.urls: Likewise.
8430         * config/i386/mingw-w64.opt.urls: Likewise.
8431         * config/i386/mingw.opt.urls: Likewise.
8432         * config/i386/nto.opt.urls: Likewise.
8433         * config/ia64/ia64.opt.urls: Likewise.
8434         * config/ia64/ilp32.opt.urls: Likewise.
8435         * config/ia64/vms.opt.urls: Likewise.
8436         * config/iq2000/iq2000.opt.urls: Likewise.
8437         * config/linux-android.opt.urls: Likewise.
8438         * config/linux.opt.urls: Likewise.
8439         * config/lm32/lm32.opt.urls: Likewise.
8440         * config/loongarch/loongarch.opt.urls: Likewise.
8441         * config/lynx.opt.urls: Likewise.
8442         * config/m32c/m32c.opt.urls: Likewise.
8443         * config/m32r/m32r.opt.urls: Likewise.
8444         * config/m68k/ieee.opt.urls: Likewise.
8445         * config/m68k/m68k-tables.opt.urls: Likewise.
8446         * config/m68k/m68k.opt.urls: Likewise.
8447         * config/m68k/uclinux.opt.urls: Likewise.
8448         * config/mcore/mcore.opt.urls: Likewise.
8449         * config/microblaze/microblaze.opt.urls: Likewise.
8450         * config/mips/mips-tables.opt.urls: Likewise.
8451         * config/mips/mips.opt.urls: Likewise.
8452         * config/mips/sde.opt.urls: Likewise.
8453         * config/mmix/mmix.opt.urls: Likewise.
8454         * config/mn10300/mn10300.opt.urls: Likewise.
8455         * config/moxie/moxie.opt.urls: Likewise.
8456         * config/msp430/msp430.opt.urls: Likewise.
8457         * config/nds32/nds32-elf.opt.urls: Likewise.
8458         * config/nds32/nds32-linux.opt.urls: Likewise.
8459         * config/nds32/nds32.opt.urls: Likewise.
8460         * config/netbsd-elf.opt.urls: Likewise.
8461         * config/netbsd.opt.urls: Likewise.
8462         * config/nios2/elf.opt.urls: Likewise.
8463         * config/nios2/nios2.opt.urls: Likewise.
8464         * config/nvptx/nvptx-gen.opt.urls: Likewise.
8465         * config/nvptx/nvptx.opt.urls: Likewise.
8466         * config/openbsd.opt.urls: Likewise.
8467         * config/or1k/elf.opt.urls: Likewise.
8468         * config/or1k/or1k.opt.urls: Likewise.
8469         * config/pa/pa-hpux.opt.urls: Likewise.
8470         * config/pa/pa-hpux1010.opt.urls: Likewise.
8471         * config/pa/pa-hpux1111.opt.urls: Likewise.
8472         * config/pa/pa-hpux1131.opt.urls: Likewise.
8473         * config/pa/pa.opt.urls: Likewise.
8474         * config/pa/pa64-hpux.opt.urls: Likewise.
8475         * config/pdp11/pdp11.opt.urls: Likewise.
8476         * config/pru/pru.opt.urls: Likewise.
8477         * config/riscv/riscv.opt.urls: Likewise.
8478         * config/rl78/rl78.opt.urls: Likewise.
8479         * config/rpath.opt.urls: Likewise.
8480         * config/rs6000/476.opt.urls: Likewise.
8481         * config/rs6000/aix64.opt.urls: Likewise.
8482         * config/rs6000/darwin.opt.urls: Likewise.
8483         * config/rs6000/linux64.opt.urls: Likewise.
8484         * config/rs6000/rs6000-tables.opt.urls: Likewise.
8485         * config/rs6000/rs6000.opt.urls: Likewise.
8486         * config/rs6000/sysv4.opt.urls: Likewise.
8487         * config/rtems.opt.urls: Likewise.
8488         * config/rx/elf.opt.urls: Likewise.
8489         * config/rx/rx.opt.urls: Likewise.
8490         * config/s390/s390.opt.urls: Likewise.
8491         * config/s390/tpf.opt.urls: Likewise.
8492         * config/sh/sh.opt.urls: Likewise.
8493         * config/sh/superh.opt.urls: Likewise.
8494         * config/sol2.opt.urls: Likewise.
8495         * config/sparc/long-double-switch.opt.urls: Likewise.
8496         * config/sparc/sparc.opt.urls: Likewise.
8497         * config/stormy16/stormy16.opt.urls: Likewise.
8498         * config/v850/v850.opt.urls: Likewise.
8499         * config/vax/elf.opt.urls: Likewise.
8500         * config/vax/vax.opt.urls: Likewise.
8501         * config/visium/visium.opt.urls: Likewise.
8502         * config/vms/vms.opt.urls: Likewise.
8503         * config/vxworks-smp.opt.urls: Likewise.
8504         * config/vxworks.opt.urls: Likewise.
8505         * config/xtensa/elf.opt.urls: Likewise.
8506         * config/xtensa/uclinux.opt.urls: Likewise.
8507         * config/xtensa/xtensa.opt.urls: Likewise.
8508         * config/bfin/bfin.opt.urls: New file.
8509
8510 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
8511
8512         * Makefile.in (OPT_URLS_HTML_DEPS): New.
8513         (regenerate-opt-urls): New target.
8514         (regenerate-opt-urls-unit-test): New target.
8515         * doc/options.texi (Option properties): Add UrlSuffix and
8516         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
8517         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
8518         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
8519         and Makefile.in's OPT_URLS_HTML_DEPS.
8520         (Anatomy of a Target Back End): Add
8521         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
8522         * regenerate-opt-urls.py: New file.
8523
8524 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
8525
8526         * diagnostic-format-sarif.cc
8527         (sarif_builder::make_logical_location_object): Convert to...
8528         (make_sarif_logical_location_object): ...this.
8529         (sarif_builder::set_any_logical_locs_arr): Update for above
8530         change.
8531         (sarif_builder::make_thread_flow_location_object): Call
8532         maybe_add_sarif_properties on each diagnostic_event.
8533         * diagnostic-format-sarif.h (class logical_location): New forward
8534         decl.
8535         (make_sarif_logical_location_object): New decl.
8536         * diagnostic-path.h (class sarif_object): New forward decl.
8537         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
8538
8539 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
8540             Patrick Lin  <patrick@andestech.com>
8541             Rufus Chen  <rufus@andestech.com>
8542             Monk Chiang  <monk.chiang@sifive.com>
8543
8544         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
8545         with Nan-boxing value.
8546         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
8547
8548 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
8549             Jeff Law  <jlaw@ventanamicro.com>
8550
8551         PR rtl-optimization/104914
8552         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
8553         a sign or zero extension is only required if the modified field
8554         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
8555         targets, don't refer to the temporarily incorrectly extended value
8556         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
8557
8558 2024-01-04  Pan Li  <pan2.li@intel.com>
8559
8560         Revert:
8561         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8562
8563         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
8564
8565 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8566
8567         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
8568
8569 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
8570
8571         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
8572         offset of fcsr.
8573
8574 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8575
8576         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
8577         (compute_nregs_for_mode): Refine LMUL.
8578         (max_number_of_live_regs): Ditto.
8579         (compute_estimated_lmul): Ditto.
8580         (has_unexpected_spills_p): Ditto.
8581
8582 2024-01-04  Li Wei  <liwei@loongson.cn>
8583
8584         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
8585         Remove useless forward declaration.
8586         (loongarch_is_even_extraction): Remove useless forward declaration.
8587         (loongarch_try_expand_lsx_vshuf_const): Removed.
8588         (loongarch_expand_vec_perm_const_1): Merged.
8589         (loongarch_is_double_duplicate): Removed.
8590         (loongarch_is_center_extraction): Ditto.
8591         (loongarch_is_reversing_permutation): Ditto.
8592         (loongarch_is_di_misalign_extract): Ditto.
8593         (loongarch_is_si_misalign_extract): Ditto.
8594         (loongarch_is_lasx_lowpart_extract): Ditto.
8595         (loongarch_is_op_reverse_perm): Ditto.
8596         (loongarch_is_single_op_perm): Ditto.
8597         (loongarch_is_divisible_perm): Ditto.
8598         (loongarch_is_triple_stride_extract): Ditto.
8599         (loongarch_expand_vec_perm_const_2): Merged.
8600         (loongarch_expand_vec_perm_const): New.
8601         (loongarch_vectorize_vec_perm_const): Adjust.
8602
8603 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
8604
8605         * omp-general.cc: Fix comment typos and misplaced/confusing
8606         comments.  Delete redundant include of omp-general.h.
8607
8608 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
8609
8610         PR rtl-optimization/104914
8611         * config/mips/mips.md (insqisi_extended): New patterns.
8612         (inshisi_extended): Ditto.
8613
8614 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
8615
8616         * config/mips/mips.cc (mips_insn_cost): New function.
8617
8618 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
8619
8620         * config/mips/mips.md (perf_ratio): New attribute.
8621
8622 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8623
8624         PR target/113206
8625         PR target/113209
8626         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
8627         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
8628         blocks belong to infinite loop.
8629         (pre_vsetvl::emit_vsetvl): Remove fake edges.
8630         * config/riscv/t-riscv: Add a new include file.
8631
8632 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8633
8634         * config/riscv/vector.md: Fix indent.
8635
8636 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
8637
8638         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
8639         OMP_CLAUSE__SIMDUID_.
8640         * tree.cc (omp_clause_num_ops): Update position of entry for
8641         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
8642         (omp_clause_code_name): Likewise.
8643
8644 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
8645
8646         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
8647         printing of FUNC_MAP/IND_FUNC_MAP labels.
8648
8649 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
8650
8651         * gcc.cc (process_command): Update copyright notice dates.
8652         * gcov-dump.cc (print_version): Ditto.
8653         * gcov.cc (print_version): Ditto.
8654         * gcov-tool.cc (print_version): Ditto.
8655         * gengtype.cc (create_file): Ditto.
8656         * doc/cpp.texi: Bump @copying's copyright year.
8657         * doc/cppinternals.texi: Ditto.
8658         * doc/gcc.texi: Ditto.
8659         * doc/gccint.texi: Ditto.
8660         * doc/gcov.texi: Ditto.
8661         * doc/install.texi: Ditto.
8662         * doc/invoke.texi: Ditto.
8663
8664 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
8665
8666         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
8667         (fmin<mode>3): Likewise.
8668         (reduc_fmax_scal_<mode>3): New define_expand.
8669         (reduc_fmin_scal_<mode>3): Likewise.
8670
8671 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8672
8673         PR target/113112
8674         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
8675         (max_number_of_live_regs): Ditto.
8676         (has_unexpected_spills_p): Ditto.
8677
8678 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
8679             Jin Ma  <jinma@linux.alibaba.com>
8680             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
8681             Christoph Müllner  <christoph.muellner@vrull.eu>
8682
8683         * config/riscv/vector.md:
8684         Use vector_length_operand for vsetvl patterns.
8685
8686 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8687
8688         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
8689         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
8690
8691 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
8692
8693         * config/aarch64/aarch64-tuning-flags.def
8694         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
8695         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
8696         * config/aarch64/aarch64.cc
8697         (aarch64_override_options_internal): Set
8698         param_fully_pipelined_fma according to tuning option.
8699         * config/aarch64/tuning_models/ampere1.h: Add
8700         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
8701         * config/aarch64/tuning_models/ampere1a.h: Likewise.
8702         * config/aarch64/tuning_models/ampere1b.h: Likewise.
8703
8704 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
8705
8706         * config/riscv/vector-crypto.md: Modify copyright year.
8707
8708 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8709
8710         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
8711
8712 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
8713
8714         * config.in: Regenerate.
8715         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
8716         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
8717         Added TLS Le Relax support.
8718         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
8719         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
8720         * configure: Regenerate.
8721         * configure.ac: Check if binutils supports TLS le relax.
8722
8723 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
8724
8725         * config/riscv/iterators.md: Add rotate insn name.
8726         * config/riscv/riscv.md: Add new insns name for crypto vector.
8727         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
8728         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
8729         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
8730
8731 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
8732
8733         PR target/113112
8734         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
8735         pointer type liveness count.
8736 \f
8737 Copyright (C) 2024 Free Software Foundation, Inc.
8738
8739 Copying and distribution of this file, with or without modification,
8740 are permitted in any medium without royalty provided the copyright
8741 notice and this notice are preserved.