2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
80 #define OPTION_MASK_ISA_AVX512VBMI_SET \
81 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
82 #define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
83 #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
84 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
85 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
86 #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
87 #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
88 #define OPTION_MASK_ISA_AVX512VNNI_SET \
89 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
90 #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
91 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
92 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
93 #define OPTION_MASK_ISA_AVX512BITALG_SET \
94 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
95 #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
96 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
97 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
98 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
99 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
100 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
101 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
102 #define OPTION_MASK_ISA_XSAVES_SET \
103 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
104 #define OPTION_MASK_ISA_XSAVEC_SET \
105 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
106 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
107 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
108 #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
109 #define OPTION_MASK_ISA2_AMX_INT8_SET \
110 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
111 #define OPTION_MASK_ISA2_AMX_BF16_SET \
112 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
113 #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
114 #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
115 #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
116 #define OPTION_MASK_ISA2_AMX_FP16_SET \
117 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
118 #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
119 #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
120 #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
121 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
122 #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
123 #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
124 #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
125 #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
126 #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
127 #define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
128 #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
129 #define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
130 #define OPTION_MASK_ISA2_AVX10_1_512_SET \
131 (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
133 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
135 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
137 #define OPTION_MASK_ISA_SSE4A_SET \
138 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
139 #define OPTION_MASK_ISA_FMA4_SET \
140 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
141 | OPTION_MASK_ISA_AVX_SET)
142 #define OPTION_MASK_ISA_XOP_SET \
143 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
144 #define OPTION_MASK_ISA_LWP_SET \
147 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
148 #define OPTION_MASK_ISA_AES_SET \
149 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
150 #define OPTION_MASK_ISA_SHA_SET \
151 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
152 #define OPTION_MASK_ISA_PCLMUL_SET \
153 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
155 #define OPTION_MASK_ISA_ABM_SET \
156 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
158 #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
159 #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
160 #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
161 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
162 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
163 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
164 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
165 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
166 #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
167 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
168 #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
169 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
171 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
172 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
173 #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
174 #define OPTION_MASK_ISA_F16C_SET \
175 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
176 #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
177 #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
178 #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
179 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
180 #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
181 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
182 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
183 #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
184 #define OPTION_MASK_ISA_VPCLMULQDQ_SET \
185 (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
186 | OPTION_MASK_ISA_AVX_SET)
187 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
188 #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
189 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
190 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
191 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
192 #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
193 #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
194 #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
195 #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
196 #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
197 #define OPTION_MASK_ISA2_WIDEKL_SET \
198 (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
200 /* Define a set of ISAs which aren't available when a given ISA is
201 disabled. MMX and SSE ISAs are handled separately. */
203 #define OPTION_MASK_ISA_MMX_UNSET \
204 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
205 #define OPTION_MASK_ISA_3DNOW_UNSET \
206 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
207 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
209 #define OPTION_MASK_ISA_SSE_UNSET \
210 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
211 #define OPTION_MASK_ISA_SSE2_UNSET \
212 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
213 #define OPTION_MASK_ISA_SSE3_UNSET \
214 (OPTION_MASK_ISA_SSE3 \
215 | OPTION_MASK_ISA_SSSE3_UNSET \
216 | OPTION_MASK_ISA_SSE4A_UNSET )
217 #define OPTION_MASK_ISA_SSSE3_UNSET \
218 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
219 #define OPTION_MASK_ISA_SSE4_1_UNSET \
220 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
221 #define OPTION_MASK_ISA_SSE4_2_UNSET \
222 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
223 #define OPTION_MASK_ISA_AVX_UNSET \
224 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
225 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
226 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
227 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
228 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
229 #define OPTION_MASK_ISA_XSAVE_UNSET \
230 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
231 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
232 | OPTION_MASK_ISA_AVX_UNSET)
233 #define OPTION_MASK_ISA2_XSAVE_UNSET \
234 (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
235 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
236 #define OPTION_MASK_ISA_AVX2_UNSET \
237 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
238 #define OPTION_MASK_ISA2_AVX2_UNSET \
239 (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
240 | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
241 | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
242 | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
243 #define OPTION_MASK_ISA_AVX512F_UNSET \
244 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
245 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
246 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
247 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
248 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
249 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
250 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
251 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
252 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
253 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
254 #define OPTION_MASK_ISA_AVX512BW_UNSET \
255 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
256 | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
257 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
258 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
259 #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
260 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
261 #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
262 #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
263 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
264 #define OPTION_MASK_ISA_AVX512FP16_UNSET OPTION_MASK_ISA_AVX512BW_UNSET
265 #define OPTION_MASK_ISA2_AVX512FP16_UNSET OPTION_MASK_ISA2_AVX512FP16
266 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
267 #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
268 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
269 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
270 #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
271 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
272 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
273 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
274 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
275 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
276 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
277 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
278 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
279 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
280 #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
281 #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
282 #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
283 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
284 #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
285 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
286 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
287 #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
288 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
289 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
290 #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
291 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
292 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
293 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
294 #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
295 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
296 #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
297 #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
298 (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
299 | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
300 | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET)
301 #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
302 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
303 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
304 #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
305 #define OPTION_MASK_ISA2_KL_UNSET \
306 (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
307 #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
308 #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
309 #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
310 #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
311 #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
312 #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
313 #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
314 #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
315 #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
316 #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
317 #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
318 #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
319 #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
320 #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
321 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
322 #define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
323 (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET)
324 #define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512
326 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
328 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
330 #define OPTION_MASK_ISA_SSE4A_UNSET \
331 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
333 #define OPTION_MASK_ISA_FMA4_UNSET \
334 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
335 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
336 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
338 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
339 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
340 #define OPTION_MASK_ISA_PCLMUL_UNSET \
341 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
342 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
343 #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
344 #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
345 #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
346 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
347 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
348 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
349 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
350 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
351 #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
352 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
353 #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
354 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
356 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
357 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
358 #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
359 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
361 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
362 (OPTION_MASK_ISA_MMX_UNSET \
363 | OPTION_MASK_ISA_SSE_UNSET)
365 #define OPTION_MASK_ISA2_AVX512F_UNSET \
366 (OPTION_MASK_ISA2_AVX512BW_UNSET \
367 | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
368 | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
369 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
370 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
371 OPTION_MASK_ISA2_SSE_UNSET
372 #define OPTION_MASK_ISA2_AVX_UNSET \
373 (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
374 | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
375 | OPTION_MASK_ISA2_SM4_UNSET)
376 #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
377 #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
378 #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
379 #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
380 #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
381 #define OPTION_MASK_ISA2_SSE2_UNSET \
382 (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
383 #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
385 #define OPTION_MASK_ISA2_AVX512BW_UNSET \
386 (OPTION_MASK_ISA2_AVX512BF16_UNSET \
387 | OPTION_MASK_ISA2_AVX512FP16_UNSET)
389 /* Set 1 << value as value of -malign-FLAG option. */
392 set_malign_value (const char **flag
, unsigned value
)
394 char *r
= XNEWVEC (char, 6);
395 sprintf (r
, "%d", 1 << value
);
399 /* Implement TARGET_HANDLE_OPTION. */
402 ix86_handle_option (struct gcc_options
*opts
,
403 struct gcc_options
*opts_set ATTRIBUTE_UNUSED
,
404 const struct cl_decoded_option
*decoded
,
407 size_t code
= decoded
->opt_index
;
408 int value
= decoded
->value
;
412 case OPT_mgeneral_regs_only
:
415 HOST_WIDE_INT general_regs_only_flags
= 0;
416 HOST_WIDE_INT general_regs_only_flags2
= 0;
418 /* NB: Enable the GPR only instructions which are enabled
419 implicitly by SSE ISAs unless they have been disabled
421 if (TARGET_SSE4_2_P (opts
->x_ix86_isa_flags
))
423 if (!TARGET_EXPLICIT_CRC32_P (opts
))
424 general_regs_only_flags
|= OPTION_MASK_ISA_CRC32
;
425 if (!TARGET_EXPLICIT_POPCNT_P (opts
))
426 general_regs_only_flags
|= OPTION_MASK_ISA_POPCNT
;
428 if (TARGET_SSE3_P (opts
->x_ix86_isa_flags
))
430 if (!TARGET_EXPLICIT_MWAIT_P (opts
))
431 general_regs_only_flags2
|= OPTION_MASK_ISA2_MWAIT
;
434 /* Disable MMX, SSE and x87 instructions if only
435 general registers are allowed. */
436 opts
->x_ix86_isa_flags
437 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
;
438 opts
->x_ix86_isa_flags2
439 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
;
440 opts
->x_ix86_isa_flags
|= general_regs_only_flags
;
441 opts
->x_ix86_isa_flags2
|= general_regs_only_flags2
;
442 opts
->x_ix86_isa_flags_explicit
443 |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
444 | general_regs_only_flags
);
445 opts
->x_ix86_isa_flags2_explicit
446 |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
447 | general_regs_only_flags2
);
449 opts
->x_target_flags
&= ~MASK_80387
;
458 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_MMX_SET
;
459 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MMX_SET
;
463 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_MMX_UNSET
;
464 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MMX_UNSET
;
471 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_3DNOW_SET
;
472 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_SET
;
476 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_3DNOW_UNSET
;
477 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_UNSET
;
484 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_3DNOW_A_SET
;
485 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_A_SET
;
489 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_3DNOW_A_UNSET
;
490 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_A_UNSET
;
497 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE_SET
;
498 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE_SET
;
502 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE_UNSET
;
503 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE_UNSET
;
504 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SSE_UNSET
;
505 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SSE_UNSET
;
512 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE2_SET
;
513 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE2_SET
;
517 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE2_UNSET
;
518 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE2_UNSET
;
519 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SSE2_UNSET
;
520 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SSE2_UNSET
;
527 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE3_SET
;
528 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE3_SET
;
532 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE3_UNSET
;
533 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE3_UNSET
;
534 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SSE3_UNSET
;
535 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SSE3_UNSET
;
542 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSSE3_SET
;
543 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSSE3_SET
;
547 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSSE3_UNSET
;
548 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSSE3_UNSET
;
549 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SSSE3_UNSET
;
550 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SSSE3_UNSET
;
557 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4_1_SET
;
558 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_1_SET
;
562 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4_1_UNSET
;
563 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_1_UNSET
;
564 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SSE4_1_UNSET
;
565 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SSE4_1_UNSET
;
572 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4_2_SET
;
573 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_2_SET
;
577 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4_2_UNSET
;
578 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_2_UNSET
;
579 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SSE4_2_UNSET
;
580 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SSE4_2_UNSET
;
587 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX_SET
;
588 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_SET
;
592 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX_UNSET
;
593 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_UNSET
;
594 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX_UNSET
;
595 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX_UNSET
;
602 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
603 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
607 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX2_UNSET
;
608 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_UNSET
;
609 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX2_UNSET
;
610 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX2_UNSET
;
617 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512F_SET
;
618 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_SET
;
622 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512F_UNSET
;
623 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_UNSET
;
624 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
625 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
626 opts
->x_ix86_no_avx512_explicit
= 1;
633 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512CD_SET
;
634 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512CD_SET
;
638 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512CD_UNSET
;
639 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512CD_UNSET
;
640 opts
->x_ix86_no_avx512_explicit
= 1;
647 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512PF_SET
;
648 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512PF_SET
;
652 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512PF_UNSET
;
653 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512PF_UNSET
;
660 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512ER_SET
;
661 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512ER_SET
;
665 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512ER_UNSET
;
666 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512ER_UNSET
;
673 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_RDPID_SET
;
674 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_RDPID_SET
;
678 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_RDPID_UNSET
;
679 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_RDPID_UNSET
;
686 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_GFNI_SET
;
687 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_GFNI_SET
;
691 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_GFNI_UNSET
;
692 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_GFNI_UNSET
;
699 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SHSTK_SET
;
700 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHSTK_SET
;
704 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SHSTK_UNSET
;
705 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHSTK_UNSET
;
712 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_VAES_SET
;
713 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_VAES_SET
;
714 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX_SET
;
715 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_SET
;
719 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_VAES_UNSET
;
720 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_VAES_UNSET
;
724 case OPT_mvpclmulqdq
:
727 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_VPCLMULQDQ_SET
;
728 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_VPCLMULQDQ_SET
;
732 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET
;
733 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_VPCLMULQDQ_UNSET
;
740 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_MOVDIRI_SET
;
741 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MOVDIRI_SET
;
745 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_MOVDIRI_UNSET
;
746 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MOVDIRI_UNSET
;
753 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_MOVDIR64B_SET
;
754 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MOVDIR64B_SET
;
758 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET
;
759 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MOVDIR64B_UNSET
;
766 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_CLDEMOTE_SET
;
767 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CLDEMOTE_SET
;
771 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET
;
772 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CLDEMOTE_UNSET
;
779 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_WAITPKG_SET
;
780 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_WAITPKG_SET
;
784 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_WAITPKG_UNSET
;
785 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_WAITPKG_UNSET
;
792 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_ENQCMD_SET
;
793 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_ENQCMD_SET
;
797 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_ENQCMD_UNSET
;
798 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_ENQCMD_UNSET
;
805 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_KL_SET
;
806 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_KL_SET
;
808 /* The Keylocker instructions need XMM registers from SSE2. */
809 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE2_SET
;
810 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE2_SET
;
814 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_KL_UNSET
;
815 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_KL_UNSET
;
822 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_WIDEKL_SET
;
823 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_WIDEKL_SET
;
825 /* The Widekl instructions need XMM registers from SSE2. */
826 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE2_SET
;
827 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE2_SET
;
831 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_WIDEKL_UNSET
;
832 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_WIDEKL_UNSET
;
839 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_SERIALIZE_SET
;
840 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SERIALIZE_SET
;
844 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SERIALIZE_UNSET
;
845 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SERIALIZE_UNSET
;
852 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_UINTR_SET
;
853 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_UINTR_SET
;
857 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_UINTR_UNSET
;
858 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_UINTR_UNSET
;
865 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_HRESET_SET
;
866 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_HRESET_SET
;
870 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_HRESET_UNSET
;
871 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_HRESET_UNSET
;
875 case OPT_mavx5124fmaps
:
878 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVX5124FMAPS_SET
;
879 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX5124FMAPS_SET
;
880 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512F_SET
;
881 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_SET
;
885 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET
;
886 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET
;
890 case OPT_mavx5124vnniw
:
893 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVX5124VNNIW_SET
;
894 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX5124VNNIW_SET
;
895 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512F_SET
;
896 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_SET
;
900 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET
;
901 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET
;
905 case OPT_mavx512vbmi2
:
908 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VBMI2_SET
;
909 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI2_SET
;
913 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET
;
914 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI2_UNSET
;
915 opts
->x_ix86_no_avx512_explicit
= 1;
919 case OPT_mavx512fp16
:
922 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVX512FP16_SET
;
923 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512FP16_SET
;
924 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512FP16_SET
;
925 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512FP16_SET
;
929 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512FP16_UNSET
;
930 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512FP16_UNSET
;
931 opts
->x_ix86_no_avx512_explicit
= 1;
935 case OPT_mavx512vnni
:
938 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VNNI_SET
;
939 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VNNI_SET
;
943 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VNNI_UNSET
;
944 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VNNI_UNSET
;
945 opts
->x_ix86_no_avx512_explicit
= 1;
949 case OPT_mavx512vpopcntdq
:
952 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET
;
953 opts
->x_ix86_isa_flags_explicit
954 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET
;
958 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET
;
959 opts
->x_ix86_isa_flags_explicit
960 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET
;
961 opts
->x_ix86_no_avx512_explicit
= 1;
965 case OPT_mavx512bitalg
:
968 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512BITALG_SET
;
969 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BITALG_SET
;
973 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512BITALG_UNSET
;
974 opts
->x_ix86_isa_flags_explicit
975 |= OPTION_MASK_ISA_AVX512BITALG_UNSET
;
976 opts
->x_ix86_no_avx512_explicit
= 1;
980 case OPT_mavx512bf16
:
983 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVX512BF16_SET
;
984 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512BF16_SET
;
985 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512BW_SET
;
986 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BW_SET
;
990 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512BF16_UNSET
;
991 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512BF16_UNSET
;
992 opts
->x_ix86_no_avx512_explicit
= 1;
999 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVXVNNI_SET
;
1000 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVXVNNI_SET
;
1001 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
1002 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
1006 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVXVNNI_UNSET
;
1007 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVXVNNI_UNSET
;
1014 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_SGX_SET
;
1015 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SGX_SET
;
1019 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SGX_UNSET
;
1020 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SGX_UNSET
;
1027 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_PCONFIG_SET
;
1028 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_PCONFIG_SET
;
1032 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_PCONFIG_UNSET
;
1033 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_PCONFIG_UNSET
;
1040 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_WBNOINVD_SET
;
1041 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_WBNOINVD_SET
;
1045 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_WBNOINVD_UNSET
;
1046 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_WBNOINVD_UNSET
;
1053 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512DQ_SET
;
1054 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512DQ_SET
;
1058 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512DQ_UNSET
;
1059 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512DQ_UNSET
;
1060 opts
->x_ix86_no_avx512_explicit
= 1;
1067 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512BW_SET
;
1068 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BW_SET
;
1072 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512BW_UNSET
;
1073 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BW_UNSET
;
1074 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512BW_UNSET
;
1075 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512BW_UNSET
;
1076 opts
->x_ix86_no_avx512_explicit
= 1;
1083 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VL_SET
;
1084 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VL_SET
;
1088 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VL_UNSET
;
1089 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VL_UNSET
;
1090 opts
->x_ix86_no_avx512_explicit
= 1;
1094 case OPT_mavx512ifma
:
1097 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512IFMA_SET
;
1098 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512IFMA_SET
;
1102 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512IFMA_UNSET
;
1103 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512IFMA_UNSET
;
1104 opts
->x_ix86_no_avx512_explicit
= 1;
1108 case OPT_mavx512vbmi
:
1111 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VBMI_SET
;
1112 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI_SET
;
1116 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VBMI_UNSET
;
1117 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI_UNSET
;
1118 opts
->x_ix86_no_avx512_explicit
= 1;
1122 case OPT_mavx512vp2intersect
:
1125 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET
;
1126 opts
->x_ix86_isa_flags2_explicit
|=
1127 OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET
;
1128 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512DQ_SET
;
1129 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512DQ_SET
;
1133 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET
;
1134 opts
->x_ix86_isa_flags2_explicit
|=
1135 OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET
;
1142 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_TSXLDTRK_SET
;
1143 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_TSXLDTRK_SET
;
1147 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET
;
1148 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_TSXLDTRK_UNSET
;
1155 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AMX_TILE_SET
;
1156 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_TILE_SET
;
1157 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVE_SET
;
1158 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVE_SET
;
1162 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AMX_TILE_UNSET
;
1163 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_TILE_UNSET
;
1170 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AMX_INT8_SET
;
1171 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_INT8_SET
;
1175 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AMX_INT8_UNSET
;
1176 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_INT8_UNSET
;
1183 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AMX_BF16_SET
;
1184 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_BF16_SET
;
1188 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AMX_BF16_UNSET
;
1189 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_BF16_UNSET
;
1196 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVXIFMA_SET
;
1197 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVXIFMA_SET
;
1198 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
1199 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
1203 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVXIFMA_UNSET
;
1204 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVXIFMA_UNSET
;
1208 case OPT_mavxvnniint8
:
1211 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVXVNNIINT8_SET
;
1212 opts
->x_ix86_isa_flags2_explicit
|=
1213 OPTION_MASK_ISA2_AVXVNNIINT8_SET
;
1214 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
1215 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
1219 opts
->x_ix86_isa_flags2
&=
1220 ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET
;
1221 opts
->x_ix86_isa_flags2_explicit
|=
1222 OPTION_MASK_ISA2_AVXVNNIINT8_UNSET
;
1226 case OPT_mavxneconvert
:
1229 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVXNECONVERT_SET
;
1230 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVXNECONVERT_SET
;
1231 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
1232 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
1236 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET
;
1237 opts
->x_ix86_isa_flags2_explicit
1238 |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET
;
1242 case OPT_mcmpccxadd
:
1245 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_CMPCCXADD_SET
;
1246 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CMPCCXADD_SET
;
1250 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET
;
1251 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CMPCCXADD_UNSET
;
1258 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AMX_FP16_SET
;
1259 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_FP16_SET
;
1263 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AMX_FP16_UNSET
;
1264 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_FP16_UNSET
;
1268 case OPT_mprefetchi
:
1271 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_PREFETCHI_SET
;
1272 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_PREFETCHI_SET
;
1276 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_PREFETCHI_UNSET
;
1277 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_PREFETCHI_UNSET
;
1284 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_RAOINT_SET
;
1285 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_RAOINT_SET
;
1289 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_RAOINT_UNSET
;
1290 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_RAOINT_UNSET
;
1294 case OPT_mamx_complex
:
1297 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AMX_COMPLEX_SET
;
1298 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_COMPLEX_SET
;
1302 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET
;
1303 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET
;
1307 case OPT_mavxvnniint16
:
1310 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVXVNNIINT16_SET
;
1311 opts
->x_ix86_isa_flags2_explicit
|=
1312 OPTION_MASK_ISA2_AVXVNNIINT16_SET
;
1313 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
1314 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
1318 opts
->x_ix86_isa_flags2
&=
1319 ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET
;
1320 opts
->x_ix86_isa_flags2_explicit
|=
1321 OPTION_MASK_ISA2_AVXVNNIINT16_UNSET
;
1328 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_SM3_SET
;
1329 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SM3_SET
;
1330 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX_SET
;
1331 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_SET
;
1335 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SM3_UNSET
;
1336 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SM3_UNSET
;
1343 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_SHA512_SET
;
1344 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SHA512_SET
;
1345 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX_SET
;
1346 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_SET
;
1350 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SHA512_UNSET
;
1351 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SHA512_UNSET
;
1358 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_SM4_SET
;
1359 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SM4_SET
;
1360 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX_SET
;
1361 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_SET
;
1365 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SM4_UNSET
;
1366 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SM4_UNSET
;
1373 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_APX_F_SET
;
1374 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_APX_F_SET
;
1375 opts
->x_ix86_apx_features
= apx_all
;
1379 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_APX_F_UNSET
;
1380 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_APX_F_UNSET
;
1381 opts
->x_ix86_apx_features
= apx_none
;
1388 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_EVEX512_SET
;
1389 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_EVEX512_SET
;
1393 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_EVEX512_UNSET
;
1394 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_EVEX512_UNSET
;
1395 opts
->x_ix86_no_avx512_explicit
= 1;
1402 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_USER_MSR_SET
;
1403 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_USER_MSR_SET
;
1407 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_USER_MSR_UNSET
;
1408 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_USER_MSR_UNSET
;
1412 case OPT_mavx10_1_256
:
1415 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVX10_1_256_SET
;
1416 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX10_1_256_SET
;
1417 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
1418 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
1422 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET
;
1423 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX10_1_256_UNSET
;
1424 opts
->x_ix86_no_avx10_1_explicit
= 1;
1428 case OPT_mavx10_1_512
:
1431 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_AVX10_1_512_SET
;
1432 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX10_1_512_SET
;
1433 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
1434 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
1438 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET
;
1439 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX10_1_512_UNSET
;
1440 opts
->x_ix86_no_avx10_1_explicit
= 1;
1447 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FMA_SET
;
1448 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA_SET
;
1452 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FMA_UNSET
;
1453 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA_UNSET
;
1460 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_RTM_SET
;
1461 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RTM_SET
;
1465 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_RTM_UNSET
;
1466 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RTM_UNSET
;
1471 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4_SET
;
1472 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_SET
;
1476 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4_UNSET
;
1477 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_UNSET
;
1478 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_SSE4_UNSET
;
1479 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_SSE4_UNSET
;
1485 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4A_SET
;
1486 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4A_SET
;
1490 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4A_UNSET
;
1491 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4A_UNSET
;
1498 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FMA4_SET
;
1499 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA4_SET
;
1503 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FMA4_UNSET
;
1504 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA4_UNSET
;
1511 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XOP_SET
;
1512 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XOP_SET
;
1516 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XOP_UNSET
;
1517 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XOP_UNSET
;
1524 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_LWP_SET
;
1525 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LWP_SET
;
1529 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_LWP_UNSET
;
1530 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LWP_UNSET
;
1537 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_ABM_SET
;
1538 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ABM_SET
;
1542 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_ABM_UNSET
;
1543 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ABM_UNSET
;
1550 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_BMI_SET
;
1551 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI_SET
;
1555 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_BMI_UNSET
;
1556 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI_UNSET
;
1563 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_BMI2_SET
;
1564 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI2_SET
;
1568 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_BMI2_UNSET
;
1569 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI2_UNSET
;
1576 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_LZCNT_SET
;
1577 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LZCNT_SET
;
1581 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_LZCNT_UNSET
;
1582 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LZCNT_UNSET
;
1589 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_TBM_SET
;
1590 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_TBM_SET
;
1594 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_TBM_UNSET
;
1595 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_TBM_UNSET
;
1602 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_POPCNT_SET
;
1603 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_POPCNT_SET
;
1607 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_POPCNT_UNSET
;
1608 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_POPCNT_UNSET
;
1615 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SAHF_SET
;
1616 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SAHF_SET
;
1620 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SAHF_UNSET
;
1621 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SAHF_UNSET
;
1628 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_CX16_SET
;
1629 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CX16_SET
;
1633 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_CX16_UNSET
;
1634 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CX16_UNSET
;
1641 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_MOVBE_SET
;
1642 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MOVBE_SET
;
1646 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_MOVBE_UNSET
;
1647 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MOVBE_UNSET
;
1654 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_CRC32_SET
;
1655 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CRC32_SET
;
1659 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_CRC32_UNSET
;
1660 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CRC32_UNSET
;
1667 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AES_SET
;
1668 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AES_SET
;
1672 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AES_UNSET
;
1673 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AES_UNSET
;
1680 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SHA_SET
;
1681 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHA_SET
;
1685 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SHA_UNSET
;
1686 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHA_UNSET
;
1693 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PCLMUL_SET
;
1694 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PCLMUL_SET
;
1698 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PCLMUL_UNSET
;
1699 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PCLMUL_UNSET
;
1706 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FSGSBASE_SET
;
1707 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FSGSBASE_SET
;
1711 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FSGSBASE_UNSET
;
1712 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FSGSBASE_UNSET
;
1719 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_RDRND_SET
;
1720 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDRND_SET
;
1724 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_RDRND_UNSET
;
1725 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDRND_UNSET
;
1732 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_PTWRITE_SET
;
1733 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_PTWRITE_SET
;
1737 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_PTWRITE_UNSET
;
1738 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_PTWRITE_UNSET
;
1745 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_F16C_SET
;
1746 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_F16C_SET
;
1750 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_F16C_UNSET
;
1751 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_F16C_UNSET
;
1758 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FXSR_SET
;
1759 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FXSR_SET
;
1763 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FXSR_UNSET
;
1764 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FXSR_UNSET
;
1771 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVE_SET
;
1772 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVE_SET
;
1776 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVE_UNSET
;
1777 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVE_UNSET
;
1778 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_XSAVE_UNSET
;
1779 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_XSAVE_UNSET
;
1786 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVEOPT_SET
;
1787 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEOPT_SET
;
1791 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVEOPT_UNSET
;
1792 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEOPT_UNSET
;
1799 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVEC_SET
;
1800 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEC_SET
;
1804 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVEC_UNSET
;
1805 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEC_UNSET
;
1812 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVES_SET
;
1813 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVES_SET
;
1817 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVES_UNSET
;
1818 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVES_UNSET
;
1825 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_RDSEED_SET
;
1826 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDSEED_SET
;
1830 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_RDSEED_UNSET
;
1831 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDSEED_UNSET
;
1838 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PRFCHW_SET
;
1839 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PRFCHW_SET
;
1843 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PRFCHW_UNSET
;
1844 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PRFCHW_UNSET
;
1851 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_ADX_SET
;
1852 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ADX_SET
;
1856 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_ADX_UNSET
;
1857 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ADX_UNSET
;
1861 case OPT_mprefetchwt1
:
1864 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PREFETCHWT1_SET
;
1865 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PREFETCHWT1_SET
;
1869 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET
;
1870 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PREFETCHWT1_UNSET
;
1874 case OPT_mclflushopt
:
1877 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_CLFLUSHOPT_SET
;
1878 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLFLUSHOPT_SET
;
1882 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET
;
1883 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLFLUSHOPT_UNSET
;
1890 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_CLWB_SET
;
1891 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLWB_SET
;
1895 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_CLWB_UNSET
;
1896 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLWB_UNSET
;
1903 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_MWAITX_SET
;
1904 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MWAITX_SET
;
1908 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_MWAITX_UNSET
;
1909 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MWAITX_UNSET
;
1916 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_MWAIT_SET
;
1917 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MWAIT_SET
;
1921 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_MWAIT_UNSET
;
1922 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_MWAIT_UNSET
;
1929 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA2_CLZERO_SET
;
1930 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CLZERO_SET
;
1934 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_CLZERO_UNSET
;
1935 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_CLZERO_UNSET
;
1942 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PKU_SET
;
1943 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PKU_SET
;
1947 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PKU_UNSET
;
1948 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PKU_UNSET
;
1953 case OPT_malign_loops_
:
1954 warning_at (loc
, 0, "%<-malign-loops%> is obsolete, "
1955 "use %<-falign-loops%>");
1956 if (value
> MAX_CODE_ALIGN
)
1957 error_at (loc
, "%<-malign-loops=%d%> is not between 0 and %d",
1958 value
, MAX_CODE_ALIGN
);
1960 set_malign_value (&opts
->x_str_align_loops
, value
);
1963 case OPT_malign_jumps_
:
1964 warning_at (loc
, 0, "%<-malign-jumps%> is obsolete, "
1965 "use %<-falign-jumps%>");
1966 if (value
> MAX_CODE_ALIGN
)
1967 error_at (loc
, "%<-malign-jumps=%d%> is not between 0 and %d",
1968 value
, MAX_CODE_ALIGN
);
1970 set_malign_value (&opts
->x_str_align_jumps
, value
);
1973 case OPT_malign_functions_
:
1975 "%<-malign-functions%> is obsolete, "
1976 "use %<-falign-functions%>");
1977 if (value
> MAX_CODE_ALIGN
)
1978 error_at (loc
, "%<-malign-functions=%d%> is not between 0 and %d",
1979 value
, MAX_CODE_ALIGN
);
1981 set_malign_value (&opts
->x_str_align_functions
, value
);
1984 case OPT_mbranch_cost_
:
1987 error_at (loc
, "%<-mbranch-cost=%d%> is not between 0 and 5", value
);
1988 opts
->x_ix86_branch_cost
= 5;
1997 static const struct default_options ix86_option_optimization_table
[] =
1999 /* Enable redundant extension instructions removal at -O2 and higher. */
2000 { OPT_LEVELS_2_PLUS
, OPT_free
, NULL
, 1 },
2001 /* Enable function splitting at -O2 and higher. */
2002 { OPT_LEVELS_2_PLUS
, OPT_freorder_blocks_and_partition
, NULL
, 1 },
2003 /* The STC algorithm produces the smallest code at -Os, for x86. */
2004 { OPT_LEVELS_2_PLUS
, OPT_freorder_blocks_algorithm_
, NULL
,
2005 REORDER_BLOCKS_ALGORITHM_STC
},
2007 /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
2008 loop unrolling at -O2. */
2009 { OPT_LEVELS_2_PLUS_SPEED_ONLY
, OPT_funroll_loops
, NULL
, 1 },
2010 { OPT_LEVELS_2_PLUS_SPEED_ONLY
, OPT_munroll_only_small_loops
, NULL
, 1 },
2011 /* Turns off -frename-registers and -fweb which are enabled by
2013 { OPT_LEVELS_ALL
, OPT_frename_registers
, NULL
, 0 },
2014 { OPT_LEVELS_ALL
, OPT_fweb
, NULL
, 0 },
2015 /* Turn off -fschedule-insns by default. It tends to make the
2016 problem with not enough registers even worse. */
2017 { OPT_LEVELS_ALL
, OPT_fschedule_insns
, NULL
, 0 },
2019 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2020 SUBTARGET_OPTIMIZATION_OPTIONS
,
2022 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
2025 /* Implement TARGET_OPTION_INIT_STRUCT. */
2028 ix86_option_init_struct (struct gcc_options
*opts
)
2031 /* The Darwin libraries never set errno, so we might as well
2032 avoid calling them when that's the only reason we would. */
2033 opts
->x_flag_errno_math
= 0;
2035 opts
->x_flag_pcc_struct_return
= 2;
2036 opts
->x_flag_asynchronous_unwind_tables
= 2;
2039 /* On the x86 -fsplit-stack and -fstack-protector both use the same
2040 field in the TCB, so they cannot be used together. */
2043 ix86_supports_split_stack (bool report
,
2044 struct gcc_options
*opts ATTRIBUTE_UNUSED
)
2046 #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
2047 if (!OPTION_GLIBC_P (opts
))
2051 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
2057 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
2058 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE
)
2061 error ("%<-fsplit-stack%> requires "
2062 "assembler support for CFI directives");
2070 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
2072 static enum unwind_info_type
2073 i386_except_unwind_info (struct gcc_options
*opts
)
2075 /* Honor the --enable-sjlj-exceptions configure switch. */
2076 #ifdef CONFIG_SJLJ_EXCEPTIONS
2077 if (CONFIG_SJLJ_EXCEPTIONS
)
2081 /* On windows 64, prefer SEH exceptions over anything else. */
2082 if (TARGET_64BIT
&& DEFAULT_ABI
== MS_ABI
&& opts
->x_flag_unwind_tables
)
2085 if (DWARF2_UNWIND_INFO
)
2091 #undef TARGET_EXCEPT_UNWIND_INFO
2092 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
2094 #undef TARGET_DEFAULT_TARGET_FLAGS
2095 #define TARGET_DEFAULT_TARGET_FLAGS \
2097 | TARGET_SUBTARGET_DEFAULT \
2098 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
2100 #undef TARGET_HANDLE_OPTION
2101 #define TARGET_HANDLE_OPTION ix86_handle_option
2103 #undef TARGET_OPTION_OPTIMIZATION_TABLE
2104 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
2105 #undef TARGET_OPTION_INIT_STRUCT
2106 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
2108 #undef TARGET_SUPPORTS_SPLIT_STACK
2109 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
2111 /* This table must be in sync with enum processor_type in i386.h. */
2112 const char *const processor_names
[] =
2172 /* Guarantee that the array is aligned with enum processor_type. */
2173 STATIC_ASSERT (ARRAY_SIZE (processor_names
) == PROCESSOR_max
);
2175 const pta processor_alias_table
[] =
2177 {"i386", PROCESSOR_I386
, CPU_NONE
, 0, 0, P_NONE
},
2178 {"i486", PROCESSOR_I486
, CPU_NONE
, 0, 0, P_NONE
},
2179 {"i586", PROCESSOR_PENTIUM
, CPU_PENTIUM
, 0, 0, P_NONE
},
2180 {"pentium", PROCESSOR_PENTIUM
, CPU_PENTIUM
, 0, 0, P_NONE
},
2181 {"lakemont", PROCESSOR_LAKEMONT
, CPU_PENTIUM
, PTA_NO_80387
,
2183 {"pentium-mmx", PROCESSOR_PENTIUM
, CPU_PENTIUM
, PTA_MMX
, 0, P_NONE
},
2184 {"winchip-c6", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
, 0, P_NONE
},
2185 {"winchip2", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
| PTA_3DNOW
,
2187 {"c3", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
| PTA_3DNOW
, 0, P_NONE
},
2188 {"samuel-2", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
| PTA_3DNOW
,
2190 {"c3-2", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
2191 PTA_MMX
| PTA_SSE
| PTA_FXSR
, 0, P_NONE
},
2192 {"nehemiah", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
2193 PTA_MMX
| PTA_SSE
| PTA_FXSR
, 0, P_NONE
},
2194 {"c7", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
2195 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
, 0, P_NONE
},
2196 {"esther", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
2197 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
, 0, P_NONE
},
2198 {"i686", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
, 0, 0, P_NONE
},
2199 {"pentiumpro", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
, 0, 0, P_NONE
},
2200 {"pentium2", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
, PTA_MMX
| PTA_FXSR
,
2202 {"pentium3", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
2203 PTA_MMX
| PTA_SSE
| PTA_FXSR
, 0, P_NONE
},
2204 {"pentium3m", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
2205 PTA_MMX
| PTA_SSE
| PTA_FXSR
, 0, P_NONE
},
2206 {"pentium-m", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
2207 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_FXSR
, 0, P_NONE
},
2208 {"pentium4", PROCESSOR_PENTIUM4
, CPU_NONE
,
2209 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_FXSR
, 0, P_NONE
},
2210 {"pentium4m", PROCESSOR_PENTIUM4
, CPU_NONE
,
2211 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_FXSR
, 0, P_NONE
},
2212 {"prescott", PROCESSOR_NOCONA
, CPU_NONE
,
2213 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
, 0, P_NONE
},
2214 {"nocona", PROCESSOR_NOCONA
, CPU_NONE
,
2215 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2216 | PTA_CX16
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2217 {"core2", PROCESSOR_CORE2
, CPU_CORE2
, PTA_CORE2
,
2218 M_CPU_TYPE (INTEL_CORE2
), P_PROC_SSSE3
},
2219 {"nehalem", PROCESSOR_NEHALEM
, CPU_NEHALEM
, PTA_NEHALEM
,
2220 M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM
), P_PROC_DYNAMIC
},
2221 {"corei7", PROCESSOR_NEHALEM
, CPU_NEHALEM
, PTA_NEHALEM
,
2222 M_CPU_TYPE (INTEL_COREI7
), P_PROC_DYNAMIC
},
2223 {"westmere", PROCESSOR_NEHALEM
, CPU_NEHALEM
, PTA_WESTMERE
,
2224 M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE
), P_PROC_DYNAMIC
},
2225 {"sandybridge", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
2227 M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE
), P_PROC_DYNAMIC
},
2228 {"corei7-avx", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
2229 PTA_SANDYBRIDGE
, 0, P_PROC_DYNAMIC
},
2230 {"ivybridge", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
2232 M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE
), P_PROC_DYNAMIC
},
2233 {"core-avx-i", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
2234 PTA_IVYBRIDGE
, 0, P_PROC_DYNAMIC
},
2235 {"haswell", PROCESSOR_HASWELL
, CPU_HASWELL
, PTA_HASWELL
,
2236 M_CPU_SUBTYPE (INTEL_COREI7_HASWELL
), P_PROC_DYNAMIC
},
2237 {"core-avx2", PROCESSOR_HASWELL
, CPU_HASWELL
, PTA_HASWELL
,
2239 {"broadwell", PROCESSOR_HASWELL
, CPU_HASWELL
, PTA_BROADWELL
,
2240 M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL
), P_PROC_DYNAMIC
},
2241 {"skylake", PROCESSOR_SKYLAKE
, CPU_HASWELL
, PTA_SKYLAKE
,
2242 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE
), P_PROC_AVX2
},
2243 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512
, CPU_HASWELL
,
2245 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512
), P_PROC_AVX512F
},
2246 {"cannonlake", PROCESSOR_CANNONLAKE
, CPU_HASWELL
, PTA_CANNONLAKE
,
2247 M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE
), P_PROC_AVX512F
},
2248 {"icelake-client", PROCESSOR_ICELAKE_CLIENT
, CPU_HASWELL
,
2250 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT
), P_PROC_AVX512F
},
2251 {"rocketlake", PROCESSOR_ROCKETLAKE
, CPU_HASWELL
,
2253 M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE
), P_PROC_AVX512F
},
2254 {"icelake-server", PROCESSOR_ICELAKE_SERVER
, CPU_HASWELL
,
2256 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER
), P_PROC_AVX512F
},
2257 {"cascadelake", PROCESSOR_CASCADELAKE
, CPU_HASWELL
,
2259 M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE
), P_PROC_AVX512F
},
2260 {"tigerlake", PROCESSOR_TIGERLAKE
, CPU_HASWELL
, PTA_TIGERLAKE
,
2261 M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE
), P_PROC_AVX512F
},
2262 {"cooperlake", PROCESSOR_COOPERLAKE
, CPU_HASWELL
, PTA_COOPERLAKE
,
2263 M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE
), P_PROC_AVX512F
},
2264 {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS
, CPU_HASWELL
, PTA_SAPPHIRERAPIDS
,
2265 M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS
), P_PROC_AVX512F
},
2266 {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS
, CPU_HASWELL
, PTA_SAPPHIRERAPIDS
,
2267 M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS
), P_PROC_AVX512F
},
2268 {"alderlake", PROCESSOR_ALDERLAKE
, CPU_HASWELL
, PTA_ALDERLAKE
,
2269 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE
), P_PROC_AVX2
},
2270 {"raptorlake", PROCESSOR_ALDERLAKE
, CPU_HASWELL
, PTA_ALDERLAKE
,
2271 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE
), P_PROC_AVX2
},
2272 {"meteorlake", PROCESSOR_ALDERLAKE
, CPU_HASWELL
, PTA_ALDERLAKE
,
2273 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE
), P_PROC_AVX2
},
2274 {"graniterapids", PROCESSOR_GRANITERAPIDS
, CPU_HASWELL
, PTA_GRANITERAPIDS
,
2275 M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS
), P_PROC_AVX512F
},
2276 {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D
, CPU_HASWELL
,
2277 PTA_GRANITERAPIDS_D
, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D
),
2279 {"arrowlake", PROCESSOR_ARROWLAKE
, CPU_HASWELL
, PTA_ARROWLAKE
,
2280 M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE
), P_PROC_AVX2
},
2281 {"arrowlake-s", PROCESSOR_ARROWLAKE_S
, CPU_HASWELL
, PTA_ARROWLAKE_S
,
2282 M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S
), P_PROC_AVX2
},
2283 {"lunarlake", PROCESSOR_ARROWLAKE_S
, CPU_HASWELL
, PTA_ARROWLAKE_S
,
2284 M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S
), P_PROC_AVX2
},
2285 {"pantherlake", PROCESSOR_PANTHERLAKE
, CPU_HASWELL
, PTA_PANTHERLAKE
,
2286 M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE
), P_PROC_AVX2
},
2287 {"bonnell", PROCESSOR_BONNELL
, CPU_ATOM
, PTA_BONNELL
,
2288 M_CPU_TYPE (INTEL_BONNELL
), P_PROC_SSSE3
},
2289 {"atom", PROCESSOR_BONNELL
, CPU_ATOM
, PTA_BONNELL
,
2290 M_CPU_TYPE (INTEL_BONNELL
), P_PROC_SSSE3
},
2291 {"silvermont", PROCESSOR_SILVERMONT
, CPU_SLM
, PTA_SILVERMONT
,
2292 M_CPU_TYPE (INTEL_SILVERMONT
), P_PROC_SSE4_2
},
2293 {"slm", PROCESSOR_SILVERMONT
, CPU_SLM
, PTA_SILVERMONT
,
2294 M_CPU_TYPE (INTEL_SILVERMONT
), P_PROC_SSE4_2
},
2295 {"goldmont", PROCESSOR_GOLDMONT
, CPU_GLM
, PTA_GOLDMONT
,
2296 M_CPU_TYPE (INTEL_GOLDMONT
), P_PROC_SSE4_2
},
2297 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS
, CPU_GLM
, PTA_GOLDMONT_PLUS
,
2298 M_CPU_TYPE (INTEL_GOLDMONT_PLUS
), P_PROC_SSE4_2
},
2299 {"tremont", PROCESSOR_TREMONT
, CPU_HASWELL
, PTA_TREMONT
,
2300 M_CPU_TYPE (INTEL_TREMONT
), P_PROC_SSE4_2
},
2301 {"gracemont", PROCESSOR_ALDERLAKE
, CPU_HASWELL
, PTA_ALDERLAKE
,
2302 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE
), P_PROC_AVX2
},
2303 {"sierraforest", PROCESSOR_SIERRAFOREST
, CPU_HASWELL
, PTA_SIERRAFOREST
,
2304 M_CPU_SUBTYPE (INTEL_SIERRAFOREST
), P_PROC_AVX2
},
2305 {"grandridge", PROCESSOR_GRANDRIDGE
, CPU_HASWELL
, PTA_GRANDRIDGE
,
2306 M_CPU_TYPE (INTEL_GRANDRIDGE
), P_PROC_AVX2
},
2307 {"clearwaterforest", PROCESSOR_CLEARWATERFOREST
, CPU_HASWELL
,
2308 PTA_CLEARWATERFOREST
, M_CPU_TYPE (INTEL_CLEARWATERFOREST
), P_PROC_AVX2
},
2309 {"knl", PROCESSOR_KNL
, CPU_SLM
, PTA_KNL
,
2310 M_CPU_TYPE (INTEL_KNL
), P_PROC_AVX512F
},
2311 {"knm", PROCESSOR_KNM
, CPU_SLM
, PTA_KNM
,
2312 M_CPU_TYPE (INTEL_KNM
), P_PROC_AVX512F
},
2313 {"intel", PROCESSOR_INTEL
, CPU_SLM
, PTA_NEHALEM
,
2314 M_VENDOR (VENDOR_INTEL
), P_NONE
},
2315 {"geode", PROCESSOR_GEODE
, CPU_GEODE
,
2316 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_PREFETCH_SSE
, 0, P_NONE
},
2317 {"k6", PROCESSOR_K6
, CPU_K6
, PTA_MMX
, 0, P_NONE
},
2318 {"k6-2", PROCESSOR_K6
, CPU_K6
, PTA_MMX
| PTA_3DNOW
, 0, P_NONE
},
2319 {"k6-3", PROCESSOR_K6
, CPU_K6
, PTA_MMX
| PTA_3DNOW
, 0, P_NONE
},
2320 {"athlon", PROCESSOR_ATHLON
, CPU_ATHLON
,
2321 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_PREFETCH_SSE
, 0, P_NONE
},
2322 {"athlon-tbird", PROCESSOR_ATHLON
, CPU_ATHLON
,
2323 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_PREFETCH_SSE
, 0, P_NONE
},
2324 {"athlon-4", PROCESSOR_ATHLON
, CPU_ATHLON
,
2325 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_FXSR
, 0, P_NONE
},
2326 {"athlon-xp", PROCESSOR_ATHLON
, CPU_ATHLON
,
2327 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_FXSR
, 0, P_NONE
},
2328 {"athlon-mp", PROCESSOR_ATHLON
, CPU_ATHLON
,
2329 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_FXSR
, 0, P_NONE
},
2330 {"x86-64", PROCESSOR_K8
, CPU_K8
, PTA_X86_64_BASELINE
, 0, P_NONE
},
2331 {"x86-64-v2", PROCESSOR_K8
, CPU_GENERIC
, PTA_X86_64_V2
| PTA_NO_TUNE
,
2333 {"x86-64-v3", PROCESSOR_K8
, CPU_GENERIC
, PTA_X86_64_V3
| PTA_NO_TUNE
,
2335 {"x86-64-v4", PROCESSOR_K8
, CPU_GENERIC
, PTA_X86_64_V4
| PTA_NO_TUNE
,
2337 {"eden-x2", PROCESSOR_K8
, CPU_K8
,
2338 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
,
2340 {"nano", PROCESSOR_K8
, CPU_K8
,
2341 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2342 | PTA_SSSE3
| PTA_FXSR
, 0, P_NONE
},
2343 {"nano-1000", PROCESSOR_K8
, CPU_K8
,
2344 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2345 | PTA_SSSE3
| PTA_FXSR
, 0, P_NONE
},
2346 {"nano-2000", PROCESSOR_K8
, CPU_K8
,
2347 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2348 | PTA_SSSE3
| PTA_FXSR
, 0, P_NONE
},
2349 {"nano-3000", PROCESSOR_K8
, CPU_K8
,
2350 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2351 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
, 0, P_NONE
},
2352 {"nano-x2", PROCESSOR_K8
, CPU_K8
,
2353 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2354 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
, 0, P_NONE
},
2355 {"eden-x4", PROCESSOR_K8
, CPU_K8
,
2356 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2357 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
, 0, P_NONE
},
2358 {"nano-x4", PROCESSOR_K8
, CPU_K8
,
2359 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2360 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
, 0, P_NONE
},
2361 {"lujiazui", PROCESSOR_LUJIAZUI
, CPU_LUJIAZUI
,
2363 M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI
), P_NONE
},
2364 {"yongfeng", PROCESSOR_YONGFENG
, CPU_YONGFENG
,
2366 M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG
), P_NONE
},
2367 {"k8", PROCESSOR_K8
, CPU_K8
,
2368 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
2369 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2370 {"k8-sse3", PROCESSOR_K8
, CPU_K8
,
2371 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
2372 | PTA_SSE2
| PTA_SSE3
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2373 {"opteron", PROCESSOR_K8
, CPU_K8
,
2374 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
2375 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2376 {"opteron-sse3", PROCESSOR_K8
, CPU_K8
,
2377 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
2378 | PTA_SSE2
| PTA_SSE3
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2379 {"athlon64", PROCESSOR_K8
, CPU_K8
,
2380 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
2381 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2382 {"athlon64-sse3", PROCESSOR_K8
, CPU_K8
,
2383 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
2384 | PTA_SSE2
| PTA_SSE3
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2385 {"athlon-fx", PROCESSOR_K8
, CPU_K8
,
2386 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
2387 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
, 0, P_NONE
},
2388 {"amdfam10", PROCESSOR_AMDFAM10
, CPU_AMDFAM10
,
2389 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
2390 | PTA_SSE3
| PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_PRFCHW
| PTA_FXSR
,
2392 {"barcelona", PROCESSOR_AMDFAM10
, CPU_AMDFAM10
,
2393 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
2394 | PTA_SSE3
| PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_PRFCHW
| PTA_FXSR
,
2395 M_CPU_SUBTYPE (AMDFAM10H_BARCELONA
), P_PROC_DYNAMIC
},
2396 {"bdver1", PROCESSOR_BDVER1
, CPU_BDVER1
,
2397 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2398 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
2399 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_FMA4
2400 | PTA_XOP
| PTA_LWP
| PTA_PRFCHW
| PTA_FXSR
| PTA_XSAVE
,
2401 M_CPU_TYPE (AMDFAM15H_BDVER1
), P_PROC_XOP
},
2402 {"bdver2", PROCESSOR_BDVER2
, CPU_BDVER2
,
2403 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2404 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
2405 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_FMA4
2406 | PTA_XOP
| PTA_LWP
| PTA_BMI
| PTA_TBM
| PTA_F16C
2407 | PTA_FMA
| PTA_PRFCHW
| PTA_FXSR
| PTA_XSAVE
,
2408 M_CPU_TYPE (AMDFAM15H_BDVER2
), P_PROC_FMA
},
2409 {"bdver3", PROCESSOR_BDVER3
, CPU_BDVER3
,
2410 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2411 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
2412 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_FMA4
2413 | PTA_XOP
| PTA_LWP
| PTA_BMI
| PTA_TBM
| PTA_F16C
2414 | PTA_FMA
| PTA_PRFCHW
| PTA_FXSR
| PTA_XSAVE
2415 | PTA_XSAVEOPT
| PTA_FSGSBASE
,
2416 M_CPU_SUBTYPE (AMDFAM15H_BDVER3
), P_PROC_FMA
},
2417 {"bdver4", PROCESSOR_BDVER4
, CPU_BDVER4
,
2418 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2419 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
2420 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_AVX2
2421 | PTA_FMA4
| PTA_XOP
| PTA_LWP
| PTA_BMI
| PTA_BMI2
2422 | PTA_TBM
| PTA_F16C
| PTA_FMA
| PTA_PRFCHW
| PTA_FXSR
2423 | PTA_XSAVE
| PTA_XSAVEOPT
| PTA_FSGSBASE
| PTA_RDRND
2424 | PTA_MOVBE
| PTA_MWAITX
,
2425 M_CPU_SUBTYPE (AMDFAM15H_BDVER4
), P_PROC_AVX2
},
2426 {"znver1", PROCESSOR_ZNVER1
, CPU_ZNVER1
,
2428 M_CPU_SUBTYPE (AMDFAM17H_ZNVER1
), P_PROC_AVX2
},
2429 {"znver2", PROCESSOR_ZNVER2
, CPU_ZNVER2
,
2431 M_CPU_SUBTYPE (AMDFAM17H_ZNVER2
), P_PROC_AVX2
},
2432 {"znver3", PROCESSOR_ZNVER3
, CPU_ZNVER3
,
2434 M_CPU_SUBTYPE (AMDFAM19H_ZNVER3
), P_PROC_AVX2
},
2435 {"znver4", PROCESSOR_ZNVER4
, CPU_ZNVER4
,
2437 M_CPU_SUBTYPE (AMDFAM19H_ZNVER4
), P_PROC_AVX512F
},
2438 {"btver1", PROCESSOR_BTVER1
, CPU_GENERIC
,
2439 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2440 | PTA_SSSE3
| PTA_SSE4A
| PTA_ABM
| PTA_CX16
| PTA_PRFCHW
2441 | PTA_FXSR
| PTA_XSAVE
,
2442 M_CPU_SUBTYPE (AMDFAM15H_BDVER1
), P_PROC_SSE4_A
},
2443 {"btver2", PROCESSOR_BTVER2
, CPU_BTVER2
,
2444 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
2445 | PTA_SSSE3
| PTA_SSE4A
| PTA_ABM
| PTA_CX16
| PTA_SSE4_1
2446 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
2447 | PTA_BMI
| PTA_F16C
| PTA_MOVBE
| PTA_PRFCHW
2448 | PTA_FXSR
| PTA_XSAVE
| PTA_XSAVEOPT
,
2449 M_CPU_TYPE (AMD_BTVER2
), P_PROC_BMI
},
2451 {"generic", PROCESSOR_GENERIC
, CPU_GENERIC
,
2453 | PTA_HLE
/* flags are only used for -march switch. */,
2456 {"amd", PROCESSOR_GENERIC
, CPU_GENERIC
, 0,
2457 M_VENDOR (VENDOR_AMD
), P_NONE
},
2458 {"amdfam10h", PROCESSOR_GENERIC
, CPU_GENERIC
, 0,
2459 M_CPU_TYPE (AMDFAM10H
), P_NONE
},
2460 {"amdfam15h", PROCESSOR_GENERIC
, CPU_GENERIC
, 0,
2461 M_CPU_TYPE (AMDFAM15H
), P_NONE
},
2462 {"amdfam17h", PROCESSOR_GENERIC
, CPU_GENERIC
, 0,
2463 M_CPU_TYPE (AMDFAM17H
), P_NONE
},
2464 {"amdfam19h", PROCESSOR_GENERIC
, CPU_GENERIC
, 0,
2465 M_CPU_TYPE (AMDFAM19H
), P_NONE
},
2466 {"shanghai", PROCESSOR_GENERIC
, CPU_GENERIC
, 0,
2467 M_CPU_TYPE (AMDFAM10H_SHANGHAI
), P_NONE
},
2468 {"istanbul", PROCESSOR_GENERIC
, CPU_GENERIC
, 0,
2469 M_CPU_TYPE (AMDFAM10H_ISTANBUL
), P_NONE
},
2472 /* NB: processor_alias_table stops at the "generic" entry. */
2473 unsigned int const pta_size
= ARRAY_SIZE (processor_alias_table
) - 7;
2474 unsigned int const num_arch_names
= ARRAY_SIZE (processor_alias_table
);
2476 /* Provide valid option values for -march and -mtune options. */
2479 ix86_get_valid_option_values (int option_code
,
2480 const char *prefix ATTRIBUTE_UNUSED
)
2482 vec
<const char *> v
;
2484 opt_code opt
= (opt_code
) option_code
;
2489 for (unsigned i
= 0; i
< pta_size
; i
++)
2491 const char *name
= processor_alias_table
[i
].name
;
2492 gcc_checking_assert (name
!= NULL
);
2495 #ifdef HAVE_LOCAL_CPU_DETECT
2496 /* Add also "native" as possible value. */
2497 v
.safe_push ("native");
2502 for (unsigned i
= 0; i
< PROCESSOR_max
; i
++)
2504 const char *name
= processor_names
[i
];
2505 gcc_checking_assert (name
!= NULL
);
2516 #undef TARGET_GET_VALID_OPTION_VALUES
2517 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2519 struct gcc_targetm_common targetm_common
= TARGETM_COMMON_INITIALIZER
;