gcc/config/aarch64/aarch64-modes.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2020 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* Important note about Carry generation in AArch64.
  22
  23    Unlike some architectures, the C flag generated by a subtract
  24    operation, or a simple compare operation is set to 1 if the result
  25    does not overflow in an unsigned sense.  That is, if there is no
  26    borrow needed from a higher word.  That means that overflow from
  27    addition will set C, but overflow from a subtraction will clear C.
  28    We use CC_Cmode to represent detection of overflow from addition as
  29    CCmode is used for 'normal' compare (subtraction) operations.  For
  30    ADC, the representation becomes more complex still, since we cannot
  31    use the normal idiom of comparing the result to one of the input
  32    operands; instead we use CC_ADCmode to represent this case.  */
  33 CC_MODE (CCFP);
  34 CC_MODE (CCFPE);
  35 CC_MODE (CC_SWP);
  36 CC_MODE (CC_NZC);   /* Only N, Z and C bits of condition flags are valid.
  37                        (Used with SVE predicate tests.)  */
  38 CC_MODE (CC_NZ);    /* Only N and Z bits of condition flags are valid.  */
  39 CC_MODE (CC_Z);     /* Only Z bit of condition flags is valid.  */
  40 CC_MODE (CC_C);     /* C represents unsigned overflow of a simple addition.  */
  41 CC_MODE (CC_ADC);   /* Unsigned overflow from an ADC (add with carry).  */
  42 CC_MODE (CC_V);     /* Only V bit of condition flags is valid.  */
  43
  44 /* Half-precision floating point for __fp16.  */
  45 FLOAT_MODE (HF, 2, 0);
  46 ADJUST_FLOAT_FORMAT (HF, &ieee_half_format);
  47
  48 /* Vector modes.  */
  49
  50 VECTOR_BOOL_MODE (VNx16BI, 16, 2);
  51 VECTOR_BOOL_MODE (VNx8BI, 8, 2);
  52 VECTOR_BOOL_MODE (VNx4BI, 4, 2);
  53 VECTOR_BOOL_MODE (VNx2BI, 2, 2);
  54
  55 ADJUST_NUNITS (VNx16BI, aarch64_sve_vg * 8);
  56 ADJUST_NUNITS (VNx8BI, aarch64_sve_vg * 4);
  57 ADJUST_NUNITS (VNx4BI, aarch64_sve_vg * 2);
  58 ADJUST_NUNITS (VNx2BI, aarch64_sve_vg);
  59
  60 ADJUST_ALIGNMENT (VNx16BI, 2);
  61 ADJUST_ALIGNMENT (VNx8BI, 2);
  62 ADJUST_ALIGNMENT (VNx4BI, 2);
  63 ADJUST_ALIGNMENT (VNx2BI, 2);
  64
  65 VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI.  */
  66 VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI.  */
  67 VECTOR_MODES (FLOAT, 8);      /*                 V2SF.  */
  68 VECTOR_MODES (FLOAT, 16);     /*            V4SF V2DF.  */
  69 VECTOR_MODE (FLOAT, DF, 1);   /*                 V1DF.  */
  70 VECTOR_MODE (FLOAT, HF, 2);   /*                 V2HF.  */
  71
  72 /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments.  */
  73 INT_MODE (OI, 32);
  74
  75 /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
  76    (2 d-regs = 1 q-reg = TImode).  */
  77 INT_MODE (CI, 48);
  78 INT_MODE (XI, 64);
  79
  80 /* Define SVE modes for NVECS vectors.  VB, VH, VS and VD are the prefixes
  81    for 8-bit, 16-bit, 32-bit and 64-bit elements respectively.  It isn't
  82    strictly necessary to set the alignment here, since the default would
  83    be clamped to BIGGEST_ALIGNMENT anyhow, but it seems clearer.  */
  84 #define SVE_MODES(NVECS, VB, VH, VS, VD) \
  85   VECTOR_MODES_WITH_PREFIX (VNx, INT, 16 * NVECS, 0); \
  86   VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 16 * NVECS, 0); \
  87   \
  88   ADJUST_NUNITS (VB##QI, aarch64_sve_vg * NVECS * 8); \
  89   ADJUST_NUNITS (VH##HI, aarch64_sve_vg * NVECS * 4); \
  90   ADJUST_NUNITS (VS##SI, aarch64_sve_vg * NVECS * 2); \
  91   ADJUST_NUNITS (VD##DI, aarch64_sve_vg * NVECS); \
  92   ADJUST_NUNITS (VH##HF, aarch64_sve_vg * NVECS * 4); \
  93   ADJUST_NUNITS (VS##SF, aarch64_sve_vg * NVECS * 2); \
  94   ADJUST_NUNITS (VD##DF, aarch64_sve_vg * NVECS); \
  95   \
  96   ADJUST_ALIGNMENT (VB##QI, 16); \
  97   ADJUST_ALIGNMENT (VH##HI, 16); \
  98   ADJUST_ALIGNMENT (VS##SI, 16); \
  99   ADJUST_ALIGNMENT (VD##DI, 16); \
 100   ADJUST_ALIGNMENT (VH##HF, 16); \
 101   ADJUST_ALIGNMENT (VS##SF, 16); \
 102   ADJUST_ALIGNMENT (VD##DF, 16);
 103
 104 /* Give SVE vectors the names normally used for 256-bit vectors.
 105    The actual number depends on command-line flags.  */
 106 SVE_MODES (1, VNx16, VNx8, VNx4, VNx2)
 107 SVE_MODES (2, VNx32, VNx16, VNx8, VNx4)
 108 SVE_MODES (3, VNx48, VNx24, VNx12, VNx6)
 109 SVE_MODES (4, VNx64, VNx32, VNx16, VNx8)
 110
 111 /* Partial SVE vectors:
 112
 113       VNx2QI VNx4QI VNx8QI
 114       VNx2HI VNx4HI
 115       VNx2SI
 116
 117    In memory they occupy contiguous locations, in the same way as fixed-length
 118    vectors.  E.g. VNx8QImode is half the size of VNx16QImode.
 119
 120    Passing 1 as the final argument ensures that the modes come after all
 121    other modes in the GET_MODE_WIDER chain, so that we never pick them
 122    in preference to a full vector mode.  */
 123 VECTOR_MODES_WITH_PREFIX (VNx, INT, 2, 1);
 124 VECTOR_MODES_WITH_PREFIX (VNx, INT, 4, 1);
 125 VECTOR_MODES_WITH_PREFIX (VNx, INT, 8, 1);
 126 VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 4, 1);
 127 VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 8, 1);
 128
 129 ADJUST_NUNITS (VNx2QI, aarch64_sve_vg);
 130 ADJUST_NUNITS (VNx2HI, aarch64_sve_vg);
 131 ADJUST_NUNITS (VNx2SI, aarch64_sve_vg);
 132 ADJUST_NUNITS (VNx2HF, aarch64_sve_vg);
 133 ADJUST_NUNITS (VNx2SF, aarch64_sve_vg);
 134
 135 ADJUST_NUNITS (VNx4QI, aarch64_sve_vg * 2);
 136 ADJUST_NUNITS (VNx4HI, aarch64_sve_vg * 2);
 137 ADJUST_NUNITS (VNx4HF, aarch64_sve_vg * 2);
 138
 139 ADJUST_NUNITS (VNx8QI, aarch64_sve_vg * 4);
 140
 141 ADJUST_ALIGNMENT (VNx2QI, 1);
 142 ADJUST_ALIGNMENT (VNx4QI, 1);
 143 ADJUST_ALIGNMENT (VNx8QI, 1);
 144
 145 ADJUST_ALIGNMENT (VNx2HI, 2);
 146 ADJUST_ALIGNMENT (VNx4HI, 2);
 147 ADJUST_ALIGNMENT (VNx2HF, 2);
 148 ADJUST_ALIGNMENT (VNx4HF, 2);
 149
 150 ADJUST_ALIGNMENT (VNx2SI, 4);
 151 ADJUST_ALIGNMENT (VNx2SF, 4);
 152
 153 /* Quad float: 128-bit floating mode for long doubles.  */
 154 FLOAT_MODE (TF, 16, ieee_quad_format);
 155
 156 /* A 4-tuple of SVE vectors with the maximum -msve-vector-bits= setting.
 157    Note that this is a limit only on the compile-time sizes of modes;
 158    it is not a limit on the runtime sizes, since VL-agnostic code
 159    must work with arbitary vector lengths.  */
 160 #define MAX_BITSIZE_MODE_ANY_MODE (2048 * 4)
 161
 162 /* Coefficient 1 is multiplied by the number of 128-bit chunks in an
 163    SVE vector (referred to as "VQ") minus one.  */
 164 #define NUM_POLY_INT_COEFFS 2