1 /* Subroutines used for code generation on the Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994-2022 Free Software Foundation, Inc.
4 Sources derived from work done by Sankhya Technologies (www.sankhya.com) on
5 behalf of Synopsys Inc.
7 Position Independent Code support added,Code cleaned up,
8 Comments and Support For ARC700 instructions added by
9 Saurabh Verma (saurabh.verma@codito.com)
10 Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
12 Fixing ABI inconsistencies, optimizations for ARC600 / ARC700 pipelines,
13 profiling support added by Joern Rennecke <joern.rennecke@embecosm.com>
15 This file is part of GCC.
17 GCC is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 3, or (at your option)
22 GCC is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with GCC; see the file COPYING3. If not see
29 <http://www.gnu.org/licenses/>. */
31 #define IN_TARGET_CODE 1
35 #include "coretypes.h"
44 #include "stringpool.h"
50 #include "diagnostic.h"
51 #include "fold-const.h"
53 #include "stor-layout.h"
56 #include "insn-attr.h"
60 #include "langhooks.h"
61 #include "tm-constrs.h"
62 #include "reload.h" /* For operands_match_p */
64 #include "tree-pass.h"
70 #include "hw-doloop.h"
72 /* Which cpu we're compiling for (ARC600, ARC601, ARC700). */
73 static char arc_cpu_name
[10] = "";
74 static const char *arc_cpu_string
= arc_cpu_name
;
76 typedef struct GTY (()) _arc_jli_section
79 struct _arc_jli_section
*next
;
82 static arc_jli_section
*arc_jli_sections
= NULL
;
84 /* Track which regs are set fixed/call saved/call used from commnad line. */
85 HARD_REG_SET overrideregs
;
87 /* Maximum size of a loop. */
88 #define ARC_MAX_LOOP_LENGTH 4095
90 /* Check if an rtx fits in the store instruction format. Loads can
91 handle any constant. */
92 #define RTX_OK_FOR_OFFSET_P(MODE, X) \
93 (GET_CODE (X) == CONST_INT \
94 && SMALL_INT_RANGE (INTVAL (X), (GET_MODE_SIZE (MODE) - 1) & (~0x03), \
95 (INTVAL (X) & (GET_MODE_SIZE (MODE) - 1) & 3 \
97 : -(-GET_MODE_SIZE (MODE) | (~0x03)) >> 1)))
99 /* Array of valid operand punctuation characters. */
100 char arc_punct_chars
[256];
102 /* State used by arc_ccfsm_advance to implement conditional execution. */
103 struct GTY (()) arc_ccfsm
108 rtx_insn
*target_insn
;
112 /* Status of the IRQ_CTRL_AUX register. */
113 typedef struct irq_ctrl_saved_t
115 /* Last register number used by IRQ_CTRL_SAVED aux_reg. */
116 short irq_save_last_reg
;
117 /* True if BLINK is automatically saved. */
119 /* True if LPCOUNT is automatically saved. */
120 bool irq_save_lpcount
;
122 static irq_ctrl_saved_t irq_ctrl_saved
;
124 #define ARC_AUTOBLINK_IRQ_P(FNTYPE) \
125 ((ARC_INTERRUPT_P (FNTYPE) \
126 && irq_ctrl_saved.irq_save_blink) \
127 || (ARC_FAST_INTERRUPT_P (FNTYPE) \
128 && rgf_banked_register_count > 8))
130 #define ARC_AUTOFP_IRQ_P(FNTYPE) \
131 ((ARC_INTERRUPT_P (FNTYPE) \
132 && (irq_ctrl_saved.irq_save_last_reg > 26)) \
133 || (ARC_FAST_INTERRUPT_P (FNTYPE) \
134 && rgf_banked_register_count > 8))
136 #define ARC_AUTO_IRQ_P(FNTYPE) \
137 (ARC_INTERRUPT_P (FNTYPE) && !ARC_FAST_INTERRUPT_P (FNTYPE) \
138 && (irq_ctrl_saved.irq_save_blink \
139 || (irq_ctrl_saved.irq_save_last_reg >= 0)))
141 /* Number of registers in second bank for FIRQ support. */
142 static int rgf_banked_register_count
;
144 #define arc_ccfsm_current cfun->machine->ccfsm_current
146 #define ARC_CCFSM_BRANCH_DELETED_P(STATE) \
147 ((STATE)->state == 1 || (STATE)->state == 2)
149 /* Indicate we're conditionalizing insns now. */
150 #define ARC_CCFSM_RECORD_BRANCH_DELETED(STATE) \
151 ((STATE)->state += 2)
153 #define ARC_CCFSM_COND_EXEC_P(STATE) \
154 ((STATE)->state == 3 || (STATE)->state == 4 || (STATE)->state == 5 \
155 || current_insn_predicate)
157 /* Check if INSN has a 16 bit opcode considering struct arc_ccfsm *STATE. */
158 #define CCFSM_ISCOMPACT(INSN,STATE) \
159 (ARC_CCFSM_COND_EXEC_P (STATE) \
160 ? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
161 || get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
162 : get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
164 /* Likewise, but also consider that INSN might be in a delay slot of JUMP. */
165 #define CCFSM_DBR_ISCOMPACT(INSN,JUMP,STATE) \
166 ((ARC_CCFSM_COND_EXEC_P (STATE) \
168 && INSN_ANNULLED_BRANCH_P (JUMP) \
169 && (TARGET_AT_DBR_CONDEXEC || INSN_FROM_TARGET_P (INSN)))) \
170 ? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
171 || get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
172 : get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
174 /* Start enter/leave register range. */
175 #define ENTER_LEAVE_START_REG 13
177 /* End enter/leave register range. */
178 #define ENTER_LEAVE_END_REG 26
180 /* The maximum number of insns skipped which will be conditionalised if
182 /* When optimizing for speed:
183 Let p be the probability that the potentially skipped insns need to
184 be executed, pn the cost of a correctly predicted non-taken branch,
185 mt the cost of a mis/non-predicted taken branch,
186 mn mispredicted non-taken, pt correctly predicted taken ;
187 costs expressed in numbers of instructions like the ones considered
189 Unfortunately we don't have a measure of predictability - this
190 is linked to probability only in that in the no-eviction-scenario
191 there is a lower bound 1 - 2 * min (p, 1-p), and a somewhat larger
192 value that can be assumed *if* the distribution is perfectly random.
193 A predictability of 1 is perfectly plausible not matter what p is,
194 because the decision could be dependent on an invocation parameter
196 For large p, we want MAX_INSNS_SKIPPED == pn/(1-p) + mt - pn
197 For small p, we want MAX_INSNS_SKIPPED == pt
199 When optimizing for size:
200 We want to skip insn unless we could use 16 opcodes for the
201 non-conditionalized insn to balance the branch length or more.
202 Performance can be tie-breaker. */
203 /* If the potentially-skipped insns are likely to be executed, we'll
204 generally save one non-taken branch
206 this to be no less than the 1/p */
207 #define MAX_INSNS_SKIPPED 3
209 /* ZOL control registers. */
210 #define AUX_LP_START 0x02
211 #define AUX_LP_END 0x03
213 /* FPX AUX registers. */
214 #define AUX_DPFP_START 0x301
216 /* ARC600 MULHI register. */
217 #define AUX_MULHI 0x12
219 /* A nop is needed between a 4 byte insn that sets the condition codes and
220 a branch that uses them (the same isn't true for an 8 byte insn that sets
221 the condition codes). Set by arc_ccfsm_advance. Used by
222 arc_print_operand. */
224 static int get_arc_condition_code (rtx
);
226 static tree
arc_handle_interrupt_attribute (tree
*, tree
, tree
, int, bool *);
227 static tree
arc_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
228 static tree
arc_handle_jli_attribute (tree
*, tree
, tree
, int, bool *);
229 static tree
arc_handle_secure_attribute (tree
*, tree
, tree
, int, bool *);
230 static tree
arc_handle_uncached_attribute (tree
*, tree
, tree
, int, bool *);
231 static tree
arc_handle_aux_attribute (tree
*, tree
, tree
, int, bool *);
233 /* Initialized arc_attribute_table to NULL since arc doesnot have any
234 machine specific supported attributes. */
235 const struct attribute_spec arc_attribute_table
[] =
237 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
238 affects_type_identity, handler, exclude } */
239 { "interrupt", 1, 1, true, false, false, true,
240 arc_handle_interrupt_attribute
, NULL
},
241 /* Function calls made to this symbol must be done indirectly, because
242 it may lie outside of the 21/25 bit addressing range of a normal function
244 { "long_call", 0, 0, false, true, true, false, NULL
, NULL
},
245 /* Whereas these functions are always known to reside within the 25 bit
246 addressing range of unconditionalized bl. */
247 { "medium_call", 0, 0, false, true, true, false, NULL
, NULL
},
248 /* And these functions are always known to reside within the 21 bit
249 addressing range of blcc. */
250 { "short_call", 0, 0, false, true, true, false, NULL
, NULL
},
251 /* Function which are not having the prologue and epilogue generated
253 { "naked", 0, 0, true, false, false, false, arc_handle_fndecl_attribute
,
255 /* Functions calls made using jli instruction. The pointer in JLI
256 table is found latter. */
257 { "jli_always", 0, 0, false, true, true, false, NULL
, NULL
},
258 /* Functions calls made using jli instruction. The pointer in JLI
259 table is given as input parameter. */
260 { "jli_fixed", 1, 1, false, true, true, false, arc_handle_jli_attribute
,
262 /* Call a function using secure-mode. */
263 { "secure_call", 1, 1, false, true, true, false, arc_handle_secure_attribute
,
265 /* Bypass caches using .di flag. */
266 { "uncached", 0, 0, false, true, false, false, arc_handle_uncached_attribute
,
268 { "aux", 0, 1, true, false, false, false, arc_handle_aux_attribute
, NULL
},
269 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
271 static int arc_comp_type_attributes (const_tree
, const_tree
);
272 static void arc_file_start (void);
273 static void arc_internal_label (FILE *, const char *, unsigned long);
274 static void arc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
276 static int arc_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
277 static void arc_encode_section_info (tree decl
, rtx rtl
, int first
);
279 static void arc_init_builtins (void);
280 static rtx
arc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
282 static int branch_dest (rtx
);
284 static void arc_output_pic_addr_const (FILE *, rtx
, int);
285 static bool arc_function_ok_for_sibcall (tree
, tree
);
286 static rtx
arc_function_value (const_tree
, const_tree
, bool);
287 const char * output_shift (rtx
*);
288 static void arc_reorg (void);
289 static bool arc_in_small_data_p (const_tree
);
291 static void arc_init_reg_tables (void);
292 static bool arc_return_in_memory (const_tree
, const_tree
);
293 static bool arc_vector_mode_supported_p (machine_mode
);
295 static bool arc_can_use_doloop_p (const widest_int
&, const widest_int
&,
297 static const char *arc_invalid_within_doloop (const rtx_insn
*);
299 static void output_short_suffix (FILE *file
);
301 static bool arc_frame_pointer_required (void);
303 static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT
,
305 enum by_pieces_operation op
,
308 /* Globally visible information about currently selected cpu. */
309 const arc_cpu_t
*arc_selected_cpu
;
311 /* Traditionally, we push saved registers first in the prologue,
312 then we allocate the rest of the frame - and reverse in the epilogue.
313 This has still its merits for ease of debugging, or saving code size
314 or even execution time if the stack frame is so large that some accesses
315 can't be encoded anymore with offsets in the instruction code when using
317 Also, it would be a good starting point if we got instructions to help
318 with register save/restore.
320 However, often stack frames are small, and the pushing / popping has
322 - the stack modification prevents a lot of scheduling.
323 - frame allocation / deallocation may need extra instructions.
324 - we need to place a memory barrier after frame allocation to avoid
325 the delay slot scheduler to reschedule a frame related info and
326 messing up with dwarf unwinding. The barrier before deallocation
327 is for flushing all pending sp operations.
329 Thus, for small frames, we'd like to use a different scheme:
330 - The frame is allocated in full with the first prologue instruction,
331 and deallocated in full with the last epilogue instruction.
332 Thus, the instructions in-between can be freely scheduled.
333 - If the function has no outgoing arguments on the stack, we can allocate
334 one register save slot at the top of the stack. This register can then
335 be saved simultaneously with frame allocation, and restored with
337 This register can be picked depending on scheduling considerations,
338 although same though should go into having some set of registers
339 to be potentially lingering after a call, and others to be available
340 immediately - i.e. in the absence of interprocedual optimization, we
341 can use an ABI-like convention for register allocation to reduce
342 stalls after function return. */
344 /* ARCompact stack frames look like:
346 Before call After call
347 high +-----------------------+ +-----------------------+
348 mem | reg parm save area | | reg parm save area |
349 | only created for | | only created for |
350 | variable arg fns | | variable arg fns |
351 AP +-----------------------+ +-----------------------+
352 | return addr register | | return addr register |
353 | (if required) | | (if required) |
354 +-----------------------+ +-----------------------+
356 | reg save area | | reg save area |
358 +-----------------------+ +-----------------------+
359 | frame pointer | | frame pointer |
360 | (if required) | | (if required) |
361 FP +-----------------------+ +-----------------------+
363 | local/temp variables | | local/temp variables |
365 +-----------------------+ +-----------------------+
367 | arguments on stack | | arguments on stack |
369 SP +-----------------------+ +-----------------------+
370 | reg parm save area |
373 AP +-----------------------+
374 | return addr register |
376 +-----------------------+
380 +-----------------------+
383 FP +-----------------------+
385 | local/temp variables |
387 +-----------------------+
389 | arguments on stack |
391 mem SP +-----------------------+
394 1) The "reg parm save area" does not exist for non variable argument fns.
395 The "reg parm save area" can be eliminated completely if we created our
396 own va-arc.h, but that has tradeoffs as well (so it's not done). */
398 /* Structure to be filled in by arc_compute_frame_size with register
399 save masks, and offsets for the current function. */
400 struct GTY (()) arc_frame_info
402 unsigned int total_size
; /* # bytes that the entire frame takes up. */
403 unsigned int extra_size
; /* # bytes of extra stuff. */
404 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
405 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
406 unsigned int reg_size
; /* # bytes needed to store regs. */
407 unsigned int var_size
; /* # bytes that variables take up. */
408 uint64_t gmask
; /* Mask of saved gp registers. */
409 bool initialized
; /* FALSE if frame size already calculated. */
410 short millicode_start_reg
;
411 short millicode_end_reg
;
412 bool save_return_addr
;
415 /* GMASK bit length -1. */
418 /* Defining data structures for per-function information. */
420 typedef struct GTY (()) machine_function
422 unsigned int fn_type
;
423 struct arc_frame_info frame_info
;
424 /* To keep track of unalignment caused by short insns. */
426 struct arc_ccfsm ccfsm_current
;
427 /* Map from uid to ccfsm state during branch shortening. */
428 rtx ccfsm_current_insn
;
429 char arc_reorg_started
;
430 char prescan_initialized
;
434 /* Given a symbol RTX (const (symb <+ const_int>), returns its
438 get_symbol_alignment (rtx x
)
440 tree decl
= NULL_TREE
;
443 switch (GET_CODE (x
))
446 decl
= SYMBOL_REF_DECL (x
);
449 return get_symbol_alignment (XEXP (x
, 0));
451 gcc_assert (CONST_INT_P (XEXP (x
, 1)));
452 return get_symbol_alignment (XEXP (x
, 0));
458 align
= DECL_ALIGN (decl
);
459 align
= align
/ BITS_PER_UNIT
;
463 /* Return true if x is ok to be used as a small data address. */
466 legitimate_small_data_address_p (rtx x
, machine_mode mode
)
468 switch (GET_CODE (x
))
471 return legitimate_small_data_address_p (XEXP (x
, 0), mode
);
473 return SYMBOL_REF_SMALL_P (x
);
476 bool p0
= (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
477 && SYMBOL_REF_SMALL_P (XEXP (x
, 0));
479 /* If no constant then we cannot do small data. */
480 if (!CONST_INT_P (XEXP (x
, 1)))
483 /* Small data relocs works with scalled addresses, check if
484 the immediate fits the requirements. */
485 switch (GET_MODE_SIZE (mode
))
490 return p0
&& ((INTVAL (XEXP (x
, 1)) & 0x1) == 0);
493 return p0
&& ((INTVAL (XEXP (x
, 1)) & 0x3) == 0);
503 /* TRUE if op is an scaled address. */
505 legitimate_scaled_address_p (machine_mode mode
, rtx op
, bool strict
)
507 if (GET_CODE (op
) != PLUS
)
510 if (GET_CODE (XEXP (op
, 0)) != MULT
)
513 /* Check multiplication operands. */
514 if (!RTX_OK_FOR_INDEX_P (XEXP (XEXP (op
, 0), 0), strict
))
517 if (!CONST_INT_P (XEXP (XEXP (op
, 0), 1)))
520 switch (GET_MODE_SIZE (mode
))
523 if (INTVAL (XEXP (XEXP (op
, 0), 1)) != 2)
531 if (INTVAL (XEXP (XEXP (op
, 0), 1)) != 4)
538 /* Check the base. */
539 if (RTX_OK_FOR_BASE_P (XEXP (op
, 1), (strict
)))
544 if (CONST_INT_P (XEXP (op
, 1)))
549 /* Scalled addresses for sdata is done other places. */
550 if (legitimate_small_data_address_p (op
, mode
))
553 if (CONSTANT_P (XEXP (op
, 1)))
559 /* Check for constructions like REG + OFFS, where OFFS can be a
560 register, an immediate or an long immediate. */
563 legitimate_offset_address_p (machine_mode mode
, rtx x
, bool index
, bool strict
)
565 if (GET_CODE (x
) != PLUS
)
568 if (!RTX_OK_FOR_BASE_P (XEXP (x
, 0), (strict
)))
571 /* Check for: [Rx + small offset] or [Rx + Ry]. */
572 if (((index
&& RTX_OK_FOR_INDEX_P (XEXP (x
, 1), (strict
))
573 && GET_MODE_SIZE ((mode
)) <= 4)
574 || RTX_OK_FOR_OFFSET_P (mode
, XEXP (x
, 1))))
577 /* Check for [Rx + symbol]. */
579 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
580 /* Avoid this type of address for double or larger modes. */
581 && (GET_MODE_SIZE (mode
) <= 4)
582 /* Avoid small data which ends in something like GP +
584 && (!SYMBOL_REF_SMALL_P (XEXP (x
, 1))))
590 /* Implements target hook vector_mode_supported_p. */
593 arc_vector_mode_supported_p (machine_mode mode
)
598 return TARGET_PLUS_DMPY
;
601 return TARGET_PLUS_QMACW
;
604 return TARGET_SIMD_SET
;
611 /* Implements target hook TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
614 arc_preferred_simd_mode (scalar_mode mode
)
619 return TARGET_PLUS_QMACW
? V4HImode
: V2HImode
;
628 /* Implements target hook
629 TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES. */
632 arc_autovectorize_vector_modes (vector_modes
*modes
, bool)
634 if (TARGET_PLUS_QMACW
)
636 modes
->quick_push (V4HImode
);
637 modes
->quick_push (V2HImode
);
643 /* Implements target hook TARGET_SCHED_ISSUE_RATE. */
645 arc_sched_issue_rate (void)
658 /* TARGET_PRESERVE_RELOAD_P is still awaiting patch re-evaluation / review. */
659 static bool arc_preserve_reload_p (rtx in
) ATTRIBUTE_UNUSED
;
660 static rtx
arc_delegitimize_address (rtx
);
661 static bool arc_can_follow_jump (const rtx_insn
*follower
,
662 const rtx_insn
*followee
);
664 static rtx
frame_insn (rtx
);
665 static void arc_function_arg_advance (cumulative_args_t
,
666 const function_arg_info
&);
667 static rtx
arc_legitimize_address_0 (rtx
, rtx
, machine_mode mode
);
669 /* initialize the GCC target structure. */
670 #undef TARGET_COMP_TYPE_ATTRIBUTES
671 #define TARGET_COMP_TYPE_ATTRIBUTES arc_comp_type_attributes
672 #undef TARGET_ASM_FILE_START
673 #define TARGET_ASM_FILE_START arc_file_start
674 #undef TARGET_ATTRIBUTE_TABLE
675 #define TARGET_ATTRIBUTE_TABLE arc_attribute_table
676 #undef TARGET_ASM_INTERNAL_LABEL
677 #define TARGET_ASM_INTERNAL_LABEL arc_internal_label
678 #undef TARGET_RTX_COSTS
679 #define TARGET_RTX_COSTS arc_rtx_costs
680 #undef TARGET_ADDRESS_COST
681 #define TARGET_ADDRESS_COST arc_address_cost
683 #undef TARGET_ENCODE_SECTION_INFO
684 #define TARGET_ENCODE_SECTION_INFO arc_encode_section_info
686 #undef TARGET_CANNOT_FORCE_CONST_MEM
687 #define TARGET_CANNOT_FORCE_CONST_MEM arc_cannot_force_const_mem
689 #undef TARGET_INIT_BUILTINS
690 #define TARGET_INIT_BUILTINS arc_init_builtins
692 #undef TARGET_EXPAND_BUILTIN
693 #define TARGET_EXPAND_BUILTIN arc_expand_builtin
695 #undef TARGET_BUILTIN_DECL
696 #define TARGET_BUILTIN_DECL arc_builtin_decl
698 #undef TARGET_ASM_OUTPUT_MI_THUNK
699 #define TARGET_ASM_OUTPUT_MI_THUNK arc_output_mi_thunk
701 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
702 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
704 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
705 #define TARGET_FUNCTION_OK_FOR_SIBCALL arc_function_ok_for_sibcall
707 #undef TARGET_MACHINE_DEPENDENT_REORG
708 #define TARGET_MACHINE_DEPENDENT_REORG arc_reorg
710 #undef TARGET_IN_SMALL_DATA_P
711 #define TARGET_IN_SMALL_DATA_P arc_in_small_data_p
713 #undef TARGET_PROMOTE_FUNCTION_MODE
714 #define TARGET_PROMOTE_FUNCTION_MODE \
715 default_promote_function_mode_always_promote
717 #undef TARGET_PROMOTE_PROTOTYPES
718 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
720 #undef TARGET_RETURN_IN_MEMORY
721 #define TARGET_RETURN_IN_MEMORY arc_return_in_memory
722 #undef TARGET_PASS_BY_REFERENCE
723 #define TARGET_PASS_BY_REFERENCE arc_pass_by_reference
725 #undef TARGET_SETUP_INCOMING_VARARGS
726 #define TARGET_SETUP_INCOMING_VARARGS arc_setup_incoming_varargs
728 #undef TARGET_ARG_PARTIAL_BYTES
729 #define TARGET_ARG_PARTIAL_BYTES arc_arg_partial_bytes
731 #undef TARGET_MUST_PASS_IN_STACK
732 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
734 #undef TARGET_FUNCTION_VALUE
735 #define TARGET_FUNCTION_VALUE arc_function_value
737 #undef TARGET_SCHED_ADJUST_PRIORITY
738 #define TARGET_SCHED_ADJUST_PRIORITY arc_sched_adjust_priority
740 #undef TARGET_SCHED_ISSUE_RATE
741 #define TARGET_SCHED_ISSUE_RATE arc_sched_issue_rate
743 #undef TARGET_VECTOR_MODE_SUPPORTED_P
744 #define TARGET_VECTOR_MODE_SUPPORTED_P arc_vector_mode_supported_p
746 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
747 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arc_preferred_simd_mode
749 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
750 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES arc_autovectorize_vector_modes
752 #undef TARGET_CAN_USE_DOLOOP_P
753 #define TARGET_CAN_USE_DOLOOP_P arc_can_use_doloop_p
755 #undef TARGET_INVALID_WITHIN_DOLOOP
756 #define TARGET_INVALID_WITHIN_DOLOOP arc_invalid_within_doloop
758 #undef TARGET_PRESERVE_RELOAD_P
759 #define TARGET_PRESERVE_RELOAD_P arc_preserve_reload_p
761 #undef TARGET_CAN_FOLLOW_JUMP
762 #define TARGET_CAN_FOLLOW_JUMP arc_can_follow_jump
764 #undef TARGET_DELEGITIMIZE_ADDRESS
765 #define TARGET_DELEGITIMIZE_ADDRESS arc_delegitimize_address
767 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
768 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
769 arc_use_by_pieces_infrastructure_p
771 /* Usually, we will be able to scale anchor offsets.
772 When this fails, we want LEGITIMIZE_ADDRESS to kick in. */
773 #undef TARGET_MIN_ANCHOR_OFFSET
774 #define TARGET_MIN_ANCHOR_OFFSET (-1024)
775 #undef TARGET_MAX_ANCHOR_OFFSET
776 #define TARGET_MAX_ANCHOR_OFFSET (1020)
778 #undef TARGET_SECONDARY_RELOAD
779 #define TARGET_SECONDARY_RELOAD arc_secondary_reload
781 #define TARGET_OPTION_OVERRIDE arc_override_options
783 #define TARGET_CONDITIONAL_REGISTER_USAGE arc_conditional_register_usage
785 #define TARGET_TRAMPOLINE_INIT arc_initialize_trampoline
787 #define TARGET_CAN_ELIMINATE arc_can_eliminate
789 #define TARGET_FRAME_POINTER_REQUIRED arc_frame_pointer_required
791 #define TARGET_FUNCTION_ARG arc_function_arg
793 #define TARGET_FUNCTION_ARG_ADVANCE arc_function_arg_advance
795 #define TARGET_LEGITIMATE_CONSTANT_P arc_legitimate_constant_p
797 #define TARGET_LEGITIMATE_ADDRESS_P arc_legitimate_address_p
799 #define TARGET_MODE_DEPENDENT_ADDRESS_P arc_mode_dependent_address_p
801 #define TARGET_LEGITIMIZE_ADDRESS arc_legitimize_address
803 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
804 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P \
805 arc_no_speculation_in_delay_slots_p
808 #define TARGET_LRA_P arc_lra_p
809 #define TARGET_REGISTER_PRIORITY arc_register_priority
810 /* Stores with scaled offsets have different displacement ranges. */
811 #define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P hook_bool_void_true
812 #define TARGET_SPILL_CLASS arc_spill_class
814 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
815 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arc_allocate_stack_slots_for_args
817 #undef TARGET_WARN_FUNC_RETURN
818 #define TARGET_WARN_FUNC_RETURN arc_warn_func_return
820 #include "target-def.h"
822 #undef TARGET_ASM_ALIGNED_HI_OP
823 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
824 #undef TARGET_ASM_ALIGNED_SI_OP
825 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
828 #undef TARGET_HAVE_TLS
829 #define TARGET_HAVE_TLS HAVE_AS_TLS
832 #undef TARGET_DWARF_REGISTER_SPAN
833 #define TARGET_DWARF_REGISTER_SPAN arc_dwarf_register_span
835 #undef TARGET_HARD_REGNO_NREGS
836 #define TARGET_HARD_REGNO_NREGS arc_hard_regno_nregs
837 #undef TARGET_HARD_REGNO_MODE_OK
838 #define TARGET_HARD_REGNO_MODE_OK arc_hard_regno_mode_ok
840 #undef TARGET_MODES_TIEABLE_P
841 #define TARGET_MODES_TIEABLE_P arc_modes_tieable_p
843 /* Try to keep the (mov:DF _, reg) as early as possible so
844 that the d<add/sub/mul>h-lr insns appear together and can
845 use the peephole2 pattern. */
848 arc_sched_adjust_priority (rtx_insn
*insn
, int priority
)
850 rtx set
= single_set (insn
);
852 && GET_MODE (SET_SRC(set
)) == DFmode
853 && GET_CODE (SET_SRC(set
)) == REG
)
855 /* Incrementing priority by 20 (empirically derived). */
856 return priority
+ 20;
862 /* For ARC base register + offset addressing, the validity of the
863 address is mode-dependent for most of the offset range, as the
864 offset can be scaled by the access size.
865 We don't expose these as mode-dependent addresses in the
866 mode_dependent_address_p target hook, because that would disable
867 lots of optimizations, and most uses of these addresses are for 32
868 or 64 bit accesses anyways, which are fine.
869 However, that leaves some addresses for 8 / 16 bit values not
870 properly reloaded by the generic code, which is why we have to
871 schedule secondary reloads for these. */
874 arc_secondary_reload (bool in_p
,
878 secondary_reload_info
*sri
)
880 enum rtx_code code
= GET_CODE (x
);
882 if (cl
== DOUBLE_REGS
)
885 /* If we have a subreg (reg), where reg is a pseudo (that will end in
886 a memory location), then we may need a scratch register to handle
887 the fp/sp+largeoffset address. */
895 int regno
= REGNO (x
);
896 if (regno
>= FIRST_PSEUDO_REGISTER
)
897 regno
= reg_renumber
[regno
];
902 /* It is a pseudo that ends in a stack location. This
903 procedure only works with the old reload step. */
904 if (!lra_in_progress
&& reg_equiv_mem (REGNO (x
)))
906 /* Get the equivalent address and check the range of the
908 rtx mem
= reg_equiv_mem (REGNO (x
));
909 addr
= find_replacement (&XEXP (mem
, 0));
914 gcc_assert (MEM_P (x
));
916 addr
= simplify_rtx (addr
);
918 if (addr
&& GET_CODE (addr
) == PLUS
919 && CONST_INT_P (XEXP (addr
, 1))
920 && (!RTX_OK_FOR_OFFSET_P (mode
, XEXP (addr
, 1))))
926 in_p
? CODE_FOR_reload_qi_load
: CODE_FOR_reload_qi_store
;
930 in_p
? CODE_FOR_reload_hi_load
: CODE_FOR_reload_hi_store
;
940 /* Convert reloads using offsets that are too large to use indirect
944 arc_secondary_reload_conv (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
948 gcc_assert (GET_CODE (mem
) == MEM
);
949 addr
= XEXP (mem
, 0);
951 /* Large offset: use a move. FIXME: ld ops accepts limms as
952 offsets. Hence, the following move insn is not required. */
953 emit_move_insn (scratch
, addr
);
954 mem
= replace_equiv_address_nv (mem
, scratch
);
956 /* Now create the move. */
958 emit_insn (gen_rtx_SET (mem
, reg
));
960 emit_insn (gen_rtx_SET (reg
, mem
));
965 static unsigned arc_ifcvt (void);
969 const pass_data pass_data_arc_ifcvt
=
972 "arc_ifcvt", /* name */
973 OPTGROUP_NONE
, /* optinfo_flags */
974 TV_IFCVT2
, /* tv_id */
975 0, /* properties_required */
976 0, /* properties_provided */
977 0, /* properties_destroyed */
978 0, /* todo_flags_start */
979 TODO_df_finish
/* todo_flags_finish */
982 class pass_arc_ifcvt
: public rtl_opt_pass
985 pass_arc_ifcvt (gcc::context
*ctxt
)
986 : rtl_opt_pass (pass_data_arc_ifcvt
, ctxt
)
989 /* opt_pass methods: */
992 return new pass_arc_ifcvt (m_ctxt
);
994 virtual unsigned int execute (function
*)
998 virtual bool gate (function
*)
1000 return (optimize
> 1 && !TARGET_NO_COND_EXEC
);
1007 make_pass_arc_ifcvt (gcc::context
*ctxt
)
1009 return new pass_arc_ifcvt (ctxt
);
1012 static unsigned arc_predicate_delay_insns (void);
1016 const pass_data pass_data_arc_predicate_delay_insns
=
1019 "arc_predicate_delay_insns", /* name */
1020 OPTGROUP_NONE
, /* optinfo_flags */
1021 TV_IFCVT2
, /* tv_id */
1022 0, /* properties_required */
1023 0, /* properties_provided */
1024 0, /* properties_destroyed */
1025 0, /* todo_flags_start */
1026 TODO_df_finish
/* todo_flags_finish */
1029 class pass_arc_predicate_delay_insns
: public rtl_opt_pass
1032 pass_arc_predicate_delay_insns(gcc::context
*ctxt
)
1033 : rtl_opt_pass(pass_data_arc_predicate_delay_insns
, ctxt
)
1036 /* opt_pass methods: */
1037 virtual unsigned int execute (function
*)
1039 return arc_predicate_delay_insns ();
1041 virtual bool gate (function
*)
1043 return flag_delayed_branch
;
1050 make_pass_arc_predicate_delay_insns (gcc::context
*ctxt
)
1052 return new pass_arc_predicate_delay_insns (ctxt
);
1055 /* Called by OVERRIDE_OPTIONS to initialize various things. */
1062 /* I have the multiplier, then use it*/
1063 if (TARGET_MPYW
|| TARGET_MULTI
)
1064 arc_multcost
= COSTS_N_INSNS (1);
1066 /* Note: arc_multcost is only used in rtx_cost if speed is true. */
1067 if (arc_multcost
< 0)
1070 case ARC_TUNE_ARC700_4_2_STD
:
1072 max throughput (1 multiply + 4 other insns) / 5 cycles. */
1073 arc_multcost
= COSTS_N_INSNS (4);
1074 if (TARGET_NOMPY_SET
)
1075 arc_multcost
= COSTS_N_INSNS (30);
1077 case ARC_TUNE_ARC700_4_2_XMAC
:
1079 max throughput (1 multiply + 2 other insns) / 3 cycles. */
1080 arc_multcost
= COSTS_N_INSNS (3);
1081 if (TARGET_NOMPY_SET
)
1082 arc_multcost
= COSTS_N_INSNS (30);
1084 case ARC_TUNE_ARC600
:
1085 if (TARGET_MUL64_SET
)
1087 arc_multcost
= COSTS_N_INSNS (4);
1092 arc_multcost
= COSTS_N_INSNS (30);
1096 /* MPY instructions valid only for ARC700 or ARCv2. */
1097 if (TARGET_NOMPY_SET
&& TARGET_ARC600_FAMILY
)
1098 error ("%<-mno-mpy%> supported only for ARC700 or ARCv2");
1100 if (!TARGET_DPFP
&& TARGET_DPFP_DISABLE_LRSR
)
1101 error ("%<-mno-dpfp-lrsr%> supported only with %<-mdpfp%>");
1103 /* FPX-1. No fast and compact together. */
1104 if ((TARGET_DPFP_FAST_SET
&& TARGET_DPFP_COMPACT_SET
)
1105 || (TARGET_SPFP_FAST_SET
&& TARGET_SPFP_COMPACT_SET
))
1106 error ("FPX fast and compact options cannot be specified together");
1108 /* FPX-2. No fast-spfp for arc600 or arc601. */
1109 if (TARGET_SPFP_FAST_SET
&& TARGET_ARC600_FAMILY
)
1110 error ("%<-mspfp_fast%> not available on ARC600 or ARC601");
1112 /* FPX-4. No FPX extensions mixed with FPU extensions. */
1113 if ((TARGET_DPFP_FAST_SET
|| TARGET_DPFP_COMPACT_SET
|| TARGET_SPFP
)
1114 && TARGET_HARD_FLOAT
)
1115 error ("no FPX/FPU mixing allowed");
1117 /* Warn for unimplemented PIC in pre-ARC700 cores, and disable flag_pic. */
1118 if (flag_pic
&& TARGET_ARC600_FAMILY
)
1120 warning (0, "PIC is not supported for %qs",
1125 arc_init_reg_tables ();
1127 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
1128 memset (arc_punct_chars
, 0, sizeof (arc_punct_chars
));
1129 arc_punct_chars
['#'] = 1;
1130 arc_punct_chars
['*'] = 1;
1131 arc_punct_chars
['?'] = 1;
1132 arc_punct_chars
['!'] = 1;
1133 arc_punct_chars
['^'] = 1;
1134 arc_punct_chars
['&'] = 1;
1135 arc_punct_chars
['+'] = 1;
1136 arc_punct_chars
['_'] = 1;
1139 /* Parse -mirq-ctrl-saved=RegisterRange, blink, lp_copunt. The
1140 register range is specified as two registers separated by a dash.
1141 It always starts with r0, and its upper limit is fp register.
1142 blink and lp_count registers are optional. */
1145 irq_range (const char *cstr
)
1147 int i
, first
, last
, blink
, lpcount
, xreg
;
1148 char *str
, *dash
, *comma
;
1151 str
= (char *) alloca (i
+ 1);
1152 memcpy (str
, cstr
, i
+ 1);
1156 dash
= strchr (str
, '-');
1159 warning (OPT_mirq_ctrl_saved_
, "missing dash");
1164 comma
= strchr (dash
+ 1, ',');
1168 first
= decode_reg_name (str
);
1171 warning (OPT_mirq_ctrl_saved_
, "first register must be R0");
1175 /* At this moment we do not have the register names initialized
1177 if (!strcmp (dash
+ 1, "ilink"))
1180 last
= decode_reg_name (dash
+ 1);
1184 warning (OPT_mirq_ctrl_saved_
, "unknown register name: %s", dash
+ 1);
1190 warning (OPT_mirq_ctrl_saved_
,
1191 "last register name %s must be an odd register", dash
+ 1);
1199 warning (OPT_mirq_ctrl_saved_
,
1200 "%s-%s is an empty range", str
, dash
+ 1);
1209 comma
= strchr (str
, ',');
1213 xreg
= decode_reg_name (str
);
1225 warning (OPT_mirq_ctrl_saved_
,
1226 "unknown register name: %s", str
);
1231 irq_ctrl_saved
.irq_save_last_reg
= last
;
1232 irq_ctrl_saved
.irq_save_blink
= (blink
== 31) || (last
== 31);
1233 irq_ctrl_saved
.irq_save_lpcount
= (lpcount
== 60);
1236 /* Parse -mrgf-banked-regs=NUM option string. Valid values for NUM are 4,
1240 parse_mrgf_banked_regs_option (const char *arg
)
1246 val
= strtol (arg
, &end_ptr
, 10);
1247 if (errno
!= 0 || *arg
== '\0' || *end_ptr
!= '\0'
1248 || (val
!= 0 && val
!= 4 && val
!= 8 && val
!= 16 && val
!= 32))
1250 error ("invalid number in %<-mrgf-banked-regs=%s%> "
1251 "valid values are 0, 4, 8, 16, or 32", arg
);
1254 rgf_banked_register_count
= (int) val
;
1257 /* Check ARC options, generate derived target attributes. */
1260 arc_override_options (void)
1263 cl_deferred_option
*opt
;
1264 vec
<cl_deferred_option
> *vopt
1265 = (vec
<cl_deferred_option
> *) arc_deferred_options
;
1267 if (arc_cpu
== PROCESSOR_NONE
)
1268 arc_cpu
= TARGET_CPU_DEFAULT
;
1270 /* Set the default cpu options. */
1271 arc_selected_cpu
= &arc_cpu_types
[(int) arc_cpu
];
1273 /* Set the architectures. */
1274 switch (arc_selected_cpu
->arch_info
->arch_id
)
1277 arc_cpu_string
= "EM";
1280 arc_cpu_string
= "HS";
1283 if (arc_selected_cpu
->processor
== PROCESSOR_nps400
)
1284 arc_cpu_string
= "NPS400";
1286 arc_cpu_string
= "ARC700";
1289 arc_cpu_string
= "ARC600";
1295 irq_ctrl_saved
.irq_save_last_reg
= -1;
1296 irq_ctrl_saved
.irq_save_blink
= false;
1297 irq_ctrl_saved
.irq_save_lpcount
= false;
1299 rgf_banked_register_count
= 0;
1301 /* Handle the deferred options. */
1303 FOR_EACH_VEC_ELT (*vopt
, i
, opt
)
1305 switch (opt
->opt_index
)
1307 case OPT_mirq_ctrl_saved_
:
1309 irq_range (opt
->arg
);
1311 warning (OPT_mirq_ctrl_saved_
,
1312 "option %<-mirq-ctrl-saved%> valid only "
1313 "for ARC v2 processors");
1316 case OPT_mrgf_banked_regs_
:
1318 parse_mrgf_banked_regs_option (opt
->arg
);
1320 warning (OPT_mrgf_banked_regs_
,
1321 "option %<-mrgf-banked-regs%> valid only for "
1322 "ARC v2 processors");
1330 CLEAR_HARD_REG_SET (overrideregs
);
1331 if (common_deferred_options
)
1333 vec
<cl_deferred_option
> v
=
1334 *((vec
<cl_deferred_option
> *) common_deferred_options
);
1337 FOR_EACH_VEC_ELT (v
, i
, opt
)
1339 switch (opt
->opt_index
)
1342 case OPT_fcall_used_
:
1343 case OPT_fcall_saved_
:
1344 if ((reg
= decode_reg_name_and_count (opt
->arg
, &nregs
)) >= 0)
1345 for (j
= reg
; j
< reg
+ nregs
; j
++)
1346 SET_HARD_REG_BIT (overrideregs
, j
);
1354 /* Check options against architecture options. Throw an error if
1355 option is not allowed. Extra, check options against default
1356 architecture/cpu flags and throw an warning if we find a
1358 /* TRANSLATORS: the DOC/DOC0/DOC1 are strings which shouldn't be
1359 translated. They are like keywords which one can relate with the
1360 architectural choices taken for an ARC CPU implementation. */
1361 #define ARC_OPTX(NAME, CODE, VAR, VAL, DOC0, DOC1) \
1363 if ((!(arc_selected_cpu->arch_info->flags & CODE)) \
1365 error ("option %<%s=%s%> is not available for %qs CPU", \
1366 DOC0, DOC1, arc_selected_cpu->name); \
1367 if ((arc_selected_cpu->arch_info->dflags & CODE) \
1368 && (VAR != DEFAULT_##VAR) \
1370 warning (0, "option %qs is ignored, the default value %qs" \
1371 " is considered for %qs CPU", DOC0, DOC1, \
1372 arc_selected_cpu->name); \
1374 #define ARC_OPT(NAME, CODE, MASK, DOC) \
1376 if ((!(arc_selected_cpu->arch_info->flags & CODE)) \
1377 && (target_flags & MASK)) \
1378 error ("option %qs is not available for %qs CPU", \
1379 DOC, arc_selected_cpu->name); \
1380 if ((arc_selected_cpu->arch_info->dflags & CODE) \
1381 && (target_flags_explicit & MASK) \
1382 && (!(target_flags & MASK))) \
1383 warning (0, "unset option %qs is ignored, it is always" \
1384 " enabled for %qs CPU", DOC, \
1385 arc_selected_cpu->name); \
1388 #include "arc-options.def"
1393 /* Set cpu flags accordingly to architecture/selected cpu. The cpu
1394 specific flags are set in arc-common.c. The architecture forces
1395 the default hardware configurations in, regardless what command
1396 line options are saying. The CPU optional hw options can be
1397 turned on or off. */
1398 #define ARC_OPT(NAME, CODE, MASK, DOC) \
1400 if ((arc_selected_cpu->flags & CODE) \
1401 && ((target_flags_explicit & MASK) == 0)) \
1402 target_flags |= MASK; \
1403 if (arc_selected_cpu->arch_info->dflags & CODE) \
1404 target_flags |= MASK; \
1406 #define ARC_OPTX(NAME, CODE, VAR, VAL, DOC0, DOC1) \
1408 if ((arc_selected_cpu->flags & CODE) \
1409 && (VAR == DEFAULT_##VAR)) \
1411 if (arc_selected_cpu->arch_info->dflags & CODE) \
1415 #include "arc-options.def"
1421 switch (arc_selected_cpu
->extra
)
1423 case HAS_LPCOUNT_16
:
1430 /* Set Tune option. */
1431 if (arc_tune
== ARC_TUNE_NONE
)
1432 arc_tune
= (enum arc_tune_attr
) arc_selected_cpu
->tune
;
1434 if (arc_size_opt_level
== 3)
1437 if (TARGET_V2
&& optimize_size
&& (ATTRIBUTE_PCS
== 2))
1438 TARGET_CODE_DENSITY_FRAME
= 1;
1441 target_flags
|= MASK_NO_SDATA_SET
;
1443 /* Check for small data option */
1444 if (!OPTION_SET_P (g_switch_value
) && !TARGET_NO_SDATA_SET
)
1445 g_switch_value
= TARGET_LL64
? 8 : 4;
1447 /* A7 has an issue with delay slots. */
1448 if (TARGET_ARC700
&& (arc_tune
!= ARC_TUNE_ARC7XX
))
1449 flag_delayed_branch
= 0;
1451 /* Millicode thunks doesn't work for long calls. */
1452 if (TARGET_LONG_CALLS_SET
1453 /* neither for RF16. */
1455 target_flags
&= ~MASK_MILLICODE_THUNK_SET
;
1457 /* Set unaligned to all HS cpus. */
1458 if (!OPTION_SET_P (unaligned_access
) && TARGET_HS
)
1459 unaligned_access
= 1;
1461 /* These need to be done at start up. It's convenient to do them here. */
1465 /* The condition codes of the ARC, and the inverse function. */
1466 /* For short branches, the "c" / "nc" names are not defined in the ARC
1467 Programmers manual, so we have to use "lo" / "hs"" instead. */
1468 static const char *arc_condition_codes
[] =
1470 "al", 0, "eq", "ne", "p", "n", "lo", "hs", "v", "nv",
1471 "gt", "le", "ge", "lt", "hi", "ls", "pnz", 0
1474 enum arc_cc_code_index
1476 ARC_CC_AL
, ARC_CC_EQ
= ARC_CC_AL
+2, ARC_CC_NE
, ARC_CC_P
, ARC_CC_N
,
1477 ARC_CC_C
, ARC_CC_NC
, ARC_CC_V
, ARC_CC_NV
,
1478 ARC_CC_GT
, ARC_CC_LE
, ARC_CC_GE
, ARC_CC_LT
, ARC_CC_HI
, ARC_CC_LS
, ARC_CC_PNZ
,
1479 ARC_CC_LO
= ARC_CC_C
, ARC_CC_HS
= ARC_CC_NC
1482 #define ARC_INVERSE_CONDITION_CODE(X) ((X) ^ 1)
1484 /* Returns the index of the ARC condition code string in
1485 `arc_condition_codes'. COMPARISON should be an rtx like
1486 `(eq (...) (...))'. */
1489 get_arc_condition_code (rtx comparison
)
1491 switch (GET_MODE (XEXP (comparison
, 0)))
1494 case E_SImode
: /* For BRcc. */
1495 switch (GET_CODE (comparison
))
1497 case EQ
: return ARC_CC_EQ
;
1498 case NE
: return ARC_CC_NE
;
1499 case GT
: return ARC_CC_GT
;
1500 case LE
: return ARC_CC_LE
;
1501 case GE
: return ARC_CC_GE
;
1502 case LT
: return ARC_CC_LT
;
1503 case GTU
: return ARC_CC_HI
;
1504 case LEU
: return ARC_CC_LS
;
1505 case LTU
: return ARC_CC_LO
;
1506 case GEU
: return ARC_CC_HS
;
1507 default : gcc_unreachable ();
1510 switch (GET_CODE (comparison
))
1512 case EQ
: return ARC_CC_EQ
;
1513 case NE
: return ARC_CC_NE
;
1514 case GE
: return ARC_CC_P
;
1515 case LT
: return ARC_CC_N
;
1516 case GT
: return ARC_CC_PNZ
;
1517 default : gcc_unreachable ();
1520 switch (GET_CODE (comparison
))
1522 case EQ
: return ARC_CC_EQ
;
1523 case NE
: return ARC_CC_NE
;
1524 default : gcc_unreachable ();
1527 switch (GET_CODE (comparison
))
1529 case LTU
: return ARC_CC_C
;
1530 case GEU
: return ARC_CC_NC
;
1531 default : gcc_unreachable ();
1533 case E_CC_FP_GTmode
:
1534 if (TARGET_ARGONAUT_SET
&& TARGET_SPFP
)
1535 switch (GET_CODE (comparison
))
1537 case GT
: return ARC_CC_N
;
1538 case UNLE
: return ARC_CC_P
;
1539 default : gcc_unreachable ();
1542 switch (GET_CODE (comparison
))
1544 case GT
: return ARC_CC_HI
;
1545 case UNLE
: return ARC_CC_LS
;
1546 default : gcc_unreachable ();
1548 case E_CC_FP_GEmode
:
1549 /* Same for FPX and non-FPX. */
1550 switch (GET_CODE (comparison
))
1552 case GE
: return ARC_CC_HS
;
1553 case UNLT
: return ARC_CC_LO
;
1554 default : gcc_unreachable ();
1556 case E_CC_FP_UNEQmode
:
1557 switch (GET_CODE (comparison
))
1559 case UNEQ
: return ARC_CC_EQ
;
1560 case LTGT
: return ARC_CC_NE
;
1561 default : gcc_unreachable ();
1563 case E_CC_FP_ORDmode
:
1564 switch (GET_CODE (comparison
))
1566 case UNORDERED
: return ARC_CC_C
;
1567 case ORDERED
: return ARC_CC_NC
;
1568 default : gcc_unreachable ();
1571 switch (GET_CODE (comparison
))
1573 case EQ
: return ARC_CC_EQ
;
1574 case NE
: return ARC_CC_NE
;
1575 case UNORDERED
: return ARC_CC_C
;
1576 case ORDERED
: return ARC_CC_NC
;
1577 case LTGT
: return ARC_CC_HI
;
1578 case UNEQ
: return ARC_CC_LS
;
1579 default : gcc_unreachable ();
1583 switch (GET_CODE (comparison
))
1585 case EQ
: return ARC_CC_EQ
;
1586 case NE
: return ARC_CC_NE
;
1587 case GT
: return ARC_CC_GT
;
1588 case GE
: return ARC_CC_GE
;
1589 case LT
: return ARC_CC_C
;
1590 case LE
: return ARC_CC_LS
;
1591 case UNORDERED
: return ARC_CC_V
;
1592 case ORDERED
: return ARC_CC_NV
;
1593 case UNGT
: return ARC_CC_HI
;
1594 case UNGE
: return ARC_CC_HS
;
1595 case UNLT
: return ARC_CC_LT
;
1596 case UNLE
: return ARC_CC_LE
;
1597 /* UNEQ and LTGT do not have representation. */
1598 case LTGT
: /* Fall through. */
1599 case UNEQ
: /* Fall through. */
1600 default : gcc_unreachable ();
1602 case E_CC_FPU_UNEQmode
:
1603 switch (GET_CODE (comparison
))
1605 case LTGT
: return ARC_CC_NE
;
1606 case UNEQ
: return ARC_CC_EQ
;
1607 default : gcc_unreachable ();
1609 default : gcc_unreachable ();
1615 /* Return true if COMPARISON has a short form that can accomodate OFFSET. */
1618 arc_short_comparison_p (rtx comparison
, int offset
)
1620 gcc_assert (ARC_CC_NC
== ARC_CC_HS
);
1621 gcc_assert (ARC_CC_C
== ARC_CC_LO
);
1622 switch (get_arc_condition_code (comparison
))
1624 case ARC_CC_EQ
: case ARC_CC_NE
:
1625 return offset
>= -512 && offset
<= 506;
1626 case ARC_CC_GT
: case ARC_CC_LE
: case ARC_CC_GE
: case ARC_CC_LT
:
1627 case ARC_CC_HI
: case ARC_CC_LS
: case ARC_CC_LO
: case ARC_CC_HS
:
1628 return offset
>= -64 && offset
<= 58;
1634 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1635 return the mode to be used for the comparison. */
1638 arc_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
1640 machine_mode mode
= GET_MODE (x
);
1643 /* For an operation that sets the condition codes as a side-effect, the
1644 C and V flags is not set as for cmp, so we can only use comparisons where
1645 this doesn't matter. (For LT and GE we can use "mi" and "pl"
1647 /* ??? We could use "pnz" for greater than zero, however, we could then
1648 get into trouble because the comparison could not be reversed. */
1649 if (GET_MODE_CLASS (mode
) == MODE_INT
1651 && (op
== EQ
|| op
== NE
1652 || ((op
== LT
|| op
== GE
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4)))
1655 /* add.f for if (a+b) */
1657 && GET_CODE (y
) == NEG
1658 && (op
== EQ
|| op
== NE
))
1661 /* Check if this is a test suitable for bxor.f . */
1662 if (mode
== SImode
&& (op
== EQ
|| op
== NE
) && CONST_INT_P (y
)
1663 && ((INTVAL (y
) - 1) & INTVAL (y
)) == 0
1667 /* Check if this is a test suitable for add / bmsk.f . */
1668 if (mode
== SImode
&& (op
== EQ
|| op
== NE
) && CONST_INT_P (y
)
1669 && GET_CODE (x
) == AND
&& CONST_INT_P ((x1
= XEXP (x
, 1)))
1670 && ((INTVAL (x1
) + 1) & INTVAL (x1
)) == 0
1671 && (~INTVAL (x1
) | INTVAL (y
)) < 0
1672 && (~INTVAL (x1
) | INTVAL (y
)) > -0x800)
1675 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
1676 && GET_CODE (x
) == PLUS
1677 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
1680 if (TARGET_ARGONAUT_SET
1681 && ((mode
== SFmode
&& TARGET_SPFP
) || (mode
== DFmode
&& TARGET_DPFP
)))
1684 case EQ
: case NE
: case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
1686 case LT
: case UNGE
: case GT
: case UNLE
:
1687 return CC_FP_GTmode
;
1688 case LE
: case UNGT
: case GE
: case UNLT
:
1689 return CC_FP_GEmode
;
1690 default: gcc_unreachable ();
1692 else if (TARGET_HARD_FLOAT
1693 && ((mode
== SFmode
&& TARGET_FP_SP_BASE
)
1694 || (mode
== DFmode
&& TARGET_FP_DP_BASE
)))
1715 return CC_FPU_UNEQmode
;
1720 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& TARGET_OPTFPE
)
1724 case EQ
: case NE
: return CC_Zmode
;
1726 case GT
: case UNLE
: return CC_FP_GTmode
;
1728 case GE
: case UNLT
: return CC_FP_GEmode
;
1729 case UNEQ
: case LTGT
: return CC_FP_UNEQmode
;
1730 case ORDERED
: case UNORDERED
: return CC_FP_ORDmode
;
1731 default: gcc_unreachable ();
1737 /* Vectors to keep interesting information about registers where it can easily
1738 be got. We use to use the actual mode value as the bit number, but there
1739 is (or may be) more than 32 modes now. Instead we use two tables: one
1740 indexed by hard register number, and one indexed by mode. */
1742 /* The purpose of arc_mode_class is to shrink the range of modes so that
1743 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
1744 mapped into one arc_mode_class mode. */
1746 enum arc_mode_class
{
1748 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
1749 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
1753 /* Modes for condition codes. */
1754 #define C_MODES (1 << (int) C_MODE)
1756 /* Modes for single-word and smaller quantities. */
1757 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
1759 /* Modes for double-word and smaller quantities. */
1760 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
1762 /* Mode for 8-byte DF values only. */
1763 #define DF_MODES (1 << DF_MODE)
1765 /* Modes for quad-word and smaller quantities. */
1766 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
1768 /* Modes for 128-bit vectors. */
1769 #define V_MODES (1 << (int) V_MODE)
1771 /* Value is 1 if register/mode pair is acceptable on arc. */
1773 static unsigned int arc_hard_regno_modes
[] = {
1774 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
1775 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
1776 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, D_MODES
,
1777 D_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1779 /* ??? Leave these as S_MODES for now. */
1780 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1781 DF_MODES
, 0, DF_MODES
, 0, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1782 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1783 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, C_MODES
, S_MODES
,
1785 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1786 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1787 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1788 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1790 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1791 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1792 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1793 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1795 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1796 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1800 static unsigned int arc_mode_class
[NUM_MACHINE_MODES
];
1802 enum reg_class arc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
1805 arc_preferred_reload_class (rtx
, enum reg_class cl
)
1810 /* Initialize the arc_mode_class array. */
1813 arc_init_reg_tables (void)
1817 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1819 machine_mode m
= (machine_mode
) i
;
1821 switch (GET_MODE_CLASS (m
))
1824 case MODE_PARTIAL_INT
:
1825 case MODE_COMPLEX_INT
:
1826 if (GET_MODE_SIZE (m
) <= 4)
1827 arc_mode_class
[i
] = 1 << (int) S_MODE
;
1828 else if (GET_MODE_SIZE (m
) == 8)
1829 arc_mode_class
[i
] = 1 << (int) D_MODE
;
1830 else if (GET_MODE_SIZE (m
) == 16)
1831 arc_mode_class
[i
] = 1 << (int) T_MODE
;
1832 else if (GET_MODE_SIZE (m
) == 32)
1833 arc_mode_class
[i
] = 1 << (int) O_MODE
;
1835 arc_mode_class
[i
] = 0;
1838 case MODE_COMPLEX_FLOAT
:
1839 if (GET_MODE_SIZE (m
) <= 4)
1840 arc_mode_class
[i
] = 1 << (int) SF_MODE
;
1841 else if (GET_MODE_SIZE (m
) == 8)
1842 arc_mode_class
[i
] = 1 << (int) DF_MODE
;
1843 else if (GET_MODE_SIZE (m
) == 16)
1844 arc_mode_class
[i
] = 1 << (int) TF_MODE
;
1845 else if (GET_MODE_SIZE (m
) == 32)
1846 arc_mode_class
[i
] = 1 << (int) OF_MODE
;
1848 arc_mode_class
[i
] = 0;
1850 case MODE_VECTOR_INT
:
1851 if (GET_MODE_SIZE (m
) == 4)
1852 arc_mode_class
[i
] = (1 << (int) S_MODE
);
1853 else if (GET_MODE_SIZE (m
) == 8)
1854 arc_mode_class
[i
] = (1 << (int) D_MODE
);
1856 arc_mode_class
[i
] = (1 << (int) V_MODE
);
1860 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
1861 we must explicitly check for them here. */
1862 if (i
== (int) CCmode
|| i
== (int) CC_ZNmode
|| i
== (int) CC_Zmode
1863 || i
== (int) CC_Cmode
1864 || i
== CC_FP_GTmode
|| i
== CC_FP_GEmode
|| i
== CC_FP_ORDmode
1865 || i
== CC_FPUmode
|| i
== CC_FPUEmode
|| i
== CC_FPU_UNEQmode
)
1866 arc_mode_class
[i
] = 1 << (int) C_MODE
;
1868 arc_mode_class
[i
] = 0;
1874 /* Core registers 56..59 are used for multiply extension options.
1875 The dsp option uses r56 and r57, these are then named acc1 and acc2.
1876 acc1 is the highpart, and acc2 the lowpart, so which register gets which
1877 number depends on endianness.
1878 The mul64 multiplier options use r57 for mlo, r58 for mmid and r59 for mhi.
1879 Because mlo / mhi form a 64 bit value, we use different gcc internal
1880 register numbers to make them form a register pair as the gcc internals
1881 know it. mmid gets number 57, if still available, and mlo / mhi get
1882 number 58 and 59, depending on endianness. We use DBX_REGISTER_NUMBER
1883 to map this back. */
1884 char rname56
[5] = "r56";
1885 char rname57
[5] = "r57";
1886 char rname58
[5] = "r58";
1887 char rname59
[5] = "r59";
1888 char rname29
[7] = "ilink1";
1889 char rname30
[7] = "ilink2";
1892 arc_conditional_register_usage (void)
1896 int fix_start
= 60, fix_end
= 55;
1900 /* For ARCv2 the core register set is changed. */
1901 strcpy (rname29
, "ilink");
1902 strcpy (rname30
, "r30");
1904 if (!TEST_HARD_REG_BIT (overrideregs
, R30_REG
))
1906 /* No user interference. Set the r30 to be used by the
1908 call_used_regs
[R30_REG
] = 1;
1909 fixed_regs
[R30_REG
] = 0;
1911 arc_regno_reg_class
[R30_REG
] = GENERAL_REGS
;
1915 if (TARGET_MUL64_SET
)
1917 fix_start
= R57_REG
;
1920 /* We don't provide a name for mmed. In rtl / assembly resource lists,
1921 you are supposed to refer to it as mlo & mhi, e.g
1922 (zero_extract:SI (reg:DI 58) (const_int 32) (16)) .
1923 In an actual asm instruction, you are of course use mmed.
1924 The point of avoiding having a separate register for mmed is that
1925 this way, we don't have to carry clobbers of that reg around in every
1926 isntruction that modifies mlo and/or mhi. */
1927 strcpy (rname57
, "");
1928 strcpy (rname58
, "mlo");
1929 strcpy (rname59
, "mhi");
1932 /* The nature of arc_tp_regno is actually something more like a global
1933 register, however globalize_reg requires a declaration.
1934 We use EPILOGUE_USES to compensate so that sets from
1935 __builtin_set_frame_pointer are not deleted. */
1936 if (arc_tp_regno
!= -1)
1937 fixed_regs
[arc_tp_regno
] = call_used_regs
[arc_tp_regno
] = 1;
1939 if (TARGET_MULMAC_32BY16_SET
)
1941 fix_start
= MUL32x16_REG
;
1942 fix_end
= fix_end
> R57_REG
? fix_end
: R57_REG
;
1943 strcpy (rname56
, TARGET_BIG_ENDIAN
? "acc1" : "acc2");
1944 strcpy (rname57
, TARGET_BIG_ENDIAN
? "acc2" : "acc1");
1946 for (regno
= fix_start
; regno
<= fix_end
; regno
++)
1948 if (!fixed_regs
[regno
])
1949 warning (0, "multiply option implies r%d is fixed", regno
);
1950 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
1953 /* Reduced configuration: don't use r4-r9, r16-r25. */
1956 for (i
= R4_REG
; i
<= R9_REG
; i
++)
1957 fixed_regs
[i
] = call_used_regs
[i
] = 1;
1958 for (i
= R16_REG
; i
<= R25_REG
; i
++)
1959 fixed_regs
[i
] = call_used_regs
[i
] = 1;
1962 /* ARCHS has 64-bit data-path which makes use of the even-odd paired
1965 for (regno
= R1_REG
; regno
< R32_REG
; regno
+=2)
1966 arc_hard_regno_modes
[regno
] = S_MODES
;
1968 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1971 if ((i
<= R3_REG
) || ((i
>= R12_REG
) && (i
<= R15_REG
)))
1972 arc_regno_reg_class
[i
] = ARCOMPACT16_REGS
;
1974 arc_regno_reg_class
[i
] = GENERAL_REGS
;
1976 else if (i
< LP_COUNT
)
1977 arc_regno_reg_class
[i
] = GENERAL_REGS
;
1979 arc_regno_reg_class
[i
] = NO_REGS
;
1981 /* Handle Special Registers. */
1982 arc_regno_reg_class
[CC_REG
] = NO_REGS
; /* CC_REG: must be NO_REGS. */
1983 arc_regno_reg_class
[FRAME_POINTER_REGNUM
] = GENERAL_REGS
;
1984 arc_regno_reg_class
[ARG_POINTER_REGNUM
] = GENERAL_REGS
;
1987 for (i
= R40_REG
; i
< R44_REG
; ++i
)
1989 arc_regno_reg_class
[i
] = DOUBLE_REGS
;
1990 if (!TARGET_ARGONAUT_SET
)
1991 CLEAR_HARD_REG_BIT (reg_class_contents
[GENERAL_REGS
], i
);
1995 /* Disable all DOUBLE_REGISTER settings, if not generating DPFP
1997 arc_regno_reg_class
[R40_REG
] = ALL_REGS
;
1998 arc_regno_reg_class
[R41_REG
] = ALL_REGS
;
1999 arc_regno_reg_class
[R42_REG
] = ALL_REGS
;
2000 arc_regno_reg_class
[R43_REG
] = ALL_REGS
;
2002 fixed_regs
[R40_REG
] = 1;
2003 fixed_regs
[R41_REG
] = 1;
2004 fixed_regs
[R42_REG
] = 1;
2005 fixed_regs
[R43_REG
] = 1;
2007 arc_hard_regno_modes
[R40_REG
] = 0;
2008 arc_hard_regno_modes
[R42_REG
] = 0;
2011 if (TARGET_SIMD_SET
)
2013 gcc_assert (ARC_FIRST_SIMD_VR_REG
== 64);
2014 gcc_assert (ARC_LAST_SIMD_VR_REG
== 127);
2016 for (i
= ARC_FIRST_SIMD_VR_REG
; i
<= ARC_LAST_SIMD_VR_REG
; i
++)
2017 arc_regno_reg_class
[i
] = SIMD_VR_REGS
;
2019 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_REG
== 128);
2020 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_IN_REG
== 128);
2021 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG
== 136);
2022 gcc_assert (ARC_LAST_SIMD_DMA_CONFIG_REG
== 143);
2024 for (i
= ARC_FIRST_SIMD_DMA_CONFIG_REG
;
2025 i
<= ARC_LAST_SIMD_DMA_CONFIG_REG
; i
++)
2026 arc_regno_reg_class
[i
] = SIMD_DMA_CONFIG_REGS
;
2030 arc_regno_reg_class
[PCL_REG
] = NO_REGS
;
2032 /*ARCV2 Accumulator. */
2034 && (TARGET_FP_DP_FUSED
|| TARGET_FP_SP_FUSED
))
2035 || TARGET_PLUS_DMPY
)
2037 arc_regno_reg_class
[ACCL_REGNO
] = GENERAL_REGS
;
2038 arc_regno_reg_class
[ACCH_REGNO
] = GENERAL_REGS
;
2040 /* Allow the compiler to freely use them. */
2041 if (!TEST_HARD_REG_BIT (overrideregs
, ACCL_REGNO
))
2042 fixed_regs
[ACCL_REGNO
] = 0;
2043 if (!TEST_HARD_REG_BIT (overrideregs
, ACCH_REGNO
))
2044 fixed_regs
[ACCH_REGNO
] = 0;
2046 if (!fixed_regs
[ACCH_REGNO
] && !fixed_regs
[ACCL_REGNO
])
2047 arc_hard_regno_modes
[ACC_REG_FIRST
] = D_MODES
;
2051 /* Implement TARGET_HARD_REGNO_NREGS. */
2054 arc_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
2056 if (GET_MODE_SIZE (mode
) == 16
2057 && regno
>= ARC_FIRST_SIMD_VR_REG
2058 && regno
<= ARC_LAST_SIMD_VR_REG
)
2061 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
2064 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2067 arc_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2069 return (arc_hard_regno_modes
[regno
] & arc_mode_class
[mode
]) != 0;
2072 /* Implement TARGET_MODES_TIEABLE_P. Tie QI/HI/SI modes together. */
2075 arc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2077 return (GET_MODE_CLASS (mode1
) == MODE_INT
2078 && GET_MODE_CLASS (mode2
) == MODE_INT
2079 && GET_MODE_SIZE (mode1
) <= UNITS_PER_WORD
2080 && GET_MODE_SIZE (mode2
) <= UNITS_PER_WORD
);
2083 /* Handle an "interrupt" attribute; arguments as in
2084 struct attribute_spec.handler. */
2087 arc_handle_interrupt_attribute (tree
*, tree name
, tree args
, int,
2092 tree value
= TREE_VALUE (args
);
2094 if (TREE_CODE (value
) != STRING_CST
)
2096 warning (OPT_Wattributes
,
2097 "argument of %qE attribute is not a string constant",
2099 *no_add_attrs
= true;
2102 && strcmp (TREE_STRING_POINTER (value
), "ilink1")
2103 && strcmp (TREE_STRING_POINTER (value
), "ilink2"))
2105 warning (OPT_Wattributes
,
2106 "argument of %qE attribute is not \"ilink1\" or \"ilink2\"",
2108 *no_add_attrs
= true;
2111 && strcmp (TREE_STRING_POINTER (value
), "ilink")
2112 && strcmp (TREE_STRING_POINTER (value
), "firq"))
2114 warning (OPT_Wattributes
,
2115 "argument of %qE attribute is not \"ilink\" or \"firq\"",
2117 *no_add_attrs
= true;
2124 arc_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2125 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2127 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2129 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2131 *no_add_attrs
= true;
2137 /* Type of function DECL.
2139 The result is cached. To reset the cache at the end of a function,
2140 call with DECL = NULL_TREE. */
2143 arc_compute_function_type (struct function
*fun
)
2145 tree attr
, decl
= fun
->decl
;
2146 unsigned int fn_type
= fun
->machine
->fn_type
;
2148 if (fn_type
!= ARC_FUNCTION_UNKNOWN
)
2151 /* Check if it is a naked function. */
2152 if (lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) != NULL_TREE
)
2153 fn_type
|= ARC_FUNCTION_NAKED
;
2155 fn_type
|= ARC_FUNCTION_NORMAL
;
2157 /* Now see if this is an interrupt handler. */
2158 attr
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (decl
));
2159 if (attr
!= NULL_TREE
)
2161 tree value
, args
= TREE_VALUE (attr
);
2163 gcc_assert (list_length (args
) == 1);
2164 value
= TREE_VALUE (args
);
2165 gcc_assert (TREE_CODE (value
) == STRING_CST
);
2167 if (!strcmp (TREE_STRING_POINTER (value
), "ilink1")
2168 || !strcmp (TREE_STRING_POINTER (value
), "ilink"))
2169 fn_type
|= ARC_FUNCTION_ILINK1
;
2170 else if (!strcmp (TREE_STRING_POINTER (value
), "ilink2"))
2171 fn_type
|= ARC_FUNCTION_ILINK2
;
2172 else if (!strcmp (TREE_STRING_POINTER (value
), "firq"))
2173 fn_type
|= ARC_FUNCTION_FIRQ
;
2178 return fun
->machine
->fn_type
= fn_type
;
2181 /* Implement `TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS' */
2184 arc_allocate_stack_slots_for_args (void)
2186 /* Naked functions should not allocate stack slots for arguments. */
2187 unsigned int fn_type
= arc_compute_function_type (cfun
);
2189 return !ARC_NAKED_P(fn_type
);
2192 /* Implement `TARGET_WARN_FUNC_RETURN'. */
2195 arc_warn_func_return (tree decl
)
2197 struct function
*func
= DECL_STRUCT_FUNCTION (decl
);
2198 unsigned int fn_type
= arc_compute_function_type (func
);
2200 return !ARC_NAKED_P (fn_type
);
2203 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
2204 and two if they are nearly compatible (which causes a warning to be
2208 arc_comp_type_attributes (const_tree type1
,
2211 int l1
, l2
, m1
, m2
, s1
, s2
;
2213 /* Check for mismatch of non-default calling convention. */
2214 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2217 /* Check for mismatched call attributes. */
2218 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2219 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2220 m1
= lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2221 m2
= lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2222 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2223 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2225 /* Only bother to check if an attribute is defined. */
2226 if (l1
| l2
| m1
| m2
| s1
| s2
)
2228 /* If one type has an attribute, the other must have the same attribute. */
2229 if ((l1
!= l2
) || (m1
!= m2
) || (s1
!= s2
))
2232 /* Disallow mixed attributes. */
2233 if (l1
+ m1
+ s1
> 1)
2241 /* Misc. utilities. */
2243 /* X and Y are two things to compare using CODE. Emit the compare insn and
2244 return the rtx for the cc reg in the proper mode. */
2247 gen_compare_reg (rtx comparison
, machine_mode omode
)
2249 enum rtx_code code
= GET_CODE (comparison
);
2250 rtx x
= XEXP (comparison
, 0);
2251 rtx y
= XEXP (comparison
, 1);
2253 machine_mode mode
, cmode
;
2256 cmode
= GET_MODE (x
);
2257 if (cmode
== VOIDmode
)
2258 cmode
= GET_MODE (y
);
2259 gcc_assert (cmode
== SImode
|| cmode
== SFmode
|| cmode
== DFmode
);
2260 if (cmode
== SImode
)
2262 if (!register_operand (x
, SImode
))
2264 if (register_operand (y
, SImode
))
2269 code
= swap_condition (code
);
2272 x
= copy_to_mode_reg (SImode
, x
);
2274 if (GET_CODE (y
) == SYMBOL_REF
&& flag_pic
)
2275 y
= copy_to_mode_reg (SImode
, y
);
2279 x
= force_reg (cmode
, x
);
2280 y
= force_reg (cmode
, y
);
2282 mode
= SELECT_CC_MODE (code
, x
, y
);
2284 cc_reg
= gen_rtx_REG (mode
, CC_REG
);
2286 /* ??? FIXME (x-y)==0, as done by both cmpsfpx_raw and
2287 cmpdfpx_raw, is not a correct comparison for floats:
2288 http://www.cygnus-software.com/papers/comparingfloats/comparingfloats.htm
2290 if (TARGET_ARGONAUT_SET
2291 && ((cmode
== SFmode
&& TARGET_SPFP
) || (cmode
== DFmode
&& TARGET_DPFP
)))
2295 case NE
: case EQ
: case LT
: case UNGE
: case LE
: case UNGT
:
2296 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2298 case GT
: case UNLE
: case GE
: case UNLT
:
2299 code
= swap_condition (code
);
2307 if (cmode
== SFmode
)
2309 emit_insn (gen_cmpsfpx_raw (x
, y
));
2313 /* Accepts Dx regs directly by insns. */
2314 emit_insn (gen_cmpdfpx_raw (x
, y
));
2317 if (mode
!= CC_FPXmode
)
2318 emit_insn (gen_rtx_SET (cc_reg
,
2319 gen_rtx_COMPARE (mode
,
2320 gen_rtx_REG (CC_FPXmode
, 61),
2323 else if (TARGET_FPX_QUARK
&& (cmode
== SFmode
))
2327 case NE
: case EQ
: case GT
: case UNLE
: case GE
: case UNLT
:
2328 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2330 case LT
: case UNGE
: case LE
: case UNGT
:
2331 code
= swap_condition (code
);
2340 emit_insn (gen_cmp_quark (cc_reg
,
2341 gen_rtx_COMPARE (mode
, x
, y
)));
2343 else if (TARGET_HARD_FLOAT
2344 && ((cmode
== SFmode
&& TARGET_FP_SP_BASE
)
2345 || (cmode
== DFmode
&& TARGET_FP_DP_BASE
)))
2346 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2347 else if (GET_MODE_CLASS (cmode
) == MODE_FLOAT
&& TARGET_OPTFPE
)
2349 rtx op0
= gen_rtx_REG (cmode
, 0);
2350 rtx op1
= gen_rtx_REG (cmode
, GET_MODE_SIZE (cmode
) / UNITS_PER_WORD
);
2355 case NE
: case EQ
: case GT
: case UNLE
: case GE
: case UNLT
:
2356 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2358 case LT
: case UNGE
: case LE
: case UNGT
:
2359 code
= swap_condition (code
);
2365 if (currently_expanding_to_rtl
)
2373 emit_move_insn (op0
, x
);
2374 emit_move_insn (op1
, y
);
2378 gcc_assert (rtx_equal_p (op0
, x
));
2379 gcc_assert (rtx_equal_p (op1
, y
));
2386 emit_insn (gen_cmp_float (cc_reg
, gen_rtx_COMPARE (mode
, op0
, op1
)));
2389 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2390 return gen_rtx_fmt_ee (code
, omode
, cc_reg
, const0_rtx
);
2393 /* Return true if VALUE, a const_double, will fit in a limm (4 byte number).
2394 We assume the value can be either signed or unsigned. */
2397 arc_double_limm_p (rtx value
)
2399 HOST_WIDE_INT low
, high
;
2401 gcc_assert (GET_CODE (value
) == CONST_DOUBLE
);
2406 low
= CONST_DOUBLE_LOW (value
);
2407 high
= CONST_DOUBLE_HIGH (value
);
2409 if (low
& 0x80000000)
2411 return (((unsigned HOST_WIDE_INT
) low
<= 0xffffffff && high
== 0)
2412 || (((low
& - (unsigned HOST_WIDE_INT
) 0x80000000)
2413 == - (unsigned HOST_WIDE_INT
) 0x80000000)
2418 return (unsigned HOST_WIDE_INT
) low
<= 0x7fffffff && high
== 0;
2422 /* Do any needed setup for a variadic function. For the ARC, we must
2423 create a register parameter block, and then copy any anonymous arguments
2424 in registers to memory.
2426 CUM has not been updated for the last named argument (which is given
2427 by ARG), and we rely on this fact. */
2430 arc_setup_incoming_varargs (cumulative_args_t args_so_far
,
2431 const function_arg_info
&arg
,
2432 int *pretend_size
, int no_rtl
)
2435 CUMULATIVE_ARGS next_cum
;
2437 /* We must treat `__builtin_va_alist' as an anonymous arg. */
2439 next_cum
= *get_cumulative_args (args_so_far
);
2440 arc_function_arg_advance (pack_cumulative_args (&next_cum
), arg
);
2441 first_anon_arg
= next_cum
;
2443 if (FUNCTION_ARG_REGNO_P (first_anon_arg
))
2445 /* First anonymous (unnamed) argument is in a reg. */
2447 /* Note that first_reg_offset < MAX_ARC_PARM_REGS. */
2448 int first_reg_offset
= first_anon_arg
;
2453 = gen_rtx_MEM (BLKmode
, plus_constant (Pmode
, arg_pointer_rtx
,
2454 FIRST_PARM_OFFSET (0)));
2455 move_block_from_reg (first_reg_offset
, regblock
,
2456 MAX_ARC_PARM_REGS
- first_reg_offset
);
2460 = ((MAX_ARC_PARM_REGS
- first_reg_offset
) * UNITS_PER_WORD
);
2464 /* Cost functions. */
2466 /* Provide the costs of an addressing mode that contains ADDR.
2467 If ADDR is not a valid address, its cost is irrelevant. */
2470 arc_address_cost (rtx addr
, machine_mode
, addr_space_t
, bool speed
)
2472 switch (GET_CODE (addr
))
2475 return speed
|| satisfies_constraint_Rcq (addr
) ? 0 : 1;
2476 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
2477 case PRE_MODIFY
: case POST_MODIFY
:
2483 if (TARGET_NPS_CMEM
&& cmem_address (addr
, SImode
))
2485 /* Most likely needs a LIMM. */
2486 return COSTS_N_INSNS (1);
2490 rtx plus0
= XEXP (addr
, 0);
2491 rtx plus1
= XEXP (addr
, 1);
2493 if (GET_CODE (plus0
) != REG
2494 && (GET_CODE (plus0
) != MULT
2495 || !CONST_INT_P (XEXP (plus0
, 1))
2496 || (INTVAL (XEXP (plus0
, 1)) != 2
2497 && INTVAL (XEXP (plus0
, 1)) != 4)))
2500 switch (GET_CODE (plus1
))
2503 return (!RTX_OK_FOR_OFFSET_P (SImode
, plus1
)
2507 : (satisfies_constraint_Rcq (plus0
)
2508 && satisfies_constraint_O (plus1
))
2512 return (speed
< 1 ? 0
2513 : (satisfies_constraint_Rcq (plus0
)
2514 && satisfies_constraint_Rcq (plus1
))
2519 return COSTS_N_INSNS (1);
2532 /* Emit instruction X with the frame related bit set. */
2538 RTX_FRAME_RELATED_P (x
) = 1;
2542 /* Emit a frame insn to move SRC to DST. */
2545 frame_move (rtx dst
, rtx src
)
2547 rtx tmp
= gen_rtx_SET (dst
, src
);
2548 RTX_FRAME_RELATED_P (tmp
) = 1;
2549 return frame_insn (tmp
);
2552 /* Like frame_move, but add a REG_INC note for REG if ADDR contains an
2553 auto increment address, or is zero. */
2556 frame_move_inc (rtx dst
, rtx src
, rtx reg
, rtx addr
)
2558 rtx insn
= frame_move (dst
, src
);
2561 || GET_CODE (addr
) == PRE_DEC
|| GET_CODE (addr
) == POST_INC
2562 || GET_CODE (addr
) == PRE_MODIFY
|| GET_CODE (addr
) == POST_MODIFY
)
2563 add_reg_note (insn
, REG_INC
, reg
);
2567 /* Emit a frame insn which adjusts a frame address register REG by OFFSET. */
2570 frame_add (rtx reg
, HOST_WIDE_INT offset
)
2572 gcc_assert ((offset
& 0x3) == 0);
2575 return frame_move (reg
, plus_constant (Pmode
, reg
, offset
));
2578 /* Emit a frame insn which adjusts stack pointer by OFFSET. */
2581 frame_stack_add (HOST_WIDE_INT offset
)
2583 return frame_add (stack_pointer_rtx
, offset
);
2586 /* Helper function to wrap FRAME_POINTER_NEEDED. We do this as
2587 FRAME_POINTER_NEEDED will not be true until the IRA (Integrated
2588 Register Allocator) pass, while we want to get the frame size
2589 correct earlier than the IRA pass.
2591 When a function uses eh_return we must ensure that the fp register
2592 is saved and then restored so that the unwinder can restore the
2593 correct value for the frame we are going to jump to.
2595 To do this we force all frames that call eh_return to require a
2596 frame pointer (see arc_frame_pointer_required), this
2597 will ensure that the previous frame pointer is stored on entry to
2598 the function, and will then be reloaded at function exit.
2600 As the frame pointer is handled as a special case in our prologue
2601 and epilogue code it must not be saved and restored using the
2602 MUST_SAVE_REGISTER mechanism otherwise we run into issues where GCC
2603 believes that the function is not using a frame pointer and that
2604 the value in the fp register is the frame pointer, while the
2605 prologue and epilogue are busy saving and restoring the fp
2608 During compilation of a function the frame size is evaluated
2609 multiple times, it is not until the reload pass is complete the
2610 frame size is considered fixed (it is at this point that space for
2611 all spills has been allocated). However the frame_pointer_needed
2612 variable is not set true until the register allocation pass, as a
2613 result in the early stages the frame size does not include space
2614 for the frame pointer to be spilled.
2616 The problem that this causes is that the rtl generated for
2617 EH_RETURN_HANDLER_RTX uses the details of the frame size to compute
2618 the offset from the frame pointer at which the return address
2619 lives. However, in early passes GCC has not yet realised we need a
2620 frame pointer, and so has not included space for the frame pointer
2621 in the frame size, and so gets the offset of the return address
2622 wrong. This should not be an issue as in later passes GCC has
2623 realised that the frame pointer needs to be spilled, and has
2624 increased the frame size. However, the rtl for the
2625 EH_RETURN_HANDLER_RTX is not regenerated to use the newer, larger
2626 offset, and the wrong smaller offset is used. */
2629 arc_frame_pointer_needed (void)
2631 return (frame_pointer_needed
|| crtl
->calls_eh_return
);
2634 /* Tell prologue and epilogue if register REGNO should be saved /
2635 restored. The SPECIAL_P is true when the register may need special
2636 ld/st sequence. The return address, and stack pointer are treated
2637 separately. Don't consider them here. */
2640 arc_must_save_register (int regno
, struct function
*func
, bool special_p
)
2642 unsigned int fn_type
= arc_compute_function_type (func
);
2643 bool irq_auto_save_p
= ((irq_ctrl_saved
.irq_save_last_reg
>= regno
)
2644 && ARC_AUTO_IRQ_P (fn_type
));
2645 bool firq_auto_save_p
= ARC_FAST_INTERRUPT_P (fn_type
);
2647 switch (rgf_banked_register_count
)
2650 firq_auto_save_p
&= (regno
< 4);
2653 firq_auto_save_p
&= ((regno
< 4) || ((regno
> 11) && (regno
< 16)));
2656 firq_auto_save_p
&= ((regno
< 4) || ((regno
> 9) && (regno
< 16))
2657 || ((regno
> 25) && (regno
< 29))
2658 || ((regno
> 29) && (regno
< 32)));
2661 firq_auto_save_p
&= (regno
!= 29) && (regno
< 32);
2664 firq_auto_save_p
= false;
2671 case RETURN_ADDR_REGNUM
:
2672 case STACK_POINTER_REGNUM
:
2673 /* The stack pointer and the return address are handled
2678 /* r30 is either used as ilink2 by ARCv1 or as a free register
2689 /* If those ones are used by the FPX machinery, we handle them
2691 if (TARGET_DPFP
&& !special_p
)
2716 /* The Extension Registers. */
2717 if (ARC_INTERRUPT_P (fn_type
)
2718 && (df_regs_ever_live_p (RETURN_ADDR_REGNUM
)
2719 || df_regs_ever_live_p (regno
))
2720 /* Not all extension registers are available, choose the
2722 && !fixed_regs
[regno
])
2728 /* ARC600 specifies those ones as mlo/mhi registers, otherwise
2729 just handle them like any other extension register. */
2730 if (ARC_INTERRUPT_P (fn_type
)
2731 && (df_regs_ever_live_p (RETURN_ADDR_REGNUM
)
2732 || df_regs_ever_live_p (regno
))
2733 /* Not all extension registers are available, choose the
2735 && ((!fixed_regs
[regno
] && !special_p
)
2736 || (TARGET_MUL64_SET
&& special_p
)))
2743 /* Fixed/control register, nothing to do. LP_COUNT is
2747 case HARD_FRAME_POINTER_REGNUM
:
2748 /* If we need FP reg as a frame pointer then don't save it as a
2750 if (arc_frame_pointer_needed ())
2758 if (((df_regs_ever_live_p (regno
) && !call_used_or_fixed_reg_p (regno
))
2759 /* In an interrupt save everything. */
2760 || (ARC_INTERRUPT_P (fn_type
)
2761 && (df_regs_ever_live_p (RETURN_ADDR_REGNUM
)
2762 || df_regs_ever_live_p (regno
))))
2763 /* Do not emit code for auto saved regs. */
2765 && !firq_auto_save_p
)
2770 /* Return true if the return address must be saved in the current function,
2771 otherwise return false. */
2774 arc_must_save_return_addr (struct function
*func
)
2776 if (func
->machine
->frame_info
.save_return_addr
)
2782 /* Return non-zero if there are registers to be saved or loaded using
2783 millicode thunks. We can only use consecutive sequences starting
2784 with r13, and not going beyond r25.
2785 GMASK is a bitmask of registers to save. This function sets
2786 FRAME->millicod_start_reg .. FRAME->millicode_end_reg to the range
2787 of registers to be saved / restored with a millicode call. */
2790 arc_compute_millicode_save_restore_regs (uint64_t gmask
,
2791 struct arc_frame_info
*frame
)
2795 int start_reg
= 13, end_reg
= 25;
2797 for (regno
= start_reg
; regno
<= end_reg
&& (gmask
& (1ULL << regno
));)
2799 end_reg
= regno
- 1;
2800 /* There is no point in using millicode thunks if we don't save/restore
2801 at least three registers. For non-leaf functions we also have the
2803 if (regno
- start_reg
>= 3 - (crtl
->is_leaf
== 0))
2805 frame
->millicode_start_reg
= 13;
2806 frame
->millicode_end_reg
= regno
- 1;
2812 /* Return the bytes needed to compute the frame pointer from the
2813 current stack pointer. */
2816 arc_compute_frame_size (void)
2819 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
2820 unsigned int reg_size
;
2822 struct arc_frame_info
*frame_info
;
2824 unsigned int extra_plus_reg_size
;
2825 unsigned int extra_plus_reg_size_aligned
;
2826 unsigned int fn_type
= arc_compute_function_type (cfun
);
2828 /* The answer might already be known. */
2829 if (cfun
->machine
->frame_info
.initialized
)
2830 return cfun
->machine
->frame_info
.total_size
;
2832 frame_info
= &cfun
->machine
->frame_info
;
2833 size
= ARC_STACK_ALIGN (get_frame_size ());
2835 /* 1) Size of locals and temporaries. */
2838 /* 2) Size of outgoing arguments. */
2839 args_size
= crtl
->outgoing_args_size
;
2841 /* 3) Calculate space needed for saved registers.
2842 ??? We ignore the extension registers for now. */
2844 /* See if this is an interrupt handler. Call used registers must be saved
2850 /* The last 4 regs are special, avoid them. */
2851 for (regno
= 0; regno
<= (GMASK_LEN
- 4); regno
++)
2853 if (arc_must_save_register (regno
, cfun
, false))
2855 reg_size
+= UNITS_PER_WORD
;
2856 gmask
|= 1ULL << regno
;
2860 /* In a frame that calls __builtin_eh_return two data registers are
2861 used to pass values back to the exception handler.
2863 Ensure that these registers are spilled to the stack so that the
2864 exception throw code can find them, and update the saved values.
2865 The handling code will then consume these reloaded values to
2866 handle the exception. */
2867 if (crtl
->calls_eh_return
)
2868 for (regno
= 0; EH_RETURN_DATA_REGNO (regno
) != INVALID_REGNUM
; regno
++)
2870 reg_size
+= UNITS_PER_WORD
;
2871 gmask
|= 1ULL << regno
;
2874 /* Check if we need to save the return address. */
2875 frame_info
->save_return_addr
= (!crtl
->is_leaf
2876 || df_regs_ever_live_p (RETURN_ADDR_REGNUM
)
2877 || crtl
->calls_eh_return
);
2879 /* Saving blink reg for millicode thunk calls. */
2880 if (TARGET_MILLICODE_THUNK_SET
2881 && !ARC_INTERRUPT_P (fn_type
)
2882 && !crtl
->calls_eh_return
)
2884 if (arc_compute_millicode_save_restore_regs (gmask
, frame_info
))
2885 frame_info
->save_return_addr
= true;
2888 /* Save lp_count, lp_start and lp_end. */
2889 if (arc_lpcwidth
!= 0 && arc_must_save_register (LP_COUNT
, cfun
, true))
2890 reg_size
+= UNITS_PER_WORD
* 3;
2892 /* Check for the special R40-R44 regs used by FPX extension. */
2893 if (arc_must_save_register (TARGET_BIG_ENDIAN
? R41_REG
: R40_REG
,
2895 reg_size
+= UNITS_PER_WORD
* 2;
2896 if (arc_must_save_register (TARGET_BIG_ENDIAN
? R43_REG
: R42_REG
,
2898 reg_size
+= UNITS_PER_WORD
* 2;
2900 /* Check for special MLO/MHI case used by ARC600' MUL64
2902 if (arc_must_save_register (R58_REG
, cfun
, TARGET_MUL64_SET
))
2903 reg_size
+= UNITS_PER_WORD
* 2;
2905 /* 4) Calculate extra size made up of the blink + fp size. */
2907 if (arc_must_save_return_addr (cfun
))
2909 /* Add FP size only when it is not autosaved. */
2910 if (arc_frame_pointer_needed ()
2911 && !ARC_AUTOFP_IRQ_P (fn_type
))
2914 /* 5) Space for variable arguments passed in registers */
2915 pretend_size
= crtl
->args
.pretend_args_size
;
2917 /* Ensure everything before the locals is aligned appropriately. */
2918 extra_plus_reg_size
= extra_size
+ reg_size
;
2919 extra_plus_reg_size_aligned
= ARC_STACK_ALIGN (extra_plus_reg_size
);
2920 reg_size
= extra_plus_reg_size_aligned
- extra_size
;
2922 /* Compute total frame size. */
2923 total_size
= var_size
+ args_size
+ extra_size
+ pretend_size
+ reg_size
;
2925 /* It used to be the case that the alignment was forced at this
2926 point. However, that is dangerous, calculations based on
2927 total_size would be wrong. Given that this has never cropped up
2928 as an issue I've changed this to an assert for now. */
2929 gcc_assert (total_size
== ARC_STACK_ALIGN (total_size
));
2931 /* Save computed information. */
2932 frame_info
->total_size
= total_size
;
2933 frame_info
->extra_size
= extra_size
;
2934 frame_info
->pretend_size
= pretend_size
;
2935 frame_info
->var_size
= var_size
;
2936 frame_info
->args_size
= args_size
;
2937 frame_info
->reg_size
= reg_size
;
2938 frame_info
->gmask
= gmask
;
2939 frame_info
->initialized
= reload_completed
;
2941 /* Ok, we're done. */
2945 /* Build dwarf information when the context is saved via AUX_IRQ_CTRL
2949 arc_dwarf_emit_irq_save_regs (void)
2951 rtx tmp
, par
, insn
, reg
;
2954 par
= gen_rtx_SEQUENCE (VOIDmode
,
2955 rtvec_alloc (irq_ctrl_saved
.irq_save_last_reg
+ 1
2956 + irq_ctrl_saved
.irq_save_blink
2957 + irq_ctrl_saved
.irq_save_lpcount
2960 /* Build the stack adjustment note for unwind info. */
2962 offset
= UNITS_PER_WORD
* (irq_ctrl_saved
.irq_save_last_reg
+ 1
2963 + irq_ctrl_saved
.irq_save_blink
2964 + irq_ctrl_saved
.irq_save_lpcount
);
2965 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, -1 * offset
);
2966 tmp
= gen_rtx_SET (stack_pointer_rtx
, tmp
);
2967 RTX_FRAME_RELATED_P (tmp
) = 1;
2968 XVECEXP (par
, 0, j
++) = tmp
;
2970 offset
-= UNITS_PER_WORD
;
2972 /* 1st goes LP_COUNT. */
2973 if (irq_ctrl_saved
.irq_save_lpcount
)
2975 reg
= gen_rtx_REG (SImode
, 60);
2976 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
2977 tmp
= gen_frame_mem (SImode
, tmp
);
2978 tmp
= gen_rtx_SET (tmp
, reg
);
2979 RTX_FRAME_RELATED_P (tmp
) = 1;
2980 XVECEXP (par
, 0, j
++) = tmp
;
2981 offset
-= UNITS_PER_WORD
;
2984 /* 2nd goes BLINK. */
2985 if (irq_ctrl_saved
.irq_save_blink
)
2987 reg
= gen_rtx_REG (SImode
, 31);
2988 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
2989 tmp
= gen_frame_mem (SImode
, tmp
);
2990 tmp
= gen_rtx_SET (tmp
, reg
);
2991 RTX_FRAME_RELATED_P (tmp
) = 1;
2992 XVECEXP (par
, 0, j
++) = tmp
;
2993 offset
-= UNITS_PER_WORD
;
2996 /* Build the parallel of the remaining registers recorded as saved
2998 for (i
= irq_ctrl_saved
.irq_save_last_reg
; i
>= 0; i
--)
3000 reg
= gen_rtx_REG (SImode
, i
);
3001 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
3002 tmp
= gen_frame_mem (SImode
, tmp
);
3003 tmp
= gen_rtx_SET (tmp
, reg
);
3004 RTX_FRAME_RELATED_P (tmp
) = 1;
3005 XVECEXP (par
, 0, j
++) = tmp
;
3006 offset
-= UNITS_PER_WORD
;
3009 /* Dummy insn used to anchor the dwarf info. */
3010 insn
= emit_insn (gen_stack_irq_dwarf());
3011 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, par
);
3012 RTX_FRAME_RELATED_P (insn
) = 1;
3015 /* Helper for prologue: emit frame store with pre_modify or pre_dec to
3016 save register REG on stack. An initial offset OFFSET can be passed
3020 frame_save_reg (rtx reg
, HOST_WIDE_INT offset
)
3026 rtx tmp
= plus_constant (Pmode
, stack_pointer_rtx
,
3027 offset
- GET_MODE_SIZE (GET_MODE (reg
)));
3028 addr
= gen_frame_mem (GET_MODE (reg
),
3029 gen_rtx_PRE_MODIFY (Pmode
,
3034 addr
= gen_frame_mem (GET_MODE (reg
), gen_rtx_PRE_DEC (Pmode
,
3035 stack_pointer_rtx
));
3036 frame_move_inc (addr
, reg
, stack_pointer_rtx
, 0);
3038 return GET_MODE_SIZE (GET_MODE (reg
)) - offset
;
3041 /* Helper used when saving AUX regs during ISR. */
3046 rtx stkslot
= gen_rtx_MEM (GET_MODE (reg
), gen_rtx_PRE_DEC (Pmode
,
3047 stack_pointer_rtx
));
3048 rtx insn
= emit_move_insn (stkslot
, reg
);
3049 RTX_FRAME_RELATED_P (insn
) = 1;
3050 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3051 gen_rtx_SET (stack_pointer_rtx
,
3052 plus_constant (Pmode
, stack_pointer_rtx
,
3053 -GET_MODE_SIZE (GET_MODE (reg
)))));
3054 return GET_MODE_SIZE (GET_MODE (reg
));
3057 /* Helper for epilogue: emit frame load with post_modify or post_inc
3058 to restore register REG from stack. The initial offset is passed
3062 frame_restore_reg (rtx reg
, HOST_WIDE_INT offset
)
3068 rtx tmp
= plus_constant (Pmode
, stack_pointer_rtx
,
3069 offset
+ GET_MODE_SIZE (GET_MODE (reg
)));
3070 addr
= gen_frame_mem (GET_MODE (reg
),
3071 gen_rtx_POST_MODIFY (Pmode
,
3076 addr
= gen_frame_mem (GET_MODE (reg
), gen_rtx_POST_INC (Pmode
,
3077 stack_pointer_rtx
));
3078 insn
= frame_move_inc (reg
, addr
, stack_pointer_rtx
, 0);
3079 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
3081 if (reg
== hard_frame_pointer_rtx
)
3082 add_reg_note (insn
, REG_CFA_DEF_CFA
,
3083 plus_constant (Pmode
, stack_pointer_rtx
,
3084 GET_MODE_SIZE (GET_MODE (reg
)) + offset
));
3086 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3087 gen_rtx_SET (stack_pointer_rtx
,
3088 plus_constant (Pmode
, stack_pointer_rtx
,
3089 GET_MODE_SIZE (GET_MODE (reg
))
3092 return GET_MODE_SIZE (GET_MODE (reg
)) + offset
;
3095 /* Helper used when restoring AUX regs during ISR. */
3100 rtx stkslot
= gen_rtx_MEM (GET_MODE (reg
), gen_rtx_POST_INC (Pmode
,
3101 stack_pointer_rtx
));
3102 rtx insn
= emit_move_insn (reg
, stkslot
);
3103 RTX_FRAME_RELATED_P (insn
) = 1;
3104 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3105 gen_rtx_SET (stack_pointer_rtx
,
3106 plus_constant (Pmode
, stack_pointer_rtx
,
3107 GET_MODE_SIZE (GET_MODE (reg
)))));
3108 return GET_MODE_SIZE (GET_MODE (reg
));
3111 /* Check if we have a continous range to be save/restored with the
3112 help of enter/leave instructions. A vaild register range starts
3113 from $r13 and is up to (including) $r26. */
3116 arc_enter_leave_p (uint64_t gmask
)
3119 unsigned int rmask
= 0;
3124 for (regno
= ENTER_LEAVE_START_REG
;
3125 regno
<= ENTER_LEAVE_END_REG
&& (gmask
& (1ULL << regno
)); regno
++)
3126 rmask
|= 1ULL << regno
;
3134 /* ARC's prologue, save any needed call-saved regs (and call-used if
3135 this is an interrupt handler) for ARCompact ISA, using ST/STD
3139 arc_save_callee_saves (uint64_t gmask
,
3142 HOST_WIDE_INT offset
,
3146 int frame_allocated
= 0;
3149 /* The home-grown ABI says link register is saved first. */
3152 reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3153 frame_allocated
+= frame_save_reg (reg
, offset
);
3157 /* N.B. FRAME_POINTER_MASK and RETURN_ADDR_MASK are cleared in gmask. */
3159 for (i
= GMASK_LEN
; i
>= 0; i
--)
3161 machine_mode save_mode
= SImode
;
3164 && ((i
- 1) % 2 == 0)
3165 && ((gmask
& (1ULL << i
)) != 0)
3166 && ((gmask
& (1ULL << (i
- 1))) != 0))
3171 else if ((gmask
& (1ULL << i
)) == 0)
3174 reg
= gen_rtx_REG (save_mode
, i
);
3175 frame_allocated
+= frame_save_reg (reg
, offset
);
3179 /* Save frame pointer if needed. First save the FP on stack, if not
3180 autosaved. Unfortunately, I cannot add it to gmask and use the
3181 above loop to save fp because our ABI states fp goes aftert all
3182 registers are saved. */
3185 frame_allocated
+= frame_save_reg (hard_frame_pointer_rtx
, offset
);
3189 /* Emit mov fp,sp. */
3191 frame_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3193 return frame_allocated
;
3196 /* ARC's epilogue, restore any required call-saved regs (and call-used
3197 if it is for an interrupt handler) using LD/LDD instructions. */
3200 arc_restore_callee_saves (uint64_t gmask
,
3203 HOST_WIDE_INT offset
,
3204 HOST_WIDE_INT allocated
)
3207 int frame_deallocated
= 0;
3208 HOST_WIDE_INT offs
= cfun
->machine
->frame_info
.reg_size
;
3209 unsigned int fn_type
= arc_compute_function_type (cfun
);
3210 bool early_blink_restore
;
3213 /* Emit mov fp,sp. */
3214 if (arc_frame_pointer_needed () && offset
)
3216 frame_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3217 frame_deallocated
+= offset
;
3223 /* Any offset is taken care by previous if-statement. */
3224 gcc_assert (offset
== 0);
3225 frame_deallocated
+= frame_restore_reg (hard_frame_pointer_rtx
, 0);
3230 /* No $fp involved, we need to do an add to set the $sp to the
3231 location of the first register. */
3232 frame_stack_add (offset
);
3233 frame_deallocated
+= offset
;
3237 /* When we do not optimize for size or we aren't in an interrupt,
3238 restore first blink. */
3239 early_blink_restore
= restore_blink
&& !optimize_size
&& offs
3240 && !ARC_INTERRUPT_P (fn_type
);
3241 if (early_blink_restore
)
3243 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
, offs
);
3244 reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3245 rtx insn
= frame_move_inc (reg
, gen_frame_mem (Pmode
, addr
),
3246 stack_pointer_rtx
, NULL_RTX
);
3247 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
3248 restore_blink
= false;
3251 /* N.B. FRAME_POINTER_MASK and RETURN_ADDR_MASK are cleared in gmask. */
3253 for (i
= 0; i
<= GMASK_LEN
; i
++)
3255 machine_mode restore_mode
= SImode
;
3259 && ((gmask
& (1ULL << i
)) != 0)
3260 && ((gmask
& (1ULL << (i
+ 1))) != 0))
3261 restore_mode
= DImode
;
3262 else if ((gmask
& (1ULL << i
)) == 0)
3265 reg
= gen_rtx_REG (restore_mode
, i
);
3267 switch (restore_mode
)
3270 if ((GMASK_LEN
- __builtin_clzll (gmask
)) == (i
+ 1)
3271 && early_blink_restore
)
3275 if ((GMASK_LEN
- __builtin_clzll (gmask
)) == i
3276 && early_blink_restore
)
3282 frame_deallocated
+= frame_restore_reg (reg
, offs
);
3285 if (restore_mode
== DImode
)
3291 reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3292 frame_deallocated
+= frame_restore_reg (reg
, allocated
3294 /* Consider as well the
3300 return frame_deallocated
;
3303 /* ARC prologue, save the registers using enter instruction. Leave
3304 instruction can also save $blink (SAVE_BLINK) and $fp (SAVE_FP)
3308 arc_save_callee_enter (uint64_t gmask
,
3311 HOST_WIDE_INT offset
)
3313 int start_reg
= ENTER_LEAVE_START_REG
;
3314 int end_reg
= ENTER_LEAVE_END_REG
;
3315 int regno
, indx
, off
, nregs
;
3317 int frame_allocated
= 0;
3319 for (regno
= start_reg
; regno
<= end_reg
&& (gmask
& (1ULL << regno
));)
3322 end_reg
= regno
- 1;
3323 nregs
= end_reg
- start_reg
+ 1;
3324 nregs
+= save_blink
? 1 : 0;
3325 nregs
+= save_fp
? 1 : 0;
3328 frame_stack_add (offset
);
3330 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
+ (save_fp
? 1 : 0)
3334 reg
= gen_rtx_SET (stack_pointer_rtx
,
3335 plus_constant (Pmode
,
3337 -nregs
* UNITS_PER_WORD
));
3338 RTX_FRAME_RELATED_P (reg
) = 1;
3339 XVECEXP (insn
, 0, indx
++) = reg
;
3340 off
= nregs
* UNITS_PER_WORD
;
3344 reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3345 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
3348 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (mem
, reg
);
3349 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
++)) = 1;
3350 off
-= UNITS_PER_WORD
;
3354 for (regno
= start_reg
;
3356 regno
++, indx
++, off
-= UNITS_PER_WORD
)
3358 reg
= gen_rtx_REG (SImode
, regno
);
3359 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3362 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (mem
, reg
);
3363 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
)) = 1;
3364 gmask
= gmask
& ~(1ULL << regno
);
3369 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
3372 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (mem
, hard_frame_pointer_rtx
);
3373 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
++)) = 1;
3374 off
-= UNITS_PER_WORD
;
3376 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (hard_frame_pointer_rtx
,
3378 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
++)) = 1;
3382 gcc_assert (off
== 0);
3383 insn
= frame_insn (insn
);
3385 add_reg_note (insn
, REG_INC
, stack_pointer_rtx
);
3387 frame_allocated
= nregs
* UNITS_PER_WORD
;
3389 /* offset is a negative number, make sure we add it. */
3390 return frame_allocated
- offset
;
3393 /* ARC epilogue, restore the registers using leave instruction. An
3394 initial offset is passed in OFFSET. Besides restoring an register
3395 range, leave can also restore $blink (RESTORE_BLINK), or $fp
3396 (RESTORE_FP), and can automatic return (RETURN_P). */
3399 arc_restore_callee_leave (uint64_t gmask
,
3403 HOST_WIDE_INT offset
)
3405 int start_reg
= ENTER_LEAVE_START_REG
;
3406 int end_reg
= ENTER_LEAVE_END_REG
;
3407 int regno
, indx
, off
, nregs
;
3409 int frame_allocated
= 0;
3411 for (regno
= start_reg
; regno
<= end_reg
&& (gmask
& (1ULL << regno
));)
3414 end_reg
= regno
- 1;
3415 nregs
= end_reg
- start_reg
+ 1;
3416 nregs
+= restore_blink
? 1 : 0;
3417 nregs
+= restore_fp
? 1 : 0;
3419 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
+ 1
3420 + (return_p
? 1 : 0)));
3424 XVECEXP (insn
, 0, indx
++) = ret_rtx
;
3428 /* I cannot emit set (sp, fp) here as cselib expects a single sp
3429 set and not two. Thus, use the offset, and change sp adjust
3431 frame_allocated
+= offset
;
3434 if (offset
&& !restore_fp
)
3436 /* This add is only emmited when we do not restore fp with leave
3438 frame_stack_add (offset
);
3439 frame_allocated
+= offset
;
3443 reg
= gen_rtx_SET (stack_pointer_rtx
,
3444 plus_constant (Pmode
,
3446 offset
+ nregs
* UNITS_PER_WORD
));
3447 RTX_FRAME_RELATED_P (reg
) = 1;
3448 XVECEXP (insn
, 0, indx
++) = reg
;
3449 off
= nregs
* UNITS_PER_WORD
;
3453 reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3454 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
3457 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (reg
, mem
);
3458 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
++)) = 1;
3459 off
-= UNITS_PER_WORD
;
3462 for (regno
= start_reg
;
3464 regno
++, indx
++, off
-= UNITS_PER_WORD
)
3466 reg
= gen_rtx_REG (SImode
, regno
);
3467 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3470 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (reg
, mem
);
3471 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
)) = 1;
3472 gmask
= gmask
& ~(1ULL << regno
);
3477 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
3480 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (hard_frame_pointer_rtx
, mem
);
3481 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
++)) = 1;
3482 off
-= UNITS_PER_WORD
;
3485 gcc_assert (off
== 0);
3488 insn
= emit_jump_insn (insn
);
3489 RTX_FRAME_RELATED_P (insn
) = 1;
3492 insn
= frame_insn (insn
);
3494 add_reg_note (insn
, REG_INC
, stack_pointer_rtx
);
3496 /* Dwarf related info. */
3499 add_reg_note (insn
, REG_CFA_RESTORE
, hard_frame_pointer_rtx
);
3500 add_reg_note (insn
, REG_CFA_DEF_CFA
,
3501 plus_constant (Pmode
, stack_pointer_rtx
,
3502 offset
+ nregs
* UNITS_PER_WORD
));
3506 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3507 gen_rtx_SET (stack_pointer_rtx
,
3508 plus_constant (Pmode
, stack_pointer_rtx
,
3509 nregs
* UNITS_PER_WORD
)));
3512 add_reg_note (insn
, REG_CFA_RESTORE
,
3513 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
3514 for (regno
= start_reg
; regno
<= end_reg
; regno
++)
3515 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (SImode
, regno
));
3517 frame_allocated
+= nregs
* UNITS_PER_WORD
;
3519 return frame_allocated
;
3522 /* Millicode thunks implementation:
3523 Generates calls to millicodes for registers starting from r13 to r25
3524 Present Limitations:
3525 - Only one range supported. The remaining regs will have the ordinary
3526 st and ld instructions for store and loads. Hence a gmask asking
3527 to store r13-14, r16-r25 will only generate calls to store and
3528 load r13 to r14 while store and load insns will be generated for
3529 r16 to r25 in the prologue and epilogue respectively.
3531 - Presently library only supports register ranges starting from r13.
3535 arc_save_callee_milli (uint64_t gmask
,
3538 HOST_WIDE_INT offset
,
3539 HOST_WIDE_INT reg_size
)
3543 int regno
, indx
, off
, nregs
;
3545 int frame_allocated
= 0;
3547 for (regno
= start_reg
; regno
<= end_reg
&& (gmask
& (1ULL << regno
));)
3550 end_reg
= regno
- 1;
3551 nregs
= end_reg
- start_reg
+ 1;
3552 gcc_assert (end_reg
> 14);
3555 /* Allocate space on stack for the registers, and take into account
3556 also the initial offset. The registers will be saved using
3557 offsets. N.B. OFFSET is a negative number. */
3560 reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3561 frame_allocated
+= frame_save_reg (reg
, offset
);
3565 if (reg_size
|| offset
)
3567 frame_stack_add (offset
- reg_size
);
3568 frame_allocated
+= nregs
* UNITS_PER_WORD
- offset
;
3572 /* Start generate millicode call. */
3573 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
+ 1));
3576 /* This is a call, we clobber blink. */
3577 XVECEXP (insn
, 0, nregs
) =
3578 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
3580 for (regno
= start_reg
, indx
= 0, off
= 0;
3582 regno
++, indx
++, off
+= UNITS_PER_WORD
)
3584 reg
= gen_rtx_REG (SImode
, regno
);
3585 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3588 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (mem
, reg
);
3589 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
)) = 1;
3590 gmask
= gmask
& ~(1ULL << regno
);
3592 insn
= frame_insn (insn
);
3594 /* Add DWARF info. */
3595 for (regno
= start_reg
, off
= 0;
3597 regno
++, off
+= UNITS_PER_WORD
)
3599 reg
= gen_rtx_REG (SImode
, regno
);
3600 mem
= gen_rtx_MEM (SImode
, plus_constant (Pmode
,
3601 stack_pointer_rtx
, off
));
3602 add_reg_note (insn
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, reg
));
3606 /* In the case of millicode thunk, we need to restore the
3607 clobbered blink register. */
3608 if (arc_must_save_return_addr (cfun
))
3610 emit_insn (gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
3612 plus_constant (Pmode
,
3617 /* Save remaining registers using st instructions. */
3618 for (regno
= 0; regno
<= GMASK_LEN
; regno
++)
3620 if ((gmask
& (1ULL << regno
)) == 0)
3623 reg
= gen_rtx_REG (SImode
, regno
);
3624 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3627 frame_move_inc (mem
, reg
, stack_pointer_rtx
, 0);
3628 frame_allocated
+= UNITS_PER_WORD
;
3629 off
+= UNITS_PER_WORD
;
3632 /* Save frame pointer if needed. First save the FP on stack, if not
3633 autosaved. Unfortunately, I cannot add it to gmask and use the
3634 above loop to save fp because our ABI states fp goes aftert all
3635 registers are saved. */
3637 frame_allocated
+= frame_save_reg (hard_frame_pointer_rtx
, offset
);
3639 /* Emit mov fp,sp. */
3640 if (arc_frame_pointer_needed ())
3641 frame_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3643 return frame_allocated
;
3646 /* Like the previous function but restore. */
3649 arc_restore_callee_milli (uint64_t gmask
,
3653 HOST_WIDE_INT offset
)
3657 int regno
, indx
, off
, nregs
;
3659 int frame_allocated
= 0;
3661 for (regno
= start_reg
; regno
<= end_reg
&& (gmask
& (1ULL << regno
));)
3664 end_reg
= regno
- 1;
3665 nregs
= end_reg
- start_reg
+ 1;
3666 gcc_assert (end_reg
> 14);
3668 /* Emit mov fp,sp. */
3669 if (arc_frame_pointer_needed () && offset
)
3671 frame_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3672 frame_allocated
= offset
;
3677 frame_allocated
+= frame_restore_reg (hard_frame_pointer_rtx
, 0);
3681 /* No fp involved, hence, we need to adjust the sp via an
3683 frame_stack_add (offset
);
3684 frame_allocated
+= offset
;
3688 /* Start generate millicode call. */
3689 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc ((return_p
? 1 : 0)
3695 /* sibling call, the blink is restored with the help of the
3696 value held into r12. */
3697 reg
= gen_rtx_REG (Pmode
, 12);
3698 XVECEXP (insn
, 0, indx
++) = ret_rtx
;
3699 XVECEXP (insn
, 0, indx
++) =
3700 gen_rtx_SET (stack_pointer_rtx
,
3701 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, reg
));
3702 frame_allocated
+= UNITS_PER_WORD
;
3706 /* This is a call, we clobber blink. */
3707 XVECEXP (insn
, 0, nregs
) =
3708 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
3711 for (regno
= start_reg
, off
= 0;
3713 regno
++, indx
++, off
+= UNITS_PER_WORD
)
3715 reg
= gen_rtx_REG (SImode
, regno
);
3716 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3719 XVECEXP (insn
, 0, indx
) = gen_rtx_SET (reg
, mem
);
3720 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, indx
)) = 1;
3721 gmask
= gmask
& ~(1ULL << regno
);
3724 /* Restore remaining registers using LD instructions. */
3725 for (regno
= 0; regno
<= GMASK_LEN
; regno
++)
3727 if ((gmask
& (1ULL << regno
)) == 0)
3730 reg
= gen_rtx_REG (SImode
, regno
);
3731 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3734 rtx tmp
= frame_move_inc (reg
, mem
, stack_pointer_rtx
, 0);
3735 add_reg_note (tmp
, REG_CFA_RESTORE
, reg
);
3736 off
+= UNITS_PER_WORD
;
3739 /* Emit millicode call. */
3742 reg
= gen_rtx_REG (Pmode
, 12);
3743 frame_insn (gen_rtx_SET (reg
, GEN_INT (off
)));
3744 frame_allocated
+= off
;
3745 insn
= emit_jump_insn (insn
);
3746 RTX_FRAME_RELATED_P (insn
) = 1;
3749 insn
= frame_insn (insn
);
3751 /* Add DWARF info. */
3752 for (regno
= start_reg
; regno
<= end_reg
; regno
++)
3754 reg
= gen_rtx_REG (SImode
, regno
);
3755 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
3759 if (restore_blink
&& !return_p
)
3761 reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3762 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
3764 insn
= frame_insn (gen_rtx_SET (reg
, mem
));
3765 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
3768 return frame_allocated
;
3771 /* Set up the stack and frame pointer (if desired) for the function. */
3774 arc_expand_prologue (void)
3777 uint64_t gmask
= cfun
->machine
->frame_info
.gmask
;
3778 struct arc_frame_info
*frame
= &cfun
->machine
->frame_info
;
3779 unsigned int frame_size_to_allocate
;
3780 int first_offset
= 0;
3781 unsigned int fn_type
= arc_compute_function_type (cfun
);
3782 bool save_blink
= false;
3783 bool save_fp
= false;
3784 bool emit_move
= false;
3786 /* Naked functions don't have prologue. */
3787 if (ARC_NAKED_P (fn_type
))
3789 if (flag_stack_usage_info
)
3790 current_function_static_stack_size
= 0;
3794 /* Compute total frame size. */
3795 size
= arc_compute_frame_size ();
3797 if (flag_stack_usage_info
)
3798 current_function_static_stack_size
= size
;
3800 /* Keep track of frame size to be allocated. */
3801 frame_size_to_allocate
= size
;
3803 /* These cases shouldn't happen. Catch them now. */
3804 gcc_assert (!(size
== 0 && gmask
));
3806 /* Allocate space for register arguments if this is a variadic function. */
3807 if (frame
->pretend_size
!= 0)
3808 first_offset
= -frame
->pretend_size
;
3810 /* IRQ using automatic save mechanism will save the register before
3812 if (ARC_AUTO_IRQ_P (fn_type
)
3813 && !ARC_FAST_INTERRUPT_P (fn_type
))
3815 frame_stack_add (first_offset
);
3817 arc_dwarf_emit_irq_save_regs ();
3820 save_blink
= arc_must_save_return_addr (cfun
)
3821 && !ARC_AUTOBLINK_IRQ_P (fn_type
);
3822 save_fp
= arc_frame_pointer_needed () && !ARC_AUTOFP_IRQ_P (fn_type
)
3823 && !ARC_INTERRUPT_P (fn_type
);
3824 emit_move
= arc_frame_pointer_needed () && !ARC_INTERRUPT_P (fn_type
);
3826 /* Use enter/leave only for non-interrupt functions. */
3827 if (TARGET_CODE_DENSITY
3828 && TARGET_CODE_DENSITY_FRAME
3829 && !ARC_AUTOFP_IRQ_P (fn_type
)
3830 && !ARC_AUTOBLINK_IRQ_P (fn_type
)
3831 && !ARC_INTERRUPT_P (fn_type
)
3832 && arc_enter_leave_p (gmask
))
3833 frame_size_to_allocate
-= arc_save_callee_enter (gmask
, save_blink
,
3836 else if (frame
->millicode_end_reg
> 14)
3837 frame_size_to_allocate
-= arc_save_callee_milli (gmask
, save_blink
,
3842 frame_size_to_allocate
-= arc_save_callee_saves (gmask
, save_blink
, save_fp
,
3843 first_offset
, emit_move
);
3845 /* Check if we need to save the ZOL machinery. */
3846 if (arc_lpcwidth
!= 0 && arc_must_save_register (LP_COUNT
, cfun
, true))
3848 rtx reg0
= gen_rtx_REG (SImode
, R0_REG
);
3849 emit_insn (gen_rtx_SET (reg0
,
3850 gen_rtx_UNSPEC_VOLATILE
3851 (Pmode
, gen_rtvec (1, GEN_INT (AUX_LP_START
)),
3853 frame_size_to_allocate
-= push_reg (reg0
);
3854 emit_insn (gen_rtx_SET (reg0
,
3855 gen_rtx_UNSPEC_VOLATILE
3856 (Pmode
, gen_rtvec (1, GEN_INT (AUX_LP_END
)),
3858 frame_size_to_allocate
-= push_reg (reg0
);
3859 emit_move_insn (reg0
, gen_rtx_REG (SImode
, LP_COUNT
));
3860 frame_size_to_allocate
-= push_reg (reg0
);
3863 /* Save AUX regs used by FPX machinery. */
3864 if (arc_must_save_register (TARGET_BIG_ENDIAN
? R41_REG
: R40_REG
,
3867 rtx reg0
= gen_rtx_REG (SImode
, R0_REG
);
3870 for (i
= 0; i
< 4; i
++)
3872 emit_insn (gen_rtx_SET (reg0
,
3873 gen_rtx_UNSPEC_VOLATILE
3874 (Pmode
, gen_rtvec (1, GEN_INT (AUX_DPFP_START
3877 frame_size_to_allocate
-= push_reg (reg0
);
3881 /* Save ARC600' MUL64 registers. */
3882 if (arc_must_save_register (R58_REG
, cfun
, true))
3883 frame_size_to_allocate
-= arc_save_callee_saves (3ULL << 58,
3884 false, false, 0, false);
3886 if (arc_frame_pointer_needed () && ARC_INTERRUPT_P (fn_type
))
3888 /* Just save fp at the end of the saving context. */
3889 frame_size_to_allocate
-=
3890 arc_save_callee_saves (0, false, !ARC_AUTOFP_IRQ_P (fn_type
), 0, true);
3893 /* Allocate the stack frame. */
3894 if (frame_size_to_allocate
> 0)
3895 frame_stack_add ((HOST_WIDE_INT
) 0 - frame_size_to_allocate
);
3897 /* Emit a blockage to avoid delay slot scheduling. */
3898 emit_insn (gen_blockage ());
3901 /* Return the register number of the register holding the return address
3902 for a function of type TYPE. */
3905 arc_return_address_register (unsigned int fn_type
)
3909 if (ARC_INTERRUPT_P (fn_type
))
3911 if ((fn_type
& (ARC_FUNCTION_ILINK1
| ARC_FUNCTION_FIRQ
)) != 0)
3913 else if ((fn_type
& ARC_FUNCTION_ILINK2
) != 0)
3918 else if (ARC_NORMAL_P (fn_type
) || ARC_NAKED_P (fn_type
))
3919 regno
= RETURN_ADDR_REGNUM
;
3921 gcc_assert (regno
!= 0);
3925 /* Do any necessary cleanup after a function to restore stack, frame,
3929 arc_expand_epilogue (int sibcall_p
)
3932 unsigned int fn_type
= arc_compute_function_type (cfun
);
3933 unsigned int size_to_deallocate
;
3935 int can_trust_sp_p
= !cfun
->calls_alloca
;
3937 bool restore_fp
= arc_frame_pointer_needed () && !ARC_AUTOFP_IRQ_P (fn_type
);
3938 bool restore_blink
= arc_must_save_return_addr (cfun
)
3939 && !ARC_AUTOBLINK_IRQ_P (fn_type
);
3940 uint64_t gmask
= cfun
->machine
->frame_info
.gmask
;
3941 bool return_p
= !sibcall_p
&& fn_type
== ARC_FUNCTION_NORMAL
3942 && !cfun
->machine
->frame_info
.pretend_size
;
3943 struct arc_frame_info
*frame
= &cfun
->machine
->frame_info
;
3945 /* Naked functions don't have epilogue. */
3946 if (ARC_NAKED_P (fn_type
))
3949 size
= arc_compute_frame_size ();
3950 size_to_deallocate
= size
;
3952 first_offset
= size
- (frame
->pretend_size
+ frame
->reg_size
3953 + frame
->extra_size
);
3955 if (!can_trust_sp_p
)
3956 gcc_assert (arc_frame_pointer_needed ());
3958 /* Emit a blockage to avoid/flush all pending sp operations. */
3960 emit_insn (gen_blockage ());
3962 if (ARC_INTERRUPT_P (fn_type
) && restore_fp
)
3964 /* We need to restore FP before any SP operation in an
3966 size_to_deallocate
-= arc_restore_callee_saves (0, false,
3969 size_to_deallocate
);
3974 /* Restore ARC600' MUL64 registers. */
3975 if (arc_must_save_register (R58_REG
, cfun
, true))
3978 rtx reg0
= gen_rtx_REG (SImode
, R0_REG
);
3979 rtx reg1
= gen_rtx_REG (SImode
, R1_REG
);
3980 size_to_deallocate
-= pop_reg (reg0
);
3981 size_to_deallocate
-= pop_reg (reg1
);
3983 insn
= emit_insn (gen_mulu64 (reg0
, const1_rtx
));
3984 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (SImode
, R58_REG
));
3985 RTX_FRAME_RELATED_P (insn
) = 1;
3986 emit_insn (gen_arc600_stall ());
3987 insn
= emit_insn (gen_rtx_UNSPEC_VOLATILE
3988 (VOIDmode
, gen_rtvec (2, reg1
, GEN_INT (AUX_MULHI
)),
3990 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (SImode
, R59_REG
));
3991 RTX_FRAME_RELATED_P (insn
) = 1;
3994 /* Restore AUX-regs used by FPX machinery. */
3995 if (arc_must_save_register (TARGET_BIG_ENDIAN
? R41_REG
: R40_REG
,
3998 rtx reg0
= gen_rtx_REG (SImode
, R0_REG
);
4001 for (i
= 0; i
< 4; i
++)
4003 size_to_deallocate
-= pop_reg (reg0
);
4004 emit_insn (gen_rtx_UNSPEC_VOLATILE
4005 (VOIDmode
, gen_rtvec (2, reg0
, GEN_INT (AUX_DPFP_START
4011 /* Check if we need to restore the ZOL machinery. */
4012 if (arc_lpcwidth
!=0 && arc_must_save_register (LP_COUNT
, cfun
, true))
4014 rtx reg0
= gen_rtx_REG (SImode
, R0_REG
);
4016 size_to_deallocate
-= pop_reg (reg0
);
4017 emit_move_insn (gen_rtx_REG (SImode
, LP_COUNT
), reg0
);
4019 size_to_deallocate
-= pop_reg (reg0
);
4020 emit_insn (gen_rtx_UNSPEC_VOLATILE
4021 (VOIDmode
, gen_rtvec (2, reg0
, GEN_INT (AUX_LP_END
)),
4024 size_to_deallocate
-= pop_reg (reg0
);
4025 emit_insn (gen_rtx_UNSPEC_VOLATILE
4026 (VOIDmode
, gen_rtvec (2, reg0
, GEN_INT (AUX_LP_START
)),
4030 if (TARGET_CODE_DENSITY
4031 && TARGET_CODE_DENSITY_FRAME
4032 && !ARC_AUTOFP_IRQ_P (fn_type
)
4033 && !ARC_AUTOBLINK_IRQ_P (fn_type
)
4034 && !ARC_INTERRUPT_P (fn_type
)
4035 && arc_enter_leave_p (gmask
))
4037 /* Using leave instruction. */
4038 size_to_deallocate
-= arc_restore_callee_leave (gmask
, restore_blink
,
4044 gcc_assert (size_to_deallocate
== 0);
4048 else if (frame
->millicode_end_reg
> 14)
4050 /* Using millicode calls. */
4051 size_to_deallocate
-= arc_restore_callee_milli (gmask
, restore_blink
,
4057 gcc_assert (size_to_deallocate
== 0);
4062 size_to_deallocate
-= arc_restore_callee_saves (gmask
, restore_blink
,
4065 size_to_deallocate
);
4067 /* Keep track of how much of the stack pointer we've restored. It
4068 makes the following a lot more readable. */
4069 restored
= size
- size_to_deallocate
;
4071 if (size
> restored
)
4072 frame_stack_add (size
- restored
);
4074 /* For frames that use __builtin_eh_return, the register defined by
4075 EH_RETURN_STACKADJ_RTX is set to 0 for all standard return paths.
4076 On eh_return paths however, the register is set to the value that
4077 should be added to the stack pointer in order to restore the
4078 correct stack pointer for the exception handling frame.
4080 For ARC we are going to use r2 for EH_RETURN_STACKADJ_RTX, add
4081 this onto the stack for eh_return frames. */
4082 if (crtl
->calls_eh_return
)
4083 emit_insn (gen_add2_insn (stack_pointer_rtx
,
4084 EH_RETURN_STACKADJ_RTX
));
4086 /* Emit the return instruction. */
4087 if (ARC_INTERRUPT_P (fn_type
))
4089 rtx ra
= gen_rtx_REG (Pmode
, arc_return_address_register (fn_type
));
4092 emit_jump_insn (gen_rtie ());
4093 else if (TARGET_ARC700
)
4094 emit_jump_insn (gen_rtie ());
4096 emit_jump_insn (gen_arc600_rtie (ra
));
4098 else if (sibcall_p
== FALSE
)
4099 emit_jump_insn (gen_simple_return ());
4102 /* Helper for {push/pop}_multi_operand: check if rtx OP is a suitable
4103 construct to match either enter or leave instruction. Which one
4104 which is selected by PUSH_P argument. */
4107 arc_check_multi (rtx op
, bool push_p
)
4109 HOST_WIDE_INT len
= XVECLEN (op
, 0);
4110 unsigned int regno
, i
, start
;
4111 unsigned int memp
= push_p
? 0 : 1;
4118 elt
= XVECEXP (op
, 0, 0);
4119 if (!push_p
&& GET_CODE (elt
) == RETURN
)
4122 for (i
= start
, regno
= ENTER_LEAVE_START_REG
; i
< len
; i
++, regno
++)
4124 rtx elt
= XVECEXP (op
, 0, i
);
4127 if (GET_CODE (elt
) != SET
)
4129 mem
= XEXP (elt
, memp
);
4130 reg
= XEXP (elt
, 1 - memp
);
4136 /* Check for blink. */
4137 if (REGNO (reg
) == RETURN_ADDR_REGNUM
4140 else if (REGNO (reg
) == HARD_FRAME_POINTER_REGNUM
)
4142 else if (REGNO (reg
) != regno
)
4145 addr
= XEXP (mem
, 0);
4146 if (GET_CODE (addr
) == PLUS
)
4148 if (!rtx_equal_p (stack_pointer_rtx
, XEXP (addr
, 0))
4149 || !CONST_INT_P (XEXP (addr
, 1)))
4154 if (!rtx_equal_p (stack_pointer_rtx
, addr
))
4161 /* Return rtx for the location of the return address on the stack,
4162 suitable for use in __builtin_eh_return. The new return address
4163 will be written to this location in order to redirect the return to
4164 the exception handler. Our ABI says the blink is pushed first on
4165 stack followed by an unknown number of register saves, and finally
4166 by fp. Hence we cannot use the EH_RETURN_ADDRESS macro as the
4167 stack is not finalized. */
4170 arc_eh_return_address_location (rtx source
)
4174 struct arc_frame_info
*afi
;
4176 arc_compute_frame_size ();
4177 afi
= &cfun
->machine
->frame_info
;
4179 gcc_assert (crtl
->calls_eh_return
);
4180 gcc_assert (afi
->save_return_addr
);
4181 gcc_assert (afi
->extra_size
>= 4);
4183 /* The '-4' removes the size of the return address, which is
4184 included in the 'extra_size' field. */
4185 offset
= afi
->reg_size
+ afi
->extra_size
- 4;
4186 mem
= gen_frame_mem (Pmode
,
4187 plus_constant (Pmode
, hard_frame_pointer_rtx
, offset
));
4189 /* The following should not be needed, and is, really a hack. The
4190 issue being worked around here is that the DSE (Dead Store
4191 Elimination) pass will remove this write to the stack as it sees
4192 a single store and no corresponding read. The read however
4193 occurs in the epilogue code, which is not added into the function
4194 rtl until a later pass. So, at the time of DSE, the decision to
4195 remove this store seems perfectly sensible. Marking the memory
4196 address as volatile obviously has the effect of preventing DSE
4197 from removing the store. */
4198 MEM_VOLATILE_P (mem
) = true;
4199 emit_move_insn (mem
, source
);
4204 /* Helper to generate unspec constant. */
4207 arc_unspec_offset (rtx loc
, int unspec
)
4209 return gen_rtx_CONST (Pmode
, gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, loc
),
4213 /* !TARGET_BARREL_SHIFTER support. */
4214 /* Emit a shift insn to set OP0 to OP1 shifted by OP2; CODE specifies what
4218 emit_shift (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
4220 rtx shift
= gen_rtx_fmt_ee (code
, SImode
, op1
, op2
);
4222 = ((shift4_operator (shift
, SImode
) ? gen_shift_si3
: gen_shift_si3_loop
)
4223 (op0
, op1
, op2
, shift
));
4227 /* Output the assembler code for doing a shift.
4228 We go to a bit of trouble to generate efficient code as the ARC601 only has
4229 single bit shifts. This is taken from the h8300 port. We only have one
4230 mode of shifting and can't access individual bytes like the h8300 can, so
4231 this is greatly simplified (at the expense of not generating hyper-
4234 This function is not used if the variable shift insns are present. */
4236 /* FIXME: This probably can be done using a define_split in arc.md.
4237 Alternately, generate rtx rather than output instructions. */
4240 output_shift (rtx
*operands
)
4242 /* static int loopend_lab;*/
4243 rtx shift
= operands
[3];
4244 machine_mode mode
= GET_MODE (shift
);
4245 enum rtx_code code
= GET_CODE (shift
);
4246 const char *shift_one
;
4248 gcc_assert (mode
== SImode
);
4252 case ASHIFT
: shift_one
= "add %0,%1,%1"; break;
4253 case ASHIFTRT
: shift_one
= "asr %0,%1"; break;
4254 case LSHIFTRT
: shift_one
= "lsr %0,%1"; break;
4255 default: gcc_unreachable ();
4258 if (GET_CODE (operands
[2]) != CONST_INT
)
4260 output_asm_insn ("and.f lp_count,%2, 0x1f", operands
);
4267 n
= INTVAL (operands
[2]);
4269 /* Only consider the lower 5 bits of the shift count. */
4272 /* First see if we can do them inline. */
4273 /* ??? We could get better scheduling & shorter code (using short insns)
4274 by using splitters. Alas, that'd be even more verbose. */
4275 if (code
== ASHIFT
&& n
<= 9 && n
> 2
4276 && dest_reg_operand (operands
[4], SImode
))
4278 output_asm_insn ("mov %4,0\n\tadd3 %0,%4,%1", operands
);
4279 for (n
-=3 ; n
>= 3; n
-= 3)
4280 output_asm_insn ("add3 %0,%4,%0", operands
);
4282 output_asm_insn ("add2 %0,%4,%0", operands
);
4284 output_asm_insn ("add %0,%0,%0", operands
);
4290 output_asm_insn (shift_one
, operands
);
4291 operands
[1] = operands
[0];
4294 /* See if we can use a rotate/and. */
4295 else if (n
== BITS_PER_WORD
- 1)
4300 output_asm_insn ("and %0,%1,1\n\tror %0,%0", operands
);
4303 /* The ARC doesn't have a rol insn. Use something else. */
4304 output_asm_insn ("add.f 0,%1,%1\n\tsbc %0,%0,%0", operands
);
4307 /* The ARC doesn't have a rol insn. Use something else. */
4308 output_asm_insn ("add.f 0,%1,%1\n\trlc %0,0", operands
);
4314 else if (n
== BITS_PER_WORD
- 2 && dest_reg_operand (operands
[4], SImode
))
4319 output_asm_insn ("and %0,%1,3\n\tror %0,%0\n\tror %0,%0", operands
);
4322 #if 1 /* Need some scheduling comparisons. */
4323 output_asm_insn ("add.f %4,%1,%1\n\tsbc %0,%0,%0\n\t"
4324 "add.f 0,%4,%4\n\trlc %0,%0", operands
);
4326 output_asm_insn ("add.f %4,%1,%1\n\tbxor %0,%4,31\n\t"
4327 "sbc.f %0,%0,%4\n\trlc %0,%0", operands
);
4332 output_asm_insn ("add.f %4,%1,%1\n\trlc %0,0\n\t"
4333 "add.f 0,%4,%4\n\trlc %0,%0", operands
);
4335 output_asm_insn ("add.f %0,%1,%1\n\trlc.f %0,0\n\t"
4336 "and %0,%0,1\n\trlc %0,%0", operands
);
4343 else if (n
== BITS_PER_WORD
- 3 && code
== ASHIFT
)
4344 output_asm_insn ("and %0,%1,7\n\tror %0,%0\n\tror %0,%0\n\tror %0,%0",
4349 operands
[2] = GEN_INT (n
);
4350 output_asm_insn ("mov.f lp_count, %2", operands
);
4354 output_asm_insn ("lpnz\t2f", operands
);
4355 output_asm_insn (shift_one
, operands
);
4356 output_asm_insn ("nop", operands
);
4357 fprintf (asm_out_file
, "2:\t%s end single insn loop\n",
4366 /* Nested function support. */
4368 /* Output assembler code for a block containing the constant parts of
4369 a trampoline, leaving space for variable parts. A trampoline looks
4375 .word function's address
4376 .word static chain value
4381 arc_asm_trampoline_template (FILE *f
)
4383 asm_fprintf (f
, "\tld_s\t%s,[pcl,8]\n", ARC_TEMP_SCRATCH_REG
);
4384 asm_fprintf (f
, "\tld\t%s,[pcl,12]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4385 asm_fprintf (f
, "\tj_s\t[%s]\n", ARC_TEMP_SCRATCH_REG
);
4386 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
4387 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
4390 /* Emit RTL insns to initialize the variable parts of a trampoline.
4391 FNADDR is an RTX for the address of the function's pure code. CXT
4392 is an RTX for the static chain value for the function.
4394 The fastest trampoline to execute for trampolines within +-8KB of CTX
4398 j [limm] 0x20200f80 limm
4400 and that would also be faster to write to the stack by computing
4401 the offset from CTX to TRAMP at compile time. However, it would
4402 really be better to get rid of the high cost of cache invalidation
4403 when generating trampolines, which requires that the code part of
4404 trampolines stays constant, and additionally either making sure
4405 that no executable code but trampolines is on the stack, no icache
4406 entries linger for the area of the stack from when before the stack
4407 was allocated, and allocating trampolines in trampoline-only cache
4408 lines or allocate trampolines fram a special pool of pre-allocated
4412 arc_initialize_trampoline (rtx tramp
, tree fndecl
, rtx cxt
)
4414 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4416 emit_block_move (tramp
, assemble_trampoline_template (),
4417 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4418 emit_move_insn (adjust_address (tramp
, SImode
, 8), fnaddr
);
4419 emit_move_insn (adjust_address (tramp
, SImode
, 12), cxt
);
4420 maybe_emit_call_builtin___clear_cache (XEXP (tramp
, 0),
4421 plus_constant (Pmode
,
4426 /* Add the given function declaration to emit code in JLI section. */
4429 arc_add_jli_section (rtx pat
)
4433 arc_jli_section
*sec
= arc_jli_sections
, *new_section
;
4434 tree decl
= SYMBOL_REF_DECL (pat
);
4441 /* For fixed locations do not generate the jli table entry. It
4442 should be provided by the user as an asm file. */
4443 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
4444 if (lookup_attribute ("jli_fixed", attrs
))
4448 name
= XSTR (pat
, 0);
4450 /* Don't insert the same symbol twice. */
4453 if(strcmp (name
, sec
->name
) == 0)
4458 /* New name, insert it. */
4459 new_section
= (arc_jli_section
*) xmalloc (sizeof (arc_jli_section
));
4460 gcc_assert (new_section
!= NULL
);
4461 new_section
->name
= name
;
4462 new_section
->next
= arc_jli_sections
;
4463 arc_jli_sections
= new_section
;
4466 /* This is set briefly to 1 when we output a ".as" address modifer, and then
4467 reset when we output the scaled address. */
4468 static int output_scaled
= 0;
4470 /* Set when we force sdata output. */
4471 static int output_sdata
= 0;
4473 /* Print operand X (an rtx) in assembler syntax to file FILE.
4474 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4475 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4476 /* In final.c:output_asm_insn:
4479 'c' : constant address if CONSTANT_ADDRESS_P
4485 'p': bit Position of lsb
4486 's': size of bit field
4487 '#': condbranch delay slot suffix
4488 '*': jump delay slot suffix
4489 '?' : nonjump-insn suffix for conditional execution or short instruction
4490 '!' : jump / call suffix for conditional execution or short instruction
4491 '`': fold constant inside unary o-perator, re-recognize, and emit.
4495 'S': JLI instruction
4496 'j': used by mov instruction to properly emit jli related labels.
4497 'B': Branch comparison operand - suppress sda reference
4498 'H': Most significant word
4499 'L': Least significant word
4500 'A': ASCII decimal representation of floating point value
4501 'U': Load/store update or scaling indicator
4502 'V': cache bypass indicator for volatile
4507 'o': original symbol - no @ prepending. */
4510 arc_print_operand (FILE *file
, rtx x
, int code
)
4515 if (GET_CODE (x
) == CONST_INT
)
4516 fprintf (file
, "%d",exact_log2(INTVAL (x
) + 1) - 1 );
4518 output_operand_lossage ("invalid operand to %%Z code");
4523 if (GET_CODE (x
) == CONST_INT
)
4524 fprintf (file
, "%d",exact_log2 (INTVAL (x
) & 0xffffffff));
4526 output_operand_lossage ("invalid operand to %%z code");
4531 if (GET_CODE (x
) == CONST_INT
)
4532 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) );
4534 output_operand_lossage ("invalid operands to %%c code");
4539 if (GET_CODE (x
) == CONST_INT
)
4540 fprintf (file
, "%d",exact_log2(~INTVAL (x
)) );
4542 output_operand_lossage ("invalid operand to %%M code");
4547 if (GET_CODE (x
) == CONST_INT
)
4548 fprintf (file
, "%d", exact_log2 (INTVAL (x
) & -INTVAL (x
)));
4550 output_operand_lossage ("invalid operand to %%p code");
4554 if (GET_CODE (x
) == CONST_INT
)
4556 HOST_WIDE_INT i
= INTVAL (x
);
4557 HOST_WIDE_INT s
= exact_log2 (i
& -i
);
4558 fprintf (file
, "%d", exact_log2 (((0xffffffffUL
& i
) >> s
) + 1));
4561 output_operand_lossage ("invalid operand to %%s code");
4565 /* Conditional branches depending on condition codes.
4566 Note that this is only for branches that were known to depend on
4567 condition codes before delay slot scheduling;
4568 out-of-range brcc / bbit expansions should use '*'.
4569 This distinction is important because of the different
4570 allowable delay slot insns and the output of the delay suffix
4571 for TARGET_AT_DBR_COND_EXEC. */
4573 /* Unconditional branches / branches not depending on condition codes.
4574 This could also be a CALL_INSN.
4575 Output the appropriate delay slot suffix. */
4576 if (final_sequence
&& final_sequence
->len () != 1)
4578 rtx_insn
*jump
= final_sequence
->insn (0);
4579 rtx_insn
*delay
= final_sequence
->insn (1);
4581 /* For TARGET_PAD_RETURN we might have grabbed the delay insn. */
4582 if (delay
->deleted ())
4584 if (JUMP_P (jump
) && INSN_ANNULLED_BRANCH_P (jump
))
4585 fputs (INSN_FROM_TARGET_P (delay
) ? ".d"
4586 : TARGET_AT_DBR_CONDEXEC
&& code
== '#' ? ".d"
4587 : get_attr_type (jump
) == TYPE_RETURN
&& code
== '#' ? ""
4594 case '?' : /* with leading "." */
4595 case '!' : /* without leading "." */
4596 /* This insn can be conditionally executed. See if the ccfsm machinery
4597 says it should be conditionalized.
4598 If it shouldn't, we'll check the compact attribute if this insn
4599 has a short variant, which may be used depending on code size and
4600 alignment considerations. */
4601 if (current_insn_predicate
)
4602 arc_ccfsm_current
.cc
4603 = get_arc_condition_code (current_insn_predicate
);
4604 if (ARC_CCFSM_COND_EXEC_P (&arc_ccfsm_current
))
4606 /* Is this insn in a delay slot sequence? */
4607 if (!final_sequence
|| XVECLEN (final_sequence
, 0) < 2
4608 || current_insn_predicate
4609 || CALL_P (final_sequence
->insn (0))
4610 || simplejump_p (final_sequence
->insn (0)))
4612 /* This insn isn't in a delay slot sequence, or conditionalized
4613 independently of its position in a delay slot. */
4614 fprintf (file
, "%s%s",
4615 code
== '?' ? "." : "",
4616 arc_condition_codes
[arc_ccfsm_current
.cc
]);
4617 /* If this is a jump, there are still short variants. However,
4618 only beq_s / bne_s have the same offset range as b_s,
4619 and the only short conditional returns are jeq_s and jne_s. */
4621 && (arc_ccfsm_current
.cc
== ARC_CC_EQ
4622 || arc_ccfsm_current
.cc
== ARC_CC_NE
4623 || 0 /* FIXME: check if branch in 7 bit range. */))
4624 output_short_suffix (file
);
4626 else if (code
== '!') /* Jump with delay slot. */
4627 fputs (arc_condition_codes
[arc_ccfsm_current
.cc
], file
);
4628 else /* An Instruction in a delay slot of a jump or call. */
4630 rtx jump
= XVECEXP (final_sequence
, 0, 0);
4631 rtx insn
= XVECEXP (final_sequence
, 0, 1);
4633 /* If the insn is annulled and is from the target path, we need
4634 to inverse the condition test. */
4635 if (JUMP_P (jump
) && INSN_ANNULLED_BRANCH_P (jump
))
4637 if (INSN_FROM_TARGET_P (insn
))
4638 fprintf (file
, "%s%s",
4639 code
== '?' ? "." : "",
4640 arc_condition_codes
[ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current
.cc
)]);
4642 fprintf (file
, "%s%s",
4643 code
== '?' ? "." : "",
4644 arc_condition_codes
[arc_ccfsm_current
.cc
]);
4645 if (arc_ccfsm_current
.state
== 5)
4646 arc_ccfsm_current
.state
= 0;
4649 /* This insn is executed for either path, so don't
4650 conditionalize it at all. */
4651 output_short_suffix (file
);
4656 output_short_suffix (file
);
4659 /* FIXME: fold constant inside unary operator, re-recognize, and emit. */
4662 fputs (arc_condition_codes
[get_arc_condition_code (x
)], file
);
4665 fputs (arc_condition_codes
[ARC_INVERSE_CONDITION_CODE
4666 (get_arc_condition_code (x
))],
4670 /* Write second word of DImode or DFmode reference,
4671 register or memory. */
4672 if (GET_CODE (x
) == REG
)
4673 fputs (reg_names
[REGNO (x
)+1], file
);
4674 else if (GET_CODE (x
) == MEM
)
4678 /* Handle possible auto-increment. For PRE_INC / PRE_DEC /
4679 PRE_MODIFY, we will have handled the first word already;
4680 For POST_INC / POST_DEC / POST_MODIFY, the access to the
4681 first word will be done later. In either case, the access
4682 to the first word will do the modify, and we only have
4683 to add an offset of four here. */
4684 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
4685 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
4686 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
4687 || GET_CODE (XEXP (x
, 0)) == POST_INC
4688 || GET_CODE (XEXP (x
, 0)) == POST_DEC
4689 || GET_CODE (XEXP (x
, 0)) == POST_MODIFY
)
4690 output_address (VOIDmode
,
4691 plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 4));
4692 else if (output_scaled
)
4694 rtx addr
= XEXP (x
, 0);
4695 int size
= GET_MODE_SIZE (GET_MODE (x
));
4697 output_address (VOIDmode
,
4698 plus_constant (Pmode
, XEXP (addr
, 0),
4699 ((INTVAL (XEXP (addr
, 1)) + 4)
4700 >> (size
== 2 ? 1 : 2))));
4704 output_address (VOIDmode
,
4705 plus_constant (Pmode
, XEXP (x
, 0), 4));
4709 output_operand_lossage ("invalid operand to %%R code");
4713 if (GET_CODE (x
) == SYMBOL_REF
4714 && arc_is_jli_call_p (x
))
4716 if (SYMBOL_REF_DECL (x
))
4718 tree attrs
= (TREE_TYPE (SYMBOL_REF_DECL (x
)) != error_mark_node
4719 ? TYPE_ATTRIBUTES (TREE_TYPE (SYMBOL_REF_DECL (x
)))
4721 if (lookup_attribute ("jli_fixed", attrs
))
4723 /* No special treatment for jli_fixed functions. */
4726 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"\t; @",
4727 TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attrs
))));
4728 assemble_name (file
, XSTR (x
, 0));
4732 fprintf (file
, "@__jli.");
4733 assemble_name (file
, XSTR (x
, 0));
4735 arc_add_jli_section (x
);
4738 if (GET_CODE (x
) == SYMBOL_REF
4739 && arc_is_secure_call_p (x
))
4741 /* No special treatment for secure functions. */
4744 tree attrs
= (TREE_TYPE (SYMBOL_REF_DECL (x
)) != error_mark_node
4745 ? TYPE_ATTRIBUTES (TREE_TYPE (SYMBOL_REF_DECL (x
)))
4747 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"\t; @",
4748 TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attrs
))));
4749 assemble_name (file
, XSTR (x
, 0));
4753 case 'B' /* Branch or other LIMM ref - must not use sda references. */ :
4756 output_addr_const (file
, x
);
4762 if (GET_CODE (x
) == REG
)
4764 /* L = least significant word, H = most significant word. */
4765 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
4766 fputs (reg_names
[REGNO (x
)], file
);
4768 fputs (reg_names
[REGNO (x
)+1], file
);
4770 else if (GET_CODE (x
) == CONST_INT
4771 || GET_CODE (x
) == CONST_DOUBLE
)
4773 rtx first
, second
, word
;
4775 split_double (x
, &first
, &second
);
4777 if((WORDS_BIG_ENDIAN
) == 0)
4778 word
= (code
== 'L' ? first
: second
);
4780 word
= (code
== 'L' ? second
: first
);
4782 fprintf (file
, "0x%08" PRIx32
, ((uint32_t) INTVAL (word
)));
4785 output_operand_lossage ("invalid operand to %%H/%%L code");
4791 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
4792 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
);
4794 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
4795 fprintf (file
, "%s", str
);
4799 /* Output a load/store with update indicator if appropriate. */
4800 if (GET_CODE (x
) == MEM
)
4802 rtx addr
= XEXP (x
, 0);
4803 switch (GET_CODE (addr
))
4805 case PRE_INC
: case PRE_DEC
: case PRE_MODIFY
:
4806 fputs (".a", file
); break;
4807 case POST_INC
: case POST_DEC
: case POST_MODIFY
:
4808 fputs (".ab", file
); break;
4810 /* Are we using a scaled index? */
4811 if (GET_CODE (XEXP (addr
, 0)) == MULT
)
4812 fputs (".as", file
);
4813 /* Can we use a scaled offset? */
4814 else if (CONST_INT_P (XEXP (addr
, 1))
4815 && GET_MODE_SIZE (GET_MODE (x
)) > 1
4816 && (!(INTVAL (XEXP (addr
, 1))
4817 & (GET_MODE_SIZE (GET_MODE (x
)) - 1) & 3))
4818 /* Does it make a difference? */
4819 && !SMALL_INT_RANGE(INTVAL (XEXP (addr
, 1)),
4820 GET_MODE_SIZE (GET_MODE (x
)) - 2, 0))
4822 fputs (".as", file
);
4828 if (legitimate_small_data_address_p (addr
, GET_MODE (x
))
4829 && GET_MODE_SIZE (GET_MODE (x
)) > 1)
4831 int align
= get_symbol_alignment (addr
);
4833 switch (GET_MODE (x
))
4842 if (align
&& ((align
& mask
) == 0))
4843 fputs (".as", file
);
4849 gcc_assert (CONSTANT_P (addr
)); break;
4853 output_operand_lossage ("invalid operand to %%U code");
4856 /* Output cache bypass indicator for a load/store insn. Volatile memory
4857 refs are defined to use the cache bypass mechanism. */
4858 if (GET_CODE (x
) == MEM
)
4860 if ((MEM_VOLATILE_P (x
) && !TARGET_VOLATILE_CACHE_SET
)
4861 || arc_is_uncached_mem_p (x
))
4862 fputs (".di", file
);
4865 output_operand_lossage ("invalid operand to %%V code");
4870 /* Do nothing special. */
4873 fputs (reg_names
[REGNO (x
)]+1, file
);
4876 /* This punctuation character is needed because label references are
4877 printed in the output template using %l. This is a front end
4878 character, and when we want to emit a '@' before it, we have to use
4884 /* Output an operator. */
4885 switch (GET_CODE (x
))
4887 case PLUS
: fputs ("add", file
); return;
4888 case SS_PLUS
: fputs ("adds", file
); return;
4889 case AND
: fputs ("and", file
); return;
4890 case IOR
: fputs ("or", file
); return;
4891 case XOR
: fputs ("xor", file
); return;
4892 case MINUS
: fputs ("sub", file
); return;
4893 case SS_MINUS
: fputs ("subs", file
); return;
4894 case ASHIFT
: fputs ("asl", file
); return;
4895 case ASHIFTRT
: fputs ("asr", file
); return;
4896 case LSHIFTRT
: fputs ("lsr", file
); return;
4897 case ROTATERT
: fputs ("ror", file
); return;
4898 case MULT
: fputs ("mpy", file
); return;
4899 case ABS
: fputs ("abs", file
); return; /* Unconditional. */
4900 case NEG
: fputs ("neg", file
); return;
4901 case SS_NEG
: fputs ("negs", file
); return;
4902 case NOT
: fputs ("not", file
); return; /* Unconditional. */
4904 fputs ("ext", file
); /* bmsk allows predication. */
4906 case SIGN_EXTEND
: /* Unconditional. */
4907 fputs ("sex", file
);
4909 switch (GET_MODE (XEXP (x
, 0)))
4911 case E_QImode
: fputs ("b", file
); return;
4912 case E_HImode
: fputs ("w", file
); return;
4917 if (GET_MODE (x
) != HImode
)
4919 fputs ("sat16", file
);
4922 output_operand_lossage ("invalid operand to %%O code"); return;
4924 if (GET_CODE (x
) == SYMBOL_REF
)
4926 assemble_name (file
, XSTR (x
, 0));
4931 if (TARGET_ANNOTATE_ALIGN
)
4932 fprintf (file
, "; unalign: %d", cfun
->machine
->unalign
);
4948 output_operand_lossage ("invalid operand output code");
4951 switch (GET_CODE (x
))
4954 fputs (reg_names
[REGNO (x
)], file
);
4958 rtx addr
= XEXP (x
, 0);
4959 int size
= GET_MODE_SIZE (GET_MODE (x
));
4961 if (legitimate_small_data_address_p (addr
, GET_MODE (x
)))
4966 switch (GET_CODE (addr
))
4968 case PRE_INC
: case POST_INC
:
4969 output_address (VOIDmode
,
4970 plus_constant (Pmode
, XEXP (addr
, 0), size
)); break;
4971 case PRE_DEC
: case POST_DEC
:
4972 output_address (VOIDmode
,
4973 plus_constant (Pmode
, XEXP (addr
, 0), -size
));
4975 case PRE_MODIFY
: case POST_MODIFY
:
4976 output_address (VOIDmode
, XEXP (addr
, 1)); break;
4980 output_address (VOIDmode
,
4981 plus_constant (Pmode
, XEXP (addr
, 0),
4982 (INTVAL (XEXP (addr
, 1))
4983 >> (size
== 2 ? 1 : 2))));
4987 output_address (VOIDmode
, addr
);
4990 if (flag_pic
&& CONSTANT_ADDRESS_P (addr
))
4991 arc_output_pic_addr_const (file
, addr
, code
);
4993 output_address (VOIDmode
, addr
);
5000 /* We handle SFmode constants here as output_addr_const doesn't. */
5001 if (GET_MODE (x
) == SFmode
)
5005 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
5006 fprintf (file
, "0x%08lx", l
);
5010 /* Let output_addr_const deal with it. */
5013 || (GET_CODE (x
) == CONST
5014 && GET_CODE (XEXP (x
, 0)) == UNSPEC
5015 && (XINT (XEXP (x
, 0), 1) == UNSPEC_TLS_OFF
5016 || XINT (XEXP (x
, 0), 1) == UNSPEC_TLS_GD
))
5017 || (GET_CODE (x
) == CONST
5018 && GET_CODE (XEXP (x
, 0)) == PLUS
5019 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == UNSPEC
5020 && (XINT (XEXP (XEXP (x
, 0), 0), 1) == UNSPEC_TLS_OFF
5021 || XINT (XEXP (XEXP (x
, 0), 0), 1) == UNSPEC_TLS_GD
)))
5022 arc_output_pic_addr_const (file
, x
, code
);
5024 output_addr_const (file
, x
);
5029 /* Print a memory address as an operand to reference that memory location. */
5032 arc_print_operand_address (FILE *file
, rtx addr
)
5034 rtx base
, index
= 0;
5036 switch (GET_CODE (addr
))
5039 fputs (reg_names
[REGNO (addr
)], file
);
5043 fputs ("gp,", file
);
5044 output_addr_const (file
, addr
);
5046 fputs ("@sda", file
);
5050 if (GET_CODE (XEXP (addr
, 0)) == MULT
)
5051 index
= XEXP (XEXP (addr
, 0), 0), base
= XEXP (addr
, 1);
5052 else if (CONST_INT_P (XEXP (addr
, 0)))
5053 index
= XEXP (addr
, 0), base
= XEXP (addr
, 1);
5055 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
5057 gcc_assert (OBJECT_P (base
));
5058 arc_print_operand_address (file
, base
);
5059 if (CONSTANT_P (base
) && CONST_INT_P (index
))
5063 gcc_assert (OBJECT_P (index
));
5064 arc_print_operand_address (file
, index
);
5068 rtx c
= XEXP (addr
, 0);
5070 if ((GET_CODE (c
) == UNSPEC
5071 && (XINT (c
, 1) == UNSPEC_TLS_OFF
5072 || XINT (c
, 1) == UNSPEC_TLS_IE
))
5073 || (GET_CODE (c
) == PLUS
5074 && GET_CODE (XEXP (c
, 0)) == UNSPEC
5075 && (XINT (XEXP (c
, 0), 1) == UNSPEC_TLS_OFF
5076 || XINT (XEXP (c
, 0), 1) == ARC_UNSPEC_GOTOFFPC
)))
5078 arc_output_pic_addr_const (file
, c
, 0);
5081 gcc_assert (GET_CODE (c
) == PLUS
);
5082 gcc_assert (GET_CODE (XEXP (c
, 0)) == SYMBOL_REF
);
5083 gcc_assert (GET_CODE (XEXP (c
, 1)) == CONST_INT
);
5085 output_address (VOIDmode
, XEXP (addr
, 0));
5091 /* We shouldn't get here as we've lost the mode of the memory object
5092 (which says how much to inc/dec by. */
5097 arc_output_pic_addr_const (file
, addr
, 0);
5099 output_addr_const (file
, addr
);
5104 /* Conditional execution support.
5106 This is based on the ARM port but for now is much simpler.
5108 A finite state machine takes care of noticing whether or not instructions
5109 can be conditionally executed, and thus decrease execution time and code
5110 size by deleting branch instructions. The fsm is controlled by
5111 arc_ccfsm_advance (called by arc_final_prescan_insn), and controls the
5112 actions of PRINT_OPERAND. The patterns in the .md file for the branch
5113 insns also have a hand in this. */
5114 /* The way we leave dealing with non-anulled or annull-false delay slot
5115 insns to the consumer is awkward. */
5117 /* The state of the fsm controlling condition codes are:
5118 0: normal, do nothing special
5119 1: don't output this insn
5120 2: don't output this insn
5121 3: make insns conditional
5122 4: make insns conditional
5123 5: make insn conditional (only for outputting anulled delay slot insns)
5125 special value for cfun->machine->uid_ccfsm_state:
5126 6: return with but one insn before it since function start / call
5128 State transitions (state->state by whom, under what condition):
5129 0 -> 1 arc_ccfsm_advance, if insn is a conditional branch skipping over
5131 0 -> 2 arc_ccfsm_advance, if insn is a conditional branch followed
5132 by zero or more non-jump insns and an unconditional branch with
5133 the same target label as the condbranch.
5134 1 -> 3 branch patterns, after having not output the conditional branch
5135 2 -> 4 branch patterns, after having not output the conditional branch
5136 0 -> 5 branch patterns, for anulled delay slot insn.
5137 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL, if the `target' label is reached
5138 (the target label has CODE_LABEL_NUMBER equal to
5139 arc_ccfsm_target_label).
5140 4 -> 0 arc_ccfsm_advance, if `target' unconditional branch is reached
5141 3 -> 1 arc_ccfsm_advance, finding an 'else' jump skipping over some insns.
5142 5 -> 0 when outputting the delay slot insn
5144 If the jump clobbers the conditions then we use states 2 and 4.
5146 A similar thing can be done with conditional return insns.
5148 We also handle separating branches from sets of the condition code.
5149 This is done here because knowledge of the ccfsm state is required,
5150 we may not be outputting the branch. */
5152 /* arc_final_prescan_insn calls arc_ccfsm_advance to adjust arc_ccfsm_current,
5153 before letting final output INSN. */
5156 arc_ccfsm_advance (rtx_insn
*insn
, struct arc_ccfsm
*state
)
5158 /* BODY will hold the body of INSN. */
5161 /* This will be 1 if trying to repeat the trick (ie: do the `else' part of
5162 an if/then/else), and things need to be reversed. */
5165 /* If we start with a return insn, we only succeed if we find another one. */
5166 int seeking_return
= 0;
5168 /* START_INSN will hold the insn from where we start looking. This is the
5169 first insn after the following code_label if REVERSE is true. */
5170 rtx_insn
*start_insn
= insn
;
5172 /* Type of the jump_insn. Brcc insns don't affect ccfsm changes,
5173 since they don't rely on a cmp preceding the. */
5174 enum attr_type jump_insn_type
;
5176 /* Allow -mdebug-ccfsm to turn this off so we can see how well it does.
5177 We can't do this in macro FINAL_PRESCAN_INSN because its called from
5178 final_scan_insn which has `optimize' as a local. */
5179 if (optimize
< 2 || TARGET_NO_COND_EXEC
)
5182 /* Ignore notes and labels. */
5185 body
= PATTERN (insn
);
5186 /* If in state 4, check if the target branch is reached, in order to
5187 change back to state 0. */
5188 if (state
->state
== 4)
5190 if (insn
== state
->target_insn
)
5192 state
->target_insn
= NULL
;
5198 /* If in state 3, it is possible to repeat the trick, if this insn is an
5199 unconditional branch to a label, and immediately following this branch
5200 is the previous target label which is only used once, and the label this
5201 branch jumps to is not too far off. Or in other words "we've done the
5202 `then' part, see if we can do the `else' part." */
5203 if (state
->state
== 3)
5205 if (simplejump_p (insn
))
5207 start_insn
= next_nonnote_insn (start_insn
);
5208 if (GET_CODE (start_insn
) == BARRIER
)
5210 /* ??? Isn't this always a barrier? */
5211 start_insn
= next_nonnote_insn (start_insn
);
5213 if (GET_CODE (start_insn
) == CODE_LABEL
5214 && CODE_LABEL_NUMBER (start_insn
) == state
->target_label
5215 && LABEL_NUSES (start_insn
) == 1)
5220 else if (GET_CODE (body
) == SIMPLE_RETURN
)
5222 start_insn
= next_nonnote_insn (start_insn
);
5223 if (GET_CODE (start_insn
) == BARRIER
)
5224 start_insn
= next_nonnote_insn (start_insn
);
5225 if (GET_CODE (start_insn
) == CODE_LABEL
5226 && CODE_LABEL_NUMBER (start_insn
) == state
->target_label
5227 && LABEL_NUSES (start_insn
) == 1)
5239 if (GET_CODE (insn
) != JUMP_INSN
5240 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
5241 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
5244 /* We can't predicate BRCC or loop ends.
5245 Also, when generating PIC code, and considering a medium range call,
5246 we can't predicate the call. */
5247 jump_insn_type
= get_attr_type (insn
);
5248 if (jump_insn_type
== TYPE_BRCC
5249 || jump_insn_type
== TYPE_BRCC_NO_DELAY_SLOT
5250 || jump_insn_type
== TYPE_LOOP_END
5251 || (jump_insn_type
== TYPE_CALL
&& !get_attr_predicable (insn
)))
5254 /* This jump might be paralleled with a clobber of the condition codes,
5255 the jump should always come first. */
5256 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5257 body
= XVECEXP (body
, 0, 0);
5260 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
5261 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
5263 int insns_skipped
= 0, fail
= FALSE
, succeed
= FALSE
;
5264 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
5265 int then_not_else
= TRUE
;
5266 /* Nonzero if next insn must be the target label. */
5267 int next_must_be_target_label_p
;
5268 rtx_insn
*this_insn
= start_insn
;
5271 /* Register the insn jumped to. */
5274 if (!seeking_return
)
5275 label
= XEXP (SET_SRC (body
), 0);
5277 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
5278 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
5279 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
5281 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
5282 then_not_else
= FALSE
;
5284 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == SIMPLE_RETURN
)
5286 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == SIMPLE_RETURN
)
5289 then_not_else
= FALSE
;
5294 /* If this is a non-annulled branch with a delay slot, there is
5295 no need to conditionalize the delay slot. */
5296 if ((GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) == SEQUENCE
)
5297 && state
->state
== 0 && !INSN_ANNULLED_BRANCH_P (insn
))
5299 this_insn
= NEXT_INSN (this_insn
);
5301 /* See how many insns this branch skips, and what kind of insns. If all
5302 insns are okay, and the label or unconditional branch to the same
5303 label is not too far away, succeed. */
5304 for (insns_skipped
= 0, next_must_be_target_label_p
= FALSE
;
5305 !fail
&& !succeed
&& insns_skipped
< MAX_INSNS_SKIPPED
;
5310 this_insn
= next_nonnote_insn (this_insn
);
5314 if (next_must_be_target_label_p
)
5316 if (GET_CODE (this_insn
) == BARRIER
)
5318 if (GET_CODE (this_insn
) == CODE_LABEL
5319 && this_insn
== label
)
5329 switch (GET_CODE (this_insn
))
5332 /* Succeed if it is the target label, otherwise fail since
5333 control falls in from somewhere else. */
5334 if (this_insn
== label
)
5344 /* Succeed if the following insn is the target label.
5346 If return insns are used then the last insn in a function
5347 will be a barrier. */
5348 next_must_be_target_label_p
= TRUE
;
5352 /* Can handle a call insn if there are no insns after it.
5353 IE: The next "insn" is the target label. We don't have to
5354 worry about delay slots as such insns are SEQUENCE's inside
5355 INSN's. ??? It is possible to handle such insns though. */
5356 if (get_attr_cond (this_insn
) == COND_CANUSE
)
5357 next_must_be_target_label_p
= TRUE
;
5363 scanbody
= PATTERN (this_insn
);
5365 /* If this is an unconditional branch to the same label, succeed.
5366 If it is to another label, do nothing. If it is conditional,
5368 /* ??? Probably, the test for the SET and the PC are
5371 if (GET_CODE (scanbody
) == SET
5372 && GET_CODE (SET_DEST (scanbody
)) == PC
)
5374 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
5375 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
5380 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
5382 else if (get_attr_cond (this_insn
) != COND_CANUSE
)
5385 else if (GET_CODE (scanbody
) == SIMPLE_RETURN
5391 else if (GET_CODE (scanbody
) == PARALLEL
)
5393 if (get_attr_cond (this_insn
) != COND_CANUSE
)
5399 scanbody
= PATTERN (this_insn
);
5401 /* We can only do this with insns that can use the condition
5402 codes (and don't set them). */
5403 if (GET_CODE (scanbody
) == SET
5404 || GET_CODE (scanbody
) == PARALLEL
)
5406 if (get_attr_cond (this_insn
) != COND_CANUSE
)
5409 /* We can't handle other insns like sequences. */
5421 if ((!seeking_return
) && (state
->state
== 1 || reverse
))
5422 state
->target_label
= CODE_LABEL_NUMBER (label
);
5423 else if (seeking_return
|| state
->state
== 2)
5425 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
5427 this_insn
= next_nonnote_insn (this_insn
);
5429 gcc_assert (!this_insn
||
5430 (GET_CODE (this_insn
) != BARRIER
5431 && GET_CODE (this_insn
) != CODE_LABEL
));
5435 /* Oh dear! we ran off the end, give up. */
5436 extract_insn_cached (insn
);
5438 state
->target_insn
= NULL
;
5441 state
->target_insn
= this_insn
;
5446 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
5450 state
->cond
= XEXP (SET_SRC (body
), 0);
5451 state
->cc
= get_arc_condition_code (XEXP (SET_SRC (body
), 0));
5454 if (reverse
|| then_not_else
)
5455 state
->cc
= ARC_INVERSE_CONDITION_CODE (state
->cc
);
5458 /* Restore recog_operand. Getting the attributes of other insns can
5459 destroy this array, but final.c assumes that it remains intact
5460 across this call; since the insn has been recognized already we
5461 call insn_extract direct. */
5462 extract_insn_cached (insn
);
5466 /* Record that we are currently outputting label NUM with prefix PREFIX.
5467 It it's the label we're looking for, reset the ccfsm machinery.
5469 Called from ASM_OUTPUT_INTERNAL_LABEL. */
5472 arc_ccfsm_at_label (const char *prefix
, int num
, struct arc_ccfsm
*state
)
5474 if (state
->state
== 3 && state
->target_label
== num
5475 && !strcmp (prefix
, "L"))
5478 state
->target_insn
= NULL
;
5482 /* We are considering a conditional branch with the condition COND.
5483 Check if we want to conditionalize a delay slot insn, and if so modify
5484 the ccfsm state accordingly.
5485 REVERSE says branch will branch when the condition is false. */
5487 arc_ccfsm_record_condition (rtx cond
, bool reverse
, rtx_insn
*jump
,
5488 struct arc_ccfsm
*state
)
5490 rtx_insn
*seq_insn
= NEXT_INSN (PREV_INSN (jump
));
5492 state
= &arc_ccfsm_current
;
5494 gcc_assert (state
->state
== 0);
5495 if (seq_insn
!= jump
)
5497 rtx insn
= XVECEXP (PATTERN (seq_insn
), 0, 1);
5499 if (!as_a
<rtx_insn
*> (insn
)->deleted ()
5500 && INSN_ANNULLED_BRANCH_P (jump
)
5501 && (TARGET_AT_DBR_CONDEXEC
|| INSN_FROM_TARGET_P (insn
)))
5504 state
->cc
= get_arc_condition_code (cond
);
5506 arc_ccfsm_current
.cc
5507 = ARC_INVERSE_CONDITION_CODE (state
->cc
);
5508 rtx pat
= PATTERN (insn
);
5509 if (GET_CODE (pat
) == COND_EXEC
)
5510 gcc_assert ((INSN_FROM_TARGET_P (insn
)
5511 ? ARC_INVERSE_CONDITION_CODE (state
->cc
) : state
->cc
)
5512 == get_arc_condition_code (XEXP (pat
, 0)));
5519 /* Update *STATE as we would when we emit INSN. */
5522 arc_ccfsm_post_advance (rtx_insn
*insn
, struct arc_ccfsm
*state
)
5524 enum attr_type type
;
5527 arc_ccfsm_at_label ("L", CODE_LABEL_NUMBER (insn
), state
);
5528 else if (JUMP_P (insn
)
5529 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
5530 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
5531 && ((type
= get_attr_type (insn
)) == TYPE_BRANCH
5532 || ((type
== TYPE_UNCOND_BRANCH
5533 || type
== TYPE_RETURN
)
5534 && ARC_CCFSM_BRANCH_DELETED_P (state
))))
5536 if (ARC_CCFSM_BRANCH_DELETED_P (state
))
5537 ARC_CCFSM_RECORD_BRANCH_DELETED (state
);
5540 rtx src
= SET_SRC (PATTERN (insn
));
5541 arc_ccfsm_record_condition (XEXP (src
, 0), XEXP (src
, 1) == pc_rtx
,
5545 else if (arc_ccfsm_current
.state
== 5)
5546 arc_ccfsm_current
.state
= 0;
5549 /* Return true if the current insn, which is a conditional branch, is to be
5553 arc_ccfsm_branch_deleted_p (void)
5555 return ARC_CCFSM_BRANCH_DELETED_P (&arc_ccfsm_current
);
5558 /* Record a branch isn't output because subsequent insns can be
5562 arc_ccfsm_record_branch_deleted (void)
5564 ARC_CCFSM_RECORD_BRANCH_DELETED (&arc_ccfsm_current
);
5567 /* During insn output, indicate if the current insn is predicated. */
5570 arc_ccfsm_cond_exec_p (void)
5572 return (cfun
->machine
->prescan_initialized
5573 && ARC_CCFSM_COND_EXEC_P (&arc_ccfsm_current
));
5576 /* When deciding if an insn should be output short, we want to know something
5577 about the following insns:
5578 - if another insn follows which we know we can output as a short insn
5579 before an alignment-sensitive point, we can output this insn short:
5580 the decision about the eventual alignment can be postponed.
5581 - if a to-be-aligned label comes next, we should output this insn such
5582 as to get / preserve 4-byte alignment.
5583 - if a likely branch without delay slot insn, or a call with an immediately
5584 following short insn comes next, we should out output this insn such as to
5585 get / preserve 2 mod 4 unalignment.
5586 - do the same for a not completely unlikely branch with a short insn
5587 following before any other branch / label.
5588 - in order to decide if we are actually looking at a branch, we need to
5589 call arc_ccfsm_advance.
5590 - in order to decide if we are looking at a short insn, we should know
5591 if it is conditionalized. To a first order of approximation this is
5592 the case if the state from arc_ccfsm_advance from before this insn
5593 indicates the insn is conditionalized. However, a further refinement
5594 could be to not conditionalize an insn if the destination register(s)
5595 is/are dead in the non-executed case. */
5596 /* Return non-zero if INSN should be output as a short insn. UNALIGN is
5597 zero if the current insn is aligned to a 4-byte-boundary, two otherwise.
5598 If CHECK_ATTR is greater than 0, check the iscompact attribute first. */
5601 arc_verify_short (rtx_insn
*insn
, int, int check_attr
)
5603 enum attr_iscompact iscompact
;
5607 iscompact
= get_attr_iscompact (insn
);
5608 if (iscompact
== ISCOMPACT_FALSE
)
5612 return (get_attr_length (insn
) & 2) != 0;
5615 /* When outputting an instruction (alternative) that can potentially be short,
5616 output the short suffix if the insn is in fact short, and update
5617 cfun->machine->unalign accordingly. */
5620 output_short_suffix (FILE *file
)
5622 rtx_insn
*insn
= current_output_insn
;
5626 if (arc_verify_short (insn
, cfun
->machine
->unalign
, 1))
5628 fprintf (file
, "_s");
5629 cfun
->machine
->unalign
^= 2;
5631 /* Restore recog_operand. */
5632 extract_insn_cached (insn
);
5635 /* Implement FINAL_PRESCAN_INSN. */
5638 arc_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
5639 int noperands ATTRIBUTE_UNUSED
)
5641 if (TARGET_DUMPISIZE
)
5642 fprintf (asm_out_file
, "\n; at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
5644 if (!cfun
->machine
->prescan_initialized
)
5646 /* Clear lingering state from branch shortening. */
5647 memset (&arc_ccfsm_current
, 0, sizeof arc_ccfsm_current
);
5648 cfun
->machine
->prescan_initialized
= 1;
5650 arc_ccfsm_advance (insn
, &arc_ccfsm_current
);
5653 /* Given FROM and TO register numbers, say whether this elimination is allowed.
5654 Frame pointer elimination is automatically handled.
5656 All eliminations are permissible. If we need a frame
5657 pointer, we must eliminate ARG_POINTER_REGNUM into
5658 FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5661 arc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
5663 return ((to
== HARD_FRAME_POINTER_REGNUM
) || (to
== STACK_POINTER_REGNUM
));
5666 /* Define the offset between two registers, one to be eliminated, and
5667 the other its replacement, at the start of a routine. */
5670 arc_initial_elimination_offset (int from
, int to
)
5672 if (!cfun
->machine
->frame_info
.initialized
)
5673 arc_compute_frame_size ();
5675 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
5677 return (cfun
->machine
->frame_info
.extra_size
5678 + cfun
->machine
->frame_info
.reg_size
);
5681 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5683 return (cfun
->machine
->frame_info
.total_size
5684 - cfun
->machine
->frame_info
.pretend_size
);
5687 if ((from
== FRAME_POINTER_REGNUM
) && (to
== STACK_POINTER_REGNUM
))
5689 return (cfun
->machine
->frame_info
.total_size
5690 - (cfun
->machine
->frame_info
.pretend_size
5691 + cfun
->machine
->frame_info
.extra_size
5692 + cfun
->machine
->frame_info
.reg_size
));
5694 if ((from
== FRAME_POINTER_REGNUM
) && (to
== HARD_FRAME_POINTER_REGNUM
))
5701 arc_frame_pointer_required (void)
5703 return cfun
->calls_alloca
|| crtl
->calls_eh_return
;
5707 /* Return the destination address of a branch. */
5710 branch_dest (rtx branch
)
5712 rtx pat
= PATTERN (branch
);
5713 rtx dest
= (GET_CODE (pat
) == PARALLEL
5714 ? SET_SRC (XVECEXP (pat
, 0, 0)) : SET_SRC (pat
));
5717 if (GET_CODE (dest
) == IF_THEN_ELSE
)
5718 dest
= XEXP (dest
, XEXP (dest
, 1) == pc_rtx
? 2 : 1);
5720 dest
= XEXP (dest
, 0);
5721 dest_uid
= INSN_UID (dest
);
5723 return INSN_ADDRESSES (dest_uid
);
5727 /* Implement TARGET_ENCODE_SECTION_INFO hook. */
5730 arc_encode_section_info (tree decl
, rtx rtl
, int first
)
5732 /* For sdata, SYMBOL_FLAG_LOCAL and SYMBOL_FLAG_FUNCTION.
5733 This clears machine specific flags, so has to come first. */
5734 default_encode_section_info (decl
, rtl
, first
);
5736 /* Check if it is a function, and whether it has the
5737 [long/medium/short]_call attribute specified. */
5738 if (TREE_CODE (decl
) == FUNCTION_DECL
)
5740 rtx symbol
= XEXP (rtl
, 0);
5741 int flags
= SYMBOL_REF_FLAGS (symbol
);
5743 tree attr
= (TREE_TYPE (decl
) != error_mark_node
5744 ? TYPE_ATTRIBUTES (TREE_TYPE (decl
)) : NULL_TREE
);
5745 tree long_call_attr
= lookup_attribute ("long_call", attr
);
5746 tree medium_call_attr
= lookup_attribute ("medium_call", attr
);
5747 tree short_call_attr
= lookup_attribute ("short_call", attr
);
5749 if (long_call_attr
!= NULL_TREE
)
5750 flags
|= SYMBOL_FLAG_LONG_CALL
;
5751 else if (medium_call_attr
!= NULL_TREE
)
5752 flags
|= SYMBOL_FLAG_MEDIUM_CALL
;
5753 else if (short_call_attr
!= NULL_TREE
)
5754 flags
|= SYMBOL_FLAG_SHORT_CALL
;
5756 SYMBOL_REF_FLAGS (symbol
) = flags
;
5758 else if (TREE_CODE (decl
) == VAR_DECL
)
5760 rtx symbol
= XEXP (rtl
, 0);
5762 tree attr
= (TREE_TYPE (decl
) != error_mark_node
5763 ? DECL_ATTRIBUTES (decl
) : NULL_TREE
);
5765 tree sec_attr
= lookup_attribute ("section", attr
);
5768 const char *sec_name
5769 = TREE_STRING_POINTER (TREE_VALUE (TREE_VALUE (sec_attr
)));
5770 if (strcmp (sec_name
, ".cmem") == 0
5771 || strcmp (sec_name
, ".cmem_shared") == 0
5772 || strcmp (sec_name
, ".cmem_private") == 0)
5773 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_CMEM
;
5778 /* This is how to output a definition of an internal numbered label where
5779 PREFIX is the class of label and NUM is the number within the class. */
5781 static void arc_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
5784 arc_ccfsm_at_label (prefix
, labelno
, &arc_ccfsm_current
);
5785 default_internal_label (stream
, prefix
, labelno
);
5788 /* Set the cpu type and print out other fancy things,
5789 at the top of the file. */
5791 static void arc_file_start (void)
5793 default_file_start ();
5794 fprintf (asm_out_file
, "\t.cpu %s\n", arc_cpu_string
);
5796 /* Set some want to have build attributes. */
5797 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_PCS_config, %d\n",
5799 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_rf16, %d\n",
5800 TARGET_RF16
? 1 : 0);
5801 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_pic, %d\n",
5803 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_tls, %d\n",
5804 (arc_tp_regno
!= -1) ? 1 : 0);
5805 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_sda, %d\n",
5806 TARGET_NO_SDATA_SET
? 0 : 2);
5807 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_ABI_exceptions, %d\n",
5808 TARGET_OPTFPE
? 1 : 0);
5810 asm_fprintf (asm_out_file
, "\t.arc_attribute Tag_ARC_CPU_variation, %d\n",
5811 (arc_tune
< ARC_TUNE_CORE_3
) ? 2 :
5812 (arc_tune
== ARC_TUNE_CORE_3
? 3 : 4));
5815 /* Implement `TARGET_ASM_FILE_END'. */
5816 /* Outputs to the stdio stream FILE jli related text. */
5818 void arc_file_end (void)
5820 arc_jli_section
*sec
= arc_jli_sections
;
5824 fprintf (asm_out_file
, "\n");
5825 fprintf (asm_out_file
, "# JLI entry for function ");
5826 assemble_name (asm_out_file
, sec
->name
);
5827 fprintf (asm_out_file
, "\n\t.section .jlitab, \"axG\", @progbits, "
5829 assemble_name (asm_out_file
, sec
->name
);
5830 fprintf (asm_out_file
,", comdat\n");
5832 fprintf (asm_out_file
, "\t.align\t4\n");
5833 fprintf (asm_out_file
, "__jli.");
5834 assemble_name (asm_out_file
, sec
->name
);
5835 fprintf (asm_out_file
, ":\n\t.weak __jli.");
5836 assemble_name (asm_out_file
, sec
->name
);
5837 fprintf (asm_out_file
, "\n\tb\t@");
5838 assemble_name (asm_out_file
, sec
->name
);
5839 fprintf (asm_out_file
, "\n");
5842 file_end_indicate_exec_stack ();
5845 /* Cost functions. */
5847 /* Compute a (partial) cost for rtx X. Return true if the complete
5848 cost has been computed, and false if subexpressions should be
5849 scanned. In either case, *TOTAL contains the cost result. */
5852 arc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
5853 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
5855 int code
= GET_CODE (x
);
5859 /* Small integers are as cheap as registers. */
5862 bool nolimm
= false; /* Can we do without long immediate? */
5865 if (UNSIGNED_INT6 (INTVAL (x
)))
5871 case AND
: /* bclr, bmsk, ext[bw] */
5872 if (satisfies_constraint_Ccp (x
) /* bclr */
5873 || satisfies_constraint_C1p (x
) /* bmsk */)
5876 case IOR
: /* bset */
5877 if (satisfies_constraint_C0p (x
)) /* bset */
5881 if (satisfies_constraint_C0p (x
)) /* bxor */
5885 if (UNSIGNED_INT8 (INTVAL (x
)))
5887 if (satisfies_constraint_Chi (x
))
5889 if (satisfies_constraint_Clo (x
))
5893 if (TARGET_MUL64_SET
)
5894 if (SIGNED_INT12 (INTVAL (x
)))
5909 /* 4 byte values can be fetched as immediate constants -
5910 let's give that the cost of an extra insn. */
5914 *total
= speed
? COSTS_N_INSNS (1) : COSTS_N_INSNS (4);
5923 *total
= COSTS_N_INSNS (1);
5926 split_double (x
, &first
, &second
);
5927 *total
= COSTS_N_INSNS (!SMALL_INT (INTVAL (first
))
5928 + !SMALL_INT (INTVAL (second
)));
5932 /* Encourage synth_mult to find a synthetic multiply when reasonable.
5933 If we need more than 12 insns to do a multiply, then go out-of-line,
5934 since the call overhead will be < 10% of the cost of the multiply. */
5938 if (TARGET_BARREL_SHIFTER
)
5940 if (CONSTANT_P (XEXP (x
, 0)))
5942 *total
+= rtx_cost (XEXP (x
, 1), mode
, (enum rtx_code
) code
,
5946 *total
= COSTS_N_INSNS (1);
5948 else if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5949 *total
= COSTS_N_INSNS (16);
5952 *total
= COSTS_N_INSNS (INTVAL (XEXP ((x
), 1)));
5953 /* ??? want_to_gcse_p can throw negative shift counts at us,
5954 and then panics when it gets a negative cost as result.
5955 Seen for gcc.c-torture/compile/20020710-1.c -Os . */
5963 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5964 && (TARGET_FP_SP_SQRT
|| TARGET_FP_DP_SQRT
))
5965 *total
= COSTS_N_INSNS(1);
5966 else if (GET_MODE_CLASS (mode
) == MODE_INT
5968 *total
= COSTS_N_INSNS(1);
5970 *total
= COSTS_N_INSNS(30);
5972 *total
= COSTS_N_INSNS(1);
5976 if ((TARGET_DPFP
&& GET_MODE (x
) == DFmode
))
5977 *total
= COSTS_N_INSNS (1);
5979 *total
= arc_multcost
;
5980 /* We do not want synth_mult sequences when optimizing
5982 else if (TARGET_ANY_MPY
)
5983 *total
= COSTS_N_INSNS (1);
5985 *total
= COSTS_N_INSNS (2);
5989 if (outer_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
5990 && RTX_OK_FOR_OFFSET_P (mode
, XEXP (x
, 1)))
5996 if ((GET_CODE (XEXP (x
, 0)) == ASHIFT
5997 && _1_2_3_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
5998 || (GET_CODE (XEXP (x
, 0)) == MULT
5999 && _2_4_8_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
)))
6001 if (CONSTANT_P (XEXP (x
, 1)) && !speed
)
6002 *total
+= COSTS_N_INSNS (4);
6003 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), mode
, PLUS
, 1, speed
);
6008 if ((GET_CODE (XEXP (x
, 1)) == ASHIFT
6009 && _1_2_3_operand (XEXP (XEXP (x
, 1), 1), VOIDmode
))
6010 || (GET_CODE (XEXP (x
, 1)) == MULT
6011 && _2_4_8_operand (XEXP (XEXP (x
, 1), 1), VOIDmode
)))
6013 if (CONSTANT_P (XEXP (x
, 0)) && !speed
)
6014 *total
+= COSTS_N_INSNS (4);
6015 *total
+= rtx_cost (XEXP (XEXP (x
, 1), 0), mode
, PLUS
, 1, speed
);
6022 rtx op0
= XEXP (x
, 0);
6023 rtx op1
= XEXP (x
, 1);
6025 if (GET_CODE (op0
) == ZERO_EXTRACT
&& op1
== const0_rtx
6026 && XEXP (op0
, 1) == const1_rtx
)
6028 /* btst / bbit0 / bbit1:
6029 Small integers and registers are free; everything else can
6030 be put in a register. */
6031 mode
= GET_MODE (XEXP (op0
, 0));
6032 *total
= (rtx_cost (XEXP (op0
, 0), mode
, SET
, 1, speed
)
6033 + rtx_cost (XEXP (op0
, 2), mode
, SET
, 1, speed
));
6036 if (GET_CODE (op0
) == AND
&& op1
== const0_rtx
6037 && satisfies_constraint_C1p (XEXP (op0
, 1)))
6040 *total
= rtx_cost (XEXP (op0
, 0), VOIDmode
, SET
, 1, speed
);
6044 if (GET_CODE (op1
) == NEG
)
6046 /* op0 might be constant, the inside of op1 is rather
6047 unlikely to be so. So swapping the operands might lower
6049 mode
= GET_MODE (op0
);
6050 *total
= (rtx_cost (op0
, mode
, PLUS
, 1, speed
)
6051 + rtx_cost (XEXP (op1
, 0), mode
, PLUS
, 0, speed
));
6056 if (outer_code
== IF_THEN_ELSE
6057 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTRACT
6058 && XEXP (x
, 1) == const0_rtx
6059 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
6061 /* btst / bbit0 / bbit1:
6062 Small integers and registers are free; everything else can
6063 be put in a register. */
6064 rtx op0
= XEXP (x
, 0);
6066 mode
= GET_MODE (XEXP (op0
, 0));
6067 *total
= (rtx_cost (XEXP (op0
, 0), mode
, SET
, 1, speed
)
6068 + rtx_cost (XEXP (op0
, 2), mode
, SET
, 1, speed
));
6072 /* scc_insn expands into two insns. */
6073 case GTU
: case GEU
: case LEU
:
6075 *total
+= COSTS_N_INSNS (1);
6077 case LTU
: /* might use adc. */
6079 *total
+= COSTS_N_INSNS (1) - 1;
6086 /* Return true if ADDR is a valid pic address.
6087 A valid pic address on arc should look like
6088 const (unspec (SYMBOL_REF/LABEL) (ARC_UNSPEC_GOTOFF/ARC_UNSPEC_GOT)) */
6091 arc_legitimate_pic_addr_p (rtx addr
)
6093 if (GET_CODE (addr
) != CONST
)
6096 addr
= XEXP (addr
, 0);
6099 if (GET_CODE (addr
) == PLUS
)
6101 if (GET_CODE (XEXP (addr
, 1)) != CONST_INT
)
6103 addr
= XEXP (addr
, 0);
6106 if (GET_CODE (addr
) != UNSPEC
6107 || XVECLEN (addr
, 0) != 1)
6110 /* Must be one of @GOT, @GOTOFF, @GOTOFFPC, @tlsgd, tlsie. */
6111 if (XINT (addr
, 1) != ARC_UNSPEC_GOT
6112 && XINT (addr
, 1) != ARC_UNSPEC_GOTOFF
6113 && XINT (addr
, 1) != ARC_UNSPEC_GOTOFFPC
6114 && XINT (addr
, 1) != UNSPEC_TLS_GD
6115 && XINT (addr
, 1) != UNSPEC_TLS_IE
)
6118 if (GET_CODE (XVECEXP (addr
, 0, 0)) != SYMBOL_REF
6119 && GET_CODE (XVECEXP (addr
, 0, 0)) != LABEL_REF
)
6127 /* Return true if OP contains a symbol reference. */
6130 symbolic_reference_mentioned_p (rtx op
)
6135 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
6138 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
6139 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
6145 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
6146 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
6150 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
6157 /* Return true if OP contains a SYMBOL_REF that is not wrapped in an unspec.
6158 If SKIP_LOCAL is true, skip symbols that bind locally.
6159 This is used further down in this file, and, without SKIP_LOCAL,
6160 in the addsi3 / subsi3 expanders when generating PIC code. */
6163 arc_raw_symbolic_reference_mentioned_p (rtx op
, bool skip_local
)
6168 if (GET_CODE(op
) == UNSPEC
)
6171 if (GET_CODE (op
) == SYMBOL_REF
)
6173 if (SYMBOL_REF_TLS_MODEL (op
))
6177 tree decl
= SYMBOL_REF_DECL (op
);
6178 return !skip_local
|| !decl
|| !default_binds_local_p (decl
);
6181 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
6182 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
6188 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
6189 if (arc_raw_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
),
6194 else if (fmt
[i
] == 'e'
6195 && arc_raw_symbolic_reference_mentioned_p (XEXP (op
, i
),
6203 /* The __tls_get_attr symbol. */
6204 static GTY(()) rtx arc_tls_symbol
;
6206 /* Emit a call to __tls_get_addr. TI is the argument to this function.
6207 RET is an RTX for the return value location. The entire insn sequence
6211 arc_call_tls_get_addr (rtx ti
)
6213 rtx arg
= gen_rtx_REG (Pmode
, R0_REG
);
6214 rtx ret
= gen_rtx_REG (Pmode
, R0_REG
);
6218 if (!arc_tls_symbol
)
6219 arc_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6221 emit_move_insn (arg
, ti
);
6222 fn
= gen_rtx_MEM (SImode
, arc_tls_symbol
);
6223 insn
= emit_call_insn (gen_call_value (ret
, fn
, const0_rtx
));
6224 RTL_CONST_CALL_P (insn
) = 1;
6225 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), ret
);
6226 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), arg
);
6231 #define DTPOFF_ZERO_SYM ".tdata"
6233 /* Return a legitimized address for ADDR,
6234 which is a SYMBOL_REF with tls_model MODEL. */
6237 arc_legitimize_tls_address (rtx addr
, enum tls_model model
)
6241 if (!flag_pic
&& model
== TLS_MODEL_LOCAL_DYNAMIC
)
6242 model
= TLS_MODEL_LOCAL_EXEC
;
6245 /* The TP pointer needs to be set. */
6246 gcc_assert (arc_tp_regno
!= -1);
6250 case TLS_MODEL_GLOBAL_DYNAMIC
:
6251 tmp
= gen_reg_rtx (Pmode
);
6252 emit_move_insn (tmp
, arc_unspec_offset (addr
, UNSPEC_TLS_GD
));
6253 return arc_call_tls_get_addr (tmp
);
6255 case TLS_MODEL_LOCAL_DYNAMIC
:
6258 const char *base_name
;
6260 decl
= SYMBOL_REF_DECL (addr
);
6261 base_name
= DTPOFF_ZERO_SYM
;
6262 if (decl
&& bss_initializer_p (decl
))
6263 base_name
= ".tbss";
6265 base
= gen_rtx_SYMBOL_REF (Pmode
, base_name
);
6266 tmp
= gen_reg_rtx (Pmode
);
6267 emit_move_insn (tmp
, arc_unspec_offset (base
, UNSPEC_TLS_GD
));
6268 base
= arc_call_tls_get_addr (tmp
);
6269 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, base
),
6270 arc_unspec_offset (addr
, UNSPEC_TLS_OFF
));
6272 case TLS_MODEL_INITIAL_EXEC
:
6273 addr
= arc_unspec_offset (addr
, UNSPEC_TLS_IE
);
6274 addr
= copy_to_mode_reg (Pmode
, gen_const_mem (Pmode
, addr
));
6275 return gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, arc_tp_regno
), addr
);
6277 case TLS_MODEL_LOCAL_EXEC
:
6278 addr
= arc_unspec_offset (addr
, UNSPEC_TLS_OFF
);
6279 return gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, arc_tp_regno
), addr
);
6286 /* Return true if SYMBOL_REF X binds locally. */
6289 arc_symbol_binds_local_p (const_rtx x
)
6291 return (SYMBOL_REF_DECL (x
)
6292 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
6293 : SYMBOL_REF_LOCAL_P (x
));
6296 /* Legitimize a pic address reference in ADDR. The return value is
6297 the legitimated address. */
6300 arc_legitimize_pic_address (rtx addr
)
6305 switch (GET_CODE (addr
))
6308 /* Can be one or our GOT or GOTOFFPC unspecs. This situation
6309 happens when an address is not a legitimate constant and we
6310 need the resolve it via force_reg in
6311 prepare_move_operands. */
6312 switch (XINT (addr
, 1))
6314 case ARC_UNSPEC_GOT
:
6315 case ARC_UNSPEC_GOTOFFPC
:
6316 /* Recover the symbol ref. */
6317 addr
= XVECEXP (addr
, 0, 0);
6324 /* TLS symbols are handled in different place. */
6325 if (SYMBOL_REF_TLS_MODEL (addr
))
6328 /* This symbol must be referenced via a load from the Global
6329 Offset Table (@GOTPC). */
6330 if (!arc_symbol_binds_local_p (addr
))
6331 return gen_const_mem (Pmode
, arc_unspec_offset (addr
, ARC_UNSPEC_GOT
));
6333 /* Local symb: use @pcl to access it. */
6336 return arc_unspec_offset (addr
, ARC_UNSPEC_GOTOFFPC
);
6345 /* Output address constant X to FILE, taking PIC into account. */
6348 arc_output_pic_addr_const (FILE * file
, rtx x
, int code
)
6353 switch (GET_CODE (x
))
6363 output_addr_const (file
, x
);
6365 /* Local functions do not get references through the PLT. */
6366 if (code
== 'P' && ! SYMBOL_REF_LOCAL_P (x
))
6367 fputs ("@plt", file
);
6371 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
6372 assemble_name (file
, buf
);
6376 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
6377 assemble_name (file
, buf
);
6381 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
6385 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
6389 if (GET_MODE (x
) == VOIDmode
)
6391 /* We can use %d if the number is one word and positive. */
6392 if (CONST_DOUBLE_HIGH (x
))
6393 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
6394 CONST_DOUBLE_HIGH (x
), CONST_DOUBLE_LOW (x
));
6395 else if (CONST_DOUBLE_LOW (x
) < 0)
6396 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
6398 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
6401 /* We can't handle floating point constants;
6402 PRINT_OPERAND must handle them. */
6403 output_operand_lossage ("floating constant misused");
6407 /* FIXME: Not needed here. */
6408 /* Some assemblers need integer constants to appear last (eg masm). */
6409 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
6411 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
6412 fprintf (file
, "+");
6413 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
6415 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6417 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
6418 if (INTVAL (XEXP (x
, 1)) >= 0)
6419 fprintf (file
, "+");
6420 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
6427 /* Avoid outputting things like x-x or x+5-x,
6428 since some assemblers can't handle that. */
6429 x
= simplify_subtraction (x
);
6430 if (GET_CODE (x
) != MINUS
)
6433 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
6434 fprintf (file
, "-");
6435 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6436 && INTVAL (XEXP (x
, 1)) < 0)
6438 fprintf (file
, "(");
6439 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
6440 fprintf (file
, ")");
6443 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
6448 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
6454 bool pcrel
; pcrel
= false;
6455 rtx base
; base
= NULL
;
6456 gcc_assert (XVECLEN (x
, 0) >= 1);
6457 switch (XINT (x
, 1))
6459 case ARC_UNSPEC_GOT
:
6460 suffix
= "@gotpc", pcrel
= true;
6462 case ARC_UNSPEC_GOTOFF
:
6465 case ARC_UNSPEC_GOTOFFPC
:
6466 suffix
= "@pcl", pcrel
= true;
6468 case ARC_UNSPEC_PLT
:
6472 suffix
= "@tlsgd", pcrel
= true;
6475 suffix
= "@tlsie", pcrel
= true;
6477 case UNSPEC_TLS_OFF
:
6478 if (XVECLEN (x
, 0) == 2)
6479 base
= XVECEXP (x
, 0, 1);
6480 if (SYMBOL_REF_TLS_MODEL (XVECEXP (x
, 0, 0)) == TLS_MODEL_LOCAL_EXEC
6481 || (!flag_pic
&& !base
))
6487 suffix
= "@invalid";
6488 output_operand_lossage ("invalid UNSPEC as operand: %d", XINT (x
,1));
6492 fputs ("pcl,", file
);
6493 arc_output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
6494 fputs (suffix
, file
);
6496 arc_output_pic_addr_const (file
, base
, code
);
6500 output_operand_lossage ("invalid expression as operand");
6504 /* The function returning the number of words, at the beginning of an
6505 argument, must be put in registers. The returned value must be
6506 zero for arguments that are passed entirely in registers or that
6507 are entirely pushed on the stack.
6509 On some machines, certain arguments must be passed partially in
6510 registers and partially in memory. On these machines, typically
6511 the first N words of arguments are passed in registers, and the
6512 rest on the stack. If a multi-word argument (a `double' or a
6513 structure) crosses that boundary, its first few words must be
6514 passed in registers and the rest must be pushed. This function
6515 tells the compiler when this occurs, and how many of the words
6516 should go in registers.
6518 `FUNCTION_ARG' for these arguments should return the first register
6519 to be used by the caller for this argument; likewise
6520 `FUNCTION_INCOMING_ARG', for the called function.
6522 The function is used to implement macro FUNCTION_ARG_PARTIAL_NREGS. */
6524 /* If REGNO is the least arg reg available then what is the total number of arg
6526 #define GPR_REST_ARG_REGS(REGNO) \
6527 ((REGNO) <= MAX_ARC_PARM_REGS ? MAX_ARC_PARM_REGS - (REGNO) : 0 )
6529 /* Since arc parm regs are contiguous. */
6530 #define ARC_NEXT_ARG_REG(REGNO) ( (REGNO) + 1 )
6532 /* Implement TARGET_ARG_PARTIAL_BYTES. */
6535 arc_arg_partial_bytes (cumulative_args_t cum_v
, const function_arg_info
&arg
)
6537 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6538 int bytes
= arg
.promoted_size_in_bytes ();
6539 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6543 arg_num
= ROUND_ADVANCE_CUM (arg_num
, arg
.mode
, arg
.type
);
6544 ret
= GPR_REST_ARG_REGS (arg_num
);
6546 /* ICEd at function.c:2361, and ret is copied to data->partial */
6547 ret
= (ret
>= words
? 0 : ret
* UNITS_PER_WORD
);
6552 /* Implement TARGET_FUNCTION_ARG. On the ARC the first MAX_ARC_PARM_REGS
6553 args are normally in registers and the rest are pushed. */
6556 arc_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
6558 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6561 const char *debstr ATTRIBUTE_UNUSED
;
6563 arg_num
= ROUND_ADVANCE_CUM (arg_num
, arg
.mode
, arg
.type
);
6564 /* Return a marker for use in the call instruction. */
6565 if (arg
.end_marker_p ())
6570 else if (GPR_REST_ARG_REGS (arg_num
) > 0)
6572 ret
= gen_rtx_REG (arg
.mode
, arg_num
);
6573 debstr
= reg_names
[arg_num
];
6583 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
6584 /* For the ARC: the cum set here is passed on to function_arg where we
6585 look at its value and say which reg to use. Strategy: advance the
6586 regnumber here till we run out of arg regs, then set *cum to last
6587 reg. In function_arg, since *cum > last arg reg we would return 0
6588 and thus the arg will end up on the stack. For straddling args of
6589 course function_arg_partial_nregs will come into play. */
6592 arc_function_arg_advance (cumulative_args_t cum_v
,
6593 const function_arg_info
&arg
)
6595 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6596 int bytes
= arg
.promoted_size_in_bytes ();
6597 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6601 *cum
= ROUND_ADVANCE_CUM (*cum
, arg
.mode
, arg
.type
);
6602 for (i
= 0; i
< words
; i
++)
6603 *cum
= ARC_NEXT_ARG_REG (*cum
);
6607 /* Define how to find the value returned by a function.
6608 VALTYPE is the data type of the value (as a tree).
6609 If the precise function being called is known, FN_DECL_OR_TYPE is its
6610 FUNCTION_DECL; otherwise, FN_DECL_OR_TYPE is its type. */
6613 arc_function_value (const_tree valtype
,
6614 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6615 bool outgoing ATTRIBUTE_UNUSED
)
6617 machine_mode mode
= TYPE_MODE (valtype
);
6618 int unsignedp ATTRIBUTE_UNUSED
;
6620 unsignedp
= TYPE_UNSIGNED (valtype
);
6621 if (INTEGRAL_TYPE_P (valtype
) || TREE_CODE (valtype
) == OFFSET_TYPE
)
6622 PROMOTE_MODE (mode
, unsignedp
, valtype
);
6623 return gen_rtx_REG (mode
, 0);
6626 /* Returns the return address that is used by builtin_return_address. */
6629 arc_return_addr_rtx (int count
, ATTRIBUTE_UNUSED rtx frame
)
6634 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
6637 /* Determine if a given RTX is a valid constant. We already know this
6638 satisfies CONSTANT_P. */
6641 arc_legitimate_constant_p (machine_mode mode
, rtx x
)
6643 switch (GET_CODE (x
))
6648 if (arc_legitimate_pic_addr_p (x
))
6651 return arc_legitimate_constant_p (mode
, XEXP (x
, 0));
6654 if (SYMBOL_REF_TLS_MODEL (x
))
6666 return arc_legitimate_constant_p (mode
, XEXP (x
, 0));
6671 bool t1
= arc_legitimate_constant_p (mode
, XEXP (x
, 0));
6672 bool t2
= arc_legitimate_constant_p (mode
, XEXP (x
, 1));
6681 return TARGET_PLUS_DMPY
;
6684 return TARGET_PLUS_QMACW
;
6690 switch (XINT (x
, 1))
6693 case UNSPEC_TLS_OFF
:
6697 /* Any other unspec ending here are pic related, hence the above
6698 constant pic address checking returned false. */
6704 fatal_insn ("unrecognized supposed constant", x
);
6711 arc_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
6713 if (RTX_OK_FOR_BASE_P (x
, strict
))
6715 if (legitimate_offset_address_p (mode
, x
, TARGET_INDEXED_LOADS
, strict
))
6717 if (legitimate_scaled_address_p (mode
, x
, strict
))
6719 if (legitimate_small_data_address_p (x
, mode
))
6721 if (GET_CODE (x
) == CONST_INT
&& LARGE_INT (INTVAL (x
)))
6724 /* When we compile for size avoid const (@sym + offset)
6726 if (!flag_pic
&& optimize_size
&& !reload_completed
6727 && (GET_CODE (x
) == CONST
)
6728 && (GET_CODE (XEXP (x
, 0)) == PLUS
)
6729 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
6730 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) == 0
6731 && !SYMBOL_REF_FUNCTION_P (XEXP (XEXP (x
, 0), 0)))
6733 rtx addend
= XEXP (XEXP (x
, 0), 1);
6734 gcc_assert (CONST_INT_P (addend
));
6735 HOST_WIDE_INT offset
= INTVAL (addend
);
6737 /* Allow addresses having a large offset to pass. Anyhow they
6738 will end in a limm. */
6739 return !(offset
> -1024 && offset
< 1020);
6742 if ((GET_MODE_SIZE (mode
) != 16) && CONSTANT_P (x
))
6744 return arc_legitimate_constant_p (mode
, x
);
6746 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == PRE_INC
6747 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == POST_INC
)
6748 && RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6750 /* We're restricted here by the `st' insn. */
6751 if ((GET_CODE (x
) == PRE_MODIFY
|| GET_CODE (x
) == POST_MODIFY
)
6752 && GET_CODE (XEXP ((x
), 1)) == PLUS
6753 && rtx_equal_p (XEXP ((x
), 0), XEXP (XEXP (x
, 1), 0))
6754 && legitimate_offset_address_p (QImode
, XEXP (x
, 1),
6755 TARGET_AUTO_MODIFY_REG
, strict
))
6760 /* Return true iff ADDR (a legitimate address expression)
6761 has an effect that depends on the machine mode it is used for. */
6764 arc_mode_dependent_address_p (const_rtx addr
, addr_space_t
)
6766 /* SYMBOL_REF is not mode dependent: it is either a small data reference,
6767 which is valid for loads and stores, or a limm offset, which is valid for
6768 loads. Scaled indices are scaled by the access mode. */
6769 if (GET_CODE (addr
) == PLUS
6770 && GET_CODE (XEXP ((addr
), 0)) == MULT
)
6775 /* Determine if it's legal to put X into the constant pool. */
6778 arc_cannot_force_const_mem (machine_mode mode
, rtx x
)
6780 return !arc_legitimate_constant_p (mode
, x
);
6783 /* IDs for all the ARC builtins. */
6787 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6788 ARC_BUILTIN_ ## NAME,
6789 #include "builtins.def"
6795 struct GTY(()) arc_builtin_description
6797 enum insn_code icode
;
6802 static GTY(()) struct arc_builtin_description
6803 arc_bdesc
[ARC_BUILTIN_COUNT
] =
6805 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6806 { (enum insn_code) CODE_FOR_ ## ICODE, N_ARGS, NULL_TREE },
6807 #include "builtins.def"
6811 /* Transform UP into lowercase and write the result to LO.
6812 You must provide enough space for LO. Return LO. */
6815 arc_tolower (char *lo
, const char *up
)
6819 for (; *up
; up
++, lo
++)
6820 *lo
= TOLOWER (*up
);
6827 /* Implement `TARGET_BUILTIN_DECL'. */
6830 arc_builtin_decl (unsigned id
, bool initialize_p ATTRIBUTE_UNUSED
)
6832 if (id
< ARC_BUILTIN_COUNT
)
6833 return arc_bdesc
[id
].fndecl
;
6835 return error_mark_node
;
6839 arc_init_builtins (void)
6841 tree V4HI_type_node
;
6842 tree V2SI_type_node
;
6843 tree V2HI_type_node
;
6845 /* Vector types based on HS SIMD elements. */
6846 V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
6847 V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
6848 V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
6850 tree pcvoid_type_node
6851 = build_pointer_type (build_qualified_type (void_type_node
,
6853 tree V8HI_type_node
= build_vector_type_for_mode (intHI_type_node
,
6856 tree void_ftype_void
6857 = build_function_type_list (void_type_node
, NULL_TREE
);
6859 = build_function_type_list (integer_type_node
, integer_type_node
,
6861 tree int_ftype_pcvoid_int
6862 = build_function_type_list (integer_type_node
, pcvoid_type_node
,
6863 integer_type_node
, NULL_TREE
);
6864 tree void_ftype_usint_usint
6865 = build_function_type_list (void_type_node
, long_unsigned_type_node
,
6866 long_unsigned_type_node
, NULL_TREE
);
6867 tree int_ftype_int_int
6868 = build_function_type_list (integer_type_node
, integer_type_node
,
6869 integer_type_node
, NULL_TREE
);
6870 tree usint_ftype_usint
6871 = build_function_type_list (long_unsigned_type_node
,
6872 long_unsigned_type_node
, NULL_TREE
);
6873 tree void_ftype_usint
6874 = build_function_type_list (void_type_node
, long_unsigned_type_node
,
6877 = build_function_type_list (integer_type_node
, void_type_node
,
6880 = build_function_type_list (void_type_node
, integer_type_node
,
6882 tree int_ftype_short
6883 = build_function_type_list (integer_type_node
, short_integer_type_node
,
6886 /* Old ARC SIMD types. */
6887 tree v8hi_ftype_v8hi_v8hi
6888 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6889 V8HI_type_node
, NULL_TREE
);
6890 tree v8hi_ftype_v8hi_int
6891 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6892 integer_type_node
, NULL_TREE
);
6893 tree v8hi_ftype_v8hi_int_int
6894 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6895 integer_type_node
, integer_type_node
,
6897 tree void_ftype_v8hi_int_int
6898 = build_function_type_list (void_type_node
, V8HI_type_node
,
6899 integer_type_node
, integer_type_node
,
6901 tree void_ftype_v8hi_int_int_int
6902 = build_function_type_list (void_type_node
, V8HI_type_node
,
6903 integer_type_node
, integer_type_node
,
6904 integer_type_node
, NULL_TREE
);
6905 tree v8hi_ftype_int_int
6906 = build_function_type_list (V8HI_type_node
, integer_type_node
,
6907 integer_type_node
, NULL_TREE
);
6908 tree void_ftype_int_int
6909 = build_function_type_list (void_type_node
, integer_type_node
,
6910 integer_type_node
, NULL_TREE
);
6911 tree v8hi_ftype_v8hi
6912 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6914 /* ARCv2 SIMD types. */
6915 tree long_ftype_v4hi_v4hi
6916 = build_function_type_list (long_long_integer_type_node
,
6917 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
6918 tree int_ftype_v2hi_v2hi
6919 = build_function_type_list (integer_type_node
,
6920 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6921 tree v2si_ftype_v2hi_v2hi
6922 = build_function_type_list (V2SI_type_node
,
6923 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6924 tree v2hi_ftype_v2hi_v2hi
6925 = build_function_type_list (V2HI_type_node
,
6926 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6927 tree v2si_ftype_v2si_v2si
6928 = build_function_type_list (V2SI_type_node
,
6929 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
6930 tree v4hi_ftype_v4hi_v4hi
6931 = build_function_type_list (V4HI_type_node
,
6932 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
6933 tree long_ftype_v2si_v2hi
6934 = build_function_type_list (long_long_integer_type_node
,
6935 V2SI_type_node
, V2HI_type_node
, NULL_TREE
);
6937 /* Add the builtins. */
6938 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6940 int id = ARC_BUILTIN_ ## NAME; \
6941 const char *Name = "__builtin_arc_" #NAME; \
6942 char *name = (char*) alloca (1 + strlen (Name)); \
6944 gcc_assert (id < ARC_BUILTIN_COUNT); \
6946 arc_bdesc[id].fndecl \
6947 = add_builtin_function (arc_tolower(name, Name), TYPE, id, \
6948 BUILT_IN_MD, NULL, NULL_TREE); \
6950 #include "builtins.def"
6954 /* Helper to expand __builtin_arc_aligned (void* val, int
6958 arc_expand_builtin_aligned (tree exp
)
6960 tree arg0
= CALL_EXPR_ARG (exp
, 0);
6961 tree arg1
= CALL_EXPR_ARG (exp
, 1);
6963 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6964 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6966 if (!CONST_INT_P (op1
))
6968 /* If we can't fold the alignment to a constant integer
6969 whilst optimizing, this is probably a user error. */
6971 warning (0, "%<__builtin_arc_aligned%> with non-constant alignment");
6975 HOST_WIDE_INT alignTest
= INTVAL (op1
);
6976 /* Check alignTest is positive, and a power of two. */
6977 if (alignTest
<= 0 || alignTest
!= (alignTest
& -alignTest
))
6979 error ("invalid alignment value for %<__builtin_arc_aligned%>");
6983 if (CONST_INT_P (op0
))
6985 HOST_WIDE_INT pnt
= INTVAL (op0
);
6987 if ((pnt
& (alignTest
- 1)) == 0)
6992 unsigned align
= get_pointer_alignment (arg0
);
6993 unsigned numBits
= alignTest
* BITS_PER_UNIT
;
6995 if (align
&& align
>= numBits
)
6997 /* Another attempt to ascertain alignment. Check the type
6998 we are pointing to. */
6999 if (POINTER_TYPE_P (TREE_TYPE (arg0
))
7000 && TYPE_ALIGN (TREE_TYPE (TREE_TYPE (arg0
))) >= numBits
)
7005 /* Default to false. */
7009 /* Helper arc_expand_builtin, generates a pattern for the given icode
7013 apply_GEN_FCN (enum insn_code icode
, rtx
*arg
)
7015 switch (insn_data
[icode
].n_generator_args
)
7018 return GEN_FCN (icode
) ();
7020 return GEN_FCN (icode
) (arg
[0]);
7022 return GEN_FCN (icode
) (arg
[0], arg
[1]);
7024 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2]);
7026 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2], arg
[3]);
7028 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2], arg
[3], arg
[4]);
7034 /* Expand an expression EXP that calls a built-in function,
7035 with result going to TARGET if that's convenient
7036 (and in mode MODE if that's convenient).
7037 SUBTARGET may be used as the target for computing one of EXP's operands.
7038 IGNORE is nonzero if the value is to be ignored. */
7041 arc_expand_builtin (tree exp
,
7043 rtx subtarget ATTRIBUTE_UNUSED
,
7044 machine_mode mode ATTRIBUTE_UNUSED
,
7045 int ignore ATTRIBUTE_UNUSED
)
7047 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
7048 unsigned int id
= DECL_MD_FUNCTION_CODE (fndecl
);
7049 const struct arc_builtin_description
*d
= &arc_bdesc
[id
];
7050 int i
, j
, n_args
= call_expr_nargs (exp
);
7053 enum insn_code icode
= d
->icode
;
7054 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7071 if (id
>= ARC_BUILTIN_COUNT
)
7072 internal_error ("bad builtin fcode");
7074 /* 1st part: Expand special builtins. */
7077 case ARC_BUILTIN_NOP
:
7078 emit_insn (gen_nopv ());
7081 case ARC_BUILTIN_RTIE
:
7082 case ARC_BUILTIN_SYNC
:
7083 case ARC_BUILTIN_BRK
:
7084 case ARC_BUILTIN_SWI
:
7085 case ARC_BUILTIN_UNIMP_S
:
7086 gcc_assert (icode
!= 0);
7087 emit_insn (GEN_FCN (icode
) (const1_rtx
));
7090 case ARC_BUILTIN_ALIGNED
:
7091 return arc_expand_builtin_aligned (exp
);
7093 case ARC_BUILTIN_CLRI
:
7094 target
= gen_reg_rtx (SImode
);
7095 emit_insn (gen_clri (target
, const1_rtx
));
7098 case ARC_BUILTIN_TRAP_S
:
7099 case ARC_BUILTIN_SLEEP
:
7100 arg0
= CALL_EXPR_ARG (exp
, 0);
7102 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
7104 gcc_assert (icode
!= 0);
7105 emit_insn (GEN_FCN (icode
) (op0
));
7108 case ARC_BUILTIN_VDORUN
:
7109 case ARC_BUILTIN_VDIRUN
:
7110 arg0
= CALL_EXPR_ARG (exp
, 0);
7111 arg1
= CALL_EXPR_ARG (exp
, 1);
7112 op0
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7113 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7115 target
= gen_rtx_REG (SImode
, (id
== ARC_BUILTIN_VDIRUN
) ? 131 : 139);
7117 mode0
= insn_data
[icode
].operand
[1].mode
;
7118 mode1
= insn_data
[icode
].operand
[2].mode
;
7120 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
7121 op0
= copy_to_mode_reg (mode0
, op0
);
7123 if (!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
7124 op1
= copy_to_mode_reg (mode1
, op1
);
7126 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
7133 case ARC_BUILTIN_VDIWR
:
7134 case ARC_BUILTIN_VDOWR
:
7135 arg0
= CALL_EXPR_ARG (exp
, 0);
7136 arg1
= CALL_EXPR_ARG (exp
, 1);
7137 op0
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7138 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7140 if (!CONST_INT_P (op0
)
7141 || !(UNSIGNED_INT3 (INTVAL (op0
))))
7142 error ("operand 1 should be an unsigned 3-bit immediate");
7144 mode1
= insn_data
[icode
].operand
[1].mode
;
7146 if (icode
== CODE_FOR_vdiwr_insn
)
7147 target
= gen_rtx_REG (SImode
,
7148 ARC_FIRST_SIMD_DMA_CONFIG_IN_REG
+ INTVAL (op0
));
7149 else if (icode
== CODE_FOR_vdowr_insn
)
7150 target
= gen_rtx_REG (SImode
,
7151 ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG
+ INTVAL (op0
));
7155 if (!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
7156 op1
= copy_to_mode_reg (mode1
, op1
);
7158 pat
= GEN_FCN (icode
) (target
, op1
);
7165 case ARC_BUILTIN_VASRW
:
7166 case ARC_BUILTIN_VSR8
:
7167 case ARC_BUILTIN_VSR8AW
:
7168 arg0
= CALL_EXPR_ARG (exp
, 0);
7169 arg1
= CALL_EXPR_ARG (exp
, 1);
7170 op0
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
7171 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7172 op2
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
7174 target
= gen_reg_rtx (V8HImode
);
7175 mode0
= insn_data
[icode
].operand
[1].mode
;
7176 mode1
= insn_data
[icode
].operand
[2].mode
;
7178 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
7179 op0
= copy_to_mode_reg (mode0
, op0
);
7181 if ((!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
7182 || !(UNSIGNED_INT3 (INTVAL (op1
))))
7183 error ("operand 2 should be an unsigned 3-bit value (I0-I7)");
7185 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
7192 case ARC_BUILTIN_VLD32WH
:
7193 case ARC_BUILTIN_VLD32WL
:
7194 case ARC_BUILTIN_VLD64
:
7195 case ARC_BUILTIN_VLD32
:
7198 arg0
= CALL_EXPR_ARG (exp
, 0); /* source vreg. */
7199 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
7200 arg2
= CALL_EXPR_ARG (exp
, 2); /* u8. */
7202 src_vreg
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
7203 op0
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7204 op1
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7205 op2
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
7207 /* target <- src vreg. */
7208 emit_insn (gen_move_insn (target
, src_vreg
));
7210 /* target <- vec_concat: target, mem (Ib, u8). */
7211 mode0
= insn_data
[icode
].operand
[3].mode
;
7212 mode1
= insn_data
[icode
].operand
[1].mode
;
7214 if ((!insn_data
[icode
].operand
[3].predicate (op0
, mode0
))
7215 || !(UNSIGNED_INT3 (INTVAL (op0
))))
7216 error ("operand 1 should be an unsigned 3-bit value (I0-I7)");
7218 if ((!insn_data
[icode
].operand
[1].predicate (op1
, mode1
))
7219 || !(UNSIGNED_INT8 (INTVAL (op1
))))
7220 error ("operand 2 should be an unsigned 8-bit value");
7222 pat
= GEN_FCN (icode
) (target
, op1
, op2
, op0
);
7229 case ARC_BUILTIN_VLD64W
:
7230 case ARC_BUILTIN_VLD128
:
7231 arg0
= CALL_EXPR_ARG (exp
, 0); /* dest vreg. */
7232 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
7234 op0
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
7235 op1
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7236 op2
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7238 /* target <- src vreg. */
7239 target
= gen_reg_rtx (V8HImode
);
7241 /* target <- vec_concat: target, mem (Ib, u8). */
7242 mode0
= insn_data
[icode
].operand
[1].mode
;
7243 mode1
= insn_data
[icode
].operand
[2].mode
;
7244 mode2
= insn_data
[icode
].operand
[3].mode
;
7246 if ((!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
7247 || !(UNSIGNED_INT3 (INTVAL (op1
))))
7248 error ("operand 1 should be an unsigned 3-bit value (I0-I7)");
7250 if ((!insn_data
[icode
].operand
[3].predicate (op2
, mode2
))
7251 || !(UNSIGNED_INT8 (INTVAL (op2
))))
7252 error ("operand 2 should be an unsigned 8-bit value");
7254 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
7262 case ARC_BUILTIN_VST128
:
7263 case ARC_BUILTIN_VST64
:
7264 arg0
= CALL_EXPR_ARG (exp
, 0); /* src vreg. */
7265 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
7266 arg2
= CALL_EXPR_ARG (exp
, 2); /* u8. */
7268 op0
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
7269 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7270 op2
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7271 op3
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
7273 mode0
= insn_data
[icode
].operand
[0].mode
;
7274 mode1
= insn_data
[icode
].operand
[1].mode
;
7275 mode2
= insn_data
[icode
].operand
[2].mode
;
7276 mode3
= insn_data
[icode
].operand
[3].mode
;
7278 if ((!insn_data
[icode
].operand
[1].predicate (op1
, mode1
))
7279 || !(UNSIGNED_INT3 (INTVAL (op1
))))
7280 error ("operand 2 should be an unsigned 3-bit value (I0-I7)");
7282 if ((!insn_data
[icode
].operand
[2].predicate (op2
, mode2
))
7283 || !(UNSIGNED_INT8 (INTVAL (op2
))))
7284 error ("operand 3 should be an unsigned 8-bit value");
7286 if (!insn_data
[icode
].operand
[3].predicate (op3
, mode3
))
7287 op3
= copy_to_mode_reg (mode3
, op3
);
7289 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
7296 case ARC_BUILTIN_VST16_N
:
7297 case ARC_BUILTIN_VST32_N
:
7298 arg0
= CALL_EXPR_ARG (exp
, 0); /* source vreg. */
7299 arg1
= CALL_EXPR_ARG (exp
, 1); /* u3. */
7300 arg2
= CALL_EXPR_ARG (exp
, 2); /* [I]0-7. */
7301 arg3
= CALL_EXPR_ARG (exp
, 3); /* u8. */
7303 op0
= expand_expr (arg3
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7304 op1
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
7305 op2
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7306 op3
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
7307 op4
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
7309 mode0
= insn_data
[icode
].operand
[0].mode
;
7310 mode2
= insn_data
[icode
].operand
[2].mode
;
7311 mode3
= insn_data
[icode
].operand
[3].mode
;
7312 mode4
= insn_data
[icode
].operand
[4].mode
;
7314 /* Do some correctness checks for the operands. */
7315 if ((!insn_data
[icode
].operand
[0].predicate (op0
, mode0
))
7316 || !(UNSIGNED_INT8 (INTVAL (op0
))))
7317 error ("operand 4 should be an unsigned 8-bit value (0-255)");
7319 if ((!insn_data
[icode
].operand
[2].predicate (op2
, mode2
))
7320 || !(UNSIGNED_INT3 (INTVAL (op2
))))
7321 error ("operand 3 should be an unsigned 3-bit value (I0-I7)");
7323 if (!insn_data
[icode
].operand
[3].predicate (op3
, mode3
))
7324 op3
= copy_to_mode_reg (mode3
, op3
);
7326 if ((!insn_data
[icode
].operand
[4].predicate (op4
, mode4
))
7327 || !(UNSIGNED_INT3 (INTVAL (op4
))))
7328 error ("operand 2 should be an unsigned 3-bit value (subreg 0-7)");
7329 else if (icode
== CODE_FOR_vst32_n_insn
7330 && ((INTVAL (op4
) % 2) != 0))
7331 error ("operand 2 should be an even 3-bit value (subreg 0,2,4,6)");
7333 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
, op4
);
7344 /* 2nd part: Expand regular builtins. */
7346 internal_error ("bad builtin fcode");
7348 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
7353 if (target
== NULL_RTX
7354 || GET_MODE (target
) != tmode
7355 || !insn_data
[icode
].operand
[0].predicate (target
, tmode
))
7357 target
= gen_reg_rtx (tmode
);
7362 gcc_assert (n_args
<= 4);
7363 for (i
= 0; i
< n_args
; i
++, j
++)
7365 tree arg
= CALL_EXPR_ARG (exp
, i
);
7366 machine_mode mode
= insn_data
[icode
].operand
[j
].mode
;
7367 rtx op
= expand_expr (arg
, NULL_RTX
, mode
, EXPAND_NORMAL
);
7368 machine_mode opmode
= GET_MODE (op
);
7369 char c
= insn_data
[icode
].operand
[j
].constraint
[0];
7371 /* SIMD extension requires exact immediate operand match. */
7372 if ((id
> ARC_BUILTIN_SIMD_BEGIN
)
7373 && (id
< ARC_BUILTIN_SIMD_END
)
7377 if (!CONST_INT_P (op
))
7378 error ("builtin requires an immediate for operand %d", j
);
7382 if (!satisfies_constraint_L (op
))
7383 error ("operand %d should be a 6 bit unsigned immediate", j
);
7386 if (!satisfies_constraint_P (op
))
7387 error ("operand %d should be a 8 bit unsigned immediate", j
);
7390 if (!satisfies_constraint_K (op
))
7391 error ("operand %d should be a 3 bit unsigned immediate", j
);
7394 error ("unknown builtin immediate operand type for operand %d",
7399 if (CONST_INT_P (op
))
7402 if ((opmode
== SImode
) && (mode
== HImode
))
7405 op
= gen_lowpart (HImode
, op
);
7408 /* In case the insn wants input operands in modes different from
7409 the result, abort. */
7410 gcc_assert (opmode
== mode
|| opmode
== VOIDmode
);
7412 if (!insn_data
[icode
].operand
[i
+ nonvoid
].predicate (op
, mode
))
7413 op
= copy_to_mode_reg (mode
, op
);
7418 pat
= apply_GEN_FCN (icode
, xop
);
7419 if (pat
== NULL_RTX
)
7430 /* Returns true if the operands[opno] is a valid compile-time constant to be
7431 used as register number in the code for builtins. Else it flags an error
7432 and returns false. */
7435 check_if_valid_regno_const (rtx
*operands
, int opno
)
7438 switch (GET_CODE (operands
[opno
]))
7445 error ("register number must be a compile-time constant. "
7446 "Try giving higher optimization levels");
7452 /* Return true if it is ok to make a tail-call to DECL. */
7455 arc_function_ok_for_sibcall (tree decl
,
7456 tree exp ATTRIBUTE_UNUSED
)
7458 tree attrs
= NULL_TREE
;
7460 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
7461 if (ARC_INTERRUPT_P (arc_compute_function_type (cfun
)))
7466 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
7468 if (lookup_attribute ("jli_always", attrs
))
7470 if (lookup_attribute ("jli_fixed", attrs
))
7472 if (lookup_attribute ("secure_call", attrs
))
7476 /* Everything else is ok. */
7480 /* Output code to add DELTA to the first argument, and then jump
7481 to FUNCTION. Used for C++ multiple inheritance. */
7484 arc_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
7485 HOST_WIDE_INT delta
,
7486 HOST_WIDE_INT vcall_offset
,
7489 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk
));
7490 int mi_delta
= delta
;
7491 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
7494 = aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
) ? 1 : 0;
7497 assemble_start_function (thunk
, fnname
);
7500 mi_delta
= - mi_delta
;
7502 /* Add DELTA. When possible use a plain add, otherwise load it into
7503 a register first. */
7505 while (mi_delta
!= 0)
7507 if ((mi_delta
& (3 << shift
)) == 0)
7511 asm_fprintf (file
, "\t%s\t%s, %s, %d\n",
7512 mi_op
, reg_names
[this_regno
], reg_names
[this_regno
],
7513 mi_delta
& (0xff << shift
));
7514 mi_delta
&= ~(0xff << shift
);
7519 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7520 if (vcall_offset
!= 0)
7522 /* ld r12,[this] --> temp = *this
7523 add r12,r12,vcall_offset --> temp = *(*this + vcall_offset)
7525 add this,this,r12 --> this+ = *(*this + vcall_offset) */
7526 asm_fprintf (file
, "\tld\t%s, [%s]\n",
7527 ARC_TEMP_SCRATCH_REG
, reg_names
[this_regno
]);
7528 asm_fprintf (file
, "\tadd\t%s, %s, " HOST_WIDE_INT_PRINT_DEC
"\n",
7529 ARC_TEMP_SCRATCH_REG
, ARC_TEMP_SCRATCH_REG
, vcall_offset
);
7530 asm_fprintf (file
, "\tld\t%s, [%s]\n",
7531 ARC_TEMP_SCRATCH_REG
, ARC_TEMP_SCRATCH_REG
);
7532 asm_fprintf (file
, "\tadd\t%s, %s, %s\n", reg_names
[this_regno
],
7533 reg_names
[this_regno
], ARC_TEMP_SCRATCH_REG
);
7536 fnaddr
= XEXP (DECL_RTL (function
), 0);
7538 if (arc_is_longcall_p (fnaddr
))
7542 asm_fprintf (file
, "\tld\t%s, [pcl, @",
7543 ARC_TEMP_SCRATCH_REG
);
7544 assemble_name (file
, XSTR (fnaddr
, 0));
7545 fputs ("@gotpc]\n", file
);
7546 asm_fprintf (file
, "\tj\t[%s]", ARC_TEMP_SCRATCH_REG
);
7550 fputs ("\tj\t@", file
);
7551 assemble_name (file
, XSTR (fnaddr
, 0));
7556 fputs ("\tb\t@", file
);
7557 assemble_name (file
, XSTR (fnaddr
, 0));
7559 fputs ("@plt\n", file
);
7562 assemble_end_function (thunk
, fnname
);
7565 /* Return true if a 32 bit "long_call" should be generated for
7566 this calling SYM_REF. We generate a long_call if the function:
7568 a. has an __attribute__((long call))
7569 or b. the -mlong-calls command line switch has been specified
7571 However we do not generate a long call if the function has an
7572 __attribute__ ((short_call)) or __attribute__ ((medium_call))
7574 This function will be called by C fragments contained in the machine
7575 description file. */
7578 arc_is_longcall_p (rtx sym_ref
)
7580 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
7583 return (SYMBOL_REF_LONG_CALL_P (sym_ref
)
7584 || (TARGET_LONG_CALLS_SET
7585 && !SYMBOL_REF_SHORT_CALL_P (sym_ref
)
7586 && !SYMBOL_REF_MEDIUM_CALL_P (sym_ref
)));
7590 /* Likewise for short calls. */
7593 arc_is_shortcall_p (rtx sym_ref
)
7595 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
7598 return (SYMBOL_REF_SHORT_CALL_P (sym_ref
)
7599 || (!TARGET_LONG_CALLS_SET
&& !TARGET_MEDIUM_CALLS
7600 && !SYMBOL_REF_LONG_CALL_P (sym_ref
)
7601 && !SYMBOL_REF_MEDIUM_CALL_P (sym_ref
)));
7605 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7608 arc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7610 if (AGGREGATE_TYPE_P (type
) || TREE_ADDRESSABLE (type
))
7614 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7615 return (size
== -1 || size
> (TARGET_V2
? 16 : 8));
7620 arc_pass_by_reference (cumulative_args_t
, const function_arg_info
&arg
)
7622 return (arg
.type
!= 0
7623 && (TREE_CODE (TYPE_SIZE (arg
.type
)) != INTEGER_CST
7624 || TREE_ADDRESSABLE (arg
.type
)));
7627 /* Implement TARGET_CAN_USE_DOLOOP_P. */
7630 arc_can_use_doloop_p (const widest_int
&,
7631 const widest_int
&iterations_max
,
7632 unsigned int loop_depth
, bool entered_at_top
)
7634 /* Considering limitations in the hardware, only use doloop
7635 for innermost loops which must be entered from the top. */
7636 if (loop_depth
> 1 || !entered_at_top
)
7639 /* Check for lp_count width boundary. */
7640 if (arc_lpcwidth
!= 32
7641 && (wi::gtu_p (iterations_max
, ((1 << arc_lpcwidth
) - 1))
7642 || wi::eq_p (iterations_max
, 0)))
7647 /* NULL if INSN insn is valid within a low-overhead loop. Otherwise
7648 return why doloop cannot be applied. */
7651 arc_invalid_within_doloop (const rtx_insn
*insn
)
7654 return "Function call in the loop.";
7656 /* FIXME! add here all the ZOL exceptions. */
7660 /* Return the next active insn, skiping the inline assembly code. */
7663 arc_active_insn (rtx_insn
*insn
)
7667 insn
= NEXT_INSN (insn
);
7669 || (active_insn_p (insn
)
7670 && NONDEBUG_INSN_P (insn
)
7672 && GET_CODE (PATTERN (insn
)) != UNSPEC_VOLATILE
7673 && GET_CODE (PATTERN (insn
)) != PARALLEL
))
7679 /* Search for a sequence made out of two stores and a given number of
7680 loads, insert a nop if required. */
7683 check_store_cacheline_hazard (void)
7685 rtx_insn
*insn
, *succ0
, *insn1
;
7688 for (insn
= get_insns (); insn
; insn
= arc_active_insn (insn
))
7690 succ0
= arc_active_insn (insn
);
7695 if (!single_set (insn
))
7698 if ((get_attr_type (insn
) != TYPE_STORE
))
7701 /* Found at least two consecutive stores. Goto the end of the
7703 for (insn1
= succ0
; insn1
; insn1
= arc_active_insn (insn1
))
7704 if (!single_set (insn1
) || get_attr_type (insn1
) != TYPE_STORE
)
7707 /* Save were we are. */
7710 /* Now, check the next two instructions for the following cases:
7711 1. next instruction is a LD => insert 2 nops between store
7713 2. next-next instruction is a LD => inset 1 nop after the store
7715 if (insn1
&& single_set (insn1
)
7716 && (get_attr_type (insn1
) == TYPE_LOAD
))
7719 emit_insn_before (gen_nopv (), insn1
);
7720 emit_insn_before (gen_nopv (), insn1
);
7724 if (insn1
&& (get_attr_type (insn1
) == TYPE_COMPARE
))
7726 /* REG_SAVE_NOTE is used by Haifa scheduler, we are in
7727 reorg, so it is safe to reuse it for avoiding the
7728 current compare insn to be part of a BRcc
7730 add_reg_note (insn1
, REG_SAVE_NOTE
, GEN_INT (3));
7732 insn1
= arc_active_insn (insn1
);
7733 if (insn1
&& single_set (insn1
)
7734 && (get_attr_type (insn1
) == TYPE_LOAD
))
7737 emit_insn_before (gen_nopv (), insn1
);
7751 /* Return true if a load instruction (CONSUMER) uses the same address as a
7752 store instruction (PRODUCER). This function is used to avoid st/ld
7753 address hazard in ARC700 cores. */
7756 arc_store_addr_hazard_internal_p (rtx_insn
* producer
, rtx_insn
* consumer
)
7758 rtx in_set
, out_set
;
7759 rtx out_addr
, in_addr
;
7767 /* Peel the producer and the consumer for the address. */
7768 out_set
= single_set (producer
);
7771 out_addr
= SET_DEST (out_set
);
7774 if (GET_CODE (out_addr
) == ZERO_EXTEND
7775 || GET_CODE (out_addr
) == SIGN_EXTEND
)
7776 out_addr
= XEXP (out_addr
, 0);
7778 if (!MEM_P (out_addr
))
7781 in_set
= single_set (consumer
);
7784 in_addr
= SET_SRC (in_set
);
7787 if (GET_CODE (in_addr
) == ZERO_EXTEND
7788 || GET_CODE (in_addr
) == SIGN_EXTEND
)
7789 in_addr
= XEXP (in_addr
, 0);
7791 if (!MEM_P (in_addr
))
7793 /* Get rid of the MEM and check if the addresses are
7795 in_addr
= XEXP (in_addr
, 0);
7796 out_addr
= XEXP (out_addr
, 0);
7798 return exp_equiv_p (in_addr
, out_addr
, 0, true);
7804 /* Return TRUE is we have an store address hazard. */
7807 arc_store_addr_hazard_p (rtx_insn
* producer
, rtx_insn
* consumer
)
7809 if (TARGET_ARC700
&& (arc_tune
!= ARC_TUNE_ARC7XX
))
7811 return arc_store_addr_hazard_internal_p (producer
, consumer
);
7814 /* The same functionality as arc_hazard. It is called in machine
7815 reorg before any other optimization. Hence, the NOP size is taken
7816 into account when doing branch shortening. */
7819 workaround_arc_anomaly (void)
7821 rtx_insn
*insn
, *succ0
;
7823 /* For any architecture: call arc_hazard here. */
7824 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7826 succ0
= next_real_insn (insn
);
7827 if (arc_hazard (insn
, succ0
))
7829 emit_insn_before (gen_nopv (), succ0
);
7836 /* Old A7 are suffering of a cache hazard, and we need to insert two
7837 nops between any sequence of stores and a load. */
7838 if (arc_tune
!= ARC_TUNE_ARC7XX
)
7839 check_store_cacheline_hazard ();
7842 /* A callback for the hw-doloop pass. Called when a loop we have discovered
7843 turns out not to be optimizable; we have to split the loop_end pattern into
7844 a subtract and a test. */
7847 hwloop_fail (hwloop_info loop
)
7850 rtx insn
= loop
->loop_end
;
7853 && (loop
->length
&& (loop
->length
<= ARC_MAX_LOOP_LENGTH
))
7854 && REG_P (loop
->iter_reg
))
7856 /* TARGET_V2 core3 has dbnz instructions. */
7857 test
= gen_dbnz (loop
->iter_reg
, loop
->start_label
);
7858 insn
= emit_jump_insn_before (test
, loop
->loop_end
);
7860 else if (REG_P (loop
->iter_reg
) && (REGNO (loop
->iter_reg
) == LP_COUNT
))
7862 /* We have the lp_count as loop iterator, try to use it. */
7863 emit_insn_before (gen_loop_fail (), loop
->loop_end
);
7864 test
= gen_rtx_NE (VOIDmode
, gen_rtx_REG (CC_ZNmode
, CC_REG
),
7866 test
= gen_rtx_IF_THEN_ELSE (VOIDmode
, test
,
7867 gen_rtx_LABEL_REF (Pmode
, loop
->start_label
),
7869 insn
= emit_jump_insn_before (gen_rtx_SET (pc_rtx
, test
),
7874 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
7878 test
= gen_rtx_NE (VOIDmode
, loop
->iter_reg
, const0_rtx
);
7879 insn
= emit_jump_insn_before (gen_cbranchsi4 (test
,
7885 JUMP_LABEL (insn
) = loop
->start_label
;
7886 LABEL_NUSES (loop
->start_label
)++;
7887 delete_insn (loop
->loop_end
);
7890 /* Return the next insn after INSN that is not a NOTE, but stop the
7891 search before we enter another basic block. This routine does not
7892 look inside SEQUENCEs. */
7895 next_nonnote_insn_bb (rtx_insn
*insn
)
7899 insn
= NEXT_INSN (insn
);
7900 if (insn
== 0 || !NOTE_P (insn
))
7902 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
7909 /* Optimize LOOP. */
7912 hwloop_optimize (hwloop_info loop
)
7916 basic_block entry_bb
, bb
;
7918 rtx_insn
*insn
, *seq
, *entry_after
, *last_insn
, *end_label
;
7919 unsigned int length
;
7920 bool need_fix
= false;
7921 rtx lp_reg
= gen_rtx_REG (SImode
, LP_COUNT
);
7923 if (loop
->depth
> 1)
7926 fprintf (dump_file
, ";; loop %d is not innermost\n",
7931 if (!loop
->incoming_dest
)
7934 fprintf (dump_file
, ";; loop %d has more than one entry\n",
7939 if (loop
->incoming_dest
!= loop
->head
)
7942 fprintf (dump_file
, ";; loop %d is not entered from head\n",
7947 if (loop
->has_call
|| loop
->has_asm
)
7950 fprintf (dump_file
, ";; loop %d has invalid insn\n",
7955 /* Scan all the blocks to make sure they don't use iter_reg. */
7956 if (loop
->iter_reg_used
|| loop
->iter_reg_used_outside
)
7959 fprintf (dump_file
, ";; loop %d uses iterator\n",
7964 /* Check if start_label appears before doloop_end. */
7966 for (insn
= loop
->start_label
;
7967 insn
&& insn
!= loop
->loop_end
;
7968 insn
= NEXT_INSN (insn
))
7970 length
+= NONDEBUG_INSN_P (insn
) ? get_attr_length (insn
) : 0;
7971 if (JUMP_TABLES_IN_TEXT_SECTION
7972 && JUMP_TABLE_DATA_P (insn
))
7975 fprintf (dump_file
, ";; loop %d has a jump table\n",
7984 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
7989 loop
->length
= length
;
7990 if (loop
->length
> ARC_MAX_LOOP_LENGTH
)
7993 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
7996 else if (!loop
->length
)
7999 fprintf (dump_file
, ";; loop %d is empty\n", loop
->loop_no
);
8003 /* Check if we use a register or not. */
8004 if (!REG_P (loop
->iter_reg
))
8007 fprintf (dump_file
, ";; loop %d iterator is MEM\n",
8012 /* Check if we use a register or not. */
8013 if (!REG_P (loop
->iter_reg
))
8016 fprintf (dump_file
, ";; loop %d iterator is MEM\n",
8021 /* Check if loop register is lpcount. */
8022 if (REG_P (loop
->iter_reg
) && (REGNO (loop
->iter_reg
)) != LP_COUNT
)
8025 fprintf (dump_file
, ";; loop %d doesn't use lp_count as loop"
8028 /* This loop doesn't use the lp_count, check though if we can
8030 if (TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, LP_COUNT
)
8031 /* In very unique cases we may have LP_COUNT alive. */
8032 || (loop
->incoming_src
8033 && REGNO_REG_SET_P (df_get_live_out (loop
->incoming_src
),
8037 fprintf (dump_file
, ";; loop %d, lp_count is alive", loop
->loop_no
);
8044 /* Check for control like instruction as the last instruction of a
8047 last_insn
= PREV_INSN (loop
->loop_end
);
8051 for (; last_insn
!= BB_HEAD (bb
);
8052 last_insn
= PREV_INSN (last_insn
))
8053 if (NONDEBUG_INSN_P (last_insn
))
8056 if (last_insn
!= BB_HEAD (bb
))
8059 if (single_pred_p (bb
)
8060 && single_pred_edge (bb
)->flags
& EDGE_FALLTHRU
8061 && single_pred (bb
) != ENTRY_BLOCK_PTR_FOR_FN (cfun
))
8063 bb
= single_pred (bb
);
8064 last_insn
= BB_END (bb
);
8077 fprintf (dump_file
, ";; loop %d has no last instruction\n",
8082 if ((TARGET_ARC600_FAMILY
|| TARGET_HS
)
8083 && INSN_P (last_insn
)
8084 && (JUMP_P (last_insn
) || CALL_P (last_insn
)
8085 || GET_CODE (PATTERN (last_insn
)) == SEQUENCE
8086 /* At this stage we can have (insn (clobber (mem:BLK
8087 (reg)))) instructions, ignore them. */
8088 || (GET_CODE (PATTERN (last_insn
)) != CLOBBER
8089 && (get_attr_type (last_insn
) == TYPE_BRCC
8090 || get_attr_type (last_insn
) == TYPE_BRCC_NO_DELAY_SLOT
))))
8092 if (loop
->length
+ 2 > ARC_MAX_LOOP_LENGTH
)
8095 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
8099 fprintf (dump_file
, ";; loop %d has a control like last insn; "
8103 last_insn
= emit_insn_after (gen_nopv (), last_insn
);
8106 if (LABEL_P (last_insn
))
8109 fprintf (dump_file
, ";; loop %d has a label as last insn; "
8112 last_insn
= emit_insn_after (gen_nopv (), last_insn
);
8115 /* SAVE_NOTE is used by haifa scheduler. However, we are after it
8116 and we can use it to indicate the last ZOL instruction cannot be
8117 part of a delay slot. */
8118 add_reg_note (last_insn
, REG_SAVE_NOTE
, GEN_INT (2));
8120 loop
->last_insn
= last_insn
;
8122 /* Get the loop iteration register. */
8123 iter_reg
= loop
->iter_reg
;
8125 gcc_assert (REG_P (iter_reg
));
8129 FOR_EACH_VEC_SAFE_ELT (loop
->incoming
, i
, entry_edge
)
8130 if (entry_edge
->flags
& EDGE_FALLTHRU
)
8133 if (entry_edge
== NULL
)
8136 fprintf (dump_file
, ";; loop %d has no fallthru edge jumping "
8141 /* The loop is good. */
8142 end_label
= gen_label_rtx ();
8143 loop
->end_label
= end_label
;
8145 /* Place the zero_cost_loop_start instruction before the loop. */
8146 entry_bb
= entry_edge
->src
;
8152 /* The loop uses a R-register, but the lp_count is free, thus
8154 emit_insn (gen_rtx_SET (lp_reg
, iter_reg
));
8155 SET_HARD_REG_BIT (loop
->regs_set_in_loop
, LP_COUNT
);
8159 fprintf (dump_file
, ";; fix loop %d to use lp_count\n",
8164 insn
= emit_insn (gen_arc_lp (loop
->start_label
,
8170 entry_after
= BB_END (entry_bb
);
8171 if (!single_succ_p (entry_bb
) || vec_safe_length (loop
->incoming
) > 1
8178 emit_insn_before (seq
, BB_HEAD (loop
->head
));
8179 seq
= emit_label_before (gen_label_rtx (), seq
);
8180 new_bb
= create_basic_block (seq
, insn
, entry_bb
);
8181 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
8183 if (!(e
->flags
& EDGE_FALLTHRU
))
8184 redirect_edge_and_branch_force (e
, new_bb
);
8186 redirect_edge_succ (e
, new_bb
);
8189 make_edge (new_bb
, loop
->head
, 0);
8194 while (DEBUG_INSN_P (entry_after
)
8195 || (NOTE_P (entry_after
)
8196 && NOTE_KIND (entry_after
) != NOTE_INSN_BASIC_BLOCK
8197 /* Make sure we don't split a call and its corresponding
8198 CALL_ARG_LOCATION note. */
8199 && NOTE_KIND (entry_after
) != NOTE_INSN_CALL_ARG_LOCATION
))
8200 entry_after
= NEXT_INSN (entry_after
);
8202 entry_after
= next_nonnote_insn_bb (entry_after
);
8204 gcc_assert (entry_after
);
8205 emit_insn_before (seq
, entry_after
);
8208 /* Insert the loop end label before the last instruction of the
8210 emit_label_after (end_label
, loop
->last_insn
);
8211 /* Make sure we mark the begining and end label as used. */
8212 LABEL_NUSES (loop
->end_label
)++;
8213 LABEL_NUSES (loop
->start_label
)++;
8218 /* A callback for the hw-doloop pass. This function examines INSN; if
8219 it is a loop_end pattern we recognize, return the reg rtx for the
8220 loop counter. Otherwise, return NULL_RTX. */
8223 hwloop_pattern_reg (rtx_insn
*insn
)
8227 if (!JUMP_P (insn
) || recog_memoized (insn
) != CODE_FOR_loop_end
)
8230 reg
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 1));
8236 static struct hw_doloop_hooks arc_doloop_hooks
=
8243 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
8244 and tries to rewrite the RTL of these loops so that proper Blackfin
8245 hardware loops are generated. */
8248 arc_reorg_loops (void)
8250 reorg_loops (true, &arc_doloop_hooks
);
8253 /* Scan all calls and add symbols to be emitted in the jli section if
8257 jli_call_scan (void)
8261 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8266 rtx pat
= PATTERN (insn
);
8267 if (GET_CODE (pat
) == COND_EXEC
)
8268 pat
= COND_EXEC_CODE (pat
);
8269 pat
= XVECEXP (pat
, 0, 0);
8270 if (GET_CODE (pat
) == SET
)
8271 pat
= SET_SRC (pat
);
8273 pat
= XEXP (XEXP (pat
, 0), 0);
8274 if (GET_CODE (pat
) == SYMBOL_REF
8275 && arc_is_jli_call_p (pat
))
8276 arc_add_jli_section (pat
);
8280 /* Add padding if necessary to avoid a mispredict. A return could
8281 happen immediately after the function start. A call/return and
8282 return/return must be 6 bytes apart to avoid mispredict. */
8290 if (!TARGET_PAD_RETURN
)
8293 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8295 rtx_insn
*prev0
= prev_active_insn (insn
);
8296 bool wantlong
= false;
8298 if (!INSN_P (insn
) || GET_CODE (PATTERN (insn
)) != SIMPLE_RETURN
)
8303 prev0
= emit_insn_before (gen_nopv (), insn
);
8304 /* REG_SAVE_NOTE is used by Haifa scheduler, we are in reorg
8305 so it is safe to reuse it for forcing a particular length
8306 for an instruction. */
8307 add_reg_note (prev0
, REG_SAVE_NOTE
, GEN_INT (1));
8308 emit_insn_before (gen_nopv (), insn
);
8311 offset
= get_attr_length (prev0
);
8313 if (get_attr_length (prev0
) == 2
8314 && get_attr_iscompact (prev0
) != ISCOMPACT_TRUE
)
8316 /* Force long version of the insn. */
8321 rtx_insn
*prev
= prev_active_insn (prev0
);
8323 offset
+= get_attr_length (prev
);
8325 prev
= prev_active_insn (prev
);
8327 offset
+= get_attr_length (prev
);
8332 prev
= emit_insn_before (gen_nopv (), insn
);
8333 add_reg_note (prev
, REG_SAVE_NOTE
, GEN_INT (1));
8336 emit_insn_before (gen_nopv (), insn
);
8343 add_reg_note (prev0
, REG_SAVE_NOTE
, GEN_INT (1));
8345 /* Emit a blockage to avoid delay slot scheduling. */
8346 emit_insn_before (gen_blockage (), insn
);
8350 static int arc_reorg_in_progress
= 0;
8352 /* ARC's machince specific reorg function. */
8363 cfun
->machine
->arc_reorg_started
= 1;
8364 arc_reorg_in_progress
= 1;
8366 compute_bb_for_insn ();
8370 /* Doloop optimization. */
8373 workaround_arc_anomaly ();
8377 /* FIXME: should anticipate ccfsm action, generate special patterns for
8378 to-be-deleted branches that have no delay slot and have at least the
8379 length of the size increase forced on other insns that are conditionalized.
8380 This can also have an insn_list inside that enumerates insns which are
8381 not actually conditionalized because the destinations are dead in the
8383 Could also tag branches that we want to be unaligned if they get no delay
8384 slot, or even ones that we don't want to do delay slot sheduling for
8385 because we can unalign them.
8387 However, there are cases when conditional execution is only possible after
8388 delay slot scheduling:
8390 - If a delay slot is filled with a nocond/set insn from above, the previous
8391 basic block can become elegible for conditional execution.
8392 - If a delay slot is filled with a nocond insn from the fall-through path,
8393 the branch with that delay slot can become eligble for conditional
8394 execution (however, with the same sort of data flow analysis that dbr
8395 does, we could have figured out before that we don't need to
8396 conditionalize this insn.)
8397 - If a delay slot insn is filled with an insn from the target, the
8398 target label gets its uses decremented (even deleted if falling to zero),
8399 thus possibly creating more condexec opportunities there.
8400 Therefore, we should still be prepared to apply condexec optimization on
8401 non-prepared branches if the size increase of conditionalized insns is no
8402 more than the size saved from eliminating the branch. An invocation option
8403 could also be used to reserve a bit of extra size for condbranches so that
8404 this'll work more often (could also test in arc_reorg if the block is
8405 'close enough' to be eligible for condexec to make this likely, and
8406 estimate required size increase). */
8407 /* Generate BRcc insns, by combining cmp and Bcc insns wherever possible. */
8408 if (TARGET_NO_BRCC_SET
)
8413 init_insn_lengths();
8416 if (optimize
> 1 && !TARGET_NO_COND_EXEC
)
8419 unsigned int flags
= pass_data_arc_ifcvt
.todo_flags_finish
;
8420 df_finish_pass ((flags
& TODO_df_verify
) != 0);
8424 fprintf (dump_file
, ";; After if conversion:\n\n");
8425 print_rtl (dump_file
, get_insns ());
8429 /* Call shorten_branches to calculate the insn lengths. */
8430 shorten_branches (get_insns());
8431 cfun
->machine
->ccfsm_current_insn
= NULL_RTX
;
8433 if (!INSN_ADDRESSES_SET_P())
8434 fatal_error (input_location
,
8435 "insn addresses not set after shorten branches");
8437 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8440 enum attr_type insn_type
;
8442 /* If a non-jump insn (or a casesi jump table), continue. */
8443 if (GET_CODE (insn
) != JUMP_INSN
||
8444 GET_CODE (PATTERN (insn
)) == ADDR_VEC
8445 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
8448 /* If we already have a brcc, note if it is suitable for brcc_s.
8449 Be a bit generous with the brcc_s range so that we can take
8450 advantage of any code shortening from delay slot scheduling. */
8451 if (recog_memoized (insn
) == CODE_FOR_cbranchsi4_scratch
)
8453 rtx pat
= PATTERN (insn
);
8454 rtx op
= XEXP (SET_SRC (XVECEXP (pat
, 0, 0)), 0);
8455 rtx
*ccp
= &XEXP (XVECEXP (pat
, 0, 1), 0);
8457 offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
8458 if ((offset
>= -140 && offset
< 140)
8459 && rtx_equal_p (XEXP (op
, 1), const0_rtx
)
8460 && compact_register_operand (XEXP (op
, 0), VOIDmode
)
8461 && equality_comparison_operator (op
, VOIDmode
))
8462 PUT_MODE (*ccp
, CC_Zmode
);
8463 else if (GET_MODE (*ccp
) == CC_Zmode
)
8464 PUT_MODE (*ccp
, CC_ZNmode
);
8467 if ((insn_type
= get_attr_type (insn
)) == TYPE_BRCC
8468 || insn_type
== TYPE_BRCC_NO_DELAY_SLOT
)
8471 /* OK. so we have a jump insn. */
8472 /* We need to check that it is a bcc. */
8473 /* Bcc => set (pc) (if_then_else ) */
8474 pattern
= PATTERN (insn
);
8475 if (GET_CODE (pattern
) != SET
8476 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
8477 || ANY_RETURN_P (XEXP (SET_SRC (pattern
), 1)))
8480 /* Now check if the jump is beyond the s9 range. */
8481 if (CROSSING_JUMP_P (insn
))
8483 offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
8485 if(offset
> 253 || offset
< -254)
8488 pc_target
= SET_SRC (pattern
);
8490 /* Avoid FPU instructions. */
8491 if ((GET_MODE (XEXP (XEXP (pc_target
, 0), 0)) == CC_FPUmode
)
8492 || (GET_MODE (XEXP (XEXP (pc_target
, 0), 0)) == CC_FPUEmode
)
8493 || (GET_MODE (XEXP (XEXP (pc_target
, 0), 0)) == CC_FPU_UNEQmode
))
8496 /* Now go back and search for the set cc insn. */
8498 label
= XEXP (pc_target
, 1);
8502 rtx_insn
*scan
, *link_insn
= NULL
;
8504 for (scan
= PREV_INSN (insn
);
8505 scan
&& GET_CODE (scan
) != CODE_LABEL
;
8506 scan
= PREV_INSN (scan
))
8508 if (! INSN_P (scan
))
8510 pat
= PATTERN (scan
);
8511 if (GET_CODE (pat
) == SET
8512 && cc_register (SET_DEST (pat
), VOIDmode
))
8522 /* Check if this is a data dependency. */
8523 rtx op
, cc_clob_rtx
, op0
, op1
, brcc_insn
, note
;
8526 /* Make sure we can use it for brcc insns. */
8527 if (find_reg_note (link_insn
, REG_SAVE_NOTE
, GEN_INT (3)))
8530 /* Ok this is the set cc. copy args here. */
8531 op
= XEXP (pc_target
, 0);
8533 op0
= cmp0
= XEXP (SET_SRC (pat
), 0);
8534 op1
= cmp1
= XEXP (SET_SRC (pat
), 1);
8535 if (GET_CODE (op0
) == ZERO_EXTRACT
8536 && XEXP (op0
, 1) == const1_rtx
8537 && (GET_CODE (op
) == EQ
8538 || GET_CODE (op
) == NE
))
8540 /* btst / b{eq,ne} -> bbit{0,1} */
8541 op0
= XEXP (cmp0
, 0);
8542 op1
= XEXP (cmp0
, 2);
8544 else if (!register_operand (op0
, VOIDmode
)
8545 || !general_operand (op1
, VOIDmode
))
8547 /* Be careful not to break what cmpsfpx_raw is
8548 trying to create for checking equality of
8549 single-precision floats. */
8550 else if (TARGET_SPFP
8551 && GET_MODE (op0
) == SFmode
8552 && GET_MODE (op1
) == SFmode
)
8555 /* None of the two cmp operands should be set between the
8556 cmp and the branch. */
8557 if (reg_set_between_p (op0
, link_insn
, insn
))
8560 if (reg_set_between_p (op1
, link_insn
, insn
))
8563 /* Since the MODE check does not work, check that this is
8564 CC reg's last set location before insn, and also no
8565 instruction between the cmp and branch uses the
8567 if ((reg_set_between_p (SET_DEST (pat
), link_insn
, insn
))
8568 || (reg_used_between_p (SET_DEST (pat
), link_insn
, insn
)))
8571 /* CC reg should be dead after insn. */
8572 if (!find_regno_note (insn
, REG_DEAD
, CC_REG
))
8575 op
= gen_rtx_fmt_ee (GET_CODE (op
),
8576 GET_MODE (op
), cmp0
, cmp1
);
8577 /* If we create a LIMM where there was none before,
8578 we only benefit if we can avoid a scheduling bubble
8579 for the ARC600. Otherwise, we'd only forgo chances
8580 at short insn generation, and risk out-of-range
8582 if (!brcc_nolimm_operator (op
, VOIDmode
)
8583 && !long_immediate_operand (op1
, VOIDmode
)
8585 || (TARGET_V2
&& optimize_size
)
8586 || next_active_insn (link_insn
) != insn
))
8589 /* Emit bbit / brcc (or brcc_s if possible).
8590 CC_Zmode indicates that brcc_s is possible. */
8593 cc_clob_rtx
= gen_rtx_REG (CC_ZNmode
, CC_REG
);
8594 else if ((offset
>= -140 && offset
< 140)
8595 && rtx_equal_p (op1
, const0_rtx
)
8596 && compact_register_operand (op0
, VOIDmode
)
8597 && (GET_CODE (op
) == EQ
8598 || GET_CODE (op
) == NE
))
8599 cc_clob_rtx
= gen_rtx_REG (CC_Zmode
, CC_REG
);
8601 cc_clob_rtx
= gen_rtx_REG (CCmode
, CC_REG
);
8604 = gen_rtx_IF_THEN_ELSE (VOIDmode
, op
, label
, pc_rtx
);
8605 brcc_insn
= gen_rtx_SET (pc_rtx
, brcc_insn
);
8606 cc_clob_rtx
= gen_rtx_CLOBBER (VOIDmode
, cc_clob_rtx
);
8609 (VOIDmode
, gen_rtvec (2, brcc_insn
, cc_clob_rtx
));
8610 brcc_insn
= emit_jump_insn_before (brcc_insn
, insn
);
8612 JUMP_LABEL (brcc_insn
) = JUMP_LABEL (insn
);
8613 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
8616 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
8617 REG_NOTES (brcc_insn
) = note
;
8619 note
= find_reg_note (link_insn
, REG_DEAD
, op0
);
8622 remove_note (link_insn
, note
);
8623 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
8624 REG_NOTES (brcc_insn
) = note
;
8626 note
= find_reg_note (link_insn
, REG_DEAD
, op1
);
8629 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
8630 REG_NOTES (brcc_insn
) = note
;
8635 /* Delete the bcc insn. */
8636 set_insn_deleted (insn
);
8638 /* Delete the cmp insn. */
8639 set_insn_deleted (link_insn
);
8644 /* Clear out insn_addresses. */
8645 INSN_ADDRESSES_FREE ();
8649 if (INSN_ADDRESSES_SET_P())
8650 fatal_error (input_location
, "insn addresses not freed");
8652 arc_reorg_in_progress
= 0;
8655 /* Check if the operands are valid for BRcc.d generation
8656 Valid Brcc.d patterns are
8660 For cc={GT, LE, GTU, LEU}, u6=63 cannot be allowed,
8661 since they are encoded by the assembler as {GE, LT, HS, LS} 64, which
8662 does not have a delay slot
8664 Assumed precondition: Second operand is either a register or a u6 value. */
8667 valid_brcc_with_delay_p (rtx
*operands
)
8669 if (optimize_size
&& GET_MODE (operands
[4]) == CC_Zmode
)
8671 return brcc_nolimm_operator (operands
[0], VOIDmode
);
8674 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
8675 access DECL using %gp_rel(...)($gp). */
8678 arc_in_small_data_p (const_tree decl
)
8683 /* Only variables are going into small data area. */
8684 if (TREE_CODE (decl
) != VAR_DECL
)
8687 if (TARGET_NO_SDATA_SET
)
8690 /* Disable sdata references to weak variables. */
8691 if (DECL_WEAK (decl
))
8694 /* Don't put constants into the small data section: we want them to
8695 be in ROM rather than RAM. */
8696 if (TREE_READONLY (decl
))
8699 /* To ensure -mvolatile-cache works ld.di does not have a
8700 gp-relative variant. */
8701 if (!TARGET_VOLATILE_CACHE_SET
8702 && TREE_THIS_VOLATILE (decl
))
8705 /* Likewise for uncached data. */
8706 attr
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
8707 if (lookup_attribute ("uncached", attr
))
8710 /* and for aux regs. */
8711 attr
= DECL_ATTRIBUTES (decl
);
8712 if (lookup_attribute ("aux", attr
))
8715 if (DECL_SECTION_NAME (decl
) != 0)
8717 const char *name
= DECL_SECTION_NAME (decl
);
8718 if (strcmp (name
, ".sdata") == 0
8719 || strcmp (name
, ".sbss") == 0)
8722 /* If it's not public, there's no need to put it in the small data
8724 else if (TREE_PUBLIC (decl
))
8726 size
= int_size_in_bytes (TREE_TYPE (decl
));
8727 return (size
> 0 && size
<= g_switch_value
);
8732 /* Return true if OP is an acceptable memory operand for ARCompact
8733 16-bit gp-relative load instructions.
8735 /* volatile cache option still to be handled. */
8738 compact_sda_memory_operand (rtx op
, machine_mode mode
, bool short_p
)
8745 /* Eliminate non-memory operations. */
8746 if (GET_CODE (op
) != MEM
)
8749 if (mode
== VOIDmode
)
8750 mode
= GET_MODE (op
);
8752 size
= GET_MODE_SIZE (mode
);
8754 /* dword operations really put out 2 instructions, so eliminate them. */
8755 if (size
> UNITS_PER_WORD
)
8758 /* Decode the address now. */
8759 addr
= XEXP (op
, 0);
8761 if (!legitimate_small_data_address_p (addr
, mode
))
8764 if (!short_p
|| size
== 1)
8767 /* Now check for the alignment, the short loads using gp require the
8768 addresses to be aligned. */
8769 align
= get_symbol_alignment (addr
);
8780 if (align
&& ((align
& mask
) == 0))
8785 /* Return TRUE if PAT is accessing an aux-reg. */
8788 arc_is_aux_reg_p (rtx pat
)
8790 tree attrs
= NULL_TREE
;
8796 /* Get the memory attributes. */
8797 addr
= MEM_EXPR (pat
);
8801 /* Get the attributes. */
8802 if (TREE_CODE (addr
) == VAR_DECL
)
8803 attrs
= DECL_ATTRIBUTES (addr
);
8804 else if (TREE_CODE (addr
) == MEM_REF
)
8805 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr
, 0)));
8809 if (lookup_attribute ("aux", attrs
))
8814 /* Implement ASM_OUTPUT_ALIGNED_DECL_LOCAL. */
8817 arc_asm_output_aligned_decl_local (FILE * stream
, tree decl
, const char * name
,
8818 unsigned HOST_WIDE_INT size
,
8819 unsigned HOST_WIDE_INT align
,
8820 unsigned HOST_WIDE_INT globalize_p
)
8822 int in_small_data
= arc_in_small_data_p (decl
);
8823 rtx mem
= decl
== NULL_TREE
? NULL_RTX
: DECL_RTL (decl
);
8825 /* Don't output aux-reg symbols. */
8826 if (mem
!= NULL_RTX
&& MEM_P (mem
)
8827 && SYMBOL_REF_P (XEXP (mem
, 0))
8828 && arc_is_aux_reg_p (mem
))
8832 switch_to_section (get_named_section (NULL
, ".sbss", 0));
8833 /* named_section (0,".sbss",0); */
8835 switch_to_section (bss_section
);
8838 (*targetm
.asm_out
.globalize_label
) (stream
, name
);
8840 ASM_OUTPUT_ALIGN (stream
, floor_log2 ((align
) / BITS_PER_UNIT
));
8841 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8842 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8843 ASM_OUTPUT_LABEL (stream
, name
);
8846 ASM_OUTPUT_SKIP (stream
, size
);
8850 arc_preserve_reload_p (rtx in
)
8852 return (GET_CODE (in
) == PLUS
8853 && RTX_OK_FOR_BASE_P (XEXP (in
, 0), true)
8854 && CONST_INT_P (XEXP (in
, 1))
8855 && !((INTVAL (XEXP (in
, 1)) & 511)));
8858 /* Implement TARGET_REGISTER_MOVE_COST. */
8861 arc_register_move_cost (machine_mode
,
8862 reg_class_t from_class
, reg_class_t to_class
)
8864 /* Force an attempt to 'mov Dy,Dx' to spill. */
8865 if ((TARGET_ARC700
|| TARGET_EM
) && TARGET_DPFP
8866 && from_class
== DOUBLE_REGS
&& to_class
== DOUBLE_REGS
)
8872 /* Emit code for an addsi3 instruction with OPERANDS.
8873 COND_P indicates if this will use conditional execution.
8874 Return the length of the instruction.
8875 If OUTPUT_P is false, don't actually output the instruction, just return
8878 arc_output_addsi (rtx
*operands
, bool cond_p
, bool output_p
)
8882 int match
= operands_match_p (operands
[0], operands
[1]);
8883 int match2
= operands_match_p (operands
[0], operands
[2]);
8884 int intval
= (REG_P (operands
[2]) ? 1
8885 : CONST_INT_P (operands
[2]) ? INTVAL (operands
[2]) : 0xbadc057);
8886 int neg_intval
= -intval
;
8887 int short_0
= satisfies_constraint_Rcq (operands
[0]);
8888 int short_p
= (!cond_p
&& short_0
&& satisfies_constraint_Rcq (operands
[1]));
8891 #define REG_H_P(OP) (REG_P (OP) && ((TARGET_V2 && REGNO (OP) <= 31 \
8892 && REGNO (OP) != 30) \
8895 #define ADDSI_OUTPUT1(FORMAT) do {\
8897 output_asm_insn (FORMAT, operands);\
8900 #define ADDSI_OUTPUT(LIST) do {\
8903 ADDSI_OUTPUT1 (format);\
8907 /* First try to emit a 16 bit insn. */
8910 /* If we are actually about to output this insn, don't try a 16 bit
8911 variant if we already decided that we don't want that
8912 (I.e. we upsized this insn to align some following insn.)
8913 E.g. add_s r0,sp,70 is 16 bit, but add r0,sp,70 requires a LIMM -
8914 but add1 r0,sp,35 doesn't. */
8915 && (!output_p
|| (get_attr_length (current_output_insn
) & 2)))
8917 /* Generate add_s a,b,c; add_s b,b,u7; add_s c,b,u3; add_s b,b,h
8920 && ((REG_H_P (operands
[2])
8921 && (match
|| satisfies_constraint_Rcq (operands
[2])))
8922 || (CONST_INT_P (operands
[2])
8923 && ((unsigned) intval
<= (match
? 127 : 7)))))
8924 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;1");
8926 /* Generate add_s b,b,h patterns. */
8927 if (short_0
&& match2
&& REG_H_P (operands
[1]))
8928 ADDSI_OUTPUT1 ("add%? %0,%2,%1 ;2");
8930 /* Generate add_s b,sp,u7; add_s sp,sp,u7 patterns. */
8931 if ((short_0
|| REGNO (operands
[0]) == STACK_POINTER_REGNUM
)
8932 && REGNO (operands
[1]) == STACK_POINTER_REGNUM
&& !(intval
& ~124))
8933 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;3");
8935 if ((short_p
&& (unsigned) neg_intval
<= (match
? 31 : 7))
8936 || (REGNO (operands
[0]) == STACK_POINTER_REGNUM
8937 && match
&& !(neg_intval
& ~124)))
8938 ADDSI_OUTPUT1 ("sub%? %0,%1,%n2 ;4");
8940 /* Generate add_s h,h,s3 patterns. */
8941 if (REG_H_P (operands
[0]) && match
&& TARGET_V2
8942 && CONST_INT_P (operands
[2]) && ((intval
>= -1) && (intval
<= 6)))
8943 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;5");
8945 /* Generate add_s r0,b,u6; add_s r1,b,u6 patterns. */
8946 if (TARGET_CODE_DENSITY
&& REG_P (operands
[0]) && REG_P (operands
[1])
8947 && ((REGNO (operands
[0]) == 0) || (REGNO (operands
[0]) == 1))
8948 && satisfies_constraint_Rcq (operands
[1])
8949 && satisfies_constraint_L (operands
[2]))
8950 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;6");
8953 /* Now try to emit a 32 bit insn without long immediate. */
8955 if (!match
&& match2
&& REG_P (operands
[1]))
8956 ADDSI_OUTPUT1 ("add%? %0,%2,%1");
8957 if (match
|| !cond_p
)
8959 int limit
= (match
&& !cond_p
) ? 0x7ff : 0x3f;
8960 int range_factor
= neg_intval
& intval
;
8963 if (intval
== (HOST_WIDE_INT
) (HOST_WIDE_INT_M1U
<< 31))
8964 ADDSI_OUTPUT1 ("bxor%? %0,%1,31");
8966 /* If we can use a straight add / sub instead of a {add,sub}[123] of
8967 same size, do, so - the insn latency is lower. */
8968 /* -0x800 is a 12-bit constant for add /add3 / sub / sub3, but
8970 if ((intval
>= 0 && intval
<= limit
)
8971 || (intval
== -0x800 && limit
== 0x7ff))
8972 ADDSI_OUTPUT1 ("add%? %0,%1,%2");
8973 else if ((intval
< 0 && neg_intval
<= limit
)
8974 || (intval
== 0x800 && limit
== 0x7ff))
8975 ADDSI_OUTPUT1 ("sub%? %0,%1,%n2");
8976 shift
= range_factor
>= 8 ? 3 : (range_factor
>> 1);
8977 gcc_assert (shift
== 0 || shift
== 1 || shift
== 2 || shift
== 3);
8978 gcc_assert ((((1 << shift
) - 1) & intval
) == 0);
8979 if (((intval
< 0 && intval
!= -0x4000)
8980 /* sub[123] is slower than add_s / sub, only use it if it
8981 avoids a long immediate. */
8982 && neg_intval
<= limit
<< shift
)
8983 || (intval
== 0x4000 && limit
== 0x7ff))
8984 ADDSI_OUTPUT ((format
, "sub%d%%? %%0,%%1,%d",
8985 shift
, neg_intval
>> shift
));
8986 else if ((intval
>= 0 && intval
<= limit
<< shift
)
8987 || (intval
== -0x4000 && limit
== 0x7ff))
8988 ADDSI_OUTPUT ((format
, "add%d%%? %%0,%%1,%d", shift
, intval
>> shift
));
8990 /* Try to emit a 16 bit opcode with long immediate. */
8992 if (short_p
&& match
)
8993 ADDSI_OUTPUT1 ("add%? %0,%1,%2");
8995 /* We have to use a 32 bit opcode, and with a long immediate. */
8997 ADDSI_OUTPUT1 (intval
< 0 ? "sub%? %0,%1,%n2" : "add%? %0,%1,%2");
9000 /* Emit code for an commutative_cond_exec instruction with OPERANDS.
9001 Return the length of the instruction.
9002 If OUTPUT_P is false, don't actually output the instruction, just return
9005 arc_output_commutative_cond_exec (rtx
*operands
, bool output_p
)
9007 enum rtx_code commutative_op
= GET_CODE (operands
[3]);
9008 const char *pat
= NULL
;
9010 /* Canonical rtl should not have a constant in the first operand position. */
9011 gcc_assert (!CONSTANT_P (operands
[1]));
9013 switch (commutative_op
)
9016 if (satisfies_constraint_C1p (operands
[2]))
9017 pat
= "bmsk%? %0,%1,%Z2";
9018 else if (satisfies_constraint_C2p (operands
[2]))
9020 operands
[2] = GEN_INT ((~INTVAL (operands
[2])));
9021 pat
= "bmskn%? %0,%1,%Z2";
9023 else if (satisfies_constraint_Ccp (operands
[2]))
9024 pat
= "bclr%? %0,%1,%M2";
9025 else if (satisfies_constraint_CnL (operands
[2]))
9026 pat
= "bic%? %0,%1,%n2-1";
9029 if (satisfies_constraint_C0p (operands
[2]))
9030 pat
= "bset%? %0,%1,%z2";
9033 if (satisfies_constraint_C0p (operands
[2]))
9034 pat
= "bxor%? %0,%1,%z2";
9037 return arc_output_addsi (operands
, true, output_p
);
9041 output_asm_insn (pat
? pat
: "%O3.%d5 %0,%1,%2", operands
);
9042 if (pat
|| REG_P (operands
[2]) || satisfies_constraint_L (operands
[2]))
9047 /* Helper function of arc_expand_cpymem. ADDR points to a chunk of memory.
9048 Emit code and return an potentially modified address such that offsets
9049 up to SIZE are can be added to yield a legitimate address.
9050 if REUSE is set, ADDR is a register that may be modified. */
9053 force_offsettable (rtx addr
, HOST_WIDE_INT size
, bool reuse
)
9056 rtx offs
= const0_rtx
;
9058 if (GET_CODE (base
) == PLUS
)
9060 offs
= XEXP (base
, 1);
9061 base
= XEXP (base
, 0);
9064 || (REGNO (base
) != STACK_POINTER_REGNUM
9065 && REGNO_PTR_FRAME_P (REGNO (base
)))
9066 || !CONST_INT_P (offs
) || !SMALL_INT (INTVAL (offs
))
9067 || !SMALL_INT (INTVAL (offs
) + size
))
9070 emit_insn (gen_add2_insn (addr
, offs
));
9072 addr
= copy_to_mode_reg (Pmode
, addr
);
9077 /* Like move_by_pieces, but take account of load latency, and actual
9078 offset ranges. Return true on success. */
9081 arc_expand_cpymem (rtx
*operands
)
9083 rtx dst
= operands
[0];
9084 rtx src
= operands
[1];
9085 rtx dst_addr
, src_addr
;
9087 int align
= INTVAL (operands
[3]);
9094 if (!CONST_INT_P (operands
[2]))
9096 size
= INTVAL (operands
[2]);
9097 /* move_by_pieces_ninsns is static, so we can't use it. */
9101 n_pieces
= (size
+ 4) / 8U + ((size
>> 1) & 1) + (size
& 1);
9103 n_pieces
= (size
+ 2) / 4U + (size
& 1);
9105 else if (align
== 2)
9106 n_pieces
= (size
+ 1) / 2U;
9109 if (n_pieces
>= (unsigned int) (optimize_size
? 3 : 15))
9111 /* Force 32 bit aligned and larger datum to use 64 bit transfers, if
9113 if (TARGET_LL64
&& (piece
>= 4) && (size
>= 8))
9117 dst_addr
= force_offsettable (XEXP (operands
[0], 0), size
, 0);
9118 src_addr
= force_offsettable (XEXP (operands
[1], 0), size
, 0);
9119 store
[0] = store
[1] = NULL_RTX
;
9120 tmpx
[0] = tmpx
[1] = NULL_RTX
;
9121 for (i
= 0; size
> 0; i
^= 1, size
-= piece
)
9126 while (piece
> size
)
9128 mode
= smallest_int_mode_for_size (piece
* BITS_PER_UNIT
);
9129 /* If we don't re-use temporaries, the scheduler gets carried away,
9130 and the register pressure gets unnecessarily high. */
9131 if (0 && tmpx
[i
] && GET_MODE (tmpx
[i
]) == mode
)
9134 tmpx
[i
] = tmp
= gen_reg_rtx (mode
);
9135 dst_addr
= force_offsettable (dst_addr
, piece
, 1);
9136 src_addr
= force_offsettable (src_addr
, piece
, 1);
9138 emit_insn (store
[i
]);
9139 emit_move_insn (tmp
, change_address (src
, mode
, src_addr
));
9140 store
[i
] = gen_move_insn (change_address (dst
, mode
, dst_addr
), tmp
);
9141 dst_addr
= plus_constant (Pmode
, dst_addr
, piece
);
9142 src_addr
= plus_constant (Pmode
, src_addr
, piece
);
9145 emit_insn (store
[i
]);
9147 emit_insn (store
[i
^1]);
9152 arc_get_aux_arg (rtx pat
, int *auxr
)
9154 tree attr
, addr
= MEM_EXPR (pat
);
9155 if (TREE_CODE (addr
) != VAR_DECL
)
9158 attr
= DECL_ATTRIBUTES (addr
);
9159 if (lookup_attribute ("aux", attr
))
9161 tree arg
= TREE_VALUE (attr
);
9164 *auxr
= TREE_INT_CST_LOW (TREE_VALUE (arg
));
9172 /* Prepare operands for move in MODE. Return true iff the move has
9176 prepare_move_operands (rtx
*operands
, machine_mode mode
)
9178 if ((MEM_P (operands
[0]) || MEM_P (operands
[1]))
9179 && SCALAR_INT_MODE_P (mode
))
9181 /* First handle aux attribute. */
9186 if (MEM_P (operands
[0]) && arc_is_aux_reg_p (operands
[0]))
9188 /* Save operation. */
9189 if (arc_get_aux_arg (operands
[0], &auxr
))
9191 tmp
= gen_reg_rtx (SImode
);
9192 emit_move_insn (tmp
, GEN_INT (auxr
));
9195 tmp
= XEXP (operands
[0], 0);
9197 operands
[1] = force_reg (SImode
, operands
[1]);
9198 emit_insn (gen_rtx_UNSPEC_VOLATILE
9199 (VOIDmode
, gen_rtvec (2, operands
[1], tmp
),
9203 if (MEM_P (operands
[1]) && arc_is_aux_reg_p (operands
[1]))
9205 if (arc_get_aux_arg (operands
[1], &auxr
))
9207 tmp
= gen_reg_rtx (SImode
);
9208 emit_move_insn (tmp
, GEN_INT (auxr
));
9212 tmp
= XEXP (operands
[1], 0);
9213 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
9215 /* Load operation. */
9216 gcc_assert (REG_P (operands
[0]));
9217 emit_insn (gen_rtx_SET (operands
[0],
9218 gen_rtx_UNSPEC_VOLATILE
9219 (SImode
, gen_rtvec (1, tmp
),
9224 /* Second, we check for the uncached. */
9225 if (arc_is_uncached_mem_p (operands
[0]))
9227 if (!REG_P (operands
[1]))
9228 operands
[1] = force_reg (mode
, operands
[1]);
9229 emit_insn (gen_rtx_UNSPEC_VOLATILE
9230 (VOIDmode
, gen_rtvec (2, operands
[0], operands
[1]),
9234 if (arc_is_uncached_mem_p (operands
[1]))
9236 rtx tmp
= operands
[0];
9238 if (MEM_P (operands
[0]))
9239 tmp
= gen_reg_rtx (mode
);
9241 emit_insn (gen_rtx_SET
9243 gen_rtx_UNSPEC_VOLATILE
9244 (mode
, gen_rtvec (1, operands
[1]),
9245 VUNSPEC_ARC_LDDI
)));
9246 if (MEM_P (operands
[0]))
9255 if (GET_CODE (operands
[1]) == SYMBOL_REF
)
9257 enum tls_model model
= SYMBOL_REF_TLS_MODEL (operands
[1]);
9258 if (MEM_P (operands
[0]))
9259 operands
[1] = force_reg (mode
, operands
[1]);
9261 operands
[1] = arc_legitimize_tls_address (operands
[1], model
);
9264 operands
[1] = arc_legitimize_pic_address (operands
[1]);
9266 /* Store instructions are limited, they only accept as address an
9267 immediate, a register or a register plus a small immediate. */
9268 if (MEM_P (operands
[0])
9269 && !move_dest_operand (operands
[0], mode
))
9271 rtx tmp0
= copy_to_mode_reg (Pmode
, XEXP (operands
[0], 0));
9272 rtx tmp1
= change_address (operands
[0], mode
, tmp0
);
9273 MEM_COPY_ATTRIBUTES (tmp1
, operands
[0]);
9277 /* Check if it is constant but it is not legitimized. */
9278 if (CONSTANT_P (operands
[1])
9279 && !arc_legitimate_constant_p (mode
, operands
[1]))
9280 operands
[1] = force_reg (mode
, XEXP (operands
[1], 0));
9281 else if (MEM_P (operands
[0])
9282 && ((CONSTANT_P (operands
[1])
9283 && !satisfies_constraint_Cm3 (operands
[1]))
9284 || MEM_P (operands
[1])))
9285 operands
[1] = force_reg (mode
, operands
[1]);
9290 /* Output a library call to a function called FNAME that has been arranged
9291 to be local to any dso. */
9294 arc_output_libcall (const char *fname
)
9296 unsigned len
= strlen (fname
);
9297 static char buf
[64];
9299 gcc_assert (len
< sizeof buf
- 35);
9300 if (TARGET_LONG_CALLS_SET
9301 || (TARGET_MEDIUM_CALLS
&& arc_ccfsm_cond_exec_p ()))
9304 sprintf (buf
, "add r12,pcl,@%s@pcl\n\tjl%%!%%* [r12]", fname
);
9306 sprintf (buf
, "jl%%! @%s", fname
);
9309 sprintf (buf
, "bl%%!%%* @%s", fname
);
9313 /* Return the SImode highpart of the DImode value IN. */
9316 disi_highpart (rtx in
)
9318 return simplify_gen_subreg (SImode
, in
, DImode
, TARGET_BIG_ENDIAN
? 0 : 4);
9321 /* Return length adjustment for INSN.
9323 A write to a core reg greater or equal to 32 must not be immediately
9324 followed by a use. Anticipate the length requirement to insert a nop
9325 between PRED and SUCC to prevent a hazard. */
9328 arc600_corereg_hazard (rtx_insn
*pred
, rtx_insn
*succ
)
9332 if (GET_CODE (PATTERN (pred
)) == SEQUENCE
)
9333 pred
= as_a
<rtx_sequence
*> (PATTERN (pred
))->insn (1);
9334 if (GET_CODE (PATTERN (succ
)) == SEQUENCE
)
9335 succ
= as_a
<rtx_sequence
*> (PATTERN (succ
))->insn (0);
9336 if (recog_memoized (pred
) == CODE_FOR_mulsi_600
9337 || recog_memoized (pred
) == CODE_FOR_umul_600
9338 || recog_memoized (pred
) == CODE_FOR_mac_600
9339 || recog_memoized (pred
) == CODE_FOR_mul64_600
9340 || recog_memoized (pred
) == CODE_FOR_mac64_600
9341 || recog_memoized (pred
) == CODE_FOR_umul64_600
9342 || recog_memoized (pred
) == CODE_FOR_umac64_600
)
9344 subrtx_iterator::array_type array
;
9345 FOR_EACH_SUBRTX (iter
, array
, PATTERN (pred
), NONCONST
)
9347 const_rtx x
= *iter
;
9348 switch (GET_CODE (x
))
9350 case SET
: case POST_INC
: case POST_DEC
: case PRE_INC
: case PRE_DEC
:
9353 /* This is also fine for PRE/POST_MODIFY, because they
9357 rtx dest
= XEXP (x
, 0);
9358 /* Check if this sets an extension register. N.B. we use 61 for the
9359 condition codes, which is definitely not an extension register. */
9360 if (REG_P (dest
) && REGNO (dest
) >= 32 && REGNO (dest
) < 61
9361 /* Check if the same register is used by the PAT. */
9362 && (refers_to_regno_p
9364 REGNO (dest
) + (GET_MODE_SIZE (GET_MODE (dest
)) + 3) / 4U,
9365 PATTERN (succ
), 0)))
9371 /* Given a rtx, check if it is an assembly instruction or not. */
9374 arc_asm_insn_p (rtx x
)
9381 switch (GET_CODE (x
))
9388 return arc_asm_insn_p (SET_SRC (x
));
9392 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
9393 j
+= arc_asm_insn_p (XVECEXP (x
, 0, i
));
9406 A write to a core reg greater or equal to 32 must not be immediately
9407 followed by a use. Anticipate the length requirement to insert a nop
9408 between PRED and SUCC to prevent a hazard. */
9411 arc_hazard (rtx_insn
*pred
, rtx_insn
*succ
)
9413 if (!pred
|| !INSN_P (pred
) || !succ
|| !INSN_P (succ
))
9417 return arc600_corereg_hazard (pred
, succ
);
9422 /* Return length adjustment for INSN. */
9425 arc_adjust_insn_length (rtx_insn
*insn
, int len
, bool)
9429 /* We already handle sequences by ignoring the delay sequence flag. */
9430 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
9433 /* Check for return with but one preceding insn since function
9435 if (TARGET_PAD_RETURN
9437 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
9438 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
9439 && get_attr_type (insn
) == TYPE_RETURN
)
9441 rtx_insn
*prev
= prev_active_insn (insn
);
9443 if (!prev
|| !(prev
= prev_active_insn (prev
))
9444 || ((NONJUMP_INSN_P (prev
)
9445 && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
9446 ? CALL_ATTR (as_a
<rtx_sequence
*> (PATTERN (prev
))->insn (0),
9448 : CALL_ATTR (prev
, NON_SIBCALL
)))
9453 rtx_insn
*succ
= next_real_insn (insn
);
9455 /* One the ARC600, a write to an extension register must be separated
9457 if (succ
&& INSN_P (succ
))
9458 len
+= arc600_corereg_hazard (insn
, succ
);
9461 /* Restore extracted operands - otherwise splitters like the addsi3_mixed one
9463 extract_constrain_insn_cached (insn
);
9468 /* Return a copy of COND from *STATEP, inverted if that is indicated by the
9469 CC field of *STATEP. */
9472 arc_get_ccfsm_cond (struct arc_ccfsm
*statep
, bool reverse
)
9474 rtx cond
= statep
->cond
;
9475 int raw_cc
= get_arc_condition_code (cond
);
9477 raw_cc
= ARC_INVERSE_CONDITION_CODE (raw_cc
);
9479 if (statep
->cc
== raw_cc
)
9480 return copy_rtx (cond
);
9482 gcc_assert (ARC_INVERSE_CONDITION_CODE (raw_cc
) == statep
->cc
);
9484 machine_mode ccm
= GET_MODE (XEXP (cond
, 0));
9485 enum rtx_code code
= reverse_condition (GET_CODE (cond
));
9486 if (code
== UNKNOWN
|| ccm
== CC_FP_GTmode
|| ccm
== CC_FP_GEmode
)
9487 code
= reverse_condition_maybe_unordered (GET_CODE (cond
));
9489 return gen_rtx_fmt_ee (code
, GET_MODE (cond
),
9490 copy_rtx (XEXP (cond
, 0)), copy_rtx (XEXP (cond
, 1)));
9493 /* Return version of PAT conditionalized with COND, which is part of INSN.
9494 ANNULLED indicates if INSN is an annulled delay-slot insn.
9495 Register further changes if necessary. */
9497 conditionalize_nonjump (rtx pat
, rtx cond
, rtx insn
, bool annulled
)
9499 /* For commutative operators, we generally prefer to have
9500 the first source match the destination. */
9501 if (GET_CODE (pat
) == SET
)
9503 rtx src
= SET_SRC (pat
);
9505 if (COMMUTATIVE_P (src
))
9507 rtx src0
= XEXP (src
, 0);
9508 rtx src1
= XEXP (src
, 1);
9509 rtx dst
= SET_DEST (pat
);
9511 if (rtx_equal_p (src1
, dst
) && !rtx_equal_p (src0
, dst
)
9512 /* Leave add_n alone - the canonical form is to
9513 have the complex summand first. */
9515 pat
= gen_rtx_SET (dst
,
9516 gen_rtx_fmt_ee (GET_CODE (src
), GET_MODE (src
),
9521 /* dwarf2out.c:dwarf2out_frame_debug_expr doesn't know
9522 what to do with COND_EXEC. */
9523 if (RTX_FRAME_RELATED_P (insn
))
9525 /* If this is the delay slot insn of an anulled branch,
9526 dwarf2out.c:scan_trace understands the anulling semantics
9527 without the COND_EXEC. */
9528 gcc_assert (annulled
);
9529 rtx note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
, pat
,
9531 validate_change (insn
, ®_NOTES (insn
), note
, 1);
9533 pat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, pat
);
9537 /* Use the ccfsm machinery to do if conversion. */
9542 struct arc_ccfsm
*statep
= &cfun
->machine
->ccfsm_current
;
9544 memset (statep
, 0, sizeof *statep
);
9545 for (rtx_insn
*insn
= get_insns (); insn
; insn
= next_insn (insn
))
9547 arc_ccfsm_advance (insn
, statep
);
9549 switch (statep
->state
)
9555 /* Deleted branch. */
9556 arc_ccfsm_post_advance (insn
, statep
);
9557 gcc_assert (!IN_RANGE (statep
->state
, 1, 2));
9558 rtx_insn
*seq
= NEXT_INSN (PREV_INSN (insn
));
9559 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
9561 rtx slot
= XVECEXP (PATTERN (seq
), 0, 1);
9562 rtx pat
= PATTERN (slot
);
9563 if (INSN_ANNULLED_BRANCH_P (insn
))
9566 = arc_get_ccfsm_cond (statep
, INSN_FROM_TARGET_P (slot
));
9567 pat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, pat
);
9569 if (!validate_change (seq
, &PATTERN (seq
), pat
, 0))
9571 PUT_CODE (slot
, NOTE
);
9572 NOTE_KIND (slot
) = NOTE_INSN_DELETED
;
9576 set_insn_deleted (insn
);
9582 && statep
->target_label
== CODE_LABEL_NUMBER (insn
))
9584 arc_ccfsm_post_advance (insn
, statep
);
9585 if (--LABEL_NUSES (insn
) == 0)
9591 if (!NONDEBUG_INSN_P (insn
))
9594 /* Conditionalized insn. */
9596 rtx_insn
*prev
, *pprev
;
9597 rtx
*patp
, pat
, cond
;
9598 bool annulled
; annulled
= false;
9600 /* If this is a delay slot insn in a non-annulled branch,
9601 don't conditionalize it. N.B., this should be fine for
9602 conditional return too. However, don't do this for
9603 unconditional branches, as these would be encountered when
9604 processing an 'else' part. */
9605 prev
= PREV_INSN (insn
);
9606 pprev
= PREV_INSN (prev
);
9607 if (pprev
&& NEXT_INSN (NEXT_INSN (pprev
)) == NEXT_INSN (insn
)
9608 && JUMP_P (prev
) && get_attr_cond (prev
) == COND_USE
)
9610 if (!INSN_ANNULLED_BRANCH_P (prev
))
9615 patp
= &PATTERN (insn
);
9617 cond
= arc_get_ccfsm_cond (statep
, INSN_FROM_TARGET_P (insn
));
9618 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
9620 /* ??? don't conditionalize if all side effects are dead
9621 in the not-execute case. */
9623 pat
= conditionalize_nonjump (pat
, cond
, insn
, annulled
);
9625 else if (simplejump_p (insn
))
9627 patp
= &SET_SRC (pat
);
9628 pat
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, *patp
, pc_rtx
);
9630 else if (JUMP_P (insn
) && ANY_RETURN_P (PATTERN (insn
)))
9632 pat
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, pat
, pc_rtx
);
9633 pat
= gen_rtx_SET (pc_rtx
, pat
);
9637 validate_change (insn
, patp
, pat
, 1);
9638 if (!apply_change_group ())
9642 rtx_insn
*next
= next_nonnote_insn (insn
);
9643 if (GET_CODE (next
) == BARRIER
)
9645 if (statep
->state
== 3)
9652 arc_ccfsm_post_advance (insn
, statep
);
9657 /* Find annulled delay insns and convert them to use the appropriate predicate.
9658 This allows branch shortening to size up these insns properly. */
9661 arc_predicate_delay_insns (void)
9663 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9665 rtx pat
, jump
, dlay
, src
, cond
, *patp
;
9668 if (!NONJUMP_INSN_P (insn
)
9669 || GET_CODE (pat
= PATTERN (insn
)) != SEQUENCE
)
9671 jump
= XVECEXP (pat
, 0, 0);
9672 dlay
= XVECEXP (pat
, 0, 1);
9673 if (!JUMP_P (jump
) || !INSN_ANNULLED_BRANCH_P (jump
))
9675 /* If the branch insn does the annulling, leave the delay insn alone. */
9676 if (!TARGET_AT_DBR_CONDEXEC
&& !INSN_FROM_TARGET_P (dlay
))
9678 /* ??? Could also leave DLAY un-conditionalized if its target is dead
9679 on the other path. */
9680 gcc_assert (GET_CODE (PATTERN (jump
)) == SET
);
9681 gcc_assert (SET_DEST (PATTERN (jump
)) == pc_rtx
);
9682 src
= SET_SRC (PATTERN (jump
));
9683 gcc_assert (GET_CODE (src
) == IF_THEN_ELSE
);
9684 cond
= XEXP (src
, 0);
9685 if (XEXP (src
, 2) == pc_rtx
)
9687 else if (XEXP (src
, 1) == pc_rtx
)
9691 if (reverse
!= !INSN_FROM_TARGET_P (dlay
))
9693 machine_mode ccm
= GET_MODE (XEXP (cond
, 0));
9694 enum rtx_code code
= reverse_condition (GET_CODE (cond
));
9695 if (code
== UNKNOWN
|| ccm
== CC_FP_GTmode
|| ccm
== CC_FP_GEmode
)
9696 code
= reverse_condition_maybe_unordered (GET_CODE (cond
));
9698 cond
= gen_rtx_fmt_ee (code
, GET_MODE (cond
),
9699 copy_rtx (XEXP (cond
, 0)),
9700 copy_rtx (XEXP (cond
, 1)));
9703 cond
= copy_rtx (cond
);
9704 patp
= &PATTERN (dlay
);
9706 pat
= conditionalize_nonjump (pat
, cond
, dlay
, true);
9707 validate_change (dlay
, patp
, pat
, 1);
9708 if (!apply_change_group ())
9714 /* For ARC600: If a write to a core reg >=32 appears in a delay slot
9715 (other than of a forward brcc), it creates a hazard when there is a read
9716 of the same register at the branch target. We can't know what is at the
9717 branch target of calls, and for branches, we don't really know before the
9718 end of delay slot scheduling, either. Not only can individual instruction
9719 be hoisted out into a delay slot, a basic block can also be emptied this
9720 way, and branch and/or fall through targets be redirected. Hence we don't
9721 want such writes in a delay slot. */
9723 /* Return nonzreo iff INSN writes to an extension core register. */
9726 arc_write_ext_corereg (rtx insn
)
9728 subrtx_iterator::array_type array
;
9729 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
9731 const_rtx x
= *iter
;
9732 switch (GET_CODE (x
))
9734 case SET
: case POST_INC
: case POST_DEC
: case PRE_INC
: case PRE_DEC
:
9737 /* This is also fine for PRE/POST_MODIFY, because they
9741 const_rtx dest
= XEXP (x
, 0);
9742 if (REG_P (dest
) && REGNO (dest
) >= 32 && REGNO (dest
) < 61)
9748 /* This is like the hook, but returns NULL when it can't / won't generate
9749 a legitimate address. */
9752 arc_legitimize_address_0 (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
9758 if (GET_CODE (addr
) == CONST
)
9759 addr
= XEXP (addr
, 0);
9761 if (GET_CODE (addr
) == PLUS
9762 && CONST_INT_P (XEXP (addr
, 1))
9763 && ((GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
9764 && !SYMBOL_REF_FUNCTION_P (XEXP (addr
, 0)))
9765 || (REG_P (XEXP (addr
, 0))
9766 && (INTVAL (XEXP (addr
, 1)) & 252))))
9768 HOST_WIDE_INT offs
, upper
;
9769 int size
= GET_MODE_SIZE (mode
);
9771 offs
= INTVAL (XEXP (addr
, 1));
9772 upper
= (offs
+ 256 * size
) & ~511 * size
;
9773 inner
= plus_constant (Pmode
, XEXP (addr
, 0), upper
);
9774 #if 0 /* ??? this produces worse code for EEMBC idctrn01 */
9775 if (GET_CODE (x
) == CONST
)
9776 inner
= gen_rtx_CONST (Pmode
, inner
);
9778 addr
= plus_constant (Pmode
, force_reg (Pmode
, inner
), offs
- upper
);
9781 else if (GET_CODE (addr
) == SYMBOL_REF
&& !SYMBOL_REF_FUNCTION_P (addr
))
9782 x
= force_reg (Pmode
, x
);
9783 if (memory_address_p ((machine_mode
) mode
, x
))
9789 arc_legitimize_address (rtx orig_x
, rtx oldx
, machine_mode mode
)
9791 rtx new_x
= arc_legitimize_address_0 (orig_x
, oldx
, mode
);
9799 arc_delegitimize_address_0 (rtx op
)
9801 switch (GET_CODE (op
))
9804 return arc_delegitimize_address_0 (XEXP (op
, 0));
9807 switch (XINT (op
, 1))
9809 case ARC_UNSPEC_GOT
:
9810 case ARC_UNSPEC_GOTOFFPC
:
9811 return XVECEXP (op
, 0, 0);
9819 rtx t1
= arc_delegitimize_address_0 (XEXP (op
, 0));
9820 rtx t2
= XEXP (op
, 1);
9823 return gen_rtx_PLUS (GET_MODE (op
), t1
, t2
);
9834 arc_delegitimize_address (rtx orig_x
)
9841 x
= arc_delegitimize_address_0 (x
);
9846 x
= replace_equiv_address_nv (orig_x
, x
);
9850 /* Return a REG rtx for acc1. N.B. the gcc-internal representation may
9851 differ from the hardware register number in order to allow the generic
9852 code to correctly split the concatenation of acc1 and acc2. */
9857 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 56: 57);
9860 /* Return a REG rtx for acc2. N.B. the gcc-internal representation may
9861 differ from the hardware register number in order to allow the generic
9862 code to correctly split the concatenation of acc1 and acc2. */
9867 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 57: 56);
9870 /* When estimating sizes during arc_reorg, when optimizing for speed, there
9871 are three reasons why we need to consider branches to be length 6:
9872 - annull-false delay slot insns are implemented using conditional execution,
9873 thus preventing short insn formation where used.
9874 - for ARC600: annul-true delay slot insns are implemented where possible
9875 using conditional execution, preventing short insn formation where used.
9876 - for ARC700: likely or somewhat likely taken branches are made long and
9877 unaligned if possible to avoid branch penalty. */
9880 arc_branch_size_unknown_p (void)
9882 return !optimize_size
&& arc_reorg_in_progress
;
9885 /* The usual; we set up our machine_function data. */
9887 static struct machine_function
*
9888 arc_init_machine_status (void)
9890 struct machine_function
*machine
;
9891 machine
= ggc_cleared_alloc
<machine_function
> ();
9892 machine
->fn_type
= ARC_FUNCTION_UNKNOWN
;
9897 /* Implements INIT_EXPANDERS. We just set up to call the above
9901 arc_init_expanders (void)
9903 init_machine_status
= arc_init_machine_status
;
9906 /* Check if OP is a proper parallel of a millicode call pattern. OFFSET
9907 indicates a number of elements to ignore - that allows to have a
9908 sibcall pattern that starts with (return). LOAD_P is zero for store
9909 multiple (for prologues), and one for load multiples (for epilogues),
9910 and two for load multiples where no final clobber of blink is required.
9911 We also skip the first load / store element since this is supposed to
9912 be checked in the instruction pattern. */
9915 arc_check_millicode (rtx op
, int offset
, int load_p
)
9917 int len
= XVECLEN (op
, 0) - offset
;
9922 if (len
< 2 || len
> 13)
9928 rtx elt
= XVECEXP (op
, 0, --len
);
9930 if (GET_CODE (elt
) != CLOBBER
9931 || !REG_P (XEXP (elt
, 0))
9932 || REGNO (XEXP (elt
, 0)) != RETURN_ADDR_REGNUM
9933 || len
< 3 || len
> 13)
9936 for (i
= 1; i
< len
; i
++)
9938 rtx elt
= XVECEXP (op
, 0, i
+ offset
);
9941 if (GET_CODE (elt
) != SET
)
9943 mem
= XEXP (elt
, load_p
);
9944 reg
= XEXP (elt
, 1-load_p
);
9945 if (!REG_P (reg
) || REGNO (reg
) != 13U+i
|| !MEM_P (mem
))
9947 addr
= XEXP (mem
, 0);
9948 if (GET_CODE (addr
) != PLUS
9949 || !rtx_equal_p (stack_pointer_rtx
, XEXP (addr
, 0))
9950 || !CONST_INT_P (XEXP (addr
, 1)) || INTVAL (XEXP (addr
, 1)) != i
*4)
9956 /* Accessor functions for cfun->machine->unalign. */
9959 arc_clear_unalign (void)
9962 cfun
->machine
->unalign
= 0;
9966 arc_toggle_unalign (void)
9968 cfun
->machine
->unalign
^= 2;
9971 /* Operands 0..2 are the operands of a addsi which uses a 12 bit
9972 constant in operand 2, but which would require a LIMM because of
9974 operands 3 and 4 are new SET_SRCs for operands 0. */
9977 split_addsi (rtx
*operands
)
9979 int val
= INTVAL (operands
[2]);
9981 /* Try for two short insns first. Lengths being equal, we prefer
9982 expansions with shorter register lifetimes. */
9983 if (val
> 127 && val
<= 255
9984 && satisfies_constraint_Rcq (operands
[0]))
9986 operands
[3] = operands
[2];
9987 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[1]);
9991 operands
[3] = operands
[1];
9992 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[2]);
9996 /* Operands 0..2 are the operands of a subsi which uses a 12 bit
9997 constant in operand 1, but which would require a LIMM because of
9999 operands 3 and 4 are new SET_SRCs for operands 0. */
10002 split_subsi (rtx
*operands
)
10004 int val
= INTVAL (operands
[1]);
10006 /* Try for two short insns first. Lengths being equal, we prefer
10007 expansions with shorter register lifetimes. */
10008 if (satisfies_constraint_Rcq (operands
[0])
10009 && satisfies_constraint_Rcq (operands
[2]))
10011 if (val
>= -31 && val
<= 127)
10013 operands
[3] = gen_rtx_NEG (SImode
, operands
[2]);
10014 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[1]);
10017 else if (val
>= 0 && val
< 255)
10019 operands
[3] = operands
[1];
10020 operands
[4] = gen_rtx_MINUS (SImode
, operands
[0], operands
[2]);
10024 /* If the destination is not an ARCompact16 register, we might
10025 still have a chance to make a short insn if the source is;
10026 we need to start with a reg-reg move for this. */
10027 operands
[3] = operands
[2];
10028 operands
[4] = gen_rtx_MINUS (SImode
, operands
[1], operands
[0]);
10031 /* Handle DOUBLE_REGS uses.
10032 Operand 0: destination register
10033 Operand 1: source register */
10036 arc_process_double_reg_moves (rtx
*operands
)
10038 enum usesDxState
{ none
, srcDx
, destDx
, maxDx
};
10039 enum usesDxState state
= none
;
10040 rtx dest
= operands
[0];
10041 rtx src
= operands
[1];
10043 if (refers_to_regno_p (40, 44, src
, 0))
10046 gcc_assert (REG_P (dest
));
10048 if (refers_to_regno_p (40, 44, dest
, 0))
10050 /* Via arc_register_move_cost, we should never see D,D moves. */
10051 gcc_assert (REG_P (src
));
10052 gcc_assert (state
== none
);
10059 if (state
== srcDx
)
10061 /* Without the LR insn, we need to split this into a
10062 sequence of insns which will use the DEXCLx and DADDHxy
10063 insns to be able to read the Dx register in question. */
10064 if (TARGET_DPFP_DISABLE_LRSR
)
10066 /* gen *movdf_insn_nolrsr */
10067 rtx set
= gen_rtx_SET (dest
, src
);
10068 rtx use1
= gen_rtx_USE (VOIDmode
, const1_rtx
);
10069 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, use1
)));
10073 /* When we have 'mov D, r' or 'mov D, D' then get the target
10074 register pair for use with LR insn. */
10075 rtx destHigh
= simplify_gen_subreg (SImode
, dest
, DFmode
,
10076 TARGET_BIG_ENDIAN
? 0 : 4);
10077 rtx destLow
= simplify_gen_subreg (SImode
, dest
, DFmode
,
10078 TARGET_BIG_ENDIAN
? 4 : 0);
10080 /* Produce the two LR insns to get the high and low parts. */
10081 emit_insn (gen_rtx_SET (destHigh
,
10082 gen_rtx_UNSPEC_VOLATILE (Pmode
,
10083 gen_rtvec (1, src
),
10084 VUNSPEC_ARC_LR_HIGH
)));
10085 emit_insn (gen_rtx_SET (destLow
,
10086 gen_rtx_UNSPEC_VOLATILE (Pmode
,
10087 gen_rtvec (1, src
),
10091 else if (state
== destDx
)
10093 /* When we have 'mov r, D' or 'mov D, D' and we have access to the
10094 LR insn get the target register pair. */
10095 rtx srcHigh
= simplify_gen_subreg (SImode
, src
, DFmode
,
10096 TARGET_BIG_ENDIAN
? 0 : 4);
10097 rtx srcLow
= simplify_gen_subreg (SImode
, src
, DFmode
,
10098 TARGET_BIG_ENDIAN
? 4 : 0);
10100 emit_insn (gen_dexcl_2op (dest
, srcHigh
, srcLow
));
10103 gcc_unreachable ();
10109 /* Check if we need to split a 64bit move. We do not need to split it if we can
10110 use vadd2 or ldd/std instructions. */
10113 arc_split_move_p (rtx
*operands
)
10115 machine_mode mode
= GET_MODE (operands
[0]);
10118 && ((memory_operand (operands
[0], mode
)
10119 && (even_register_operand (operands
[1], mode
)
10120 || satisfies_constraint_Cm3 (operands
[1])))
10121 || (memory_operand (operands
[1], mode
)
10122 && even_register_operand (operands
[0], mode
))))
10125 if (TARGET_PLUS_QMACW
10126 && even_register_operand (operands
[0], mode
)
10127 && even_register_operand (operands
[1], mode
))
10133 /* operands 0..1 are the operands of a 64 bit move instruction.
10134 split it into two moves with operands 2/3 and 4/5. */
10137 arc_split_move (rtx
*operands
)
10139 machine_mode mode
= GET_MODE (operands
[0]);
10146 if (arc_process_double_reg_moves (operands
))
10150 if (TARGET_PLUS_QMACW
10151 && GET_CODE (operands
[1]) == CONST_VECTOR
)
10153 HOST_WIDE_INT intval0
, intval1
;
10154 if (GET_MODE (operands
[1]) == V2SImode
)
10156 intval0
= INTVAL (XVECEXP (operands
[1], 0, 0));
10157 intval1
= INTVAL (XVECEXP (operands
[1], 0, 1));
10161 intval1
= INTVAL (XVECEXP (operands
[1], 0, 3)) << 16;
10162 intval1
|= INTVAL (XVECEXP (operands
[1], 0, 2)) & 0xFFFF;
10163 intval0
= INTVAL (XVECEXP (operands
[1], 0, 1)) << 16;
10164 intval0
|= INTVAL (XVECEXP (operands
[1], 0, 0)) & 0xFFFF;
10166 xop
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]));
10167 xop
[3] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
10168 xop
[2] = GEN_INT (trunc_int_for_mode (intval0
, SImode
));
10169 xop
[1] = GEN_INT (trunc_int_for_mode (intval1
, SImode
));
10170 emit_move_insn (xop
[0], xop
[2]);
10171 emit_move_insn (xop
[3], xop
[1]);
10175 for (i
= 0; i
< 2; i
++)
10177 if (MEM_P (operands
[i
]) && auto_inc_p (XEXP (operands
[i
], 0)))
10179 rtx addr
= XEXP (operands
[i
], 0);
10181 enum rtx_code code
;
10183 gcc_assert (!reg_overlap_mentioned_p (operands
[0], addr
));
10184 switch (GET_CODE (addr
))
10186 case PRE_DEC
: o
= GEN_INT (-8); goto pre_modify
;
10187 case PRE_INC
: o
= GEN_INT (8); goto pre_modify
;
10188 case PRE_MODIFY
: o
= XEXP (XEXP (addr
, 1), 1);
10192 case POST_DEC
: o
= GEN_INT (-8); goto post_modify
;
10193 case POST_INC
: o
= GEN_INT (8); goto post_modify
;
10194 case POST_MODIFY
: o
= XEXP (XEXP (addr
, 1), 1);
10196 code
= POST_MODIFY
;
10200 gcc_unreachable ();
10202 r
= XEXP (addr
, 0);
10203 xop
[0+i
] = adjust_automodify_address_nv
10204 (operands
[i
], SImode
,
10205 gen_rtx_fmt_ee (code
, Pmode
, r
,
10206 gen_rtx_PLUS (Pmode
, r
, o
)),
10208 xop
[2+i
] = adjust_automodify_address_nv
10209 (operands
[i
], SImode
, plus_constant (Pmode
, r
, 4), 4);
10213 xop
[0+i
] = operand_subword (operands
[i
], 0, 0, mode
);
10214 xop
[2+i
] = operand_subword (operands
[i
], 1, 0, mode
);
10217 if (reg_overlap_mentioned_p (xop
[0], xop
[3]))
10220 gcc_assert (!reg_overlap_mentioned_p (xop
[2], xop
[1]));
10223 emit_move_insn (xop
[0 + swap
], xop
[1 + swap
]);
10224 emit_move_insn (xop
[2 - swap
], xop
[3 - swap
]);
10228 /* Select between the instruction output templates s_tmpl (for short INSNs)
10229 and l_tmpl (for long INSNs). */
10232 arc_short_long (rtx_insn
*insn
, const char *s_tmpl
, const char *l_tmpl
)
10234 int is_short
= arc_verify_short (insn
, cfun
->machine
->unalign
, -1);
10236 extract_constrain_insn_cached (insn
);
10237 return is_short
? s_tmpl
: l_tmpl
;
10240 /* Searches X for any reference to REGNO, returning the rtx of the
10241 reference found if any. Otherwise, returns NULL_RTX. */
10244 arc_regno_use_in (unsigned int regno
, rtx x
)
10250 if (REG_P (x
) && refers_to_regno_p (regno
, x
))
10253 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10254 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
10258 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
10261 else if (fmt
[i
] == 'E')
10262 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10263 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
10270 /* Code has a minimum p2 alignment of 1, which we must restore after
10271 an ADDR_DIFF_VEC. */
10274 arc_label_align (rtx_insn
*label
)
10276 if (align_labels
.levels
[0].log
< 1)
10278 rtx_insn
*next
= next_nonnote_nondebug_insn (label
);
10279 if (INSN_P (next
) && recog_memoized (next
) >= 0)
10282 return align_labels
.levels
[0].log
;
10285 /* Return true if LABEL is in executable code. */
10288 arc_text_label (rtx_insn
*label
)
10292 /* ??? We use deleted labels like they were still there, see
10293 gcc.c-torture/compile/20000326-2.c . */
10294 gcc_assert (GET_CODE (label
) == CODE_LABEL
10295 || (GET_CODE (label
) == NOTE
10296 && NOTE_KIND (label
) == NOTE_INSN_DELETED_LABEL
));
10297 next
= next_nonnote_insn (label
);
10299 return (!JUMP_TABLE_DATA_P (next
)
10300 || GET_CODE (PATTERN (next
)) != ADDR_VEC
);
10301 else if (!PREV_INSN (label
))
10302 /* ??? sometimes text labels get inserted very late, see
10303 gcc.dg/torture/stackalign/comp-goto-1.c */
10308 /* Without this, gcc.dg/tree-prof/bb-reorg.c fails to assemble
10309 when compiling with -O2 -freorder-blocks-and-partition -fprofile-use
10310 -D_PROFILE_USE; delay branch scheduling then follows a crossing jump
10311 to redirect two breqs. */
10314 arc_can_follow_jump (const rtx_insn
*follower
, const rtx_insn
*followee
)
10316 /* ??? get_attr_type is declared to take an rtx. */
10317 union { const rtx_insn
*c
; rtx_insn
*r
; } u
;
10320 if (CROSSING_JUMP_P (followee
))
10321 switch (get_attr_type (u
.r
))
10324 if (get_attr_length (u
.r
) != 2)
10326 /* Fall through. */
10328 case TYPE_BRCC_NO_DELAY_SLOT
:
10337 /* Implement EPILOGUE_USES.
10338 Return true if REGNO should be added to the deemed uses of the epilogue.
10340 We have to make sure all the register restore instructions are
10341 known to be live in interrupt functions, plus the blink register if
10342 it is clobbered by the isr. */
10345 arc_epilogue_uses (int regno
)
10347 unsigned int fn_type
;
10348 fn_type
= arc_compute_function_type (cfun
);
10350 if (regno
== arc_tp_regno
)
10353 if (regno
== RETURN_ADDR_REGNUM
)
10356 if (regno
== arc_return_address_register (fn_type
))
10359 if (epilogue_completed
&& ARC_INTERRUPT_P (fn_type
))
10361 /* An interrupt function restores more registers. */
10362 if (df_regs_ever_live_p (regno
) || call_used_or_fixed_reg_p (regno
))
10369 /* Helper for EH_USES macro. */
10372 arc_eh_uses (int regno
)
10374 if (regno
== arc_tp_regno
)
10379 /* Return true if we use LRA instead of reload pass. */
10384 return arc_lra_flag
;
10387 /* ??? Should we define TARGET_REGISTER_PRIORITY? We might perfer to use
10388 Rcq registers, because some insn are shorter with them. OTOH we already
10389 have separate alternatives for this purpose, and other insns don't
10390 mind, so maybe we should rather prefer the other registers?
10391 We need more data, and we can only get that if we allow people to
10392 try all options. */
10394 arc_register_priority (int r
)
10396 switch (arc_lra_priority_tag
)
10398 case ARC_LRA_PRIORITY_NONE
:
10400 case ARC_LRA_PRIORITY_NONCOMPACT
:
10401 return ((((r
& 7) ^ 4) - 4) & 15) != r
;
10402 case ARC_LRA_PRIORITY_COMPACT
:
10403 return ((((r
& 7) ^ 4) - 4) & 15) == r
;
10405 gcc_unreachable ();
10410 arc_spill_class (reg_class_t
/* orig_class */, machine_mode
)
10412 return GENERAL_REGS
;
10416 arc_legitimize_reload_address (rtx
*p
, machine_mode mode
, int opnum
,
10420 enum reload_type type
= (enum reload_type
) itype
;
10422 if (GET_CODE (x
) == PLUS
10423 && CONST_INT_P (XEXP (x
, 1))
10424 && (RTX_OK_FOR_BASE_P (XEXP (x
, 0), true)
10425 || (REG_P (XEXP (x
, 0))
10426 && reg_equiv_constant (REGNO (XEXP (x
, 0))))))
10428 int scale
= GET_MODE_SIZE (mode
);
10430 rtx index_rtx
= XEXP (x
, 1);
10431 HOST_WIDE_INT offset
= INTVAL (index_rtx
), offset_base
;
10432 rtx reg
, sum
, sum2
;
10436 if ((scale
-1) & offset
)
10438 shift
= scale
>> 1;
10440 = ((offset
+ (256 << shift
))
10441 & ((HOST_WIDE_INT
)((unsigned HOST_WIDE_INT
) -512 << shift
)));
10442 /* Sometimes the normal form does not suit DImode. We
10443 could avoid that by using smaller ranges, but that
10444 would give less optimized code when SImode is
10446 if (GET_MODE_SIZE (mode
) + offset
- offset_base
<= (256 << shift
))
10451 regno
= REGNO (reg
);
10452 sum2
= sum
= plus_constant (Pmode
, reg
, offset_base
);
10454 if (reg_equiv_constant (regno
))
10456 sum2
= plus_constant (Pmode
, reg_equiv_constant (regno
),
10458 if (GET_CODE (sum2
) == PLUS
)
10459 sum2
= gen_rtx_CONST (Pmode
, sum2
);
10461 *p
= gen_rtx_PLUS (Pmode
, sum
, GEN_INT (offset
- offset_base
));
10462 push_reload (sum2
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
10463 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
,
10468 /* We must re-recognize what we created before. */
10469 else if (GET_CODE (x
) == PLUS
10470 && GET_CODE (XEXP (x
, 0)) == PLUS
10471 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
10472 && REG_P (XEXP (XEXP (x
, 0), 0))
10473 && CONST_INT_P (XEXP (x
, 1)))
10475 /* Because this address is so complex, we know it must have
10476 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
10477 it is already unshared, and needs no further unsharing. */
10478 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
10479 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10485 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
10488 arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
10489 unsigned int align
,
10490 enum by_pieces_operation op
,
10493 /* Let the cpymem expander handle small block moves. */
10494 if (op
== MOVE_BY_PIECES
)
10497 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
10500 /* Emit a (pre) memory barrier around an atomic sequence according to
10504 arc_pre_atomic_barrier (enum memmodel model
)
10506 if (need_atomic_barrier_p (model
, true))
10507 emit_insn (gen_memory_barrier ());
10510 /* Emit a (post) memory barrier around an atomic sequence according to
10514 arc_post_atomic_barrier (enum memmodel model
)
10516 if (need_atomic_barrier_p (model
, false))
10517 emit_insn (gen_memory_barrier ());
10520 /* Expand a compare and swap pattern. */
10523 emit_unlikely_jump (rtx insn
)
10525 rtx_insn
*jump
= emit_jump_insn (insn
);
10526 add_reg_br_prob_note (jump
, profile_probability::very_unlikely ());
10529 /* Expand code to perform a 8 or 16-bit compare and swap by doing
10530 32-bit compare and swap on the word containing the byte or
10531 half-word. The difference between a weak and a strong CAS is that
10532 the weak version may simply fail. The strong version relies on two
10533 loops, one checks if the SCOND op is succsfully or not, the other
10534 checks if the 32 bit accessed location which contains the 8 or 16
10535 bit datum is not changed by other thread. The first loop is
10536 implemented by the atomic_compare_and_swapsi_1 pattern. The second
10537 loops is implemented by this routine. */
10540 arc_expand_compare_and_swap_qh (rtx bool_result
, rtx result
, rtx mem
,
10541 rtx oldval
, rtx newval
, rtx weak
,
10542 rtx mod_s
, rtx mod_f
)
10544 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10545 rtx addr
= gen_reg_rtx (Pmode
);
10546 rtx off
= gen_reg_rtx (SImode
);
10547 rtx oldv
= gen_reg_rtx (SImode
);
10548 rtx newv
= gen_reg_rtx (SImode
);
10549 rtx oldvalue
= gen_reg_rtx (SImode
);
10550 rtx newvalue
= gen_reg_rtx (SImode
);
10551 rtx res
= gen_reg_rtx (SImode
);
10552 rtx resv
= gen_reg_rtx (SImode
);
10553 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
, x
;
10555 bool is_weak
= (weak
!= const0_rtx
);
10557 /* Truncate the address. */
10558 emit_insn (gen_rtx_SET (addr
,
10559 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10561 /* Compute the datum offset. */
10562 emit_insn (gen_rtx_SET (off
,
10563 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10564 if (TARGET_BIG_ENDIAN
)
10565 emit_insn (gen_rtx_SET (off
,
10566 gen_rtx_MINUS (SImode
,
10567 (GET_MODE (mem
) == QImode
) ?
10568 GEN_INT (3) : GEN_INT (2), off
)));
10570 /* Normal read from truncated address. */
10571 memsi
= gen_rtx_MEM (SImode
, addr
);
10572 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10573 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10575 val
= copy_to_reg (memsi
);
10577 /* Convert the offset in bits. */
10578 emit_insn (gen_rtx_SET (off
,
10579 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10581 /* Get the proper mask. */
10582 if (GET_MODE (mem
) == QImode
)
10583 mask
= force_reg (SImode
, GEN_INT (0xff));
10585 mask
= force_reg (SImode
, GEN_INT (0xffff));
10587 emit_insn (gen_rtx_SET (mask
,
10588 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10590 /* Prepare the old and new values. */
10591 emit_insn (gen_rtx_SET (val
,
10592 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10595 oldval
= gen_lowpart (SImode
, oldval
);
10596 emit_insn (gen_rtx_SET (oldv
,
10597 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10599 newval
= gen_lowpart_common (SImode
, newval
);
10600 emit_insn (gen_rtx_SET (newv
,
10601 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10603 emit_insn (gen_rtx_SET (oldv
,
10604 gen_rtx_AND (SImode
, oldv
, mask
)));
10606 emit_insn (gen_rtx_SET (newv
,
10607 gen_rtx_AND (SImode
, newv
, mask
)));
10611 end_label
= gen_label_rtx ();
10612 loop_label
= gen_label_rtx ();
10613 emit_label (loop_label
);
10616 /* Make the old and new values. */
10617 emit_insn (gen_rtx_SET (oldvalue
,
10618 gen_rtx_IOR (SImode
, oldv
, val
)));
10620 emit_insn (gen_rtx_SET (newvalue
,
10621 gen_rtx_IOR (SImode
, newv
, val
)));
10623 /* Try an 32bit atomic compare and swap. It clobbers the CC
10625 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
,
10626 weak
, mod_s
, mod_f
));
10628 /* Regardless of the weakness of the operation, a proper boolean
10629 result needs to be provided. */
10630 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10631 x
= gen_rtx_EQ (SImode
, x
, const0_rtx
);
10632 emit_insn (gen_rtx_SET (bool_result
, x
));
10636 /* Check the results: if the atomic op is successfully the goto
10638 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10639 x
= gen_rtx_EQ (VOIDmode
, x
, const0_rtx
);
10640 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10641 gen_rtx_LABEL_REF (Pmode
, end_label
), pc_rtx
);
10642 emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
10644 /* Wait for the right moment when the accessed 32-bit location
10646 emit_insn (gen_rtx_SET (resv
,
10647 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10649 mode
= SELECT_CC_MODE (NE
, resv
, val
);
10650 cc
= gen_rtx_REG (mode
, CC_REG
);
10651 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (mode
, resv
, val
)));
10653 /* Set the new value of the 32 bit location, proper masked. */
10654 emit_insn (gen_rtx_SET (val
, resv
));
10656 /* Try again if location is unstable. Fall through if only
10657 scond op failed. */
10658 x
= gen_rtx_NE (VOIDmode
, cc
, const0_rtx
);
10659 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10660 gen_rtx_LABEL_REF (Pmode
, loop_label
), pc_rtx
);
10661 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10663 emit_label (end_label
);
10666 /* End: proper return the result for the given mode. */
10667 emit_insn (gen_rtx_SET (res
,
10668 gen_rtx_AND (SImode
, res
, mask
)));
10670 emit_insn (gen_rtx_SET (res
,
10671 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10673 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10676 /* Helper function used by "atomic_compare_and_swap" expand
10680 arc_expand_compare_and_swap (rtx operands
[])
10682 rtx bval
, rval
, mem
, oldval
, newval
, is_weak
, mod_s
, mod_f
, x
;
10685 bval
= operands
[0];
10686 rval
= operands
[1];
10688 oldval
= operands
[3];
10689 newval
= operands
[4];
10690 is_weak
= operands
[5];
10691 mod_s
= operands
[6];
10692 mod_f
= operands
[7];
10693 mode
= GET_MODE (mem
);
10695 if (reg_overlap_mentioned_p (rval
, oldval
))
10696 oldval
= copy_to_reg (oldval
);
10698 if (mode
== SImode
)
10700 emit_insn (gen_atomic_compare_and_swapsi_1 (rval
, mem
, oldval
, newval
,
10701 is_weak
, mod_s
, mod_f
));
10702 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10703 x
= gen_rtx_EQ (SImode
, x
, const0_rtx
);
10704 emit_insn (gen_rtx_SET (bval
, x
));
10708 arc_expand_compare_and_swap_qh (bval
, rval
, mem
, oldval
, newval
,
10709 is_weak
, mod_s
, mod_f
);
10713 /* Helper function used by the "atomic_compare_and_swapsi_1"
10717 arc_split_compare_and_swap (rtx operands
[])
10719 rtx rval
, mem
, oldval
, newval
;
10721 enum memmodel mod_s
, mod_f
;
10723 rtx label1
, label2
, x
, cond
;
10725 rval
= operands
[0];
10727 oldval
= operands
[2];
10728 newval
= operands
[3];
10729 is_weak
= (operands
[4] != const0_rtx
);
10730 mod_s
= (enum memmodel
) INTVAL (operands
[5]);
10731 mod_f
= (enum memmodel
) INTVAL (operands
[6]);
10732 mode
= GET_MODE (mem
);
10734 /* ARC atomic ops work only with 32-bit aligned memories. */
10735 gcc_assert (mode
== SImode
);
10737 arc_pre_atomic_barrier (mod_s
);
10742 label1
= gen_label_rtx ();
10743 emit_label (label1
);
10745 label2
= gen_label_rtx ();
10747 /* Load exclusive. */
10748 emit_insn (gen_arc_load_exclusivesi (rval
, mem
));
10750 /* Check if it is oldval. */
10751 mode
= SELECT_CC_MODE (NE
, rval
, oldval
);
10752 cond
= gen_rtx_REG (mode
, CC_REG
);
10753 emit_insn (gen_rtx_SET (cond
, gen_rtx_COMPARE (mode
, rval
, oldval
)));
10755 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10756 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10757 gen_rtx_LABEL_REF (Pmode
, label2
), pc_rtx
);
10758 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10760 /* Exclusively store new item. Store clobbers CC reg. */
10761 emit_insn (gen_arc_store_exclusivesi (mem
, newval
));
10765 /* Check the result of the store. */
10766 cond
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10767 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10768 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10769 gen_rtx_LABEL_REF (Pmode
, label1
), pc_rtx
);
10770 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10773 if (mod_f
!= MEMMODEL_RELAXED
)
10774 emit_label (label2
);
10776 arc_post_atomic_barrier (mod_s
);
10778 if (mod_f
== MEMMODEL_RELAXED
)
10779 emit_label (label2
);
10782 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
10783 to perform. MEM is the memory on which to operate. VAL is the second
10784 operand of the binary operator. BEFORE and AFTER are optional locations to
10785 return the value of MEM either before of after the operation. MODEL_RTX
10786 is a CONST_INT containing the memory model to use. */
10789 arc_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
10790 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
10792 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
10793 machine_mode mode
= GET_MODE (mem
);
10794 rtx label
, x
, cond
;
10795 rtx before
= orig_before
, after
= orig_after
;
10797 /* ARC atomic ops work only with 32-bit aligned memories. */
10798 gcc_assert (mode
== SImode
);
10800 arc_pre_atomic_barrier (model
);
10802 label
= gen_label_rtx ();
10803 emit_label (label
);
10804 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
10806 if (before
== NULL_RTX
)
10807 before
= gen_reg_rtx (mode
);
10809 if (after
== NULL_RTX
)
10810 after
= gen_reg_rtx (mode
);
10812 /* Load exclusive. */
10813 emit_insn (gen_arc_load_exclusivesi (before
, mem
));
10818 x
= gen_rtx_AND (mode
, before
, val
);
10819 emit_insn (gen_rtx_SET (after
, x
));
10820 x
= gen_rtx_NOT (mode
, after
);
10821 emit_insn (gen_rtx_SET (after
, x
));
10825 if (CONST_INT_P (val
))
10827 val
= GEN_INT (-INTVAL (val
));
10833 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
10834 emit_insn (gen_rtx_SET (after
, x
));
10838 /* Exclusively store new item. Store clobbers CC reg. */
10839 emit_insn (gen_arc_store_exclusivesi (mem
, after
));
10841 /* Check the result of the store. */
10842 cond
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10843 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10844 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10846 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10848 arc_post_atomic_barrier (model
);
10851 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
10854 arc_no_speculation_in_delay_slots_p ()
10859 /* Return a parallel of registers to represent where to find the
10860 register pieces if required, otherwise NULL_RTX. */
10863 arc_dwarf_register_span (rtx rtl
)
10865 machine_mode mode
= GET_MODE (rtl
);
10869 if (GET_MODE_SIZE (mode
) != 8)
10872 p
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
10873 regno
= REGNO (rtl
);
10874 XVECEXP (p
, 0, 0) = gen_rtx_REG (SImode
, regno
);
10875 XVECEXP (p
, 0, 1) = gen_rtx_REG (SImode
, regno
+ 1);
10880 /* Return true if OP is an acceptable memory operand for ARCompact
10881 16-bit load instructions of MODE.
10883 AV2SHORT: TRUE if address needs to fit into the new ARCv2 short
10884 non scaled instructions.
10886 SCALED: TRUE if address can be scaled. */
10889 compact_memory_operand_p (rtx op
, machine_mode mode
,
10890 bool av2short
, bool scaled
)
10892 rtx addr
, plus0
, plus1
;
10895 /* Eliminate non-memory operations. */
10896 if (GET_CODE (op
) != MEM
)
10899 /* .di instructions have no 16-bit form. */
10900 if (MEM_VOLATILE_P (op
) && !TARGET_VOLATILE_CACHE_SET
)
10903 /* likewise for uncached types. */
10904 if (arc_is_uncached_mem_p (op
))
10907 if (mode
== VOIDmode
)
10908 mode
= GET_MODE (op
);
10910 size
= GET_MODE_SIZE (mode
);
10912 /* dword operations really put out 2 instructions, so eliminate
10914 if (size
> UNITS_PER_WORD
)
10917 /* Decode the address now. */
10918 addr
= XEXP (op
, 0);
10919 switch (GET_CODE (addr
))
10922 return (REGNO (addr
) >= FIRST_PSEUDO_REGISTER
10923 || COMPACT_GP_REG_P (REGNO (addr
))
10924 || (SP_REG_P (REGNO (addr
)) && (size
!= 2)));
10926 plus0
= XEXP (addr
, 0);
10927 plus1
= XEXP (addr
, 1);
10929 if ((GET_CODE (plus0
) == REG
)
10930 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10931 || COMPACT_GP_REG_P (REGNO (plus0
)))
10932 && ((GET_CODE (plus1
) == REG
)
10933 && ((REGNO (plus1
) >= FIRST_PSEUDO_REGISTER
)
10934 || COMPACT_GP_REG_P (REGNO (plus1
)))))
10939 if ((GET_CODE (plus0
) == REG
)
10940 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10941 || (COMPACT_GP_REG_P (REGNO (plus0
)) && !av2short
)
10942 || (IN_RANGE (REGNO (plus0
), 0, 31) && av2short
))
10943 && (GET_CODE (plus1
) == CONST_INT
))
10945 bool valid
= false;
10947 off
= INTVAL (plus1
);
10949 /* Negative offset is not supported in 16-bit load/store insns. */
10953 /* Only u5 immediates allowed in code density instructions. */
10961 /* This is an ldh_s.x instruction, check the u6
10963 if (COMPACT_GP_REG_P (REGNO (plus0
)))
10967 /* Only u5 immediates allowed in 32bit access code
10968 density instructions. */
10969 if (REGNO (plus0
) <= 31)
10970 return ((off
< 32) && (off
% 4 == 0));
10977 if (COMPACT_GP_REG_P (REGNO (plus0
)))
10988 /* The 6-bit constant get shifted to fit the real
10989 5-bits field. Check also for the alignment. */
10990 return ((off
< 64) && (off
% 2 == 0));
10992 return ((off
< 128) && (off
% 4 == 0));
10999 if (REG_P (plus0
) && CONST_INT_P (plus1
)
11000 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
11001 || SP_REG_P (REGNO (plus0
)))
11004 off
= INTVAL (plus1
);
11005 return ((size
!= 2) && (off
>= 0 && off
< 128) && (off
% 4 == 0));
11008 if ((GET_CODE (plus0
) == MULT
)
11009 && (GET_CODE (XEXP (plus0
, 0)) == REG
)
11010 && ((REGNO (XEXP (plus0
, 0)) >= FIRST_PSEUDO_REGISTER
)
11011 || COMPACT_GP_REG_P (REGNO (XEXP (plus0
, 0))))
11012 && (GET_CODE (plus1
) == REG
)
11013 && ((REGNO (plus1
) >= FIRST_PSEUDO_REGISTER
)
11014 || COMPACT_GP_REG_P (REGNO (plus1
))))
11018 /* TODO: 'gp' and 'pcl' are to supported as base address operand
11019 for 16-bit load instructions. */
11024 /* Return nonzero if a jli call should be generated for a call from
11025 the current function to DECL. */
11028 arc_is_jli_call_p (rtx pat
)
11031 tree decl
= SYMBOL_REF_DECL (pat
);
11033 /* If it is not a well defined public function then return false. */
11034 if (!decl
|| !SYMBOL_REF_FUNCTION_P (pat
) || !TREE_PUBLIC (decl
))
11037 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
11038 if (lookup_attribute ("jli_always", attrs
))
11041 if (lookup_attribute ("jli_fixed", attrs
))
11044 return TARGET_JLI_ALWAYS
;
11047 /* Handle and "jli" attribute; arguments as in struct
11048 attribute_spec.handler. */
11051 arc_handle_jli_attribute (tree
*node ATTRIBUTE_UNUSED
,
11052 tree name
, tree args
, int,
11053 bool *no_add_attrs
)
11057 warning (OPT_Wattributes
,
11058 "%qE attribute only valid for ARCv2 architecture",
11060 *no_add_attrs
= true;
11063 if (args
== NULL_TREE
)
11065 warning (OPT_Wattributes
,
11066 "argument of %qE attribute is missing",
11068 *no_add_attrs
= true;
11072 if (TREE_CODE (TREE_VALUE (args
)) == NON_LVALUE_EXPR
)
11073 TREE_VALUE (args
) = TREE_OPERAND (TREE_VALUE (args
), 0);
11074 tree arg
= TREE_VALUE (args
);
11075 if (TREE_CODE (arg
) != INTEGER_CST
)
11077 warning (0, "%qE attribute allows only an integer constant argument",
11079 *no_add_attrs
= true;
11081 /* FIXME! add range check. TREE_INT_CST_LOW (arg) */
11086 /* Handle and "scure" attribute; arguments as in struct
11087 attribute_spec.handler. */
11090 arc_handle_secure_attribute (tree
*node ATTRIBUTE_UNUSED
,
11091 tree name
, tree args
, int,
11092 bool *no_add_attrs
)
11096 warning (OPT_Wattributes
,
11097 "%qE attribute only valid for ARC EM architecture",
11099 *no_add_attrs
= true;
11102 if (args
== NULL_TREE
)
11104 warning (OPT_Wattributes
,
11105 "argument of %qE attribute is missing",
11107 *no_add_attrs
= true;
11111 if (TREE_CODE (TREE_VALUE (args
)) == NON_LVALUE_EXPR
)
11112 TREE_VALUE (args
) = TREE_OPERAND (TREE_VALUE (args
), 0);
11113 tree arg
= TREE_VALUE (args
);
11114 if (TREE_CODE (arg
) != INTEGER_CST
)
11116 warning (0, "%qE attribute allows only an integer constant argument",
11118 *no_add_attrs
= true;
11124 /* Return nonzero if the symbol is a secure function. */
11127 arc_is_secure_call_p (rtx pat
)
11130 tree decl
= SYMBOL_REF_DECL (pat
);
11135 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
11136 if (lookup_attribute ("secure_call", attrs
))
11142 /* Handle "uncached" qualifier. */
11145 arc_handle_uncached_attribute (tree
*node
,
11146 tree name
, tree args
,
11147 int flags ATTRIBUTE_UNUSED
,
11148 bool *no_add_attrs
)
11150 if (DECL_P (*node
) && TREE_CODE (*node
) != TYPE_DECL
)
11152 error ("%qE attribute only applies to types",
11154 *no_add_attrs
= true;
11158 warning (OPT_Wattributes
, "argument of %qE attribute ignored", name
);
11163 /* Return TRUE if PAT is a memory addressing an uncached data. */
11166 arc_is_uncached_mem_p (rtx pat
)
11168 tree attrs
= NULL_TREE
;
11174 /* Get the memory attributes. */
11175 addr
= MEM_EXPR (pat
);
11179 /* Get the attributes. */
11180 if (TREE_CODE (addr
) == MEM_REF
11181 || TREE_CODE (addr
) == VAR_DECL
)
11183 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (addr
));
11184 if (lookup_attribute ("uncached", attrs
))
11187 if (TREE_CODE (addr
) == MEM_REF
)
11189 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr
, 0)));
11190 if (lookup_attribute ("uncached", attrs
))
11192 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr
, 1)));
11193 if (lookup_attribute ("uncached", attrs
))
11197 /* Check the definitions of the structs. */
11198 while (handled_component_p (addr
))
11200 if (TREE_CODE (addr
) == COMPONENT_REF
)
11202 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (addr
));
11203 if (lookup_attribute ("uncached", attrs
))
11205 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr
, 0)));
11206 if (lookup_attribute ("uncached", attrs
))
11208 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr
, 1)));
11209 if (lookup_attribute ("uncached", attrs
))
11212 addr
= TREE_OPERAND (addr
, 0);
11217 /* Handle aux attribute. The auxiliary registers are addressed using
11218 special instructions lr and sr. The attribute 'aux' indicates if a
11219 variable refers to the aux-regs and what is the register number
11223 arc_handle_aux_attribute (tree
*node
,
11224 tree name
, tree args
, int,
11225 bool *no_add_attrs
)
11227 /* Isn't it better to use address spaces for the aux-regs? */
11228 if (DECL_P (*node
))
11230 if (TREE_CODE (*node
) != VAR_DECL
)
11232 error ("%qE attribute only applies to variables", name
);
11233 *no_add_attrs
= true;
11237 if (TREE_CODE (TREE_VALUE (args
)) == NON_LVALUE_EXPR
)
11238 TREE_VALUE (args
) = TREE_OPERAND (TREE_VALUE (args
), 0);
11239 tree arg
= TREE_VALUE (args
);
11240 if (TREE_CODE (arg
) != INTEGER_CST
)
11242 warning (OPT_Wattributes
, "%qE attribute allows only an integer "
11243 "constant argument", name
);
11244 *no_add_attrs
= true;
11246 /* FIXME! add range check. TREE_INT_CST_LOW (arg) */
11249 if (TREE_CODE (*node
) == VAR_DECL
)
11251 tree fntype
= TREE_TYPE (*node
);
11252 if (fntype
&& TREE_CODE (fntype
) == POINTER_TYPE
)
11254 tree attrs
= tree_cons (get_identifier ("aux"), NULL_TREE
,
11255 TYPE_ATTRIBUTES (fntype
));
11256 TYPE_ATTRIBUTES (fntype
) = attrs
;
11263 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
11264 anchors for small data: the GP register acts as an anchor in that
11265 case. We also don't want to use them for PC-relative accesses,
11266 where the PC acts as an anchor. Prohibit also TLS symbols to use
11270 arc_use_anchors_for_symbol_p (const_rtx symbol
)
11272 if (SYMBOL_REF_TLS_MODEL (symbol
))
11278 if (SYMBOL_REF_SMALL_P (symbol
))
11281 return default_use_anchors_for_symbol_p (symbol
);
11284 /* Return true if SUBST can't safely replace its equivalent during RA. */
11286 arc_cannot_substitute_mem_equiv_p (rtx
)
11288 /* If SUBST is mem[base+index], the address may not fit ISA,
11289 thus return true. */
11293 /* Checks whether the operands are valid for use in an LDD/STD
11294 instruction. Assumes that RT, and RT2 are REG. This is guaranteed
11295 by the patterns. Assumes that the address in the base register RN
11296 is word aligned. Pattern guarantees that both memory accesses use
11297 the same base register, the offsets are constants within the range,
11298 and the gap between the offsets is 4. If reload complete then
11299 check that registers are legal. */
11302 operands_ok_ldd_std (rtx rt
, rtx rt2
, HOST_WIDE_INT offset
)
11304 unsigned int t
, t2
;
11306 if (!reload_completed
)
11309 if (!(SMALL_INT_RANGE (offset
, (GET_MODE_SIZE (DImode
) - 1) & (~0x03),
11310 (offset
& (GET_MODE_SIZE (DImode
) - 1) & 3
11311 ? 0 : -(-GET_MODE_SIZE (DImode
) | (~0x03)) >> 1))))
11317 if ((t2
== PCL_REG
)
11318 || (t
% 2 != 0) /* First destination register is not even. */
11325 /* Helper for gen_operands_ldd_std. Returns true iff the memory
11326 operand MEM's address contains an immediate offset from the base
11327 register and has no side effects, in which case it sets BASE and
11328 OFFSET accordingly. */
11331 mem_ok_for_ldd_std (rtx mem
, rtx
*base
, rtx
*offset
)
11335 gcc_assert (base
!= NULL
&& offset
!= NULL
);
11337 /* TODO: Handle more general memory operand patterns, such as
11338 PRE_DEC and PRE_INC. */
11340 if (side_effects_p (mem
))
11343 /* Can't deal with subregs. */
11344 if (GET_CODE (mem
) == SUBREG
)
11347 gcc_assert (MEM_P (mem
));
11349 *offset
= const0_rtx
;
11351 addr
= XEXP (mem
, 0);
11353 /* If addr isn't valid for DImode, then we can't handle it. */
11354 if (!arc_legitimate_address_p (DImode
, addr
,
11355 reload_in_progress
|| reload_completed
))
11363 else if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == MINUS
)
11365 *base
= XEXP (addr
, 0);
11366 *offset
= XEXP (addr
, 1);
11367 return (REG_P (*base
) && CONST_INT_P (*offset
));
11373 /* Called from peephole2 to replace two word-size accesses with a
11374 single LDD/STD instruction. Returns true iff we can generate a new
11375 instruction sequence. That is, both accesses use the same base
11376 register and the gap between constant offsets is 4. OPERANDS are
11377 the operands found by the peephole matcher; OPERANDS[0,1] are
11378 register operands, and OPERANDS[2,3] are the corresponding memory
11379 operands. LOAD indicates whether the access is load or store. */
11382 gen_operands_ldd_std (rtx
*operands
, bool load
, bool commute
)
11385 HOST_WIDE_INT offsets
[2], offset
;
11387 rtx cur_base
, cur_offset
, tmp
;
11388 rtx base
= NULL_RTX
;
11390 /* Check that the memory references are immediate offsets from the
11391 same base register. Extract the base register, the destination
11392 registers, and the corresponding memory offsets. */
11393 for (i
= 0; i
< nops
; i
++)
11395 if (!mem_ok_for_ldd_std (operands
[nops
+i
], &cur_base
, &cur_offset
))
11400 else if (REGNO (base
) != REGNO (cur_base
))
11403 offsets
[i
] = INTVAL (cur_offset
);
11404 if (GET_CODE (operands
[i
]) == SUBREG
)
11406 tmp
= SUBREG_REG (operands
[i
]);
11407 gcc_assert (GET_MODE (operands
[i
]) == GET_MODE (tmp
));
11412 /* Make sure there is no dependency between the individual loads. */
11413 if (load
&& REGNO (operands
[0]) == REGNO (base
))
11414 return false; /* RAW. */
11416 if (load
&& REGNO (operands
[0]) == REGNO (operands
[1]))
11417 return false; /* WAW. */
11419 /* Make sure the instructions are ordered with lower memory access first. */
11420 if (offsets
[0] > offsets
[1])
11422 gap
= offsets
[0] - offsets
[1];
11423 offset
= offsets
[1];
11425 /* Swap the instructions such that lower memory is accessed first. */
11426 std::swap (operands
[0], operands
[1]);
11427 std::swap (operands
[2], operands
[3]);
11431 gap
= offsets
[1] - offsets
[0];
11432 offset
= offsets
[0];
11435 /* Make sure accesses are to consecutive memory locations. */
11439 /* Make sure we generate legal instructions. */
11440 if (operands_ok_ldd_std (operands
[0], operands
[1], offset
))
11443 if (load
&& commute
)
11445 /* Try reordering registers. */
11446 std::swap (operands
[0], operands
[1]);
11447 if (operands_ok_ldd_std (operands
[0], operands
[1], offset
))
11454 /* This order of allocation is used when we compile for size. It
11455 allocates first the registers which are most probably to end up in
11456 a short instruction. */
11457 static const int size_alloc_order
[] =
11459 0, 1, 2, 3, 12, 13, 14, 15,
11460 4, 5, 6, 7, 8, 9, 10, 11
11463 /* Adjust register allocation order when compiling for size. */
11465 arc_adjust_reg_alloc_order (void)
11467 const int arc_default_alloc_order
[] = REG_ALLOC_ORDER
;
11468 memcpy (reg_alloc_order
, arc_default_alloc_order
, sizeof (reg_alloc_order
));
11470 memcpy (reg_alloc_order
, size_alloc_order
, sizeof (size_alloc_order
));
11473 /* Implement TARGET_MEMORY_MOVE_COST. */
11476 arc_memory_move_cost (machine_mode mode
,
11477 reg_class_t rclass ATTRIBUTE_UNUSED
,
11478 bool in ATTRIBUTE_UNUSED
)
11480 if ((GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
11481 || ((GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
* 2) && TARGET_LL64
))
11484 return (2 * GET_MODE_SIZE (mode
));
11487 /* Split an OR instruction into multiple BSET/OR instructions in a
11488 attempt to avoid long immediate constants. The next strategies are
11489 employed when destination is 'q' reg.
11491 1. if there are up to three bits set in the mask, a succession of
11492 three bset instruction will be emitted:
11494 BSET(_S) rA,rB,mask1/BSET_S rA,rA,mask2/BSET_S rA,rA,mask3
11496 2. if the lower 6 bits of the mask is set and there is only one
11497 bit set in the upper remaining bits then we will emit one bset and
11498 one OR instruction:
11499 OR rA, rB, mask -> OR rA,rB,mask1/BSET_S rA,mask2
11501 3. otherwise an OR with limm will be emmitted. */
11504 arc_split_ior (rtx
*operands
)
11506 unsigned HOST_WIDE_INT mask
, maskx
;
11507 rtx op1
= operands
[1];
11509 gcc_assert (CONST_INT_P (operands
[2]));
11510 mask
= INTVAL (operands
[2]) & 0xffffffff;
11512 if (__builtin_popcount (mask
) > 3 || (mask
& 0x3f))
11514 maskx
= mask
& 0x3f;
11515 emit_insn (gen_rtx_SET (operands
[0],
11516 gen_rtx_IOR (SImode
, op1
, GEN_INT (maskx
))));
11521 switch (__builtin_popcount (mask
))
11524 maskx
= 1 << (__builtin_ffs (mask
) - 1);
11525 emit_insn (gen_rtx_SET (operands
[0],
11526 gen_rtx_IOR (SImode
, op1
, GEN_INT (maskx
))));
11531 maskx
= 1 << (__builtin_ffs (mask
) - 1);
11532 emit_insn (gen_rtx_SET (operands
[0],
11533 gen_rtx_IOR (SImode
, op1
, GEN_INT (maskx
))));
11538 maskx
= 1 << (__builtin_ffs (mask
) - 1);
11539 emit_insn (gen_rtx_SET (operands
[0],
11540 gen_rtx_IOR (SImode
, op1
, GEN_INT (maskx
))));
11545 gcc_unreachable ();
11549 /* Helper to check C0x constraint. */
11552 arc_check_ior_const (HOST_WIDE_INT ival
)
11554 unsigned int mask
= (unsigned int) (ival
& 0xffffffff);
11556 if (UNSIGNED_INT6 (ival
)
11557 || IS_POWEROF2_P (mask
))
11559 if (__builtin_popcount (mask
) <= 3)
11561 if (__builtin_popcount (mask
& ~0x3f) <= 1)
11566 /* Split a mov with long immediate instruction into smaller, size
11567 friendly instructions. */
11570 arc_split_mov_const (rtx
*operands
)
11572 unsigned HOST_WIDE_INT ival
;
11573 HOST_WIDE_INT shimm
;
11574 machine_mode mode
= GET_MODE (operands
[0]);
11576 /* Manage a constant. */
11577 gcc_assert (CONST_INT_P (operands
[1]));
11578 ival
= INTVAL (operands
[1]) & 0xffffffff;
11580 /* 1. Check if we can just rotate limm by 8 but using ROR8. */
11581 if (TARGET_BARREL_SHIFTER
&& TARGET_V2
11582 && ((ival
& ~0x3f000000) == 0))
11584 shimm
= (ival
>> 24) & 0x3f;
11585 emit_insn (gen_rtx_SET (operands
[0],
11586 gen_rtx_ROTATERT (mode
, GEN_INT (shimm
),
11590 /* 2. Check if we can just shift by 8 to fit into the u6 of LSL8. */
11591 if (TARGET_BARREL_SHIFTER
&& TARGET_V2
11592 && ((ival
& ~0x3f00) == 0))
11594 shimm
= (ival
>> 8) & 0x3f;
11595 emit_insn (gen_rtx_SET (operands
[0],
11596 gen_rtx_ASHIFT (mode
, GEN_INT (shimm
),
11601 /* 3. Check if we can just shift by 16 to fit into the u6 of LSL16. */
11602 if (TARGET_BARREL_SHIFTER
&& TARGET_V2
11603 && ((ival
& ~0x3f0000) == 0))
11605 shimm
= (ival
>> 16) & 0x3f;
11606 emit_insn (gen_rtx_SET (operands
[0],
11607 gen_rtx_ASHIFT (mode
, GEN_INT (shimm
),
11612 /* 4. Check if we can do something like mov_s h,u8 / asl_s ra,h,#nb. */
11613 if (((ival
>> (__builtin_ffs (ival
) - 1)) & 0xffffff00) == 0
11614 && TARGET_BARREL_SHIFTER
)
11616 HOST_WIDE_INT shift
= __builtin_ffs (ival
);
11617 shimm
= (ival
>> (shift
- 1)) & 0xff;
11618 emit_insn (gen_rtx_SET (operands
[0], GEN_INT (shimm
)));
11619 emit_insn (gen_rtx_SET (operands
[0],
11620 gen_rtx_ASHIFT (mode
, operands
[0],
11621 GEN_INT (shift
- 1))));
11625 /* 5. Check if we can just rotate the limm, useful when no barrel
11626 shifter is present. */
11627 if ((ival
& ~0x8000001f) == 0)
11629 shimm
= (ival
* 2 + 1) & 0x3f;
11630 emit_insn (gen_rtx_SET (operands
[0],
11631 gen_rtx_ROTATERT (mode
, GEN_INT (shimm
),
11636 /* 6. Check if we can do something with bmask. */
11637 if (IS_POWEROF2_P (ival
+ 1))
11639 emit_insn (gen_rtx_SET (operands
[0], constm1_rtx
));
11640 emit_insn (gen_rtx_SET (operands
[0],
11641 gen_rtx_AND (mode
, operands
[0],
11646 gcc_unreachable ();
11649 /* Helper to check Cax constraint. */
11652 arc_check_mov_const (HOST_WIDE_INT ival
)
11654 ival
= ival
& 0xffffffff;
11656 if (SIGNED_INT12 (ival
))
11659 if ((ival
& ~0x8000001f) == 0)
11662 if (IS_POWEROF2_P (ival
+ 1))
11665 /* The next rules requires a barrel shifter. */
11666 if (!TARGET_BARREL_SHIFTER
)
11669 if (((ival
>> (__builtin_ffs (ival
) - 1)) & 0xffffff00) == 0)
11672 if ((ival
& ~0x3f00) == 0)
11675 if ((ival
& ~0x3f0000) == 0)
11678 if ((ival
& ~0x3f000000) == 0)
11684 /* Return nonzero if this function is known to have a null epilogue.
11685 This allows the optimizer to omit jumps to jumps if no stack
11689 arc_can_use_return_insn (void)
11691 return (reload_completed
&& cfun
->machine
->frame_info
.total_size
== 0
11692 && !ARC_INTERRUPT_P (arc_compute_function_type (cfun
)));
11695 /* Helper for INSN_COST.
11697 Per Segher Boessenkool: rtx_costs computes the cost for any rtx (an
11698 insn, a set, a set source, any random piece of one). set_src_cost,
11699 set_rtx_cost, etc. are helper functions that use that.
11701 Those functions do not work for parallels. Also, costs are not
11702 additive like this simplified model assumes. Also, more complex
11703 backends tend to miss many cases in their rtx_costs function.
11705 Many passes that want costs want to know the cost of a full insn. Like
11706 combine. That's why I created insn_cost: it solves all of the above
11710 arc_insn_cost (rtx_insn
*insn
, bool speed
)
11713 if (recog_memoized (insn
) < 0)
11716 /* If optimizing for size, we want the insn size. */
11718 return get_attr_length (insn
);
11720 /* Use cost if provided. */
11721 cost
= get_attr_cost (insn
);
11725 /* For speed make a simple cost model: memory access is more
11726 expensive than any other instruction. */
11727 enum attr_type type
= get_attr_type (insn
);
11733 cost
= COSTS_N_INSNS (2);
11737 cost
= COSTS_N_INSNS (1);
11744 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
11745 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
11747 #undef TARGET_CONSTANT_ALIGNMENT
11748 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
11750 #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P
11751 #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P arc_cannot_substitute_mem_equiv_p
11753 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11754 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arc_asm_trampoline_template
11756 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
11757 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
11759 #undef TARGET_REGISTER_MOVE_COST
11760 #define TARGET_REGISTER_MOVE_COST arc_register_move_cost
11762 #undef TARGET_MEMORY_MOVE_COST
11763 #define TARGET_MEMORY_MOVE_COST arc_memory_move_cost
11765 #undef TARGET_INSN_COST
11766 #define TARGET_INSN_COST arc_insn_cost
11768 struct gcc_target targetm
= TARGET_INITIALIZER
;
11770 #include "gt-arc.h"