gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2020 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target Report RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target Report RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target Report
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target Report
  42 Same as -mA6.
  43
  44 mARC601
  45 Target Report
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target Report
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target Report
  54 Same as -mA7.
  55
  56 mjli-always
  57 Target Report Mask(JLI_ALWAYS)
  58 Force all calls to be made via a jli instruction.
  59
  60 mmpy-option=
  61 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
  62 -mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
  63
  64 Enum
  65 Name(arc_mpy) Type(int)
  66
  67 EnumValue
  68 Enum(arc_mpy) String(0) Value(0)
  69
  70 EnumValue
  71 Enum(arc_mpy) String(none) Value(0) Canonical
  72
  73 EnumValue
  74 Enum(arc_mpy) String(1) Value(1)
  75
  76 EnumValue
  77 Enum(arc_mpy) String(w) Value(1) Canonical
  78
  79 EnumValue
  80 Enum(arc_mpy) String(2) Value(2)
  81
  82 EnumValue
  83 Enum(arc_mpy) String(mpy) Value(2)
  84
  85 EnumValue
  86 Enum(arc_mpy) String(wlh1) Value(2) Canonical
  87
  88 EnumValue
  89 Enum(arc_mpy) String(3) Value(3)
  90
  91 EnumValue
  92 Enum(arc_mpy) String(wlh2) Value(3) Canonical
  93
  94 EnumValue
  95 Enum(arc_mpy) String(4) Value(4)
  96
  97 EnumValue
  98 Enum(arc_mpy) String(wlh3) Value(4) Canonical
  99
 100 EnumValue
 101 Enum(arc_mpy) String(5) Value(5)
 102
 103 EnumValue
 104 Enum(arc_mpy) String(wlh4) Value(5) Canonical
 105
 106 EnumValue
 107 Enum(arc_mpy) String(6) Value(6)
 108
 109 EnumValue
 110 Enum(arc_mpy) String(wlh5) Value(6) Canonical
 111
 112 EnumValue
 113 Enum(arc_mpy) String(7) Value(7)
 114
 115 EnumValue
 116 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
 117
 118 EnumValue
 119 Enum(arc_mpy) String(8) Value(8)
 120
 121 EnumValue
 122 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
 123
 124 EnumValue
 125 Enum(arc_mpy) String(9) Value(9)
 126
 127 EnumValue
 128 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
 129
 130 mdiv-rem
 131 Target Report Mask(DIVREM)
 132 Enable DIV-REM instructions for ARCv2.
 133
 134 mcode-density
 135 Target Report Mask(CODE_DENSITY)
 136 Enable code density instructions for ARCv2.
 137
 138 mmixed-code
 139 Target Report Mask(MIXED_CODE_SET)
 140 Tweak register allocation to help 16-bit instruction generation.
 141 ; originally this was:
 142 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
 143 ; but we do that without -mmixed-code, too, it's just a different instruction
 144 ; count / size tradeoff.
 145
 146 ; We use an explict definition for the negative form because that is the
 147 ; actually interesting option, and we want that to have its own comment.
 148 mvolatile-cache
 149 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
 150 Use ordinarily cached memory accesses for volatile references.
 151
 152 mno-volatile-cache
 153 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
 154 Enable cache bypass for volatile references.
 155
 156 mbarrel-shifter
 157 Target Report Mask(BARREL_SHIFTER)
 158 Generate instructions supported by barrel shifter.
 159
 160 mnorm
 161 Target Report Mask(NORM_SET)
 162 Generate norm instruction.
 163
 164 mswap
 165 Target Report Mask(SWAP_SET)
 166 Generate swap instruction.
 167
 168 mmul64
 169 Target Report Mask(MUL64_SET)
 170 Generate mul64 and mulu64 instructions.
 171
 172 mno-mpy
 173 Target Report Mask(NOMPY_SET) Warn(%qs is deprecated)
 174 Do not generate mpy instructions for ARC700.
 175
 176 mea
 177 Target Report Mask(EA_SET)
 178 Generate extended arithmetic instructions, only valid for ARC700.
 179
 180 msoft-float
 181 Target Report Mask(0)
 182 Dummy flag. This is the default unless FPX switches are provided explicitly.
 183
 184 mlong-calls
 185 Target Report Mask(LONG_CALLS_SET)
 186 Generate call insns as register indirect calls.
 187
 188 mno-brcc
 189 Target Report Mask(NO_BRCC_SET)
 190 Do no generate BRcc instructions in arc_reorg.
 191
 192 msdata
 193 Target Report InverseMask(NO_SDATA_SET)
 194 Generate sdata references.  This is the default, unless you compile for PIC.
 195
 196 mmillicode
 197 Target Report Mask(MILLICODE_THUNK_SET)
 198 Generate millicode thunks.
 199
 200 mspfp
 201 Target Report Mask(SPFP_COMPACT_SET)
 202 FPX: Generate Single Precision FPX (compact) instructions.
 203
 204 mspfp-compact
 205 Target Report Mask(SPFP_COMPACT_SET) MaskExists
 206 FPX: Generate Single Precision FPX (compact) instructions.
 207
 208 mspfp-fast
 209 Target Report Mask(SPFP_FAST_SET)
 210 FPX: Generate Single Precision FPX (fast) instructions.
 211
 212 margonaut
 213 Target Report Mask(ARGONAUT_SET)
 214 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 215
 216 mdpfp
 217 Target Report Mask(DPFP_COMPACT_SET)
 218 FPX: Generate Double Precision FPX (compact) instructions.
 219
 220 mdpfp-compact
 221 Target Report Mask(DPFP_COMPACT_SET) MaskExists
 222 FPX: Generate Double Precision FPX (compact) instructions.
 223
 224 mdpfp-fast
 225 Target Report Mask(DPFP_FAST_SET)
 226 FPX: Generate Double Precision FPX (fast) instructions.
 227
 228 mno-dpfp-lrsr
 229 Target Report Mask(DPFP_DISABLE_LRSR)
 230 Disable LR and SR instructions from using FPX extension aux registers.
 231
 232 msimd
 233 Target Report Mask(SIMD_SET)
 234 Enable generation of ARC SIMD instructions via target-specific builtins.
 235
 236 mcpu=
 237 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 238 -mcpu=CPU       Compile code for ARC variant CPU.
 239
 240 msize-level=
 241 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 242 Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 243
 244 misize
 245 Target Report PchIgnore Var(TARGET_DUMPISIZE)
 246 Annotate assembler instructions with estimated addresses.
 247
 248 mmultcost=
 249 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 250 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 251
 252 mtune=
 253 Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE)
 254 -mcpu=TUNE Tune code for given ARC variant.
 255
 256 Enum
 257 Name(arc_tune_attr) Type(int)
 258
 259 EnumValue
 260 Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600)
 261
 262 EnumValue
 263 Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600)
 264
 265 EnumValue
 266 Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX)
 267
 268 EnumValue
 269 Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD)
 270
 271 EnumValue
 272 Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC)
 273
 274 EnumValue
 275 Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC)
 276
 277 EnumValue
 278 Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC)
 279
 280 EnumValue
 281 Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3)
 282
 283 mindexed-loads
 284 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
 285 Enable the use of indexed loads.
 286
 287 mauto-modify-reg
 288 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
 289 Enable the use of pre/post modify with register displacement.
 290
 291 mmul32x16
 292 Target Report Mask(MULMAC_32BY16_SET)
 293 Generate 32x16 multiply and mac instructions.
 294
 295 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
 296 ; alas, basic-block.h is not included in options.c .
 297 munalign-prob-threshold=
 298 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
 299 Set probability threshold for unaligning branches.
 300
 301 mmedium-calls
 302 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 303 Don't use less than 25 bit addressing range for calls.
 304
 305 mannotate-align
 306 Target Var(TARGET_ANNOTATE_ALIGN)
 307 Explain what alignment considerations lead to the decision to make an insn short or long.
 308
 309 malign-call
 310 Target Var(TARGET_ALIGN_CALL)
 311 Do alignment optimizations for call instructions.
 312
 313 mRcq
 314 Target Var(TARGET_Rcq)
 315 Enable Rcq constraint handling - most short code generation depends on this.
 316
 317 mRcw
 318 Target Var(TARGET_Rcw)
 319 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 320
 321 mearly-cbranchsi
 322 Target Var(TARGET_EARLY_CBRANCHSI)
 323 Enable pre-reload use of cbranchsi pattern.
 324
 325 mbbit-peephole
 326 Target Var(TARGET_BBIT_PEEPHOLE)
 327 Enable bbit peephole2.
 328
 329 mcase-vector-pcrel
 330 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 331 Use pc-relative switch case tables - this enables case table shortening.
 332
 333 mcompact-casesi
 334 Target Warn(%qs is deprecated)
 335 Enable compact casesi pattern.
 336
 337 mq-class
 338 Target Var(TARGET_Q_CLASS)
 339 Enable 'q' instruction alternatives.
 340
 341 mexpand-adddi
 342 Target Warn(%qs is deprecated)
 343 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 344
 345
 346 ; Flags used by the assembler, but for which we define preprocessor
 347 ; macro symbols as well.
 348 mcrc
 349 Target Report Warn(%qs is deprecated)
 350 Enable variable polynomial CRC extension.
 351
 352 mdsp-packa
 353 Target Report Warn(%qs is deprecated)
 354 Enable DSP 3.1 Pack A extensions.
 355
 356 mdvbf
 357 Target Report Warn(%qs is deprecated)
 358 Enable dual viterbi butterfly extension.
 359
 360 mmac-d16
 361 Target Report Undocumented Warn(%qs is deprecated)
 362
 363 mmac-24
 364 Target Report Undocumented Warn(%qs is deprecated)
 365
 366 mtelephony
 367 Target Report RejectNegative Warn(%qs is deprecated)
 368 Enable Dual and Single Operand Instructions for Telephony.
 369
 370 mxy
 371 Target Report
 372 Enable XY Memory extension (DSP version 3).
 373
 374 ; ARC700 4.10 extension instructions
 375 mlock
 376 Target Report
 377 Enable Locked Load/Store Conditional extension.
 378
 379 mswape
 380 Target Report
 381 Enable swap byte ordering extension instruction.
 382
 383 mrtsc
 384 Target Report Warn(%qs is deprecated)
 385 Enable 64-bit Time-Stamp Counter extension instruction.
 386
 387 EB
 388 Target
 389 Pass -EB option through to linker.
 390
 391 EL
 392 Target
 393 Pass -EL option through to linker.
 394
 395 marclinux
 396 Target
 397 Pass -marclinux option through to linker.
 398
 399 marclinux_prof
 400 Target
 401 Pass -marclinux_prof option through to linker.
 402
 403 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 404 mlra
 405 Target Report Var(arc_lra_flag) Init(1) Save
 406 Use LRA instead of reload.
 407
 408 mlra-priority-none
 409 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 410 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 411
 412 mlra-priority-compact
 413 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 414 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 415
 416 mlra-priority-noncompact
 417 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 418 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 419
 420 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 421
 422 mEA
 423 Target
 424
 425 multcost=
 426 Target RejectNegative Joined
 427
 428 matomic
 429 Target Report Mask(ATOMIC)
 430 Enable atomic instructions.
 431
 432 mll64
 433 Target Report Mask(LL64)
 434 Enable double load/store instructions for ARC HS.
 435
 436 mfpu=
 437 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
 438 Specify the name of the target floating point configuration.
 439
 440 Enum
 441 Name(arc_fpu) Type(int)
 442
 443 EnumValue
 444 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
 445
 446 EnumValue
 447 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
 448
 449 EnumValue
 450 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
 451
 452 EnumValue
 453 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
 454
 455 EnumValue
 456 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
 457
 458 EnumValue
 459 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
 460
 461 EnumValue
 462 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
 463
 464 EnumValue
 465 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
 466
 467 EnumValue
 468 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
 469
 470 EnumValue
 471 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
 472
 473 EnumValue
 474 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
 475
 476 EnumValue
 477 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
 478
 479 mtp-regno=
 480 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
 481 Specify thread pointer register number.
 482
 483 mtp-regno=none
 484 Target RejectNegative Var(arc_tp_regno,-1)
 485
 486 mbitops
 487 Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
 488 Enable use of NPS400 bit operations.
 489
 490 mcmem
 491 Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
 492 Enable use of NPS400 xld/xst extension.
 493
 494 munaligned-access
 495 Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
 496 Enable unaligned word and halfword accesses to packed data.
 497
 498 mirq-ctrl-saved=
 499 Target RejectNegative Joined Var(arc_deferred_options) Defer
 500 Specifies the registers that the processor saves on an interrupt entry and exit.
 501
 502 mrgf-banked-regs=
 503 Target RejectNegative Joined Var(arc_deferred_options) Defer
 504 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
 505
 506 mlpc-width=
 507 Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
 508 Sets LP_COUNT register width.  Possible values are 8, 16, 20, 24, 28, and 32.
 509
 510 Enum
 511 Name(arc_lpc) Type(int)
 512
 513 EnumValue
 514 Enum(arc_lpc) String(8) Value(8)
 515
 516 EnumValue
 517 Enum(arc_lpc) String(16) Value(16)
 518
 519 EnumValue
 520 Enum(arc_lpc) String(20) Value(20)
 521
 522 EnumValue
 523 Enum(arc_lpc) String(24) Value(24)
 524
 525 EnumValue
 526 Enum(arc_lpc) String(28) Value(28)
 527
 528 EnumValue
 529 Enum(arc_lpc) String(32) Value(32)
 530
 531 mrf16
 532 Target Report Mask(RF16)
 533 Enable 16-entry register file.
 534
 535 mbranch-index
 536 Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
 537 Enable use of BI/BIH instructions when available.
 538
 539 mcode-density-frame
 540 Target Report Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
 541 Enable ENTER_S and LEAVE_S opcodes for ARCv2.