gcc/config/arm/arm1026ejs.md

   1 ;; ARM 1026EJ-S Pipeline Description
   2 ;; Copyright (C) 2003-2020 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; These descriptions are based on the information contained in the
  22 ;; ARM1026EJ-S Technical Reference Manual, Copyright (c) 2003 ARM
  23 ;; Limited.
  24 ;;
  25
  26 ;; This automaton provides a pipeline description for the ARM
  27 ;; 1026EJ-S core.
  28 ;;
  29 ;; The model given here assumes that the condition for all conditional
  30 ;; instructions is "true", i.e., that all of the instructions are
  31 ;; actually executed.
  32
  33 (define_automaton "arm1026ejs")
  34
  35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  36 ;; Pipelines
  37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  38
  39 ;; There are two pipelines:
  40 ;;
  41 ;; - An Arithmetic Logic Unit (ALU) pipeline.
  42 ;;
  43 ;;   The ALU pipeline has fetch, issue, decode, execute, memory, and
  44 ;;   write stages. We only need to model the execute, memory and write
  45 ;;   stages.
  46 ;;
  47 ;; - A Load-Store Unit (LSU) pipeline.
  48 ;;
  49 ;;   The LSU pipeline has decode, execute, memory, and write stages.
  50 ;;   We only model the execute, memory and write stages.
  51
  52 (define_cpu_unit "a_e,a_m,a_w" "arm1026ejs")
  53 (define_cpu_unit "l_e,l_m,l_w" "arm1026ejs")
  54
  55 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  56 ;; ALU Instructions
  57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  58
  59 ;; ALU instructions require three cycles to execute, and use the ALU
  60 ;; pipeline in each of the three stages.  The results are available
  61 ;; after the execute stage has finished.
  62 ;;
  63 ;; If the destination register is the PC, the pipelines are stalled
  64 ;; for several cycles.  That case is not modeled here.
  65
  66 ;; ALU operations with no shifted operand
  67 (define_insn_reservation "alu_op" 1
  68  (and (eq_attr "tune" "arm1026ejs")
  69       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
  70                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
  71                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
  72                        adr,bfm,rev,\
  73                        shift_imm,shift_reg,\
  74                        mov_imm,mov_reg,mvn_imm,mvn_reg,\
  75                        multiple"))
  76  "a_e,a_m,a_w")
  77
  78 ;; ALU operations with a shift-by-constant operand
  79 (define_insn_reservation "alu_shift_op" 1
  80  (and (eq_attr "tune" "arm1026ejs")
  81       (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
  82                        logic_shift_imm,logics_shift_imm,\
  83                        extend,mov_shift,mvn_shift"))
  84  "a_e,a_m,a_w")
  85
  86 ;; ALU operations with a shift-by-register operand
  87 ;; These really stall in the decoder, in order to read
  88 ;; the shift value in a second cycle. Pretend we take two cycles in
  89 ;; the execute stage.
  90 (define_insn_reservation "alu_shift_reg_op" 2
  91  (and (eq_attr "tune" "arm1026ejs")
  92       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
  93                        logic_shift_reg,logics_shift_reg,\
  94                        mov_shift_reg,mvn_shift_reg"))
  95  "a_e*2,a_m,a_w")
  96
  97 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  98 ;; Multiplication Instructions
  99 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 100
 101 ;; Multiplication instructions loop in the execute stage until the
 102 ;; instruction has been passed through the multiplier array enough
 103 ;; times.
 104
 105 ;; The result of the "smul" and "smulw" instructions is not available
 106 ;; until after the memory stage.
 107 (define_insn_reservation "mult1" 2
 108  (and (eq_attr "tune" "arm1026ejs")
 109       (eq_attr "type" "smulxy,smulwy"))
 110  "a_e,a_m,a_w")
 111
 112 ;; The "smlaxy" and "smlawx" instructions require two iterations through
 113 ;; the execute stage; the result is available immediately following
 114 ;; the execute stage.
 115 (define_insn_reservation "mult2" 2
 116  (and (eq_attr "tune" "arm1026ejs")
 117       (eq_attr "type" "smlaxy,smlalxy,smlawx"))
 118  "a_e*2,a_m,a_w")
 119
 120 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
 121 ;; through the execute stage; the result is not available until after
 122 ;; the memory stage.
 123 (define_insn_reservation "mult3" 3
 124  (and (eq_attr "tune" "arm1026ejs")
 125       (eq_attr "type" "smlalxy,mul,mla"))
 126  "a_e*2,a_m,a_w")
 127
 128 ;; The "muls" and "mlas" instructions loop in the execute stage for
 129 ;; four iterations in order to set the flags.  The value result is
 130 ;; available after three iterations.
 131 (define_insn_reservation "mult4" 3
 132  (and (eq_attr "tune" "arm1026ejs")
 133       (eq_attr "type" "muls,mlas"))
 134  "a_e*4,a_m,a_w")
 135
 136 ;; Long multiply instructions that produce two registers of
 137 ;; output (such as umull) make their results available in two cycles;
 138 ;; the least significant word is available before the most significant
 139 ;; word.  That fact is not modeled; instead, the instructions are
 140 ;; described as if the entire result was available at the end of the
 141 ;; cycle in which both words are available.
 142
 143 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
 144 ;; three iterations through the execute cycle, and make their results
 145 ;; available after the memory cycle.
 146 (define_insn_reservation "mult5" 4
 147  (and (eq_attr "tune" "arm1026ejs")
 148       (eq_attr "type" "umull,umlal,smull,smlal"))
 149  "a_e*3,a_m,a_w")
 150
 151 ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
 152 ;; the execute stage for five iterations in order to set the flags.
 153 ;; The value result is available after four iterations.
 154 (define_insn_reservation "mult6" 4
 155  (and (eq_attr "tune" "arm1026ejs")
 156       (eq_attr "type" "umulls,umlals,smulls,smlals"))
 157  "a_e*5,a_m,a_w")
 158
 159 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 160 ;; Load/Store Instructions
 161 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 162
 163 ;; The models for load/store instructions do not accurately describe
 164 ;; the difference between operations with a base register writeback
 165 ;; (such as "ldm!").  These models assume that all memory references
 166 ;; hit in dcache.
 167
 168 ;; LSU instructions require six cycles to execute.  They use the ALU
 169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
 170 ;; three through six.
 171 ;; Loads and stores which use a scaled register offset or scaled
 172 ;; register pre-indexed addressing mode take three cycles EXCEPT for
 173 ;; those that are base + offset with LSL of 0 or 2, or base - offset
 174 ;; with LSL of zero.  The remainder take 1 cycle to execute.
 175 ;; For 4byte loads there is a bypass from the load stage
 176
 177 (define_insn_reservation "load1_op" 2
 178  (and (eq_attr "tune" "arm1026ejs")
 179       (eq_attr "type" "load_byte,load_4"))
 180  "a_e+l_e,l_m,a_w+l_w")
 181
 182 (define_insn_reservation "store1_op" 0
 183  (and (eq_attr "tune" "arm1026ejs")
 184       (eq_attr "type" "store_4"))
 185  "a_e+l_e,l_m,a_w+l_w")
 186
 187 ;; A load's result can be stored by an immediately following store
 188 (define_bypass 1 "load1_op" "store1_op" "arm_no_early_store_addr_dep")
 189
 190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
 191 ;; registers have been processed.
 192 ;;
 193 ;; The time it takes to load the data depends on whether or not the
 194 ;; base address is 64-bit aligned; if it is not, an additional cycle
 195 ;; is required.  This model assumes that the address is always 64-bit
 196 ;; aligned.  Because the processor can load two registers per cycle,
 197 ;; that assumption means that we use the same instruction reservations
 198 ;; for loading 2k and 2k - 1 registers.
 199 ;;
 200 ;; The ALU pipeline is stalled until the completion of the last memory
 201 ;; stage in the LSU pipeline.  That is modeled by keeping the ALU
 202 ;; execute stage busy until that point.
 203 ;;
 204 ;; As with ALU operations, if one of the destination registers is the
 205 ;; PC, there are additional stalls; that is not modeled.
 206
 207 (define_insn_reservation "load2_op" 2
 208  (and (eq_attr "tune" "arm1026ejs")
 209       (eq_attr "type" "load_8"))
 210  "a_e+l_e,l_m,a_w+l_w")
 211
 212 (define_insn_reservation "store2_op" 0
 213  (and (eq_attr "tune" "arm1026ejs")
 214       (eq_attr "type" "store_8"))
 215  "a_e+l_e,l_m,a_w+l_w")
 216
 217 (define_insn_reservation "load34_op" 3
 218  (and (eq_attr "tune" "arm1026ejs")
 219       (eq_attr "type" "load_12,load_16"))
 220  "a_e+l_e,a_e+l_e+l_m,a_e+l_m,a_w+l_w")
 221
 222 (define_insn_reservation "store34_op" 0
 223  (and (eq_attr "tune" "arm1026ejs")
 224       (eq_attr "type" "store_12,store_16"))
 225  "a_e+l_e,a_e+l_e+l_m,a_e+l_m,a_w+l_w")
 226
 227 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 228 ;; Branch and Call Instructions
 229 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 230
 231 ;; Branch instructions are difficult to model accurately.  The ARM
 232 ;; core can predict most branches.  If the branch is predicted
 233 ;; correctly, and predicted early enough, the branch can be completely
 234 ;; eliminated from the instruction stream.  Some branches can
 235 ;; therefore appear to require zero cycles to execute.  We assume that
 236 ;; all branches are predicted correctly, and that the latency is
 237 ;; therefore the minimum value.
 238
 239 (define_insn_reservation "branch_op" 0
 240  (and (eq_attr "tune" "arm1026ejs")
 241       (eq_attr "type" "branch"))
 242  "nothing")
 243
 244 ;; The latency for a call is not predictable.  Therefore, we use 32 as
 245 ;; roughly equivalent to positive infinity.
 246
 247 (define_insn_reservation "call_op" 32
 248  (and (eq_attr "tune" "arm1026ejs")
 249       (eq_attr "type" "call"))
 250  "nothing")