1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2020 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
26 #include "coretypes.h"
34 #include "stringpool.h"
40 #include "diagnostic-core.h"
42 #include "stor-layout.h"
45 #include "conditions.h"
47 #include "insn-attr.h"
51 #include "tm-constrs.h"
54 /* This file should be included last. */
55 #include "target-def.h"
57 /* Classifies a h8300_src_operand or h8300_dst_operand.
60 A constant operand of some sort.
66 A memory reference with a constant address.
69 A memory reference with a register as its address.
72 Some other kind of memory reference. */
73 enum h8300_operand_class
83 /* For a general two-operand instruction, element [X][Y] gives
84 the length of the opcode fields when the first operand has class
85 (X + 1) and the second has class Y. */
86 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
88 /* Forward declarations. */
89 static const char *byte_reg (rtx
, int);
90 static int h8300_interrupt_function_p (tree
);
91 static int h8300_saveall_function_p (tree
);
92 static int h8300_monitor_function_p (tree
);
93 static int h8300_os_task_function_p (tree
);
94 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
95 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
96 static unsigned int compute_saved_regs (void);
97 static const char *cond_string (enum rtx_code
);
98 static unsigned int h8300_asm_insn_count (const char *);
99 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
100 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
101 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
102 static void h8300_print_operand_address (FILE *, machine_mode
, rtx
);
103 static void h8300_print_operand (FILE *, rtx
, int);
104 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
105 #ifndef OBJECT_FORMAT_ELF
106 static void h8300_asm_named_section (const char *, unsigned int, tree
);
108 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
109 static int h8300_and_costs (rtx
);
110 static int h8300_shift_costs (rtx
);
111 static void h8300_push_pop (int, int, bool, bool);
112 static int h8300_stack_offset_p (rtx
, int);
113 static int h8300_ldm_stm_regno (rtx
, int, int, int);
114 static void h8300_reorg (void);
115 static unsigned int h8300_constant_length (rtx
);
116 static unsigned int h8300_displacement_length (rtx
, int);
117 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
118 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
119 static unsigned int h8300_unary_length (rtx
);
120 static unsigned int h8300_short_immediate_length (rtx
);
121 static unsigned int h8300_bitfield_length (rtx
, rtx
);
122 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
123 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
124 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
125 static bool h8300_hard_regno_scratch_ok (unsigned int);
126 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
128 /* CPU_TYPE, says what cpu we're compiling for. */
131 /* True if a #pragma interrupt has been seen for the current function. */
132 static int pragma_interrupt
;
134 /* True if a #pragma saveall has been seen for the current function. */
135 static int pragma_saveall
;
137 static const char *const names_big
[] =
138 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
140 static const char *const names_extended
[] =
141 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
143 static const char *const names_upper_extended
[] =
144 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
146 /* Points to one of the above. */
147 /* ??? The above could be put in an array indexed by CPU_TYPE. */
148 const char * const *h8_reg_names
;
150 /* Various operations needed by the following, indexed by CPU_TYPE. */
152 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
154 /* Value of MOVE_RATIO. */
155 int h8300_move_ratio
;
157 /* See below where shifts are handled for explanation of this enum. */
167 /* Symbols of the various shifts which can be used as indices. */
171 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
174 /* Macros to keep the shift algorithm tables small. */
175 #define INL SHIFT_INLINE
176 #define ROT SHIFT_ROT_AND
177 #define LOP SHIFT_LOOP
178 #define SPC SHIFT_SPECIAL
180 /* The shift algorithms for each machine, mode, shift type, and shift
181 count are defined below. The three tables below correspond to
182 QImode, HImode, and SImode, respectively. Each table is organized
183 by, in the order of indices, machine, shift type, and shift count. */
185 static enum shift_alg shift_alg_qi
[3][3][8] = {
188 /* 0 1 2 3 4 5 6 7 */
189 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
190 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
191 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
195 /* 0 1 2 3 4 5 6 7 */
196 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
197 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
198 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
202 /* 0 1 2 3 4 5 6 7 */
203 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
204 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
205 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
209 static enum shift_alg shift_alg_hi
[3][3][16] = {
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
216 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
218 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
219 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
234 /* 0 1 2 3 4 5 6 7 */
235 /* 8 9 10 11 12 13 14 15 */
236 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
237 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
238 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
239 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
240 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
241 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
245 static enum shift_alg shift_alg_si
[3][3][32] = {
248 /* 0 1 2 3 4 5 6 7 */
249 /* 8 9 10 11 12 13 14 15 */
250 /* 16 17 18 19 20 21 22 23 */
251 /* 24 25 26 27 28 29 30 31 */
252 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
253 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
254 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
255 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
256 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
257 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
258 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
259 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
260 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
261 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
262 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
263 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
267 /* 0 1 2 3 4 5 6 7 */
268 /* 8 9 10 11 12 13 14 15 */
269 /* 16 17 18 19 20 21 22 23 */
270 /* 24 25 26 27 28 29 30 31 */
271 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
272 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
273 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
274 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
275 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
276 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
277 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
278 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
279 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
280 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
281 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
282 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
286 /* 0 1 2 3 4 5 6 7 */
287 /* 8 9 10 11 12 13 14 15 */
288 /* 16 17 18 19 20 21 22 23 */
289 /* 24 25 26 27 28 29 30 31 */
290 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
291 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
292 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
293 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
294 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
295 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
296 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
297 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
298 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
299 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
300 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
301 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
317 /* Initialize various cpu specific globals at start up. */
320 h8300_option_override (void)
322 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
323 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
324 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
326 #ifndef OBJECT_FORMAT_ELF
329 error ("%<-msx%> is not supported in coff");
330 target_flags
|= MASK_H8300S
;
336 cpu_type
= (int) CPU_H8300
;
337 h8_reg_names
= names_big
;
341 /* For this we treat the H8/300H and H8S the same. */
342 cpu_type
= (int) CPU_H8300H
;
343 h8_reg_names
= names_extended
;
345 h8_push_op
= h8_push_ops
[cpu_type
];
346 h8_pop_op
= h8_pop_ops
[cpu_type
];
347 h8_mov_op
= h8_mov_ops
[cpu_type
];
349 if (!TARGET_H8300S
&& TARGET_MAC
)
351 error ("%<-ms2600%> is used without %<-ms%>");
352 target_flags
|= MASK_H8300S_1
;
355 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
357 error ("%<-mn%> is used without %<-mh%> or %<-ms%> or %<-msx%>");
358 target_flags
^= MASK_NORMAL_MODE
;
361 if (! TARGET_H8300S
&& TARGET_EXR
)
363 error ("%<-mexr%> is used without %<-ms%>");
364 target_flags
|= MASK_H8300S_1
;
367 if (TARGET_H8300
&& TARGET_INT32
)
369 error ("%<-mint32%> is not supported for H8300 and H8300L targets");
370 target_flags
^= MASK_INT32
;
373 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
375 error ("%<-mexr%> is used without %<-ms%> or %<-msx%>");
376 target_flags
|= MASK_H8300S_1
;
379 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
381 warning (OPT_mno_exr
, "%<-mno-exr%> valid only with %<-ms%> or "
382 "%<-msx%> - Option ignored!");
386 if ((TARGET_NORMAL_MODE
))
388 error ("%<-mn%> is not supported for linux targets");
389 target_flags
^= MASK_NORMAL_MODE
;
393 /* Some of the shifts are optimized for speed by default.
394 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
395 If optimizing for size, change shift_alg for those shift to
400 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
401 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
402 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
403 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
405 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
406 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
408 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
409 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
412 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
413 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
415 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
416 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
418 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
419 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
420 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
421 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
424 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
427 /* Work out a value for MOVE_RATIO. */
430 /* Memory-memory moves are quite expensive without the
431 h8sx instructions. */
432 h8300_move_ratio
= 3;
434 else if (flag_omit_frame_pointer
)
436 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
437 sometimes be as short as two individual memory-to-memory moves,
438 but since they use all the call-saved registers, it seems better
439 to allow up to three moves here. */
440 h8300_move_ratio
= 4;
442 else if (optimize_size
)
444 /* In this case we don't use movmd sequences since they tend
445 to be longer than calls to memcpy(). Memory-to-memory
446 moves are cheaper than for !TARGET_H8300SX, so it makes
447 sense to have a slightly higher threshold. */
448 h8300_move_ratio
= 4;
452 /* We use movmd sequences for some moves since it can be quicker
453 than calling memcpy(). The sequences will need to save and
454 restore er6 though, so bump up the cost. */
455 h8300_move_ratio
= 6;
458 /* This target defaults to strict volatile bitfields. */
459 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
460 flag_strict_volatile_bitfields
= 1;
463 /* Return the byte register name for a register rtx X. B should be 0
464 if you want a lower byte register. B should be 1 if you want an
465 upper byte register. */
468 byte_reg (rtx x
, int b
)
470 static const char *const names_small
[] = {
471 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
472 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
475 gcc_assert (REG_P (x
));
477 return names_small
[REGNO (x
) * 2 + b
];
480 /* REGNO must be saved/restored across calls if this macro is true. */
482 #define WORD_REG_USED(regno) \
484 /* No need to save registers if this function will not return. */ \
485 && ! TREE_THIS_VOLATILE (current_function_decl) \
486 && (h8300_saveall_function_p (current_function_decl) \
487 /* Save any call saved register that was used. */ \
488 || (df_regs_ever_live_p (regno) \
489 && !call_used_or_fixed_reg_p (regno)) \
490 /* Save the frame pointer if it was used. */ \
491 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
492 /* Save any register used in an interrupt handler. */ \
493 || (h8300_current_function_interrupt_function_p () \
494 && df_regs_ever_live_p (regno)) \
495 /* Save call clobbered registers in non-leaf interrupt \
497 || (h8300_current_function_interrupt_function_p () \
498 && call_used_or_fixed_reg_p (regno) \
501 /* We use this to wrap all emitted insns in the prologue. */
503 F (rtx_insn
*x
, bool set_it
)
506 RTX_FRAME_RELATED_P (x
) = 1;
510 /* Mark all the subexpressions of the PARALLEL rtx PAR as
511 frame-related. Return PAR.
513 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
514 PARALLEL rtx other than the first if they do not have the
515 FRAME_RELATED flag set on them. */
519 int len
= XVECLEN (par
, 0);
522 for (i
= 0; i
< len
; i
++)
523 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, i
)) = 1;
528 /* Output assembly language to FILE for the operation OP with operand size
529 SIZE to adjust the stack pointer. */
532 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
534 /* If the frame size is 0, we don't have anything to do. */
538 /* H8/300 cannot add/subtract a large constant with a single
539 instruction. If a temporary register is available, load the
540 constant to it and then do the addition. */
543 && !h8300_current_function_interrupt_function_p ()
544 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
546 rtx r3
= gen_rtx_REG (Pmode
, 3);
547 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
548 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
549 stack_pointer_rtx
, r3
)), in_prologue
);
553 /* The stack adjustment made here is further optimized by the
554 splitter. In case of H8/300, the splitter always splits the
555 addition emitted here to make the adjustment interrupt-safe.
556 FIXME: We don't always tag those, because we don't know what
557 the splitter will do. */
560 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
562 GEN_INT (sign
* size
)));
567 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
568 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
572 /* Round up frame size SIZE. */
575 round_frame_size (HOST_WIDE_INT size
)
577 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
578 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
581 /* Compute which registers to push/pop.
582 Return a bit vector of registers. */
585 compute_saved_regs (void)
587 unsigned int saved_regs
= 0;
590 /* Construct a bit vector of registers to be pushed/popped. */
591 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
593 if (WORD_REG_USED (regno
))
594 saved_regs
|= 1 << regno
;
597 /* Don't push/pop the frame pointer as it is treated separately. */
598 if (frame_pointer_needed
)
599 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
604 /* Emit an insn to push register RN. */
607 push (int rn
, bool in_prologue
)
609 rtx reg
= gen_rtx_REG (word_mode
, rn
);
613 x
= gen_push_h8300 (reg
);
614 else if (!TARGET_NORMAL_MODE
)
615 x
= gen_push_h8300hs_advanced (reg
);
617 x
= gen_push_h8300hs_normal (reg
);
618 x
= F (emit_insn (x
), in_prologue
);
619 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
623 /* Emit an insn to pop register RN. */
628 rtx reg
= gen_rtx_REG (word_mode
, rn
);
632 x
= gen_pop_h8300 (reg
);
633 else if (!TARGET_NORMAL_MODE
)
634 x
= gen_pop_h8300hs_advanced (reg
);
636 x
= gen_pop_h8300hs_normal (reg
);
638 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
642 /* Emit an instruction to push or pop NREGS consecutive registers
643 starting at register REGNO. POP_P selects a pop rather than a
644 push and RETURN_P is true if the instruction should return.
646 It must be possible to do the requested operation in a single
647 instruction. If NREGS == 1 && !RETURN_P, use a normal push
648 or pop insn. Otherwise emit a parallel of the form:
651 [(return) ;; if RETURN_P
652 (save or restore REGNO)
653 (save or restore REGNO + 1)
655 (save or restore REGNO + NREGS - 1)
656 (set sp (plus sp (const_int adjust)))] */
659 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
665 /* See whether we can use a simple push or pop. */
666 if (!return_p
&& nregs
== 1)
675 /* We need one element for the return insn, if present, one for each
676 register, and one for stack adjustment. */
677 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
678 sp
= stack_pointer_rtx
;
681 /* Add the return instruction. */
684 RTVEC_ELT (vec
, i
) = ret_rtx
;
688 /* Add the register moves. */
689 for (j
= 0; j
< nregs
; j
++)
695 /* Register REGNO + NREGS - 1 is popped first. Before the
696 stack adjustment, its slot is at address @sp. */
697 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
698 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
699 (nregs
- j
- 1) * 4));
703 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
704 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
705 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
707 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (lhs
, rhs
);
710 /* Add the stack adjustment. */
711 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
712 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, offset
));
714 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
724 /* Return true if X has the value sp + OFFSET. */
727 h8300_stack_offset_p (rtx x
, int offset
)
730 return x
== stack_pointer_rtx
;
732 return (GET_CODE (x
) == PLUS
733 && XEXP (x
, 0) == stack_pointer_rtx
734 && GET_CODE (XEXP (x
, 1)) == CONST_INT
735 && INTVAL (XEXP (x
, 1)) == offset
);
738 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
739 something that may be an ldm or stm instruction. If it fits
740 the required template, return the register it loads or stores,
743 LOAD_P is true if X should be a load, false if it should be a store.
744 NREGS is the number of registers that the whole instruction is expected
745 to load or store. INDEX is the index of the register that X should
746 load or store, relative to the lowest-numbered register. */
749 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
751 int regindex
, memindex
, offset
;
754 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
756 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
758 if (GET_CODE (x
) == SET
759 && GET_CODE (XEXP (x
, regindex
)) == REG
760 && GET_CODE (XEXP (x
, memindex
)) == MEM
761 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
762 return REGNO (XEXP (x
, regindex
));
767 /* Return true if the elements of VEC starting at FIRST describe an
768 ldm or stm instruction (LOAD_P says which). */
771 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
774 int nregs
, i
, regno
, adjust
;
776 /* There must be a stack adjustment, a register move, and at least one
777 other operation (a return or another register move). */
778 if (GET_NUM_ELEM (vec
) < 3)
781 /* Get the range of registers to be pushed or popped. */
782 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
783 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
785 /* Check that the call to h8300_ldm_stm_regno succeeded and
786 that we're only dealing with GPRs. */
787 if (regno
< 0 || regno
+ nregs
> 8)
790 /* 2-register h8s instructions must start with an even-numbered register.
791 3- and 4-register instructions must start with er0 or er4. */
794 if ((regno
& 1) != 0)
796 if (nregs
> 2 && (regno
& 3) != 0)
800 /* Check the other loads or stores. */
801 for (i
= 1; i
< nregs
; i
++)
802 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
806 /* Check the stack adjustment. */
807 last
= RTVEC_ELT (vec
, first
+ nregs
);
808 adjust
= (load_p
? nregs
: -nregs
) * 4;
809 return (GET_CODE (last
) == SET
810 && SET_DEST (last
) == stack_pointer_rtx
811 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
814 /* This is what the stack looks like after the prolog of
815 a function with a frame has been set up:
821 <saved registers> <- sp
823 This is what the stack looks like after the prolog of
824 a function which doesn't have a frame:
829 <saved registers> <- sp
832 /* Generate RTL code for the function prologue. */
835 h8300_expand_prologue (void)
841 /* If the current function has the OS_Task attribute set, then
842 we have a naked prologue. */
843 if (h8300_os_task_function_p (current_function_decl
))
846 if (h8300_monitor_function_p (current_function_decl
))
847 /* The monitor function act as normal functions, which means it
848 can accept parameters and return values. In addition to this,
849 interrupts are masked in prologue and return with "rte" in epilogue. */
850 emit_insn (gen_monitor_prologue ());
852 if (frame_pointer_needed
)
855 push (HARD_FRAME_POINTER_REGNUM
, true);
856 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
859 /* Push the rest of the registers in ascending order. */
860 saved_regs
= compute_saved_regs ();
861 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
864 if (saved_regs
& (1 << regno
))
868 /* See how many registers we can push at the same time. */
869 if ((TARGET_H8300SX
|| (regno
& 3) == 0)
870 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
873 else if ((TARGET_H8300SX
|| (regno
& 3) == 0)
874 && ((saved_regs
>> regno
) & 0x07) == 0x07)
877 else if ((TARGET_H8300SX
|| (regno
& 1) == 0)
878 && ((saved_regs
>> regno
) & 0x03) == 0x03)
882 h8300_push_pop (regno
, n_regs
, false, false);
886 /* Leave room for locals. */
887 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
889 if (flag_stack_usage_info
)
890 current_function_static_stack_size
891 = round_frame_size (get_frame_size ())
892 + (__builtin_popcount (saved_regs
) * UNITS_PER_WORD
)
893 + (frame_pointer_needed
? UNITS_PER_WORD
: 0);
896 /* Return nonzero if we can use "rts" for the function currently being
900 h8300_can_use_return_insn_p (void)
902 return (reload_completed
903 && !frame_pointer_needed
904 && get_frame_size () == 0
905 && compute_saved_regs () == 0);
908 /* Generate RTL code for the function epilogue. */
911 h8300_expand_epilogue (void)
916 HOST_WIDE_INT frame_size
;
919 if (h8300_os_task_function_p (current_function_decl
))
920 /* OS_Task epilogues are nearly naked -- they just have an
924 frame_size
= round_frame_size (get_frame_size ());
927 /* Deallocate locals. */
928 h8300_emit_stack_adjustment (1, frame_size
, false);
930 /* Pop the saved registers in descending order. */
931 saved_regs
= compute_saved_regs ();
932 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
935 if (saved_regs
& (1 << regno
))
939 /* See how many registers we can pop at the same time. */
940 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
941 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
944 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
945 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
948 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
949 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
953 /* See if this pop would be the last insn before the return.
954 If so, use rte/l or rts/l instead of pop or ldm.l. */
956 && !frame_pointer_needed
958 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
961 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
965 /* Pop frame pointer if we had one. */
966 if (frame_pointer_needed
)
970 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
974 emit_jump_insn (ret_rtx
);
977 /* Return nonzero if the current function is an interrupt
981 h8300_current_function_interrupt_function_p (void)
983 return (h8300_interrupt_function_p (current_function_decl
));
987 h8300_current_function_monitor_function_p ()
989 return (h8300_monitor_function_p (current_function_decl
));
992 /* Output assembly code for the start of the file. */
995 h8300_file_start (void)
997 default_file_start ();
1000 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1001 else if (TARGET_H8300S
)
1002 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1003 else if (TARGET_H8300H
)
1004 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1007 /* Output assembly language code for the end of file. */
1010 h8300_file_end (void)
1012 fputs ("\t.end\n", asm_out_file
);
1015 /* Split an add of a small constant into two adds/subs insns.
1017 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1018 instead of adds/subs. */
1021 split_adds_subs (machine_mode mode
, rtx
*operands
)
1023 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1024 rtx reg
= operands
[0];
1025 HOST_WIDE_INT sign
= 1;
1026 HOST_WIDE_INT amount
;
1027 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1029 /* Force VAL to be positive so that we do not have to consider the
1040 gen_add
= gen_addhi3
;
1044 gen_add
= gen_addsi3
;
1051 /* Try different amounts in descending order. */
1052 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1056 for (; val
>= amount
; val
-= amount
)
1057 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1063 /* Handle machine specific pragmas for compatibility with existing
1064 compilers for the H8/300.
1066 pragma saveall generates prologue/epilogue code which saves and
1067 restores all the registers on function entry.
1069 pragma interrupt saves and restores all registers, and exits with
1070 an rte instruction rather than an rts. A pointer to a function
1071 with this attribute may be safely used in an interrupt vector. */
1074 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1076 pragma_interrupt
= 1;
1080 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1085 /* If the next function argument ARG is to be passed in a register, return
1086 a reg RTX for the hard register in which to pass the argument. CUM
1087 represents the state after the last argument. If the argument is to
1088 be pushed, NULL_RTX is returned.
1090 On the H8/300 all normal args are pushed, unless -mquickcall in which
1091 case the first 3 arguments are passed in registers. */
1094 h8300_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
1096 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1098 static const char *const hand_list
[] = {
1117 rtx result
= NULL_RTX
;
1121 /* Never pass unnamed arguments in registers. */
1125 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1126 if (TARGET_QUICKCALL
)
1129 /* If calling hand written assembler, use 4 regs of args. */
1132 const char * const *p
;
1134 fname
= XSTR (cum
->libcall
, 0);
1136 /* See if this libcall is one of the hand coded ones. */
1137 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1146 int size
= arg
.promoted_size_in_bytes ();
1147 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1148 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1149 result
= gen_rtx_REG (arg
.mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1155 /* Update the data in CUM to advance over argument ARG. */
1158 h8300_function_arg_advance (cumulative_args_t cum_v
,
1159 const function_arg_info
&arg
)
1161 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1163 cum
->nbytes
+= ((arg
.promoted_size_in_bytes () + UNITS_PER_WORD
- 1)
1168 /* Implements TARGET_REGISTER_MOVE_COST.
1170 Any SI register-to-register move may need to be reloaded,
1171 so inmplement h8300_register_move_cost to return > 2 so that reload never
1175 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1176 reg_class_t from
, reg_class_t to
)
1178 if (from
== MAC_REGS
|| to
== MAC_REG
)
1184 /* Compute the cost of an and insn. */
1187 h8300_and_costs (rtx x
)
1191 if (GET_MODE (x
) == QImode
)
1194 if (GET_MODE (x
) != HImode
1195 && GET_MODE (x
) != SImode
)
1199 operands
[1] = XEXP (x
, 0);
1200 operands
[2] = XEXP (x
, 1);
1202 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1205 /* Compute the cost of a shift insn. */
1208 h8300_shift_costs (rtx x
)
1212 if (GET_MODE (x
) != QImode
1213 && GET_MODE (x
) != HImode
1214 && GET_MODE (x
) != SImode
)
1219 operands
[2] = XEXP (x
, 1);
1221 return compute_a_shift_length (NULL
, operands
) / 2;
1224 /* Worker function for TARGET_RTX_COSTS. */
1227 h8300_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
1228 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
1230 int code
= GET_CODE (x
);
1232 if (TARGET_H8300SX
&& outer_code
== MEM
)
1234 /* Estimate the number of execution states needed to calculate
1236 if (register_operand (x
, VOIDmode
)
1237 || GET_CODE (x
) == POST_INC
1238 || GET_CODE (x
) == POST_DEC
1242 *total
= COSTS_N_INSNS (1);
1250 HOST_WIDE_INT n
= INTVAL (x
);
1254 /* Constant operands need the same number of processor
1255 states as register operands. Although we could try to
1256 use a size-based cost for !speed, the lack of
1257 of a mode makes the results very unpredictable. */
1261 if (n
>= -4 && n
<= 4)
1272 *total
= 0 + (outer_code
== SET
);
1276 if (TARGET_H8300H
|| TARGET_H8300S
)
1277 *total
= 0 + (outer_code
== SET
);
1292 /* See comment for CONST_INT. */
1304 if (XEXP (x
, 1) == const0_rtx
)
1309 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1310 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1312 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1315 /* We say that MOD and DIV are so expensive because otherwise we'll
1316 generate some really horrible code for division of a power of two. */
1322 switch (GET_MODE (x
))
1326 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1330 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1336 *total
= COSTS_N_INSNS (12);
1341 switch (GET_MODE (x
))
1345 *total
= COSTS_N_INSNS (2);
1349 *total
= COSTS_N_INSNS (5);
1355 *total
= COSTS_N_INSNS (4);
1361 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1363 *total
= COSTS_N_INSNS (2);
1366 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1368 *total
= COSTS_N_INSNS (1);
1371 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1376 if (GET_MODE (x
) == HImode
)
1383 *total
= COSTS_N_INSNS (1);
1388 /* Documentation for the machine specific operand escapes:
1390 'E' like s but negative.
1391 'F' like t but negative.
1392 'G' constant just the negative
1393 'R' print operand as a byte:8 address if appropriate, else fall back to
1395 'S' print operand as a long word
1396 'T' print operand as a word
1397 'V' find the set bit, and print its number.
1398 'W' find the clear bit, and print its number.
1399 'X' print operand as a byte
1400 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1401 If this operand isn't a register, fall back to 'R' handling.
1403 'c' print the opcode corresponding to rtl
1404 'e' first word of 32-bit value - if reg, then least reg. if mem
1405 then least. if const then most sig word
1406 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1407 then +2. if const then least sig word
1408 'j' print operand as condition code.
1409 'k' print operand as reverse condition code.
1410 'm' convert an integer operand to a size suffix (.b, .w or .l)
1411 'o' print an integer without a leading '#'
1412 's' print as low byte of 16-bit value
1413 't' print as high byte of 16-bit value
1414 'w' print as low byte of 32-bit value
1415 'x' print as 2nd byte of 32-bit value
1416 'y' print as 3rd byte of 32-bit value
1417 'z' print as msb of 32-bit value
1420 /* Return assembly language string which identifies a comparison type. */
1423 cond_string (enum rtx_code code
)
1452 /* Print operand X using operand code CODE to assembly language output file
1456 h8300_print_operand (FILE *file
, rtx x
, int code
)
1458 /* This is used for communication between codes V,W,Z and Y. */
1464 if (h8300_constant_length (x
) == 2)
1465 fprintf (file
, ":16");
1467 fprintf (file
, ":32");
1470 switch (GET_CODE (x
))
1473 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1476 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1483 switch (GET_CODE (x
))
1486 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1489 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1496 gcc_assert (GET_CODE (x
) == CONST_INT
);
1497 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1500 if (GET_CODE (x
) == REG
)
1501 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1506 if (GET_CODE (x
) == REG
)
1507 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1512 bitint
= (INTVAL (x
) & 0xffff);
1513 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1514 bitint
= exact_log2 (bitint
& 0xff);
1516 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1517 gcc_assert (bitint
>= 0);
1518 fprintf (file
, "#%d", bitint
);
1521 bitint
= ((~INTVAL (x
)) & 0xffff);
1522 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1523 bitint
= exact_log2 (bitint
& 0xff);
1525 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1526 gcc_assert (bitint
>= 0);
1527 fprintf (file
, "#%d", bitint
);
1531 if (GET_CODE (x
) == REG
)
1532 fprintf (file
, "%s", byte_reg (x
, 0));
1537 gcc_assert (bitint
>= 0);
1538 if (GET_CODE (x
) == REG
)
1539 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1541 h8300_print_operand (file
, x
, 'R');
1545 bitint
= INTVAL (x
);
1546 fprintf (file
, "#%d", bitint
& 7);
1549 switch (GET_CODE (x
))
1552 fprintf (file
, "or");
1555 fprintf (file
, "xor");
1558 fprintf (file
, "and");
1565 switch (GET_CODE (x
))
1569 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1571 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1574 h8300_print_operand (file
, x
, 0);
1577 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1582 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1583 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1592 switch (GET_CODE (x
))
1596 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1598 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1601 x
= adjust_address (x
, HImode
, 2);
1602 h8300_print_operand (file
, x
, 0);
1605 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1610 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1611 fprintf (file
, "#%ld", (val
& 0xffff));
1619 fputs (cond_string (GET_CODE (x
)), file
);
1622 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1625 gcc_assert (GET_CODE (x
) == CONST_INT
);
1645 h8300_print_operand_address (file
, VOIDmode
, x
);
1648 if (GET_CODE (x
) == CONST_INT
)
1649 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1651 fprintf (file
, "%s", byte_reg (x
, 0));
1654 if (GET_CODE (x
) == CONST_INT
)
1655 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1657 fprintf (file
, "%s", byte_reg (x
, 1));
1660 if (GET_CODE (x
) == CONST_INT
)
1661 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1663 fprintf (file
, "%s",
1664 byte_reg (x
, TARGET_H8300
? 2 : 0));
1667 if (GET_CODE (x
) == CONST_INT
)
1668 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1670 fprintf (file
, "%s",
1671 byte_reg (x
, TARGET_H8300
? 3 : 1));
1674 if (GET_CODE (x
) == CONST_INT
)
1675 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1677 fprintf (file
, "%s", byte_reg (x
, 0));
1680 if (GET_CODE (x
) == CONST_INT
)
1681 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1683 fprintf (file
, "%s", byte_reg (x
, 1));
1688 switch (GET_CODE (x
))
1691 switch (GET_MODE (x
))
1694 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1695 fprintf (file
, "%s", byte_reg (x
, 0));
1696 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1697 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1701 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1705 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1714 rtx addr
= XEXP (x
, 0);
1716 fprintf (file
, "@");
1717 output_address (GET_MODE (x
), addr
);
1719 /* Add a length suffix to constant addresses. Although this
1720 is often unnecessary, it helps to avoid ambiguity in the
1721 syntax of mova. If we wrote an insn like:
1723 mova/w.l @(1,@foo.b),er0
1725 then .b would be considered part of the symbol name.
1726 Adding a length after foo will avoid this. */
1727 if (CONSTANT_P (addr
))
1731 /* Used for mov.b and bit operations. */
1732 if (h8300_eightbit_constant_address_p (addr
))
1734 fprintf (file
, ":8");
1740 /* We should not get here if we are processing bit
1741 operations on H8/300 or H8/300H because 'U'
1742 constraint does not allow bit operations on the
1743 tiny area on these machines. */
1748 if (h8300_constant_length (addr
) == 2)
1749 fprintf (file
, ":16");
1751 fprintf (file
, ":32");
1763 fprintf (file
, "#");
1764 h8300_print_operand_address (file
, VOIDmode
, x
);
1769 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1770 fprintf (file
, "#%ld", val
);
1779 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1782 h8300_print_operand_punct_valid_p (unsigned char code
)
1784 return (code
== '#');
1787 /* Output assembly language output for the address ADDR to FILE. */
1790 h8300_print_operand_address (FILE *file
, machine_mode mode
, rtx addr
)
1795 switch (GET_CODE (addr
))
1798 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1802 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1806 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1810 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1814 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1818 fprintf (file
, "(");
1820 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1821 if (GET_CODE (index
) == REG
)
1824 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1825 fprintf (file
, ",");
1829 h8300_print_operand_address (file
, mode
, index
);
1833 h8300_print_operand (file
, index
, 'X');
1838 h8300_print_operand (file
, index
, 'T');
1843 h8300_print_operand (file
, index
, 'S');
1847 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1852 h8300_print_operand_address (file
, mode
, XEXP (addr
, 0));
1853 fprintf (file
, "+");
1854 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1856 fprintf (file
, ")");
1861 /* Since the H8/300 only has 16-bit pointers, negative values are also
1862 those >= 32768. This happens for example with pointer minus a
1863 constant. We don't want to turn (char *p - 2) into
1864 (char *p + 65534) because loop unrolling can build upon this
1865 (IE: char *p + 131068). */
1866 int n
= INTVAL (addr
);
1868 n
= (int) (short) n
;
1869 fprintf (file
, "%d", n
);
1874 output_addr_const (file
, addr
);
1879 /* Output all insn addresses and their sizes into the assembly language
1880 output file. This is helpful for debugging whether the length attributes
1881 in the md file are correct. This is not meant to be a user selectable
1885 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1886 int num_operands ATTRIBUTE_UNUSED
)
1888 /* This holds the last insn address. */
1889 static int last_insn_address
= 0;
1891 const int uid
= INSN_UID (insn
);
1893 if (TARGET_ADDRESSES
)
1895 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1896 INSN_ADDRESSES (uid
) - last_insn_address
);
1897 last_insn_address
= INSN_ADDRESSES (uid
);
1901 /* Prepare for an SI sized move. */
1904 h8300_expand_movsi (rtx operands
[])
1906 rtx src
= operands
[1];
1907 rtx dst
= operands
[0];
1908 if (!reload_in_progress
&& !reload_completed
)
1910 if (!register_operand (dst
, GET_MODE (dst
)))
1912 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1913 emit_move_insn (tmp
, src
);
1920 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1921 Frame pointer elimination is automatically handled.
1923 For the h8300, if frame pointer elimination is being done, we would like to
1924 convert ap and rp into sp, not fp.
1926 All other eliminations are valid. */
1929 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1931 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1934 /* Conditionally modify register usage based on target flags. */
1937 h8300_conditional_register_usage (void)
1940 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1943 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1944 Define the offset between two registers, one to be eliminated, and
1945 the other its replacement, at the start of a routine. */
1948 h8300_initial_elimination_offset (int from
, int to
)
1950 /* The number of bytes that the return address takes on the stack. */
1951 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1953 /* The number of bytes that the saved frame pointer takes on the stack. */
1954 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1956 /* The number of bytes that the saved registers, excluding the frame
1957 pointer, take on the stack. */
1958 int saved_regs_size
= 0;
1960 /* The number of bytes that the locals takes on the stack. */
1961 int frame_size
= round_frame_size (get_frame_size ());
1965 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1966 if (WORD_REG_USED (regno
))
1967 saved_regs_size
+= UNITS_PER_WORD
;
1969 /* Adjust saved_regs_size because the above loop took the frame
1970 pointer int account. */
1971 saved_regs_size
-= fp_size
;
1975 case HARD_FRAME_POINTER_REGNUM
:
1978 case ARG_POINTER_REGNUM
:
1979 return pc_size
+ fp_size
;
1980 case RETURN_ADDRESS_POINTER_REGNUM
:
1982 case FRAME_POINTER_REGNUM
:
1983 return -saved_regs_size
;
1988 case STACK_POINTER_REGNUM
:
1991 case ARG_POINTER_REGNUM
:
1992 return pc_size
+ saved_regs_size
+ frame_size
;
1993 case RETURN_ADDRESS_POINTER_REGNUM
:
1994 return saved_regs_size
+ frame_size
;
1995 case FRAME_POINTER_REGNUM
:
2007 /* Worker function for RETURN_ADDR_RTX. */
2010 h8300_return_addr_rtx (int count
, rtx frame
)
2015 ret
= gen_rtx_MEM (Pmode
,
2016 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2017 else if (flag_omit_frame_pointer
)
2020 ret
= gen_rtx_MEM (Pmode
,
2021 memory_address (Pmode
,
2022 plus_constant (Pmode
, frame
,
2024 set_mem_alias_set (ret
, get_frame_alias_set ());
2028 /* Update the condition code from the insn. */
2031 notice_update_cc (rtx body
, rtx_insn
*insn
)
2035 switch (get_attr_cc (insn
))
2038 /* Insn does not affect CC at all. */
2042 /* Insn does not change CC, but the 0'th operand has been changed. */
2043 if (cc_status
.value1
!= 0
2044 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2045 cc_status
.value1
= 0;
2046 if (cc_status
.value2
!= 0
2047 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2048 cc_status
.value2
= 0;
2052 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2053 The V flag is unusable. The C flag may or may not be known but
2054 that's ok because alter_cond will change tests to use EQ/NE. */
2056 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2057 set
= single_set (insn
);
2058 cc_status
.value1
= SET_SRC (set
);
2059 if (SET_DEST (set
) != cc0_rtx
)
2060 cc_status
.value2
= SET_DEST (set
);
2064 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2065 The C flag may or may not be known but that's ok because
2066 alter_cond will change tests to use EQ/NE. */
2068 cc_status
.flags
|= CC_NO_CARRY
;
2069 set
= single_set (insn
);
2070 cc_status
.value1
= SET_SRC (set
);
2071 if (SET_DEST (set
) != cc0_rtx
)
2073 /* If the destination is STRICT_LOW_PART, strip off
2075 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2076 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2078 cc_status
.value2
= SET_DEST (set
);
2083 /* The insn is a compare instruction. */
2085 cc_status
.value1
= SET_SRC (body
);
2089 /* Insn doesn't leave CC in a usable state. */
2095 /* Given that X occurs in an address of the form (plus X constant),
2096 return the part of X that is expected to be a register. There are
2097 four kinds of addressing mode to recognize:
2104 If SIZE is nonnull, and the address is one of the last three forms,
2105 set *SIZE to the index multiplication factor. Set it to 0 for
2106 plain @(dd,Rn) addresses.
2108 MODE is the mode of the value being accessed. It can be VOIDmode
2109 if the address is known to be valid, but its mode is unknown. */
2112 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2119 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2122 && (mode
== VOIDmode
2123 || GET_MODE_CLASS (mode
) == MODE_INT
2124 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2126 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2128 /* When accessing byte-sized values, the index can be
2129 a zero-extended QImode or HImode register. */
2130 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2135 /* We're looking for addresses of the form:
2138 or (mult (zero_extend X) I)
2140 where I is the size of the operand being accessed.
2141 The canonical form of the second expression is:
2143 (and (mult (subreg X) I) J)
2145 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2148 if (GET_CODE (x
) == AND
2149 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2151 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2152 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2154 index
= XEXP (x
, 0);
2155 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2163 if (GET_CODE (index
) == MULT
2164 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2165 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2166 return XEXP (index
, 0);
2173 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2175 On the H8/300, the predecrement and postincrement address depend thus
2176 (the amount of decrement or increment being the length of the operand). */
2179 h8300_mode_dependent_address_p (const_rtx addr
,
2180 addr_space_t as ATTRIBUTE_UNUSED
)
2182 if (GET_CODE (addr
) == PLUS
2183 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2189 static const h8300_length_table addb_length_table
=
2191 /* #xx Rs @aa @Rs @xx */
2192 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2193 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2194 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2195 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2198 static const h8300_length_table addw_length_table
=
2200 /* #xx Rs @aa @Rs @xx */
2201 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2202 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2203 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2204 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2207 static const h8300_length_table addl_length_table
=
2209 /* #xx Rs @aa @Rs @xx */
2210 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2211 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2212 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2213 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2216 #define logicb_length_table addb_length_table
2217 #define logicw_length_table addw_length_table
2219 static const h8300_length_table logicl_length_table
=
2221 /* #xx Rs @aa @Rs @xx */
2222 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2223 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2224 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2225 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2228 static const h8300_length_table movb_length_table
=
2230 /* #xx Rs @aa @Rs @xx */
2231 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2232 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2233 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2234 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2237 #define movw_length_table movb_length_table
2239 static const h8300_length_table movl_length_table
=
2241 /* #xx Rs @aa @Rs @xx */
2242 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2243 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2244 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2245 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2248 /* Return the size of the given address or displacement constant. */
2251 h8300_constant_length (rtx constant
)
2253 /* Check for (@d:16,Reg). */
2254 if (GET_CODE (constant
) == CONST_INT
2255 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2258 /* Check for (@d:16,Reg) in cases where the displacement is
2259 an absolute address. */
2260 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2266 /* Return the size of a displacement field in address ADDR, which should
2267 have the form (plus X constant). SIZE is the number of bytes being
2271 h8300_displacement_length (rtx addr
, int size
)
2275 offset
= XEXP (addr
, 1);
2277 /* Check for @(d:2,Reg). */
2278 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2279 && GET_CODE (offset
) == CONST_INT
2280 && (INTVAL (offset
) == size
2281 || INTVAL (offset
) == size
* 2
2282 || INTVAL (offset
) == size
* 3))
2285 return h8300_constant_length (offset
);
2288 /* Store the class of operand OP in *OPCLASS and return the length of any
2289 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2290 can be null if only the length is needed. */
2293 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2295 enum h8300_operand_class dummy
;
2300 if (CONSTANT_P (op
))
2302 *opclass
= H8OP_IMMEDIATE
;
2304 /* Byte-sized immediates are stored in the opcode fields. */
2308 /* If this is a 32-bit instruction, see whether the constant
2309 will fit into a 16-bit immediate field. */
2312 && GET_CODE (op
) == CONST_INT
2313 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2318 else if (GET_CODE (op
) == MEM
)
2321 if (CONSTANT_P (op
))
2323 *opclass
= H8OP_MEM_ABSOLUTE
;
2324 return h8300_constant_length (op
);
2326 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2328 *opclass
= H8OP_MEM_COMPLEX
;
2329 return h8300_displacement_length (op
, size
);
2331 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2333 *opclass
= H8OP_MEM_COMPLEX
;
2336 else if (register_operand (op
, VOIDmode
))
2338 *opclass
= H8OP_MEM_BASE
;
2342 gcc_assert (register_operand (op
, VOIDmode
));
2343 *opclass
= H8OP_REGISTER
;
2347 /* Return the length of the instruction described by TABLE given that
2348 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2349 and OP2 must be an h8300_src_operand. */
2352 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2354 enum h8300_operand_class op1_class
, op2_class
;
2355 unsigned int size
, immediate_length
;
2357 size
= GET_MODE_SIZE (GET_MODE (op1
));
2358 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2359 + h8300_classify_operand (op2
, size
, &op2_class
));
2360 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2363 /* Return the length of a unary instruction such as neg or not given that
2364 its operand is OP. */
2367 h8300_unary_length (rtx op
)
2369 enum h8300_operand_class opclass
;
2370 unsigned int size
, operand_length
;
2372 size
= GET_MODE_SIZE (GET_MODE (op
));
2373 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2380 return (size
== 4 ? 6 : 4);
2382 case H8OP_MEM_ABSOLUTE
:
2383 return operand_length
+ (size
== 4 ? 6 : 4);
2385 case H8OP_MEM_COMPLEX
:
2386 return operand_length
+ 6;
2393 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2396 h8300_short_immediate_length (rtx op
)
2398 enum h8300_operand_class opclass
;
2399 unsigned int size
, operand_length
;
2401 size
= GET_MODE_SIZE (GET_MODE (op
));
2402 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2410 case H8OP_MEM_ABSOLUTE
:
2411 case H8OP_MEM_COMPLEX
:
2412 return 4 + operand_length
;
2419 /* Likewise bitfield load and store instructions. */
2422 h8300_bitfield_length (rtx op
, rtx op2
)
2424 enum h8300_operand_class opclass
;
2425 unsigned int size
, operand_length
;
2427 if (GET_CODE (op
) == REG
)
2429 gcc_assert (GET_CODE (op
) != REG
);
2431 size
= GET_MODE_SIZE (GET_MODE (op
));
2432 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2437 case H8OP_MEM_ABSOLUTE
:
2438 case H8OP_MEM_COMPLEX
:
2439 return 4 + operand_length
;
2446 /* Calculate the length of general binary instruction INSN using TABLE. */
2449 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2453 set
= single_set (insn
);
2456 if (BINARY_P (SET_SRC (set
)))
2457 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2458 XEXP (SET_SRC (set
), 1), table
);
2461 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2462 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2463 XEXP (XEXP (SET_SRC (set
), 1), 1),
2468 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2469 memory reference and either (1) it has the form @(d:16,Rn) or
2470 (2) its address has the code given by INC_CODE. */
2473 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2478 if (GET_CODE (op
) != MEM
)
2481 addr
= XEXP (op
, 0);
2482 size
= GET_MODE_SIZE (GET_MODE (op
));
2483 if (size
!= 1 && size
!= 2)
2486 return (GET_CODE (addr
) == inc_code
2487 || (GET_CODE (addr
) == PLUS
2488 && GET_CODE (XEXP (addr
, 0)) == REG
2489 && h8300_displacement_length (addr
, size
) == 2));
2492 /* Calculate the length of move instruction INSN using the given length
2493 table. Although the tables are correct for most cases, there is some
2494 irregularity in the length of mov.b and mov.w. The following forms:
2501 are two bytes shorter than most other "mov Rs, @complex" or
2502 "mov @complex,Rd" combinations. */
2505 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2509 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2510 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2512 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2517 /* Return the length of a mova instruction with the given operands.
2518 DEST is the register destination, SRC is the source address and
2519 OFFSET is the 16-bit or 32-bit displacement. */
2522 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2527 + h8300_constant_length (offset
)
2528 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2529 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2534 /* Compute the length of INSN based on its length_table attribute.
2535 OPERANDS is the array of its operands. */
2538 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2540 switch (get_attr_length_table (insn
))
2542 case LENGTH_TABLE_NONE
:
2545 case LENGTH_TABLE_ADD
:
2546 if (GET_MODE (operands
[0]) == QImode
)
2547 return h8300_binary_length (insn
, &addb_length_table
);
2548 else if (GET_MODE (operands
[0]) == HImode
)
2549 return h8300_binary_length (insn
, &addw_length_table
);
2550 else if (GET_MODE (operands
[0]) == SImode
)
2551 return h8300_binary_length (insn
, &addl_length_table
);
2554 case LENGTH_TABLE_LOGICB
:
2555 return h8300_binary_length (insn
, &logicb_length_table
);
2557 case LENGTH_TABLE_MOVB
:
2558 return h8300_move_length (operands
, &movb_length_table
);
2560 case LENGTH_TABLE_MOVW
:
2561 return h8300_move_length (operands
, &movw_length_table
);
2563 case LENGTH_TABLE_MOVL
:
2564 return h8300_move_length (operands
, &movl_length_table
);
2566 case LENGTH_TABLE_MOVA
:
2567 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2569 case LENGTH_TABLE_MOVA_ZERO
:
2570 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2572 case LENGTH_TABLE_UNARY
:
2573 return h8300_unary_length (operands
[0]);
2575 case LENGTH_TABLE_MOV_IMM4
:
2576 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2578 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2579 return h8300_short_immediate_length (operands
[0]);
2581 case LENGTH_TABLE_BITFIELD
:
2582 return h8300_bitfield_length (operands
[0], operands
[1]);
2584 case LENGTH_TABLE_BITBRANCH
:
2585 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2592 /* Return true if LHS and RHS are memory references that can be mapped
2593 to the same h8sx assembly operand. LHS appears as the destination of
2594 an instruction and RHS appears as a source.
2596 Three cases are allowed:
2598 - RHS is @+Rn or @-Rn, LHS is @Rn
2599 - RHS is @Rn, LHS is @Rn+ or @Rn-
2600 - RHS and LHS have the same address and neither has side effects. */
2603 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2605 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2607 rhs
= XEXP (rhs
, 0);
2608 lhs
= XEXP (lhs
, 0);
2610 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2611 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2613 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2614 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2616 if (rtx_equal_p (rhs
, lhs
))
2622 /* Return true if OPERANDS[1] can be mapped to the same assembly
2623 operand as OPERANDS[0]. */
2626 h8300_operands_match_p (rtx
*operands
)
2628 if (register_operand (operands
[0], VOIDmode
)
2629 && register_operand (operands
[1], VOIDmode
))
2632 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2638 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2639 region DEST. The two regions do not overlap and have the common
2640 alignment given by ALIGNMENT. Return true on success.
2642 Using movmd for variable-length moves seems to involve some
2643 complex trade-offs. For instance:
2645 - Preparing for a movmd instruction is similar to preparing
2646 for a memcpy. The main difference is that the arguments
2647 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2649 - Since movmd clobbers the frame pointer, we need to save
2650 and restore it somehow when frame_pointer_needed. This can
2651 sometimes make movmd sequences longer than calls to memcpy().
2653 - The counter register is 16 bits, so the instruction is only
2654 suitable for variable-length moves when sizeof (size_t) == 2.
2655 That's only true in normal mode.
2657 - We will often lack static alignment information. Falling back
2658 on movmd.b would likely be slower than calling memcpy(), at least
2661 This function therefore only uses movmd when the length is a
2662 known constant, and only then if -fomit-frame-pointer is in
2663 effect or if we're not optimizing for size.
2665 At the moment the function uses movmd for all in-range constants,
2666 but it might be better to fall back on memcpy() for large moves
2667 if ALIGNMENT == 1. */
2670 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2671 HOST_WIDE_INT alignment
)
2673 if (!flag_omit_frame_pointer
&& optimize_size
)
2676 if (GET_CODE (length
) == CONST_INT
)
2678 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2682 /* Use movmd.l if the alignment allows it, otherwise fall back
2684 factor
= (alignment
>= 2 ? 4 : 1);
2686 /* Make sure the length is within range. We can handle counter
2687 values up to 65536, although HImode truncation will make
2688 the count appear negative in rtl dumps. */
2689 n
= INTVAL (length
);
2690 if (n
<= 0 || n
/ factor
> 65536)
2693 /* Create temporary registers for the source and destination
2694 pointers. Initialize them to the start of each region. */
2695 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2696 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2698 /* Create references to the movmd source and destination blocks. */
2699 first_dest
= replace_equiv_address (dest
, dest_reg
);
2700 first_src
= replace_equiv_address (src
, src_reg
);
2702 set_mem_size (first_dest
, n
& -factor
);
2703 set_mem_size (first_src
, n
& -factor
);
2705 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2706 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2708 if ((n
& -factor
) != n
)
2710 /* Move SRC and DEST past the region we just copied.
2711 This is done to update the memory attributes. */
2712 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2713 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2715 /* Replace the addresses with the source and destination
2716 registers, which movmd has left with the right values. */
2717 dest
= replace_equiv_address (dest
, dest_reg
);
2718 src
= replace_equiv_address (src
, src_reg
);
2720 /* Mop up the left-over bytes. */
2722 emit_move_insn (adjust_address (dest
, HImode
, 0),
2723 adjust_address (src
, HImode
, 0));
2725 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2726 adjust_address (src
, QImode
, n
& 2));
2733 /* Move ADDR into er6 after pushing its old value onto the stack. */
2736 h8300_swap_into_er6 (rtx addr
)
2738 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
, false);
2739 if (frame_pointer_needed
)
2740 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2741 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2742 2 * UNITS_PER_WORD
));
2744 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2745 gen_rtx_SET (stack_pointer_rtx
,
2746 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2748 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2749 if (REGNO (addr
) == SP_REG
)
2750 emit_move_insn (hard_frame_pointer_rtx
,
2751 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2752 GET_MODE_SIZE (word_mode
)));
2755 /* Move the current value of er6 into ADDR and pop its old value
2759 h8300_swap_out_of_er6 (rtx addr
)
2763 if (REGNO (addr
) != SP_REG
)
2764 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2766 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2767 if (frame_pointer_needed
)
2768 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2769 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2770 2 * UNITS_PER_WORD
));
2772 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2773 gen_rtx_SET (stack_pointer_rtx
,
2774 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2777 /* Return the length of mov instruction. */
2780 compute_mov_length (rtx
*operands
)
2782 /* If the mov instruction involves a memory operand, we compute the
2783 length, assuming the largest addressing mode is used, and then
2784 adjust later in the function. Otherwise, we compute and return
2785 the exact length in one step. */
2786 machine_mode mode
= GET_MODE (operands
[0]);
2787 rtx dest
= operands
[0];
2788 rtx src
= operands
[1];
2791 if (GET_CODE (src
) == MEM
)
2792 addr
= XEXP (src
, 0);
2793 else if (GET_CODE (dest
) == MEM
)
2794 addr
= XEXP (dest
, 0);
2800 unsigned int base_length
;
2805 if (addr
== NULL_RTX
)
2808 /* The eightbit addressing is available only in QImode, so
2809 go ahead and take care of it. */
2810 if (h8300_eightbit_constant_address_p (addr
))
2817 if (addr
== NULL_RTX
)
2822 if (src
== const0_rtx
)
2832 if (addr
== NULL_RTX
)
2837 if (GET_CODE (src
) == CONST_INT
)
2839 if (src
== const0_rtx
)
2842 if ((INTVAL (src
) & 0xffff) == 0)
2845 if ((INTVAL (src
) & 0xffff) == 0)
2848 if ((INTVAL (src
) & 0xffff)
2849 == ((INTVAL (src
) >> 16) & 0xffff))
2859 if (addr
== NULL_RTX
)
2864 if (satisfies_constraint_G (src
))
2877 /* Adjust the length based on the addressing mode used.
2878 Specifically, we subtract the difference between the actual
2879 length and the longest one, which is @(d:16,Rs). For SImode
2880 and SFmode, we double the adjustment because two mov.w are
2881 used to do the job. */
2883 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2884 if (GET_CODE (addr
) == PRE_DEC
2885 || GET_CODE (addr
) == POST_INC
)
2887 if (mode
== QImode
|| mode
== HImode
)
2888 return base_length
- 2;
2890 /* In SImode and SFmode, we use two mov.w instructions, so
2891 double the adjustment. */
2892 return base_length
- 4;
2895 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2896 in SImode and SFmode, the second mov.w involves an address
2897 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2899 if (GET_CODE (addr
) == REG
)
2900 return base_length
- 2;
2906 unsigned int base_length
;
2911 if (addr
== NULL_RTX
)
2914 /* The eightbit addressing is available only in QImode, so
2915 go ahead and take care of it. */
2916 if (h8300_eightbit_constant_address_p (addr
))
2923 if (addr
== NULL_RTX
)
2928 if (src
== const0_rtx
)
2938 if (addr
== NULL_RTX
)
2942 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2948 if (GET_CODE (src
) == CONST_INT
)
2950 int val
= INTVAL (src
);
2955 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2958 switch (val
& 0xffffffff)
2979 if (addr
== NULL_RTX
)
2984 if (satisfies_constraint_G (src
))
2997 /* Adjust the length based on the addressing mode used.
2998 Specifically, we subtract the difference between the actual
2999 length and the longest one, which is @(d:24,ERs). */
3001 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3002 if (GET_CODE (addr
) == PRE_DEC
3003 || GET_CODE (addr
) == POST_INC
)
3004 return base_length
- 6;
3006 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3007 if (GET_CODE (addr
) == REG
)
3008 return base_length
- 6;
3010 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3012 if (GET_CODE (addr
) == PLUS
3013 && GET_CODE (XEXP (addr
, 0)) == REG
3014 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3015 && INTVAL (XEXP (addr
, 1)) > -32768
3016 && INTVAL (XEXP (addr
, 1)) < 32767)
3017 return base_length
- 4;
3019 /* @aa:16 is 4 bytes shorter than the longest. */
3020 if (h8300_tiny_constant_address_p (addr
))
3021 return base_length
- 4;
3023 /* @aa:24 is 2 bytes shorter than the longest. */
3024 if (CONSTANT_P (addr
))
3025 return base_length
- 2;
3031 /* Output an addition insn. */
3034 output_plussi (rtx
*operands
)
3036 machine_mode mode
= GET_MODE (operands
[0]);
3038 gcc_assert (mode
== SImode
);
3042 if (GET_CODE (operands
[2]) == REG
)
3043 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3045 if (GET_CODE (operands
[2]) == CONST_INT
)
3047 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3049 if ((n
& 0xffffff) == 0)
3050 return "add\t%z2,%z0";
3051 if ((n
& 0xffff) == 0)
3052 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3053 if ((n
& 0xff) == 0)
3054 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3057 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3061 if (GET_CODE (operands
[2]) == CONST_INT
3062 && register_operand (operands
[1], VOIDmode
))
3064 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3066 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3067 return "add.l\t%S2,%S0";
3068 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3069 return "sub.l\t%G2,%S0";
3071 /* See if we can finish with 2 bytes. */
3073 switch ((unsigned int) intval
& 0xffffffff)
3078 return "adds\t%2,%S0";
3083 return "subs\t%G2,%S0";
3087 operands
[2] = GEN_INT (intval
>> 16);
3088 return "inc.w\t%2,%e0";
3092 operands
[2] = GEN_INT (intval
>> 16);
3093 return "dec.w\t%G2,%e0";
3096 /* See if we can finish with 4 bytes. */
3097 if ((intval
& 0xffff) == 0)
3099 operands
[2] = GEN_INT (intval
>> 16);
3100 return "add.w\t%2,%e0";
3104 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3106 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3107 return "sub.l\t%S2,%S0";
3109 return "add.l\t%S2,%S0";
3113 /* ??? It would be much easier to add the h8sx stuff if a single function
3114 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3115 /* Compute the length of an addition insn. */
3118 compute_plussi_length (rtx
*operands
)
3120 machine_mode mode
= GET_MODE (operands
[0]);
3122 gcc_assert (mode
== SImode
);
3126 if (GET_CODE (operands
[2]) == REG
)
3129 if (GET_CODE (operands
[2]) == CONST_INT
)
3131 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3133 if ((n
& 0xffffff) == 0)
3135 if ((n
& 0xffff) == 0)
3137 if ((n
& 0xff) == 0)
3145 if (GET_CODE (operands
[2]) == CONST_INT
3146 && register_operand (operands
[1], VOIDmode
))
3148 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3150 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3152 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3155 /* See if we can finish with 2 bytes. */
3157 switch ((unsigned int) intval
& 0xffffffff)
3178 /* See if we can finish with 4 bytes. */
3179 if ((intval
& 0xffff) == 0)
3183 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3184 return h8300_length_from_table (operands
[0],
3185 GEN_INT (-INTVAL (operands
[2])),
3186 &addl_length_table
);
3188 return h8300_length_from_table (operands
[0], operands
[2],
3189 &addl_length_table
);
3194 /* Compute which flag bits are valid after an addition insn. */
3197 compute_plussi_cc (rtx
*operands
)
3199 machine_mode mode
= GET_MODE (operands
[0]);
3201 gcc_assert (mode
== SImode
);
3209 if (GET_CODE (operands
[2]) == CONST_INT
3210 && register_operand (operands
[1], VOIDmode
))
3212 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3214 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3216 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3219 /* See if we can finish with 2 bytes. */
3221 switch ((unsigned int) intval
& 0xffffffff)
3226 return CC_NONE_0HIT
;
3231 return CC_NONE_0HIT
;
3242 /* See if we can finish with 4 bytes. */
3243 if ((intval
& 0xffff) == 0)
3251 /* Output a logical insn. */
3254 output_logical_op (machine_mode mode
, rtx
*operands
)
3256 /* Figure out the logical op that we need to perform. */
3257 enum rtx_code code
= GET_CODE (operands
[3]);
3258 /* Pretend that every byte is affected if both operands are registers. */
3259 const unsigned HOST_WIDE_INT intval
=
3260 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3261 /* Always use the full instruction if the
3262 first operand is in memory. It is better
3263 to use define_splits to generate the shorter
3264 sequence where valid. */
3265 && register_operand (operands
[1], VOIDmode
)
3266 ? INTVAL (operands
[2]) : 0x55555555);
3267 /* The determinant of the algorithm. If we perform an AND, 0
3268 affects a bit. Otherwise, 1 affects a bit. */
3269 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3270 /* Break up DET into pieces. */
3271 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3272 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3273 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3274 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3275 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3276 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3277 int lower_half_easy_p
= 0;
3278 int upper_half_easy_p
= 0;
3279 /* The name of an insn. */
3301 /* First, see if we can finish with one insn. */
3302 if ((TARGET_H8300H
|| TARGET_H8300S
)
3306 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3307 output_asm_insn (insn_buf
, operands
);
3311 /* Take care of the lower byte. */
3314 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3315 output_asm_insn (insn_buf
, operands
);
3317 /* Take care of the upper byte. */
3320 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3321 output_asm_insn (insn_buf
, operands
);
3326 if (TARGET_H8300H
|| TARGET_H8300S
)
3328 /* Determine if the lower half can be taken care of in no more
3330 lower_half_easy_p
= (b0
== 0
3332 || (code
!= IOR
&& w0
== 0xffff));
3334 /* Determine if the upper half can be taken care of in no more
3336 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3337 || (code
== AND
&& w1
== 0xff00));
3340 /* Check if doing everything with one insn is no worse than
3341 using multiple insns. */
3342 if ((TARGET_H8300H
|| TARGET_H8300S
)
3343 && w0
!= 0 && w1
!= 0
3344 && !(lower_half_easy_p
&& upper_half_easy_p
)
3345 && !(code
== IOR
&& w1
== 0xffff
3346 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3348 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3349 output_asm_insn (insn_buf
, operands
);
3353 /* Take care of the lower and upper words individually. For
3354 each word, we try different methods in the order of
3356 1) the special insn (in case of AND or XOR),
3357 2) the word-wise insn, and
3358 3) The byte-wise insn. */
3360 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3361 output_asm_insn ((code
== AND
)
3362 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3364 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3368 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3369 output_asm_insn (insn_buf
, operands
);
3375 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3376 output_asm_insn (insn_buf
, operands
);
3380 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3381 output_asm_insn (insn_buf
, operands
);
3386 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3387 output_asm_insn ((code
== AND
)
3388 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3390 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3393 && (w0
& 0x8000) != 0)
3395 output_asm_insn ("exts.l\t%S0", operands
);
3397 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3401 output_asm_insn ("extu.w\t%e0", operands
);
3403 else if (TARGET_H8300H
|| TARGET_H8300S
)
3407 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3408 output_asm_insn (insn_buf
, operands
);
3415 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3416 output_asm_insn (insn_buf
, operands
);
3420 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3421 output_asm_insn (insn_buf
, operands
);
3432 /* Compute the length of a logical insn. */
3435 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3437 /* Figure out the logical op that we need to perform. */
3438 enum rtx_code code
= GET_CODE (operands
[3]);
3439 /* Pretend that every byte is affected if both operands are registers. */
3440 const unsigned HOST_WIDE_INT intval
=
3441 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3442 /* Always use the full instruction if the
3443 first operand is in memory. It is better
3444 to use define_splits to generate the shorter
3445 sequence where valid. */
3446 && register_operand (operands
[1], VOIDmode
)
3447 ? INTVAL (operands
[2]) : 0x55555555);
3448 /* The determinant of the algorithm. If we perform an AND, 0
3449 affects a bit. Otherwise, 1 affects a bit. */
3450 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3451 /* Break up DET into pieces. */
3452 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3453 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3454 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3455 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3456 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3457 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3458 int lower_half_easy_p
= 0;
3459 int upper_half_easy_p
= 0;
3461 unsigned int length
= 0;
3466 /* First, see if we can finish with one insn. */
3467 if ((TARGET_H8300H
|| TARGET_H8300S
)
3471 length
= h8300_length_from_table (operands
[1], operands
[2],
3472 &logicw_length_table
);
3476 /* Take care of the lower byte. */
3480 /* Take care of the upper byte. */
3486 if (TARGET_H8300H
|| TARGET_H8300S
)
3488 /* Determine if the lower half can be taken care of in no more
3490 lower_half_easy_p
= (b0
== 0
3492 || (code
!= IOR
&& w0
== 0xffff));
3494 /* Determine if the upper half can be taken care of in no more
3496 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3497 || (code
== AND
&& w1
== 0xff00));
3500 /* Check if doing everything with one insn is no worse than
3501 using multiple insns. */
3502 if ((TARGET_H8300H
|| TARGET_H8300S
)
3503 && w0
!= 0 && w1
!= 0
3504 && !(lower_half_easy_p
&& upper_half_easy_p
)
3505 && !(code
== IOR
&& w1
== 0xffff
3506 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3508 length
= h8300_length_from_table (operands
[1], operands
[2],
3509 &logicl_length_table
);
3513 /* Take care of the lower and upper words individually. For
3514 each word, we try different methods in the order of
3516 1) the special insn (in case of AND or XOR),
3517 2) the word-wise insn, and
3518 3) The byte-wise insn. */
3520 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3524 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3540 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3544 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3547 && (w0
& 0x8000) != 0)
3551 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3557 else if (TARGET_H8300H
|| TARGET_H8300S
)
3578 /* Compute which flag bits are valid after a logical insn. */
3581 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3583 /* Figure out the logical op that we need to perform. */
3584 enum rtx_code code
= GET_CODE (operands
[3]);
3585 /* Pretend that every byte is affected if both operands are registers. */
3586 const unsigned HOST_WIDE_INT intval
=
3587 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3588 /* Always use the full instruction if the
3589 first operand is in memory. It is better
3590 to use define_splits to generate the shorter
3591 sequence where valid. */
3592 && register_operand (operands
[1], VOIDmode
)
3593 ? INTVAL (operands
[2]) : 0x55555555);
3594 /* The determinant of the algorithm. If we perform an AND, 0
3595 affects a bit. Otherwise, 1 affects a bit. */
3596 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3597 /* Break up DET into pieces. */
3598 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3599 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3600 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3601 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3602 int lower_half_easy_p
= 0;
3603 int upper_half_easy_p
= 0;
3604 /* Condition code. */
3605 enum attr_cc cc
= CC_CLOBBER
;
3610 /* First, see if we can finish with one insn. */
3611 if ((TARGET_H8300H
|| TARGET_H8300S
)
3619 if (TARGET_H8300H
|| TARGET_H8300S
)
3621 /* Determine if the lower half can be taken care of in no more
3623 lower_half_easy_p
= (b0
== 0
3625 || (code
!= IOR
&& w0
== 0xffff));
3627 /* Determine if the upper half can be taken care of in no more
3629 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3630 || (code
== AND
&& w1
== 0xff00));
3633 /* Check if doing everything with one insn is no worse than
3634 using multiple insns. */
3635 if ((TARGET_H8300H
|| TARGET_H8300S
)
3636 && w0
!= 0 && w1
!= 0
3637 && !(lower_half_easy_p
&& upper_half_easy_p
)
3638 && !(code
== IOR
&& w1
== 0xffff
3639 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3645 if ((TARGET_H8300H
|| TARGET_H8300S
)
3648 && (w0
& 0x8000) != 0)
3660 /* Expand a conditional branch. */
3663 h8300_expand_branch (rtx operands
[])
3665 enum rtx_code code
= GET_CODE (operands
[0]);
3666 rtx op0
= operands
[1];
3667 rtx op1
= operands
[2];
3668 rtx label
= operands
[3];
3671 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3672 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3674 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3675 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3676 gen_rtx_LABEL_REF (VOIDmode
, label
),
3678 emit_jump_insn (gen_rtx_SET (pc_rtx
, tmp
));
3682 /* Expand a conditional store. */
3685 h8300_expand_store (rtx operands
[])
3687 rtx dest
= operands
[0];
3688 enum rtx_code code
= GET_CODE (operands
[1]);
3689 rtx op0
= operands
[2];
3690 rtx op1
= operands
[3];
3693 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3694 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3696 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3697 emit_insn (gen_rtx_SET (dest
, tmp
));
3702 We devote a fair bit of code to getting efficient shifts since we
3703 can only shift one bit at a time on the H8/300 and H8/300H and only
3704 one or two bits at a time on the H8S.
3706 All shift code falls into one of the following ways of
3709 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3710 when a straight line shift is about the same size or smaller than
3713 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3714 off the bits we don't need. This is used when only a few of the
3715 bits in the original value will survive in the shifted value.
3717 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3718 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3719 shifts can be added if the shift count is slightly more than 8 or
3720 16. This case also includes other oddballs that are not worth
3723 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3725 For each shift count, we try to use code that has no trade-off
3726 between code size and speed whenever possible.
3728 If the trade-off is unavoidable, we try to be reasonable.
3729 Specifically, the fastest version is one instruction longer than
3730 the shortest version, we take the fastest version. We also provide
3731 the use a way to switch back to the shortest version with -Os.
3733 For the details of the shift algorithms for various shift counts,
3734 refer to shift_alg_[qhs]i. */
3736 /* Classify a shift with the given mode and code. OP is the shift amount. */
3738 enum h8sx_shift_type
3739 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3741 if (!TARGET_H8300SX
)
3742 return H8SX_SHIFT_NONE
;
3748 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3749 if (GET_CODE (op
) != CONST_INT
)
3750 return H8SX_SHIFT_BINARY
;
3752 /* Reject out-of-range shift amounts. */
3753 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3754 return H8SX_SHIFT_NONE
;
3756 /* Power-of-2 shifts are effectively unary operations. */
3757 if (exact_log2 (INTVAL (op
)) >= 0)
3758 return H8SX_SHIFT_UNARY
;
3760 return H8SX_SHIFT_BINARY
;
3763 if (op
== const1_rtx
|| op
== const2_rtx
)
3764 return H8SX_SHIFT_UNARY
;
3765 return H8SX_SHIFT_NONE
;
3768 if (GET_CODE (op
) == CONST_INT
3769 && (INTVAL (op
) == 1
3771 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3772 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3773 return H8SX_SHIFT_UNARY
;
3774 return H8SX_SHIFT_NONE
;
3777 return H8SX_SHIFT_NONE
;
3781 /* Return the asm template for a single h8sx shift instruction.
3782 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3783 is the source and OPERANDS[3] is the shift. SUFFIX is the
3784 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3785 prefix for the destination operand. */
3788 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3790 static char buffer
[16];
3793 switch (GET_CODE (operands
[3]))
3809 if (INTVAL (operands
[2]) > 2)
3811 /* This is really a right rotate. */
3812 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3813 - INTVAL (operands
[2]));
3821 if (operands
[2] == const1_rtx
)
3822 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3824 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3828 /* Emit code to do shifts. */
3831 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3833 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3835 case H8SX_SHIFT_BINARY
:
3836 operands
[1] = force_reg (mode
, operands
[1]);
3839 case H8SX_SHIFT_UNARY
:
3842 case H8SX_SHIFT_NONE
:
3846 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3848 /* Need a loop to get all the bits we want - we generate the
3849 code at emit time, but need to allocate a scratch reg now. */
3851 emit_insn (gen_rtx_PARALLEL
3854 gen_rtx_SET (copy_rtx (operands
[0]),
3855 gen_rtx_fmt_ee (code
, mode
,
3856 copy_rtx (operands
[0]), operands
[2])),
3857 gen_rtx_CLOBBER (VOIDmode
,
3858 gen_rtx_SCRATCH (QImode
)))));
3862 /* Symbols of the various modes which can be used as indices. */
3866 QIshift
, HIshift
, SIshift
3869 /* For single bit shift insns, record assembler and what bits of the
3870 condition code are valid afterwards (represented as various CC_FOO
3871 bits, 0 means CC isn't left in a usable state). */
3875 const char *const assembler
;
3876 const enum attr_cc cc_valid
;
3879 /* Assembler instruction shift table.
3881 These tables are used to look up the basic shifts.
3882 They are indexed by cpu, shift_type, and mode. */
3884 static const struct shift_insn shift_one
[2][3][3] =
3890 { "shll\t%X0", CC_SET_ZNV
},
3891 { "add.w\t%T0,%T0", CC_SET_ZN
},
3892 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3894 /* SHIFT_LSHIFTRT */
3896 { "shlr\t%X0", CC_SET_ZNV
},
3897 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3898 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3900 /* SHIFT_ASHIFTRT */
3902 { "shar\t%X0", CC_SET_ZNV
},
3903 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3904 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3911 { "shll.b\t%X0", CC_SET_ZNV
},
3912 { "shll.w\t%T0", CC_SET_ZNV
},
3913 { "shll.l\t%S0", CC_SET_ZNV
}
3915 /* SHIFT_LSHIFTRT */
3917 { "shlr.b\t%X0", CC_SET_ZNV
},
3918 { "shlr.w\t%T0", CC_SET_ZNV
},
3919 { "shlr.l\t%S0", CC_SET_ZNV
}
3921 /* SHIFT_ASHIFTRT */
3923 { "shar.b\t%X0", CC_SET_ZNV
},
3924 { "shar.w\t%T0", CC_SET_ZNV
},
3925 { "shar.l\t%S0", CC_SET_ZNV
}
3930 static const struct shift_insn shift_two
[3][3] =
3934 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3935 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3936 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3938 /* SHIFT_LSHIFTRT */
3940 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3941 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3942 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3944 /* SHIFT_ASHIFTRT */
3946 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3947 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3948 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3952 /* Rotates are organized by which shift they'll be used in implementing.
3953 There's no need to record whether the cc is valid afterwards because
3954 it is the AND insn that will decide this. */
3956 static const char *const rotate_one
[2][3][3] =
3963 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3966 /* SHIFT_LSHIFTRT */
3969 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3972 /* SHIFT_ASHIFTRT */
3975 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3987 /* SHIFT_LSHIFTRT */
3993 /* SHIFT_ASHIFTRT */
4002 static const char *const rotate_two
[3][3] =
4010 /* SHIFT_LSHIFTRT */
4016 /* SHIFT_ASHIFTRT */
4025 /* Shift algorithm. */
4028 /* The number of bits to be shifted by shift1 and shift2. Valid
4029 when ALG is SHIFT_SPECIAL. */
4030 unsigned int remainder
;
4032 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4033 const char *special
;
4035 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4036 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4039 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4040 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4043 /* CC status for SHIFT_INLINE. */
4044 enum attr_cc cc_inline
;
4046 /* CC status for SHIFT_SPECIAL. */
4047 enum attr_cc cc_special
;
4050 static void get_shift_alg (enum shift_type
,
4051 enum shift_mode
, unsigned int,
4052 struct shift_info
*);
4054 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4055 best algorithm for doing the shift. The assembler code is stored
4056 in the pointers in INFO. We achieve the maximum efficiency in most
4057 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4058 SImode in particular have a lot of room to optimize.
4060 We first determine the strategy of the shift algorithm by a table
4061 lookup. If that tells us to use a hand crafted assembly code, we
4062 go into the big switch statement to find what that is. Otherwise,
4063 we resort to a generic way, such as inlining. In either case, the
4064 result is returned through INFO. */
4067 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4068 unsigned int count
, struct shift_info
*info
)
4072 /* Find the target CPU. */
4075 else if (TARGET_H8300S
)
4080 /* Find the shift algorithm. */
4081 info
->alg
= SHIFT_LOOP
;
4085 if (count
< GET_MODE_BITSIZE (QImode
))
4086 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4090 if (count
< GET_MODE_BITSIZE (HImode
))
4091 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4095 if (count
< GET_MODE_BITSIZE (SImode
))
4096 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4103 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4107 info
->remainder
= count
;
4111 /* It is up to the caller to know that looping clobbers cc. */
4112 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4113 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4114 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4118 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4119 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4120 info
->cc_inline
= CC_CLOBBER
;
4124 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4125 info
->remainder
= 0;
4126 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4127 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4128 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4129 info
->cc_special
= CC_CLOBBER
;
4133 /* Here we only deal with SHIFT_SPECIAL. */
4137 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4138 through the entire value. */
4139 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4140 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4150 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4152 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4154 case SHIFT_LSHIFTRT
:
4156 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4158 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4160 case SHIFT_ASHIFTRT
:
4161 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4165 else if ((count
>= 8 && count
<= 13)
4166 || (TARGET_H8300S
&& count
== 14))
4168 info
->remainder
= count
- 8;
4173 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4175 case SHIFT_LSHIFTRT
:
4178 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4179 info
->shift1
= "shlr.b\t%s0";
4180 info
->cc_inline
= CC_SET_ZNV
;
4184 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4185 info
->cc_special
= CC_SET_ZNV
;
4188 case SHIFT_ASHIFTRT
:
4191 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4192 info
->shift1
= "shar.b\t%s0";
4196 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4197 info
->cc_special
= CC_SET_ZNV
;
4202 else if (count
== 14)
4208 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4210 case SHIFT_LSHIFTRT
:
4212 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4214 case SHIFT_ASHIFTRT
:
4216 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4217 else if (TARGET_H8300H
)
4219 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4220 info
->cc_special
= CC_SET_ZNV
;
4222 else /* TARGET_H8300S */
4227 else if (count
== 15)
4232 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4234 case SHIFT_LSHIFTRT
:
4235 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4237 case SHIFT_ASHIFTRT
:
4238 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4245 if (TARGET_H8300
&& count
>= 8 && count
<= 9)
4247 info
->remainder
= count
- 8;
4252 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4254 case SHIFT_LSHIFTRT
:
4255 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4256 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4258 case SHIFT_ASHIFTRT
:
4259 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4263 else if (count
== 8 && !TARGET_H8300
)
4268 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4270 case SHIFT_LSHIFTRT
:
4271 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4273 case SHIFT_ASHIFTRT
:
4274 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4278 else if (count
== 15 && TARGET_H8300
)
4284 case SHIFT_LSHIFTRT
:
4285 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4287 case SHIFT_ASHIFTRT
:
4288 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4292 else if (count
== 15 && !TARGET_H8300
)
4297 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4298 info
->cc_special
= CC_SET_ZNV
;
4300 case SHIFT_LSHIFTRT
:
4301 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4302 info
->cc_special
= CC_SET_ZNV
;
4304 case SHIFT_ASHIFTRT
:
4308 else if ((TARGET_H8300
&& count
>= 16 && count
<= 20)
4309 || (TARGET_H8300H
&& count
>= 16 && count
<= 19)
4310 || (TARGET_H8300S
&& count
>= 16 && count
<= 21))
4312 info
->remainder
= count
- 16;
4317 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4319 info
->shift1
= "add.w\t%e0,%e0";
4321 case SHIFT_LSHIFTRT
:
4324 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4325 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4329 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4330 info
->cc_special
= CC_SET_ZNV
;
4333 case SHIFT_ASHIFTRT
:
4336 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4337 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4341 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4342 info
->cc_special
= CC_SET_ZNV
;
4347 else if (TARGET_H8300
&& count
>= 24 && count
<= 28)
4349 info
->remainder
= count
- 24;
4354 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4355 info
->shift1
= "shll.b\t%z0";
4356 info
->cc_inline
= CC_SET_ZNV
;
4358 case SHIFT_LSHIFTRT
:
4359 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4360 info
->shift1
= "shlr.b\t%w0";
4361 info
->cc_inline
= CC_SET_ZNV
;
4363 case SHIFT_ASHIFTRT
:
4364 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4365 info
->shift1
= "shar.b\t%w0";
4366 info
->cc_inline
= CC_SET_ZNV
;
4370 else if ((TARGET_H8300H
&& count
== 24)
4371 || (TARGET_H8300S
&& count
>= 24 && count
<= 25))
4373 info
->remainder
= count
- 24;
4378 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4380 case SHIFT_LSHIFTRT
:
4381 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4382 info
->cc_special
= CC_SET_ZNV
;
4384 case SHIFT_ASHIFTRT
:
4385 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4386 info
->cc_special
= CC_SET_ZNV
;
4390 else if (!TARGET_H8300
&& count
== 28)
4396 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4398 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4400 case SHIFT_LSHIFTRT
:
4403 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4404 info
->cc_special
= CC_SET_ZNV
;
4407 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4409 case SHIFT_ASHIFTRT
:
4413 else if (!TARGET_H8300
&& count
== 29)
4419 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4421 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4423 case SHIFT_LSHIFTRT
:
4426 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4427 info
->cc_special
= CC_SET_ZNV
;
4431 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4432 info
->cc_special
= CC_SET_ZNV
;
4435 case SHIFT_ASHIFTRT
:
4439 else if (!TARGET_H8300
&& count
== 30)
4445 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4447 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4449 case SHIFT_LSHIFTRT
:
4451 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4453 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4455 case SHIFT_ASHIFTRT
:
4459 else if (count
== 31)
4466 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4468 case SHIFT_LSHIFTRT
:
4469 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4471 case SHIFT_ASHIFTRT
:
4472 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4481 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4482 info
->cc_special
= CC_SET_ZNV
;
4484 case SHIFT_LSHIFTRT
:
4485 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4486 info
->cc_special
= CC_SET_ZNV
;
4488 case SHIFT_ASHIFTRT
:
4489 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4490 info
->cc_special
= CC_SET_ZNV
;
4503 info
->shift2
= NULL
;
4506 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4507 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4510 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4515 if (GET_MODE_BITSIZE (mode
) <= count
)
4518 /* Find out the target CPU. */
4521 else if (TARGET_H8300S
)
4526 /* Find the shift algorithm. */
4530 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4531 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4532 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4536 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4537 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4538 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4542 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4543 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4544 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4551 /* On H8/300H, count == 8 uses a scratch register. */
4552 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4553 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4556 /* Output the assembler code for doing shifts. */
4559 output_a_shift (rtx
*operands
)
4561 static int loopend_lab
;
4562 rtx shift
= operands
[3];
4563 machine_mode mode
= GET_MODE (shift
);
4564 enum rtx_code code
= GET_CODE (shift
);
4565 enum shift_type shift_type
;
4566 enum shift_mode shift_mode
;
4567 struct shift_info info
;
4575 shift_mode
= QIshift
;
4578 shift_mode
= HIshift
;
4581 shift_mode
= SIshift
;
4590 shift_type
= SHIFT_ASHIFTRT
;
4593 shift_type
= SHIFT_LSHIFTRT
;
4596 shift_type
= SHIFT_ASHIFT
;
4602 /* This case must be taken care of by one of the two splitters
4603 that convert a variable shift into a loop. */
4604 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4606 n
= INTVAL (operands
[2]);
4608 /* If the count is negative, make it 0. */
4611 /* If the count is too big, truncate it.
4612 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4613 do the intuitive thing. */
4614 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4615 n
= GET_MODE_BITSIZE (mode
);
4617 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4622 output_asm_insn (info
.special
, operands
);
4628 /* Emit two bit shifts first. */
4629 if (info
.shift2
!= NULL
)
4631 for (; n
> 1; n
-= 2)
4632 output_asm_insn (info
.shift2
, operands
);
4635 /* Now emit one bit shifts for any residual. */
4637 output_asm_insn (info
.shift1
, operands
);
4642 int m
= GET_MODE_BITSIZE (mode
) - n
;
4643 const int mask
= (shift_type
== SHIFT_ASHIFT
4644 ? ((1 << m
) - 1) << n
4648 /* Not all possibilities of rotate are supported. They shouldn't
4649 be generated, but let's watch for 'em. */
4650 gcc_assert (info
.shift1
);
4652 /* Emit two bit rotates first. */
4653 if (info
.shift2
!= NULL
)
4655 for (; m
> 1; m
-= 2)
4656 output_asm_insn (info
.shift2
, operands
);
4659 /* Now single bit rotates for any residual. */
4661 output_asm_insn (info
.shift1
, operands
);
4663 /* Now mask off the high bits. */
4667 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4671 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4672 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4679 output_asm_insn (insn_buf
, operands
);
4684 /* A loop to shift by a "large" constant value.
4685 If we have shift-by-2 insns, use them. */
4686 if (info
.shift2
!= NULL
)
4688 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4689 names_big
[REGNO (operands
[4])]);
4690 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4691 output_asm_insn (info
.shift2
, operands
);
4692 output_asm_insn ("add #0xff,%X4", operands
);
4693 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4695 output_asm_insn (info
.shift1
, operands
);
4699 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4700 names_big
[REGNO (operands
[4])]);
4701 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4702 output_asm_insn (info
.shift1
, operands
);
4703 output_asm_insn ("add #0xff,%X4", operands
);
4704 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4713 /* Count the number of assembly instructions in a string TEMPL. */
4716 h8300_asm_insn_count (const char *templ
)
4718 unsigned int count
= 1;
4720 for (; *templ
; templ
++)
4727 /* Compute the length of a shift insn. */
4730 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4732 rtx shift
= operands
[3];
4733 machine_mode mode
= GET_MODE (shift
);
4734 enum rtx_code code
= GET_CODE (shift
);
4735 enum shift_type shift_type
;
4736 enum shift_mode shift_mode
;
4737 struct shift_info info
;
4738 unsigned int wlength
= 0;
4743 shift_mode
= QIshift
;
4746 shift_mode
= HIshift
;
4749 shift_mode
= SIshift
;
4758 shift_type
= SHIFT_ASHIFTRT
;
4761 shift_type
= SHIFT_LSHIFTRT
;
4764 shift_type
= SHIFT_ASHIFT
;
4770 if (GET_CODE (operands
[2]) != CONST_INT
)
4772 /* Get the assembler code to do one shift. */
4773 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4775 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4779 int n
= INTVAL (operands
[2]);
4781 /* If the count is negative, make it 0. */
4784 /* If the count is too big, truncate it.
4785 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4786 do the intuitive thing. */
4787 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4788 n
= GET_MODE_BITSIZE (mode
);
4790 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4795 wlength
+= h8300_asm_insn_count (info
.special
);
4797 /* Every assembly instruction used in SHIFT_SPECIAL case
4798 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4799 see xor.l, we just pretend that xor.l counts as two insns
4800 so that the insn length will be computed correctly. */
4801 if (strstr (info
.special
, "xor.l") != NULL
)
4809 if (info
.shift2
!= NULL
)
4811 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4815 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4821 int m
= GET_MODE_BITSIZE (mode
) - n
;
4823 /* Not all possibilities of rotate are supported. They shouldn't
4824 be generated, but let's watch for 'em. */
4825 gcc_assert (info
.shift1
);
4827 if (info
.shift2
!= NULL
)
4829 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4833 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4835 /* Now mask off the high bits. */
4845 gcc_assert (!TARGET_H8300
);
4855 /* A loop to shift by a "large" constant value.
4856 If we have shift-by-2 insns, use them. */
4857 if (info
.shift2
!= NULL
)
4859 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4861 wlength
+= h8300_asm_insn_count (info
.shift1
);
4865 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4875 /* Compute which flag bits are valid after a shift insn. */
4878 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4880 rtx shift
= operands
[3];
4881 machine_mode mode
= GET_MODE (shift
);
4882 enum rtx_code code
= GET_CODE (shift
);
4883 enum shift_type shift_type
;
4884 enum shift_mode shift_mode
;
4885 struct shift_info info
;
4891 shift_mode
= QIshift
;
4894 shift_mode
= HIshift
;
4897 shift_mode
= SIshift
;
4906 shift_type
= SHIFT_ASHIFTRT
;
4909 shift_type
= SHIFT_LSHIFTRT
;
4912 shift_type
= SHIFT_ASHIFT
;
4918 /* This case must be taken care of by one of the two splitters
4919 that convert a variable shift into a loop. */
4920 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4922 n
= INTVAL (operands
[2]);
4924 /* If the count is negative, make it 0. */
4927 /* If the count is too big, truncate it.
4928 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4929 do the intuitive thing. */
4930 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4931 n
= GET_MODE_BITSIZE (mode
);
4933 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4938 if (info
.remainder
== 0)
4939 return info
.cc_special
;
4944 return info
.cc_inline
;
4947 /* This case always ends with an and instruction. */
4951 /* A loop to shift by a "large" constant value.
4952 If we have shift-by-2 insns, use them. */
4953 if (info
.shift2
!= NULL
)
4956 return info
.cc_inline
;
4965 /* A rotation by a non-constant will cause a loop to be generated, in
4966 which a rotation by one bit is used. A rotation by a constant,
4967 including the one in the loop, will be taken care of by
4968 output_a_rotate () at the insn emit time. */
4971 expand_a_rotate (rtx operands
[])
4973 rtx dst
= operands
[0];
4974 rtx src
= operands
[1];
4975 rtx rotate_amount
= operands
[2];
4976 machine_mode mode
= GET_MODE (dst
);
4978 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4981 /* We rotate in place. */
4982 emit_move_insn (dst
, src
);
4984 if (GET_CODE (rotate_amount
) != CONST_INT
)
4986 rtx counter
= gen_reg_rtx (QImode
);
4987 rtx_code_label
*start_label
= gen_label_rtx ();
4988 rtx_code_label
*end_label
= gen_label_rtx ();
4990 /* If the rotate amount is less than or equal to 0,
4991 we go out of the loop. */
4992 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4993 QImode
, 0, end_label
);
4995 /* Initialize the loop counter. */
4996 emit_move_insn (counter
, rotate_amount
);
4998 emit_label (start_label
);
5000 /* Rotate by one bit. */
5004 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5007 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5010 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5016 /* Decrement the counter by 1. */
5017 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5019 /* If the loop counter is nonzero, we go back to the beginning
5021 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5024 emit_label (end_label
);
5028 /* Rotate by AMOUNT bits. */
5032 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5035 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5038 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5048 /* Output a rotate insn. */
5051 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5053 rtx dst
= operands
[0];
5054 rtx rotate_amount
= operands
[2];
5055 enum shift_mode rotate_mode
;
5056 enum shift_type rotate_type
;
5057 const char *insn_buf
;
5060 machine_mode mode
= GET_MODE (dst
);
5062 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5067 rotate_mode
= QIshift
;
5070 rotate_mode
= HIshift
;
5073 rotate_mode
= SIshift
;
5082 rotate_type
= SHIFT_ASHIFT
;
5085 rotate_type
= SHIFT_LSHIFTRT
;
5091 amount
= INTVAL (rotate_amount
);
5093 /* Clean up AMOUNT. */
5096 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5097 amount
= GET_MODE_BITSIZE (mode
);
5099 /* Determine the faster direction. After this phase, amount will be
5100 at most a half of GET_MODE_BITSIZE (mode). */
5101 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5103 /* Flip the direction. */
5104 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5106 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5109 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5110 boost up the rotation. */
5111 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5112 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5113 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5114 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5115 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5120 /* This code works on any family. */
5121 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5122 output_asm_insn (insn_buf
, operands
);
5126 /* This code works on the H8/300H and H8S. */
5127 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5128 output_asm_insn (insn_buf
, operands
);
5135 /* Adjust AMOUNT and flip the direction. */
5136 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5138 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5141 /* Output rotate insns. */
5142 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5145 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5147 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5149 for (; amount
>= bits
; amount
-= bits
)
5150 output_asm_insn (insn_buf
, operands
);
5156 /* Compute the length of a rotate insn. */
5159 compute_a_rotate_length (rtx
*operands
)
5161 rtx src
= operands
[1];
5162 rtx amount_rtx
= operands
[2];
5163 machine_mode mode
= GET_MODE (src
);
5165 unsigned int length
= 0;
5167 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5169 amount
= INTVAL (amount_rtx
);
5171 /* Clean up AMOUNT. */
5174 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5175 amount
= GET_MODE_BITSIZE (mode
);
5177 /* Determine the faster direction. After this phase, amount
5178 will be at most a half of GET_MODE_BITSIZE (mode). */
5179 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5180 /* Flip the direction. */
5181 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5183 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5184 boost up the rotation. */
5185 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5186 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5187 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5188 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5189 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5191 /* Adjust AMOUNT and flip the direction. */
5192 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5196 /* We use 2-bit rotations on the H8S. */
5198 amount
= amount
/ 2 + amount
% 2;
5200 /* The H8/300 uses three insns to rotate one bit, taking 6
5202 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5207 /* Fix the operands of a gen_xxx so that it could become a bit
5211 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5213 /* The bit_operand predicate accepts any memory during RTL generation, but
5214 only 'U' memory afterwards, so if this is a MEM operand, we must force
5215 it to be valid for 'U' by reloading the address. */
5218 ? single_zero_operand (operands
[2], QImode
)
5219 : single_one_operand (operands
[2], QImode
))
5221 /* OK to have a memory dest. */
5222 if (GET_CODE (operands
[0]) == MEM
5223 && !satisfies_constraint_U (operands
[0]))
5225 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5226 copy_to_mode_reg (Pmode
,
5227 XEXP (operands
[0], 0)));
5228 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5232 if (GET_CODE (operands
[1]) == MEM
5233 && !satisfies_constraint_U (operands
[1]))
5235 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5236 copy_to_mode_reg (Pmode
,
5237 XEXP (operands
[1], 0)));
5238 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5244 /* Dest and src op must be register. */
5246 operands
[1] = force_reg (QImode
, operands
[1]);
5248 rtx res
= gen_reg_rtx (QImode
);
5252 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5255 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5258 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5263 emit_insn (gen_movqi (operands
[0], res
));
5268 /* Return nonzero if FUNC is an interrupt function as specified
5269 by the "interrupt" attribute. */
5272 h8300_interrupt_function_p (tree func
)
5276 if (TREE_CODE (func
) != FUNCTION_DECL
)
5279 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5280 return a
!= NULL_TREE
;
5283 /* Return nonzero if FUNC is a saveall function as specified by the
5284 "saveall" attribute. */
5287 h8300_saveall_function_p (tree func
)
5291 if (TREE_CODE (func
) != FUNCTION_DECL
)
5294 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5295 return a
!= NULL_TREE
;
5298 /* Return nonzero if FUNC is an OS_Task function as specified
5299 by the "OS_Task" attribute. */
5302 h8300_os_task_function_p (tree func
)
5306 if (TREE_CODE (func
) != FUNCTION_DECL
)
5309 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5310 return a
!= NULL_TREE
;
5313 /* Return nonzero if FUNC is a monitor function as specified
5314 by the "monitor" attribute. */
5317 h8300_monitor_function_p (tree func
)
5321 if (TREE_CODE (func
) != FUNCTION_DECL
)
5324 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5325 return a
!= NULL_TREE
;
5328 /* Return nonzero if FUNC is a function that should be called
5329 through the function vector. */
5332 h8300_funcvec_function_p (tree func
)
5336 if (TREE_CODE (func
) != FUNCTION_DECL
)
5339 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5340 return a
!= NULL_TREE
;
5343 /* Return nonzero if DECL is a variable that's in the eight bit
5347 h8300_eightbit_data_p (tree decl
)
5351 if (TREE_CODE (decl
) != VAR_DECL
)
5354 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5355 return a
!= NULL_TREE
;
5358 /* Return nonzero if DECL is a variable that's in the tiny
5362 h8300_tiny_data_p (tree decl
)
5366 if (TREE_CODE (decl
) != VAR_DECL
)
5369 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5370 return a
!= NULL_TREE
;
5373 /* Generate an 'interrupt_handler' attribute for decls. We convert
5374 all the pragmas to corresponding attributes. */
5377 h8300_insert_attributes (tree node
, tree
*attributes
)
5379 if (TREE_CODE (node
) == FUNCTION_DECL
)
5381 if (pragma_interrupt
)
5383 pragma_interrupt
= 0;
5385 /* Add an 'interrupt_handler' attribute. */
5386 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5394 /* Add an 'saveall' attribute. */
5395 *attributes
= tree_cons (get_identifier ("saveall"),
5401 /* Supported attributes:
5403 interrupt_handler: output a prologue and epilogue suitable for an
5406 saveall: output a prologue and epilogue that saves and restores
5407 all registers except the stack pointer.
5409 function_vector: This function should be called through the
5412 eightbit_data: This variable lives in the 8-bit data area and can
5413 be referenced with 8-bit absolute memory addresses.
5415 tiny_data: This variable lives in the tiny data area and can be
5416 referenced with 16-bit absolute memory references. */
5418 static const struct attribute_spec h8300_attribute_table
[] =
5420 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
5421 affects_type_identity, handler, exclude } */
5422 { "interrupt_handler", 0, 0, true, false, false, false,
5423 h8300_handle_fndecl_attribute
, NULL
},
5424 { "saveall", 0, 0, true, false, false, false,
5425 h8300_handle_fndecl_attribute
, NULL
},
5426 { "OS_Task", 0, 0, true, false, false, false,
5427 h8300_handle_fndecl_attribute
, NULL
},
5428 { "monitor", 0, 0, true, false, false, false,
5429 h8300_handle_fndecl_attribute
, NULL
},
5430 { "function_vector", 0, 0, true, false, false, false,
5431 h8300_handle_fndecl_attribute
, NULL
},
5432 { "eightbit_data", 0, 0, true, false, false, false,
5433 h8300_handle_eightbit_data_attribute
, NULL
},
5434 { "tiny_data", 0, 0, true, false, false, false,
5435 h8300_handle_tiny_data_attribute
, NULL
},
5436 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
5440 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5441 struct attribute_spec.handler. */
5443 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5444 tree args ATTRIBUTE_UNUSED
,
5445 int flags ATTRIBUTE_UNUSED
,
5448 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5450 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5452 *no_add_attrs
= true;
5458 /* Handle an "eightbit_data" attribute; arguments as in
5459 struct attribute_spec.handler. */
5461 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5462 tree args ATTRIBUTE_UNUSED
,
5463 int flags ATTRIBUTE_UNUSED
,
5468 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5470 set_decl_section_name (decl
, ".eight");
5474 warning (OPT_Wattributes
, "%qE attribute ignored",
5476 *no_add_attrs
= true;
5482 /* Handle an "tiny_data" attribute; arguments as in
5483 struct attribute_spec.handler. */
5485 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5486 tree args ATTRIBUTE_UNUSED
,
5487 int flags ATTRIBUTE_UNUSED
,
5492 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5494 set_decl_section_name (decl
, ".tiny");
5498 warning (OPT_Wattributes
, "%qE attribute ignored",
5500 *no_add_attrs
= true;
5506 /* Mark function vectors, and various small data objects. */
5509 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5511 int extra_flags
= 0;
5513 default_encode_section_info (decl
, rtl
, first
);
5515 if (TREE_CODE (decl
) == FUNCTION_DECL
5516 && h8300_funcvec_function_p (decl
))
5517 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5518 else if (TREE_CODE (decl
) == VAR_DECL
5519 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5521 if (h8300_eightbit_data_p (decl
))
5522 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5523 else if (first
&& h8300_tiny_data_p (decl
))
5524 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5528 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5531 /* Output a single-bit extraction. */
5534 output_simode_bld (int bild
, rtx operands
[])
5538 /* Clear the destination register. */
5539 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5541 /* Now output the bit load or bit inverse load, and store it in
5544 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5546 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5548 output_asm_insn ("bst\t#0,%w0", operands
);
5552 /* Determine if we can clear the destination first. */
5553 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5554 && REGNO (operands
[0]) != REGNO (operands
[1]));
5557 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5559 /* Output the bit load or bit inverse load. */
5561 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5563 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5566 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5568 /* Perform the bit store. */
5569 output_asm_insn ("rotxl.l\t%S0", operands
);
5576 /* Delayed-branch scheduling is more effective if we have some idea
5577 how long each instruction will be. Use a shorten_branches pass
5578 to get an initial estimate. */
5583 if (flag_delayed_branch
)
5584 shorten_branches (get_insns ());
5587 #ifndef OBJECT_FORMAT_ELF
5589 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5592 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5593 fprintf (asm_out_file
, "\t.section %s\n", name
);
5595 #endif /* ! OBJECT_FORMAT_ELF */
5597 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5598 which is a special case of the 'R' operand. */
5601 h8300_eightbit_constant_address_p (rtx x
)
5603 /* The ranges of the 8-bit area. */
5604 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5605 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5606 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5607 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5608 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5609 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5611 unsigned HOST_WIDE_INT addr
;
5613 /* We accept symbols declared with eightbit_data. */
5614 if (GET_CODE (x
) == SYMBOL_REF
)
5615 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5617 if (GET_CODE (x
) == CONST
5618 && GET_CODE (XEXP (x
, 0)) == PLUS
5619 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5620 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x
, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0)
5623 if (GET_CODE (x
) != CONST_INT
)
5629 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5630 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5631 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5634 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5635 on H8/300H and H8S. */
5638 h8300_tiny_constant_address_p (rtx x
)
5640 /* The ranges of the 16-bit area. */
5641 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5642 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5643 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5644 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5645 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5646 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5647 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5648 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5650 unsigned HOST_WIDE_INT addr
;
5652 switch (GET_CODE (x
))
5655 /* In the normal mode, any symbol fits in the 16-bit absolute
5656 address range. We also accept symbols declared with
5658 return (TARGET_NORMAL_MODE
5659 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5663 return (TARGET_NORMAL_MODE
5665 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5667 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5670 return TARGET_NORMAL_MODE
;
5678 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5679 locations that can be accessed as a 16-bit word. */
5682 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5684 HOST_WIDE_INT offset1
, offset2
;
5692 else if (GET_CODE (addr1
) == PLUS
5693 && REG_P (XEXP (addr1
, 0))
5694 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5696 reg1
= XEXP (addr1
, 0);
5697 offset1
= INTVAL (XEXP (addr1
, 1));
5707 else if (GET_CODE (addr2
) == PLUS
5708 && REG_P (XEXP (addr2
, 0))
5709 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5711 reg2
= XEXP (addr2
, 0);
5712 offset2
= INTVAL (XEXP (addr2
, 1));
5717 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5718 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5720 && offset1
+ 1 == offset2
)
5726 /* Return nonzero if we have the same comparison insn as I3 two insns
5727 before I3. I3 is assumed to be a comparison insn. */
5730 same_cmp_preceding_p (rtx_insn
*i3
)
5734 /* Make sure we have a sequence of three insns. */
5735 i2
= prev_nonnote_insn (i3
);
5738 i1
= prev_nonnote_insn (i2
);
5742 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5743 && any_condjump_p (i2
) && onlyjump_p (i2
));
5746 /* Return nonzero if we have the same comparison insn as I1 two insns
5747 after I1. I1 is assumed to be a comparison insn. */
5750 same_cmp_following_p (rtx_insn
*i1
)
5754 /* Make sure we have a sequence of three insns. */
5755 i2
= next_nonnote_insn (i1
);
5758 i3
= next_nonnote_insn (i2
);
5762 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5763 && any_condjump_p (i2
) && onlyjump_p (i2
));
5766 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5767 (or pops) N registers. OPERANDS are assumed to be an array of
5771 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5776 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5777 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5778 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5780 return ((REGNO (operands
[0]) == 0
5781 && REGNO (operands
[1]) == 1
5782 && REGNO (operands
[2]) == 2)
5783 || (REGNO (operands
[0]) == 4
5784 && REGNO (operands
[1]) == 5
5785 && REGNO (operands
[2]) == 6));
5788 return (REGNO (operands
[0]) == 0
5789 && REGNO (operands
[1]) == 1
5790 && REGNO (operands
[2]) == 2
5791 && REGNO (operands
[3]) == 3);
5797 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5800 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5801 unsigned int new_reg
)
5803 /* Interrupt functions can only use registers that have already been
5804 saved by the prologue, even if they would normally be
5807 if (h8300_current_function_interrupt_function_p ()
5808 && !df_regs_ever_live_p (new_reg
))
5814 /* Returns true if register REGNO is safe to be allocated as a scratch
5815 register in the current function. */
5818 h8300_hard_regno_scratch_ok (unsigned int regno
)
5820 if (h8300_current_function_interrupt_function_p ()
5821 && ! WORD_REG_USED (regno
))
5828 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5831 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5833 /* Strip off SUBREG if any. */
5834 if (GET_CODE (x
) == SUBREG
)
5839 ? REG_OK_FOR_BASE_STRICT_P (x
)
5840 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5843 /* Return nozero if X is a legitimate address. On the H8/300, a
5844 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5845 CONSTANT_ADDRESS. */
5848 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5850 /* The register indirect addresses like @er0 is always valid. */
5851 if (h8300_rtx_ok_for_base_p (x
, strict
))
5854 if (CONSTANT_ADDRESS_P (x
))
5858 && ( GET_CODE (x
) == PRE_INC
5859 || GET_CODE (x
) == PRE_DEC
5860 || GET_CODE (x
) == POST_INC
5861 || GET_CODE (x
) == POST_DEC
)
5862 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5865 if (GET_CODE (x
) == PLUS
5866 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5867 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5874 /* Implement TARGET_HARD_REGNO_MODE_OK. */
5877 h8300_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5880 /* If an even reg, then anything goes. Otherwise the mode must be
5882 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5884 /* MAC register can only be of SImode. Otherwise, anything
5886 return regno
== MAC_REG
? mode
== SImode
: 1;
5889 /* Implement TARGET_MODES_TIEABLE_P. */
5892 h8300_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
5894 return (mode1
== mode2
5895 || ((mode1
== QImode
5897 || ((TARGET_H8300H
|| TARGET_H8300S
) && mode1
== SImode
))
5900 || ((TARGET_H8300H
|| TARGET_H8300S
) && mode2
== SImode
))));
5903 /* Helper function for the move patterns. Make sure a move is legitimate. */
5906 h8300_move_ok (rtx dest
, rtx src
)
5910 /* Validate that at least one operand is a register. */
5913 if (MEM_P (src
) || CONSTANT_P (src
))
5915 addr
= XEXP (dest
, 0);
5918 else if (MEM_P (src
))
5920 addr
= XEXP (src
, 0);
5926 /* Validate that auto-inc doesn't affect OTHER. */
5927 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5929 addr
= XEXP (addr
, 0);
5931 if (addr
== stack_pointer_rtx
)
5932 return register_no_sp_elim_operand (other
, VOIDmode
);
5934 return !reg_overlap_mentioned_p(other
, addr
);
5937 /* Perform target dependent optabs initialization. */
5939 h8300_init_libfuncs (void)
5941 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5942 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5943 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5944 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5945 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5948 /* Worker function for TARGET_FUNCTION_VALUE.
5950 On the H8 the return value is in R0/R1. */
5953 h8300_function_value (const_tree ret_type
,
5954 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5955 bool outgoing ATTRIBUTE_UNUSED
)
5957 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5960 /* Worker function for TARGET_LIBCALL_VALUE.
5962 On the H8 the return value is in R0/R1. */
5965 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5967 return gen_rtx_REG (mode
, R0_REG
);
5970 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5972 On the H8, R0 is the only register thus used. */
5975 h8300_function_value_regno_p (const unsigned int regno
)
5977 return (regno
== R0_REG
);
5980 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5983 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5985 return (TYPE_MODE (type
) == BLKmode
5986 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5989 /* We emit the entire trampoline here. Depending on the pointer size,
5990 we use a different trampoline.
5994 1 0000 7903xxxx mov.w #0x1234,r3
5995 2 0004 5A00xxxx jmp @0x1234
6000 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6001 3 0006 5Axxxxxx jmp @0x123456
6006 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6008 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6011 if (Pmode
== HImode
)
6013 mem
= adjust_address (m_tramp
, HImode
, 0);
6014 emit_move_insn (mem
, GEN_INT (0x7903));
6015 mem
= adjust_address (m_tramp
, Pmode
, 2);
6016 emit_move_insn (mem
, cxt
);
6017 mem
= adjust_address (m_tramp
, HImode
, 4);
6018 emit_move_insn (mem
, GEN_INT (0x5a00));
6019 mem
= adjust_address (m_tramp
, Pmode
, 6);
6020 emit_move_insn (mem
, fnaddr
);
6026 mem
= adjust_address (m_tramp
, HImode
, 0);
6027 emit_move_insn (mem
, GEN_INT (0x7a03));
6028 mem
= adjust_address (m_tramp
, Pmode
, 2);
6029 emit_move_insn (mem
, cxt
);
6031 tem
= copy_to_reg (fnaddr
);
6032 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6033 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6034 mem
= adjust_address (m_tramp
, SImode
, 6);
6035 emit_move_insn (mem
, tem
);
6039 /* Implement PUSH_ROUNDING.
6041 On the H8/300, @-sp really pushes a byte if you ask it to - but that's
6042 dangerous, so we claim that it always pushes a word, then we catch
6043 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
6045 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4
6046 and doing a similar thing. */
6049 h8300_push_rounding (poly_int64 bytes
)
6051 return ((bytes
+ PARM_BOUNDARY
/ 8 - 1) & (-PARM_BOUNDARY
/ 8));
6054 /* Initialize the GCC target structure. */
6055 #undef TARGET_ATTRIBUTE_TABLE
6056 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6058 #undef TARGET_ASM_ALIGNED_HI_OP
6059 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6061 #undef TARGET_ASM_FILE_START
6062 #define TARGET_ASM_FILE_START h8300_file_start
6063 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6064 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6066 #undef TARGET_ASM_FILE_END
6067 #define TARGET_ASM_FILE_END h8300_file_end
6069 #undef TARGET_PRINT_OPERAND
6070 #define TARGET_PRINT_OPERAND h8300_print_operand
6071 #undef TARGET_PRINT_OPERAND_ADDRESS
6072 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6073 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6074 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6076 #undef TARGET_ENCODE_SECTION_INFO
6077 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6079 #undef TARGET_INSERT_ATTRIBUTES
6080 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6082 #undef TARGET_REGISTER_MOVE_COST
6083 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6085 #undef TARGET_RTX_COSTS
6086 #define TARGET_RTX_COSTS h8300_rtx_costs
6088 #undef TARGET_INIT_LIBFUNCS
6089 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6091 #undef TARGET_FUNCTION_VALUE
6092 #define TARGET_FUNCTION_VALUE h8300_function_value
6094 #undef TARGET_LIBCALL_VALUE
6095 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6097 #undef TARGET_FUNCTION_VALUE_REGNO_P
6098 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6100 #undef TARGET_RETURN_IN_MEMORY
6101 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6103 #undef TARGET_FUNCTION_ARG
6104 #define TARGET_FUNCTION_ARG h8300_function_arg
6106 #undef TARGET_FUNCTION_ARG_ADVANCE
6107 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6109 #undef TARGET_MACHINE_DEPENDENT_REORG
6110 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6112 #undef TARGET_HARD_REGNO_SCRATCH_OK
6113 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6115 #undef TARGET_HARD_REGNO_MODE_OK
6116 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
6118 #undef TARGET_MODES_TIEABLE_P
6119 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
6122 #define TARGET_LRA_P hook_bool_void_false
6124 #undef TARGET_LEGITIMATE_ADDRESS_P
6125 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6127 #undef TARGET_CAN_ELIMINATE
6128 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6130 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6131 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6133 #undef TARGET_TRAMPOLINE_INIT
6134 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6136 #undef TARGET_OPTION_OVERRIDE
6137 #define TARGET_OPTION_OVERRIDE h8300_option_override
6139 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6140 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6142 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
6143 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
6145 struct gcc_target targetm
= TARGET_INITIALIZER
;