gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2018 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #define IN_TARGET_CODE 1
  21
  22 #include "config.h"
  23 #include "system.h"
  24 #include "coretypes.h"
  25 #include "tm.h"
  26
  27 const char *host_detect_local_cpu (int argc, const char **argv);
  28
  29 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  30 #include "cpuid.h"
  31
  32 struct cache_desc
  33 {
  34   unsigned sizekb;
  35   unsigned assoc;
  36   unsigned line;
  37 };
  38
  39 /* Returns command line parameters that describe size and
  40    cache line size of the processor caches.  */
  41
  42 static char *
  43 describe_cache (struct cache_desc level1, struct cache_desc level2)
  44 {
  45   char size[100], line[100], size2[100];
  46
  47   /* At the moment, gcc does not use the information
  48      about the associativity of the cache.  */
  49
  50   snprintf (size, sizeof (size),
  51             "--param l1-cache-size=%u ", level1.sizekb);
  52   snprintf (line, sizeof (line),
  53             "--param l1-cache-line-size=%u ", level1.line);
  54
  55   snprintf (size2, sizeof (size2),
  56             "--param l2-cache-size=%u ", level2.sizekb);
  57
  58   return concat (size, line, size2, NULL);
  59 }
  60
  61 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  62
  63 static void
  64 detect_l2_cache (struct cache_desc *level2)
  65 {
  66   unsigned eax, ebx, ecx, edx;
  67   unsigned assoc;
  68
  69   __cpuid (0x80000006, eax, ebx, ecx, edx);
  70
  71   level2->sizekb = (ecx >> 16) & 0xffff;
  72   level2->line = ecx & 0xff;
  73
  74   assoc = (ecx >> 12) & 0xf;
  75   if (assoc == 6)
  76     assoc = 8;
  77   else if (assoc == 8)
  78     assoc = 16;
  79   else if (assoc >= 0xa && assoc <= 0xc)
  80     assoc = 32 + (assoc - 0xa) * 16;
  81   else if (assoc >= 0xd && assoc <= 0xe)
  82     assoc = 96 + (assoc - 0xd) * 32;
  83
  84   level2->assoc = assoc;
  85 }
  86
  87 /* Returns the description of caches for an AMD processor.  */
  88
  89 static const char *
  90 detect_caches_amd (unsigned max_ext_level)
  91 {
  92   unsigned eax, ebx, ecx, edx;
  93
  94   struct cache_desc level1, level2 = {0, 0, 0};
  95
  96   if (max_ext_level < 0x80000005)
  97     return "";
  98
  99   __cpuid (0x80000005, eax, ebx, ecx, edx);
 100
 101   level1.sizekb = (ecx >> 24) & 0xff;
 102   level1.assoc = (ecx >> 16) & 0xff;
 103   level1.line = ecx & 0xff;
 104
 105   if (max_ext_level >= 0x80000006)
 106     detect_l2_cache (&level2);
 107
 108   return describe_cache (level1, level2);
 109 }
 110
 111 /* Decodes the size, the associativity and the cache line size of
 112    L1/L2 caches of an Intel processor.  Values are based on
 113    "Intel Processor Identification and the CPUID Instruction"
 114    [Application Note 485], revision -032, December 2007.  */
 115
 116 static void
 117 decode_caches_intel (unsigned reg, bool xeon_mp,
 118                      struct cache_desc *level1, struct cache_desc *level2)
 119 {
 120   int i;
 121
 122   for (i = 24; i >= 0; i -= 8)
 123     switch ((reg >> i) & 0xff)
 124       {
 125       case 0x0a:
 126         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 127         break;
 128       case 0x0c:
 129         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 130         break;
 131       case 0x0d:
 132         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 133         break;
 134       case 0x0e:
 135         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 136         break;
 137       case 0x21:
 138         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 139         break;
 140       case 0x24:
 141         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 142         break;
 143       case 0x2c:
 144         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 145         break;
 146       case 0x39:
 147         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 148         break;
 149       case 0x3a:
 150         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 151         break;
 152       case 0x3b:
 153         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 154         break;
 155       case 0x3c:
 156         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 157         break;
 158       case 0x3d:
 159         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 160         break;
 161       case 0x3e:
 162         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 163         break;
 164       case 0x41:
 165         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 166         break;
 167       case 0x42:
 168         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 169         break;
 170       case 0x43:
 171         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 172         break;
 173       case 0x44:
 174         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 175         break;
 176       case 0x45:
 177         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 178         break;
 179       case 0x48:
 180         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 181         break;
 182       case 0x49:
 183         if (xeon_mp)
 184           break;
 185         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 186         break;
 187       case 0x4e:
 188         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 189         break;
 190       case 0x60:
 191         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 192         break;
 193       case 0x66:
 194         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 195         break;
 196       case 0x67:
 197         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 198         break;
 199       case 0x68:
 200         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 201         break;
 202       case 0x78:
 203         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 204         break;
 205       case 0x79:
 206         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 207         break;
 208       case 0x7a:
 209         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 210         break;
 211       case 0x7b:
 212         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 213         break;
 214       case 0x7c:
 215         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 216         break;
 217       case 0x7d:
 218         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 219         break;
 220       case 0x7f:
 221         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 222         break;
 223       case 0x80:
 224         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 225         break;
 226       case 0x82:
 227         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 228         break;
 229       case 0x83:
 230         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 231         break;
 232       case 0x84:
 233         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 234         break;
 235       case 0x85:
 236         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 237         break;
 238       case 0x86:
 239         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 240         break;
 241       case 0x87:
 242         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 243
 244       default:
 245         break;
 246       }
 247 }
 248
 249 /* Detect cache parameters using CPUID function 2.  */
 250
 251 static void
 252 detect_caches_cpuid2 (bool xeon_mp,
 253                       struct cache_desc *level1, struct cache_desc *level2)
 254 {
 255   unsigned regs[4];
 256   int nreps, i;
 257
 258   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 259
 260   nreps = regs[0] & 0x0f;
 261   regs[0] &= ~0x0f;
 262
 263   while (--nreps >= 0)
 264     {
 265       for (i = 0; i < 4; i++)
 266         if (regs[i] && !((regs[i] >> 31) & 1))
 267           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 268
 269       if (nreps)
 270         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 271     }
 272 }
 273
 274 /* Detect cache parameters using CPUID function 4. This
 275    method doesn't require hardcoded tables.  */
 276
 277 enum cache_type
 278 {
 279   CACHE_END = 0,
 280   CACHE_DATA = 1,
 281   CACHE_INST = 2,
 282   CACHE_UNIFIED = 3
 283 };
 284
 285 static void
 286 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 287                       struct cache_desc *level3)
 288 {
 289   struct cache_desc *cache;
 290
 291   unsigned eax, ebx, ecx, edx;
 292   int count;
 293
 294   for (count = 0;; count++)
 295     {
 296       __cpuid_count(4, count, eax, ebx, ecx, edx);
 297       switch (eax & 0x1f)
 298         {
 299         case CACHE_END:
 300           return;
 301         case CACHE_DATA:
 302         case CACHE_UNIFIED:
 303           {
 304             switch ((eax >> 5) & 0x07)
 305               {
 306               case 1:
 307                 cache = level1;
 308                 break;
 309               case 2:
 310                 cache = level2;
 311                 break;
 312               case 3:
 313                 cache = level3;
 314                 break;
 315               default:
 316                 cache = NULL;
 317               }
 318
 319             if (cache)
 320               {
 321                 unsigned sets = ecx + 1;
 322                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 323
 324                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 325                 cache->line = (ebx & 0x0fff) + 1;
 326
 327                 cache->sizekb = (cache->assoc * part
 328                                  * cache->line * sets) / 1024;
 329               }
 330           }
 331         default:
 332           break;
 333         }
 334     }
 335 }
 336
 337 /* Returns the description of caches for an Intel processor.  */
 338
 339 static const char *
 340 detect_caches_intel (bool xeon_mp, unsigned max_level,
 341                      unsigned max_ext_level, unsigned *l2sizekb)
 342 {
 343   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 344
 345   if (max_level >= 4)
 346     detect_caches_cpuid4 (&level1, &level2, &level3);
 347   else if (max_level >= 2)
 348     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 349   else
 350     return "";
 351
 352   if (level1.sizekb == 0)
 353     return "";
 354
 355   /* Let the L3 replace the L2. This assumes inclusive caches
 356      and single threaded program for now. */
 357   if (level3.sizekb)
 358     level2 = level3;
 359
 360   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 361      method if other methods fail to provide L2 cache parameters.  */
 362   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 363     detect_l2_cache (&level2);
 364
 365   *l2sizekb = level2.sizekb;
 366
 367   return describe_cache (level1, level2);
 368 }
 369
 370 /* This will be called by the spec parser in gcc.c when it sees
 371    a %:local_cpu_detect(args) construct.  Currently it will be called
 372    with either "arch" or "tune" as argument depending on if -march=native
 373    or -mtune=native is to be substituted.
 374
 375    It returns a string containing new command line parameters to be
 376    put at the place of the above two options, depending on what CPU
 377    this is executed.  E.g. "-march=k8" on an AMD64 machine
 378    for -march=native.
 379
 380    ARGC and ARGV are set depending on the actual arguments given
 381    in the spec.  */
 382
 383 const char *host_detect_local_cpu (int argc, const char **argv)
 384 {
 385   enum processor_type processor = PROCESSOR_I386;
 386   const char *cpu = "i386";
 387
 388   const char *cache = "";
 389   const char *options = "";
 390
 391   unsigned int eax, ebx, ecx, edx;
 392
 393   unsigned int max_level, ext_level;
 394
 395   unsigned int vendor;
 396   unsigned int model, family;
 397
 398   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 399   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 400
 401   /* Extended features */
 402   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 403   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 404   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 405   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 406   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 407   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 408   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 409   unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0;
 410   unsigned int has_pconfig = 0, has_wbnoinvd = 0;
 411   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 412   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 413   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 414   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 415   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 416   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 417   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 418   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 419   unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0, has_rdpid = 0;
 420   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
 421   unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
 422   unsigned int has_avx512bitalg = 0;
 423   unsigned int has_shstk = 0;
 424   unsigned int has_avx512vnni = 0, has_vaes = 0;
 425   unsigned int has_vpclmulqdq = 0;
 426   unsigned int has_movdiri = 0, has_movdir64b = 0;
 427   unsigned int has_waitpkg = 0;
 428   unsigned int has_cldemote = 0;
 429
 430   bool arch;
 431
 432   unsigned int l2sizekb = 0;
 433
 434   if (argc < 1)
 435     return NULL;
 436
 437   arch = !strcmp (argv[0], "arch");
 438
 439   if (!arch && strcmp (argv[0], "tune"))
 440     return NULL;
 441
 442   max_level = __get_cpuid_max (0, &vendor);
 443   if (max_level < 1)
 444     goto done;
 445
 446   __cpuid (1, eax, ebx, ecx, edx);
 447
 448   model = (eax >> 4) & 0x0f;
 449   family = (eax >> 8) & 0x0f;
 450   if (vendor == signature_INTEL_ebx
 451       || vendor == signature_AMD_ebx)
 452     {
 453       unsigned int extended_model, extended_family;
 454
 455       extended_model = (eax >> 12) & 0xf0;
 456       extended_family = (eax >> 20) & 0xff;
 457       if (family == 0x0f)
 458         {
 459           family += extended_family;
 460           model += extended_model;
 461         }
 462       else if (family == 0x06)
 463         model += extended_model;
 464     }
 465
 466   has_sse3 = ecx & bit_SSE3;
 467   has_ssse3 = ecx & bit_SSSE3;
 468   has_sse4_1 = ecx & bit_SSE4_1;
 469   has_sse4_2 = ecx & bit_SSE4_2;
 470   has_avx = ecx & bit_AVX;
 471   has_osxsave = ecx & bit_OSXSAVE;
 472   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 473   has_movbe = ecx & bit_MOVBE;
 474   has_popcnt = ecx & bit_POPCNT;
 475   has_aes = ecx & bit_AES;
 476   has_pclmul = ecx & bit_PCLMUL;
 477   has_fma = ecx & bit_FMA;
 478   has_f16c = ecx & bit_F16C;
 479   has_rdrnd = ecx & bit_RDRND;
 480   has_xsave = ecx & bit_XSAVE;
 481
 482   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 483   has_cmov = edx & bit_CMOV;
 484   has_mmx = edx & bit_MMX;
 485   has_fxsr = edx & bit_FXSAVE;
 486   has_sse = edx & bit_SSE;
 487   has_sse2 = edx & bit_SSE2;
 488
 489   if (max_level >= 7)
 490     {
 491       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 492
 493       has_bmi = ebx & bit_BMI;
 494       has_sgx = ebx & bit_SGX;
 495       has_hle = ebx & bit_HLE;
 496       has_rtm = ebx & bit_RTM;
 497       has_avx2 = ebx & bit_AVX2;
 498       has_bmi2 = ebx & bit_BMI2;
 499       has_fsgsbase = ebx & bit_FSGSBASE;
 500       has_rdseed = ebx & bit_RDSEED;
 501       has_adx = ebx & bit_ADX;
 502       has_avx512f = ebx & bit_AVX512F;
 503       has_avx512er = ebx & bit_AVX512ER;
 504       has_avx512pf = ebx & bit_AVX512PF;
 505       has_avx512cd = ebx & bit_AVX512CD;
 506       has_sha = ebx & bit_SHA;
 507       has_clflushopt = ebx & bit_CLFLUSHOPT;
 508       has_clwb = ebx & bit_CLWB;
 509       has_avx512dq = ebx & bit_AVX512DQ;
 510       has_avx512bw = ebx & bit_AVX512BW;
 511       has_avx512vl = ebx & bit_AVX512VL;
 512       has_avx512ifma = ebx & bit_AVX512IFMA;
 513
 514       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 515       has_avx512vbmi = ecx & bit_AVX512VBMI;
 516       has_pku = ecx & bit_OSPKE;
 517       has_avx512vbmi2 = ecx & bit_AVX512VBMI2;
 518       has_avx512vnni = ecx & bit_AVX512VNNI;
 519       has_rdpid = ecx & bit_RDPID;
 520       has_gfni = ecx & bit_GFNI;
 521       has_vaes = ecx & bit_VAES;
 522       has_vpclmulqdq = ecx & bit_VPCLMULQDQ;
 523       has_avx512bitalg = ecx & bit_AVX512BITALG;
 524       has_movdiri = ecx & bit_MOVDIRI;
 525       has_movdir64b = ecx & bit_MOVDIR64B;
 526       has_cldemote = ecx & bit_CLDEMOTE;
 527
 528       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
 529       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
 530
 531       has_shstk = ecx & bit_SHSTK;
 532       has_pconfig = edx & bit_PCONFIG;
 533       has_waitpkg = ecx & bit_WAITPKG;
 534     }
 535
 536   if (max_level >= 13)
 537     {
 538       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 539
 540       has_xsaveopt = eax & bit_XSAVEOPT;
 541       has_xsavec = eax & bit_XSAVEC;
 542       has_xsaves = eax & bit_XSAVES;
 543     }
 544
 545   /* Check cpuid level of extended features.  */
 546   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 547
 548   if (ext_level >= 0x80000001)
 549     {
 550       __cpuid (0x80000001, eax, ebx, ecx, edx);
 551
 552       has_lahf_lm = ecx & bit_LAHF_LM;
 553       has_sse4a = ecx & bit_SSE4a;
 554       has_abm = ecx & bit_ABM;
 555       has_lwp = ecx & bit_LWP;
 556       has_fma4 = ecx & bit_FMA4;
 557       has_xop = ecx & bit_XOP;
 558       has_tbm = ecx & bit_TBM;
 559       has_lzcnt = ecx & bit_LZCNT;
 560       has_prfchw = ecx & bit_PRFCHW;
 561
 562       has_longmode = edx & bit_LM;
 563       has_3dnowp = edx & bit_3DNOWP;
 564       has_3dnow = edx & bit_3DNOW;
 565       has_mwaitx = ecx & bit_MWAITX;
 566     }
 567
 568   if (ext_level >= 0x80000008)
 569     {
 570       __cpuid (0x80000008, eax, ebx, ecx, edx);
 571       has_clzero = ebx & bit_CLZERO;
 572       has_wbnoinvd = ebx & bit_WBNOINVD;
 573     }
 574
 575   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 576 #define XCR_XFEATURE_ENABLED_MASK       0x0
 577 #define XSTATE_FP                       0x1
 578 #define XSTATE_SSE                      0x2
 579 #define XSTATE_YMM                      0x4
 580 #define XSTATE_OPMASK                   0x20
 581 #define XSTATE_ZMM                      0x40
 582 #define XSTATE_HI_ZMM                   0x80
 583
 584 #define XCR_AVX_ENABLED_MASK \
 585   (XSTATE_SSE | XSTATE_YMM)
 586 #define XCR_AVX512F_ENABLED_MASK \
 587   (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
 588
 589   if (has_osxsave)
 590     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 591          : "=a" (eax), "=d" (edx)
 592          : "c" (XCR_XFEATURE_ENABLED_MASK));
 593   else
 594     eax = 0;
 595
 596   /* Check if AVX registers are supported.  */
 597   if ((eax & XCR_AVX_ENABLED_MASK) != XCR_AVX_ENABLED_MASK)
 598     {
 599       has_avx = 0;
 600       has_avx2 = 0;
 601       has_fma = 0;
 602       has_fma4 = 0;
 603       has_f16c = 0;
 604       has_xop = 0;
 605       has_xsave = 0;
 606       has_xsaveopt = 0;
 607       has_xsaves = 0;
 608       has_xsavec = 0;
 609     }
 610
 611   /* Check if AVX512F registers are supported.  */
 612   if ((eax & XCR_AVX512F_ENABLED_MASK) != XCR_AVX512F_ENABLED_MASK)
 613     {
 614       has_avx512f = 0;
 615       has_avx512er = 0;
 616       has_avx512pf = 0;
 617       has_avx512cd = 0;
 618       has_avx512dq = 0;
 619       has_avx512bw = 0;
 620       has_avx512vl = 0;
 621     }
 622
 623   if (!arch)
 624     {
 625       if (vendor == signature_AMD_ebx
 626           || vendor == signature_CENTAUR_ebx
 627           || vendor == signature_CYRIX_ebx
 628           || vendor == signature_NSC_ebx)
 629         cache = detect_caches_amd (ext_level);
 630       else if (vendor == signature_INTEL_ebx)
 631         {
 632           bool xeon_mp = (family == 15 && model == 6);
 633           cache = detect_caches_intel (xeon_mp, max_level,
 634                                        ext_level, &l2sizekb);
 635         }
 636     }
 637
 638   if (vendor == signature_AMD_ebx)
 639     {
 640       unsigned int name;
 641
 642       /* Detect geode processor by its processor signature.  */
 643       if (ext_level >= 0x80000002)
 644         __cpuid (0x80000002, name, ebx, ecx, edx);
 645       else
 646         name = 0;
 647
 648       if (name == signature_NSC_ebx)
 649         processor = PROCESSOR_GEODE;
 650       else if (has_movbe && family == 22)
 651         processor = PROCESSOR_BTVER2;
 652       else if (has_clzero)
 653         processor = PROCESSOR_ZNVER1;
 654       else if (has_avx2)
 655         processor = PROCESSOR_BDVER4;
 656       else if (has_xsaveopt)
 657         processor = PROCESSOR_BDVER3;
 658       else if (has_bmi)
 659         processor = PROCESSOR_BDVER2;
 660       else if (has_xop)
 661         processor = PROCESSOR_BDVER1;
 662       else if (has_sse4a && has_ssse3)
 663         processor = PROCESSOR_BTVER1;
 664       else if (has_sse4a)
 665         processor = PROCESSOR_AMDFAM10;
 666       else if (has_sse2 || has_longmode)
 667         processor = PROCESSOR_K8;
 668       else if (has_3dnowp && family == 6)
 669         processor = PROCESSOR_ATHLON;
 670       else if (has_mmx)
 671         processor = PROCESSOR_K6;
 672       else
 673         processor = PROCESSOR_PENTIUM;
 674     }
 675   else if (vendor == signature_CENTAUR_ebx)
 676     {
 677       processor = PROCESSOR_GENERIC;
 678
 679       switch (family)
 680         {
 681         default:
 682           /* We have no idea.  */
 683           break;
 684
 685         case 5:
 686           if (has_3dnow || has_mmx)
 687             processor = PROCESSOR_I486;
 688           break;
 689
 690         case 6:
 691           if (has_longmode)
 692             processor = PROCESSOR_K8;
 693           else if (model >= 9)
 694             processor = PROCESSOR_PENTIUMPRO;
 695           else if (model >= 6)
 696             processor = PROCESSOR_I486;
 697         }
 698     }
 699   else
 700     {
 701       switch (family)
 702         {
 703         case 4:
 704           processor = PROCESSOR_I486;
 705           break;
 706         case 5:
 707           processor = PROCESSOR_PENTIUM;
 708           break;
 709         case 6:
 710           processor = PROCESSOR_PENTIUMPRO;
 711           break;
 712         case 15:
 713           processor = PROCESSOR_PENTIUM4;
 714           break;
 715         default:
 716           /* We have no idea.  */
 717           processor = PROCESSOR_GENERIC;
 718         }
 719     }
 720
 721   switch (processor)
 722     {
 723     case PROCESSOR_I386:
 724       /* Default.  */
 725       break;
 726     case PROCESSOR_I486:
 727       if (arch && vendor == signature_CENTAUR_ebx)
 728         {
 729           if (model >= 6)
 730             cpu = "c3";
 731           else if (has_3dnow)
 732             cpu = "winchip2";
 733           else
 734             /* Assume WinChip C6.  */
 735             cpu = "winchip-c6";
 736         }
 737       else
 738         cpu = "i486";
 739       break;
 740     case PROCESSOR_PENTIUM:
 741       if (arch && has_mmx)
 742         cpu = "pentium-mmx";
 743       else
 744         cpu = "pentium";
 745       break;
 746     case PROCESSOR_PENTIUMPRO:
 747       switch (model)
 748         {
 749         case 0x1c:
 750         case 0x26:
 751           /* Bonnell.  */
 752           cpu = "bonnell";
 753           break;
 754         case 0x37:
 755         case 0x4a:
 756         case 0x4d:
 757         case 0x5a:
 758         case 0x5d:
 759           /* Silvermont.  */
 760           cpu = "silvermont";
 761           break;
 762         case 0x5c:
 763         case 0x5f:
 764           /* Goldmont.  */
 765           cpu = "goldmont";
 766           break;
 767         case 0x7a:
 768           /* Goldmont Plus.  */
 769           cpu = "goldmont-plus";
 770           break;
 771         case 0x0f:
 772           /* Merom.  */
 773         case 0x17:
 774         case 0x1d:
 775           /* Penryn.  */
 776           cpu = "core2";
 777           break;
 778         case 0x1a:
 779         case 0x1e:
 780         case 0x1f:
 781         case 0x2e:
 782           /* Nehalem.  */
 783           cpu = "nehalem";
 784           break;
 785         case 0x25:
 786         case 0x2c:
 787         case 0x2f:
 788           /* Westmere.  */
 789           cpu = "westmere";
 790           break;
 791         case 0x2a:
 792         case 0x2d:
 793           /* Sandy Bridge.  */
 794           cpu = "sandybridge";
 795           break;
 796         case 0x3a:
 797         case 0x3e:
 798           /* Ivy Bridge.  */
 799           cpu = "ivybridge";
 800           break;
 801         case 0x3c:
 802         case 0x3f:
 803         case 0x45:
 804         case 0x46:
 805           /* Haswell.  */
 806           cpu = "haswell";
 807           break;
 808         case 0x3d:
 809         case 0x47:
 810         case 0x4f:
 811         case 0x56:
 812           /* Broadwell.  */
 813           cpu = "broadwell";
 814           break;
 815         case 0x4e:
 816         case 0x5e:
 817           /* Skylake.  */
 818         case 0x8e:
 819         case 0x9e:
 820           /* Kaby Lake.  */
 821           cpu = "skylake";
 822           break;
 823         case 0x55:
 824           /* Skylake with AVX-512.  */
 825           cpu = "skylake-avx512";
 826           break;
 827         case 0x57:
 828           /* Knights Landing.  */
 829           cpu = "knl";
 830           break;
 831         case 0x66:
 832           /* Cannon Lake.  */
 833           cpu = "cannonlake";
 834           break;
 835         case 0x85:
 836           /* Knights Mill.  */
 837           cpu = "knm";
 838           break;
 839         default:
 840           if (arch)
 841             {
 842               /* This is unknown family 0x6 CPU.  */
 843               /* Assume Ice Lake Server.  */
 844               if (has_wbnoinvd)
 845                 cpu = "icelake-server";
 846               /* Assume Ice Lake.  */
 847               else if (has_gfni)
 848                 cpu = "icelake-client";
 849               /* Assume Cannon Lake.  */
 850               else if (has_avx512vbmi)
 851                 cpu = "cannonlake";
 852               /* Assume Knights Mill.  */
 853               else if (has_avx5124vnniw)
 854                 cpu = "knm";
 855               /* Assume Knights Landing.  */
 856               else if (has_avx512er)
 857                 cpu = "knl";
 858               /* Assume Skylake with AVX-512.  */
 859               else if (has_avx512f)
 860                 cpu = "skylake-avx512";
 861               /* Assume Skylake.  */
 862               else if (has_clflushopt)
 863                 cpu = "skylake";
 864               /* Assume Broadwell.  */
 865               else if (has_adx)
 866                 cpu = "broadwell";
 867               else if (has_avx2)
 868                 /* Assume Haswell.  */
 869                 cpu = "haswell";
 870               else if (has_avx)
 871                 /* Assume Sandy Bridge.  */
 872                 cpu = "sandybridge";
 873               else if (has_sse4_2)
 874                 {
 875                   if (has_sgx)
 876                     /* Assume Goldmont Plus.  */
 877                     cpu = "goldmont-plus";
 878                   else if (has_xsave)
 879                     /* Assume Goldmont.  */
 880                     cpu = "goldmont";
 881                   else if (has_movbe)
 882                     /* Assume Silvermont.  */
 883                     cpu = "silvermont";
 884                   else
 885                     /* Assume Nehalem.  */
 886                     cpu = "nehalem";
 887                 }
 888               else if (has_ssse3)
 889                 {
 890                   if (has_movbe)
 891                     /* Assume Bonnell.  */
 892                     cpu = "bonnell";
 893                   else
 894                     /* Assume Core 2.  */
 895                     cpu = "core2";
 896                 }
 897               else if (has_longmode)
 898                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 899                    -march=native would be unusable for 64-bit compilations,
 900                    as all the CPUs below are 32-bit only.  */
 901                 cpu = "x86-64";
 902               else if (has_sse3)
 903                 {
 904                   if (vendor == signature_CENTAUR_ebx)
 905                     /* C7 / Eden "Esther" */
 906                     cpu = "c7";
 907                   else
 908                     /* It is Core Duo.  */
 909                     cpu = "pentium-m";
 910                 }
 911               else if (has_sse2)
 912                 /* It is Pentium M.  */
 913                 cpu = "pentium-m";
 914               else if (has_sse)
 915                 {
 916                   if (vendor == signature_CENTAUR_ebx)
 917                     {
 918                       if (model >= 9)
 919                         /* Eden "Nehemiah" */
 920                         cpu = "nehemiah";
 921                       else
 922                         cpu = "c3-2";
 923                     }
 924                   else
 925                     /* It is Pentium III.  */
 926                     cpu = "pentium3";
 927                 }
 928               else if (has_mmx)
 929                 /* It is Pentium II.  */
 930                 cpu = "pentium2";
 931               else
 932                 /* Default to Pentium Pro.  */
 933                 cpu = "pentiumpro";
 934             }
 935           else
 936             /* For -mtune, we default to -mtune=generic.  */
 937             cpu = "generic";
 938           break;
 939         }
 940       break;
 941     case PROCESSOR_PENTIUM4:
 942       if (has_sse3)
 943         {
 944           if (has_longmode)
 945             cpu = "nocona";
 946           else
 947             cpu = "prescott";
 948         }
 949       else
 950         cpu = "pentium4";
 951       break;
 952     case PROCESSOR_GEODE:
 953       cpu = "geode";
 954       break;
 955     case PROCESSOR_K6:
 956       if (arch && has_3dnow)
 957         cpu = "k6-3";
 958       else
 959         cpu = "k6";
 960       break;
 961     case PROCESSOR_ATHLON:
 962       if (arch && has_sse)
 963         cpu = "athlon-4";
 964       else
 965         cpu = "athlon";
 966       break;
 967     case PROCESSOR_K8:
 968       if (arch)
 969         {
 970           if (vendor == signature_CENTAUR_ebx)
 971             {
 972               if (has_sse4_1)
 973                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 974                 cpu = "nano-3000";
 975               else if (has_ssse3)
 976                 /* Nano 1000 | Nano 2000 */
 977                 cpu = "nano";
 978               else if (has_sse3)
 979                 /* Eden X2 */
 980                 cpu = "eden-x2";
 981               else
 982                 /* Default to k8 */
 983                 cpu = "k8";
 984             }
 985           else if (has_sse3)
 986             cpu = "k8-sse3";
 987           else
 988             cpu = "k8";
 989         }
 990       else
 991         /* For -mtune, we default to -mtune=k8 */
 992         cpu = "k8";
 993       break;
 994     case PROCESSOR_AMDFAM10:
 995       cpu = "amdfam10";
 996       break;
 997     case PROCESSOR_BDVER1:
 998       cpu = "bdver1";
 999       break;
1000     case PROCESSOR_BDVER2:
1001       cpu = "bdver2";
1002       break;
1003     case PROCESSOR_BDVER3:
1004       cpu = "bdver3";
1005       break;
1006     case PROCESSOR_BDVER4:
1007       cpu = "bdver4";
1008       break;
1009     case PROCESSOR_ZNVER1:
1010       cpu = "znver1";
1011       break;
1012     case PROCESSOR_BTVER1:
1013       cpu = "btver1";
1014       break;
1015     case PROCESSOR_BTVER2:
1016       cpu = "btver2";
1017       break;
1018
1019     default:
1020       /* Use something reasonable.  */
1021       if (arch)
1022         {
1023           if (has_ssse3)
1024             cpu = "core2";
1025           else if (has_sse3)
1026             {
1027               if (has_longmode)
1028                 cpu = "nocona";
1029               else
1030                 cpu = "prescott";
1031             }
1032           else if (has_longmode)
1033             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
1034                -march=native would be unusable for 64-bit compilations,
1035                as all the CPUs below are 32-bit only.  */
1036             cpu = "x86-64";
1037           else if (has_sse2)
1038             cpu = "pentium4";
1039           else if (has_cmov)
1040             cpu = "pentiumpro";
1041           else if (has_mmx)
1042             cpu = "pentium-mmx";
1043           else if (has_cmpxchg8b)
1044             cpu = "pentium";
1045         }
1046       else
1047         cpu = "generic";
1048     }
1049
1050   if (arch)
1051     {
1052       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
1053       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
1054       const char *sse = has_sse ? " -msse" : " -mno-sse";
1055       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
1056       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
1057       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
1058       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
1059       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
1060       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
1061       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
1062       const char *aes = has_aes ? " -maes" : " -mno-aes";
1063       const char *sha = has_sha ? " -msha" : " -mno-sha";
1064       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
1065       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
1066       const char *abm = has_abm ? " -mabm" : " -mno-abm";
1067       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
1068       const char *fma = has_fma ? " -mfma" : " -mno-fma";
1069       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
1070       const char *xop = has_xop ? " -mxop" : " -mno-xop";
1071       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
1072       const char *pconfig = has_pconfig ? " -mpconfig" : " -mno-pconfig";
1073       const char *wbnoinvd = has_wbnoinvd ? " -mwbnoinvd" : " -mno-wbnoinvd";
1074       const char *sgx = has_sgx ? " -msgx" : " -mno-sgx";
1075       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
1076       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
1077       const char *avx = has_avx ? " -mavx" : " -mno-avx";
1078       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
1079       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
1080       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
1081       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
1082       const char *hle = has_hle ? " -mhle" : " -mno-hle";
1083       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
1084       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
1085       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
1086       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
1087       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
1088       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
1089       const char *adx = has_adx ? " -madx" : " -mno-adx";
1090       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
1091       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
1092       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
1093       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
1094       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
1095       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
1096       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
1097       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
1098       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
1099       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
1100       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
1101       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
1102       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
1103       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
1104       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
1105       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
1106       const char *avx5124vnniw = has_avx5124vnniw ? " -mavx5124vnniw" : " -mno-avx5124vnniw";
1107       const char *avx512vbmi2 = has_avx512vbmi2 ? " -mavx512vbmi2" : " -mno-avx512vbmi2";
1108       const char *avx512vnni = has_avx512vnni ? " -mavx512vnni" : " -mno-avx512vnni";
1109       const char *avx5124fmaps = has_avx5124fmaps ? " -mavx5124fmaps" : " -mno-avx5124fmaps";
1110       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
1111       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
1112       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
1113       const char *pku = has_pku ? " -mpku" : " -mno-pku";
1114       const char *rdpid = has_rdpid ? " -mrdpid" : " -mno-rdpid";
1115       const char *gfni = has_gfni ? " -mgfni" : " -mno-gfni";
1116       const char *shstk = has_shstk ? " -mshstk" : " -mno-shstk";
1117       const char *vaes = has_vaes ? " -mvaes" : " -mno-vaes";
1118       const char *vpclmulqdq = has_vpclmulqdq ? " -mvpclmulqdq" : " -mno-vpclmulqdq";
1119       const char *avx512bitalg = has_avx512bitalg ? " -mavx512bitalg" : " -mno-avx512bitalg";
1120       const char *movdiri = has_movdiri ? " -mmovdiri" : " -mno-movdiri";
1121       const char *movdir64b = has_movdir64b ? " -mmovdir64b" : " -mno-movdir64b";
1122       const char *waitpkg = has_waitpkg ? " -mwaitpkg" : " -mno-waitpkg";
1123       const char *cldemote = has_cldemote ? " -mcldemote" : " -mno-cldemote";
1124       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
1125                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
1126                         popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
1127                         pconfig, wbnoinvd,
1128                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
1129                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
1130                         fxsr, xsave, xsaveopt, avx512f, avx512er,
1131                         avx512cd, avx512pf, prefetchwt1, clflushopt,
1132                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
1133                         avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
1134                         clwb, mwaitx, clzero, pku, rdpid, gfni, shstk,
1135                         avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
1136                         avx512bitalg, movdiri, movdir64b, waitpkg, cldemote,
1137                         NULL);
1138     }
1139
1140 done:
1141   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
1142 }
1143 #else
1144
1145 /* If we are compiling with GCC where %EBX register is fixed, then the
1146    driver will just ignore -march and -mtune "native" target and will leave
1147    to the newly built compiler to generate code for its default target.  */
1148
1149 const char *host_detect_local_cpu (int, const char **)
1150 {
1151   return NULL;
1152 }
1153 #endif /* __GNUC__ */