gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2015 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x0d:
 130         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 131         break;
 132       case 0x0e:
 133         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 134         break;
 135       case 0x21:
 136         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 137         break;
 138       case 0x24:
 139         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 140         break;
 141       case 0x2c:
 142         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 143         break;
 144       case 0x39:
 145         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 146         break;
 147       case 0x3a:
 148         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 149         break;
 150       case 0x3b:
 151         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 152         break;
 153       case 0x3c:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 155         break;
 156       case 0x3d:
 157         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 158         break;
 159       case 0x3e:
 160         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 161         break;
 162       case 0x41:
 163         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x42:
 166         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 167         break;
 168       case 0x43:
 169         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 170         break;
 171       case 0x44:
 172         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 173         break;
 174       case 0x45:
 175         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 176         break;
 177       case 0x48:
 178         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 179         break;
 180       case 0x49:
 181         if (xeon_mp)
 182           break;
 183         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 184         break;
 185       case 0x4e:
 186         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 187         break;
 188       case 0x60:
 189         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 190         break;
 191       case 0x66:
 192         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 193         break;
 194       case 0x67:
 195         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 196         break;
 197       case 0x68:
 198         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 199         break;
 200       case 0x78:
 201         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 202         break;
 203       case 0x79:
 204         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 205         break;
 206       case 0x7a:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 208         break;
 209       case 0x7b:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 211         break;
 212       case 0x7c:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 214         break;
 215       case 0x7d:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 217         break;
 218       case 0x7f:
 219         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 220         break;
 221       case 0x80:
 222         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 223         break;
 224       case 0x82:
 225         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 226         break;
 227       case 0x83:
 228         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 229         break;
 230       case 0x84:
 231         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 232         break;
 233       case 0x85:
 234         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 235         break;
 236       case 0x86:
 237         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 238         break;
 239       case 0x87:
 240         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 241
 242       default:
 243         break;
 244       }
 245 }
 246
 247 /* Detect cache parameters using CPUID function 2.  */
 248
 249 static void
 250 detect_caches_cpuid2 (bool xeon_mp,
 251                       struct cache_desc *level1, struct cache_desc *level2)
 252 {
 253   unsigned regs[4];
 254   int nreps, i;
 255
 256   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 257
 258   nreps = regs[0] & 0x0f;
 259   regs[0] &= ~0x0f;
 260
 261   while (--nreps >= 0)
 262     {
 263       for (i = 0; i < 4; i++)
 264         if (regs[i] && !((regs[i] >> 31) & 1))
 265           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 266
 267       if (nreps)
 268         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 269     }
 270 }
 271
 272 /* Detect cache parameters using CPUID function 4. This
 273    method doesn't require hardcoded tables.  */
 274
 275 enum cache_type
 276 {
 277   CACHE_END = 0,
 278   CACHE_DATA = 1,
 279   CACHE_INST = 2,
 280   CACHE_UNIFIED = 3
 281 };
 282
 283 static void
 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 285                       struct cache_desc *level3)
 286 {
 287   struct cache_desc *cache;
 288
 289   unsigned eax, ebx, ecx, edx;
 290   int count;
 291
 292   for (count = 0;; count++)
 293     {
 294       __cpuid_count(4, count, eax, ebx, ecx, edx);
 295       switch (eax & 0x1f)
 296         {
 297         case CACHE_END:
 298           return;
 299         case CACHE_DATA:
 300         case CACHE_UNIFIED:
 301           {
 302             switch ((eax >> 5) & 0x07)
 303               {
 304               case 1:
 305                 cache = level1;
 306                 break;
 307               case 2:
 308                 cache = level2;
 309                 break;
 310               case 3:
 311                 cache = level3;
 312                 break;
 313               default:
 314                 cache = NULL;
 315               }
 316
 317             if (cache)
 318               {
 319                 unsigned sets = ecx + 1;
 320                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 321
 322                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 323                 cache->line = (ebx & 0x0fff) + 1;
 324
 325                 cache->sizekb = (cache->assoc * part
 326                                  * cache->line * sets) / 1024;
 327               }
 328           }
 329         default:
 330           break;
 331         }
 332     }
 333 }
 334
 335 /* Returns the description of caches for an Intel processor.  */
 336
 337 static const char *
 338 detect_caches_intel (bool xeon_mp, unsigned max_level,
 339                      unsigned max_ext_level, unsigned *l2sizekb)
 340 {
 341   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 342
 343   if (max_level >= 4)
 344     detect_caches_cpuid4 (&level1, &level2, &level3);
 345   else if (max_level >= 2)
 346     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 347   else
 348     return "";
 349
 350   if (level1.sizekb == 0)
 351     return "";
 352
 353   /* Let the L3 replace the L2. This assumes inclusive caches
 354      and single threaded program for now. */
 355   if (level3.sizekb)
 356     level2 = level3;
 357
 358   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 359      method if other methods fail to provide L2 cache parameters.  */
 360   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 361     detect_l2_cache (&level2);
 362
 363   *l2sizekb = level2.sizekb;
 364
 365   return describe_cache (level1, level2);
 366 }
 367
 368 /* This will be called by the spec parser in gcc.c when it sees
 369    a %:local_cpu_detect(args) construct.  Currently it will be called
 370    with either "arch" or "tune" as argument depending on if -march=native
 371    or -mtune=native is to be substituted.
 372
 373    It returns a string containing new command line parameters to be
 374    put at the place of the above two options, depending on what CPU
 375    this is executed.  E.g. "-march=k8" on an AMD64 machine
 376    for -march=native.
 377
 378    ARGC and ARGV are set depending on the actual arguments given
 379    in the spec.  */
 380
 381 const char *host_detect_local_cpu (int argc, const char **argv)
 382 {
 383   enum processor_type processor = PROCESSOR_I386;
 384   const char *cpu = "i386";
 385
 386   const char *cache = "";
 387   const char *options = "";
 388
 389   unsigned int eax, ebx, ecx, edx;
 390
 391   unsigned int max_level, ext_level;
 392
 393   unsigned int vendor;
 394   unsigned int model, family;
 395
 396   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 397   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 398
 399   /* Extended features */
 400   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 401   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 402   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 403   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 404   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 405   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 406   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 407   unsigned int has_hle = 0, has_rtm = 0;
 408   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 409   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 410   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 411   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 412   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 413   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 414   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 415   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 416   unsigned int has_pcommit = 0, has_mwaitx = 0;
 417   unsigned int has_clzero = 0;
 418
 419   bool arch;
 420
 421   unsigned int l2sizekb = 0;
 422
 423   if (argc < 1)
 424     return NULL;
 425
 426   arch = !strcmp (argv[0], "arch");
 427
 428   if (!arch && strcmp (argv[0], "tune"))
 429     return NULL;
 430
 431   max_level = __get_cpuid_max (0, &vendor);
 432   if (max_level < 1)
 433     goto done;
 434
 435   __cpuid (1, eax, ebx, ecx, edx);
 436
 437   model = (eax >> 4) & 0x0f;
 438   family = (eax >> 8) & 0x0f;
 439   if (vendor == signature_INTEL_ebx
 440       || vendor == signature_AMD_ebx)
 441     {
 442       unsigned int extended_model, extended_family;
 443
 444       extended_model = (eax >> 12) & 0xf0;
 445       extended_family = (eax >> 20) & 0xff;
 446       if (family == 0x0f)
 447         {
 448           family += extended_family;
 449           model += extended_model;
 450         }
 451       else if (family == 0x06)
 452         model += extended_model;
 453     }
 454
 455   has_sse3 = ecx & bit_SSE3;
 456   has_ssse3 = ecx & bit_SSSE3;
 457   has_sse4_1 = ecx & bit_SSE4_1;
 458   has_sse4_2 = ecx & bit_SSE4_2;
 459   has_avx = ecx & bit_AVX;
 460   has_osxsave = ecx & bit_OSXSAVE;
 461   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 462   has_movbe = ecx & bit_MOVBE;
 463   has_popcnt = ecx & bit_POPCNT;
 464   has_aes = ecx & bit_AES;
 465   has_pclmul = ecx & bit_PCLMUL;
 466   has_fma = ecx & bit_FMA;
 467   has_f16c = ecx & bit_F16C;
 468   has_rdrnd = ecx & bit_RDRND;
 469   has_xsave = ecx & bit_XSAVE;
 470
 471   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 472   has_cmov = edx & bit_CMOV;
 473   has_mmx = edx & bit_MMX;
 474   has_fxsr = edx & bit_FXSAVE;
 475   has_sse = edx & bit_SSE;
 476   has_sse2 = edx & bit_SSE2;
 477
 478   if (max_level >= 7)
 479     {
 480       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 481
 482       has_bmi = ebx & bit_BMI;
 483       has_hle = ebx & bit_HLE;
 484       has_rtm = ebx & bit_RTM;
 485       has_avx2 = ebx & bit_AVX2;
 486       has_bmi2 = ebx & bit_BMI2;
 487       has_fsgsbase = ebx & bit_FSGSBASE;
 488       has_rdseed = ebx & bit_RDSEED;
 489       has_adx = ebx & bit_ADX;
 490       has_avx512f = ebx & bit_AVX512F;
 491       has_avx512er = ebx & bit_AVX512ER;
 492       has_avx512pf = ebx & bit_AVX512PF;
 493       has_avx512cd = ebx & bit_AVX512CD;
 494       has_sha = ebx & bit_SHA;
 495       has_pcommit = ebx & bit_PCOMMIT;
 496       has_clflushopt = ebx & bit_CLFLUSHOPT;
 497       has_clwb = ebx & bit_CLWB;
 498       has_avx512dq = ebx & bit_AVX512DQ;
 499       has_avx512bw = ebx & bit_AVX512BW;
 500       has_avx512vl = ebx & bit_AVX512VL;
 501       has_avx512vl = ebx & bit_AVX512IFMA;
 502
 503       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 504       has_avx512vl = ecx & bit_AVX512VBMI;
 505     }
 506
 507   if (max_level >= 13)
 508     {
 509       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 510
 511       has_xsaveopt = eax & bit_XSAVEOPT;
 512       has_xsavec = eax & bit_XSAVEC;
 513       has_xsaves = eax & bit_XSAVES;
 514     }
 515
 516   /* Check cpuid level of extended features.  */
 517   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 518
 519   if (ext_level > 0x80000000)
 520     {
 521       __cpuid (0x80000001, eax, ebx, ecx, edx);
 522
 523       has_lahf_lm = ecx & bit_LAHF_LM;
 524       has_sse4a = ecx & bit_SSE4a;
 525       has_abm = ecx & bit_ABM;
 526       has_lwp = ecx & bit_LWP;
 527       has_fma4 = ecx & bit_FMA4;
 528       has_xop = ecx & bit_XOP;
 529       has_tbm = ecx & bit_TBM;
 530       has_lzcnt = ecx & bit_LZCNT;
 531       has_prfchw = ecx & bit_PRFCHW;
 532
 533       has_longmode = edx & bit_LM;
 534       has_3dnowp = edx & bit_3DNOWP;
 535       has_3dnow = edx & bit_3DNOW;
 536       has_mwaitx = ecx & bit_MWAITX;
 537
 538       __cpuid (0x80000008, eax, ebx, ecx, edx);
 539       has_clzero = ebx & bit_CLZERO;
 540     }
 541
 542   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 543 #define XCR_XFEATURE_ENABLED_MASK       0x0
 544 #define XSTATE_FP                       0x1
 545 #define XSTATE_SSE                      0x2
 546 #define XSTATE_YMM                      0x4
 547 #define XSTATE_OPMASK                   0x20
 548 #define XSTATE_ZMM                      0x40
 549 #define XSTATE_HI_ZMM                   0x80
 550   if (has_osxsave)
 551     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 552          : "=a" (eax), "=d" (edx)
 553          : "c" (XCR_XFEATURE_ENABLED_MASK));
 554
 555   /* Check if SSE and YMM states are supported.  */
 556   if (!has_osxsave
 557       || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
 558     {
 559       has_avx = 0;
 560       has_avx2 = 0;
 561       has_fma = 0;
 562       has_fma4 = 0;
 563       has_f16c = 0;
 564       has_xop = 0;
 565       has_xsave = 0;
 566       has_xsaveopt = 0;
 567       has_xsaves = 0;
 568       has_xsavec = 0;
 569     }
 570
 571   if (!has_osxsave
 572       || (eax &
 573           (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
 574           != (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
 575     {
 576       has_avx512f = 0;
 577       has_avx512er = 0;
 578       has_avx512pf = 0;
 579       has_avx512cd = 0;
 580       has_avx512dq = 0;
 581       has_avx512bw = 0;
 582       has_avx512vl = 0;
 583     }
 584
 585   if (!arch)
 586     {
 587       if (vendor == signature_AMD_ebx
 588           || vendor == signature_CENTAUR_ebx
 589           || vendor == signature_CYRIX_ebx
 590           || vendor == signature_NSC_ebx)
 591         cache = detect_caches_amd (ext_level);
 592       else if (vendor == signature_INTEL_ebx)
 593         {
 594           bool xeon_mp = (family == 15 && model == 6);
 595           cache = detect_caches_intel (xeon_mp, max_level,
 596                                        ext_level, &l2sizekb);
 597         }
 598     }
 599
 600   if (vendor == signature_AMD_ebx)
 601     {
 602       unsigned int name;
 603
 604       /* Detect geode processor by its processor signature.  */
 605       if (ext_level > 0x80000001)
 606         __cpuid (0x80000002, name, ebx, ecx, edx);
 607       else
 608         name = 0;
 609
 610       if (name == signature_NSC_ebx)
 611         processor = PROCESSOR_GEODE;
 612       else if (has_movbe && family == 22)
 613         processor = PROCESSOR_BTVER2;
 614       else if (has_clzero)
 615         processor = PROCESSOR_ZNVER1;
 616       else if (has_avx2)
 617         processor = PROCESSOR_BDVER4;
 618       else if (has_xsaveopt)
 619         processor = PROCESSOR_BDVER3;
 620       else if (has_bmi)
 621         processor = PROCESSOR_BDVER2;
 622       else if (has_xop)
 623         processor = PROCESSOR_BDVER1;
 624       else if (has_sse4a && has_ssse3)
 625         processor = PROCESSOR_BTVER1;
 626       else if (has_sse4a)
 627         processor = PROCESSOR_AMDFAM10;
 628       else if (has_sse2 || has_longmode)
 629         processor = PROCESSOR_K8;
 630       else if (has_3dnowp && family == 6)
 631         processor = PROCESSOR_ATHLON;
 632       else if (has_mmx)
 633         processor = PROCESSOR_K6;
 634       else
 635         processor = PROCESSOR_PENTIUM;
 636     }
 637   else if (vendor == signature_CENTAUR_ebx)
 638     {
 639       if (arch)
 640         {
 641           switch (family)
 642             {
 643             case 6:
 644               if (model > 9)
 645                 /* Use the default detection procedure.  */
 646                 processor = PROCESSOR_GENERIC;
 647               else if (model == 9)
 648                 cpu = "c3-2";
 649               else if (model >= 6)
 650                 cpu = "c3";
 651               else
 652                 processor = PROCESSOR_GENERIC;
 653               break;
 654             case 5:
 655               if (has_3dnow)
 656                 cpu = "winchip2";
 657               else if (has_mmx)
 658                 cpu = "winchip2-c6";
 659               else
 660                 processor = PROCESSOR_GENERIC;
 661               break;
 662             default:
 663               /* We have no idea.  */
 664               processor = PROCESSOR_GENERIC;
 665             }
 666         }
 667     }
 668   else
 669     {
 670       switch (family)
 671         {
 672         case 4:
 673           processor = PROCESSOR_I486;
 674           break;
 675         case 5:
 676           processor = PROCESSOR_PENTIUM;
 677           break;
 678         case 6:
 679           processor = PROCESSOR_PENTIUMPRO;
 680           break;
 681         case 15:
 682           processor = PROCESSOR_PENTIUM4;
 683           break;
 684         default:
 685           /* We have no idea.  */
 686           processor = PROCESSOR_GENERIC;
 687         }
 688     }
 689
 690   switch (processor)
 691     {
 692     case PROCESSOR_I386:
 693       /* Default.  */
 694       break;
 695     case PROCESSOR_I486:
 696       cpu = "i486";
 697       break;
 698     case PROCESSOR_PENTIUM:
 699       if (arch && has_mmx)
 700         cpu = "pentium-mmx";
 701       else
 702         cpu = "pentium";
 703       break;
 704     case PROCESSOR_PENTIUMPRO:
 705       switch (model)
 706         {
 707         case 0x1c:
 708         case 0x26:
 709           /* Bonnell.  */
 710           cpu = "bonnell";
 711           break;
 712         case 0x37:
 713         case 0x4a:
 714         case 0x4d:
 715         case 0x5a:
 716         case 0x5d:
 717           /* Silvermont.  */
 718           cpu = "silvermont";
 719           break;
 720         case 0x0f:
 721           /* Merom.  */
 722         case 0x17:
 723         case 0x1d:
 724           /* Penryn.  */
 725           cpu = "core2";
 726           break;
 727         case 0x1a:
 728         case 0x1e:
 729         case 0x1f:
 730         case 0x2e:
 731           /* Nehalem.  */
 732           cpu = "nehalem";
 733           break;
 734         case 0x25:
 735         case 0x2c:
 736         case 0x2f:
 737           /* Westmere.  */
 738           cpu = "westmere";
 739           break;
 740         case 0x2a:
 741         case 0x2d:
 742           /* Sandy Bridge.  */
 743           cpu = "sandybridge";
 744           break;
 745         case 0x3a:
 746         case 0x3e:
 747           /* Ivy Bridge.  */
 748           cpu = "ivybridge";
 749           break;
 750         case 0x3c:
 751         case 0x3f:
 752         case 0x45:
 753         case 0x46:
 754           /* Haswell.  */
 755           cpu = "haswell";
 756           break;
 757         case 0x3d:
 758         case 0x47:
 759         case 0x4f:
 760         case 0x56:
 761           /* Broadwell.  */
 762           cpu = "broadwell";
 763           break;
 764         case 0x4e:
 765         case 0x5e:
 766           /* Skylake.  */
 767           cpu = "skylake";
 768           break;
 769         case 0x57:
 770           /* Knights Landing.  */
 771           cpu = "knl";
 772           break;
 773         default:
 774           if (arch)
 775             {
 776               /* This is unknown family 0x6 CPU.  */
 777               /* Assume Knights Landing.  */
 778               if (has_avx512f)
 779                 cpu = "knl";
 780               /* Assume Broadwell.  */
 781               else if (has_adx)
 782                 cpu = "broadwell";
 783               else if (has_avx2)
 784                 /* Assume Haswell.  */
 785                 cpu = "haswell";
 786               else if (has_avx)
 787                 /* Assume Sandy Bridge.  */
 788                 cpu = "sandybridge";
 789               else if (has_sse4_2)
 790                 {
 791                   if (has_movbe)
 792                     /* Assume Silvermont.  */
 793                     cpu = "silvermont";
 794                   else
 795                     /* Assume Nehalem.  */
 796                     cpu = "nehalem";
 797                 }
 798               else if (has_ssse3)
 799                 {
 800                   if (has_movbe)
 801                     /* Assume Bonnell.  */
 802                     cpu = "bonnell";
 803                   else
 804                     /* Assume Core 2.  */
 805                     cpu = "core2";
 806                 }
 807               else if (has_longmode)
 808                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 809                    -march=native would be unusable for 64-bit compilations,
 810                    as all the CPUs below are 32-bit only.  */
 811                 cpu = "x86-64";
 812               else if (has_sse3)
 813                 /* It is Core Duo.  */
 814                 cpu = "pentium-m";
 815               else if (has_sse2)
 816                 /* It is Pentium M.  */
 817                 cpu = "pentium-m";
 818               else if (has_sse)
 819                 /* It is Pentium III.  */
 820                 cpu = "pentium3";
 821               else if (has_mmx)
 822                 /* It is Pentium II.  */
 823                 cpu = "pentium2";
 824               else
 825                 /* Default to Pentium Pro.  */
 826                 cpu = "pentiumpro";
 827             }
 828           else
 829             /* For -mtune, we default to -mtune=generic.  */
 830             cpu = "generic";
 831           break;
 832         }
 833       break;
 834     case PROCESSOR_PENTIUM4:
 835       if (has_sse3)
 836         {
 837           if (has_longmode)
 838             cpu = "nocona";
 839           else
 840             cpu = "prescott";
 841         }
 842       else
 843         cpu = "pentium4";
 844       break;
 845     case PROCESSOR_GEODE:
 846       cpu = "geode";
 847       break;
 848     case PROCESSOR_K6:
 849       if (arch && has_3dnow)
 850         cpu = "k6-3";
 851       else
 852         cpu = "k6";
 853       break;
 854     case PROCESSOR_ATHLON:
 855       if (arch && has_sse)
 856         cpu = "athlon-4";
 857       else
 858         cpu = "athlon";
 859       break;
 860     case PROCESSOR_K8:
 861       if (arch && has_sse3)
 862         cpu = "k8-sse3";
 863       else
 864         cpu = "k8";
 865       break;
 866     case PROCESSOR_AMDFAM10:
 867       cpu = "amdfam10";
 868       break;
 869     case PROCESSOR_BDVER1:
 870       cpu = "bdver1";
 871       break;
 872     case PROCESSOR_BDVER2:
 873       cpu = "bdver2";
 874       break;
 875     case PROCESSOR_BDVER3:
 876       cpu = "bdver3";
 877       break;
 878     case PROCESSOR_BDVER4:
 879       cpu = "bdver4";
 880       break;
 881     case PROCESSOR_ZNVER1:
 882       cpu = "znver1";
 883       break;
 884     case PROCESSOR_BTVER1:
 885       cpu = "btver1";
 886       break;
 887     case PROCESSOR_BTVER2:
 888       cpu = "btver2";
 889       break;
 890
 891     default:
 892       /* Use something reasonable.  */
 893       if (arch)
 894         {
 895           if (has_ssse3)
 896             cpu = "core2";
 897           else if (has_sse3)
 898             {
 899               if (has_longmode)
 900                 cpu = "nocona";
 901               else
 902                 cpu = "prescott";
 903             }
 904           else if (has_sse2)
 905             cpu = "pentium4";
 906           else if (has_cmov)
 907             cpu = "pentiumpro";
 908           else if (has_mmx)
 909             cpu = "pentium-mmx";
 910           else if (has_cmpxchg8b)
 911             cpu = "pentium";
 912         }
 913       else
 914         cpu = "generic";
 915     }
 916
 917   if (arch)
 918     {
 919       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 920       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 921       const char *sse = has_sse ? " -msse" : " -mno-sse";
 922       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 923       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 924       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 925       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 926       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 927       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 928       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 929       const char *aes = has_aes ? " -maes" : " -mno-aes";
 930       const char *sha = has_sha ? " -msha" : " -mno-sha";
 931       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 932       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 933       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 934       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 935       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 936       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 937       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 938       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 939       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 940       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 941       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 942       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 943       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 944       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 945       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 946       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 947       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
 948       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
 949       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
 950       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 951       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
 952       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
 953       const char *adx = has_adx ? " -madx" : " -mno-adx";
 954       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
 955       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
 956       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
 957       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
 958       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
 959       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
 960       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
 961       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
 962       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
 963       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
 964       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
 965       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
 966       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
 967       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
 968       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
 969       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
 970       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
 971       const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit";
 972       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
 973       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
 974       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
 975                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
 976                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
 977                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
 978                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
 979                         fxsr, xsave, xsaveopt, avx512f, avx512er,
 980                         avx512cd, avx512pf, prefetchwt1, clflushopt,
 981                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
 982                         avx512ifma, avx512vbmi, clwb, pcommit, mwaitx,
 983                         clzero, NULL);
 984     }
 985
 986 done:
 987   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 988 }
 989 #else
 990
 991 /* If we are compiling with GCC where %EBX register is fixed, then the
 992    driver will just ignore -march and -mtune "native" target and will leave
 993    to the newly built compiler to generate code for its default target.  */
 994
 995 const char *host_detect_local_cpu (int, const char **)
 996 {
 997   return NULL;
 998 }
 999 #endif /* __GNUC__ */