gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2016 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x0d:
 130         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 131         break;
 132       case 0x0e:
 133         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 134         break;
 135       case 0x21:
 136         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 137         break;
 138       case 0x24:
 139         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 140         break;
 141       case 0x2c:
 142         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 143         break;
 144       case 0x39:
 145         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 146         break;
 147       case 0x3a:
 148         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 149         break;
 150       case 0x3b:
 151         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 152         break;
 153       case 0x3c:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 155         break;
 156       case 0x3d:
 157         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 158         break;
 159       case 0x3e:
 160         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 161         break;
 162       case 0x41:
 163         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x42:
 166         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 167         break;
 168       case 0x43:
 169         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 170         break;
 171       case 0x44:
 172         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 173         break;
 174       case 0x45:
 175         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 176         break;
 177       case 0x48:
 178         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 179         break;
 180       case 0x49:
 181         if (xeon_mp)
 182           break;
 183         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 184         break;
 185       case 0x4e:
 186         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 187         break;
 188       case 0x60:
 189         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 190         break;
 191       case 0x66:
 192         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 193         break;
 194       case 0x67:
 195         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 196         break;
 197       case 0x68:
 198         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 199         break;
 200       case 0x78:
 201         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 202         break;
 203       case 0x79:
 204         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 205         break;
 206       case 0x7a:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 208         break;
 209       case 0x7b:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 211         break;
 212       case 0x7c:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 214         break;
 215       case 0x7d:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 217         break;
 218       case 0x7f:
 219         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 220         break;
 221       case 0x80:
 222         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 223         break;
 224       case 0x82:
 225         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 226         break;
 227       case 0x83:
 228         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 229         break;
 230       case 0x84:
 231         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 232         break;
 233       case 0x85:
 234         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 235         break;
 236       case 0x86:
 237         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 238         break;
 239       case 0x87:
 240         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 241
 242       default:
 243         break;
 244       }
 245 }
 246
 247 /* Detect cache parameters using CPUID function 2.  */
 248
 249 static void
 250 detect_caches_cpuid2 (bool xeon_mp,
 251                       struct cache_desc *level1, struct cache_desc *level2)
 252 {
 253   unsigned regs[4];
 254   int nreps, i;
 255
 256   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 257
 258   nreps = regs[0] & 0x0f;
 259   regs[0] &= ~0x0f;
 260
 261   while (--nreps >= 0)
 262     {
 263       for (i = 0; i < 4; i++)
 264         if (regs[i] && !((regs[i] >> 31) & 1))
 265           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 266
 267       if (nreps)
 268         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 269     }
 270 }
 271
 272 /* Detect cache parameters using CPUID function 4. This
 273    method doesn't require hardcoded tables.  */
 274
 275 enum cache_type
 276 {
 277   CACHE_END = 0,
 278   CACHE_DATA = 1,
 279   CACHE_INST = 2,
 280   CACHE_UNIFIED = 3
 281 };
 282
 283 static void
 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 285                       struct cache_desc *level3)
 286 {
 287   struct cache_desc *cache;
 288
 289   unsigned eax, ebx, ecx, edx;
 290   int count;
 291
 292   for (count = 0;; count++)
 293     {
 294       __cpuid_count(4, count, eax, ebx, ecx, edx);
 295       switch (eax & 0x1f)
 296         {
 297         case CACHE_END:
 298           return;
 299         case CACHE_DATA:
 300         case CACHE_UNIFIED:
 301           {
 302             switch ((eax >> 5) & 0x07)
 303               {
 304               case 1:
 305                 cache = level1;
 306                 break;
 307               case 2:
 308                 cache = level2;
 309                 break;
 310               case 3:
 311                 cache = level3;
 312                 break;
 313               default:
 314                 cache = NULL;
 315               }
 316
 317             if (cache)
 318               {
 319                 unsigned sets = ecx + 1;
 320                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 321
 322                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 323                 cache->line = (ebx & 0x0fff) + 1;
 324
 325                 cache->sizekb = (cache->assoc * part
 326                                  * cache->line * sets) / 1024;
 327               }
 328           }
 329         default:
 330           break;
 331         }
 332     }
 333 }
 334
 335 /* Returns the description of caches for an Intel processor.  */
 336
 337 static const char *
 338 detect_caches_intel (bool xeon_mp, unsigned max_level,
 339                      unsigned max_ext_level, unsigned *l2sizekb)
 340 {
 341   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 342
 343   if (max_level >= 4)
 344     detect_caches_cpuid4 (&level1, &level2, &level3);
 345   else if (max_level >= 2)
 346     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 347   else
 348     return "";
 349
 350   if (level1.sizekb == 0)
 351     return "";
 352
 353   /* Let the L3 replace the L2. This assumes inclusive caches
 354      and single threaded program for now. */
 355   if (level3.sizekb)
 356     level2 = level3;
 357
 358   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 359      method if other methods fail to provide L2 cache parameters.  */
 360   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 361     detect_l2_cache (&level2);
 362
 363   *l2sizekb = level2.sizekb;
 364
 365   return describe_cache (level1, level2);
 366 }
 367
 368 /* This will be called by the spec parser in gcc.c when it sees
 369    a %:local_cpu_detect(args) construct.  Currently it will be called
 370    with either "arch" or "tune" as argument depending on if -march=native
 371    or -mtune=native is to be substituted.
 372
 373    It returns a string containing new command line parameters to be
 374    put at the place of the above two options, depending on what CPU
 375    this is executed.  E.g. "-march=k8" on an AMD64 machine
 376    for -march=native.
 377
 378    ARGC and ARGV are set depending on the actual arguments given
 379    in the spec.  */
 380
 381 const char *host_detect_local_cpu (int argc, const char **argv)
 382 {
 383   enum processor_type processor = PROCESSOR_I386;
 384   const char *cpu = "i386";
 385
 386   const char *cache = "";
 387   const char *options = "";
 388
 389   unsigned int eax, ebx, ecx, edx;
 390
 391   unsigned int max_level, ext_level;
 392
 393   unsigned int vendor;
 394   unsigned int model, family;
 395
 396   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 397   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 398
 399   /* Extended features */
 400   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 401   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 402   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 403   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 404   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 405   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 406   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 407   unsigned int has_hle = 0, has_rtm = 0;
 408   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 409   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 410   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 411   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 412   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 413   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 414   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 415   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 416   unsigned int has_pcommit = 0, has_mwaitx = 0;
 417   unsigned int has_clzero = 0, has_pku = 0;
 418
 419   bool arch;
 420
 421   unsigned int l2sizekb = 0;
 422
 423   if (argc < 1)
 424     return NULL;
 425
 426   arch = !strcmp (argv[0], "arch");
 427
 428   if (!arch && strcmp (argv[0], "tune"))
 429     return NULL;
 430
 431   max_level = __get_cpuid_max (0, &vendor);
 432   if (max_level < 1)
 433     goto done;
 434
 435   __cpuid (1, eax, ebx, ecx, edx);
 436
 437   model = (eax >> 4) & 0x0f;
 438   family = (eax >> 8) & 0x0f;
 439   if (vendor == signature_INTEL_ebx
 440       || vendor == signature_AMD_ebx)
 441     {
 442       unsigned int extended_model, extended_family;
 443
 444       extended_model = (eax >> 12) & 0xf0;
 445       extended_family = (eax >> 20) & 0xff;
 446       if (family == 0x0f)
 447         {
 448           family += extended_family;
 449           model += extended_model;
 450         }
 451       else if (family == 0x06)
 452         model += extended_model;
 453     }
 454
 455   has_sse3 = ecx & bit_SSE3;
 456   has_ssse3 = ecx & bit_SSSE3;
 457   has_sse4_1 = ecx & bit_SSE4_1;
 458   has_sse4_2 = ecx & bit_SSE4_2;
 459   has_avx = ecx & bit_AVX;
 460   has_osxsave = ecx & bit_OSXSAVE;
 461   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 462   has_movbe = ecx & bit_MOVBE;
 463   has_popcnt = ecx & bit_POPCNT;
 464   has_aes = ecx & bit_AES;
 465   has_pclmul = ecx & bit_PCLMUL;
 466   has_fma = ecx & bit_FMA;
 467   has_f16c = ecx & bit_F16C;
 468   has_rdrnd = ecx & bit_RDRND;
 469   has_xsave = ecx & bit_XSAVE;
 470
 471   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 472   has_cmov = edx & bit_CMOV;
 473   has_mmx = edx & bit_MMX;
 474   has_fxsr = edx & bit_FXSAVE;
 475   has_sse = edx & bit_SSE;
 476   has_sse2 = edx & bit_SSE2;
 477
 478   if (max_level >= 7)
 479     {
 480       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 481
 482       has_bmi = ebx & bit_BMI;
 483       has_hle = ebx & bit_HLE;
 484       has_rtm = ebx & bit_RTM;
 485       has_avx2 = ebx & bit_AVX2;
 486       has_bmi2 = ebx & bit_BMI2;
 487       has_fsgsbase = ebx & bit_FSGSBASE;
 488       has_rdseed = ebx & bit_RDSEED;
 489       has_adx = ebx & bit_ADX;
 490       has_avx512f = ebx & bit_AVX512F;
 491       has_avx512er = ebx & bit_AVX512ER;
 492       has_avx512pf = ebx & bit_AVX512PF;
 493       has_avx512cd = ebx & bit_AVX512CD;
 494       has_sha = ebx & bit_SHA;
 495       has_pcommit = ebx & bit_PCOMMIT;
 496       has_clflushopt = ebx & bit_CLFLUSHOPT;
 497       has_clwb = ebx & bit_CLWB;
 498       has_avx512dq = ebx & bit_AVX512DQ;
 499       has_avx512bw = ebx & bit_AVX512BW;
 500       has_avx512vl = ebx & bit_AVX512VL;
 501       has_avx512vl = ebx & bit_AVX512IFMA;
 502
 503       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 504       has_avx512vbmi = ecx & bit_AVX512VBMI;
 505       has_pku = ecx & bit_OSPKE;
 506     }
 507
 508   if (max_level >= 13)
 509     {
 510       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 511
 512       has_xsaveopt = eax & bit_XSAVEOPT;
 513       has_xsavec = eax & bit_XSAVEC;
 514       has_xsaves = eax & bit_XSAVES;
 515     }
 516
 517   /* Check cpuid level of extended features.  */
 518   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 519
 520   if (ext_level > 0x80000000)
 521     {
 522       __cpuid (0x80000001, eax, ebx, ecx, edx);
 523
 524       has_lahf_lm = ecx & bit_LAHF_LM;
 525       has_sse4a = ecx & bit_SSE4a;
 526       has_abm = ecx & bit_ABM;
 527       has_lwp = ecx & bit_LWP;
 528       has_fma4 = ecx & bit_FMA4;
 529       has_xop = ecx & bit_XOP;
 530       has_tbm = ecx & bit_TBM;
 531       has_lzcnt = ecx & bit_LZCNT;
 532       has_prfchw = ecx & bit_PRFCHW;
 533
 534       has_longmode = edx & bit_LM;
 535       has_3dnowp = edx & bit_3DNOWP;
 536       has_3dnow = edx & bit_3DNOW;
 537       has_mwaitx = ecx & bit_MWAITX;
 538
 539       __cpuid (0x80000008, eax, ebx, ecx, edx);
 540       has_clzero = ebx & bit_CLZERO;
 541     }
 542
 543   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 544 #define XCR_XFEATURE_ENABLED_MASK       0x0
 545 #define XSTATE_FP                       0x1
 546 #define XSTATE_SSE                      0x2
 547 #define XSTATE_YMM                      0x4
 548 #define XSTATE_OPMASK                   0x20
 549 #define XSTATE_ZMM                      0x40
 550 #define XSTATE_HI_ZMM                   0x80
 551   if (has_osxsave)
 552     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 553          : "=a" (eax), "=d" (edx)
 554          : "c" (XCR_XFEATURE_ENABLED_MASK));
 555
 556   /* Check if SSE and YMM states are supported.  */
 557   if (!has_osxsave
 558       || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
 559     {
 560       has_avx = 0;
 561       has_avx2 = 0;
 562       has_fma = 0;
 563       has_fma4 = 0;
 564       has_f16c = 0;
 565       has_xop = 0;
 566       has_xsave = 0;
 567       has_xsaveopt = 0;
 568       has_xsaves = 0;
 569       has_xsavec = 0;
 570     }
 571
 572   if (!has_osxsave
 573       || (eax &
 574           (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
 575           != (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
 576     {
 577       has_avx512f = 0;
 578       has_avx512er = 0;
 579       has_avx512pf = 0;
 580       has_avx512cd = 0;
 581       has_avx512dq = 0;
 582       has_avx512bw = 0;
 583       has_avx512vl = 0;
 584     }
 585
 586   if (!arch)
 587     {
 588       if (vendor == signature_AMD_ebx
 589           || vendor == signature_CENTAUR_ebx
 590           || vendor == signature_CYRIX_ebx
 591           || vendor == signature_NSC_ebx)
 592         cache = detect_caches_amd (ext_level);
 593       else if (vendor == signature_INTEL_ebx)
 594         {
 595           bool xeon_mp = (family == 15 && model == 6);
 596           cache = detect_caches_intel (xeon_mp, max_level,
 597                                        ext_level, &l2sizekb);
 598         }
 599     }
 600
 601   if (vendor == signature_AMD_ebx)
 602     {
 603       unsigned int name;
 604
 605       /* Detect geode processor by its processor signature.  */
 606       if (ext_level > 0x80000001)
 607         __cpuid (0x80000002, name, ebx, ecx, edx);
 608       else
 609         name = 0;
 610
 611       if (name == signature_NSC_ebx)
 612         processor = PROCESSOR_GEODE;
 613       else if (has_movbe && family == 22)
 614         processor = PROCESSOR_BTVER2;
 615       else if (has_clzero)
 616         processor = PROCESSOR_ZNVER1;
 617       else if (has_avx2)
 618         processor = PROCESSOR_BDVER4;
 619       else if (has_xsaveopt)
 620         processor = PROCESSOR_BDVER3;
 621       else if (has_bmi)
 622         processor = PROCESSOR_BDVER2;
 623       else if (has_xop)
 624         processor = PROCESSOR_BDVER1;
 625       else if (has_sse4a && has_ssse3)
 626         processor = PROCESSOR_BTVER1;
 627       else if (has_sse4a)
 628         processor = PROCESSOR_AMDFAM10;
 629       else if (has_sse2 || has_longmode)
 630         processor = PROCESSOR_K8;
 631       else if (has_3dnowp && family == 6)
 632         processor = PROCESSOR_ATHLON;
 633       else if (has_mmx)
 634         processor = PROCESSOR_K6;
 635       else
 636         processor = PROCESSOR_PENTIUM;
 637     }
 638   else if (vendor == signature_CENTAUR_ebx)
 639     {
 640       processor = PROCESSOR_GENERIC;
 641
 642       switch (family)
 643         {
 644         default:
 645           /* We have no idea.  */
 646           break;
 647
 648         case 5:
 649           if (has_3dnow || has_mmx)
 650             processor = PROCESSOR_I486;
 651           break;
 652
 653         case 6:
 654           if (has_longmode)
 655             processor = PROCESSOR_K8;
 656           else if (model >= 9)
 657             processor = PROCESSOR_PENTIUMPRO;
 658           else if (model >= 6)
 659             processor = PROCESSOR_I486;
 660         }
 661     }
 662   else
 663     {
 664       switch (family)
 665         {
 666         case 4:
 667           processor = PROCESSOR_I486;
 668           break;
 669         case 5:
 670           processor = PROCESSOR_PENTIUM;
 671           break;
 672         case 6:
 673           processor = PROCESSOR_PENTIUMPRO;
 674           break;
 675         case 15:
 676           processor = PROCESSOR_PENTIUM4;
 677           break;
 678         default:
 679           /* We have no idea.  */
 680           processor = PROCESSOR_GENERIC;
 681         }
 682     }
 683
 684   switch (processor)
 685     {
 686     case PROCESSOR_I386:
 687       /* Default.  */
 688       break;
 689     case PROCESSOR_I486:
 690       if (arch && vendor == signature_CENTAUR_ebx)
 691         {
 692           if (model >= 6)
 693             cpu = "c3";
 694           else if (has_3dnow)
 695             cpu = "winchip2";
 696           else
 697             /* Assume WinChip C6.  */
 698             cpu = "winchip-c6";
 699         }
 700       else
 701         cpu = "i486";
 702       break;
 703     case PROCESSOR_PENTIUM:
 704       if (arch && has_mmx)
 705         cpu = "pentium-mmx";
 706       else
 707         cpu = "pentium";
 708       break;
 709     case PROCESSOR_PENTIUMPRO:
 710       switch (model)
 711         {
 712         case 0x1c:
 713         case 0x26:
 714           /* Bonnell.  */
 715           cpu = "bonnell";
 716           break;
 717         case 0x37:
 718         case 0x4a:
 719         case 0x4d:
 720         case 0x5a:
 721         case 0x5d:
 722           /* Silvermont.  */
 723           cpu = "silvermont";
 724           break;
 725         case 0x0f:
 726           /* Merom.  */
 727         case 0x17:
 728         case 0x1d:
 729           /* Penryn.  */
 730           cpu = "core2";
 731           break;
 732         case 0x1a:
 733         case 0x1e:
 734         case 0x1f:
 735         case 0x2e:
 736           /* Nehalem.  */
 737           cpu = "nehalem";
 738           break;
 739         case 0x25:
 740         case 0x2c:
 741         case 0x2f:
 742           /* Westmere.  */
 743           cpu = "westmere";
 744           break;
 745         case 0x2a:
 746         case 0x2d:
 747           /* Sandy Bridge.  */
 748           cpu = "sandybridge";
 749           break;
 750         case 0x3a:
 751         case 0x3e:
 752           /* Ivy Bridge.  */
 753           cpu = "ivybridge";
 754           break;
 755         case 0x3c:
 756         case 0x3f:
 757         case 0x45:
 758         case 0x46:
 759           /* Haswell.  */
 760           cpu = "haswell";
 761           break;
 762         case 0x3d:
 763         case 0x47:
 764         case 0x4f:
 765         case 0x56:
 766           /* Broadwell.  */
 767           cpu = "broadwell";
 768           break;
 769         case 0x4e:
 770         case 0x5e:
 771           /* Skylake.  */
 772           cpu = "skylake";
 773           break;
 774         case 0x57:
 775           /* Knights Landing.  */
 776           cpu = "knl";
 777           break;
 778         default:
 779           if (arch)
 780             {
 781               /* This is unknown family 0x6 CPU.  */
 782               /* Assume Knights Landing.  */
 783               if (has_avx512f)
 784                 cpu = "knl";
 785               /* Assume Broadwell.  */
 786               else if (has_adx)
 787                 cpu = "broadwell";
 788               else if (has_avx2)
 789                 /* Assume Haswell.  */
 790                 cpu = "haswell";
 791               else if (has_avx)
 792                 /* Assume Sandy Bridge.  */
 793                 cpu = "sandybridge";
 794               else if (has_sse4_2)
 795                 {
 796                   if (has_movbe)
 797                     /* Assume Silvermont.  */
 798                     cpu = "silvermont";
 799                   else
 800                     /* Assume Nehalem.  */
 801                     cpu = "nehalem";
 802                 }
 803               else if (has_ssse3)
 804                 {
 805                   if (has_movbe)
 806                     /* Assume Bonnell.  */
 807                     cpu = "bonnell";
 808                   else
 809                     /* Assume Core 2.  */
 810                     cpu = "core2";
 811                 }
 812               else if (has_longmode)
 813                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 814                    -march=native would be unusable for 64-bit compilations,
 815                    as all the CPUs below are 32-bit only.  */
 816                 cpu = "x86-64";
 817               else if (has_sse3)
 818                 {
 819                   if (vendor == signature_CENTAUR_ebx)
 820                     /* C7 / Eden "Esther" */
 821                     cpu = "c7";
 822                   else
 823                     /* It is Core Duo.  */
 824                     cpu = "pentium-m";
 825                 }
 826               else if (has_sse2)
 827                 /* It is Pentium M.  */
 828                 cpu = "pentium-m";
 829               else if (has_sse)
 830                 {
 831                   if (vendor == signature_CENTAUR_ebx)
 832                     {
 833                       if (model >= 9)
 834                         /* Eden "Nehemiah" */
 835                         cpu = "nehemiah";
 836                       else
 837                         cpu = "c3-2";
 838                     }
 839                   else
 840                     /* It is Pentium III.  */
 841                     cpu = "pentium3";
 842                 }
 843               else if (has_mmx)
 844                 /* It is Pentium II.  */
 845                 cpu = "pentium2";
 846               else
 847                 /* Default to Pentium Pro.  */
 848                 cpu = "pentiumpro";
 849             }
 850           else
 851             /* For -mtune, we default to -mtune=generic.  */
 852             cpu = "generic";
 853           break;
 854         }
 855       break;
 856     case PROCESSOR_PENTIUM4:
 857       if (has_sse3)
 858         {
 859           if (has_longmode)
 860             cpu = "nocona";
 861           else
 862             cpu = "prescott";
 863         }
 864       else
 865         cpu = "pentium4";
 866       break;
 867     case PROCESSOR_GEODE:
 868       cpu = "geode";
 869       break;
 870     case PROCESSOR_K6:
 871       if (arch && has_3dnow)
 872         cpu = "k6-3";
 873       else
 874         cpu = "k6";
 875       break;
 876     case PROCESSOR_ATHLON:
 877       if (arch && has_sse)
 878         cpu = "athlon-4";
 879       else
 880         cpu = "athlon";
 881       break;
 882     case PROCESSOR_K8:
 883       if (arch)
 884         {
 885           if (vendor == signature_CENTAUR_ebx)
 886             {
 887               if (has_sse4_1)
 888                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 889                 cpu = "nano-3000";
 890               else if (has_ssse3)
 891                 /* Nano 1000 | Nano 2000 */
 892                 cpu = "nano";
 893               else if (has_sse3)
 894                 /* Eden X2 */
 895                 cpu = "eden-x2";
 896               else
 897                 /* Default to k8 */
 898                 cpu = "k8";
 899             }
 900           else if (has_sse3)
 901             cpu = "k8-sse3";
 902           else
 903             cpu = "k8";
 904         }
 905       else
 906         /* For -mtune, we default to -mtune=k8 */
 907         cpu = "k8";
 908       break;
 909     case PROCESSOR_AMDFAM10:
 910       cpu = "amdfam10";
 911       break;
 912     case PROCESSOR_BDVER1:
 913       cpu = "bdver1";
 914       break;
 915     case PROCESSOR_BDVER2:
 916       cpu = "bdver2";
 917       break;
 918     case PROCESSOR_BDVER3:
 919       cpu = "bdver3";
 920       break;
 921     case PROCESSOR_BDVER4:
 922       cpu = "bdver4";
 923       break;
 924     case PROCESSOR_ZNVER1:
 925       cpu = "znver1";
 926       break;
 927     case PROCESSOR_BTVER1:
 928       cpu = "btver1";
 929       break;
 930     case PROCESSOR_BTVER2:
 931       cpu = "btver2";
 932       break;
 933
 934     default:
 935       /* Use something reasonable.  */
 936       if (arch)
 937         {
 938           if (has_ssse3)
 939             cpu = "core2";
 940           else if (has_sse3)
 941             {
 942               if (has_longmode)
 943                 cpu = "nocona";
 944               else
 945                 cpu = "prescott";
 946             }
 947           else if (has_longmode)
 948             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 949                -march=native would be unusable for 64-bit compilations,
 950                as all the CPUs below are 32-bit only.  */
 951             cpu = "x86-64";
 952           else if (has_sse2)
 953             cpu = "pentium4";
 954           else if (has_cmov)
 955             cpu = "pentiumpro";
 956           else if (has_mmx)
 957             cpu = "pentium-mmx";
 958           else if (has_cmpxchg8b)
 959             cpu = "pentium";
 960         }
 961       else
 962         cpu = "generic";
 963     }
 964
 965   if (arch)
 966     {
 967       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 968       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 969       const char *sse = has_sse ? " -msse" : " -mno-sse";
 970       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 971       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 972       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 973       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 974       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 975       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 976       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 977       const char *aes = has_aes ? " -maes" : " -mno-aes";
 978       const char *sha = has_sha ? " -msha" : " -mno-sha";
 979       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 980       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 981       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 982       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 983       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 984       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 985       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 986       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 987       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 988       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 989       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 990       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 991       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 992       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 993       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 994       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 995       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
 996       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
 997       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
 998       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 999       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
1000       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
1001       const char *adx = has_adx ? " -madx" : " -mno-adx";
1002       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
1003       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
1004       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
1005       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
1006       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
1007       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
1008       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
1009       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
1010       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
1011       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
1012       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
1013       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
1014       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
1015       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
1016       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
1017       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
1018       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
1019       const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit";
1020       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
1021       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
1022       const char *pku = has_pku ? " -mpku" : " -mno-pku";
1023       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
1024                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
1025                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
1026                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
1027                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
1028                         fxsr, xsave, xsaveopt, avx512f, avx512er,
1029                         avx512cd, avx512pf, prefetchwt1, clflushopt,
1030                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
1031                         avx512ifma, avx512vbmi, clwb, pcommit, mwaitx,
1032                         clzero, pku, NULL);
1033     }
1034
1035 done:
1036   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
1037 }
1038 #else
1039
1040 /* If we are compiling with GCC where %EBX register is fixed, then the
1041    driver will just ignore -march and -mtune "native" target and will leave
1042    to the newly built compiler to generate code for its default target.  */
1043
1044 const char *host_detect_local_cpu (int, const char **)
1045 {
1046   return NULL;
1047 }
1048 #endif /* __GNUC__ */