gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2017 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x0d:
 130         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 131         break;
 132       case 0x0e:
 133         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 134         break;
 135       case 0x21:
 136         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 137         break;
 138       case 0x24:
 139         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 140         break;
 141       case 0x2c:
 142         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 143         break;
 144       case 0x39:
 145         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 146         break;
 147       case 0x3a:
 148         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 149         break;
 150       case 0x3b:
 151         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 152         break;
 153       case 0x3c:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 155         break;
 156       case 0x3d:
 157         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 158         break;
 159       case 0x3e:
 160         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 161         break;
 162       case 0x41:
 163         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x42:
 166         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 167         break;
 168       case 0x43:
 169         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 170         break;
 171       case 0x44:
 172         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 173         break;
 174       case 0x45:
 175         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 176         break;
 177       case 0x48:
 178         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 179         break;
 180       case 0x49:
 181         if (xeon_mp)
 182           break;
 183         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 184         break;
 185       case 0x4e:
 186         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 187         break;
 188       case 0x60:
 189         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 190         break;
 191       case 0x66:
 192         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 193         break;
 194       case 0x67:
 195         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 196         break;
 197       case 0x68:
 198         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 199         break;
 200       case 0x78:
 201         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 202         break;
 203       case 0x79:
 204         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 205         break;
 206       case 0x7a:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 208         break;
 209       case 0x7b:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 211         break;
 212       case 0x7c:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 214         break;
 215       case 0x7d:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 217         break;
 218       case 0x7f:
 219         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 220         break;
 221       case 0x80:
 222         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 223         break;
 224       case 0x82:
 225         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 226         break;
 227       case 0x83:
 228         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 229         break;
 230       case 0x84:
 231         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 232         break;
 233       case 0x85:
 234         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 235         break;
 236       case 0x86:
 237         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 238         break;
 239       case 0x87:
 240         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 241
 242       default:
 243         break;
 244       }
 245 }
 246
 247 /* Detect cache parameters using CPUID function 2.  */
 248
 249 static void
 250 detect_caches_cpuid2 (bool xeon_mp,
 251                       struct cache_desc *level1, struct cache_desc *level2)
 252 {
 253   unsigned regs[4];
 254   int nreps, i;
 255
 256   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 257
 258   nreps = regs[0] & 0x0f;
 259   regs[0] &= ~0x0f;
 260
 261   while (--nreps >= 0)
 262     {
 263       for (i = 0; i < 4; i++)
 264         if (regs[i] && !((regs[i] >> 31) & 1))
 265           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 266
 267       if (nreps)
 268         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 269     }
 270 }
 271
 272 /* Detect cache parameters using CPUID function 4. This
 273    method doesn't require hardcoded tables.  */
 274
 275 enum cache_type
 276 {
 277   CACHE_END = 0,
 278   CACHE_DATA = 1,
 279   CACHE_INST = 2,
 280   CACHE_UNIFIED = 3
 281 };
 282
 283 static void
 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 285                       struct cache_desc *level3)
 286 {
 287   struct cache_desc *cache;
 288
 289   unsigned eax, ebx, ecx, edx;
 290   int count;
 291
 292   for (count = 0;; count++)
 293     {
 294       __cpuid_count(4, count, eax, ebx, ecx, edx);
 295       switch (eax & 0x1f)
 296         {
 297         case CACHE_END:
 298           return;
 299         case CACHE_DATA:
 300         case CACHE_UNIFIED:
 301           {
 302             switch ((eax >> 5) & 0x07)
 303               {
 304               case 1:
 305                 cache = level1;
 306                 break;
 307               case 2:
 308                 cache = level2;
 309                 break;
 310               case 3:
 311                 cache = level3;
 312                 break;
 313               default:
 314                 cache = NULL;
 315               }
 316
 317             if (cache)
 318               {
 319                 unsigned sets = ecx + 1;
 320                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 321
 322                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 323                 cache->line = (ebx & 0x0fff) + 1;
 324
 325                 cache->sizekb = (cache->assoc * part
 326                                  * cache->line * sets) / 1024;
 327               }
 328           }
 329         default:
 330           break;
 331         }
 332     }
 333 }
 334
 335 /* Returns the description of caches for an Intel processor.  */
 336
 337 static const char *
 338 detect_caches_intel (bool xeon_mp, unsigned max_level,
 339                      unsigned max_ext_level, unsigned *l2sizekb)
 340 {
 341   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 342
 343   if (max_level >= 4)
 344     detect_caches_cpuid4 (&level1, &level2, &level3);
 345   else if (max_level >= 2)
 346     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 347   else
 348     return "";
 349
 350   if (level1.sizekb == 0)
 351     return "";
 352
 353   /* Let the L3 replace the L2. This assumes inclusive caches
 354      and single threaded program for now. */
 355   if (level3.sizekb)
 356     level2 = level3;
 357
 358   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 359      method if other methods fail to provide L2 cache parameters.  */
 360   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 361     detect_l2_cache (&level2);
 362
 363   *l2sizekb = level2.sizekb;
 364
 365   return describe_cache (level1, level2);
 366 }
 367
 368 /* This will be called by the spec parser in gcc.c when it sees
 369    a %:local_cpu_detect(args) construct.  Currently it will be called
 370    with either "arch" or "tune" as argument depending on if -march=native
 371    or -mtune=native is to be substituted.
 372
 373    It returns a string containing new command line parameters to be
 374    put at the place of the above two options, depending on what CPU
 375    this is executed.  E.g. "-march=k8" on an AMD64 machine
 376    for -march=native.
 377
 378    ARGC and ARGV are set depending on the actual arguments given
 379    in the spec.  */
 380
 381 const char *host_detect_local_cpu (int argc, const char **argv)
 382 {
 383   enum processor_type processor = PROCESSOR_I386;
 384   const char *cpu = "i386";
 385
 386   const char *cache = "";
 387   const char *options = "";
 388
 389   unsigned int eax, ebx, ecx, edx;
 390
 391   unsigned int max_level, ext_level;
 392
 393   unsigned int vendor;
 394   unsigned int model, family;
 395
 396   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 397   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 398
 399   /* Extended features */
 400   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 401   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 402   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 403   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 404   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 405   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 406   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 407   unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0;
 408   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 409   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 410   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 411   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 412   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 413   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 414   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 415   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 416   unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0, has_rdpid = 0;
 417   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
 418   unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
 419   unsigned int has_ibt = 0, has_shstk = 0;
 420
 421   bool arch;
 422
 423   unsigned int l2sizekb = 0;
 424
 425   if (argc < 1)
 426     return NULL;
 427
 428   arch = !strcmp (argv[0], "arch");
 429
 430   if (!arch && strcmp (argv[0], "tune"))
 431     return NULL;
 432
 433   max_level = __get_cpuid_max (0, &vendor);
 434   if (max_level < 1)
 435     goto done;
 436
 437   __cpuid (1, eax, ebx, ecx, edx);
 438
 439   model = (eax >> 4) & 0x0f;
 440   family = (eax >> 8) & 0x0f;
 441   if (vendor == signature_INTEL_ebx
 442       || vendor == signature_AMD_ebx)
 443     {
 444       unsigned int extended_model, extended_family;
 445
 446       extended_model = (eax >> 12) & 0xf0;
 447       extended_family = (eax >> 20) & 0xff;
 448       if (family == 0x0f)
 449         {
 450           family += extended_family;
 451           model += extended_model;
 452         }
 453       else if (family == 0x06)
 454         model += extended_model;
 455     }
 456
 457   has_sse3 = ecx & bit_SSE3;
 458   has_ssse3 = ecx & bit_SSSE3;
 459   has_sse4_1 = ecx & bit_SSE4_1;
 460   has_sse4_2 = ecx & bit_SSE4_2;
 461   has_avx = ecx & bit_AVX;
 462   has_osxsave = ecx & bit_OSXSAVE;
 463   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 464   has_movbe = ecx & bit_MOVBE;
 465   has_popcnt = ecx & bit_POPCNT;
 466   has_aes = ecx & bit_AES;
 467   has_pclmul = ecx & bit_PCLMUL;
 468   has_fma = ecx & bit_FMA;
 469   has_f16c = ecx & bit_F16C;
 470   has_rdrnd = ecx & bit_RDRND;
 471   has_xsave = ecx & bit_XSAVE;
 472
 473   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 474   has_cmov = edx & bit_CMOV;
 475   has_mmx = edx & bit_MMX;
 476   has_fxsr = edx & bit_FXSAVE;
 477   has_sse = edx & bit_SSE;
 478   has_sse2 = edx & bit_SSE2;
 479
 480   if (max_level >= 7)
 481     {
 482       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 483
 484       has_bmi = ebx & bit_BMI;
 485       has_sgx = ebx & bit_SGX;
 486       has_hle = ebx & bit_HLE;
 487       has_rtm = ebx & bit_RTM;
 488       has_avx2 = ebx & bit_AVX2;
 489       has_bmi2 = ebx & bit_BMI2;
 490       has_fsgsbase = ebx & bit_FSGSBASE;
 491       has_rdseed = ebx & bit_RDSEED;
 492       has_adx = ebx & bit_ADX;
 493       has_avx512f = ebx & bit_AVX512F;
 494       has_avx512er = ebx & bit_AVX512ER;
 495       has_avx512pf = ebx & bit_AVX512PF;
 496       has_avx512cd = ebx & bit_AVX512CD;
 497       has_sha = ebx & bit_SHA;
 498       has_clflushopt = ebx & bit_CLFLUSHOPT;
 499       has_clwb = ebx & bit_CLWB;
 500       has_avx512dq = ebx & bit_AVX512DQ;
 501       has_avx512bw = ebx & bit_AVX512BW;
 502       has_avx512vl = ebx & bit_AVX512VL;
 503       has_avx512ifma = ebx & bit_AVX512IFMA;
 504
 505       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 506       has_avx512vbmi = ecx & bit_AVX512VBMI;
 507       has_pku = ecx & bit_OSPKE;
 508       has_avx512vbmi2 = ecx & bit_AVX512VBMI2;
 509       has_rdpid = ecx & bit_RDPID;
 510       has_gfni = ecx & bit_GFNI;
 511
 512       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
 513       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
 514
 515       has_shstk = ecx & bit_SHSTK;
 516       has_ibt = edx & bit_IBT;
 517     }
 518
 519   if (max_level >= 13)
 520     {
 521       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 522
 523       has_xsaveopt = eax & bit_XSAVEOPT;
 524       has_xsavec = eax & bit_XSAVEC;
 525       has_xsaves = eax & bit_XSAVES;
 526     }
 527
 528   /* Check cpuid level of extended features.  */
 529   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 530
 531   if (ext_level >= 0x80000001)
 532     {
 533       __cpuid (0x80000001, eax, ebx, ecx, edx);
 534
 535       has_lahf_lm = ecx & bit_LAHF_LM;
 536       has_sse4a = ecx & bit_SSE4a;
 537       has_abm = ecx & bit_ABM;
 538       has_lwp = ecx & bit_LWP;
 539       has_fma4 = ecx & bit_FMA4;
 540       has_xop = ecx & bit_XOP;
 541       has_tbm = ecx & bit_TBM;
 542       has_lzcnt = ecx & bit_LZCNT;
 543       has_prfchw = ecx & bit_PRFCHW;
 544
 545       has_longmode = edx & bit_LM;
 546       has_3dnowp = edx & bit_3DNOWP;
 547       has_3dnow = edx & bit_3DNOW;
 548       has_mwaitx = ecx & bit_MWAITX;
 549     }
 550
 551   if (ext_level >= 0x80000008)
 552     {
 553       __cpuid (0x80000008, eax, ebx, ecx, edx);
 554       has_clzero = ebx & bit_CLZERO;
 555     }
 556
 557   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 558 #define XCR_XFEATURE_ENABLED_MASK       0x0
 559 #define XSTATE_FP                       0x1
 560 #define XSTATE_SSE                      0x2
 561 #define XSTATE_YMM                      0x4
 562 #define XSTATE_OPMASK                   0x20
 563 #define XSTATE_ZMM                      0x40
 564 #define XSTATE_HI_ZMM                   0x80
 565
 566 #define XCR_AVX_ENABLED_MASK \
 567   (XSTATE_SSE | XSTATE_YMM)
 568 #define XCR_AVX512F_ENABLED_MASK \
 569   (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
 570
 571   if (has_osxsave)
 572     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 573          : "=a" (eax), "=d" (edx)
 574          : "c" (XCR_XFEATURE_ENABLED_MASK));
 575   else
 576     eax = 0;
 577
 578   /* Check if AVX registers are supported.  */
 579   if ((eax & XCR_AVX_ENABLED_MASK) != XCR_AVX_ENABLED_MASK)
 580     {
 581       has_avx = 0;
 582       has_avx2 = 0;
 583       has_fma = 0;
 584       has_fma4 = 0;
 585       has_f16c = 0;
 586       has_xop = 0;
 587       has_xsave = 0;
 588       has_xsaveopt = 0;
 589       has_xsaves = 0;
 590       has_xsavec = 0;
 591     }
 592
 593   /* Check if AVX512F registers are supported.  */
 594   if ((eax & XCR_AVX512F_ENABLED_MASK) != XCR_AVX512F_ENABLED_MASK)
 595     {
 596       has_avx512f = 0;
 597       has_avx512er = 0;
 598       has_avx512pf = 0;
 599       has_avx512cd = 0;
 600       has_avx512dq = 0;
 601       has_avx512bw = 0;
 602       has_avx512vl = 0;
 603     }
 604
 605   if (!arch)
 606     {
 607       if (vendor == signature_AMD_ebx
 608           || vendor == signature_CENTAUR_ebx
 609           || vendor == signature_CYRIX_ebx
 610           || vendor == signature_NSC_ebx)
 611         cache = detect_caches_amd (ext_level);
 612       else if (vendor == signature_INTEL_ebx)
 613         {
 614           bool xeon_mp = (family == 15 && model == 6);
 615           cache = detect_caches_intel (xeon_mp, max_level,
 616                                        ext_level, &l2sizekb);
 617         }
 618     }
 619
 620   if (vendor == signature_AMD_ebx)
 621     {
 622       unsigned int name;
 623
 624       /* Detect geode processor by its processor signature.  */
 625       if (ext_level >= 0x80000002)
 626         __cpuid (0x80000002, name, ebx, ecx, edx);
 627       else
 628         name = 0;
 629
 630       if (name == signature_NSC_ebx)
 631         processor = PROCESSOR_GEODE;
 632       else if (has_movbe && family == 22)
 633         processor = PROCESSOR_BTVER2;
 634       else if (has_clzero)
 635         processor = PROCESSOR_ZNVER1;
 636       else if (has_avx2)
 637         processor = PROCESSOR_BDVER4;
 638       else if (has_xsaveopt)
 639         processor = PROCESSOR_BDVER3;
 640       else if (has_bmi)
 641         processor = PROCESSOR_BDVER2;
 642       else if (has_xop)
 643         processor = PROCESSOR_BDVER1;
 644       else if (has_sse4a && has_ssse3)
 645         processor = PROCESSOR_BTVER1;
 646       else if (has_sse4a)
 647         processor = PROCESSOR_AMDFAM10;
 648       else if (has_sse2 || has_longmode)
 649         processor = PROCESSOR_K8;
 650       else if (has_3dnowp && family == 6)
 651         processor = PROCESSOR_ATHLON;
 652       else if (has_mmx)
 653         processor = PROCESSOR_K6;
 654       else
 655         processor = PROCESSOR_PENTIUM;
 656     }
 657   else if (vendor == signature_CENTAUR_ebx)
 658     {
 659       processor = PROCESSOR_GENERIC;
 660
 661       switch (family)
 662         {
 663         default:
 664           /* We have no idea.  */
 665           break;
 666
 667         case 5:
 668           if (has_3dnow || has_mmx)
 669             processor = PROCESSOR_I486;
 670           break;
 671
 672         case 6:
 673           if (has_longmode)
 674             processor = PROCESSOR_K8;
 675           else if (model >= 9)
 676             processor = PROCESSOR_PENTIUMPRO;
 677           else if (model >= 6)
 678             processor = PROCESSOR_I486;
 679         }
 680     }
 681   else
 682     {
 683       switch (family)
 684         {
 685         case 4:
 686           processor = PROCESSOR_I486;
 687           break;
 688         case 5:
 689           processor = PROCESSOR_PENTIUM;
 690           break;
 691         case 6:
 692           processor = PROCESSOR_PENTIUMPRO;
 693           break;
 694         case 15:
 695           processor = PROCESSOR_PENTIUM4;
 696           break;
 697         default:
 698           /* We have no idea.  */
 699           processor = PROCESSOR_GENERIC;
 700         }
 701     }
 702
 703   switch (processor)
 704     {
 705     case PROCESSOR_I386:
 706       /* Default.  */
 707       break;
 708     case PROCESSOR_I486:
 709       if (arch && vendor == signature_CENTAUR_ebx)
 710         {
 711           if (model >= 6)
 712             cpu = "c3";
 713           else if (has_3dnow)
 714             cpu = "winchip2";
 715           else
 716             /* Assume WinChip C6.  */
 717             cpu = "winchip-c6";
 718         }
 719       else
 720         cpu = "i486";
 721       break;
 722     case PROCESSOR_PENTIUM:
 723       if (arch && has_mmx)
 724         cpu = "pentium-mmx";
 725       else
 726         cpu = "pentium";
 727       break;
 728     case PROCESSOR_PENTIUMPRO:
 729       switch (model)
 730         {
 731         case 0x1c:
 732         case 0x26:
 733           /* Bonnell.  */
 734           cpu = "bonnell";
 735           break;
 736         case 0x37:
 737         case 0x4a:
 738         case 0x4d:
 739         case 0x5a:
 740         case 0x5d:
 741           /* Silvermont.  */
 742           cpu = "silvermont";
 743           break;
 744         case 0x0f:
 745           /* Merom.  */
 746         case 0x17:
 747         case 0x1d:
 748           /* Penryn.  */
 749           cpu = "core2";
 750           break;
 751         case 0x1a:
 752         case 0x1e:
 753         case 0x1f:
 754         case 0x2e:
 755           /* Nehalem.  */
 756           cpu = "nehalem";
 757           break;
 758         case 0x25:
 759         case 0x2c:
 760         case 0x2f:
 761           /* Westmere.  */
 762           cpu = "westmere";
 763           break;
 764         case 0x2a:
 765         case 0x2d:
 766           /* Sandy Bridge.  */
 767           cpu = "sandybridge";
 768           break;
 769         case 0x3a:
 770         case 0x3e:
 771           /* Ivy Bridge.  */
 772           cpu = "ivybridge";
 773           break;
 774         case 0x3c:
 775         case 0x3f:
 776         case 0x45:
 777         case 0x46:
 778           /* Haswell.  */
 779           cpu = "haswell";
 780           break;
 781         case 0x3d:
 782         case 0x47:
 783         case 0x4f:
 784         case 0x56:
 785           /* Broadwell.  */
 786           cpu = "broadwell";
 787           break;
 788         case 0x4e:
 789         case 0x5e:
 790           /* Skylake.  */
 791         case 0x8e:
 792         case 0x9e:
 793           /* Kaby Lake.  */
 794           cpu = "skylake";
 795           break;
 796         case 0x55:
 797           /* Skylake with AVX-512.  */
 798           cpu = "skylake-avx512";
 799           break;
 800         case 0x57:
 801           /* Knights Landing.  */
 802           cpu = "knl";
 803           break;
 804         case 0x66:
 805           /* Cannon Lake.  */
 806           cpu = "cannonlake";
 807           break;
 808         case 0x85:
 809           /* Knights Mill.  */
 810           cpu = "knm";
 811           break;
 812         default:
 813           if (arch)
 814             {
 815               /* This is unknown family 0x6 CPU.  */
 816               /* Assume Cannon Lake.  */
 817               if (has_avx512vbmi)
 818                 cpu = "cannonlake";
 819               /* Assume Knights Mill.  */
 820               else if (has_avx5124vnniw)
 821                 cpu = "knm";
 822               /* Assume Knights Landing.  */
 823               else if (has_avx512er)
 824                 cpu = "knl";
 825               /* Assume Skylake with AVX-512.  */
 826               else if (has_avx512f)
 827                 cpu = "skylake-avx512";
 828               /* Assume Skylake.  */
 829               else if (has_clflushopt)
 830                 cpu = "skylake";
 831               /* Assume Broadwell.  */
 832               else if (has_adx)
 833                 cpu = "broadwell";
 834               else if (has_avx2)
 835                 /* Assume Haswell.  */
 836                 cpu = "haswell";
 837               else if (has_avx)
 838                 /* Assume Sandy Bridge.  */
 839                 cpu = "sandybridge";
 840               else if (has_sse4_2)
 841                 {
 842                   if (has_movbe)
 843                     /* Assume Silvermont.  */
 844                     cpu = "silvermont";
 845                   else
 846                     /* Assume Nehalem.  */
 847                     cpu = "nehalem";
 848                 }
 849               else if (has_ssse3)
 850                 {
 851                   if (has_movbe)
 852                     /* Assume Bonnell.  */
 853                     cpu = "bonnell";
 854                   else
 855                     /* Assume Core 2.  */
 856                     cpu = "core2";
 857                 }
 858               else if (has_longmode)
 859                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 860                    -march=native would be unusable for 64-bit compilations,
 861                    as all the CPUs below are 32-bit only.  */
 862                 cpu = "x86-64";
 863               else if (has_sse3)
 864                 {
 865                   if (vendor == signature_CENTAUR_ebx)
 866                     /* C7 / Eden "Esther" */
 867                     cpu = "c7";
 868                   else
 869                     /* It is Core Duo.  */
 870                     cpu = "pentium-m";
 871                 }
 872               else if (has_sse2)
 873                 /* It is Pentium M.  */
 874                 cpu = "pentium-m";
 875               else if (has_sse)
 876                 {
 877                   if (vendor == signature_CENTAUR_ebx)
 878                     {
 879                       if (model >= 9)
 880                         /* Eden "Nehemiah" */
 881                         cpu = "nehemiah";
 882                       else
 883                         cpu = "c3-2";
 884                     }
 885                   else
 886                     /* It is Pentium III.  */
 887                     cpu = "pentium3";
 888                 }
 889               else if (has_mmx)
 890                 /* It is Pentium II.  */
 891                 cpu = "pentium2";
 892               else
 893                 /* Default to Pentium Pro.  */
 894                 cpu = "pentiumpro";
 895             }
 896           else
 897             /* For -mtune, we default to -mtune=generic.  */
 898             cpu = "generic";
 899           break;
 900         }
 901       break;
 902     case PROCESSOR_PENTIUM4:
 903       if (has_sse3)
 904         {
 905           if (has_longmode)
 906             cpu = "nocona";
 907           else
 908             cpu = "prescott";
 909         }
 910       else
 911         cpu = "pentium4";
 912       break;
 913     case PROCESSOR_GEODE:
 914       cpu = "geode";
 915       break;
 916     case PROCESSOR_K6:
 917       if (arch && has_3dnow)
 918         cpu = "k6-3";
 919       else
 920         cpu = "k6";
 921       break;
 922     case PROCESSOR_ATHLON:
 923       if (arch && has_sse)
 924         cpu = "athlon-4";
 925       else
 926         cpu = "athlon";
 927       break;
 928     case PROCESSOR_K8:
 929       if (arch)
 930         {
 931           if (vendor == signature_CENTAUR_ebx)
 932             {
 933               if (has_sse4_1)
 934                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 935                 cpu = "nano-3000";
 936               else if (has_ssse3)
 937                 /* Nano 1000 | Nano 2000 */
 938                 cpu = "nano";
 939               else if (has_sse3)
 940                 /* Eden X2 */
 941                 cpu = "eden-x2";
 942               else
 943                 /* Default to k8 */
 944                 cpu = "k8";
 945             }
 946           else if (has_sse3)
 947             cpu = "k8-sse3";
 948           else
 949             cpu = "k8";
 950         }
 951       else
 952         /* For -mtune, we default to -mtune=k8 */
 953         cpu = "k8";
 954       break;
 955     case PROCESSOR_AMDFAM10:
 956       cpu = "amdfam10";
 957       break;
 958     case PROCESSOR_BDVER1:
 959       cpu = "bdver1";
 960       break;
 961     case PROCESSOR_BDVER2:
 962       cpu = "bdver2";
 963       break;
 964     case PROCESSOR_BDVER3:
 965       cpu = "bdver3";
 966       break;
 967     case PROCESSOR_BDVER4:
 968       cpu = "bdver4";
 969       break;
 970     case PROCESSOR_ZNVER1:
 971       cpu = "znver1";
 972       break;
 973     case PROCESSOR_BTVER1:
 974       cpu = "btver1";
 975       break;
 976     case PROCESSOR_BTVER2:
 977       cpu = "btver2";
 978       break;
 979
 980     default:
 981       /* Use something reasonable.  */
 982       if (arch)
 983         {
 984           if (has_ssse3)
 985             cpu = "core2";
 986           else if (has_sse3)
 987             {
 988               if (has_longmode)
 989                 cpu = "nocona";
 990               else
 991                 cpu = "prescott";
 992             }
 993           else if (has_longmode)
 994             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 995                -march=native would be unusable for 64-bit compilations,
 996                as all the CPUs below are 32-bit only.  */
 997             cpu = "x86-64";
 998           else if (has_sse2)
 999             cpu = "pentium4";
1000           else if (has_cmov)
1001             cpu = "pentiumpro";
1002           else if (has_mmx)
1003             cpu = "pentium-mmx";
1004           else if (has_cmpxchg8b)
1005             cpu = "pentium";
1006         }
1007       else
1008         cpu = "generic";
1009     }
1010
1011   if (arch)
1012     {
1013       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
1014       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
1015       const char *sse = has_sse ? " -msse" : " -mno-sse";
1016       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
1017       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
1018       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
1019       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
1020       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
1021       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
1022       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
1023       const char *aes = has_aes ? " -maes" : " -mno-aes";
1024       const char *sha = has_sha ? " -msha" : " -mno-sha";
1025       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
1026       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
1027       const char *abm = has_abm ? " -mabm" : " -mno-abm";
1028       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
1029       const char *fma = has_fma ? " -mfma" : " -mno-fma";
1030       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
1031       const char *xop = has_xop ? " -mxop" : " -mno-xop";
1032       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
1033       const char *sgx = has_sgx ? " -msgx" : " -mno-sgx";
1034       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
1035       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
1036       const char *avx = has_avx ? " -mavx" : " -mno-avx";
1037       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
1038       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
1039       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
1040       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
1041       const char *hle = has_hle ? " -mhle" : " -mno-hle";
1042       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
1043       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
1044       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
1045       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
1046       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
1047       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
1048       const char *adx = has_adx ? " -madx" : " -mno-adx";
1049       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
1050       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
1051       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
1052       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
1053       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
1054       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
1055       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
1056       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
1057       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
1058       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
1059       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
1060       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
1061       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
1062       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
1063       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
1064       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
1065       const char *avx5124vnniw = has_avx5124vnniw ? " -mavx5124vnniw" : " -mno-avx5124vnniw";
1066       const char *avx512vbmi2 = has_avx512vbmi2 ? " -mavx512vbmi2" : " -mno-avx512vbmi2";
1067       const char *avx5124fmaps = has_avx5124fmaps ? " -mavx5124fmaps" : " -mno-avx5124fmaps";
1068       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
1069       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
1070       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
1071       const char *pku = has_pku ? " -mpku" : " -mno-pku";
1072       const char *rdpid = has_rdpid ? " -mrdpid" : " -mno-rdpid";
1073       const char *gfni = has_gfni ? " -mgfni" : " -mno-gfni";
1074       const char *ibt = has_ibt ? " -mibt" : " -mno-ibt";
1075       const char *shstk = has_shstk ? " -mshstk" : " -mno-shstk";
1076       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
1077                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
1078                         popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
1079                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
1080                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
1081                         fxsr, xsave, xsaveopt, avx512f, avx512er,
1082                         avx512cd, avx512pf, prefetchwt1, clflushopt,
1083                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
1084                         avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
1085                         clwb, mwaitx, clzero, pku, rdpid, gfni, ibt, shstk,
1086                         avx512vbmi2, NULL);
1087     }
1088
1089 done:
1090   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
1091 }
1092 #else
1093
1094 /* If we are compiling with GCC where %EBX register is fixed, then the
1095    driver will just ignore -march and -mtune "native" target and will leave
1096    to the newly built compiler to generate code for its default target.  */
1097
1098 const char *host_detect_local_cpu (int, const char **)
1099 {
1100   return NULL;
1101 }
1102 #endif /* __GNUC__ */